[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.h

/*
 * Copyright (c) 2015, Mellanox Technologies, Ltd.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_ESWITCH_H__
#define __MLX5_ESWITCH_H__

#include <linux/if_ether.h>
#include <linux/if_link.h>
#include <net/devlink.h>
#include <linux/mlx5/device.h>
#include <linux/mlx5/eswitch.h>
#include <linux/mlx5/vport.h>
#include <linux/mlx5/fs.h>
#include "lib/mpfs.h"

#ifdef CONFIG_MLX5_ESWITCH

#define MLX5_MAX_UC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))

#define MLX5_MAX_MC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))

#define MLX5_MIN_BW_SHARE 1

#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)

#define mlx5_esw_has_fwd_fdb(dev) \
	MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)

#define FDB_MAX_CHAIN 3
#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
#define FDB_MAX_PRIO 16

struct vport_ingress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	struct mlx5_flow_group *allow_spoofchk_only_grp;
	struct mlx5_flow_group *allow_untagged_only_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allow_rule;
	struct mlx5_flow_handle  *drop_rule;
	struct mlx5_fc           *drop_counter;
};

struct vport_egress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allowed_vlans_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allowed_vlan;
	struct mlx5_flow_handle  *drop_rule;
	struct mlx5_fc           *drop_counter;
};

struct mlx5_vport_drop_stats {
	u64 rx_dropped;
	u64 tx_dropped;
};

struct mlx5_vport_info {
	u8                      mac[ETH_ALEN];
	u16                     vlan;
	u8                      qos;
	u64                     node_guid;
	int                     link_state;
	u32                     min_rate;
	u32                     max_rate;
	bool                    spoofchk;
	bool                    trusted;
};

struct mlx5_vport {
	struct mlx5_core_dev    *dev;
	int                     vport;
	struct hlist_head       uc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct hlist_head       mc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct mlx5_flow_handle *promisc_rule;
	struct mlx5_flow_handle *allmulti_rule;
	struct work_struct      vport_change_handler;

	struct vport_ingress    ingress;
	struct vport_egress     egress;

	struct mlx5_vport_info  info;

	struct {
		bool            enabled;
		u32             esw_tsar_ix;
		u32             bw_share;
	} qos;

	bool                    enabled;
	u16                     enabled_events;
};

enum offloads_fdb_flags {
	ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
};

extern const unsigned int ESW_POOLS[4];

#define PRIO_LEVELS 2
struct mlx5_eswitch_fdb {
	union {
		struct legacy_fdb {
			struct mlx5_flow_table *fdb;
			struct mlx5_flow_group *addr_grp;
			struct mlx5_flow_group *allmulti_grp;
			struct mlx5_flow_group *promisc_grp;
			struct mlx5_flow_table *vepa_fdb;
			struct mlx5_flow_handle *vepa_uplink_rule;
			struct mlx5_flow_handle *vepa_star_rule;
		} legacy;

		struct offloads_fdb {
			struct mlx5_flow_table *slow_fdb;
			struct mlx5_flow_group *send_to_vport_grp;
			struct mlx5_flow_group *peer_miss_grp;
			struct mlx5_flow_handle **peer_miss_rules;
			struct mlx5_flow_group *miss_grp;
			struct mlx5_flow_handle *miss_rule_uni;
			struct mlx5_flow_handle *miss_rule_multi;
			int vlan_push_pop_refcount;

			struct {
				struct mlx5_flow_table *fdb;
				u32 num_rules;
			} fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
			/* Protects fdb_prio table */
			struct mutex fdb_prio_lock;

			int fdb_left[ARRAY_SIZE(ESW_POOLS)];
		} offloads;
	};
	u32 flags;
};

struct mlx5_esw_offload {
	struct mlx5_flow_table *ft_offloads;
	struct mlx5_flow_group *vport_rx_group;
	struct mlx5_eswitch_rep *vport_reps;
	struct list_head peer_flows;
	struct mutex peer_mutex;
	DECLARE_HASHTABLE(encap_tbl, 8);
	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
	u8 inline_mode;
	u64 num_flows;
	u8 encap;
};

/* E-Switch MC FDB table hash node */
struct esw_mc_addr { /* SRIOV only */
	struct l2addr_node     node;
	struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
	u32                    refcnt;
};

struct mlx5_host_work {
	struct work_struct	work;
	struct mlx5_eswitch	*esw;
};

struct mlx5_esw_functions {
	struct mlx5_nb		nb;
	u16			num_vfs;
};

struct mlx5_eswitch {
	struct mlx5_core_dev    *dev;
	struct mlx5_nb          nb;
	struct mlx5_eswitch_fdb fdb_table;
	struct hlist_head       mc_table[MLX5_L2_ADDR_HASH_SIZE];
	struct workqueue_struct *work_queue;
	struct mlx5_vport       *vports;
	int                     total_vports;
	int                     enabled_vports;
	/* Synchronize between vport change events
	 * and async SRIOV admin state changes
	 */
	struct mutex            state_lock;
	struct esw_mc_addr	mc_promisc;

	struct {
		bool            enabled;
		u32             root_tsar_id;
	} qos;

	struct mlx5_esw_offload offloads;
	int                     mode;
	int                     nvports;
	u16                     manager_vport;
	struct mlx5_esw_functions esw_funcs;
};

void esw_offloads_cleanup(struct mlx5_eswitch *esw);
int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
		      int total_nvports);
void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
int esw_offloads_init_reps(struct mlx5_eswitch *esw);
void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
				     struct mlx5_vport *vport);
int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
				 struct mlx5_vport *vport);
void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
				    struct mlx5_vport *vport);
int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
				struct mlx5_vport *vport);
void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
				  struct mlx5_vport *vport);
void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
				   struct mlx5_vport *vport);

/* E-Switch API */
int mlx5_eswitch_init(struct mlx5_core_dev *dev);
void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
			       int vport, u8 mac[ETH_ALEN]);
int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
				 int vport, int link_state);
int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				int vport, u16 vlan, u8 qos);
int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
				    int vport, bool spoofchk);
int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
				 int vport_num, bool setting);
int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
				u32 max_rate, u32 min_rate);
int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
				  int vport, struct ifla_vf_info *ivi);
int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
				 int vport,
				 struct ifla_vf_stats *vf_stats);
void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);

struct mlx5_flow_spec;
struct mlx5_esw_flow_attr;

struct mlx5_flow_handle *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_spec *spec,
				struct mlx5_esw_flow_attr *attr);
struct mlx5_flow_handle *
mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
			  struct mlx5_flow_spec *spec,
			  struct mlx5_esw_flow_attr *attr);
void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_handle *rule,
				struct mlx5_esw_flow_attr *attr);
void
mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
			  struct mlx5_flow_handle *rule,
			  struct mlx5_esw_flow_attr *attr);

bool
mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);

u16
mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);

u32
mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);

struct mlx5_flow_handle *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
				  struct mlx5_flow_destination *dest);

enum {
	SET_VLAN_STRIP	= BIT(0),
	SET_VLAN_INSERT	= BIT(1)
};

enum mlx5_flow_match_level {
	MLX5_MATCH_NONE	= MLX5_INLINE_MODE_NONE,
	MLX5_MATCH_L2	= MLX5_INLINE_MODE_L2,
	MLX5_MATCH_L3	= MLX5_INLINE_MODE_IP,
	MLX5_MATCH_L4	= MLX5_INLINE_MODE_TCP_UDP,
};

/* current maximum for flow based vport multicasting */
#define MLX5_MAX_FLOW_FWD_VPORTS 2

enum {
	MLX5_ESW_DEST_ENCAP         = BIT(0),
	MLX5_ESW_DEST_ENCAP_VALID   = BIT(1),
};

struct mlx5_esw_flow_attr {
	struct mlx5_eswitch_rep *in_rep;
	struct mlx5_core_dev	*in_mdev;
	struct mlx5_core_dev    *counter_dev;

	int split_count;
	int out_count;

	int	action;
	__be16	vlan_proto[MLX5_FS_VLAN_DEPTH];
	u16	vlan_vid[MLX5_FS_VLAN_DEPTH];
	u8	vlan_prio[MLX5_FS_VLAN_DEPTH];
	u8	total_vlan;
	bool	vlan_handled;
	struct {
		u32 flags;
		struct mlx5_eswitch_rep *rep;
		struct mlx5_core_dev *mdev;
		u32 encap_id;
	} dests[MLX5_MAX_FLOW_FWD_VPORTS];
	u32	mod_hdr_id;
	u8	match_level;
	u8	tunnel_match_level;
	struct mlx5_fc *counter;
	u32	chain;
	u16	prio;
	u32	dest_chain;
	struct mlx5e_tc_flow_parse_attr *parse_attr;
};

int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
				  struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
					 struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
					struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);

int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				  int vport, u16 vlan, u8 qos, u8 set_flags);

static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
						       u8 vlan_depth)
{
	bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
		   MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);

	if (vlan_depth == 1)
		return ret;

	return  ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
		MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
}

bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
			 struct mlx5_core_dev *dev1);
bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
			       struct mlx5_core_dev *dev1);

int mlx5_esw_query_functions(struct mlx5_core_dev *dev, u16 *num_vfs);

#define MLX5_DEBUG_ESWITCH_MASK BIT(3)

#define esw_info(__dev, format, ...)			\
	dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)

#define esw_warn(__dev, format, ...)			\
	dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)

#define esw_debug(dev, format, ...)				\
	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)

/* The returned number is valid only when the dev is eswitch manager. */
static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
{
	return mlx5_core_is_ecpf_esw_manager(dev) ?
		MLX5_VPORT_ECPF : MLX5_VPORT_PF;
}

static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
{
	/* Uplink always locate at the last element of the array.*/
	return esw->total_vports - 1;
}

static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
{
	return esw->total_vports - 2;
}

static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
						  u16 vport_num)
{
	if (vport_num == MLX5_VPORT_ECPF) {
		if (!mlx5_ecpf_vport_exists(esw->dev))
			esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
		return mlx5_eswitch_ecpf_idx(esw);
	}

	if (vport_num == MLX5_VPORT_UPLINK)
		return mlx5_eswitch_uplink_idx(esw);

	return vport_num;
}

static inline int mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
						  int index)
{
	if (index == mlx5_eswitch_ecpf_idx(esw) &&
	    mlx5_ecpf_vport_exists(esw->dev))
		return MLX5_VPORT_ECPF;

	if (index == mlx5_eswitch_uplink_idx(esw))
		return MLX5_VPORT_UPLINK;

	return index;
}

/* TODO: This mlx5e_tc function shouldn't be called by eswitch */
void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);

/* The vport getter/iterator are only valid after esw->total_vports
 * and vport->vport are initialized in mlx5_eswitch_init.
 */
#define mlx5_esw_for_all_vports(esw, i, vport)		\
	for ((i) = MLX5_VPORT_PF;			\
	     (vport) = &(esw)->vports[i],		\
	     (i) < (esw)->total_vports; (i)++)

#define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs)	\
	for ((i) = MLX5_VPORT_FIRST_VF;			\
	     (vport) = &(esw)->vports[(i)],		\
	     (i) <= (nvfs); (i)++)

#define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs)	\
	for ((i) = (nvfs);					\
	     (vport) = &(esw)->vports[(i)],			\
	     (i) >= MLX5_VPORT_FIRST_VF; (i)--)

/* The rep getter/iterator are only valid after esw->total_vports
 * and vport->vport are initialized in mlx5_eswitch_init.
 */
#define mlx5_esw_for_all_reps(esw, i, rep)			\
	for ((i) = MLX5_VPORT_PF;				\
	     (rep) = &(esw)->offloads.vport_reps[i],		\
	     (i) < (esw)->total_vports; (i)++)

#define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs)		\
	for ((i) = MLX5_VPORT_FIRST_VF;				\
	     (rep) = &(esw)->offloads.vport_reps[i],		\
	     (i) <= (nvfs); (i)++)

#define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs)	\
	for ((i) = (nvfs);					\
	     (rep) = &(esw)->offloads.vport_reps[i],		\
	     (i) >= MLX5_VPORT_FIRST_VF; (i)--)

#define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs)	\
	for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)

#define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs)	\
	for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)

struct mlx5_vport *__must_check
mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);

#else  /* CONFIG_MLX5_ESWITCH */
/* eswitch API stubs */
static inline int  mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
static inline int  mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }

#define FDB_MAX_CHAIN 1
#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
#define FDB_MAX_PRIO 1

#endif /* CONFIG_MLX5_ESWITCH */

#endif /* __MLX5_ESWITCH_H__ */
Commit	Line	Data
073bb189 SM	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_ESWITCH_H__
	34	#define __MLX5_ESWITCH_H__
	35
77256579 SM	36	#include <linux/if_ether.h>
77256579 SM	37	#include <linux/if_link.h>
feae9087	38	#include <net/devlink.h>
073bb189	39	#include <linux/mlx5/device.h>
57cbd893	40	#include <linux/mlx5/eswitch.h>
a1b3839a	41	#include <linux/mlx5/vport.h>
cc495188	42	#include <linux/mlx5/fs.h>
eeb66cdb	43	#include "lib/mpfs.h"
073bb189	44
e80541ec SM	45	#ifdef CONFIG_MLX5_ESWITCH
e80541ec SM	46
073bb189 SM	47	#define MLX5_MAX_UC_PER_VPORT(dev) \
	48	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
	49
	50	#define MLX5_MAX_MC_PER_VPORT(dev) \
	51	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
	52
c9497c98 MHY	53	#define MLX5_MIN_BW_SHARE 1
	54
	55	#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	56	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
	57
a842dd04 CM	58	#define mlx5_esw_has_fwd_fdb(dev) \
	59	MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
	60
328edb49	61	#define FDB_MAX_CHAIN 3
c92a0b94	62	#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
328edb49 PB	63	#define FDB_MAX_PRIO 16
328edb49 PB	64
5742df0f MHY	65	struct vport_ingress {
	66	struct mlx5_flow_table *acl;
	67	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	68	struct mlx5_flow_group *allow_spoofchk_only_grp;
	69	struct mlx5_flow_group *allow_untagged_only_grp;
	70	struct mlx5_flow_group *drop_grp;
74491de9 MB	71	struct mlx5_flow_handle *allow_rule;
74491de9 MB	72	struct mlx5_flow_handle *drop_rule;
b8a0dbe3	73	struct mlx5_fc *drop_counter;
5742df0f MHY	74	};
	75
	76	struct vport_egress {
	77	struct mlx5_flow_table *acl;
	78	struct mlx5_flow_group *allowed_vlans_grp;
	79	struct mlx5_flow_group *drop_grp;
74491de9 MB	80	struct mlx5_flow_handle *allowed_vlan;
74491de9 MB	81	struct mlx5_flow_handle *drop_rule;
b8a0dbe3 EE	82	struct mlx5_fc *drop_counter;
	83	};
	84
	85	struct mlx5_vport_drop_stats {
	86	u64 rx_dropped;
	87	u64 tx_dropped;
5742df0f MHY	88	};
5742df0f MHY	89
1ab2068a MHY	90	struct mlx5_vport_info {
	91	u8 mac[ETH_ALEN];
	92	u16 vlan;
	93	u8 qos;
	94	u64 node_guid;
	95	int link_state;
c9497c98	96	u32 min_rate;
1bd27b11	97	u32 max_rate;
1ab2068a MHY	98	bool spoofchk;
	99	bool trusted;
	100	};
	101
073bb189 SM	102	struct mlx5_vport {
	103	struct mlx5_core_dev *dev;
	104	int vport;
	105	struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
81848731	106	struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
74491de9 MB	107	struct mlx5_flow_handle *promisc_rule;
74491de9 MB	108	struct mlx5_flow_handle *allmulti_rule;
073bb189 SM	109	struct work_struct vport_change_handler;
073bb189 SM	110
5742df0f MHY	111	struct vport_ingress ingress;
	112	struct vport_egress egress;
	113
1ab2068a MHY	114	struct mlx5_vport_info info;
1ab2068a MHY	115
1bd27b11 MHY	116	struct {
	117	bool enabled;
	118	u32 esw_tsar_ix;
c9497c98	119	u32 bw_share;
1bd27b11 MHY	120	} qos;
1bd27b11 MHY	121
073bb189	122	bool enabled;
81848731	123	u16 enabled_events;
073bb189 SM	124	};
073bb189 SM	125
e52c2802 PB	126	enum offloads_fdb_flags {
	127	ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
	128	};
	129
	130	extern const unsigned int ESW_POOLS[4];
	131
	132	#define PRIO_LEVELS 2
81848731	133	struct mlx5_eswitch_fdb {
6ab36e35 OG	134	union {
6ab36e35 OG	135	struct legacy_fdb {
52fff327	136	struct mlx5_flow_table *fdb;
6ab36e35 OG	137	struct mlx5_flow_group *addr_grp;
	138	struct mlx5_flow_group *allmulti_grp;
	139	struct mlx5_flow_group *promisc_grp;
8da202b2 HN	140	struct mlx5_flow_table *vepa_fdb;
	141	struct mlx5_flow_handle *vepa_uplink_rule;
	142	struct mlx5_flow_handle *vepa_star_rule;
6ab36e35	143	} legacy;
69697b6e OG	144
69697b6e OG	145	struct offloads_fdb {
52fff327	146	struct mlx5_flow_table *slow_fdb;
69697b6e	147	struct mlx5_flow_group *send_to_vport_grp;
ac004b83 RD	148	struct mlx5_flow_group *peer_miss_grp;
ac004b83 RD	149	struct mlx5_flow_handle **peer_miss_rules;
69697b6e	150	struct mlx5_flow_group *miss_grp;
f80be543 MB	151	struct mlx5_flow_handle *miss_rule_uni;
f80be543 MB	152	struct mlx5_flow_handle *miss_rule_multi;
f5f82476	153	int vlan_push_pop_refcount;
e52c2802 PB	154
	155	struct {
	156	struct mlx5_flow_table *fdb;
	157	u32 num_rules;
	158	} fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
	159	/* Protects fdb_prio table */
	160	struct mutex fdb_prio_lock;
	161
	162	int fdb_left[ARRAY_SIZE(ESW_POOLS)];
69697b6e	163	} offloads;
6ab36e35	164	};
e52c2802	165	u32 flags;
6ab36e35 OG	166	};
6ab36e35 OG	167
c116c6ee OG	168	struct mlx5_esw_offload {
c116c6ee OG	169	struct mlx5_flow_table *ft_offloads;
fed9ce22	170	struct mlx5_flow_group *vport_rx_group;
127ea380	171	struct mlx5_eswitch_rep *vport_reps;
04de7dda RD	172	struct list_head peer_flows;
04de7dda RD	173	struct mutex peer_mutex;
a54e20b4	174	DECLARE_HASHTABLE(encap_tbl, 8);
11c9c548	175	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
bffaa916	176	u8 inline_mode;
375f51e2	177	u64 num_flows;
7768d197	178	u8 encap;
c116c6ee OG	179	};
c116c6ee OG	180
0a0ab1d2 EC	181	/* E-Switch MC FDB table hash node */
	182	struct esw_mc_addr { /* SRIOV only */
	183	struct l2addr_node node;
	184	struct mlx5_flow_handle uplink_rule; / Forward to uplink rule */
	185	u32 refcnt;
	186	};
	187
a3888f33 BW	188	struct mlx5_host_work {
	189	struct work_struct work;
	190	struct mlx5_eswitch *esw;
	191	};
	192
cd56f929	193	struct mlx5_esw_functions {
a3888f33 BW	194	struct mlx5_nb nb;
	195	u16 num_vfs;
	196	};
	197
073bb189 SM	198	struct mlx5_eswitch {
073bb189 SM	199	struct mlx5_core_dev *dev;
6933a937	200	struct mlx5_nb nb;
81848731 SM	201	struct mlx5_eswitch_fdb fdb_table;
81848731 SM	202	struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
073bb189 SM	203	struct workqueue_struct *work_queue;
	204	struct mlx5_vport *vports;
	205	int total_vports;
81848731	206	int enabled_vports;
dfcb1ed3 MHY	207	/* Synchronize between vport change events
	208	* and async SRIOV admin state changes
	209	*/
	210	struct mutex state_lock;
0a0ab1d2	211	struct esw_mc_addr mc_promisc;
1bd27b11 MHY	212
	213	struct {
	214	bool enabled;
	215	u32 root_tsar_id;
	216	} qos;
	217
c116c6ee	218	struct mlx5_esw_offload offloads;
6ab36e35	219	int mode;
e52c2802	220	int nvports;
a1b3839a	221	u16 manager_vport;
cd56f929	222	struct mlx5_esw_functions esw_funcs;
073bb189 SM	223	};
073bb189 SM	224
c9b99abc BW	225	void esw_offloads_cleanup(struct mlx5_eswitch *esw);
	226	int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
	227	int total_nvports);
e8d31c4d MB	228	void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
e8d31c4d MB	229	int esw_offloads_init_reps(struct mlx5_eswitch *esw);
18486737 EB	230	void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
	231	struct mlx5_vport *vport);
	232	int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
	233	struct mlx5_vport *vport);
	234	void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
	235	struct mlx5_vport *vport);
	236	int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
	237	struct mlx5_vport *vport);
	238	void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
	239	struct mlx5_vport *vport);
	240	void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
	241	struct mlx5_vport *vport);
766a0e97	242
073bb189 SM	243	/* E-Switch API */
	244	int mlx5_eswitch_init(struct mlx5_core_dev *dev);
	245	void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
6ab36e35	246	int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
81848731	247	void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
77256579 SM	248	int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
	249	int vport, u8 mac[ETH_ALEN]);
	250	int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
	251	int vport, int link_state);
9e7ea352 SM	252	int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
9e7ea352 SM	253	int vport, u16 vlan, u8 qos);
f942380c MHY	254	int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
f942380c MHY	255	int vport, bool spoofchk);
1edc57e2 MHY	256	int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1edc57e2 MHY	257	int vport_num, bool setting);
c9497c98 MHY	258	int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
c9497c98 MHY	259	u32 max_rate, u32 min_rate);
8da202b2 HN	260	int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
8da202b2 HN	261	int mlx5_eswitch_get_vepa(struct mlx5_eswitch esw, u8 setting);
77256579 SM	262	int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
77256579 SM	263	int vport, struct ifla_vf_info *ivi);
3b751a2a SM	264	int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
	265	int vport,
	266	struct ifla_vf_stats *vf_stats);
159fe639	267	void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
073bb189	268
3d80d1a2	269	struct mlx5_flow_spec;
776b12b6	270	struct mlx5_esw_flow_attr;
3d80d1a2	271
74491de9	272	struct mlx5_flow_handle *
3d80d1a2 OG	273	mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
3d80d1a2 OG	274	struct mlx5_flow_spec *spec,
776b12b6	275	struct mlx5_esw_flow_attr *attr);
e4ad91f2 CM	276	struct mlx5_flow_handle *
	277	mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
	278	struct mlx5_flow_spec *spec,
	279	struct mlx5_esw_flow_attr *attr);
d85cdccb OG	280	void
	281	mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
	282	struct mlx5_flow_handle *rule,
	283	struct mlx5_esw_flow_attr *attr);
48265006 OG	284	void
	285	mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
	286	struct mlx5_flow_handle *rule,
	287	struct mlx5_esw_flow_attr *attr);
d85cdccb	288
e52c2802 PB	289	bool
	290	mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
	291
	292	u16
	293	mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
	294
	295	u32
	296	mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
	297
74491de9	298	struct mlx5_flow_handle *
c966f7d5 GT	299	mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
c966f7d5 GT	300	struct mlx5_flow_destination *dest);
fed9ce22	301
e33dfe31 OG	302	enum {
	303	SET_VLAN_STRIP = BIT(0),
	304	SET_VLAN_INSERT = BIT(1)
	305	};
	306
d708f902 OG	307	enum mlx5_flow_match_level {
	308	MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
	309	MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
	310	MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
	311	MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
	312	};
	313
592d3651 CM	314	/* current maximum for flow based vport multicasting */
	315	#define MLX5_MAX_FLOW_FWD_VPORTS 2
	316
f493f155 EB	317	enum {
f493f155 EB	318	MLX5_ESW_DEST_ENCAP = BIT(0),
8c4dc42b	319	MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
f493f155 EB	320	};
f493f155 EB	321
776b12b6 OG	322	struct mlx5_esw_flow_attr {
776b12b6 OG	323	struct mlx5_eswitch_rep *in_rep;
10ff5359	324	struct mlx5_core_dev *in_mdev;
f9392795	325	struct mlx5_core_dev *counter_dev;
776b12b6	326
e85e02ba	327	int split_count;
592d3651 CM	328	int out_count;
592d3651 CM	329
776b12b6	330	int action;
cc495188 JL	331	__be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
	332	u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
	333	u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
	334	u8 total_vlan;
f5f82476	335	bool vlan_handled;
df65a573	336	struct {
f493f155	337	u32 flags;
df65a573 EB	338	struct mlx5_eswitch_rep *rep;
df65a573 EB	339	struct mlx5_core_dev *mdev;
8c4dc42b	340	u32 encap_id;
df65a573	341	} dests[MLX5_MAX_FLOW_FWD_VPORTS];
d7e75a32	342	u32 mod_hdr_id;
38aa51c1	343	u8 match_level;
6363651d	344	u8 tunnel_match_level;
b8aee822	345	struct mlx5_fc *counter;
e52c2802 PB	346	u32 chain;
	347	u16 prio;
	348	u32 dest_chain;
232c0013	349	struct mlx5e_tc_flow_parse_attr *parse_attr;
776b12b6 OG	350	};
776b12b6 OG	351
db7ff19e EB	352	int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
db7ff19e EB	353	struct netlink_ext_ack *extack);
feae9087	354	int mlx5_devlink_eswitch_mode_get(struct devlink devlink, u16 mode);
db7ff19e EB	355	int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
db7ff19e EB	356	struct netlink_ext_ack *extack);
bffaa916 RD	357	int mlx5_devlink_eswitch_inline_mode_get(struct devlink devlink, u8 mode);
bffaa916 RD	358	int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch esw, int nvfs, u8 mode);
db7ff19e EB	359	int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
db7ff19e EB	360	struct netlink_ext_ack *extack);
7768d197	361	int mlx5_devlink_eswitch_encap_mode_get(struct devlink devlink, u8 encap);
a4b97ab4	362	void mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch esw, u8 rep_type);
feae9087	363
f5f82476 OG	364	int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
	365	struct mlx5_esw_flow_attr *attr);
	366	int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
	367	struct mlx5_esw_flow_attr *attr);
	368	int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
	369	int vport, u16 vlan, u8 qos, u8 set_flags);
	370
cc495188 JL	371	static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
cc495188 JL	372	u8 vlan_depth)
6acfbf38	373	{
cc495188 JL	374	bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
	375	MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
	376
	377	if (vlan_depth == 1)
	378	return ret;
	379
	380	return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
	381	MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
6acfbf38 OG	382	}
6acfbf38 OG	383
eff849b2 RL	384	bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
eff849b2 RL	385	struct mlx5_core_dev *dev1);
544fe7c2 RD	386	bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
544fe7c2 RD	387	struct mlx5_core_dev *dev1);
eff849b2	388
cd56f929 VP	389	int mlx5_esw_query_functions(struct mlx5_core_dev dev, u16 num_vfs);
cd56f929 VP	390
69697b6e OG	391	#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
69697b6e OG	392
27b942fb PP	393	#define esw_info(__dev, format, ...) \
27b942fb PP	394	dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
69697b6e	395
27b942fb PP	396	#define esw_warn(__dev, format, ...) \
27b942fb PP	397	dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
69697b6e OG	398
	399	#define esw_debug(dev, format, ...) \
	400	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
a1b3839a BW	401
	402	/* The returned number is valid only when the dev is eswitch manager. */
	403	static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
	404	{
	405	return mlx5_core_is_ecpf_esw_manager(dev) ?
	406	MLX5_VPORT_ECPF : MLX5_VPORT_PF;
	407	}
	408
5ae51620 BW	409	static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
	410	{
	411	/* Uplink always locate at the last element of the array.*/
	412	return esw->total_vports - 1;
	413	}
	414
81cd229c BW	415	static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
	416	{
	417	return esw->total_vports - 2;
	418	}
	419
5ae51620 BW	420	static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
	421	u16 vport_num)
	422	{
81cd229c BW	423	if (vport_num == MLX5_VPORT_ECPF) {
	424	if (!mlx5_ecpf_vport_exists(esw->dev))
	425	esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
	426	return mlx5_eswitch_ecpf_idx(esw);
	427	}
	428
5ae51620 BW	429	if (vport_num == MLX5_VPORT_UPLINK)
	430	return mlx5_eswitch_uplink_idx(esw);
	431
	432	return vport_num;
	433	}
	434
	435	static inline int mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
	436	int index)
	437	{
81cd229c BW	438	if (index == mlx5_eswitch_ecpf_idx(esw) &&
	439	mlx5_ecpf_vport_exists(esw->dev))
	440	return MLX5_VPORT_ECPF;
	441
5ae51620 BW	442	if (index == mlx5_eswitch_uplink_idx(esw))
	443	return MLX5_VPORT_UPLINK;
	444
	445	return index;
	446	}
	447
ee576ec1 SM	448	/* TODO: This mlx5e_tc function shouldn't be called by eswitch */
	449	void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
	450
786ef904 PP	451	/* The vport getter/iterator are only valid after esw->total_vports
	452	* and vport->vport are initialized in mlx5_eswitch_init.
	453	*/
	454	#define mlx5_esw_for_all_vports(esw, i, vport) \
	455	for ((i) = MLX5_VPORT_PF; \
	456	(vport) = &(esw)->vports[i], \
	457	(i) < (esw)->total_vports; (i)++)
	458
	459	#define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
	460	for ((i) = MLX5_VPORT_FIRST_VF; \
	461	(vport) = &(esw)->vports[(i)], \
	462	(i) <= (nvfs); (i)++)
	463
	464	#define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
	465	for ((i) = (nvfs); \
	466	(vport) = &(esw)->vports[(i)], \
	467	(i) >= MLX5_VPORT_FIRST_VF; (i)--)
	468
	469	/* The rep getter/iterator are only valid after esw->total_vports
	470	* and vport->vport are initialized in mlx5_eswitch_init.
	471	*/
	472	#define mlx5_esw_for_all_reps(esw, i, rep) \
	473	for ((i) = MLX5_VPORT_PF; \
	474	(rep) = &(esw)->offloads.vport_reps[i], \
	475	(i) < (esw)->total_vports; (i)++)
	476
	477	#define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
	478	for ((i) = MLX5_VPORT_FIRST_VF; \
	479	(rep) = &(esw)->offloads.vport_reps[i], \
	480	(i) <= (nvfs); (i)++)
	481
	482	#define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
	483	for ((i) = (nvfs); \
	484	(rep) = &(esw)->offloads.vport_reps[i], \
	485	(i) >= MLX5_VPORT_FIRST_VF; (i)--)
	486
	487	#define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
	488	for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
	489
	490	#define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
	491	for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
	492
5d9986a3 BW	493	struct mlx5_vport *__must_check
	494	mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
	495
e80541ec SM	496	#else /* CONFIG_MLX5_ESWITCH */
	497	/* eswitch API stubs */
	498	static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
	499	static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
e80541ec SM	500	static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
e80541ec SM	501	static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
eff849b2	502	static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev dev0, struct mlx5_core_dev dev1) { return true; }
328edb49 PB	503
328edb49 PB	504	#define FDB_MAX_CHAIN 1
c92a0b94	505	#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
328edb49 PB	506	#define FDB_MAX_PRIO 1
328edb49 PB	507
e80541ec SM	508	#endif /* CONFIG_MLX5_ESWITCH */
e80541ec SM	509
073bb189	510	#endif /* __MLX5_ESWITCH_H__ */