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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
525e84be | 38 | #include <linux/atomic.h> |
84ae9c1f | 39 | #include <linux/xarray.h> |
feae9087 | 40 | #include <net/devlink.h> |
073bb189 | 41 | #include <linux/mlx5/device.h> |
57cbd893 | 42 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 43 | #include <linux/mlx5/vport.h> |
cc495188 | 44 | #include <linux/mlx5/fs.h> |
eeb66cdb | 45 | #include "lib/mpfs.h" |
ae430332 | 46 | #include "lib/fs_chains.h" |
d7f33a45 | 47 | #include "sf/sf.h" |
4c3844d9 | 48 | #include "en/tc_ct.h" |
0027d70c | 49 | #include "en/tc/sample.h" |
073bb189 | 50 | |
a91d98a0 CM |
51 | enum mlx5_mapped_obj_type { |
52 | MLX5_MAPPED_OBJ_CHAIN, | |
be9dc004 | 53 | MLX5_MAPPED_OBJ_SAMPLE, |
3651168c | 54 | MLX5_MAPPED_OBJ_INT_PORT_METADATA, |
a91d98a0 CM |
55 | }; |
56 | ||
57 | struct mlx5_mapped_obj { | |
58 | enum mlx5_mapped_obj_type type; | |
59 | union { | |
60 | u32 chain; | |
be9dc004 CM |
61 | struct { |
62 | u32 group_id; | |
63 | u32 rate; | |
64 | u32 trunc_size; | |
ee950e5d | 65 | u32 tunnel_id; |
be9dc004 | 66 | } sample; |
3651168c | 67 | u32 int_port_metadata; |
a91d98a0 CM |
68 | }; |
69 | }; | |
70 | ||
e80541ec SM |
71 | #ifdef CONFIG_MLX5_ESWITCH |
72 | ||
87dac697 JL |
73 | #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 |
74 | ||
073bb189 SM |
75 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
76 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
77 | ||
78 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
79 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
80 | ||
a842dd04 CM |
81 | #define mlx5_esw_has_fwd_fdb(dev) \ |
82 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
83 | ||
ae430332 AL |
84 | #define esw_chains(esw) \ |
85 | ((esw)->fdb_table.offloads.esw_chains_priv) | |
86 | ||
2198b932 RD |
87 | enum { |
88 | MAPPING_TYPE_CHAIN, | |
89 | MAPPING_TYPE_TUNNEL, | |
90 | MAPPING_TYPE_TUNNEL_ENC_OPTS, | |
91 | MAPPING_TYPE_LABELS, | |
92 | MAPPING_TYPE_ZONE, | |
3651168c | 93 | MAPPING_TYPE_INT_PORT, |
2198b932 RD |
94 | }; |
95 | ||
5742df0f MHY |
96 | struct vport_ingress { |
97 | struct mlx5_flow_table *acl; | |
10652f39 | 98 | struct mlx5_flow_handle *allow_rule; |
853b5352 | 99 | struct { |
10652f39 PP |
100 | struct mlx5_flow_group *allow_spoofchk_only_grp; |
101 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
102 | struct mlx5_flow_group *allow_untagged_only_grp; | |
103 | struct mlx5_flow_group *drop_grp; | |
853b5352 PP |
104 | struct mlx5_flow_handle *drop_rule; |
105 | struct mlx5_fc *drop_counter; | |
106 | } legacy; | |
d68316b5 | 107 | struct { |
b7826076 PP |
108 | /* Optional group to add an FTE to do internal priority |
109 | * tagging on ingress packets. | |
110 | */ | |
111 | struct mlx5_flow_group *metadata_prio_tag_grp; | |
112 | /* Group to add default match-all FTE entry to tag ingress | |
113 | * packet with metadata. | |
114 | */ | |
115 | struct mlx5_flow_group *metadata_allmatch_grp; | |
d68316b5 PP |
116 | struct mlx5_modify_hdr *modify_metadata; |
117 | struct mlx5_flow_handle *modify_metadata_rule; | |
118 | } offloads; | |
5742df0f MHY |
119 | }; |
120 | ||
121 | struct vport_egress { | |
122 | struct mlx5_flow_table *acl; | |
74491de9 | 123 | struct mlx5_flow_handle *allowed_vlan; |
ea651a86 | 124 | struct mlx5_flow_group *vlan_grp; |
bf773dc0 VP |
125 | union { |
126 | struct { | |
127 | struct mlx5_flow_group *drop_grp; | |
128 | struct mlx5_flow_handle *drop_rule; | |
129 | struct mlx5_fc *drop_counter; | |
130 | } legacy; | |
131 | struct { | |
132 | struct mlx5_flow_group *fwd_grp; | |
133 | struct mlx5_flow_handle *fwd_rule; | |
db202995 MB |
134 | struct mlx5_flow_handle *bounce_rule; |
135 | struct mlx5_flow_group *bounce_grp; | |
bf773dc0 VP |
136 | } offloads; |
137 | }; | |
b8a0dbe3 EE |
138 | }; |
139 | ||
140 | struct mlx5_vport_drop_stats { | |
141 | u64 rx_dropped; | |
142 | u64 tx_dropped; | |
5742df0f MHY |
143 | }; |
144 | ||
1ab2068a MHY |
145 | struct mlx5_vport_info { |
146 | u8 mac[ETH_ALEN]; | |
147 | u16 vlan; | |
1ab2068a MHY |
148 | u64 node_guid; |
149 | int link_state; | |
cadb129f PP |
150 | u8 qos; |
151 | u8 spoofchk: 1; | |
152 | u8 trusted: 1; | |
1ab2068a MHY |
153 | }; |
154 | ||
5019833d PP |
155 | /* Vport context events */ |
156 | enum mlx5_eswitch_vport_event { | |
157 | MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), | |
158 | MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), | |
159 | MLX5_VPORT_PROMISC_CHANGE = BIT(3), | |
160 | }; | |
161 | ||
073bb189 SM |
162 | struct mlx5_vport { |
163 | struct mlx5_core_dev *dev; | |
073bb189 | 164 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; |
81848731 | 165 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
166 | struct mlx5_flow_handle *promisc_rule; |
167 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
168 | struct work_struct vport_change_handler; |
169 | ||
5742df0f MHY |
170 | struct vport_ingress ingress; |
171 | struct vport_egress egress; | |
133dcfc5 VP |
172 | u32 default_metadata; |
173 | u32 metadata; | |
5742df0f | 174 | |
1ab2068a MHY |
175 | struct mlx5_vport_info info; |
176 | ||
1bd27b11 MHY |
177 | struct { |
178 | bool enabled; | |
179 | u32 esw_tsar_ix; | |
c9497c98 | 180 | u32 bw_share; |
e591605f PP |
181 | u32 min_rate; |
182 | u32 max_rate; | |
0fe132ea | 183 | struct mlx5_esw_rate_group *group; |
1bd27b11 MHY |
184 | } qos; |
185 | ||
6308a5f0 | 186 | u16 vport; |
073bb189 | 187 | bool enabled; |
5019833d | 188 | enum mlx5_eswitch_vport_event enabled_events; |
47dd7e60 | 189 | int index; |
c7eddc60 | 190 | struct devlink_port *dl_port; |
073bb189 SM |
191 | }; |
192 | ||
34ca6535 VB |
193 | struct mlx5_esw_indir_table; |
194 | ||
81848731 | 195 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
196 | union { |
197 | struct legacy_fdb { | |
52fff327 | 198 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
199 | struct mlx5_flow_group *addr_grp; |
200 | struct mlx5_flow_group *allmulti_grp; | |
201 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
202 | struct mlx5_flow_table *vepa_fdb; |
203 | struct mlx5_flow_handle *vepa_uplink_rule; | |
204 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 205 | } legacy; |
69697b6e OG |
206 | |
207 | struct offloads_fdb { | |
8463daf1 | 208 | struct mlx5_flow_namespace *ns; |
ec3be887 | 209 | struct mlx5_flow_table *tc_miss_table; |
52fff327 | 210 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 211 | struct mlx5_flow_group *send_to_vport_grp; |
8e404fef | 212 | struct mlx5_flow_group *send_to_vport_meta_grp; |
ac004b83 RD |
213 | struct mlx5_flow_group *peer_miss_grp; |
214 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 215 | struct mlx5_flow_group *miss_grp; |
8e404fef | 216 | struct mlx5_flow_handle **send_to_vport_meta_rules; |
f80be543 MB |
217 | struct mlx5_flow_handle *miss_rule_uni; |
218 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 219 | int vlan_push_pop_refcount; |
e52c2802 | 220 | |
ae430332 | 221 | struct mlx5_fs_chains *esw_chains_priv; |
96e32687 EC |
222 | struct { |
223 | DECLARE_HASHTABLE(table, 8); | |
224 | /* Protects vports.table */ | |
225 | struct mutex lock; | |
226 | } vports; | |
227 | ||
34ca6535 VB |
228 | struct mlx5_esw_indir_table *indir; |
229 | ||
69697b6e | 230 | } offloads; |
6ab36e35 | 231 | }; |
e52c2802 | 232 | u32 flags; |
6ab36e35 OG |
233 | }; |
234 | ||
c116c6ee | 235 | struct mlx5_esw_offload { |
11b717d6 PB |
236 | struct mlx5_flow_table *ft_offloads_restore; |
237 | struct mlx5_flow_group *restore_group; | |
6724e66b | 238 | struct mlx5_modify_hdr *restore_copy_hdr_id; |
c9355682 | 239 | struct mapping_ctx *reg_c0_obj_pool; |
11b717d6 | 240 | |
c116c6ee | 241 | struct mlx5_flow_table *ft_offloads; |
fed9ce22 | 242 | struct mlx5_flow_group *vport_rx_group; |
47dd7e60 | 243 | struct xarray vport_reps; |
04de7dda RD |
244 | struct list_head peer_flows; |
245 | struct mutex peer_mutex; | |
61086f39 | 246 | struct mutex encap_tbl_lock; /* protects encap_tbl */ |
a54e20b4 | 247 | DECLARE_HASHTABLE(encap_tbl, 8); |
14e6b038 EC |
248 | struct mutex decap_tbl_lock; /* protects decap_tbl */ |
249 | DECLARE_HASHTABLE(decap_tbl, 8); | |
dd58edc3 | 250 | struct mod_hdr_tbl mod_hdr; |
10caabda OS |
251 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
252 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
84ae9c1f | 253 | struct xarray vhca_map; |
8693115a | 254 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 255 | u8 inline_mode; |
525e84be | 256 | atomic64_t num_flows; |
98fdbea5 | 257 | enum devlink_eswitch_encap_mode encap; |
133dcfc5 | 258 | struct ida vport_metadata_ida; |
a53cf949 | 259 | unsigned int host_number; /* ECPF supports one external host */ |
c116c6ee OG |
260 | }; |
261 | ||
0a0ab1d2 EC |
262 | /* E-Switch MC FDB table hash node */ |
263 | struct esw_mc_addr { /* SRIOV only */ | |
264 | struct l2addr_node node; | |
265 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
266 | u32 refcnt; | |
267 | }; | |
268 | ||
a3888f33 BW |
269 | struct mlx5_host_work { |
270 | struct work_struct work; | |
271 | struct mlx5_eswitch *esw; | |
272 | }; | |
273 | ||
cd56f929 | 274 | struct mlx5_esw_functions { |
a3888f33 BW |
275 | struct mlx5_nb nb; |
276 | u16 num_vfs; | |
277 | }; | |
278 | ||
7445cfb1 JL |
279 | enum { |
280 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
5b7cb745 | 281 | MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), |
7445cfb1 JL |
282 | }; |
283 | ||
19e9bfa0 VB |
284 | struct mlx5_esw_bridge_offloads; |
285 | ||
073bb189 SM |
286 | struct mlx5_eswitch { |
287 | struct mlx5_core_dev *dev; | |
6933a937 | 288 | struct mlx5_nb nb; |
81848731 | 289 | struct mlx5_eswitch_fdb fdb_table; |
99ecd646 | 290 | /* legacy data structures */ |
81848731 | 291 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; |
131ce701 PP |
292 | struct esw_mc_addr mc_promisc; |
293 | /* end of legacy */ | |
073bb189 | 294 | struct workqueue_struct *work_queue; |
47dd7e60 | 295 | struct xarray vports; |
7445cfb1 | 296 | u32 flags; |
073bb189 | 297 | int total_vports; |
81848731 | 298 | int enabled_vports; |
dfcb1ed3 MHY |
299 | /* Synchronize between vport change events |
300 | * and async SRIOV admin state changes | |
301 | */ | |
302 | struct mutex state_lock; | |
1bd27b11 | 303 | |
8e0aa4bc PP |
304 | /* Protects eswitch mode change that occurs via one or more |
305 | * user commands, i.e. sriov state change, devlink commands. | |
306 | */ | |
c55479d0 | 307 | struct rw_semaphore mode_lock; |
7dc84de9 | 308 | atomic64_t user_count; |
8e0aa4bc | 309 | |
1bd27b11 MHY |
310 | struct { |
311 | bool enabled; | |
2d116e3e | 312 | u32 root_tsar_ix; |
1ae258f8 | 313 | struct mlx5_esw_rate_group *group0; |
f47e04eb | 314 | struct list_head groups; /* Protected by esw->state_lock */ |
1bd27b11 MHY |
315 | } qos; |
316 | ||
19e9bfa0 | 317 | struct mlx5_esw_bridge_offloads *br_offloads; |
c116c6ee | 318 | struct mlx5_esw_offload offloads; |
6ab36e35 | 319 | int mode; |
a1b3839a | 320 | u16 manager_vport; |
411ec9e0 | 321 | u16 first_host_vport; |
cd56f929 | 322 | struct mlx5_esw_functions esw_funcs; |
87dac697 JL |
323 | struct { |
324 | u32 large_group_num; | |
325 | } params; | |
8f010541 | 326 | struct blocking_notifier_head n_head; |
cac1eb2c | 327 | struct lock_class_key mode_lock_key; |
073bb189 SM |
328 | }; |
329 | ||
5896b972 PP |
330 | void esw_offloads_disable(struct mlx5_eswitch *esw); |
331 | int esw_offloads_enable(struct mlx5_eswitch *esw); | |
e8d31c4d MB |
332 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
333 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
ea651a86 | 334 | |
7bf481d7 PP |
335 | bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw); |
336 | int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable); | |
133dcfc5 VP |
337 | u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw); |
338 | void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata); | |
339 | ||
2d116e3e | 340 | int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 rate_mbps); |
766a0e97 | 341 | |
3651168c AL |
342 | bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw); |
343 | int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable); | |
344 | ||
073bb189 SM |
345 | /* E-Switch API */ |
346 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
347 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
ebf77bb8 PP |
348 | |
349 | #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) | |
8e0aa4bc PP |
350 | int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int mode, int num_vfs); |
351 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); | |
352 | void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw, bool clear_vf); | |
556b9d16 | 353 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf); |
77256579 | 354 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
fa997825 | 355 | u16 vport, const u8 *mac); |
77256579 | 356 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 357 | u16 vport, int link_state); |
9e7ea352 | 358 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 359 | u16 vport, u16 vlan, u8 qos); |
f942380c | 360 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 361 | u16 vport, bool spoofchk); |
1edc57e2 | 362 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
363 | u16 vport_num, bool setting); |
364 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 365 | u32 max_rate, u32 min_rate); |
0fe132ea DL |
366 | int mlx5_esw_qos_vport_update_group(struct mlx5_eswitch *esw, |
367 | struct mlx5_vport *vport, | |
368 | struct mlx5_esw_rate_group *group, | |
369 | struct netlink_ext_ack *extack); | |
8da202b2 HN |
370 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
371 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 372 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 373 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 374 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 375 | u16 vport, |
3b751a2a | 376 | struct ifla_vf_stats *vf_stats); |
159fe639 | 377 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 378 | |
238302fa | 379 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, |
e08a6832 | 380 | bool other_vport, void *in); |
57843868 | 381 | |
3d80d1a2 | 382 | struct mlx5_flow_spec; |
776b12b6 | 383 | struct mlx5_esw_flow_attr; |
10caabda OS |
384 | struct mlx5_termtbl_handle; |
385 | ||
386 | bool | |
387 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
c620b772 | 388 | struct mlx5_flow_attr *attr, |
10caabda OS |
389 | struct mlx5_flow_act *flow_act, |
390 | struct mlx5_flow_spec *spec); | |
391 | ||
392 | struct mlx5_flow_handle * | |
393 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
394 | struct mlx5_flow_table *ft, | |
395 | struct mlx5_flow_spec *spec, | |
396 | struct mlx5_esw_flow_attr *attr, | |
397 | struct mlx5_flow_act *flow_act, | |
398 | struct mlx5_flow_destination *dest, | |
399 | int num_dest); | |
400 | ||
401 | void | |
402 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
403 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 404 | |
f94d6389 CM |
405 | void |
406 | mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec); | |
407 | ||
74491de9 | 408 | struct mlx5_flow_handle * |
3d80d1a2 OG |
409 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
410 | struct mlx5_flow_spec *spec, | |
c620b772 | 411 | struct mlx5_flow_attr *attr); |
e4ad91f2 CM |
412 | struct mlx5_flow_handle * |
413 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
414 | struct mlx5_flow_spec *spec, | |
c620b772 | 415 | struct mlx5_flow_attr *attr); |
d85cdccb OG |
416 | void |
417 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
418 | struct mlx5_flow_handle *rule, | |
c620b772 | 419 | struct mlx5_flow_attr *attr); |
48265006 OG |
420 | void |
421 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
422 | struct mlx5_flow_handle *rule, | |
c620b772 | 423 | struct mlx5_flow_attr *attr); |
d85cdccb | 424 | |
74491de9 | 425 | struct mlx5_flow_handle * |
02f3afd9 | 426 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 427 | struct mlx5_flow_destination *dest); |
fed9ce22 | 428 | |
e33dfe31 OG |
429 | enum { |
430 | SET_VLAN_STRIP = BIT(0), | |
431 | SET_VLAN_INSERT = BIT(1) | |
432 | }; | |
433 | ||
d708f902 OG |
434 | enum mlx5_flow_match_level { |
435 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
436 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
437 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
438 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
439 | }; | |
440 | ||
592d3651 CM |
441 | /* current maximum for flow based vport multicasting */ |
442 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
443 | ||
f493f155 EB |
444 | enum { |
445 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 446 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
10742efc | 447 | MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2), |
f493f155 EB |
448 | }; |
449 | ||
39ac237c PB |
450 | enum { |
451 | MLX5_ESW_ATTR_FLAG_VLAN_HANDLED = BIT(0), | |
452 | MLX5_ESW_ATTR_FLAG_SLOW_PATH = BIT(1), | |
6fb0701a | 453 | MLX5_ESW_ATTR_FLAG_NO_IN_PORT = BIT(2), |
10742efc | 454 | MLX5_ESW_ATTR_FLAG_SRC_REWRITE = BIT(3), |
f94d6389 | 455 | MLX5_ESW_ATTR_FLAG_SAMPLE = BIT(4), |
d557fbbd | 456 | MLX5_ESW_ATTR_FLAG_ACCEPT = BIT(5), |
39ac237c PB |
457 | }; |
458 | ||
d557fbbd VB |
459 | /* Returns true if any of the flags that require skipping further TC/NF processing are set. */ |
460 | static inline bool | |
461 | mlx5_esw_attr_flags_skip(u32 attr_flags) | |
462 | { | |
463 | return attr_flags & (MLX5_ESW_ATTR_FLAG_SLOW_PATH | MLX5_ESW_ATTR_FLAG_ACCEPT); | |
464 | } | |
465 | ||
776b12b6 OG |
466 | struct mlx5_esw_flow_attr { |
467 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 468 | struct mlx5_core_dev *in_mdev; |
f9392795 | 469 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 470 | |
e85e02ba | 471 | int split_count; |
592d3651 CM |
472 | int out_count; |
473 | ||
cc495188 JL |
474 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
475 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
476 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
477 | u8 total_vlan; | |
df65a573 | 478 | struct { |
f493f155 | 479 | u32 flags; |
df65a573 | 480 | struct mlx5_eswitch_rep *rep; |
2b688ea5 | 481 | struct mlx5_pkt_reformat *pkt_reformat; |
df65a573 | 482 | struct mlx5_core_dev *mdev; |
10caabda | 483 | struct mlx5_termtbl_handle *termtbl; |
8914add2 | 484 | int src_port_rewrite_act_id; |
df65a573 | 485 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
34ca6535 | 486 | struct mlx5_rx_tun_attr *rx_tun_attr; |
14e6b038 | 487 | struct mlx5_pkt_reformat *decap_pkt_reformat; |
776b12b6 OG |
488 | }; |
489 | ||
db7ff19e EB |
490 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
491 | struct netlink_ext_ack *extack); | |
feae9087 | 492 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
493 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
494 | struct netlink_ext_ack *extack); | |
bffaa916 | 495 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
98fdbea5 LR |
496 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
497 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 498 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
499 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
500 | enum devlink_eswitch_encap_mode *encap); | |
82564f6c | 501 | int mlx5_devlink_port_function_hw_addr_get(struct devlink_port *port, |
f099fde1 PP |
502 | u8 *hw_addr, int *hw_addr_len, |
503 | struct netlink_ext_ack *extack); | |
82564f6c | 504 | int mlx5_devlink_port_function_hw_addr_set(struct devlink_port *port, |
330077d1 PP |
505 | const u8 *hw_addr, int hw_addr_len, |
506 | struct netlink_ext_ack *extack); | |
f099fde1 | 507 | |
a4b97ab4 | 508 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 509 | |
f5f82476 | 510 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
c620b772 | 511 | struct mlx5_flow_attr *attr); |
f5f82476 | 512 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, |
c620b772 | 513 | struct mlx5_flow_attr *attr); |
f5f82476 | 514 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 515 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 516 | |
b5f814cc EC |
517 | static inline bool mlx5_esw_qos_enabled(struct mlx5_eswitch *esw) |
518 | { | |
519 | return esw->qos.enabled; | |
520 | } | |
521 | ||
cc495188 JL |
522 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
523 | u8 vlan_depth) | |
6acfbf38 | 524 | { |
cc495188 JL |
525 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
526 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
527 | ||
528 | if (vlan_depth == 1) | |
529 | return ret; | |
530 | ||
531 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
532 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
533 | } |
534 | ||
eff849b2 RL |
535 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
536 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
537 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
538 | struct mlx5_core_dev *dev1); | |
eff849b2 | 539 | |
dd28087c | 540 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 541 | |
69697b6e OG |
542 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
543 | ||
27b942fb PP |
544 | #define esw_info(__dev, format, ...) \ |
545 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 546 | |
27b942fb PP |
547 | #define esw_warn(__dev, format, ...) \ |
548 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
549 | |
550 | #define esw_debug(dev, format, ...) \ | |
551 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a | 552 | |
b16f2bb6 PP |
553 | static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw) |
554 | { | |
555 | return esw && MLX5_ESWITCH_MANAGER(esw->dev); | |
556 | } | |
557 | ||
a1b3839a BW |
558 | /* The returned number is valid only when the dev is eswitch manager. */ |
559 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
560 | { | |
561 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
562 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
563 | } | |
564 | ||
ea2300e0 PP |
565 | static inline bool |
566 | mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) | |
567 | { | |
568 | return esw->manager_vport == vport_num; | |
569 | } | |
570 | ||
411ec9e0 BW |
571 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
572 | { | |
573 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
574 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
575 | } | |
576 | ||
3d5f41ca | 577 | static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev) |
6706a3b9 | 578 | { |
3d5f41ca | 579 | return mlx5_core_is_ecpf_esw_manager(dev); |
6706a3b9 VP |
580 | } |
581 | ||
443bf36e PP |
582 | static inline unsigned int |
583 | mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, | |
584 | u16 vport_num) | |
585 | { | |
586 | return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num; | |
587 | } | |
588 | ||
f099fde1 PP |
589 | static inline u16 |
590 | mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index) | |
591 | { | |
592 | return dl_port_index & 0xffff; | |
593 | } | |
594 | ||
ee576ec1 SM |
595 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
596 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
597 | ||
47dd7e60 PP |
598 | /* Each mark identifies eswitch vport type. |
599 | * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using | |
600 | * a single mark. | |
601 | * MLX5_ESW_VPT_VF identifies a SRIOV VF vport. | |
602 | * MLX5_ESW_VPT_SF identifies SF vport. | |
786ef904 | 603 | */ |
47dd7e60 PP |
604 | #define MLX5_ESW_VPT_HOST_FN XA_MARK_0 |
605 | #define MLX5_ESW_VPT_VF XA_MARK_1 | |
606 | #define MLX5_ESW_VPT_SF XA_MARK_2 | |
607 | ||
608 | /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init. | |
609 | * Borrowed the idea from xa_for_each_marked() but with support for desired last element. | |
786ef904 | 610 | */ |
47dd7e60 PP |
611 | |
612 | #define mlx5_esw_for_each_vport(esw, index, vport) \ | |
613 | xa_for_each(&((esw)->vports), index, vport) | |
614 | ||
615 | #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \ | |
616 | for (index = 0, entry = xa_find(xa, &index, last, filter); \ | |
617 | entry; entry = xa_find_after(xa, &index, last, filter)) | |
618 | ||
619 | #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \ | |
620 | mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter) | |
621 | ||
622 | #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \ | |
623 | mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF) | |
624 | ||
625 | #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \ | |
626 | mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN) | |
d7f33a45 | 627 | |
bd939753 | 628 | struct mlx5_eswitch *mlx5_devlink_eswitch_get(struct devlink *devlink); |
5d9986a3 BW |
629 | struct mlx5_vport *__must_check |
630 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
631 | ||
47dd7e60 PP |
632 | bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); |
633 | bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
91d6291c | 634 | |
16fff98a | 635 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 636 | |
925a6acc | 637 | int |
5019833d PP |
638 | mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, |
639 | enum mlx5_eswitch_vport_event enabled_events); | |
640 | void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); | |
641 | ||
d970812b PP |
642 | int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, u16 vport_num, |
643 | enum mlx5_eswitch_vport_event enabled_events); | |
644 | void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, u16 vport_num); | |
645 | ||
748da30b VP |
646 | int |
647 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, | |
648 | struct mlx5_vport *vport); | |
649 | void | |
650 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, | |
651 | struct mlx5_vport *vport); | |
652 | ||
c796bb7c CM |
653 | struct esw_vport_tbl_namespace { |
654 | int max_fte; | |
655 | int max_num_groups; | |
656 | u32 flags; | |
657 | }; | |
658 | ||
4c7f4028 | 659 | struct mlx5_vport_tbl_attr { |
740452e0 | 660 | u32 chain; |
4c7f4028 CM |
661 | u16 prio; |
662 | u16 vport; | |
c796bb7c | 663 | const struct esw_vport_tbl_namespace *vport_ns; |
4c7f4028 CM |
664 | }; |
665 | ||
666 | struct mlx5_flow_table * | |
0a9e2307 | 667 | mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); |
4c7f4028 | 668 | void |
0a9e2307 | 669 | mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); |
96e32687 | 670 | |
11b717d6 PB |
671 | struct mlx5_flow_handle * |
672 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); | |
11b717d6 | 673 | |
c2d7712c BW |
674 | int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num); |
675 | void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num); | |
676 | ||
d970812b PP |
677 | int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num); |
678 | void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num); | |
679 | ||
23bb50cf BW |
680 | int mlx5_eswitch_load_vport(struct mlx5_eswitch *esw, u16 vport_num, |
681 | enum mlx5_eswitch_vport_event enabled_events); | |
682 | void mlx5_eswitch_unload_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
683 | ||
684 | int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, | |
685 | enum mlx5_eswitch_vport_event enabled_events); | |
686 | void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); | |
687 | ||
c7eddc60 PP |
688 | int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, u16 vport_num); |
689 | void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_eswitch *esw, u16 vport_num); | |
690 | struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num); | |
d970812b PP |
691 | |
692 | int mlx5_esw_devlink_sf_port_register(struct mlx5_eswitch *esw, struct devlink_port *dl_port, | |
f1b9acd3 | 693 | u16 vport_num, u32 controller, u32 sfnum); |
d970812b PP |
694 | void mlx5_esw_devlink_sf_port_unregister(struct mlx5_eswitch *esw, u16 vport_num); |
695 | ||
696 | int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port, | |
f1b9acd3 | 697 | u16 vport_num, u32 controller, u32 sfnum); |
d970812b | 698 | void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num); |
87bd418e | 699 | int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id); |
d970812b | 700 | |
84ae9c1f VB |
701 | int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num); |
702 | void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num); | |
703 | int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num); | |
704 | ||
8f010541 PP |
705 | /** |
706 | * mlx5_esw_event_info - Indicates eswitch mode changed/changing. | |
707 | * | |
708 | * @new_mode: New mode of eswitch. | |
709 | */ | |
710 | struct mlx5_esw_event_info { | |
711 | u16 new_mode; | |
712 | }; | |
713 | ||
714 | int mlx5_esw_event_notifier_register(struct mlx5_eswitch *esw, struct notifier_block *n); | |
715 | void mlx5_esw_event_notifier_unregister(struct mlx5_eswitch *esw, struct notifier_block *n); | |
7dc84de9 RD |
716 | |
717 | bool mlx5_esw_hold(struct mlx5_core_dev *dev); | |
718 | void mlx5_esw_release(struct mlx5_core_dev *dev); | |
719 | void mlx5_esw_get(struct mlx5_core_dev *dev); | |
720 | void mlx5_esw_put(struct mlx5_core_dev *dev); | |
721 | int mlx5_esw_try_lock(struct mlx5_eswitch *esw); | |
722 | void mlx5_esw_unlock(struct mlx5_eswitch *esw); | |
cac1eb2c | 723 | void mlx5_esw_lock(struct mlx5_eswitch *esw); |
7dc84de9 | 724 | |
b55b3538 PP |
725 | void esw_vport_change_handle_locked(struct mlx5_vport *vport); |
726 | ||
f1b9acd3 PP |
727 | bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller); |
728 | ||
db202995 MB |
729 | int mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw, |
730 | struct mlx5_eswitch *slave_esw); | |
731 | void mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw, | |
732 | struct mlx5_eswitch *slave_esw); | |
733 | int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw); | |
734 | ||
e80541ec SM |
735 | #else /* CONFIG_MLX5_ESWITCH */ |
736 | /* eswitch API stubs */ | |
737 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
738 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
8e0aa4bc | 739 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } |
556b9d16 | 740 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf) {} |
eff849b2 | 741 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 742 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
7d0314b1 RD |
743 | static inline |
744 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; } | |
dd28087c | 745 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 746 | { |
dd28087c | 747 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 748 | } |
328edb49 | 749 | |
cac1eb2c MB |
750 | static inline void mlx5_esw_unlock(struct mlx5_eswitch *esw) { return; } |
751 | static inline void mlx5_esw_lock(struct mlx5_eswitch *esw) { return; } | |
752 | ||
9d3faa51 | 753 | static inline struct mlx5_flow_handle * |
11b717d6 PB |
754 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) |
755 | { | |
756 | return ERR_PTR(-EOPNOTSUPP); | |
757 | } | |
5a65d85d RD |
758 | |
759 | static inline unsigned int | |
760 | mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, | |
761 | u16 vport_num) | |
762 | { | |
763 | return vport_num; | |
764 | } | |
db202995 MB |
765 | |
766 | static inline int | |
767 | mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw, | |
768 | struct mlx5_eswitch *slave_esw) | |
769 | { | |
770 | return 0; | |
771 | } | |
772 | ||
773 | static inline void | |
774 | mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw, | |
775 | struct mlx5_eswitch *slave_esw) {} | |
776 | ||
777 | static inline int | |
778 | mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw) | |
779 | { | |
780 | return 0; | |
781 | } | |
e80541ec SM |
782 | #endif /* CONFIG_MLX5_ESWITCH */ |
783 | ||
073bb189 | 784 | #endif /* __MLX5_ESWITCH_H__ */ |