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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
525e84be | 38 | #include <linux/atomic.h> |
feae9087 | 39 | #include <net/devlink.h> |
073bb189 | 40 | #include <linux/mlx5/device.h> |
57cbd893 | 41 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 42 | #include <linux/mlx5/vport.h> |
cc495188 | 43 | #include <linux/mlx5/fs.h> |
eeb66cdb | 44 | #include "lib/mpfs.h" |
073bb189 | 45 | |
e80541ec SM |
46 | #ifdef CONFIG_MLX5_ESWITCH |
47 | ||
073bb189 SM |
48 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
49 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
50 | ||
51 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
52 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
53 | ||
c9497c98 MHY |
54 | #define MLX5_MIN_BW_SHARE 1 |
55 | ||
56 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
57 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
58 | ||
a842dd04 CM |
59 | #define mlx5_esw_has_fwd_fdb(dev) \ |
60 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
61 | ||
328edb49 | 62 | #define FDB_MAX_CHAIN 3 |
c92a0b94 | 63 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
64 | #define FDB_MAX_PRIO 16 |
65 | ||
5742df0f MHY |
66 | struct vport_ingress { |
67 | struct mlx5_flow_table *acl; | |
68 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
69 | struct mlx5_flow_group *allow_spoofchk_only_grp; | |
70 | struct mlx5_flow_group *allow_untagged_only_grp; | |
71 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
72 | struct mlx5_flow_handle *allow_rule; |
73 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 | 74 | struct mlx5_fc *drop_counter; |
d68316b5 PP |
75 | struct { |
76 | struct mlx5_modify_hdr *modify_metadata; | |
77 | struct mlx5_flow_handle *modify_metadata_rule; | |
78 | } offloads; | |
5742df0f MHY |
79 | }; |
80 | ||
81 | struct vport_egress { | |
82 | struct mlx5_flow_table *acl; | |
83 | struct mlx5_flow_group *allowed_vlans_grp; | |
84 | struct mlx5_flow_group *drop_grp; | |
74491de9 MB |
85 | struct mlx5_flow_handle *allowed_vlan; |
86 | struct mlx5_flow_handle *drop_rule; | |
b8a0dbe3 EE |
87 | struct mlx5_fc *drop_counter; |
88 | }; | |
89 | ||
90 | struct mlx5_vport_drop_stats { | |
91 | u64 rx_dropped; | |
92 | u64 tx_dropped; | |
5742df0f MHY |
93 | }; |
94 | ||
1ab2068a MHY |
95 | struct mlx5_vport_info { |
96 | u8 mac[ETH_ALEN]; | |
97 | u16 vlan; | |
98 | u8 qos; | |
99 | u64 node_guid; | |
100 | int link_state; | |
c9497c98 | 101 | u32 min_rate; |
1bd27b11 | 102 | u32 max_rate; |
1ab2068a MHY |
103 | bool spoofchk; |
104 | bool trusted; | |
105 | }; | |
106 | ||
5019833d PP |
107 | /* Vport context events */ |
108 | enum mlx5_eswitch_vport_event { | |
109 | MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), | |
110 | MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), | |
111 | MLX5_VPORT_PROMISC_CHANGE = BIT(3), | |
112 | }; | |
113 | ||
073bb189 SM |
114 | struct mlx5_vport { |
115 | struct mlx5_core_dev *dev; | |
116 | int vport; | |
117 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 118 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
119 | struct mlx5_flow_handle *promisc_rule; |
120 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
121 | struct work_struct vport_change_handler; |
122 | ||
5742df0f MHY |
123 | struct vport_ingress ingress; |
124 | struct vport_egress egress; | |
125 | ||
1ab2068a MHY |
126 | struct mlx5_vport_info info; |
127 | ||
1bd27b11 MHY |
128 | struct { |
129 | bool enabled; | |
130 | u32 esw_tsar_ix; | |
c9497c98 | 131 | u32 bw_share; |
1bd27b11 MHY |
132 | } qos; |
133 | ||
073bb189 | 134 | bool enabled; |
5019833d | 135 | enum mlx5_eswitch_vport_event enabled_events; |
073bb189 SM |
136 | }; |
137 | ||
e52c2802 PB |
138 | enum offloads_fdb_flags { |
139 | ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), | |
140 | }; | |
141 | ||
142 | extern const unsigned int ESW_POOLS[4]; | |
143 | ||
144 | #define PRIO_LEVELS 2 | |
81848731 | 145 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
146 | union { |
147 | struct legacy_fdb { | |
52fff327 | 148 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
149 | struct mlx5_flow_group *addr_grp; |
150 | struct mlx5_flow_group *allmulti_grp; | |
151 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
152 | struct mlx5_flow_table *vepa_fdb; |
153 | struct mlx5_flow_handle *vepa_uplink_rule; | |
154 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 155 | } legacy; |
69697b6e OG |
156 | |
157 | struct offloads_fdb { | |
8463daf1 | 158 | struct mlx5_flow_namespace *ns; |
52fff327 | 159 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 160 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
161 | struct mlx5_flow_group *peer_miss_grp; |
162 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 163 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
164 | struct mlx5_flow_handle *miss_rule_uni; |
165 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 166 | int vlan_push_pop_refcount; |
e52c2802 PB |
167 | |
168 | struct { | |
169 | struct mlx5_flow_table *fdb; | |
170 | u32 num_rules; | |
171 | } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS]; | |
172 | /* Protects fdb_prio table */ | |
173 | struct mutex fdb_prio_lock; | |
174 | ||
175 | int fdb_left[ARRAY_SIZE(ESW_POOLS)]; | |
69697b6e | 176 | } offloads; |
6ab36e35 | 177 | }; |
e52c2802 | 178 | u32 flags; |
6ab36e35 OG |
179 | }; |
180 | ||
c116c6ee OG |
181 | struct mlx5_esw_offload { |
182 | struct mlx5_flow_table *ft_offloads; | |
fed9ce22 | 183 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 184 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
185 | struct list_head peer_flows; |
186 | struct mutex peer_mutex; | |
61086f39 | 187 | struct mutex encap_tbl_lock; /* protects encap_tbl */ |
a54e20b4 | 188 | DECLARE_HASHTABLE(encap_tbl, 8); |
dd58edc3 | 189 | struct mod_hdr_tbl mod_hdr; |
10caabda OS |
190 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
191 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
8693115a | 192 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 193 | u8 inline_mode; |
525e84be | 194 | atomic64_t num_flows; |
98fdbea5 | 195 | enum devlink_eswitch_encap_mode encap; |
c116c6ee OG |
196 | }; |
197 | ||
0a0ab1d2 EC |
198 | /* E-Switch MC FDB table hash node */ |
199 | struct esw_mc_addr { /* SRIOV only */ | |
200 | struct l2addr_node node; | |
201 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
202 | u32 refcnt; | |
203 | }; | |
204 | ||
a3888f33 BW |
205 | struct mlx5_host_work { |
206 | struct work_struct work; | |
207 | struct mlx5_eswitch *esw; | |
208 | }; | |
209 | ||
cd56f929 | 210 | struct mlx5_esw_functions { |
a3888f33 BW |
211 | struct mlx5_nb nb; |
212 | u16 num_vfs; | |
213 | }; | |
214 | ||
7445cfb1 JL |
215 | enum { |
216 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
217 | }; | |
218 | ||
073bb189 SM |
219 | struct mlx5_eswitch { |
220 | struct mlx5_core_dev *dev; | |
6933a937 | 221 | struct mlx5_nb nb; |
81848731 | 222 | struct mlx5_eswitch_fdb fdb_table; |
99ecd646 | 223 | /* legacy data structures */ |
81848731 | 224 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; |
131ce701 PP |
225 | struct esw_mc_addr mc_promisc; |
226 | /* end of legacy */ | |
073bb189 SM |
227 | struct workqueue_struct *work_queue; |
228 | struct mlx5_vport *vports; | |
7445cfb1 | 229 | u32 flags; |
073bb189 | 230 | int total_vports; |
81848731 | 231 | int enabled_vports; |
dfcb1ed3 MHY |
232 | /* Synchronize between vport change events |
233 | * and async SRIOV admin state changes | |
234 | */ | |
235 | struct mutex state_lock; | |
1bd27b11 MHY |
236 | |
237 | struct { | |
238 | bool enabled; | |
239 | u32 root_tsar_id; | |
240 | } qos; | |
241 | ||
c116c6ee | 242 | struct mlx5_esw_offload offloads; |
6ab36e35 | 243 | int mode; |
e52c2802 | 244 | int nvports; |
a1b3839a | 245 | u16 manager_vport; |
411ec9e0 | 246 | u16 first_host_vport; |
cd56f929 | 247 | struct mlx5_esw_functions esw_funcs; |
073bb189 SM |
248 | }; |
249 | ||
5896b972 PP |
250 | void esw_offloads_disable(struct mlx5_eswitch *esw); |
251 | int esw_offloads_enable(struct mlx5_eswitch *esw); | |
e8d31c4d MB |
252 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
253 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
18486737 EB |
254 | void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw, |
255 | struct mlx5_vport *vport); | |
256 | int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw, | |
257 | struct mlx5_vport *vport); | |
258 | void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw, | |
259 | struct mlx5_vport *vport); | |
260 | int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw, | |
261 | struct mlx5_vport *vport); | |
262 | void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw, | |
263 | struct mlx5_vport *vport); | |
264 | void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw, | |
265 | struct mlx5_vport *vport); | |
7445cfb1 JL |
266 | void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw, |
267 | struct mlx5_vport *vport); | |
fcb64c0f EC |
268 | int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, |
269 | u32 rate_mbps); | |
766a0e97 | 270 | |
073bb189 SM |
271 | /* E-Switch API */ |
272 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
273 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
062f4bf4 | 274 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode); |
f6455de0 | 275 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw); |
77256579 | 276 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
02f3afd9 | 277 | u16 vport, u8 mac[ETH_ALEN]); |
77256579 | 278 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 279 | u16 vport, int link_state); |
9e7ea352 | 280 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 281 | u16 vport, u16 vlan, u8 qos); |
f942380c | 282 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 283 | u16 vport, bool spoofchk); |
1edc57e2 | 284 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
285 | u16 vport_num, bool setting); |
286 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 287 | u32 max_rate, u32 min_rate); |
8da202b2 HN |
288 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
289 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 290 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 291 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 292 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 293 | u16 vport, |
3b751a2a | 294 | struct ifla_vf_stats *vf_stats); |
159fe639 | 295 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 296 | |
57843868 JL |
297 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_eswitch *esw, u16 vport, |
298 | void *in, int inlen); | |
299 | int mlx5_eswitch_query_esw_vport_context(struct mlx5_eswitch *esw, u16 vport, | |
300 | void *out, int outlen); | |
301 | ||
3d80d1a2 | 302 | struct mlx5_flow_spec; |
776b12b6 | 303 | struct mlx5_esw_flow_attr; |
10caabda OS |
304 | struct mlx5_termtbl_handle; |
305 | ||
306 | bool | |
307 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
308 | struct mlx5_flow_act *flow_act, | |
309 | struct mlx5_flow_spec *spec); | |
310 | ||
311 | struct mlx5_flow_handle * | |
312 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
313 | struct mlx5_flow_table *ft, | |
314 | struct mlx5_flow_spec *spec, | |
315 | struct mlx5_esw_flow_attr *attr, | |
316 | struct mlx5_flow_act *flow_act, | |
317 | struct mlx5_flow_destination *dest, | |
318 | int num_dest); | |
319 | ||
320 | void | |
321 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
322 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 323 | |
74491de9 | 324 | struct mlx5_flow_handle * |
3d80d1a2 OG |
325 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
326 | struct mlx5_flow_spec *spec, | |
776b12b6 | 327 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
328 | struct mlx5_flow_handle * |
329 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
330 | struct mlx5_flow_spec *spec, | |
331 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
332 | void |
333 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
334 | struct mlx5_flow_handle *rule, | |
335 | struct mlx5_esw_flow_attr *attr); | |
48265006 OG |
336 | void |
337 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
338 | struct mlx5_flow_handle *rule, | |
339 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb | 340 | |
e52c2802 PB |
341 | bool |
342 | mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw); | |
343 | ||
344 | u16 | |
345 | mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw); | |
346 | ||
347 | u32 | |
348 | mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw); | |
349 | ||
74491de9 | 350 | struct mlx5_flow_handle * |
02f3afd9 | 351 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 352 | struct mlx5_flow_destination *dest); |
fed9ce22 | 353 | |
e33dfe31 OG |
354 | enum { |
355 | SET_VLAN_STRIP = BIT(0), | |
356 | SET_VLAN_INSERT = BIT(1) | |
357 | }; | |
358 | ||
d708f902 OG |
359 | enum mlx5_flow_match_level { |
360 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
361 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
362 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
363 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
364 | }; | |
365 | ||
592d3651 CM |
366 | /* current maximum for flow based vport multicasting */ |
367 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
368 | ||
f493f155 EB |
369 | enum { |
370 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 371 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
372 | }; |
373 | ||
776b12b6 OG |
374 | struct mlx5_esw_flow_attr { |
375 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 376 | struct mlx5_core_dev *in_mdev; |
f9392795 | 377 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 378 | |
e85e02ba | 379 | int split_count; |
592d3651 CM |
380 | int out_count; |
381 | ||
776b12b6 | 382 | int action; |
cc495188 JL |
383 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
384 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
385 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
386 | u8 total_vlan; | |
f5f82476 | 387 | bool vlan_handled; |
df65a573 | 388 | struct { |
f493f155 | 389 | u32 flags; |
df65a573 | 390 | struct mlx5_eswitch_rep *rep; |
2b688ea5 | 391 | struct mlx5_pkt_reformat *pkt_reformat; |
df65a573 | 392 | struct mlx5_core_dev *mdev; |
10caabda | 393 | struct mlx5_termtbl_handle *termtbl; |
df65a573 | 394 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
2b688ea5 | 395 | struct mlx5_modify_hdr *modify_hdr; |
93b3586e HN |
396 | u8 inner_match_level; |
397 | u8 outer_match_level; | |
b8aee822 | 398 | struct mlx5_fc *counter; |
e52c2802 PB |
399 | u32 chain; |
400 | u16 prio; | |
401 | u32 dest_chain; | |
232c0013 | 402 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
403 | }; |
404 | ||
db7ff19e EB |
405 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
406 | struct netlink_ext_ack *extack); | |
feae9087 | 407 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
408 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
409 | struct netlink_ext_ack *extack); | |
bffaa916 | 410 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
062f4bf4 | 411 | int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode); |
98fdbea5 LR |
412 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
413 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 414 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
415 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
416 | enum devlink_eswitch_encap_mode *encap); | |
a4b97ab4 | 417 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 418 | |
f5f82476 OG |
419 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
420 | struct mlx5_esw_flow_attr *attr); | |
421 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
422 | struct mlx5_esw_flow_attr *attr); | |
423 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
02f3afd9 | 424 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 425 | |
fdde49e0 PP |
426 | int mlx5_esw_create_vport_egress_acl_vlan(struct mlx5_eswitch *esw, |
427 | struct mlx5_vport *vport, | |
428 | u16 vlan_id, u32 flow_action); | |
429 | ||
cc495188 JL |
430 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
431 | u8 vlan_depth) | |
6acfbf38 | 432 | { |
cc495188 JL |
433 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
434 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
435 | ||
436 | if (vlan_depth == 1) | |
437 | return ret; | |
438 | ||
439 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
440 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
441 | } |
442 | ||
eff849b2 RL |
443 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
444 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
445 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
446 | struct mlx5_core_dev *dev1); | |
eff849b2 | 447 | |
dd28087c | 448 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 449 | |
69697b6e OG |
450 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
451 | ||
27b942fb PP |
452 | #define esw_info(__dev, format, ...) \ |
453 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 454 | |
27b942fb PP |
455 | #define esw_warn(__dev, format, ...) \ |
456 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
457 | |
458 | #define esw_debug(dev, format, ...) \ | |
459 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a BW |
460 | |
461 | /* The returned number is valid only when the dev is eswitch manager. */ | |
462 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
463 | { | |
464 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
465 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
466 | } | |
467 | ||
ea2300e0 PP |
468 | static inline bool |
469 | mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) | |
470 | { | |
471 | return esw->manager_vport == vport_num; | |
472 | } | |
473 | ||
411ec9e0 BW |
474 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
475 | { | |
476 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
477 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
478 | } | |
479 | ||
6706a3b9 VP |
480 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) |
481 | { | |
482 | /* Ideally device should have the functions changed supported | |
483 | * capability regardless of it being ECPF or PF wherever such | |
484 | * event should be processed such as on eswitch manager device. | |
485 | * However, some ECPF based device might not have this capability | |
486 | * set. Hence OR for ECPF check to cover such device. | |
487 | */ | |
488 | return MLX5_CAP_ESW(dev, esw_functions_changed) || | |
489 | mlx5_core_is_ecpf_esw_manager(dev); | |
490 | } | |
491 | ||
5ae51620 BW |
492 | static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw) |
493 | { | |
494 | /* Uplink always locate at the last element of the array.*/ | |
495 | return esw->total_vports - 1; | |
496 | } | |
497 | ||
81cd229c BW |
498 | static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw) |
499 | { | |
500 | return esw->total_vports - 2; | |
501 | } | |
502 | ||
5ae51620 BW |
503 | static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw, |
504 | u16 vport_num) | |
505 | { | |
81cd229c BW |
506 | if (vport_num == MLX5_VPORT_ECPF) { |
507 | if (!mlx5_ecpf_vport_exists(esw->dev)) | |
508 | esw_warn(esw->dev, "ECPF vport doesn't exist!\n"); | |
509 | return mlx5_eswitch_ecpf_idx(esw); | |
510 | } | |
511 | ||
5ae51620 BW |
512 | if (vport_num == MLX5_VPORT_UPLINK) |
513 | return mlx5_eswitch_uplink_idx(esw); | |
514 | ||
515 | return vport_num; | |
516 | } | |
517 | ||
02f3afd9 | 518 | static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw, |
5ae51620 BW |
519 | int index) |
520 | { | |
81cd229c BW |
521 | if (index == mlx5_eswitch_ecpf_idx(esw) && |
522 | mlx5_ecpf_vport_exists(esw->dev)) | |
523 | return MLX5_VPORT_ECPF; | |
524 | ||
5ae51620 BW |
525 | if (index == mlx5_eswitch_uplink_idx(esw)) |
526 | return MLX5_VPORT_UPLINK; | |
527 | ||
528 | return index; | |
529 | } | |
530 | ||
ee576ec1 SM |
531 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
532 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
533 | ||
786ef904 PP |
534 | /* The vport getter/iterator are only valid after esw->total_vports |
535 | * and vport->vport are initialized in mlx5_eswitch_init. | |
536 | */ | |
537 | #define mlx5_esw_for_all_vports(esw, i, vport) \ | |
538 | for ((i) = MLX5_VPORT_PF; \ | |
539 | (vport) = &(esw)->vports[i], \ | |
540 | (i) < (esw)->total_vports; (i)++) | |
541 | ||
5019833d PP |
542 | #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \ |
543 | for ((i) = (esw)->total_vports - 1; \ | |
544 | (vport) = &(esw)->vports[i], \ | |
545 | (i) >= MLX5_VPORT_PF; (i)--) | |
546 | ||
786ef904 PP |
547 | #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \ |
548 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
549 | (vport) = &(esw)->vports[(i)], \ | |
550 | (i) <= (nvfs); (i)++) | |
551 | ||
552 | #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \ | |
553 | for ((i) = (nvfs); \ | |
554 | (vport) = &(esw)->vports[(i)], \ | |
555 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
556 | ||
557 | /* The rep getter/iterator are only valid after esw->total_vports | |
558 | * and vport->vport are initialized in mlx5_eswitch_init. | |
559 | */ | |
560 | #define mlx5_esw_for_all_reps(esw, i, rep) \ | |
561 | for ((i) = MLX5_VPORT_PF; \ | |
562 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
563 | (i) < (esw)->total_vports; (i)++) | |
564 | ||
565 | #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \ | |
566 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
567 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
568 | (i) <= (nvfs); (i)++) | |
569 | ||
570 | #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \ | |
571 | for ((i) = (nvfs); \ | |
572 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
573 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
574 | ||
575 | #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \ | |
576 | for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++) | |
577 | ||
578 | #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \ | |
579 | for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--) | |
580 | ||
411ec9e0 BW |
581 | /* Includes host PF (vport 0) if it's not esw manager. */ |
582 | #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \ | |
583 | for ((i) = (esw)->first_host_vport; \ | |
584 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
585 | (i) <= (nvfs); (i)++) | |
586 | ||
587 | #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \ | |
588 | for ((i) = (nvfs); \ | |
589 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
590 | (i) >= (esw)->first_host_vport; (i)--) | |
591 | ||
592 | #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \ | |
593 | for ((vport) = (esw)->first_host_vport; \ | |
594 | (vport) <= (nvfs); (vport)++) | |
595 | ||
596 | #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \ | |
597 | for ((vport) = (nvfs); \ | |
598 | (vport) >= (esw)->first_host_vport; (vport)--) | |
599 | ||
5d9986a3 BW |
600 | struct mlx5_vport *__must_check |
601 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
602 | ||
91d6291c PP |
603 | bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num); |
604 | ||
062f4bf4 | 605 | void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs); |
16fff98a | 606 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 607 | |
5019833d PP |
608 | void |
609 | mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, | |
610 | enum mlx5_eswitch_vport_event enabled_events); | |
611 | void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); | |
612 | ||
e80541ec SM |
613 | #else /* CONFIG_MLX5_ESWITCH */ |
614 | /* eswitch API stubs */ | |
615 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
616 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
062f4bf4 | 617 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { return 0; } |
f6455de0 | 618 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {} |
eff849b2 | 619 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 620 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
dd28087c | 621 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 622 | { |
dd28087c | 623 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 624 | } |
328edb49 | 625 | |
062f4bf4 BW |
626 | static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {} |
627 | ||
328edb49 | 628 | #define FDB_MAX_CHAIN 1 |
c92a0b94 | 629 | #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1) |
328edb49 PB |
630 | #define FDB_MAX_PRIO 1 |
631 | ||
e80541ec SM |
632 | #endif /* CONFIG_MLX5_ESWITCH */ |
633 | ||
073bb189 | 634 | #endif /* __MLX5_ESWITCH_H__ */ |