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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
525e84be | 38 | #include <linux/atomic.h> |
feae9087 | 39 | #include <net/devlink.h> |
073bb189 | 40 | #include <linux/mlx5/device.h> |
57cbd893 | 41 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 42 | #include <linux/mlx5/vport.h> |
cc495188 | 43 | #include <linux/mlx5/fs.h> |
eeb66cdb | 44 | #include "lib/mpfs.h" |
4c3844d9 | 45 | #include "en/tc_ct.h" |
073bb189 | 46 | |
2cf2954b | 47 | #define FDB_TC_MAX_CHAIN 3 |
975b992f PB |
48 | #define FDB_FT_CHAIN (FDB_TC_MAX_CHAIN + 1) |
49 | #define FDB_TC_SLOW_PATH_CHAIN (FDB_FT_CHAIN + 1) | |
50 | ||
51 | /* The index of the last real chain (FT) + 1 as chain zero is valid as well */ | |
52 | #define FDB_NUM_CHAINS (FDB_FT_CHAIN + 1) | |
53 | ||
2cf2954b | 54 | #define FDB_TC_MAX_PRIO 16 |
4db7b98e | 55 | #define FDB_TC_LEVELS_PER_PRIO 2 |
12063c2e | 56 | |
e80541ec SM |
57 | #ifdef CONFIG_MLX5_ESWITCH |
58 | ||
87dac697 JL |
59 | #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 |
60 | ||
073bb189 SM |
61 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
62 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
63 | ||
64 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
65 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
66 | ||
c9497c98 MHY |
67 | #define MLX5_MIN_BW_SHARE 1 |
68 | ||
69 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
70 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
71 | ||
a842dd04 CM |
72 | #define mlx5_esw_has_fwd_fdb(dev) \ |
73 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
74 | ||
5742df0f MHY |
75 | struct vport_ingress { |
76 | struct mlx5_flow_table *acl; | |
10652f39 | 77 | struct mlx5_flow_handle *allow_rule; |
853b5352 | 78 | struct { |
10652f39 PP |
79 | struct mlx5_flow_group *allow_spoofchk_only_grp; |
80 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
81 | struct mlx5_flow_group *allow_untagged_only_grp; | |
82 | struct mlx5_flow_group *drop_grp; | |
853b5352 PP |
83 | struct mlx5_flow_handle *drop_rule; |
84 | struct mlx5_fc *drop_counter; | |
85 | } legacy; | |
d68316b5 | 86 | struct { |
b7826076 PP |
87 | /* Optional group to add an FTE to do internal priority |
88 | * tagging on ingress packets. | |
89 | */ | |
90 | struct mlx5_flow_group *metadata_prio_tag_grp; | |
91 | /* Group to add default match-all FTE entry to tag ingress | |
92 | * packet with metadata. | |
93 | */ | |
94 | struct mlx5_flow_group *metadata_allmatch_grp; | |
d68316b5 PP |
95 | struct mlx5_modify_hdr *modify_metadata; |
96 | struct mlx5_flow_handle *modify_metadata_rule; | |
97 | } offloads; | |
5742df0f MHY |
98 | }; |
99 | ||
100 | struct vport_egress { | |
101 | struct mlx5_flow_table *acl; | |
74491de9 | 102 | struct mlx5_flow_handle *allowed_vlan; |
ea651a86 | 103 | struct mlx5_flow_group *vlan_grp; |
bf773dc0 VP |
104 | union { |
105 | struct { | |
106 | struct mlx5_flow_group *drop_grp; | |
107 | struct mlx5_flow_handle *drop_rule; | |
108 | struct mlx5_fc *drop_counter; | |
109 | } legacy; | |
110 | struct { | |
111 | struct mlx5_flow_group *fwd_grp; | |
112 | struct mlx5_flow_handle *fwd_rule; | |
113 | } offloads; | |
114 | }; | |
b8a0dbe3 EE |
115 | }; |
116 | ||
117 | struct mlx5_vport_drop_stats { | |
118 | u64 rx_dropped; | |
119 | u64 tx_dropped; | |
5742df0f MHY |
120 | }; |
121 | ||
1ab2068a MHY |
122 | struct mlx5_vport_info { |
123 | u8 mac[ETH_ALEN]; | |
124 | u16 vlan; | |
125 | u8 qos; | |
126 | u64 node_guid; | |
127 | int link_state; | |
c9497c98 | 128 | u32 min_rate; |
1bd27b11 | 129 | u32 max_rate; |
1ab2068a MHY |
130 | bool spoofchk; |
131 | bool trusted; | |
132 | }; | |
133 | ||
5019833d PP |
134 | /* Vport context events */ |
135 | enum mlx5_eswitch_vport_event { | |
136 | MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), | |
137 | MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), | |
138 | MLX5_VPORT_PROMISC_CHANGE = BIT(3), | |
139 | }; | |
140 | ||
073bb189 SM |
141 | struct mlx5_vport { |
142 | struct mlx5_core_dev *dev; | |
143 | int vport; | |
144 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; | |
81848731 | 145 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
146 | struct mlx5_flow_handle *promisc_rule; |
147 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
148 | struct work_struct vport_change_handler; |
149 | ||
5742df0f MHY |
150 | struct vport_ingress ingress; |
151 | struct vport_egress egress; | |
152 | ||
1ab2068a MHY |
153 | struct mlx5_vport_info info; |
154 | ||
1bd27b11 MHY |
155 | struct { |
156 | bool enabled; | |
157 | u32 esw_tsar_ix; | |
c9497c98 | 158 | u32 bw_share; |
1bd27b11 MHY |
159 | } qos; |
160 | ||
073bb189 | 161 | bool enabled; |
5019833d | 162 | enum mlx5_eswitch_vport_event enabled_events; |
073bb189 SM |
163 | }; |
164 | ||
e52c2802 PB |
165 | enum offloads_fdb_flags { |
166 | ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0), | |
167 | }; | |
168 | ||
39ac237c | 169 | struct mlx5_esw_chains_priv; |
e52c2802 | 170 | |
81848731 | 171 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
172 | union { |
173 | struct legacy_fdb { | |
52fff327 | 174 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
175 | struct mlx5_flow_group *addr_grp; |
176 | struct mlx5_flow_group *allmulti_grp; | |
177 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
178 | struct mlx5_flow_table *vepa_fdb; |
179 | struct mlx5_flow_handle *vepa_uplink_rule; | |
180 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 181 | } legacy; |
69697b6e OG |
182 | |
183 | struct offloads_fdb { | |
8463daf1 | 184 | struct mlx5_flow_namespace *ns; |
52fff327 | 185 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 186 | struct mlx5_flow_group *send_to_vport_grp; |
ac004b83 RD |
187 | struct mlx5_flow_group *peer_miss_grp; |
188 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 189 | struct mlx5_flow_group *miss_grp; |
f80be543 MB |
190 | struct mlx5_flow_handle *miss_rule_uni; |
191 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 192 | int vlan_push_pop_refcount; |
e52c2802 | 193 | |
39ac237c | 194 | struct mlx5_esw_chains_priv *esw_chains_priv; |
96e32687 EC |
195 | struct { |
196 | DECLARE_HASHTABLE(table, 8); | |
197 | /* Protects vports.table */ | |
198 | struct mutex lock; | |
199 | } vports; | |
200 | ||
69697b6e | 201 | } offloads; |
6ab36e35 | 202 | }; |
e52c2802 | 203 | u32 flags; |
6ab36e35 OG |
204 | }; |
205 | ||
c116c6ee | 206 | struct mlx5_esw_offload { |
11b717d6 PB |
207 | struct mlx5_flow_table *ft_offloads_restore; |
208 | struct mlx5_flow_group *restore_group; | |
6724e66b | 209 | struct mlx5_modify_hdr *restore_copy_hdr_id; |
11b717d6 | 210 | |
c116c6ee | 211 | struct mlx5_flow_table *ft_offloads; |
fed9ce22 | 212 | struct mlx5_flow_group *vport_rx_group; |
127ea380 | 213 | struct mlx5_eswitch_rep *vport_reps; |
04de7dda RD |
214 | struct list_head peer_flows; |
215 | struct mutex peer_mutex; | |
61086f39 | 216 | struct mutex encap_tbl_lock; /* protects encap_tbl */ |
a54e20b4 | 217 | DECLARE_HASHTABLE(encap_tbl, 8); |
14e6b038 EC |
218 | struct mutex decap_tbl_lock; /* protects decap_tbl */ |
219 | DECLARE_HASHTABLE(decap_tbl, 8); | |
dd58edc3 | 220 | struct mod_hdr_tbl mod_hdr; |
10caabda OS |
221 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
222 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
8693115a | 223 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 224 | u8 inline_mode; |
525e84be | 225 | atomic64_t num_flows; |
98fdbea5 | 226 | enum devlink_eswitch_encap_mode encap; |
c116c6ee OG |
227 | }; |
228 | ||
0a0ab1d2 EC |
229 | /* E-Switch MC FDB table hash node */ |
230 | struct esw_mc_addr { /* SRIOV only */ | |
231 | struct l2addr_node node; | |
232 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
233 | u32 refcnt; | |
234 | }; | |
235 | ||
a3888f33 BW |
236 | struct mlx5_host_work { |
237 | struct work_struct work; | |
238 | struct mlx5_eswitch *esw; | |
239 | }; | |
240 | ||
cd56f929 | 241 | struct mlx5_esw_functions { |
a3888f33 BW |
242 | struct mlx5_nb nb; |
243 | u16 num_vfs; | |
244 | }; | |
245 | ||
7445cfb1 JL |
246 | enum { |
247 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
5b7cb745 | 248 | MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), |
7445cfb1 JL |
249 | }; |
250 | ||
073bb189 SM |
251 | struct mlx5_eswitch { |
252 | struct mlx5_core_dev *dev; | |
6933a937 | 253 | struct mlx5_nb nb; |
81848731 | 254 | struct mlx5_eswitch_fdb fdb_table; |
99ecd646 | 255 | /* legacy data structures */ |
81848731 | 256 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; |
131ce701 PP |
257 | struct esw_mc_addr mc_promisc; |
258 | /* end of legacy */ | |
073bb189 SM |
259 | struct workqueue_struct *work_queue; |
260 | struct mlx5_vport *vports; | |
7445cfb1 | 261 | u32 flags; |
073bb189 | 262 | int total_vports; |
81848731 | 263 | int enabled_vports; |
dfcb1ed3 MHY |
264 | /* Synchronize between vport change events |
265 | * and async SRIOV admin state changes | |
266 | */ | |
267 | struct mutex state_lock; | |
1bd27b11 | 268 | |
8e0aa4bc PP |
269 | /* Protects eswitch mode change that occurs via one or more |
270 | * user commands, i.e. sriov state change, devlink commands. | |
271 | */ | |
272 | struct mutex mode_lock; | |
273 | ||
1bd27b11 MHY |
274 | struct { |
275 | bool enabled; | |
276 | u32 root_tsar_id; | |
277 | } qos; | |
278 | ||
c116c6ee | 279 | struct mlx5_esw_offload offloads; |
6ab36e35 | 280 | int mode; |
e52c2802 | 281 | int nvports; |
a1b3839a | 282 | u16 manager_vport; |
411ec9e0 | 283 | u16 first_host_vport; |
cd56f929 | 284 | struct mlx5_esw_functions esw_funcs; |
87dac697 JL |
285 | struct { |
286 | u32 large_group_num; | |
287 | } params; | |
073bb189 SM |
288 | }; |
289 | ||
5896b972 PP |
290 | void esw_offloads_disable(struct mlx5_eswitch *esw); |
291 | int esw_offloads_enable(struct mlx5_eswitch *esw); | |
e8d31c4d MB |
292 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
293 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
ea651a86 | 294 | |
fcb64c0f EC |
295 | int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, |
296 | u32 rate_mbps); | |
766a0e97 | 297 | |
073bb189 SM |
298 | /* E-Switch API */ |
299 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
300 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
ebf77bb8 PP |
301 | |
302 | #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) | |
8e0aa4bc PP |
303 | int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int mode, int num_vfs); |
304 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); | |
305 | void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw, bool clear_vf); | |
556b9d16 | 306 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf); |
77256579 | 307 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
02f3afd9 | 308 | u16 vport, u8 mac[ETH_ALEN]); |
77256579 | 309 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 310 | u16 vport, int link_state); |
9e7ea352 | 311 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 312 | u16 vport, u16 vlan, u8 qos); |
f942380c | 313 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 314 | u16 vport, bool spoofchk); |
1edc57e2 | 315 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
316 | u16 vport_num, bool setting); |
317 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 318 | u32 max_rate, u32 min_rate); |
8da202b2 HN |
319 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
320 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 321 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 322 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 323 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 324 | u16 vport, |
3b751a2a | 325 | struct ifla_vf_stats *vf_stats); |
159fe639 | 326 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 327 | |
238302fa | 328 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, |
e08a6832 | 329 | bool other_vport, void *in); |
57843868 | 330 | |
3d80d1a2 | 331 | struct mlx5_flow_spec; |
776b12b6 | 332 | struct mlx5_esw_flow_attr; |
10caabda OS |
333 | struct mlx5_termtbl_handle; |
334 | ||
335 | bool | |
336 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
d8a2034f | 337 | struct mlx5_esw_flow_attr *attr, |
10caabda OS |
338 | struct mlx5_flow_act *flow_act, |
339 | struct mlx5_flow_spec *spec); | |
340 | ||
341 | struct mlx5_flow_handle * | |
342 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
343 | struct mlx5_flow_table *ft, | |
344 | struct mlx5_flow_spec *spec, | |
345 | struct mlx5_esw_flow_attr *attr, | |
346 | struct mlx5_flow_act *flow_act, | |
347 | struct mlx5_flow_destination *dest, | |
348 | int num_dest); | |
349 | ||
350 | void | |
351 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
352 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 353 | |
74491de9 | 354 | struct mlx5_flow_handle * |
3d80d1a2 OG |
355 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
356 | struct mlx5_flow_spec *spec, | |
776b12b6 | 357 | struct mlx5_esw_flow_attr *attr); |
e4ad91f2 CM |
358 | struct mlx5_flow_handle * |
359 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
360 | struct mlx5_flow_spec *spec, | |
361 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb OG |
362 | void |
363 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
364 | struct mlx5_flow_handle *rule, | |
365 | struct mlx5_esw_flow_attr *attr); | |
48265006 OG |
366 | void |
367 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
368 | struct mlx5_flow_handle *rule, | |
369 | struct mlx5_esw_flow_attr *attr); | |
d85cdccb | 370 | |
74491de9 | 371 | struct mlx5_flow_handle * |
02f3afd9 | 372 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 373 | struct mlx5_flow_destination *dest); |
fed9ce22 | 374 | |
e33dfe31 OG |
375 | enum { |
376 | SET_VLAN_STRIP = BIT(0), | |
377 | SET_VLAN_INSERT = BIT(1) | |
378 | }; | |
379 | ||
d708f902 OG |
380 | enum mlx5_flow_match_level { |
381 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
382 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
383 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
384 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
385 | }; | |
386 | ||
592d3651 CM |
387 | /* current maximum for flow based vport multicasting */ |
388 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
389 | ||
f493f155 EB |
390 | enum { |
391 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 392 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
f493f155 EB |
393 | }; |
394 | ||
39ac237c PB |
395 | enum { |
396 | MLX5_ESW_ATTR_FLAG_VLAN_HANDLED = BIT(0), | |
397 | MLX5_ESW_ATTR_FLAG_SLOW_PATH = BIT(1), | |
6fb0701a | 398 | MLX5_ESW_ATTR_FLAG_NO_IN_PORT = BIT(2), |
39ac237c PB |
399 | }; |
400 | ||
776b12b6 OG |
401 | struct mlx5_esw_flow_attr { |
402 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 403 | struct mlx5_core_dev *in_mdev; |
f9392795 | 404 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 405 | |
e85e02ba | 406 | int split_count; |
592d3651 CM |
407 | int out_count; |
408 | ||
776b12b6 | 409 | int action; |
cc495188 JL |
410 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
411 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
412 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
413 | u8 total_vlan; | |
df65a573 | 414 | struct { |
f493f155 | 415 | u32 flags; |
df65a573 | 416 | struct mlx5_eswitch_rep *rep; |
2b688ea5 | 417 | struct mlx5_pkt_reformat *pkt_reformat; |
df65a573 | 418 | struct mlx5_core_dev *mdev; |
10caabda | 419 | struct mlx5_termtbl_handle *termtbl; |
df65a573 | 420 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
2b688ea5 | 421 | struct mlx5_modify_hdr *modify_hdr; |
93b3586e HN |
422 | u8 inner_match_level; |
423 | u8 outer_match_level; | |
b8aee822 | 424 | struct mlx5_fc *counter; |
e52c2802 PB |
425 | u32 chain; |
426 | u16 prio; | |
427 | u32 dest_chain; | |
39ac237c | 428 | u32 flags; |
d18296ff PB |
429 | struct mlx5_flow_table *fdb; |
430 | struct mlx5_flow_table *dest_ft; | |
4c3844d9 | 431 | struct mlx5_ct_attr ct_attr; |
14e6b038 | 432 | struct mlx5_pkt_reformat *decap_pkt_reformat; |
232c0013 | 433 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
776b12b6 OG |
434 | }; |
435 | ||
db7ff19e EB |
436 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
437 | struct netlink_ext_ack *extack); | |
feae9087 | 438 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
439 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
440 | struct netlink_ext_ack *extack); | |
bffaa916 | 441 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
98fdbea5 LR |
442 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
443 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 444 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
445 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
446 | enum devlink_eswitch_encap_mode *encap); | |
a4b97ab4 | 447 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 448 | |
f5f82476 OG |
449 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
450 | struct mlx5_esw_flow_attr *attr); | |
451 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
452 | struct mlx5_esw_flow_attr *attr); | |
453 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, | |
02f3afd9 | 454 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 455 | |
b5f814cc EC |
456 | static inline bool mlx5_esw_qos_enabled(struct mlx5_eswitch *esw) |
457 | { | |
458 | return esw->qos.enabled; | |
459 | } | |
460 | ||
cc495188 JL |
461 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
462 | u8 vlan_depth) | |
6acfbf38 | 463 | { |
cc495188 JL |
464 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
465 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
466 | ||
467 | if (vlan_depth == 1) | |
468 | return ret; | |
469 | ||
470 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
471 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
472 | } |
473 | ||
eff849b2 RL |
474 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
475 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
476 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
477 | struct mlx5_core_dev *dev1); | |
eff849b2 | 478 | |
dd28087c | 479 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 480 | |
69697b6e OG |
481 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
482 | ||
27b942fb PP |
483 | #define esw_info(__dev, format, ...) \ |
484 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 485 | |
27b942fb PP |
486 | #define esw_warn(__dev, format, ...) \ |
487 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
488 | |
489 | #define esw_debug(dev, format, ...) \ | |
490 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a BW |
491 | |
492 | /* The returned number is valid only when the dev is eswitch manager. */ | |
493 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
494 | { | |
495 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
496 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
497 | } | |
498 | ||
ea2300e0 PP |
499 | static inline bool |
500 | mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) | |
501 | { | |
502 | return esw->manager_vport == vport_num; | |
503 | } | |
504 | ||
411ec9e0 BW |
505 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
506 | { | |
507 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
508 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
509 | } | |
510 | ||
6706a3b9 VP |
511 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) |
512 | { | |
513 | /* Ideally device should have the functions changed supported | |
514 | * capability regardless of it being ECPF or PF wherever such | |
515 | * event should be processed such as on eswitch manager device. | |
516 | * However, some ECPF based device might not have this capability | |
517 | * set. Hence OR for ECPF check to cover such device. | |
518 | */ | |
519 | return MLX5_CAP_ESW(dev, esw_functions_changed) || | |
520 | mlx5_core_is_ecpf_esw_manager(dev); | |
521 | } | |
522 | ||
5ae51620 BW |
523 | static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw) |
524 | { | |
525 | /* Uplink always locate at the last element of the array.*/ | |
526 | return esw->total_vports - 1; | |
527 | } | |
528 | ||
81cd229c BW |
529 | static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw) |
530 | { | |
531 | return esw->total_vports - 2; | |
532 | } | |
533 | ||
5ae51620 BW |
534 | static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw, |
535 | u16 vport_num) | |
536 | { | |
81cd229c BW |
537 | if (vport_num == MLX5_VPORT_ECPF) { |
538 | if (!mlx5_ecpf_vport_exists(esw->dev)) | |
539 | esw_warn(esw->dev, "ECPF vport doesn't exist!\n"); | |
540 | return mlx5_eswitch_ecpf_idx(esw); | |
541 | } | |
542 | ||
5ae51620 BW |
543 | if (vport_num == MLX5_VPORT_UPLINK) |
544 | return mlx5_eswitch_uplink_idx(esw); | |
545 | ||
546 | return vport_num; | |
547 | } | |
548 | ||
02f3afd9 | 549 | static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw, |
5ae51620 BW |
550 | int index) |
551 | { | |
81cd229c BW |
552 | if (index == mlx5_eswitch_ecpf_idx(esw) && |
553 | mlx5_ecpf_vport_exists(esw->dev)) | |
554 | return MLX5_VPORT_ECPF; | |
555 | ||
5ae51620 BW |
556 | if (index == mlx5_eswitch_uplink_idx(esw)) |
557 | return MLX5_VPORT_UPLINK; | |
558 | ||
559 | return index; | |
560 | } | |
561 | ||
ee576ec1 SM |
562 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
563 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
564 | ||
786ef904 PP |
565 | /* The vport getter/iterator are only valid after esw->total_vports |
566 | * and vport->vport are initialized in mlx5_eswitch_init. | |
567 | */ | |
568 | #define mlx5_esw_for_all_vports(esw, i, vport) \ | |
569 | for ((i) = MLX5_VPORT_PF; \ | |
570 | (vport) = &(esw)->vports[i], \ | |
571 | (i) < (esw)->total_vports; (i)++) | |
572 | ||
5019833d PP |
573 | #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \ |
574 | for ((i) = (esw)->total_vports - 1; \ | |
575 | (vport) = &(esw)->vports[i], \ | |
576 | (i) >= MLX5_VPORT_PF; (i)--) | |
577 | ||
786ef904 PP |
578 | #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \ |
579 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
580 | (vport) = &(esw)->vports[(i)], \ | |
581 | (i) <= (nvfs); (i)++) | |
582 | ||
583 | #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \ | |
584 | for ((i) = (nvfs); \ | |
585 | (vport) = &(esw)->vports[(i)], \ | |
586 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
587 | ||
588 | /* The rep getter/iterator are only valid after esw->total_vports | |
589 | * and vport->vport are initialized in mlx5_eswitch_init. | |
590 | */ | |
591 | #define mlx5_esw_for_all_reps(esw, i, rep) \ | |
592 | for ((i) = MLX5_VPORT_PF; \ | |
593 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
594 | (i) < (esw)->total_vports; (i)++) | |
595 | ||
596 | #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \ | |
597 | for ((i) = MLX5_VPORT_FIRST_VF; \ | |
598 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
599 | (i) <= (nvfs); (i)++) | |
600 | ||
601 | #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \ | |
602 | for ((i) = (nvfs); \ | |
603 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
604 | (i) >= MLX5_VPORT_FIRST_VF; (i)--) | |
605 | ||
606 | #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \ | |
607 | for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++) | |
608 | ||
609 | #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \ | |
610 | for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--) | |
611 | ||
411ec9e0 BW |
612 | /* Includes host PF (vport 0) if it's not esw manager. */ |
613 | #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \ | |
614 | for ((i) = (esw)->first_host_vport; \ | |
615 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
616 | (i) <= (nvfs); (i)++) | |
617 | ||
618 | #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \ | |
619 | for ((i) = (nvfs); \ | |
620 | (rep) = &(esw)->offloads.vport_reps[i], \ | |
621 | (i) >= (esw)->first_host_vport; (i)--) | |
622 | ||
623 | #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \ | |
624 | for ((vport) = (esw)->first_host_vport; \ | |
625 | (vport) <= (nvfs); (vport)++) | |
626 | ||
627 | #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \ | |
628 | for ((vport) = (nvfs); \ | |
629 | (vport) >= (esw)->first_host_vport; (vport)--) | |
630 | ||
5d9986a3 BW |
631 | struct mlx5_vport *__must_check |
632 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
633 | ||
91d6291c PP |
634 | bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num); |
635 | ||
16fff98a | 636 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 637 | |
925a6acc | 638 | int |
5019833d PP |
639 | mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, |
640 | enum mlx5_eswitch_vport_event enabled_events); | |
641 | void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); | |
642 | ||
748da30b VP |
643 | int |
644 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, | |
645 | struct mlx5_vport *vport); | |
646 | void | |
647 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, | |
648 | struct mlx5_vport *vport); | |
649 | ||
96e32687 EC |
650 | int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw); |
651 | void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw); | |
652 | ||
11b717d6 PB |
653 | struct mlx5_flow_handle * |
654 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); | |
655 | u32 | |
656 | esw_get_max_restore_tag(struct mlx5_eswitch *esw); | |
657 | ||
c2d7712c BW |
658 | int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num); |
659 | void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num); | |
660 | ||
23bb50cf BW |
661 | int mlx5_eswitch_load_vport(struct mlx5_eswitch *esw, u16 vport_num, |
662 | enum mlx5_eswitch_vport_event enabled_events); | |
663 | void mlx5_eswitch_unload_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
664 | ||
665 | int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, | |
666 | enum mlx5_eswitch_vport_event enabled_events); | |
667 | void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); | |
668 | ||
e80541ec SM |
669 | #else /* CONFIG_MLX5_ESWITCH */ |
670 | /* eswitch API stubs */ | |
671 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
672 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
8e0aa4bc | 673 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } |
556b9d16 | 674 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf) {} |
eff849b2 | 675 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 676 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
dd28087c | 677 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 678 | { |
dd28087c | 679 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 680 | } |
328edb49 | 681 | |
9d3faa51 | 682 | static inline struct mlx5_flow_handle * |
11b717d6 PB |
683 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) |
684 | { | |
685 | return ERR_PTR(-EOPNOTSUPP); | |
686 | } | |
e80541ec SM |
687 | #endif /* CONFIG_MLX5_ESWITCH */ |
688 | ||
073bb189 | 689 | #endif /* __MLX5_ESWITCH_H__ */ |