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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
69697b6e 51
47dd7e60
PP		 52#define mlx5_esw_for_each_rep(esw, i, rep) \
53 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
54
55#define mlx5_esw_for_each_sf_rep(esw, i, rep) \
56 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
57
58#define mlx5_esw_for_each_vf_rep(esw, index, rep) \
59 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
60 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
61
cd7e4186
BW		 62/* There are two match-all miss flows, one for unicast dst mac and
63 * one for multicast.
64 */
65#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 66#define UPLINK_REP_INDEX 0
67
c796bb7c
CM		 68#define MLX5_ESW_VPORT_TBL_SIZE 128
69#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
70
71static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
72 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
73 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
74 .flags = 0,
75};
76
879c8f84
BW		 77static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
78 u16 vport_num)
79{
47dd7e60 80 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 81}
82
6f7bbad1
JL		 83static void
84mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
85 struct mlx5_flow_spec *spec,
86 struct mlx5_esw_flow_attr *attr)
87{
88 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
036e19b9
HI		 89 attr && attr->in_rep)
90 spec->flow_context.flow_source =
91 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
92 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
93 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 94}
b7826076 95
f94d6389
CM		 96/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
97 * are not needed as well in the following process. So clear them all for simplicity.
98 */
99void
100mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
101{
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
103 void *misc2;
104
105 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
106 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
107
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
110
111 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
112 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
113 }
114}
115
c01cfd0f
JL		 116static void
117mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
118 struct mlx5_flow_spec *spec,
a508728a 119 struct mlx5_flow_attr *attr,
b055ecf5
MB		 120 struct mlx5_eswitch *src_esw,
121 u16 vport)
c01cfd0f
JL		 122{
123 void *misc2;
124 void *misc;
125
126 /* Use metadata matching because vport is not represented by single
127 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
128 */
129 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 130 if (mlx5_esw_indir_table_decap_vport(attr))
131 vport = mlx5_esw_indir_table_decap_vport(attr);
c01cfd0f
JL		 132 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
133 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
b055ecf5
MB		 134 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
135 vport));
c01cfd0f
JL		 136
137 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 138 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
139 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 140
141 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 142 } else {
143 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 144 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 145
146 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
147 MLX5_SET(fte_match_set_misc, misc,
148 source_eswitch_owner_vhca_id,
b055ecf5 149 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 150
151 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
152 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
153 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
154 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
155 source_eswitch_owner_vhca_id);
156
157 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
158 }
c01cfd0f
JL		 159}
160
a508728a
VB		 161static int
162esw_setup_decap_indir(struct mlx5_eswitch *esw,
163 struct mlx5_flow_attr *attr,
164 struct mlx5_flow_spec *spec)
165{
166 struct mlx5_flow_table *ft;
167
168 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
169 return -EOPNOTSUPP;
170
171 ft = mlx5_esw_indir_table_get(esw, attr, spec,
172 mlx5_esw_indir_table_decap_vport(attr), true);
173 return PTR_ERR_OR_ZERO(ft);
174}
175
9e51c0a6 176static void
a508728a
VB		 177esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
178 struct mlx5_flow_attr *attr)
179{
180 if (mlx5_esw_indir_table_decap_vport(attr))
181 mlx5_esw_indir_table_put(esw, attr,
182 mlx5_esw_indir_table_decap_vport(attr),
183 true);
184}
185
f94d6389
CM		 186static int
187esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
188 struct mlx5_flow_act *flow_act,
189 struct mlx5_esw_flow_attr *esw_attr,
190 int i)
191{
192 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
193 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
194 dest[i].sampler_id = esw_attr->sample->sampler_id;
195
196 return 0;
197}
198
a508728a 199static int
9e51c0a6
VB		 200esw_setup_ft_dest(struct mlx5_flow_destination *dest,
201 struct mlx5_flow_act *flow_act,
a508728a 202 struct mlx5_eswitch *esw,
9e51c0a6 203 struct mlx5_flow_attr *attr,
a508728a 204 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 205 int i)
206{
207 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
208 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
209 dest[i].ft = attr->dest_ft;
a508728a
VB		 210
211 if (mlx5_esw_indir_table_decap_vport(attr))
212 return esw_setup_decap_indir(esw, attr, spec);
213 return 0;
9e51c0a6
VB		 214}
215
216static void
217esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,
218 struct mlx5_flow_act *flow_act,
219 struct mlx5_fs_chains *chains,
220 int i)
221{
2a2c84fa
RD		 222 if (mlx5_chains_ignore_flow_level_supported(chains))
223 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
9e51c0a6
VB		 224 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
225 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
226}
227
228static int
229esw_setup_chain_dest(struct mlx5_flow_destination *dest,
230 struct mlx5_flow_act *flow_act,
231 struct mlx5_fs_chains *chains,
232 u32 chain, u32 prio, u32 level,
233 int i)
234{
235 struct mlx5_flow_table *ft;
236
237 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
238 ft = mlx5_chains_get_table(chains, chain, prio, level);
239 if (IS_ERR(ft))
240 return PTR_ERR(ft);
241
242 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
243 dest[i].ft = ft;
244 return 0;
245}
246
10742efc
VB		 247static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
248 int from, int to)
249{
250 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
251 struct mlx5_fs_chains *chains = esw_chains(esw);
252 int i;
253
254 for (i = from; i < to; i++)
255 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
256 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 257 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
258 esw_attr->dests[i].mdev))
259 mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport,
260 false);
10742efc
VB		 261}
262
263static bool
264esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
265{
266 int i;
267
268 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
269 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
270 return true;
271 return false;
272}
273
274static int
275esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
276 struct mlx5_flow_act *flow_act,
277 struct mlx5_eswitch *esw,
278 struct mlx5_fs_chains *chains,
279 struct mlx5_flow_attr *attr,
280 int *i)
281{
282 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
283 int j, err;
284
285 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
286 return -EOPNOTSUPP;
287
288 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
289 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
290 if (err)
291 goto err_setup_chain;
292 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
293 flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat;
294 }
295 return 0;
296
297err_setup_chain:
298 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
299 return err;
300}
301
302static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
303 struct mlx5_flow_attr *attr)
304{
305 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
306
307 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
308}
309
a508728a
VB		 310static bool
311esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
312{
313 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
314 int i;
315
316 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
317 if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
318 esw_attr->dests[i].mdev))
319 return true;
320 return false;
321}
322
323static int
324esw_setup_indir_table(struct mlx5_flow_destination *dest,
325 struct mlx5_flow_act *flow_act,
326 struct mlx5_eswitch *esw,
327 struct mlx5_flow_attr *attr,
328 struct mlx5_flow_spec *spec,
329 bool ignore_flow_lvl,
330 int *i)
331{
332 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
333 int j, err;
334
335 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
336 return -EOPNOTSUPP;
337
338 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
339 if (ignore_flow_lvl)
340 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
341 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
342
343 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec,
344 esw_attr->dests[j].rep->vport, false);
345 if (IS_ERR(dest[*i].ft)) {
346 err = PTR_ERR(dest[*i].ft);
347 goto err_indir_tbl_get;
348 }
349 }
350
351 if (mlx5_esw_indir_table_decap_vport(attr)) {
352 err = esw_setup_decap_indir(esw, attr, spec);
353 if (err)
354 goto err_indir_tbl_get;
355 }
356
357 return 0;
358
359err_indir_tbl_get:
360 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
361 return err;
362}
363
364static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
365{
366 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
367
368 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
369 esw_cleanup_decap_indir(esw, attr);
370}
371
9e51c0a6
VB		 372static void
373esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
374{
375 mlx5_chains_put_table(chains, chain, prio, level);
376}
377
378static void
379esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
380 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
381 int attr_idx, int dest_idx, bool pkt_reformat)
382{
383 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
384 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
385 dest[dest_idx].vport.vhca_id =
386 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
387 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
388 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
389 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
390 if (pkt_reformat) {
391 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
392 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
393 }
394 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
395 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
396 }
397}
398
399static int
400esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
401 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
402 int i)
403{
404 int j;
405
406 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
407 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
408 return i;
409}
410
e929e3da
MD		 411static bool
412esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
413{
414 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
415 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
416 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
417}
418
9e51c0a6
VB		 419static int
420esw_setup_dests(struct mlx5_flow_destination *dest,
421 struct mlx5_flow_act *flow_act,
422 struct mlx5_eswitch *esw,
423 struct mlx5_flow_attr *attr,
10742efc 424 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 425 int *i)
426{
427 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
428 struct mlx5_fs_chains *chains = esw_chains(esw);
429 int err = 0;
430
10742efc 431 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 432 esw_src_port_rewrite_supported(esw))
10742efc
VB		 433 attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE;
434
f94d6389
CM		 435 if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) {
436 esw_setup_sampler_dest(dest, flow_act, esw_attr, *i);
437 (*i)++;
438 } else if (attr->dest_ft) {
a508728a 439 esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);
9e51c0a6
VB		 440 (*i)++;
441 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
442 esw_setup_slow_path_dest(dest, flow_act, chains, *i);
443 (*i)++;
444 } else if (attr->dest_chain) {
445 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
446 1, 0, *i);
447 (*i)++;
a508728a
VB		 448 } else if (esw_is_indir_table(esw, attr)) {
449 err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i);
10742efc
VB		 450 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
451 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 452 } else {
453 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
454 }
455
456 return err;
457}
458
459static void
460esw_cleanup_dests(struct mlx5_eswitch *esw,
461 struct mlx5_flow_attr *attr)
462{
10742efc 463 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 464 struct mlx5_fs_chains *chains = esw_chains(esw);
465
a508728a
VB		 466 if (attr->dest_ft) {
467 esw_cleanup_decap_indir(esw, attr);
468 } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
10742efc
VB		 469 if (attr->dest_chain)
470 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 471 else if (esw_is_indir_table(esw, attr))
472 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 473 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
474 esw_cleanup_chain_src_port_rewrite(esw, attr);
475 }
9e51c0a6
VB		 476}
477
74491de9 478struct mlx5_flow_handle *
3d80d1a2
OG		 479mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
480 struct mlx5_flow_spec *spec,
c620b772 481 struct mlx5_flow_attr *attr)
3d80d1a2 482{
592d3651 483 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 484 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 485 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 486 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 487 bool split = !!(esw_attr->split_count);
488 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 489 struct mlx5_flow_handle *rule;
e52c2802 490 struct mlx5_flow_table *fdb;
9e51c0a6 491 int i = 0;
3d80d1a2 492
f6455de0 493 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 494 return ERR_PTR(-EOPNOTSUPP);
495
6acfbf38
OG		 496 flow_act.action = attr->action;
497 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 498 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 499 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
500 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
501 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 502 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
503 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
504 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 505 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 506 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
507 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
508 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 509 }
6acfbf38 510 }
776b12b6 511
10742efc
VB		 512 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
513
66958ed9 514 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 515 int err;
516
10742efc 517 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 518 if (err) {
519 rule = ERR_PTR(err);
520 goto err_create_goto_table;
56e858df 521 }
e37a79e5 522 }
14e6b038 523
c620b772
AL		 524 if (esw_attr->decap_pkt_reformat)
525 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 526
66958ed9 527 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 528 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 529 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 530 i++;
3d80d1a2
OG		 531 }
532
93b3586e 533 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 534 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 535 if (attr->inner_match_level != MLX5_MATCH_NONE)
536 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 537
aa24670e 538 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 539 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 540
f94d6389
CM		 541 /* esw_attr->sample is allocated only when there is a sample action */
542 if (esw_attr->sample && esw_attr->sample->sample_default_tbl) {
543 fdb = esw_attr->sample->sample_default_tbl;
544 } else if (split) {
c620b772
AL		 545 fwd_attr.chain = attr->chain;
546 fwd_attr.prio = attr->prio;
547 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 548 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 549
0a9e2307 550 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 551 } else {
d18296ff 552 if (attr->chain || attr->prio)
ae430332
AL		 553 fdb = mlx5_chains_get_table(chains, attr->chain,
554 attr->prio, 0);
d18296ff 555 else
c620b772 556 fdb = attr->ft;
6fb0701a
PB		 557
558 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
a508728a 559 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 560 esw_attr->in_mdev->priv.eswitch,
561 esw_attr->in_rep->vport);
96e32687 562 }
e52c2802
PB		 563 if (IS_ERR(fdb)) {
564 rule = ERR_CAST(fdb);
565 goto err_esw_get;
566 }
567
84be2fda 568 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 569 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 570 &flow_act, dest, i);
84be2fda 571 else
10caabda 572 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 573 if (IS_ERR(rule))
e52c2802 574 goto err_add_rule;
375f51e2 575 else
525e84be 576 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 577
e52c2802
PB		 578 return rule;
579
580err_add_rule:
96e32687 581 if (split)
0a9e2307 582 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 583 else if (attr->chain || attr->prio)
ae430332 584 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 585err_esw_get:
9e51c0a6 586 esw_cleanup_dests(esw, attr);
e52c2802 587err_create_goto_table:
aa0cbbae 588 return rule;
3d80d1a2
OG		 589}
590
e4ad91f2
CM		 591struct mlx5_flow_handle *
592mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
593 struct mlx5_flow_spec *spec,
c620b772 594 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 595{
596 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 597 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 598 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 599 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 600 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 601 struct mlx5_flow_table *fast_fdb;
602 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 603 struct mlx5_flow_handle *rule;
10742efc 604 int i, err = 0;
e4ad91f2 605
ae430332 606 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 607 if (IS_ERR(fast_fdb)) {
608 rule = ERR_CAST(fast_fdb);
609 goto err_get_fast;
610 }
611
c620b772
AL		 612 fwd_attr.chain = attr->chain;
613 fwd_attr.prio = attr->prio;
614 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 615 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 616 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 617 if (IS_ERR(fwd_fdb)) {
618 rule = ERR_CAST(fwd_fdb);
619 goto err_get_fwd;
620 }
621
e4ad91f2 622 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 623 for (i = 0; i < esw_attr->split_count; i++) {
a508728a
VB		 624 if (esw_is_indir_table(esw, attr))
625 err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i);
626 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
10742efc
VB		 627 err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr,
628 &i);
629 else
630 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
631
632 if (err) {
633 rule = ERR_PTR(err);
634 goto err_chain_src_rewrite;
635 }
636 }
e4ad91f2 637 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 638 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 639 i++;
640
a508728a 641 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 642 esw_attr->in_mdev->priv.eswitch,
643 esw_attr->in_rep->vport);
e4ad91f2 644
93b3586e 645 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 646 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 647
278d51f2 648 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 649 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 650
10742efc
VB		 651 if (IS_ERR(rule)) {
652 i = esw_attr->split_count;
653 goto err_chain_src_rewrite;
654 }
e4ad91f2 655
525e84be 656 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 657
658 return rule;
10742efc
VB		 659err_chain_src_rewrite:
660 esw_put_dest_tables_loop(esw, attr, 0, i);
0a9e2307 661 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 662err_get_fwd:
ae430332 663 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 664err_get_fast:
e4ad91f2
CM		 665 return rule;
666}
667
e52c2802
PB		 668static void
669__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
670 struct mlx5_flow_handle *rule,
c620b772 671 struct mlx5_flow_attr *attr,
e52c2802
PB		 672 bool fwd_rule)
673{
c620b772 674 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 675 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 676 bool split = (esw_attr->split_count > 0);
677 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 678 int i;
e52c2802
PB		 679
680 mlx5_del_flow_rules(rule);
10caabda 681
84be2fda 682 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 683 /* unref the term table */
684 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 685 if (esw_attr->dests[i].termtbl)
686 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 687 }
10caabda
OS		 688 }
689
525e84be 690 atomic64_dec(&esw->offloads.num_flows);
e52c2802 691
c620b772
AL		 692 if (fwd_rule || split) {
693 fwd_attr.chain = attr->chain;
694 fwd_attr.prio = attr->prio;
695 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 696 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 697 }
698
e52c2802 699 if (fwd_rule) {
0a9e2307 700 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 701 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
10742efc 702 esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count);
e52c2802 703 } else {
96e32687 704 if (split)
0a9e2307 705 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 706 else if (attr->chain || attr->prio)
ae430332 707 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 708 esw_cleanup_dests(esw, attr);
e52c2802
PB		 709 }
710}
711
d85cdccb
OG		 712void
713mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
714 struct mlx5_flow_handle *rule,
c620b772 715 struct mlx5_flow_attr *attr)
d85cdccb 716{
e52c2802 717 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 718}
719
48265006
OG		 720void
721mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
722 struct mlx5_flow_handle *rule,
c620b772 723 struct mlx5_flow_attr *attr)
48265006 724{
e52c2802 725 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 726}
727
f5f82476
OG		 728static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
729{
730 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 731 unsigned long i;
732 int err = 0;
f5f82476
OG		 733
734 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
47dd7e60 735 mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 736 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 737 continue;
738
739 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
740 if (err)
741 goto out;
742 }
743
744out:
745 return err;
746}
747
748static struct mlx5_eswitch_rep *
749esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
750{
751 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
752
753 in_rep = attr->in_rep;
df65a573 754 out_rep = attr->dests[0].rep;
f5f82476
OG		 755
756 if (push)
757 vport = in_rep;
758 else if (pop)
759 vport = out_rep;
760 else
761 vport = in_rep;
762
763 return vport;
764}
765
766static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
767 bool push, bool pop, bool fwd)
768{
769 struct mlx5_eswitch_rep *in_rep, *out_rep;
770
771 if ((push || pop) && !fwd)
772 goto out_notsupp;
773
774 in_rep = attr->in_rep;
df65a573 775 out_rep = attr->dests[0].rep;
f5f82476 776
b05af6aa 777 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 778 goto out_notsupp;
779
b05af6aa 780 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 781 goto out_notsupp;
782
783 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
784 if (!push && !pop && fwd)
b05af6aa 785 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 786 goto out_notsupp;
787
788 /* protects against (1) setting rules with different vlans to push and
789 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
790 */
1482bd3d 791 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 792 goto out_notsupp;
793
794 return 0;
795
796out_notsupp:
9eb78923 797 return -EOPNOTSUPP;
f5f82476
OG		 798}
799
800int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 801 struct mlx5_flow_attr *attr)
f5f82476
OG		 802{
803 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 804 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 805 struct mlx5_eswitch_rep *vport = NULL;
806 bool push, pop, fwd;
807 int err = 0;
808
6acfbf38 809 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 810 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 811 return 0;
812
f5f82476
OG		 813 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
814 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 815 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
816 !attr->dest_chain);
f5f82476 817
0e18134f
VB		 818 mutex_lock(&esw->state_lock);
819
c620b772 820 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 821 if (err)
0e18134f 822 goto unlock;
f5f82476 823
39ac237c 824 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 825
c620b772 826 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 827
828 if (!push && !pop && fwd) {
829 /* tracks VF --> wire rules without vlan push action */
c620b772 830 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 831 vport->vlan_refcount++;
39ac237c 832 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 833 }
834
0e18134f 835 goto unlock;
f5f82476
OG		 836 }
837
838 if (!push && !pop)
0e18134f 839 goto unlock;
f5f82476
OG		 840
841 if (!(offloads->vlan_push_pop_refcount)) {
842 /* it's the 1st vlan rule, apply global vlan pop policy */
843 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
844 if (err)
845 goto out;
846 }
847 offloads->vlan_push_pop_refcount++;
848
849 if (push) {
850 if (vport->vlan_refcount)
851 goto skip_set_push;
852
c620b772
AL		 853 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
854 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 855 if (err)
856 goto out;
c620b772 857 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 858skip_set_push:
859 vport->vlan_refcount++;
860 }
861out:
862 if (!err)
39ac237c 863 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 864unlock:
865 mutex_unlock(&esw->state_lock);
f5f82476
OG		 866 return err;
867}
868
869int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 870 struct mlx5_flow_attr *attr)
f5f82476
OG		 871{
872 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 873 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 874 struct mlx5_eswitch_rep *vport = NULL;
875 bool push, pop, fwd;
876 int err = 0;
877
6acfbf38 878 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 879 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 880 return 0;
881
39ac237c 882 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 883 return 0;
884
885 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
886 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
887 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
888
0e18134f
VB		 889 mutex_lock(&esw->state_lock);
890
c620b772 891 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 892
893 if (!push && !pop && fwd) {
894 /* tracks VF --> wire rules without vlan push action */
c620b772 895 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 896 vport->vlan_refcount--;
897
0e18134f 898 goto out;
f5f82476
OG		 899 }
900
901 if (push) {
902 vport->vlan_refcount--;
903 if (vport->vlan_refcount)
904 goto skip_unset_push;
905
906 vport->vlan = 0;
907 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
908 0, 0, SET_VLAN_STRIP);
909 if (err)
910 goto out;
911 }
912
913skip_unset_push:
914 offloads->vlan_push_pop_refcount--;
915 if (offloads->vlan_push_pop_refcount)
0e18134f 916 goto out;
f5f82476
OG		 917
918 /* no more vlan rules, stop global vlan pop policy */
919 err = esw_set_global_vlan_pop(esw, 0);
920
921out:
0e18134f 922 mutex_unlock(&esw->state_lock);
f5f82476
OG		 923 return err;
924}
925
f7a68945 926struct mlx5_flow_handle *
3a46f4fb 927mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
979bf468 928 struct mlx5_eswitch *from_esw,
3a46f4fb 929 struct mlx5_eswitch_rep *rep,
02f3afd9 930 u32 sqn)
ab22be9b 931{
66958ed9 932 struct mlx5_flow_act flow_act = {0};
4c5009c5 933 struct mlx5_flow_destination dest = {};
74491de9 934 struct mlx5_flow_handle *flow_rule;
c5bb1730 935 struct mlx5_flow_spec *spec;
ab22be9b
OG		 936 void *misc;
937
1b9a07ee 938 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 939 if (!spec) {
ab22be9b
OG		 940 flow_rule = ERR_PTR(-ENOMEM);
941 goto out;
942 }
943
c5bb1730 944 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 945 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a 946 /* source vport is the esw manager */
979bf468 947 MLX5_SET(fte_match_set_misc, misc, source_port, from_esw->manager_vport);
3a46f4fb 948 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a 949 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
979bf468 950 MLX5_CAP_GEN(from_esw->dev, vhca_id));
ab22be9b 951
c5bb1730 952 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 953 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
954 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3a46f4fb 955 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a
MB		 956 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
957 source_eswitch_owner_vhca_id);
ab22be9b 958
c5bb1730 959 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 960 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 961 dest.vport.num = rep->vport;
962 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
963 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 964 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 965
d0444254
AL		 966 if (rep->vport == MLX5_VPORT_UPLINK)
967 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
968
3a46f4fb 969 flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb,
39ac237c 970 spec, &flow_act, &dest, 1);
ab22be9b 971 if (IS_ERR(flow_rule))
3a46f4fb
MB		 972 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
973 PTR_ERR(flow_rule));
ab22be9b 974out:
c5bb1730 975 kvfree(spec);
ab22be9b
OG		 976 return flow_rule;
977}
57cbd893 978EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 979
159fe639
MB		 980void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
981{
982 mlx5_del_flow_rules(rule);
983}
984
8e404fef
VB		 985static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
986{
987 struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules;
47dd7e60 988 int i = 0, num_vfs = esw->esw_funcs.num_vfs;
8e404fef
VB		 989
990 if (!num_vfs || !flows)
991 return;
992
47dd7e60
PP		 993 for (i = 0; i < num_vfs; i++)
994 mlx5_del_flow_rules(flows[i]);
8e404fef
VB		 995
996 kvfree(flows);
997}
998
999static int
1000mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
1001{
8e404fef
VB		 1002 struct mlx5_flow_destination dest = {};
1003 struct mlx5_flow_act flow_act = {0};
6308a5f0 1004 int num_vfs, rule_idx = 0, err = 0;
8e404fef
VB		 1005 struct mlx5_flow_handle *flow_rule;
1006 struct mlx5_flow_handle **flows;
1007 struct mlx5_flow_spec *spec;
47dd7e60
PP		 1008 struct mlx5_vport *vport;
1009 unsigned long i;
6308a5f0 1010 u16 vport_num;
8e404fef
VB		 1011
1012 num_vfs = esw->esw_funcs.num_vfs;
1013 flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL);
1014 if (!flows)
1015 return -ENOMEM;
1016
1017 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1018 if (!spec) {
1019 err = -ENOMEM;
1020 goto alloc_err;
1021 }
1022
1023 MLX5_SET(fte_match_param, spec->match_criteria,
1024 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1025 MLX5_SET(fte_match_param, spec->match_criteria,
1026 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1027 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1028 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1029
1030 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1031 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1032 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1033
47dd7e60
PP		 1034 mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) {
1035 vport_num = vport->vport;
8e404fef
VB		 1036 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1037 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1038 dest.vport.num = vport_num;
1039
1040 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1041 spec, &flow_act, &dest, 1);
1042 if (IS_ERR(flow_rule)) {
1043 err = PTR_ERR(flow_rule);
1044 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n",
1045 rule_idx, PTR_ERR(flow_rule));
1046 goto rule_err;
1047 }
1048 flows[rule_idx++] = flow_rule;
1049 }
1050
1051 esw->fdb_table.offloads.send_to_vport_meta_rules = flows;
1052 kvfree(spec);
1053 return 0;
1054
1055rule_err:
1056 while (--rule_idx >= 0)
1057 mlx5_del_flow_rules(flows[rule_idx]);
1058 kvfree(spec);
1059alloc_err:
1060 kvfree(flows);
1061 return err;
1062}
1063
5b7cb745
PB		 1064static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1065{
1066 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1067 MLX5_FDB_TO_VPORT_REG_C_1;
1068}
1069
332bd3a5 1070static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 1071{
1072 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 1073 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1074 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 1075 u8 curr, wanted;
c1286050
JL		 1076 int err;
1077
5b7cb745
PB		 1078 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1079 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 1080 return 0;
c1286050 1081
e08a6832
LR		 1082 MLX5_SET(query_esw_vport_context_in, in, opcode,
1083 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1084 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 1085 if (err)
1086 return err;
1087
5b7cb745
PB		 1088 curr = MLX5_GET(query_esw_vport_context_out, out,
1089 esw_vport_context.fdb_to_vport_reg_c_id);
1090 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1091 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1092 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 1093
332bd3a5 1094 if (enable)
5b7cb745 1095 curr |= wanted;
332bd3a5 1096 else
5b7cb745 1097 curr &= ~wanted;
c1286050 1098
e08a6832 1099 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 1100 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 1101 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 1102 field_select.fdb_to_vport_reg_c_id, 1);
1103
e08a6832 1104 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 1105 if (!err) {
1106 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1107 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1108 else
1109 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1110 }
1111
1112 return err;
c1286050
JL		 1113}
1114
a5641cb5
JL		 1115static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1116 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1117 struct mlx5_flow_spec *spec,
1118 struct mlx5_flow_destination *dest)
1119{
a5641cb5 1120 void *misc;
ac004b83 1121
a5641cb5
JL		 1122 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1123 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1124 misc_parameters_2);
0f0d3827
PB		 1125 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1126 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1127
a5641cb5
JL		 1128 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1129 } else {
1130 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1131 misc_parameters);
ac004b83 1132
a5641cb5
JL		 1133 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1134 MLX5_CAP_GEN(peer_dev, vhca_id));
1135
1136 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1137
1138 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1139 misc_parameters);
1140 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1141 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1142 source_eswitch_owner_vhca_id);
1143 }
ac004b83
RD		 1144
1145 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1146 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1147 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1148 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1149}
1150
a5641cb5
JL		 1151static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1152 struct mlx5_eswitch *peer_esw,
1153 struct mlx5_flow_spec *spec,
1154 u16 vport)
1155{
1156 void *misc;
1157
1158 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1159 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1160 misc_parameters_2);
1161 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1162 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1163 vport));
1164 } else {
1165 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1166 misc_parameters);
1167 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1168 }
1169}
1170
ac004b83
RD		 1171static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1172 struct mlx5_core_dev *peer_dev)
1173{
1174 struct mlx5_flow_destination dest = {};
1175 struct mlx5_flow_act flow_act = {0};
1176 struct mlx5_flow_handle **flows;
ac004b83
RD		 1177 /* total vports is the same for both e-switches */
1178 int nvports = esw->total_vports;
47dd7e60
PP		 1179 struct mlx5_flow_handle *flow;
1180 struct mlx5_flow_spec *spec;
1181 struct mlx5_vport *vport;
1182 unsigned long i;
ac004b83 1183 void *misc;
47dd7e60 1184 int err;
ac004b83
RD		 1185
1186 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1187 if (!spec)
1188 return -ENOMEM;
1189
a5641cb5 1190 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 1191
1192 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
1193 if (!flows) {
1194 err = -ENOMEM;
1195 goto alloc_flows_err;
1196 }
1197
1198 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1199 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1200 misc_parameters);
1201
81cd229c 1202 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1203 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1204 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1205 spec, MLX5_VPORT_PF);
1206
81cd229c
BW		 1207 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1208 spec, &flow_act, &dest, 1);
1209 if (IS_ERR(flow)) {
1210 err = PTR_ERR(flow);
1211 goto add_pf_flow_err;
1212 }
47dd7e60 1213 flows[vport->index] = flow;
81cd229c
BW		 1214 }
1215
1216 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1217 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c
BW		 1218 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1219 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1220 spec, &flow_act, &dest, 1);
1221 if (IS_ERR(flow)) {
1222 err = PTR_ERR(flow);
1223 goto add_ecpf_flow_err;
1224 }
47dd7e60 1225 flows[vport->index] = flow;
81cd229c
BW		 1226 }
1227
47dd7e60 1228 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1229 esw_set_peer_miss_rule_source_port(esw,
1230 peer_dev->priv.eswitch,
47dd7e60 1231 spec, vport->vport);
a5641cb5 1232
ac004b83
RD		 1233 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1234 spec, &flow_act, &dest, 1);
1235 if (IS_ERR(flow)) {
1236 err = PTR_ERR(flow);
81cd229c 1237 goto add_vf_flow_err;
ac004b83 1238 }
47dd7e60 1239 flows[vport->index] = flow;
ac004b83
RD		 1240 }
1241
1242 esw->fdb_table.offloads.peer_miss_rules = flows;
1243
1244 kvfree(spec);
1245 return 0;
1246
81cd229c 1247add_vf_flow_err:
47dd7e60
PP		 1248 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1249 if (!flows[vport->index])
1250 continue;
1251 mlx5_del_flow_rules(flows[vport->index]);
1252 }
1253 if (mlx5_ecpf_vport_exists(esw->dev)) {
1254 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1255 mlx5_del_flow_rules(flows[vport->index]);
1256 }
81cd229c 1257add_ecpf_flow_err:
47dd7e60
PP		 1258 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1259 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1260 mlx5_del_flow_rules(flows[vport->index]);
1261 }
81cd229c
BW		 1262add_pf_flow_err:
1263 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1264 kvfree(flows);
1265alloc_flows_err:
1266 kvfree(spec);
1267 return err;
1268}
1269
1270static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1271{
1272 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1273 struct mlx5_vport *vport;
1274 unsigned long i;
ac004b83
RD		 1275
1276 flows = esw->fdb_table.offloads.peer_miss_rules;
1277
47dd7e60
PP		 1278 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1279 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1280
47dd7e60
PP		 1281 if (mlx5_ecpf_vport_exists(esw->dev)) {
1282 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1283 mlx5_del_flow_rules(flows[vport->index]);
1284 }
81cd229c 1285
47dd7e60
PP		 1286 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1287 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1288 mlx5_del_flow_rules(flows[vport->index]);
1289 }
ac004b83
RD		 1290 kvfree(flows);
1291}
1292
3aa33572
OG		 1293static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1294{
66958ed9 1295 struct mlx5_flow_act flow_act = {0};
4c5009c5 1296 struct mlx5_flow_destination dest = {};
74491de9 1297 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1298 struct mlx5_flow_spec *spec;
f80be543
MB		 1299 void *headers_c;
1300 void *headers_v;
3aa33572 1301 int err = 0;
f80be543
MB		 1302 u8 *dmac_c;
1303 u8 *dmac_v;
3aa33572 1304
1b9a07ee 1305 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1306 if (!spec) {
3aa33572
OG		 1307 err = -ENOMEM;
1308 goto out;
1309 }
1310
f80be543
MB		 1311 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1312 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1313 outer_headers);
1314 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1315 outer_headers.dmac_47_16);
1316 dmac_c[0] = 0x01;
1317
3aa33572 1318 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1319 dest.vport.num = esw->manager_vport;
66958ed9 1320 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1321
39ac237c
PB		 1322 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1323 spec, &flow_act, &dest, 1);
3aa33572
OG		 1324 if (IS_ERR(flow_rule)) {
1325 err = PTR_ERR(flow_rule);
f80be543 1326 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1327 goto out;
1328 }
1329
f80be543
MB		 1330 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1331
1332 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1333 outer_headers);
1334 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1335 outer_headers.dmac_47_16);
1336 dmac_v[0] = 0x01;
39ac237c
PB		 1337 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1338 spec, &flow_act, &dest, 1);
f80be543
MB		 1339 if (IS_ERR(flow_rule)) {
1340 err = PTR_ERR(flow_rule);
1341 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1342 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1343 goto out;
1344 }
1345
1346 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1347
3aa33572 1348out:
c5bb1730 1349 kvfree(spec);
3aa33572
OG		 1350 return err;
1351}
1352
11b717d6
PB		 1353struct mlx5_flow_handle *
1354esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1355{
1356 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1357 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1358 struct mlx5_flow_context *flow_context;
1359 struct mlx5_flow_handle *flow_rule;
1360 struct mlx5_flow_destination dest;
1361 struct mlx5_flow_spec *spec;
1362 void *misc;
1363
60acc105
PB		 1364 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1365 return ERR_PTR(-EOPNOTSUPP);
1366
9f4d9283 1367 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1368 if (!spec)
1369 return ERR_PTR(-ENOMEM);
1370
1371 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1372 misc_parameters_2);
1373 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1374 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1375 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1376 misc_parameters_2);
1377 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1378 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1379 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1380 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1381 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1382
1383 flow_context = &spec->flow_context;
1384 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1385 flow_context->flow_tag = tag;
1386 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1387 dest.ft = esw->offloads.ft_offloads;
1388
1389 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1390 kvfree(spec);
11b717d6
PB		 1391
1392 if (IS_ERR(flow_rule))
1393 esw_warn(esw->dev,
1394 "Failed to create restore rule for tag: %d, err(%d)\n",
1395 tag, (int)PTR_ERR(flow_rule));
1396
1397 return flow_rule;
1398}
1399
1967ce6e 1400#define MAX_PF_SQ 256
cd3d07e7 1401#define MAX_SQ_NVPORTS 32
1967ce6e 1402
a5641cb5
JL		 1403static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1404 u32 *flow_group_in)
1405{
1406 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1407 flow_group_in,
1408 match_criteria);
1409
1410 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1411 MLX5_SET(create_flow_group_in, flow_group_in,
1412 match_criteria_enable,
1413 MLX5_MATCH_MISC_PARAMETERS_2);
1414
0f0d3827
PB		 1415 MLX5_SET(fte_match_param, match_criteria,
1416 misc_parameters_2.metadata_reg_c_0,
1417 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1418 } else {
1419 MLX5_SET(create_flow_group_in, flow_group_in,
1420 match_criteria_enable,
1421 MLX5_MATCH_MISC_PARAMETERS);
1422
1423 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1424 misc_parameters.source_port);
1425 }
1426}
1427
ae430332 1428#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1429static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1430{
1431 struct mlx5_vport_tbl_attr attr;
1432 struct mlx5_vport *vport;
47dd7e60 1433 unsigned long i;
4c7f4028
CM		 1434
1435 attr.chain = 0;
1436 attr.prio = 1;
47dd7e60 1437 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1438 attr.vport = vport->vport;
c796bb7c 1439 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1440 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1441 }
1442}
1443
0a9e2307 1444static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1445{
1446 struct mlx5_vport_tbl_attr attr;
1447 struct mlx5_flow_table *fdb;
1448 struct mlx5_vport *vport;
47dd7e60 1449 unsigned long i;
4c7f4028
CM		 1450
1451 attr.chain = 0;
1452 attr.prio = 1;
47dd7e60 1453 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1454 attr.vport = vport->vport;
c796bb7c 1455 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1456 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1457 if (IS_ERR(fdb))
1458 goto out;
1459 }
1460 return 0;
1461
1462out:
0a9e2307 1463 esw_vport_tbl_put(esw);
4c7f4028
CM		 1464 return PTR_ERR(fdb);
1465}
1466
ae430332
AL		 1467#define fdb_modify_header_fwd_to_table_supported(esw) \
1468 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1469static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1470{
1471 struct mlx5_core_dev *dev = esw->dev;
1472
1473 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1474 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1475
1476 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1477 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1478 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1479 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1480 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1481 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1482 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1483 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1484 /* Disabled when ttl workaround is needed, e.g
1485 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1486 */
1487 esw_warn(dev,
1488 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1489 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1490 } else {
1491 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1492 esw_info(dev, "Supported tc chains and prios offload\n");
1493 }
1494
1495 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1496 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1497}
1498
1499static int
1500esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1501{
1502 struct mlx5_core_dev *dev = esw->dev;
1503 struct mlx5_flow_table *nf_ft, *ft;
1504 struct mlx5_chains_attr attr = {};
1505 struct mlx5_fs_chains *chains;
1506 u32 fdb_max;
1507 int err;
1508
1509 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1510
1511 esw_init_chains_offload_flags(esw, &attr.flags);
1512 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1513 attr.max_ft_sz = fdb_max;
1514 attr.max_grp_num = esw->params.large_group_num;
1515 attr.default_ft = miss_fdb;
c9355682 1516 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1517
1518 chains = mlx5_chains_create(dev, &attr);
1519 if (IS_ERR(chains)) {
1520 err = PTR_ERR(chains);
1521 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1522 return err;
1523 }
1524
1525 esw->fdb_table.offloads.esw_chains_priv = chains;
1526
1527 /* Create tc_end_ft which is the always created ft chain */
1528 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1529 1, 0);
1530 if (IS_ERR(nf_ft)) {
1531 err = PTR_ERR(nf_ft);
1532 goto nf_ft_err;
1533 }
1534
1535 /* Always open the root for fast path */
1536 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1537 if (IS_ERR(ft)) {
1538 err = PTR_ERR(ft);
1539 goto level_0_err;
1540 }
1541
1542 /* Open level 1 for split fdb rules now if prios isn't supported */
1543 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1544 err = esw_vport_tbl_get(esw);
ae430332
AL		 1545 if (err)
1546 goto level_1_err;
1547 }
1548
1549 mlx5_chains_set_end_ft(chains, nf_ft);
1550
1551 return 0;
1552
1553level_1_err:
1554 mlx5_chains_put_table(chains, 0, 1, 0);
1555level_0_err:
1556 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1557nf_ft_err:
1558 mlx5_chains_destroy(chains);
1559 esw->fdb_table.offloads.esw_chains_priv = NULL;
1560
1561 return err;
1562}
1563
1564static void
1565esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1566{
1567 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1568 esw_vport_tbl_put(esw);
ae430332
AL		 1569 mlx5_chains_put_table(chains, 0, 1, 0);
1570 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1571 mlx5_chains_destroy(chains);
1572}
1573
1574#else /* CONFIG_MLX5_CLS_ACT */
1575
1576static int
1577esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1578{ return 0; }
1579
1580static void
1581esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1582{}
1583
1584#endif
1585
0da3c12d 1586static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1587{
1588 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1589 struct mlx5_flow_table_attr ft_attr = {};
8e404fef 1590 int num_vfs, table_size, ix, err = 0;
1967ce6e
OG		 1591 struct mlx5_core_dev *dev = esw->dev;
1592 struct mlx5_flow_namespace *root_ns;
1593 struct mlx5_flow_table *fdb = NULL;
39ac237c 1594 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1595 struct mlx5_flow_group *g;
1596 void *match_criteria;
f80be543 1597 u8 *dmac;
1967ce6e
OG		 1598
1599 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1600
1b9a07ee 1601 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1602 if (!flow_group_in)
1603 return -ENOMEM;
1604
1605 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1606 if (!root_ns) {
1607 esw_warn(dev, "Failed to get FDB flow namespace\n");
1608 err = -EOPNOTSUPP;
1609 goto ns_err;
1610 }
8463daf1
MG		 1611 esw->fdb_table.offloads.ns = root_ns;
1612 err = mlx5_flow_namespace_set_mode(root_ns,
1613 esw->dev->priv.steering->mode);
1614 if (err) {
1615 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1616 goto ns_err;
1617 }
1967ce6e 1618
0da3c12d 1619 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
8e404fef 1620 MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs;
b3ba5149 1621
e52c2802
PB		 1622 /* create the slow path fdb with encap set, so further table instances
1623 * can be created at run time while VFs are probed if the FW allows that.
1624 */
1625 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1626 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1627 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1628
1629 ft_attr.flags = flags;
b3ba5149
ES		 1630 ft_attr.max_fte = table_size;
1631 ft_attr.prio = FDB_SLOW_PATH;
1632
1633 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1634 if (IS_ERR(fdb)) {
1635 err = PTR_ERR(fdb);
1636 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1637 goto slow_fdb_err;
1638 }
52fff327 1639 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1640
ec3be887
VB		 1641 /* Create empty TC-miss managed table. This allows plugging in following
1642 * priorities without directly exposing their level 0 table to
1643 * eswitch_offloads and passing it as miss_fdb to following call to
1644 * esw_chains_create().
1645 */
1646 memset(&ft_attr, 0, sizeof(ft_attr));
1647 ft_attr.prio = FDB_TC_MISS;
1648 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1649 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1650 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1651 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1652 goto tc_miss_table_err;
1653 }
1654
1655 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
39ac237c 1656 if (err) {
ae430332 1657 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1658 goto fdb_chains_err;
e52c2802
PB		 1659 }
1660
69697b6e 1661 /* create send-to-vport group */
69697b6e
OG		 1662 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1663 MLX5_MATCH_MISC_PARAMETERS);
1664
1665 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1666
1667 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1668 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
7d97822a
MB		 1669 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1670 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1671 misc_parameters.source_eswitch_owner_vhca_id);
1672 MLX5_SET(create_flow_group_in, flow_group_in,
1673 source_eswitch_owner_vhca_id_valid, 1);
1674 }
69697b6e 1675
0da3c12d 1676 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1677 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1678 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1679
1680 g = mlx5_create_flow_group(fdb, flow_group_in);
1681 if (IS_ERR(g)) {
1682 err = PTR_ERR(g);
1683 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1684 goto send_vport_err;
1685 }
1686 esw->fdb_table.offloads.send_to_vport_grp = g;
1687
e929e3da
MD		 1688 if (esw_src_port_rewrite_supported(esw)) {
1689 /* meta send to vport */
1690 memset(flow_group_in, 0, inlen);
1691 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1692 MLX5_MATCH_MISC_PARAMETERS_2);
8e404fef 1693
e929e3da 1694 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
8e404fef 1695
e929e3da
MD		 1696 MLX5_SET(fte_match_param, match_criteria,
1697 misc_parameters_2.metadata_reg_c_0,
1698 mlx5_eswitch_get_vport_metadata_mask());
1699 MLX5_SET(fte_match_param, match_criteria,
1700 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1701
1702 num_vfs = esw->esw_funcs.num_vfs;
1703 if (num_vfs) {
1704 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1705 MLX5_SET(create_flow_group_in, flow_group_in,
1706 end_flow_index, ix + num_vfs - 1);
1707 ix += num_vfs;
1708
1709 g = mlx5_create_flow_group(fdb, flow_group_in);
1710 if (IS_ERR(g)) {
1711 err = PTR_ERR(g);
1712 esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n",
1713 err);
1714 goto send_vport_meta_err;
1715 }
1716 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1717
1718 err = mlx5_eswitch_add_send_to_vport_meta_rules(esw);
1719 if (err)
1720 goto meta_rule_err;
8e404fef 1721 }
8e404fef
VB		 1722 }
1723
6cec0229
MD		 1724 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1725 /* create peer esw miss group */
1726 memset(flow_group_in, 0, inlen);
ac004b83 1727
6cec0229 1728 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1729
6cec0229
MD		 1730 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1731 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1732 flow_group_in,
1733 match_criteria);
ac004b83 1734
6cec0229
MD		 1735 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1736 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1737
6cec0229
MD		 1738 MLX5_SET(create_flow_group_in, flow_group_in,
1739 source_eswitch_owner_vhca_id_valid, 1);
1740 }
ac004b83 1741
6cec0229
MD		 1742 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1743 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1744 ix + esw->total_vports - 1);
1745 ix += esw->total_vports;
ac004b83 1746
6cec0229
MD		 1747 g = mlx5_create_flow_group(fdb, flow_group_in);
1748 if (IS_ERR(g)) {
1749 err = PTR_ERR(g);
1750 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1751 goto peer_miss_err;
1752 }
1753 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1754 }
ac004b83 1755
69697b6e
OG		 1756 /* create miss group */
1757 memset(flow_group_in, 0, inlen);
f80be543
MB		 1758 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1759 MLX5_MATCH_OUTER_HEADERS);
1760 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1761 match_criteria);
1762 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1763 outer_headers.dmac_47_16);
1764 dmac[0] = 0x01;
69697b6e
OG		 1765
1766 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1767 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1768 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1769
1770 g = mlx5_create_flow_group(fdb, flow_group_in);
1771 if (IS_ERR(g)) {
1772 err = PTR_ERR(g);
1773 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1774 goto miss_err;
1775 }
1776 esw->fdb_table.offloads.miss_grp = g;
1777
3aa33572
OG		 1778 err = esw_add_fdb_miss_rule(esw);
1779 if (err)
1780 goto miss_rule_err;
1781
c88a026e 1782 kvfree(flow_group_in);
69697b6e
OG		 1783 return 0;
1784
3aa33572
OG		 1785miss_rule_err:
1786 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1787miss_err:
6cec0229
MD		 1788 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1789 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1790peer_miss_err:
8e404fef
VB		 1791 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1792meta_rule_err:
1793 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1794 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1795send_vport_meta_err:
69697b6e
OG		 1796 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1797send_vport_err:
ae430332 1798 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1799fdb_chains_err:
ec3be887
VB		 1800 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1801tc_miss_table_err:
52fff327 1802 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1803slow_fdb_err:
8463daf1
MG		 1804 /* Holds true only as long as DMFS is the default */
1805 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1806ns_err:
1807 kvfree(flow_group_in);
1808 return err;
1809}
1810
1967ce6e 1811static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1812{
e52c2802 1813 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1814 return;
1815
1967ce6e 1816 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1817 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1818 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
8e404fef 1819 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
69697b6e 1820 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1821 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1822 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1823 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1824 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1825 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1826
ae430332
AL		 1827 esw_chains_destroy(esw, esw_chains(esw));
1828
ec3be887 1829 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
52fff327 1830 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1831 /* Holds true only as long as DMFS is the default */
1832 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1833 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1834 atomic64_set(&esw->user_count, 0);
69697b6e 1835}
c116c6ee 1836
8d6bd3c3 1837static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1838{
b3ba5149 1839 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1840 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1841 struct mlx5_flow_table *ft_offloads;
1842 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1843 int err = 0;
1844
1845 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1846 if (!ns) {
1847 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1848 return -EOPNOTSUPP;
c116c6ee
OG		 1849 }
1850
8d6bd3c3 1851 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1852 ft_attr.prio = 1;
b3ba5149
ES		 1853
1854 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1855 if (IS_ERR(ft_offloads)) {
1856 err = PTR_ERR(ft_offloads);
1857 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1858 return err;
1859 }
1860
1861 esw->offloads.ft_offloads = ft_offloads;
1862 return 0;
1863}
1864
1865static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1866{
1867 struct mlx5_esw_offload *offloads = &esw->offloads;
1868
1869 mlx5_destroy_flow_table(offloads->ft_offloads);
1870}
fed9ce22 1871
8d6bd3c3 1872static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1873{
1874 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1875 struct mlx5_flow_group *g;
fed9ce22 1876 u32 *flow_group_in;
8d6bd3c3 1877 int nvports;
fed9ce22 1878 int err = 0;
fed9ce22 1879
8d6bd3c3 1880 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1881 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1882 if (!flow_group_in)
1883 return -ENOMEM;
1884
1885 /* create vport rx group */
a5641cb5 1886 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1887
1888 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1889 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1890
1891 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1892
1893 if (IS_ERR(g)) {
1894 err = PTR_ERR(g);
1895 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1896 goto out;
1897 }
1898
1899 esw->offloads.vport_rx_group = g;
1900out:
e574978a 1901 kvfree(flow_group_in);
fed9ce22
OG		 1902 return err;
1903}
1904
1905static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1906{
1907 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1908}
1909
74491de9 1910struct mlx5_flow_handle *
02f3afd9 1911mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1912 struct mlx5_flow_destination *dest)
fed9ce22 1913{
66958ed9 1914 struct mlx5_flow_act flow_act = {0};
74491de9 1915 struct mlx5_flow_handle *flow_rule;
c5bb1730 1916 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1917 void *misc;
1918
1b9a07ee 1919 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1920 if (!spec) {
fed9ce22
OG		 1921 flow_rule = ERR_PTR(-ENOMEM);
1922 goto out;
1923 }
1924
a5641cb5
JL		 1925 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1926 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1927 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1928 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1929
a5641cb5 1930 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1931 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1932 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1933
a5641cb5
JL		 1934 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1935 } else {
1936 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1937 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1938
1939 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1940 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1941
1942 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1943 }
fed9ce22 1944
66958ed9 1945 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1946 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1947 &flow_act, dest, 1);
fed9ce22
OG		 1948 if (IS_ERR(flow_rule)) {
1949 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1950 goto out;
1951 }
1952
1953out:
c5bb1730 1954 kvfree(spec);
fed9ce22
OG		 1955 return flow_rule;
1956}
feae9087 1957
47dd7e60 1958static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 1959{
1960 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1961 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 1962 struct mlx5_vport *vport;
1963 unsigned long i;
cc617ced
PP		 1964
1965 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1966 return -EOPNOTSUPP;
1967
1968 if (esw->mode == MLX5_ESWITCH_NONE)
1969 return -EOPNOTSUPP;
1970
1971 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1972 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1973 mlx5_mode = MLX5_INLINE_MODE_NONE;
1974 goto out;
1975 case MLX5_CAP_INLINE_MODE_L2:
1976 mlx5_mode = MLX5_INLINE_MODE_L2;
1977 goto out;
1978 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1979 goto query_vports;
1980 }
1981
1982query_vports:
1983 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 1984 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
1985 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 1986 if (prev_mlx5_mode != mlx5_mode)
1987 return -EINVAL;
1988 prev_mlx5_mode = mlx5_mode;
1989 }
1990
1991out:
1992 *mode = mlx5_mode;
1993 return 0;
e08a6832 1994}
bf3347c4 1995
11b717d6
PB		 1996static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1997{
1998 struct mlx5_esw_offload *offloads = &esw->offloads;
1999
60acc105
PB		 2000 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2001 return;
2002
6724e66b 2003 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 2004 mlx5_destroy_flow_group(offloads->restore_group);
2005 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2006}
2007
2008static int esw_create_restore_table(struct mlx5_eswitch *esw)
2009{
d65dbedf 2010 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 2011 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2012 struct mlx5_flow_table_attr ft_attr = {};
2013 struct mlx5_core_dev *dev = esw->dev;
2014 struct mlx5_flow_namespace *ns;
6724e66b 2015 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 2016 void *match_criteria, *misc;
2017 struct mlx5_flow_table *ft;
2018 struct mlx5_flow_group *g;
2019 u32 *flow_group_in;
2020 int err = 0;
2021
60acc105
PB		 2022 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2023 return 0;
2024
11b717d6
PB		 2025 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2026 if (!ns) {
2027 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2028 return -EOPNOTSUPP;
2029 }
2030
2031 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2032 if (!flow_group_in) {
2033 err = -ENOMEM;
2034 goto out_free;
2035 }
2036
a91d98a0 2037 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2038 ft = mlx5_create_flow_table(ns, &ft_attr);
2039 if (IS_ERR(ft)) {
2040 err = PTR_ERR(ft);
2041 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2042 err);
2043 goto out_free;
2044 }
2045
11b717d6
PB		 2046 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2047 match_criteria);
2048 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2049 misc_parameters_2);
2050
2051 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2052 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2053 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2054 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2055 ft_attr.max_fte - 1);
2056 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2057 MLX5_MATCH_MISC_PARAMETERS_2);
2058 g = mlx5_create_flow_group(ft, flow_group_in);
2059 if (IS_ERR(g)) {
2060 err = PTR_ERR(g);
2061 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2062 err);
2063 goto err_group;
2064 }
2065
6724e66b
PB		 2066 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2067 MLX5_SET(copy_action_in, modact, src_field,
2068 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2069 MLX5_SET(copy_action_in, modact, dst_field,
2070 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2071 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2072 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2073 modact);
2074 if (IS_ERR(mod_hdr)) {
e9864539 2075 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2076 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2077 err);
6724e66b
PB		 2078 goto err_mod_hdr;
2079 }
2080
11b717d6
PB		 2081 esw->offloads.ft_offloads_restore = ft;
2082 esw->offloads.restore_group = g;
6724e66b 2083 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2084
c8508713
RD		 2085 kvfree(flow_group_in);
2086
11b717d6
PB		 2087 return 0;
2088
6724e66b
PB		 2089err_mod_hdr:
2090 mlx5_destroy_flow_group(g);
11b717d6
PB		 2091err_group:
2092 mlx5_destroy_flow_table(ft);
2093out_free:
2094 kvfree(flow_group_in);
2095
2096 return err;
cc617ced
PP		 2097}
2098
db7ff19e
EB		 2099static int esw_offloads_start(struct mlx5_eswitch *esw,
2100 struct netlink_ext_ack *extack)
c930a3ad 2101{
062f4bf4 2102 int err, err1;
c930a3ad 2103
8e0aa4bc
PP		 2104 mlx5_eswitch_disable_locked(esw, false);
2105 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2106 esw->dev->priv.sriov.num_vfs);
6c419ba8 2107 if (err) {
8c98ee77
EB		 2108 NL_SET_ERR_MSG_MOD(extack,
2109 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 2110 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2111 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2112 if (err1) {
2113 NL_SET_ERR_MSG_MOD(extack,
2114 "Failed setting eswitch back to legacy");
2115 }
6c419ba8 2116 }
bffaa916
RD		 2117 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2118 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2119 &esw->offloads.inline_mode)) {
2120 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2121 NL_SET_ERR_MSG_MOD(extack,
2122 "Inline mode is different between vports");
bffaa916
RD		 2123 }
2124 }
c930a3ad
OG		 2125 return err;
2126}
2127
47dd7e60
PP		 2128static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2129 struct mlx5_eswitch_rep *rep,
2130 xa_mark_t mark)
e8d31c4d 2131{
47dd7e60
PP		 2132 bool mark_set;
2133
2134 /* Copy the mark from vport to its rep */
2135 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2136 if (mark_set)
2137 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
e8d31c4d
MB		 2138}
2139
47dd7e60 2140static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2141{
e8d31c4d 2142 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2143 int rep_type;
2144 int err;
e8d31c4d 2145
47dd7e60
PP		 2146 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2147 if (!rep)
e8d31c4d
MB		 2148 return -ENOMEM;
2149
47dd7e60
PP		 2150 rep->vport = vport->vport;
2151 rep->vport_index = vport->index;
2152 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2153 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2154
47dd7e60
PP		 2155 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2156 if (err)
2157 goto insert_err;
2158
2159 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2160 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2161 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2162 return 0;
2163
2164insert_err:
2165 kfree(rep);
2166 return err;
2167}
2168
2169static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2170 struct mlx5_eswitch_rep *rep)
2171{
2172 xa_erase(&esw->offloads.vport_reps, rep->vport);
2173 kfree(rep);
2174}
2175
2176void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2177{
2178 struct mlx5_eswitch_rep *rep;
2179 unsigned long i;
e8d31c4d 2180
47dd7e60
PP		 2181 mlx5_esw_for_each_rep(esw, i, rep)
2182 mlx5_esw_offloads_rep_cleanup(esw, rep);
2183 xa_destroy(&esw->offloads.vport_reps);
2184}
2185
2186int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2187{
2188 struct mlx5_vport *vport;
2189 unsigned long i;
2190 int err;
2191
2192 xa_init(&esw->offloads.vport_reps);
2193
2194 mlx5_esw_for_each_vport(esw, i, vport) {
2195 err = mlx5_esw_offloads_rep_init(esw, vport);
2196 if (err)
2197 goto err;
2198 }
e8d31c4d 2199 return 0;
47dd7e60
PP		 2200
2201err:
2202 esw_offloads_cleanup_reps(esw);
2203 return err;
e8d31c4d
MB		 2204}
2205
c9b99abc
BW		 2206static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2207 struct mlx5_eswitch_rep *rep, u8 rep_type)
2208{
8693115a 2209 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2210 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2211 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2212}
2213
d7f33a45
VP		 2214static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2215{
2216 struct mlx5_eswitch_rep *rep;
47dd7e60 2217 unsigned long i;
d7f33a45
VP		 2218
2219 mlx5_esw_for_each_sf_rep(esw, i, rep)
2220 __esw_offloads_unload_rep(esw, rep, rep_type);
2221}
2222
4110fc59 2223static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2224{
2225 struct mlx5_eswitch_rep *rep;
47dd7e60 2226 unsigned long i;
4110fc59 2227
d7f33a45
VP		 2228 __unload_reps_sf_vport(esw, rep_type);
2229
47dd7e60 2230 mlx5_esw_for_each_vf_rep(esw, i, rep)
4110fc59 2231 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 2232
81cd229c
BW		 2233 if (mlx5_ecpf_vport_exists(esw->dev)) {
2234 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2235 __esw_offloads_unload_rep(esw, rep, rep_type);
2236 }
2237
2238 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2239 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2240 __esw_offloads_unload_rep(esw, rep, rep_type);
2241 }
2242
879c8f84 2243 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 2244 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2245}
2246
d970812b 2247int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2248{
c2d7712c
BW		 2249 struct mlx5_eswitch_rep *rep;
2250 int rep_type;
a4b97ab4
MB		 2251 int err;
2252
c2d7712c
BW		 2253 rep = mlx5_eswitch_get_rep(esw, vport_num);
2254 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2255 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2256 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2257 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2258 if (err)
2259 goto err_reps;
2260 }
2261
2262 return 0;
a4b97ab4
MB		 2263
2264err_reps:
c2d7712c
BW		 2265 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2266 for (--rep_type; rep_type >= 0; rep_type--)
2267 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2268 return err;
2269}
2270
d970812b 2271void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2272{
2273 struct mlx5_eswitch_rep *rep;
2274 int rep_type;
2275
c2d7712c
BW		 2276 rep = mlx5_eswitch_get_rep(esw, vport_num);
2277 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2278 __esw_offloads_unload_rep(esw, rep, rep_type);
2279}
2280
38679b5a
PP		 2281int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2282{
2283 int err;
2284
2285 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2286 return 0;
2287
865d6d1c
RD		 2288 if (vport_num != MLX5_VPORT_UPLINK) {
2289 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2290 if (err)
2291 return err;
2292 }
c7eddc60 2293
38679b5a 2294 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2295 if (err)
2296 goto load_err;
2297 return err;
2298
2299load_err:
865d6d1c
RD		 2300 if (vport_num != MLX5_VPORT_UPLINK)
2301 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2302 return err;
2303}
2304
2305void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2306{
2307 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2308 return;
2309
2310 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c
RD		 2311
2312 if (vport_num != MLX5_VPORT_UPLINK)
2313 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2314}
2315
ac004b83
RD		 2316#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2317#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2318
2319static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2320 struct mlx5_eswitch *peer_esw)
2321{
ac004b83 2322
027d7166 2323 return esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
ac004b83
RD		 2324}
2325
2326static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
2327{
d956873f 2328#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2329 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2330#endif
ac004b83
RD		 2331 esw_del_fdb_peer_miss_rules(esw);
2332}
2333
8463daf1
MG		 2334static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2335 struct mlx5_eswitch *peer_esw,
2336 bool pair)
2337{
2338 struct mlx5_flow_root_namespace *peer_ns;
2339 struct mlx5_flow_root_namespace *ns;
2340 int err;
2341
2342 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2343 ns = esw->dev->priv.steering->fdb_root_ns;
2344
2345 if (pair) {
2346 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2347 if (err)
2348 return err;
2349
e53e6655 2350 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 2351 if (err) {
2352 mlx5_flow_namespace_set_peer(ns, NULL);
2353 return err;
2354 }
2355 } else {
2356 mlx5_flow_namespace_set_peer(ns, NULL);
2357 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2358 }
2359
2360 return 0;
2361}
2362
ac004b83
RD		 2363static int mlx5_esw_offloads_devcom_event(int event,
2364 void *my_data,
2365 void *event_data)
2366{
2367 struct mlx5_eswitch *esw = my_data;
ac004b83 2368 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 2369 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 2370 int err;
2371
2372 switch (event) {
2373 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 2374 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2375 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2376 break;
2377
8463daf1 2378 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2379 if (err)
2380 goto err_out;
8463daf1
MG		 2381 err = mlx5_esw_offloads_pair(esw, peer_esw);
2382 if (err)
2383 goto err_peer;
ac004b83
RD		 2384
2385 err = mlx5_esw_offloads_pair(peer_esw, esw);
2386 if (err)
2387 goto err_pair;
2388
2389 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2390 break;
2391
2392 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2393 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
2394 break;
2395
2396 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2397 mlx5_esw_offloads_unpair(peer_esw);
2398 mlx5_esw_offloads_unpair(esw);
8463daf1 2399 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2400 break;
2401 }
2402
2403 return 0;
2404
2405err_pair:
2406 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 2407err_peer:
2408 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2409err_out:
2410 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2411 event, err);
2412 return err;
2413}
2414
2415static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2416{
2417 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2418
04de7dda
RD		 2419 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2420 mutex_init(&esw->offloads.peer_mutex);
2421
ac004b83
RD		 2422 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2423 return;
2424
2425 mlx5_devcom_register_component(devcom,
2426 MLX5_DEVCOM_ESW_OFFLOADS,
2427 mlx5_esw_offloads_devcom_event,
2428 esw);
2429
2430 mlx5_devcom_send_event(devcom,
2431 MLX5_DEVCOM_ESW_OFFLOADS,
2432 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2433}
2434
2435static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2436{
2437 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2438
2439 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2440 return;
2441
2442 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2443 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2444
2445 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2446}
2447
7bf481d7 2448bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 2449{
2450 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2451 return false;
2452
2453 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2454 MLX5_FDB_TO_VPORT_REG_C_0))
2455 return false;
2456
2457 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2458 return false;
2459
2460 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2461 mlx5_ecpf_vport_exists(esw->dev))
2462 return false;
2463
2464 return true;
2465}
2466
133dcfc5
VP		 2467u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2468{
7cd7becd 2469 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2470 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2471 u32 pf_num;
133dcfc5
VP		 2472 int id;
2473
7cd7becd 2474 /* Only 4 bits of pf_num */
2475 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2476 if (pf_num > max_pf_num)
2477 return 0;
133dcfc5 2478
7cd7becd 2479 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2480 /* Use only non-zero vport_id (1-4095) for all PF's */
2481 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2482 if (id < 0)
2483 return 0;
2484 id = (pf_num << ESW_VPORT_BITS) | id;
2485 return id;
133dcfc5
VP		 2486}
2487
2488void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2489{
7cd7becd 2490 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2491
2492 /* Metadata contains only 12 bits of actual ida id */
2493 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2494}
2495
2496static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2497 struct mlx5_vport *vport)
2498{
133dcfc5
VP		 2499 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2500 vport->metadata = vport->default_metadata;
2501 return vport->metadata ? 0 : -ENOSPC;
2502}
2503
2504static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2505 struct mlx5_vport *vport)
2506{
406493a5 2507 if (!vport->default_metadata)
133dcfc5
VP		 2508 return;
2509
2510 WARN_ON(vport->metadata != vport->default_metadata);
2511 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2512}
2513
fc99c3d6
VP		 2514static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2515{
2516 struct mlx5_vport *vport;
47dd7e60 2517 unsigned long i;
fc99c3d6
VP		 2518
2519 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2520 return;
2521
47dd7e60 2522 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 2523 esw_offloads_vport_metadata_cleanup(esw, vport);
2524}
2525
2526static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2527{
2528 struct mlx5_vport *vport;
47dd7e60 2529 unsigned long i;
fc99c3d6 2530 int err;
fc99c3d6
VP		 2531
2532 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2533 return 0;
2534
47dd7e60 2535 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 2536 err = esw_offloads_vport_metadata_setup(esw, vport);
2537 if (err)
2538 goto metadata_err;
2539 }
2540
2541 return 0;
2542
2543metadata_err:
2544 esw_offloads_metadata_uninit(esw);
2545 return err;
2546}
2547
7bf481d7
PP		 2548int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable)
2549{
2550 int err = 0;
2551
2552 down_write(&esw->mode_lock);
2553 if (esw->mode != MLX5_ESWITCH_NONE) {
2554 err = -EBUSY;
2555 goto done;
2556 }
2557 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2558 err = -EOPNOTSUPP;
2559 goto done;
2560 }
2561 if (enable)
2562 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2563 else
2564 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2565done:
2566 up_write(&esw->mode_lock);
2567 return err;
2568}
2569
748da30b 2570int
89a0f1fb
PP		 2571esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2572 struct mlx5_vport *vport)
7445cfb1 2573{
7445cfb1
JL		 2574 int err;
2575
07bab950 2576 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2577 if (err)
fc99c3d6 2578 return err;
7445cfb1 2579
2c40db2f
PP		 2580 err = esw_acl_egress_ofld_setup(esw, vport);
2581 if (err)
2582 goto egress_err;
07bab950
VP		 2583
2584 return 0;
2585
2586egress_err:
2587 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2588 return err;
2589}
18486737 2590
748da30b 2591void
89a0f1fb
PP		 2592esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2593 struct mlx5_vport *vport)
2594{
ea651a86 2595 esw_acl_egress_ofld_cleanup(vport);
07bab950 2596 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2597}
7445cfb1 2598
748da30b 2599static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2600{
2601 struct mlx5_vport *vport;
18486737 2602
748da30b 2603 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2604 if (IS_ERR(vport))
2605 return PTR_ERR(vport);
2606
4e9a9ef7 2607 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2608}
2609
748da30b 2610static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2611{
786ef904 2612 struct mlx5_vport *vport;
7445cfb1 2613
748da30b 2614 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2615 if (IS_ERR(vport))
2616 return;
2617
748da30b 2618 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2619}
2620
062f4bf4 2621static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 2622{
34ca6535 2623 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 2624 int err;
2625
5c1d260e 2626 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2627 mutex_init(&esw->fdb_table.offloads.vports.lock);
2628 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 2629 atomic64_set(&esw->user_count, 0);
e52c2802 2630
34ca6535
VB		 2631 indir = mlx5_esw_indir_table_init();
2632 if (IS_ERR(indir)) {
2633 err = PTR_ERR(indir);
2634 goto create_indir_err;
2635 }
2636 esw->fdb_table.offloads.indir = indir;
2637
748da30b 2638 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2639 if (err)
f8d1edda 2640 goto create_acl_err;
18486737 2641
8d6bd3c3 2642 err = esw_create_offloads_table(esw);
c930a3ad 2643 if (err)
11b717d6 2644 goto create_offloads_err;
c930a3ad 2645
11b717d6 2646 err = esw_create_restore_table(esw);
c930a3ad 2647 if (err)
11b717d6
PB		 2648 goto create_restore_err;
2649
0da3c12d 2650 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2651 if (err)
2652 goto create_fdb_err;
c930a3ad 2653
8d6bd3c3 2654 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2655 if (err)
2656 goto create_fg_err;
2657
2658 return 0;
2659
2660create_fg_err:
1967ce6e 2661 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2662create_fdb_err:
11b717d6
PB		 2663 esw_destroy_restore_table(esw);
2664create_restore_err:
2665 esw_destroy_offloads_table(esw);
2666create_offloads_err:
748da30b 2667 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2668create_acl_err:
34ca6535
VB		 2669 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
2670create_indir_err:
f8d1edda 2671 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2672 return err;
2673}
2674
eca8cc38
BW		 2675static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2676{
2677 esw_destroy_vport_rx_group(esw);
eca8cc38 2678 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2679 esw_destroy_restore_table(esw);
2680 esw_destroy_offloads_table(esw);
748da30b 2681 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 2682 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 2683 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2684}
2685
7e736f9a
PP		 2686static void
2687esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2688{
5ccf2770 2689 bool host_pf_disabled;
7e736f9a 2690 u16 new_num_vfs;
a3888f33 2691
7e736f9a
PP		 2692 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2693 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2694 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2695 host_params_context.host_pf_disabled);
a3888f33 2696
7e736f9a
PP		 2697 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2698 return;
a3888f33
BW		 2699
2700 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2701 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2702 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2703 } else {
7e736f9a 2704 int err;
a3888f33 2705
23bb50cf
BW		 2706 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2707 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2708 if (err)
7e736f9a 2709 return;
a3888f33 2710 }
7e736f9a 2711 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2712}
2713
7e736f9a 2714static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2715{
7e736f9a
PP		 2716 struct mlx5_host_work *host_work;
2717 struct mlx5_eswitch *esw;
dd28087c 2718 const u32 *out;
ac35dcd6 2719
7e736f9a
PP		 2720 host_work = container_of(work, struct mlx5_host_work, work);
2721 esw = host_work->esw;
a3888f33 2722
dd28087c
PP		 2723 out = mlx5_esw_query_functions(esw->dev);
2724 if (IS_ERR(out))
7e736f9a 2725 goto out;
a3888f33 2726
7e736f9a 2727 esw_vfs_changed_event_handler(esw, out);
dd28087c 2728 kvfree(out);
a3888f33 2729out:
ac35dcd6
VP		 2730 kfree(host_work);
2731}
2732
16fff98a 2733int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2734{
cd56f929 2735 struct mlx5_esw_functions *esw_funcs;
a3888f33 2736 struct mlx5_host_work *host_work;
a3888f33
BW		 2737 struct mlx5_eswitch *esw;
2738
2739 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2740 if (!host_work)
2741 return NOTIFY_DONE;
2742
cd56f929
VP		 2743 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2744 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2745
2746 host_work->esw = esw;
2747
062f4bf4 2748 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2749 queue_work(esw->work_queue, &host_work->work);
2750
2751 return NOTIFY_OK;
2752}
2753
a53cf949
PP		 2754static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2755{
2756 const u32 *query_host_out;
2757
2758 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2759 return 0;
2760
2761 query_host_out = mlx5_esw_query_functions(esw->dev);
2762 if (IS_ERR(query_host_out))
2763 return PTR_ERR(query_host_out);
2764
2765 /* Mark non local controller with non zero controller number. */
2766 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2767 host_params_context.host_number);
2768 kvfree(query_host_out);
2769 return 0;
2770}
2771
f1b9acd3
PP		 2772bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
2773{
2774 /* Local controller is always valid */
2775 if (controller == 0)
2776 return true;
2777
2778 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2779 return false;
2780
2781 /* External host number starts with zero in device */
2782 return (controller == esw->offloads.host_number + 1);
2783}
2784
5896b972 2785int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2786{
c9355682 2787 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 2788 struct mlx5_vport *vport;
47dd7e60 2789 unsigned long i;
2198b932 2790 u64 mapping_id;
47dd7e60 2791 int err;
eca8cc38 2792
9a64144d
MG		 2793 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2794 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2795 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2796 else
2797 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2798
2bb72e7e 2799 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2800 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2801
a53cf949
PP		 2802 err = mlx5_esw_host_number_init(esw);
2803 if (err)
cd1ef966 2804 goto err_metadata;
a53cf949 2805
fc99c3d6
VP		 2806 err = esw_offloads_metadata_init(esw);
2807 if (err)
2808 goto err_metadata;
2809
332bd3a5
PP		 2810 err = esw_set_passing_vport_metadata(esw, true);
2811 if (err)
2812 goto err_vport_metadata;
c1286050 2813
2198b932
RD		 2814 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
2815
2816 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
2817 sizeof(struct mlx5_mapped_obj),
2818 ESW_REG_C0_USER_DATA_METADATA_MASK,
2819 true);
2820
c9355682
CM		 2821 if (IS_ERR(reg_c0_obj_pool)) {
2822 err = PTR_ERR(reg_c0_obj_pool);
2823 goto err_pool;
2824 }
2825 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
2826
7983a675
PB		 2827 err = esw_offloads_steering_init(esw);
2828 if (err)
2829 goto err_steering_init;
2830
3b83b6c2
DL		 2831 /* Representor will control the vport link state */
2832 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2833 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2834
c2d7712c
BW		 2835 /* Uplink vport rep must load first. */
2836 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2837 if (err)
c2d7712c 2838 goto err_uplink;
c1286050 2839
c2d7712c 2840 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2841 if (err)
c2d7712c 2842 goto err_vports;
eca8cc38
BW		 2843
2844 esw_offloads_devcom_init(esw);
a3888f33 2845
eca8cc38
BW		 2846 return 0;
2847
925a6acc 2848err_vports:
c2d7712c
BW		 2849 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2850err_uplink:
7983a675 2851 esw_offloads_steering_cleanup(esw);
79949985 2852err_steering_init:
c9355682
CM		 2853 mapping_destroy(reg_c0_obj_pool);
2854err_pool:
79949985 2855 esw_set_passing_vport_metadata(esw, false);
7983a675 2856err_vport_metadata:
fc99c3d6
VP		 2857 esw_offloads_metadata_uninit(esw);
2858err_metadata:
8463daf1 2859 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2860 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2861 return err;
2862}
2863
db7ff19e
EB		 2864static int esw_offloads_stop(struct mlx5_eswitch *esw,
2865 struct netlink_ext_ack *extack)
c930a3ad 2866{
062f4bf4 2867 int err, err1;
c930a3ad 2868
8e0aa4bc
PP		 2869 mlx5_eswitch_disable_locked(esw, false);
2870 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2871 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2872 if (err) {
8c98ee77 2873 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2874 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2875 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2876 if (err1) {
2877 NL_SET_ERR_MSG_MOD(extack,
2878 "Failed setting eswitch back to offloads");
2879 }
6c419ba8 2880 }
c930a3ad
OG		 2881
2882 return err;
2883}
2884
5896b972 2885void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2886{
ac004b83 2887 esw_offloads_devcom_cleanup(esw);
5896b972 2888 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2889 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2890 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2891 esw_offloads_steering_cleanup(esw);
c9355682 2892 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 2893 esw_offloads_metadata_uninit(esw);
8463daf1 2894 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2895 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2896 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2897}
2898
ef78618b 2899static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2900{
2901 switch (mode) {
2902 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2903 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2904 break;
2905 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2906 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2907 break;
2908 default:
2909 return -EINVAL;
2910 }
2911
2912 return 0;
2913}
2914
ef78618b
OG		 2915static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2916{
2917 switch (mlx5_mode) {
f6455de0 2918 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2919 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2920 break;
f6455de0 2921 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2922 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2923 break;
2924 default:
2925 return -EINVAL;
2926 }
2927
2928 return 0;
2929}
2930
bffaa916
RD		 2931static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2932{
2933 switch (mode) {
2934 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2935 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2936 break;
2937 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2938 *mlx5_mode = MLX5_INLINE_MODE_L2;
2939 break;
2940 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2941 *mlx5_mode = MLX5_INLINE_MODE_IP;
2942 break;
2943 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2944 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2945 break;
2946 default:
2947 return -EINVAL;
2948 }
2949
2950 return 0;
2951}
2952
2953static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2954{
2955 switch (mlx5_mode) {
2956 case MLX5_INLINE_MODE_NONE:
2957 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2958 break;
2959 case MLX5_INLINE_MODE_L2:
2960 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2961 break;
2962 case MLX5_INLINE_MODE_IP:
2963 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2964 break;
2965 case MLX5_INLINE_MODE_TCP_UDP:
2966 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2967 break;
2968 default:
2969 return -EINVAL;
2970 }
2971
2972 return 0;
2973}
2974
ae24432c
PP		 2975static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2976{
2977 /* devlink commands in NONE eswitch mode are currently supported only
2978 * on ECPF.
2979 */
2980 return (esw->mode == MLX5_ESWITCH_NONE &&
2981 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2982}
2983
db7ff19e
EB		 2984int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2985 struct netlink_ext_ack *extack)
9d1cef19 2986{
9d1cef19 2987 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2988 struct mlx5_eswitch *esw;
ea2128fd 2989 int err = 0;
9d1cef19 2990
bd939753
PP		 2991 esw = mlx5_devlink_eswitch_get(devlink);
2992 if (IS_ERR(esw))
2993 return PTR_ERR(esw);
9d1cef19 2994
ef78618b 2995 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2996 return -EINVAL;
2997
7dc84de9
RD		 2998 err = mlx5_esw_try_lock(esw);
2999 if (err < 0) {
3000 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
3001 return err;
3002 }
3003 cur_mlx5_mode = err;
3004 err = 0;
3005
c930a3ad 3006 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 3007 goto unlock;
c930a3ad
OG		 3008
3009 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 3010 err = esw_offloads_start(esw, extack);
c930a3ad 3011 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 3012 err = esw_offloads_stop(esw, extack);
c930a3ad 3013 else
8e0aa4bc
PP		 3014 err = -EINVAL;
3015
3016unlock:
7dc84de9 3017 mlx5_esw_unlock(esw);
8e0aa4bc 3018 return err;
feae9087
OG		 3019}
3020
3021int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3022{
bd939753 3023 struct mlx5_eswitch *esw;
9d1cef19 3024 int err;
c930a3ad 3025
bd939753
PP		 3026 esw = mlx5_devlink_eswitch_get(devlink);
3027 if (IS_ERR(esw))
3028 return PTR_ERR(esw);
c930a3ad 3029
c55479d0 3030 down_write(&esw->mode_lock);
bd939753 3031 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 3032 if (err)
8e0aa4bc 3033 goto unlock;
ae24432c 3034
8e0aa4bc
PP		 3035 err = esw_mode_to_devlink(esw->mode, mode);
3036unlock:
c55479d0 3037 up_write(&esw->mode_lock);
8e0aa4bc 3038 return err;
feae9087 3039}
127ea380 3040
47dd7e60
PP		 3041static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3042 struct netlink_ext_ack *extack)
3043{
3044 struct mlx5_core_dev *dev = esw->dev;
3045 struct mlx5_vport *vport;
3046 u16 err_vport_num = 0;
3047 unsigned long i;
3048 int err = 0;
3049
3050 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3051 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3052 if (err) {
3053 err_vport_num = vport->vport;
3054 NL_SET_ERR_MSG_MOD(extack,
3055 "Failed to set min inline on vport");
3056 goto revert_inline_mode;
3057 }
3058 }
3059 return 0;
3060
3061revert_inline_mode:
3062 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3063 if (vport->vport == err_vport_num)
3064 break;
3065 mlx5_modify_nic_vport_min_inline(dev,
3066 vport->vport,
3067 esw->offloads.inline_mode);
3068 }
3069 return err;
3070}
3071
db7ff19e
EB		 3072int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3073 struct netlink_ext_ack *extack)
bffaa916
RD		 3074{
3075 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3076 struct mlx5_eswitch *esw;
bffaa916 3077 u8 mlx5_mode;
47dd7e60 3078 int err;
bffaa916 3079
bd939753
PP		 3080 esw = mlx5_devlink_eswitch_get(devlink);
3081 if (IS_ERR(esw))
3082 return PTR_ERR(esw);
bffaa916 3083
c55479d0 3084 down_write(&esw->mode_lock);
ae24432c
PP		 3085 err = eswitch_devlink_esw_mode_check(esw);
3086 if (err)
8e0aa4bc 3087 goto out;
ae24432c 3088
c415f704
OG		 3089 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3090 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3091 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 3092 goto out;
c8b838d1 3093 fallthrough;
c415f704 3094 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3095 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3096 err = -EOPNOTSUPP;
3097 goto out;
c415f704
OG		 3098 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3099 break;
3100 }
bffaa916 3101
525e84be 3102 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3103 NL_SET_ERR_MSG_MOD(extack,
3104 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3105 err = -EOPNOTSUPP;
3106 goto out;
375f51e2
RD		 3107 }
3108
bffaa916
RD		 3109 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3110 if (err)
3111 goto out;
3112
47dd7e60
PP		 3113 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3114 if (err)
3115 goto out;
bffaa916
RD		 3116
3117 esw->offloads.inline_mode = mlx5_mode;
c55479d0 3118 up_write(&esw->mode_lock);
bffaa916
RD		 3119 return 0;
3120
bffaa916 3121out:
c55479d0 3122 up_write(&esw->mode_lock);
bffaa916
RD		 3123 return err;
3124}
3125
3126int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3127{
bd939753 3128 struct mlx5_eswitch *esw;
9d1cef19 3129 int err;
bffaa916 3130
bd939753
PP		 3131 esw = mlx5_devlink_eswitch_get(devlink);
3132 if (IS_ERR(esw))
3133 return PTR_ERR(esw);
bffaa916 3134
c55479d0 3135 down_write(&esw->mode_lock);
ae24432c
PP		 3136 err = eswitch_devlink_esw_mode_check(esw);
3137 if (err)
8e0aa4bc 3138 goto unlock;
ae24432c 3139
8e0aa4bc
PP		 3140 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3141unlock:
c55479d0 3142 up_write(&esw->mode_lock);
8e0aa4bc 3143 return err;
bffaa916
RD		 3144}
3145
98fdbea5
LR		 3146int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3147 enum devlink_eswitch_encap_mode encap,
db7ff19e 3148 struct netlink_ext_ack *extack)
7768d197
RD		 3149{
3150 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3151 struct mlx5_eswitch *esw;
7768d197
RD		 3152 int err;
3153
bd939753
PP		 3154 esw = mlx5_devlink_eswitch_get(devlink);
3155 if (IS_ERR(esw))
3156 return PTR_ERR(esw);
7768d197 3157
c55479d0 3158 down_write(&esw->mode_lock);
ae24432c
PP		 3159 err = eswitch_devlink_esw_mode_check(esw);
3160 if (err)
8e0aa4bc 3161 goto unlock;
ae24432c 3162
7768d197 3163 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3164 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3165 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3166 err = -EOPNOTSUPP;
3167 goto unlock;
3168 }
7768d197 3169
8e0aa4bc
PP		 3170 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3171 err = -EOPNOTSUPP;
3172 goto unlock;
3173 }
7768d197 3174
f6455de0 3175 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3176 esw->offloads.encap = encap;
8e0aa4bc 3177 goto unlock;
7768d197
RD		 3178 }
3179
3180 if (esw->offloads.encap == encap)
8e0aa4bc 3181 goto unlock;
7768d197 3182
525e84be 3183 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3184 NL_SET_ERR_MSG_MOD(extack,
3185 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3186 err = -EOPNOTSUPP;
3187 goto unlock;
7768d197
RD		 3188 }
3189
e52c2802 3190 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3191
3192 esw->offloads.encap = encap;
e52c2802 3193
0da3c12d 3194 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3195
7768d197 3196 if (err) {
8c98ee77
EB		 3197 NL_SET_ERR_MSG_MOD(extack,
3198 "Failed re-creating fast FDB table");
7768d197 3199 esw->offloads.encap = !encap;
0da3c12d 3200 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3201 }
e52c2802 3202
8e0aa4bc 3203unlock:
c55479d0 3204 up_write(&esw->mode_lock);
7768d197
RD		 3205 return err;
3206}
3207
98fdbea5
LR		 3208int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3209 enum devlink_eswitch_encap_mode *encap)
7768d197 3210{
bd939753 3211 struct mlx5_eswitch *esw;
9d1cef19 3212 int err;
7768d197 3213
bd939753
PP		 3214 esw = mlx5_devlink_eswitch_get(devlink);
3215 if (IS_ERR(esw))
3216 return PTR_ERR(esw);
3217
7768d197 3218
c55479d0 3219 down_write(&esw->mode_lock);
ae24432c
PP		 3220 err = eswitch_devlink_esw_mode_check(esw);
3221 if (err)
8e0aa4bc 3222 goto unlock;
ae24432c 3223
7768d197 3224 *encap = esw->offloads.encap;
8e0aa4bc 3225unlock:
c55479d0 3226 up_write(&esw->mode_lock);
7768d197
RD		 3227 return 0;
3228}
3229
c2d7712c
BW		 3230static bool
3231mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3232{
3233 /* Currently, only ECPF based device has representor for host PF. */
3234 if (vport_num == MLX5_VPORT_PF &&
3235 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3236 return false;
3237
3238 if (vport_num == MLX5_VPORT_ECPF &&
3239 !mlx5_ecpf_vport_exists(esw->dev))
3240 return false;
3241
3242 return true;
3243}
3244
f8e8fa02 3245void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 3246 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 3247 u8 rep_type)
127ea380 3248{
8693115a 3249 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 3250 struct mlx5_eswitch_rep *rep;
47dd7e60 3251 unsigned long i;
9deb2241 3252
8693115a 3253 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 3254 mlx5_esw_for_each_rep(esw, i, rep) {
3255 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 3256 rep->esw = esw;
c2d7712c
BW		 3257 rep_data = &rep->rep_data[rep_type];
3258 atomic_set(&rep_data->state, REP_REGISTERED);
3259 }
f8e8fa02 3260 }
127ea380 3261}
f8e8fa02 3262EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 3263
f8e8fa02 3264void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 3265{
cb67b832 3266 struct mlx5_eswitch_rep *rep;
47dd7e60 3267 unsigned long i;
cb67b832 3268
f6455de0 3269 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 3270 __unload_reps_all_vport(esw, rep_type);
127ea380 3271
47dd7e60 3272 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 3273 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 3274}
f8e8fa02 3275EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 3276
a4b97ab4 3277void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 3278{
726293f1
HHZ		 3279 struct mlx5_eswitch_rep *rep;
3280
879c8f84 3281 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 3282 return rep->rep_data[rep_type].priv;
726293f1 3283}
22215908
MB		 3284
3285void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 3286 u16 vport,
22215908
MB		 3287 u8 rep_type)
3288{
22215908
MB		 3289 struct mlx5_eswitch_rep *rep;
3290
879c8f84 3291 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 3292
8693115a
PP		 3293 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3294 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3295 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 3296 return NULL;
3297}
57cbd893 3298EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 3299
3300void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3301{
879c8f84 3302 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 3303}
57cbd893
MB		 3304EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3305
3306struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 3307 u16 vport)
57cbd893 3308{
879c8f84 3309 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 3310}
3311EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 3312
5b7cb745
PB		 3313bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3314{
3315 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3316}
3317EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3318
7445cfb1
JL		 3319bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3320{
3321 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3322}
3323EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3324
0f0d3827 3325u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 3326 u16 vport_num)
3327{
133dcfc5 3328 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 3329
133dcfc5
VP		 3330 if (WARN_ON_ONCE(IS_ERR(vport)))
3331 return 0;
0f0d3827 3332
133dcfc5 3333 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 3334}
3335EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 3336
3337int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 3338 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 3339{
3340 int err;
3341
3342 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3343 if (err)
3344 return err;
3345
f1b9acd3 3346 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 3347 if (err)
3348 goto devlink_err;
3349
3350 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3351 if (err)
3352 goto rep_err;
3353 return 0;
3354
3355rep_err:
3356 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3357devlink_err:
3358 mlx5_esw_vport_disable(esw, vport_num);
3359 return err;
3360}
3361
3362void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3363{
3364 mlx5_esw_offloads_rep_unload(esw, vport_num);
3365 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3366 mlx5_esw_vport_disable(esw, vport_num);
3367}
84ae9c1f
VB		 3368
3369static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3370{
3371 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3372 void *query_ctx;
3373 void *hca_caps;
3374 int err;
3375
3376 *vhca_id = 0;
3377 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3378 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3379 return -EPERM;
3380
3381 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3382 if (!query_ctx)
3383 return -ENOMEM;
3384
3385 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx);
3386 if (err)
3387 goto out_free;
3388
3389 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3390 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3391
3392out_free:
3393 kfree(query_ctx);
3394 return err;
3395}
3396
3397int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3398{
3399 u16 *old_entry, *vhca_map_entry, vhca_id;
3400 int err;
3401
3402 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3403 if (err) {
3404 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3405 vport_num, err);
3406 return err;
3407 }
3408
3409 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3410 if (!vhca_map_entry)
3411 return -ENOMEM;
3412
3413 *vhca_map_entry = vport_num;
3414 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3415 if (xa_is_err(old_entry)) {
3416 kfree(vhca_map_entry);
3417 return xa_err(old_entry);
3418 }
3419 kfree(old_entry);
3420 return 0;
3421}
3422
3423void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3424{
3425 u16 *vhca_map_entry, vhca_id;
3426 int err;
3427
3428 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3429 if (err)
3430 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3431 vport_num, err);
3432
3433 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3434 kfree(vhca_map_entry);
3435}
3436
3437int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3438{
3439 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3440
3441 if (!res)
3442 return -ENOENT;
3443
3444 *vport_num = *res;
3445 return 0;
3446}
10742efc
VB		 3447
3448u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3449 u16 vport_num)
3450{
3451 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3452
3453 if (WARN_ON_ONCE(IS_ERR(vport)))
3454 return 0;
3455
3456 return vport->metadata;
3457}
3458EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
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