]>
Commit | Line | Data |
---|---|---|
69697b6e OG |
1 | /* |
2 | * Copyright (c) 2016, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/etherdevice.h> | |
133dcfc5 | 34 | #include <linux/idr.h> |
69697b6e OG |
35 | #include <linux/mlx5/driver.h> |
36 | #include <linux/mlx5/mlx5_ifc.h> | |
37 | #include <linux/mlx5/vport.h> | |
38 | #include <linux/mlx5/fs.h> | |
39 | #include "mlx5_core.h" | |
40 | #include "eswitch.h" | |
34ca6535 | 41 | #include "esw/indir_table.h" |
ea651a86 | 42 | #include "esw/acl/ofld.h" |
80f09dfc | 43 | #include "rdma.h" |
e52c2802 PB |
44 | #include "en.h" |
45 | #include "fs_core.h" | |
ac004b83 | 46 | #include "lib/devcom.h" |
a3888f33 | 47 | #include "lib/eq.h" |
ae430332 | 48 | #include "lib/fs_chains.h" |
c620b772 | 49 | #include "en_tc.h" |
c9355682 | 50 | #include "en/mapping.h" |
c85a6b8f | 51 | #include "devlink.h" |
69697b6e | 52 | |
47dd7e60 PP |
53 | #define mlx5_esw_for_each_rep(esw, i, rep) \ |
54 | xa_for_each(&((esw)->offloads.vport_reps), i, rep) | |
55 | ||
56 | #define mlx5_esw_for_each_sf_rep(esw, i, rep) \ | |
57 | xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF) | |
58 | ||
59 | #define mlx5_esw_for_each_vf_rep(esw, index, rep) \ | |
60 | mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \ | |
61 | rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF) | |
62 | ||
cd7e4186 BW |
63 | /* There are two match-all miss flows, one for unicast dst mac and |
64 | * one for multicast. | |
65 | */ | |
66 | #define MLX5_ESW_MISS_FLOWS (2) | |
c9b99abc BW |
67 | #define UPLINK_REP_INDEX 0 |
68 | ||
c796bb7c CM |
69 | #define MLX5_ESW_VPORT_TBL_SIZE 128 |
70 | #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4 | |
71 | ||
72 | static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = { | |
73 | .max_fte = MLX5_ESW_VPORT_TBL_SIZE, | |
74 | .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS, | |
75 | .flags = 0, | |
76 | }; | |
77 | ||
879c8f84 BW |
78 | static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw, |
79 | u16 vport_num) | |
80 | { | |
47dd7e60 | 81 | return xa_load(&esw->offloads.vport_reps, vport_num); |
879c8f84 BW |
82 | } |
83 | ||
6f7bbad1 JL |
84 | static void |
85 | mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw, | |
86 | struct mlx5_flow_spec *spec, | |
87 | struct mlx5_esw_flow_attr *attr) | |
88 | { | |
89 | if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) && | |
036e19b9 HI |
90 | attr && attr->in_rep) |
91 | spec->flow_context.flow_source = | |
92 | attr->in_rep->vport == MLX5_VPORT_UPLINK ? | |
93 | MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK : | |
94 | MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT; | |
6f7bbad1 | 95 | } |
b7826076 | 96 | |
f94d6389 CM |
97 | /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits |
98 | * are not needed as well in the following process. So clear them all for simplicity. | |
99 | */ | |
100 | void | |
101 | mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec) | |
102 | { | |
103 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
104 | void *misc2; | |
105 | ||
106 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); | |
107 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0); | |
108 | ||
109 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); | |
110 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0); | |
111 | ||
112 | if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2))) | |
113 | spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2; | |
114 | } | |
115 | } | |
116 | ||
c01cfd0f JL |
117 | static void |
118 | mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw, | |
119 | struct mlx5_flow_spec *spec, | |
a508728a | 120 | struct mlx5_flow_attr *attr, |
b055ecf5 MB |
121 | struct mlx5_eswitch *src_esw, |
122 | u16 vport) | |
c01cfd0f JL |
123 | { |
124 | void *misc2; | |
125 | void *misc; | |
126 | ||
127 | /* Use metadata matching because vport is not represented by single | |
128 | * VHCA in dual-port RoCE mode, and matching on source vport may fail. | |
129 | */ | |
130 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
a508728a VB |
131 | if (mlx5_esw_indir_table_decap_vport(attr)) |
132 | vport = mlx5_esw_indir_table_decap_vport(attr); | |
c01cfd0f JL |
133 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); |
134 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, | |
b055ecf5 MB |
135 | mlx5_eswitch_get_vport_metadata_for_match(src_esw, |
136 | vport)); | |
c01cfd0f JL |
137 | |
138 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); | |
0f0d3827 PB |
139 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, |
140 | mlx5_eswitch_get_vport_metadata_mask()); | |
c01cfd0f JL |
141 | |
142 | spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; | |
c01cfd0f JL |
143 | } else { |
144 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); | |
b055ecf5 | 145 | MLX5_SET(fte_match_set_misc, misc, source_port, vport); |
c01cfd0f JL |
146 | |
147 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) | |
148 | MLX5_SET(fte_match_set_misc, misc, | |
149 | source_eswitch_owner_vhca_id, | |
b055ecf5 | 150 | MLX5_CAP_GEN(src_esw->dev, vhca_id)); |
c01cfd0f JL |
151 | |
152 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters); | |
153 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
154 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) | |
155 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, | |
156 | source_eswitch_owner_vhca_id); | |
157 | ||
158 | spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS; | |
159 | } | |
c01cfd0f JL |
160 | } |
161 | ||
a508728a VB |
162 | static int |
163 | esw_setup_decap_indir(struct mlx5_eswitch *esw, | |
164 | struct mlx5_flow_attr *attr, | |
165 | struct mlx5_flow_spec *spec) | |
166 | { | |
167 | struct mlx5_flow_table *ft; | |
168 | ||
169 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE)) | |
170 | return -EOPNOTSUPP; | |
171 | ||
172 | ft = mlx5_esw_indir_table_get(esw, attr, spec, | |
173 | mlx5_esw_indir_table_decap_vport(attr), true); | |
174 | return PTR_ERR_OR_ZERO(ft); | |
175 | } | |
176 | ||
9e51c0a6 | 177 | static void |
a508728a VB |
178 | esw_cleanup_decap_indir(struct mlx5_eswitch *esw, |
179 | struct mlx5_flow_attr *attr) | |
180 | { | |
181 | if (mlx5_esw_indir_table_decap_vport(attr)) | |
182 | mlx5_esw_indir_table_put(esw, attr, | |
183 | mlx5_esw_indir_table_decap_vport(attr), | |
184 | true); | |
185 | } | |
186 | ||
f94d6389 CM |
187 | static int |
188 | esw_setup_sampler_dest(struct mlx5_flow_destination *dest, | |
189 | struct mlx5_flow_act *flow_act, | |
bcd6740c | 190 | struct mlx5_flow_attr *attr, |
f94d6389 CM |
191 | int i) |
192 | { | |
193 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
194 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER; | |
bcd6740c | 195 | dest[i].sampler_id = attr->sample_attr->sampler_id; |
f94d6389 CM |
196 | |
197 | return 0; | |
198 | } | |
199 | ||
a508728a | 200 | static int |
9e51c0a6 VB |
201 | esw_setup_ft_dest(struct mlx5_flow_destination *dest, |
202 | struct mlx5_flow_act *flow_act, | |
a508728a | 203 | struct mlx5_eswitch *esw, |
9e51c0a6 | 204 | struct mlx5_flow_attr *attr, |
a508728a | 205 | struct mlx5_flow_spec *spec, |
9e51c0a6 VB |
206 | int i) |
207 | { | |
208 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
209 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
210 | dest[i].ft = attr->dest_ft; | |
a508728a VB |
211 | |
212 | if (mlx5_esw_indir_table_decap_vport(attr)) | |
213 | return esw_setup_decap_indir(esw, attr, spec); | |
214 | return 0; | |
9e51c0a6 VB |
215 | } |
216 | ||
217 | static void | |
218 | esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, | |
219 | struct mlx5_flow_act *flow_act, | |
220 | struct mlx5_fs_chains *chains, | |
221 | int i) | |
222 | { | |
2a2c84fa RD |
223 | if (mlx5_chains_ignore_flow_level_supported(chains)) |
224 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
9e51c0a6 VB |
225 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; |
226 | dest[i].ft = mlx5_chains_get_tc_end_ft(chains); | |
227 | } | |
228 | ||
229 | static int | |
230 | esw_setup_chain_dest(struct mlx5_flow_destination *dest, | |
231 | struct mlx5_flow_act *flow_act, | |
232 | struct mlx5_fs_chains *chains, | |
233 | u32 chain, u32 prio, u32 level, | |
234 | int i) | |
235 | { | |
236 | struct mlx5_flow_table *ft; | |
237 | ||
238 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
239 | ft = mlx5_chains_get_table(chains, chain, prio, level); | |
240 | if (IS_ERR(ft)) | |
241 | return PTR_ERR(ft); | |
242 | ||
243 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
244 | dest[i].ft = ft; | |
245 | return 0; | |
246 | } | |
247 | ||
10742efc VB |
248 | static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr, |
249 | int from, int to) | |
250 | { | |
251 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
252 | struct mlx5_fs_chains *chains = esw_chains(esw); | |
253 | int i; | |
254 | ||
255 | for (i = from; i < to; i++) | |
256 | if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE) | |
257 | mlx5_chains_put_table(chains, 0, 1, 0); | |
a508728a VB |
258 | else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport, |
259 | esw_attr->dests[i].mdev)) | |
260 | mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport, | |
261 | false); | |
10742efc VB |
262 | } |
263 | ||
264 | static bool | |
265 | esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr) | |
266 | { | |
267 | int i; | |
268 | ||
269 | for (i = esw_attr->split_count; i < esw_attr->out_count; i++) | |
270 | if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE) | |
271 | return true; | |
272 | return false; | |
273 | } | |
274 | ||
275 | static int | |
276 | esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest, | |
277 | struct mlx5_flow_act *flow_act, | |
278 | struct mlx5_eswitch *esw, | |
279 | struct mlx5_fs_chains *chains, | |
280 | struct mlx5_flow_attr *attr, | |
281 | int *i) | |
282 | { | |
283 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
284 | int j, err; | |
285 | ||
286 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE)) | |
287 | return -EOPNOTSUPP; | |
288 | ||
289 | for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) { | |
290 | err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i); | |
291 | if (err) | |
292 | goto err_setup_chain; | |
293 | flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; | |
294 | flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat; | |
295 | } | |
296 | return 0; | |
297 | ||
298 | err_setup_chain: | |
299 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j); | |
300 | return err; | |
301 | } | |
302 | ||
303 | static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw, | |
304 | struct mlx5_flow_attr *attr) | |
305 | { | |
306 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
307 | ||
308 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count); | |
309 | } | |
310 | ||
a508728a VB |
311 | static bool |
312 | esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr) | |
313 | { | |
314 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
315 | int i; | |
316 | ||
317 | for (i = esw_attr->split_count; i < esw_attr->out_count; i++) | |
318 | if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport, | |
319 | esw_attr->dests[i].mdev)) | |
320 | return true; | |
321 | return false; | |
322 | } | |
323 | ||
324 | static int | |
325 | esw_setup_indir_table(struct mlx5_flow_destination *dest, | |
326 | struct mlx5_flow_act *flow_act, | |
327 | struct mlx5_eswitch *esw, | |
328 | struct mlx5_flow_attr *attr, | |
329 | struct mlx5_flow_spec *spec, | |
330 | bool ignore_flow_lvl, | |
331 | int *i) | |
332 | { | |
333 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
334 | int j, err; | |
335 | ||
336 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE)) | |
337 | return -EOPNOTSUPP; | |
338 | ||
339 | for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) { | |
340 | if (ignore_flow_lvl) | |
341 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
342 | dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
343 | ||
344 | dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec, | |
345 | esw_attr->dests[j].rep->vport, false); | |
346 | if (IS_ERR(dest[*i].ft)) { | |
347 | err = PTR_ERR(dest[*i].ft); | |
348 | goto err_indir_tbl_get; | |
349 | } | |
350 | } | |
351 | ||
352 | if (mlx5_esw_indir_table_decap_vport(attr)) { | |
353 | err = esw_setup_decap_indir(esw, attr, spec); | |
354 | if (err) | |
355 | goto err_indir_tbl_get; | |
356 | } | |
357 | ||
358 | return 0; | |
359 | ||
360 | err_indir_tbl_get: | |
361 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j); | |
362 | return err; | |
363 | } | |
364 | ||
365 | static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr) | |
366 | { | |
367 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
368 | ||
369 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count); | |
370 | esw_cleanup_decap_indir(esw, attr); | |
371 | } | |
372 | ||
9e51c0a6 VB |
373 | static void |
374 | esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level) | |
375 | { | |
376 | mlx5_chains_put_table(chains, chain, prio, level); | |
377 | } | |
378 | ||
379 | static void | |
380 | esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act, | |
381 | struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr, | |
382 | int attr_idx, int dest_idx, bool pkt_reformat) | |
383 | { | |
384 | dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
385 | dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport; | |
c6719725 MD |
386 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) { |
387 | dest[dest_idx].vport.vhca_id = | |
388 | MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id); | |
9e51c0a6 | 389 | dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID; |
c6719725 | 390 | } |
9e51c0a6 VB |
391 | if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) { |
392 | if (pkt_reformat) { | |
393 | flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; | |
394 | flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat; | |
395 | } | |
396 | dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; | |
397 | dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat; | |
398 | } | |
399 | } | |
400 | ||
401 | static int | |
402 | esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act, | |
403 | struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr, | |
404 | int i) | |
405 | { | |
406 | int j; | |
407 | ||
408 | for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++) | |
409 | esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true); | |
410 | return i; | |
411 | } | |
412 | ||
e929e3da MD |
413 | static bool |
414 | esw_src_port_rewrite_supported(struct mlx5_eswitch *esw) | |
415 | { | |
416 | return MLX5_CAP_GEN(esw->dev, reg_c_preserve) && | |
417 | mlx5_eswitch_vport_match_metadata_enabled(esw) && | |
418 | MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level); | |
419 | } | |
420 | ||
9e51c0a6 VB |
421 | static int |
422 | esw_setup_dests(struct mlx5_flow_destination *dest, | |
423 | struct mlx5_flow_act *flow_act, | |
424 | struct mlx5_eswitch *esw, | |
425 | struct mlx5_flow_attr *attr, | |
10742efc | 426 | struct mlx5_flow_spec *spec, |
9e51c0a6 VB |
427 | int *i) |
428 | { | |
429 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
430 | struct mlx5_fs_chains *chains = esw_chains(esw); | |
431 | int err = 0; | |
432 | ||
10742efc | 433 | if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) && |
e929e3da | 434 | esw_src_port_rewrite_supported(esw)) |
10742efc VB |
435 | attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE; |
436 | ||
f94d6389 | 437 | if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) { |
bcd6740c | 438 | esw_setup_sampler_dest(dest, flow_act, attr, *i); |
f94d6389 CM |
439 | (*i)++; |
440 | } else if (attr->dest_ft) { | |
a508728a | 441 | esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i); |
9e51c0a6 VB |
442 | (*i)++; |
443 | } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) { | |
444 | esw_setup_slow_path_dest(dest, flow_act, chains, *i); | |
445 | (*i)++; | |
446 | } else if (attr->dest_chain) { | |
447 | err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, | |
448 | 1, 0, *i); | |
449 | (*i)++; | |
a508728a VB |
450 | } else if (esw_is_indir_table(esw, attr)) { |
451 | err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i); | |
10742efc VB |
452 | } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) { |
453 | err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i); | |
9e51c0a6 VB |
454 | } else { |
455 | *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i); | |
456 | } | |
457 | ||
458 | return err; | |
459 | } | |
460 | ||
461 | static void | |
462 | esw_cleanup_dests(struct mlx5_eswitch *esw, | |
463 | struct mlx5_flow_attr *attr) | |
464 | { | |
10742efc | 465 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
9e51c0a6 VB |
466 | struct mlx5_fs_chains *chains = esw_chains(esw); |
467 | ||
a508728a VB |
468 | if (attr->dest_ft) { |
469 | esw_cleanup_decap_indir(esw, attr); | |
470 | } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) { | |
10742efc VB |
471 | if (attr->dest_chain) |
472 | esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0); | |
a508728a VB |
473 | else if (esw_is_indir_table(esw, attr)) |
474 | esw_cleanup_indir_table(esw, attr); | |
10742efc VB |
475 | else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) |
476 | esw_cleanup_chain_src_port_rewrite(esw, attr); | |
477 | } | |
9e51c0a6 VB |
478 | } |
479 | ||
74491de9 | 480 | struct mlx5_flow_handle * |
3d80d1a2 OG |
481 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
482 | struct mlx5_flow_spec *spec, | |
c620b772 | 483 | struct mlx5_flow_attr *attr) |
3d80d1a2 | 484 | { |
592d3651 | 485 | struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {}; |
42f7ad67 | 486 | struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, }; |
c620b772 | 487 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
ae430332 | 488 | struct mlx5_fs_chains *chains = esw_chains(esw); |
c620b772 AL |
489 | bool split = !!(esw_attr->split_count); |
490 | struct mlx5_vport_tbl_attr fwd_attr; | |
74491de9 | 491 | struct mlx5_flow_handle *rule; |
e52c2802 | 492 | struct mlx5_flow_table *fdb; |
9e51c0a6 | 493 | int i = 0; |
3d80d1a2 | 494 | |
f6455de0 | 495 | if (esw->mode != MLX5_ESWITCH_OFFLOADS) |
3d80d1a2 OG |
496 | return ERR_PTR(-EOPNOTSUPP); |
497 | ||
6acfbf38 OG |
498 | flow_act.action = attr->action; |
499 | /* if per flow vlan pop/push is emulated, don't set that into the firmware */ | |
cc495188 | 500 | if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1)) |
6acfbf38 OG |
501 | flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH | |
502 | MLX5_FLOW_CONTEXT_ACTION_VLAN_POP); | |
503 | else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) { | |
c620b772 AL |
504 | flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]); |
505 | flow_act.vlan[0].vid = esw_attr->vlan_vid[0]; | |
506 | flow_act.vlan[0].prio = esw_attr->vlan_prio[0]; | |
cc495188 | 507 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) { |
c620b772 AL |
508 | flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]); |
509 | flow_act.vlan[1].vid = esw_attr->vlan_vid[1]; | |
510 | flow_act.vlan[1].prio = esw_attr->vlan_prio[1]; | |
cc495188 | 511 | } |
6acfbf38 | 512 | } |
776b12b6 | 513 | |
10742efc VB |
514 | mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr); |
515 | ||
66958ed9 | 516 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { |
9e51c0a6 VB |
517 | int err; |
518 | ||
10742efc | 519 | err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i); |
9e51c0a6 VB |
520 | if (err) { |
521 | rule = ERR_PTR(err); | |
522 | goto err_create_goto_table; | |
56e858df | 523 | } |
e37a79e5 | 524 | } |
14e6b038 | 525 | |
c620b772 AL |
526 | if (esw_attr->decap_pkt_reformat) |
527 | flow_act.pkt_reformat = esw_attr->decap_pkt_reformat; | |
14e6b038 | 528 | |
66958ed9 | 529 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { |
e37a79e5 | 530 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; |
171c7625 | 531 | dest[i].counter_id = mlx5_fc_id(attr->counter); |
e37a79e5 | 532 | i++; |
3d80d1a2 OG |
533 | } |
534 | ||
93b3586e | 535 | if (attr->outer_match_level != MLX5_MATCH_NONE) |
6363651d | 536 | spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS; |
93b3586e HN |
537 | if (attr->inner_match_level != MLX5_MATCH_NONE) |
538 | spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS; | |
3d80d1a2 | 539 | |
aa24670e | 540 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
2b688ea5 | 541 | flow_act.modify_hdr = attr->modify_hdr; |
d7e75a32 | 542 | |
2741f223 | 543 | if (split) { |
c620b772 AL |
544 | fwd_attr.chain = attr->chain; |
545 | fwd_attr.prio = attr->prio; | |
546 | fwd_attr.vport = esw_attr->in_rep->vport; | |
c796bb7c | 547 | fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
c620b772 | 548 | |
0a9e2307 | 549 | fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr); |
96e32687 | 550 | } else { |
d18296ff | 551 | if (attr->chain || attr->prio) |
ae430332 AL |
552 | fdb = mlx5_chains_get_table(chains, attr->chain, |
553 | attr->prio, 0); | |
d18296ff | 554 | else |
c620b772 | 555 | fdb = attr->ft; |
6fb0701a PB |
556 | |
557 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT)) | |
a508728a | 558 | mlx5_eswitch_set_rule_source_port(esw, spec, attr, |
b055ecf5 MB |
559 | esw_attr->in_mdev->priv.eswitch, |
560 | esw_attr->in_rep->vport); | |
96e32687 | 561 | } |
e52c2802 PB |
562 | if (IS_ERR(fdb)) { |
563 | rule = ERR_CAST(fdb); | |
564 | goto err_esw_get; | |
565 | } | |
566 | ||
84be2fda | 567 | if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec)) |
c620b772 | 568 | rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr, |
10caabda | 569 | &flow_act, dest, i); |
84be2fda | 570 | else |
10caabda | 571 | rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i); |
3d80d1a2 | 572 | if (IS_ERR(rule)) |
e52c2802 | 573 | goto err_add_rule; |
375f51e2 | 574 | else |
525e84be | 575 | atomic64_inc(&esw->offloads.num_flows); |
3d80d1a2 | 576 | |
e52c2802 PB |
577 | return rule; |
578 | ||
579 | err_add_rule: | |
96e32687 | 580 | if (split) |
0a9e2307 | 581 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
d18296ff | 582 | else if (attr->chain || attr->prio) |
ae430332 | 583 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
e52c2802 | 584 | err_esw_get: |
9e51c0a6 | 585 | esw_cleanup_dests(esw, attr); |
e52c2802 | 586 | err_create_goto_table: |
aa0cbbae | 587 | return rule; |
3d80d1a2 OG |
588 | } |
589 | ||
e4ad91f2 CM |
590 | struct mlx5_flow_handle * |
591 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
592 | struct mlx5_flow_spec *spec, | |
c620b772 | 593 | struct mlx5_flow_attr *attr) |
e4ad91f2 CM |
594 | { |
595 | struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {}; | |
42f7ad67 | 596 | struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, }; |
c620b772 | 597 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
ae430332 | 598 | struct mlx5_fs_chains *chains = esw_chains(esw); |
c620b772 | 599 | struct mlx5_vport_tbl_attr fwd_attr; |
e52c2802 PB |
600 | struct mlx5_flow_table *fast_fdb; |
601 | struct mlx5_flow_table *fwd_fdb; | |
e4ad91f2 | 602 | struct mlx5_flow_handle *rule; |
10742efc | 603 | int i, err = 0; |
e4ad91f2 | 604 | |
ae430332 | 605 | fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0); |
e52c2802 PB |
606 | if (IS_ERR(fast_fdb)) { |
607 | rule = ERR_CAST(fast_fdb); | |
608 | goto err_get_fast; | |
609 | } | |
610 | ||
c620b772 AL |
611 | fwd_attr.chain = attr->chain; |
612 | fwd_attr.prio = attr->prio; | |
613 | fwd_attr.vport = esw_attr->in_rep->vport; | |
c796bb7c | 614 | fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
0a9e2307 | 615 | fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr); |
e52c2802 PB |
616 | if (IS_ERR(fwd_fdb)) { |
617 | rule = ERR_CAST(fwd_fdb); | |
618 | goto err_get_fwd; | |
619 | } | |
620 | ||
e4ad91f2 | 621 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
10742efc | 622 | for (i = 0; i < esw_attr->split_count; i++) { |
a508728a VB |
623 | if (esw_is_indir_table(esw, attr)) |
624 | err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i); | |
625 | else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) | |
10742efc VB |
626 | err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr, |
627 | &i); | |
628 | else | |
629 | esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false); | |
630 | ||
631 | if (err) { | |
632 | rule = ERR_PTR(err); | |
633 | goto err_chain_src_rewrite; | |
634 | } | |
635 | } | |
e4ad91f2 | 636 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; |
873d2f12 | 637 | dest[i].ft = fwd_fdb; |
e4ad91f2 CM |
638 | i++; |
639 | ||
a508728a | 640 | mlx5_eswitch_set_rule_source_port(esw, spec, attr, |
b055ecf5 MB |
641 | esw_attr->in_mdev->priv.eswitch, |
642 | esw_attr->in_rep->vport); | |
e4ad91f2 | 643 | |
93b3586e | 644 | if (attr->outer_match_level != MLX5_MATCH_NONE) |
c01cfd0f | 645 | spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS; |
e4ad91f2 | 646 | |
278d51f2 | 647 | flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; |
e52c2802 | 648 | rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i); |
e4ad91f2 | 649 | |
10742efc VB |
650 | if (IS_ERR(rule)) { |
651 | i = esw_attr->split_count; | |
652 | goto err_chain_src_rewrite; | |
653 | } | |
e4ad91f2 | 654 | |
525e84be | 655 | atomic64_inc(&esw->offloads.num_flows); |
e52c2802 PB |
656 | |
657 | return rule; | |
10742efc VB |
658 | err_chain_src_rewrite: |
659 | esw_put_dest_tables_loop(esw, attr, 0, i); | |
0a9e2307 | 660 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
e52c2802 | 661 | err_get_fwd: |
ae430332 | 662 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
e52c2802 | 663 | err_get_fast: |
e4ad91f2 CM |
664 | return rule; |
665 | } | |
666 | ||
e52c2802 PB |
667 | static void |
668 | __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw, | |
669 | struct mlx5_flow_handle *rule, | |
c620b772 | 670 | struct mlx5_flow_attr *attr, |
e52c2802 PB |
671 | bool fwd_rule) |
672 | { | |
c620b772 | 673 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
ae430332 | 674 | struct mlx5_fs_chains *chains = esw_chains(esw); |
c620b772 AL |
675 | bool split = (esw_attr->split_count > 0); |
676 | struct mlx5_vport_tbl_attr fwd_attr; | |
10caabda | 677 | int i; |
e52c2802 PB |
678 | |
679 | mlx5_del_flow_rules(rule); | |
10caabda | 680 | |
84be2fda | 681 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) { |
d8a2034f EC |
682 | /* unref the term table */ |
683 | for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) { | |
c620b772 AL |
684 | if (esw_attr->dests[i].termtbl) |
685 | mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl); | |
d8a2034f | 686 | } |
10caabda OS |
687 | } |
688 | ||
525e84be | 689 | atomic64_dec(&esw->offloads.num_flows); |
e52c2802 | 690 | |
c620b772 AL |
691 | if (fwd_rule || split) { |
692 | fwd_attr.chain = attr->chain; | |
693 | fwd_attr.prio = attr->prio; | |
694 | fwd_attr.vport = esw_attr->in_rep->vport; | |
c796bb7c | 695 | fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
c620b772 AL |
696 | } |
697 | ||
e52c2802 | 698 | if (fwd_rule) { |
0a9e2307 | 699 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
ae430332 | 700 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
10742efc | 701 | esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count); |
e52c2802 | 702 | } else { |
96e32687 | 703 | if (split) |
0a9e2307 | 704 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
d18296ff | 705 | else if (attr->chain || attr->prio) |
ae430332 | 706 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
9e51c0a6 | 707 | esw_cleanup_dests(esw, attr); |
e52c2802 PB |
708 | } |
709 | } | |
710 | ||
d85cdccb OG |
711 | void |
712 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
713 | struct mlx5_flow_handle *rule, | |
c620b772 | 714 | struct mlx5_flow_attr *attr) |
d85cdccb | 715 | { |
e52c2802 | 716 | __mlx5_eswitch_del_rule(esw, rule, attr, false); |
d85cdccb OG |
717 | } |
718 | ||
48265006 OG |
719 | void |
720 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
721 | struct mlx5_flow_handle *rule, | |
c620b772 | 722 | struct mlx5_flow_attr *attr) |
48265006 | 723 | { |
e52c2802 | 724 | __mlx5_eswitch_del_rule(esw, rule, attr, true); |
48265006 OG |
725 | } |
726 | ||
f5f82476 OG |
727 | static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val) |
728 | { | |
729 | struct mlx5_eswitch_rep *rep; | |
47dd7e60 PP |
730 | unsigned long i; |
731 | int err = 0; | |
f5f82476 OG |
732 | |
733 | esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none"); | |
47dd7e60 | 734 | mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) { |
8693115a | 735 | if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED) |
f5f82476 OG |
736 | continue; |
737 | ||
738 | err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val); | |
739 | if (err) | |
740 | goto out; | |
741 | } | |
742 | ||
743 | out: | |
744 | return err; | |
745 | } | |
746 | ||
747 | static struct mlx5_eswitch_rep * | |
748 | esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop) | |
749 | { | |
750 | struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL; | |
751 | ||
752 | in_rep = attr->in_rep; | |
df65a573 | 753 | out_rep = attr->dests[0].rep; |
f5f82476 OG |
754 | |
755 | if (push) | |
756 | vport = in_rep; | |
757 | else if (pop) | |
758 | vport = out_rep; | |
759 | else | |
760 | vport = in_rep; | |
761 | ||
762 | return vport; | |
763 | } | |
764 | ||
765 | static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr, | |
766 | bool push, bool pop, bool fwd) | |
767 | { | |
768 | struct mlx5_eswitch_rep *in_rep, *out_rep; | |
769 | ||
770 | if ((push || pop) && !fwd) | |
771 | goto out_notsupp; | |
772 | ||
773 | in_rep = attr->in_rep; | |
df65a573 | 774 | out_rep = attr->dests[0].rep; |
f5f82476 | 775 | |
b05af6aa | 776 | if (push && in_rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
777 | goto out_notsupp; |
778 | ||
b05af6aa | 779 | if (pop && out_rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
780 | goto out_notsupp; |
781 | ||
782 | /* vport has vlan push configured, can't offload VF --> wire rules w.o it */ | |
783 | if (!push && !pop && fwd) | |
b05af6aa | 784 | if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
785 | goto out_notsupp; |
786 | ||
787 | /* protects against (1) setting rules with different vlans to push and | |
788 | * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0) | |
789 | */ | |
1482bd3d | 790 | if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0])) |
f5f82476 OG |
791 | goto out_notsupp; |
792 | ||
793 | return 0; | |
794 | ||
795 | out_notsupp: | |
9eb78923 | 796 | return -EOPNOTSUPP; |
f5f82476 OG |
797 | } |
798 | ||
799 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, | |
c620b772 | 800 | struct mlx5_flow_attr *attr) |
f5f82476 OG |
801 | { |
802 | struct offloads_fdb *offloads = &esw->fdb_table.offloads; | |
c620b772 | 803 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
f5f82476 OG |
804 | struct mlx5_eswitch_rep *vport = NULL; |
805 | bool push, pop, fwd; | |
806 | int err = 0; | |
807 | ||
6acfbf38 | 808 | /* nop if we're on the vlan push/pop non emulation mode */ |
cc495188 | 809 | if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1)) |
6acfbf38 OG |
810 | return 0; |
811 | ||
f5f82476 OG |
812 | push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH); |
813 | pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP); | |
e52c2802 PB |
814 | fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) && |
815 | !attr->dest_chain); | |
f5f82476 | 816 | |
0e18134f VB |
817 | mutex_lock(&esw->state_lock); |
818 | ||
c620b772 | 819 | err = esw_add_vlan_action_check(esw_attr, push, pop, fwd); |
f5f82476 | 820 | if (err) |
0e18134f | 821 | goto unlock; |
f5f82476 | 822 | |
39ac237c | 823 | attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED; |
f5f82476 | 824 | |
c620b772 | 825 | vport = esw_vlan_action_get_vport(esw_attr, push, pop); |
f5f82476 OG |
826 | |
827 | if (!push && !pop && fwd) { | |
828 | /* tracks VF --> wire rules without vlan push action */ | |
c620b772 | 829 | if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) { |
f5f82476 | 830 | vport->vlan_refcount++; |
39ac237c | 831 | attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED; |
f5f82476 OG |
832 | } |
833 | ||
0e18134f | 834 | goto unlock; |
f5f82476 OG |
835 | } |
836 | ||
837 | if (!push && !pop) | |
0e18134f | 838 | goto unlock; |
f5f82476 OG |
839 | |
840 | if (!(offloads->vlan_push_pop_refcount)) { | |
841 | /* it's the 1st vlan rule, apply global vlan pop policy */ | |
842 | err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP); | |
843 | if (err) | |
844 | goto out; | |
845 | } | |
846 | offloads->vlan_push_pop_refcount++; | |
847 | ||
848 | if (push) { | |
849 | if (vport->vlan_refcount) | |
850 | goto skip_set_push; | |
851 | ||
c620b772 AL |
852 | err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0], |
853 | 0, SET_VLAN_INSERT | SET_VLAN_STRIP); | |
f5f82476 OG |
854 | if (err) |
855 | goto out; | |
c620b772 | 856 | vport->vlan = esw_attr->vlan_vid[0]; |
f5f82476 OG |
857 | skip_set_push: |
858 | vport->vlan_refcount++; | |
859 | } | |
860 | out: | |
861 | if (!err) | |
39ac237c | 862 | attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED; |
0e18134f VB |
863 | unlock: |
864 | mutex_unlock(&esw->state_lock); | |
f5f82476 OG |
865 | return err; |
866 | } | |
867 | ||
868 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
c620b772 | 869 | struct mlx5_flow_attr *attr) |
f5f82476 OG |
870 | { |
871 | struct offloads_fdb *offloads = &esw->fdb_table.offloads; | |
c620b772 | 872 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
f5f82476 OG |
873 | struct mlx5_eswitch_rep *vport = NULL; |
874 | bool push, pop, fwd; | |
875 | int err = 0; | |
876 | ||
6acfbf38 | 877 | /* nop if we're on the vlan push/pop non emulation mode */ |
cc495188 | 878 | if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1)) |
6acfbf38 OG |
879 | return 0; |
880 | ||
39ac237c | 881 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED)) |
f5f82476 OG |
882 | return 0; |
883 | ||
884 | push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH); | |
885 | pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP); | |
886 | fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST); | |
887 | ||
0e18134f VB |
888 | mutex_lock(&esw->state_lock); |
889 | ||
c620b772 | 890 | vport = esw_vlan_action_get_vport(esw_attr, push, pop); |
f5f82476 OG |
891 | |
892 | if (!push && !pop && fwd) { | |
893 | /* tracks VF --> wire rules without vlan push action */ | |
c620b772 | 894 | if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
895 | vport->vlan_refcount--; |
896 | ||
0e18134f | 897 | goto out; |
f5f82476 OG |
898 | } |
899 | ||
900 | if (push) { | |
901 | vport->vlan_refcount--; | |
902 | if (vport->vlan_refcount) | |
903 | goto skip_unset_push; | |
904 | ||
905 | vport->vlan = 0; | |
906 | err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, | |
907 | 0, 0, SET_VLAN_STRIP); | |
908 | if (err) | |
909 | goto out; | |
910 | } | |
911 | ||
912 | skip_unset_push: | |
913 | offloads->vlan_push_pop_refcount--; | |
914 | if (offloads->vlan_push_pop_refcount) | |
0e18134f | 915 | goto out; |
f5f82476 OG |
916 | |
917 | /* no more vlan rules, stop global vlan pop policy */ | |
918 | err = esw_set_global_vlan_pop(esw, 0); | |
919 | ||
920 | out: | |
0e18134f | 921 | mutex_unlock(&esw->state_lock); |
f5f82476 OG |
922 | return err; |
923 | } | |
924 | ||
f7a68945 | 925 | struct mlx5_flow_handle * |
3a46f4fb | 926 | mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw, |
979bf468 | 927 | struct mlx5_eswitch *from_esw, |
3a46f4fb | 928 | struct mlx5_eswitch_rep *rep, |
02f3afd9 | 929 | u32 sqn) |
ab22be9b | 930 | { |
66958ed9 | 931 | struct mlx5_flow_act flow_act = {0}; |
4c5009c5 | 932 | struct mlx5_flow_destination dest = {}; |
74491de9 | 933 | struct mlx5_flow_handle *flow_rule; |
c5bb1730 | 934 | struct mlx5_flow_spec *spec; |
ab22be9b OG |
935 | void *misc; |
936 | ||
1b9a07ee | 937 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
c5bb1730 | 938 | if (!spec) { |
ab22be9b OG |
939 | flow_rule = ERR_PTR(-ENOMEM); |
940 | goto out; | |
941 | } | |
942 | ||
c5bb1730 | 943 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); |
ab22be9b | 944 | MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn); |
a1b3839a | 945 | /* source vport is the esw manager */ |
979bf468 | 946 | MLX5_SET(fte_match_set_misc, misc, source_port, from_esw->manager_vport); |
3a46f4fb | 947 | if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch)) |
7d97822a | 948 | MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, |
979bf468 | 949 | MLX5_CAP_GEN(from_esw->dev, vhca_id)); |
ab22be9b | 950 | |
c5bb1730 | 951 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters); |
ab22be9b OG |
952 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn); |
953 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
3a46f4fb | 954 | if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch)) |
7d97822a MB |
955 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, |
956 | source_eswitch_owner_vhca_id); | |
ab22be9b | 957 | |
c5bb1730 | 958 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS; |
ab22be9b | 959 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; |
3a46f4fb MB |
960 | dest.vport.num = rep->vport; |
961 | dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id); | |
962 | dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID; | |
66958ed9 | 963 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
ab22be9b | 964 | |
d0444254 AL |
965 | if (rep->vport == MLX5_VPORT_UPLINK) |
966 | spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT; | |
967 | ||
3a46f4fb | 968 | flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb, |
39ac237c | 969 | spec, &flow_act, &dest, 1); |
ab22be9b | 970 | if (IS_ERR(flow_rule)) |
3a46f4fb MB |
971 | esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n", |
972 | PTR_ERR(flow_rule)); | |
ab22be9b | 973 | out: |
c5bb1730 | 974 | kvfree(spec); |
ab22be9b OG |
975 | return flow_rule; |
976 | } | |
57cbd893 | 977 | EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule); |
ab22be9b | 978 | |
159fe639 MB |
979 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule) |
980 | { | |
981 | mlx5_del_flow_rules(rule); | |
982 | } | |
983 | ||
8e404fef VB |
984 | static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw) |
985 | { | |
986 | struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules; | |
47dd7e60 | 987 | int i = 0, num_vfs = esw->esw_funcs.num_vfs; |
8e404fef VB |
988 | |
989 | if (!num_vfs || !flows) | |
990 | return; | |
991 | ||
47dd7e60 PP |
992 | for (i = 0; i < num_vfs; i++) |
993 | mlx5_del_flow_rules(flows[i]); | |
8e404fef VB |
994 | |
995 | kvfree(flows); | |
996 | } | |
997 | ||
998 | static int | |
999 | mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw) | |
1000 | { | |
8e404fef VB |
1001 | struct mlx5_flow_destination dest = {}; |
1002 | struct mlx5_flow_act flow_act = {0}; | |
6308a5f0 | 1003 | int num_vfs, rule_idx = 0, err = 0; |
8e404fef VB |
1004 | struct mlx5_flow_handle *flow_rule; |
1005 | struct mlx5_flow_handle **flows; | |
1006 | struct mlx5_flow_spec *spec; | |
47dd7e60 PP |
1007 | struct mlx5_vport *vport; |
1008 | unsigned long i; | |
6308a5f0 | 1009 | u16 vport_num; |
8e404fef VB |
1010 | |
1011 | num_vfs = esw->esw_funcs.num_vfs; | |
1012 | flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL); | |
1013 | if (!flows) | |
1014 | return -ENOMEM; | |
1015 | ||
1016 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); | |
1017 | if (!spec) { | |
1018 | err = -ENOMEM; | |
1019 | goto alloc_err; | |
1020 | } | |
1021 | ||
1022 | MLX5_SET(fte_match_param, spec->match_criteria, | |
1023 | misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask()); | |
1024 | MLX5_SET(fte_match_param, spec->match_criteria, | |
1025 | misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK); | |
1026 | MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1, | |
1027 | ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK); | |
1028 | ||
1029 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; | |
1030 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
1031 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
1032 | ||
47dd7e60 PP |
1033 | mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) { |
1034 | vport_num = vport->vport; | |
8e404fef VB |
1035 | MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0, |
1036 | mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num)); | |
1037 | dest.vport.num = vport_num; | |
1038 | ||
1039 | flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, | |
1040 | spec, &flow_act, &dest, 1); | |
1041 | if (IS_ERR(flow_rule)) { | |
1042 | err = PTR_ERR(flow_rule); | |
1043 | esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n", | |
1044 | rule_idx, PTR_ERR(flow_rule)); | |
1045 | goto rule_err; | |
1046 | } | |
1047 | flows[rule_idx++] = flow_rule; | |
1048 | } | |
1049 | ||
1050 | esw->fdb_table.offloads.send_to_vport_meta_rules = flows; | |
1051 | kvfree(spec); | |
1052 | return 0; | |
1053 | ||
1054 | rule_err: | |
1055 | while (--rule_idx >= 0) | |
1056 | mlx5_del_flow_rules(flows[rule_idx]); | |
1057 | kvfree(spec); | |
1058 | alloc_err: | |
1059 | kvfree(flows); | |
1060 | return err; | |
1061 | } | |
1062 | ||
5b7cb745 PB |
1063 | static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw) |
1064 | { | |
1065 | return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) & | |
1066 | MLX5_FDB_TO_VPORT_REG_C_1; | |
1067 | } | |
1068 | ||
332bd3a5 | 1069 | static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable) |
c1286050 JL |
1070 | { |
1071 | u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {}; | |
e08a6832 LR |
1072 | u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {}; |
1073 | u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {}; | |
5b7cb745 | 1074 | u8 curr, wanted; |
c1286050 JL |
1075 | int err; |
1076 | ||
5b7cb745 PB |
1077 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw) && |
1078 | !mlx5_eswitch_vport_match_metadata_enabled(esw)) | |
332bd3a5 | 1079 | return 0; |
c1286050 | 1080 | |
e08a6832 LR |
1081 | MLX5_SET(query_esw_vport_context_in, in, opcode, |
1082 | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT); | |
1083 | err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out); | |
c1286050 JL |
1084 | if (err) |
1085 | return err; | |
1086 | ||
5b7cb745 PB |
1087 | curr = MLX5_GET(query_esw_vport_context_out, out, |
1088 | esw_vport_context.fdb_to_vport_reg_c_id); | |
1089 | wanted = MLX5_FDB_TO_VPORT_REG_C_0; | |
1090 | if (mlx5_eswitch_reg_c1_loopback_supported(esw)) | |
1091 | wanted |= MLX5_FDB_TO_VPORT_REG_C_1; | |
c1286050 | 1092 | |
332bd3a5 | 1093 | if (enable) |
5b7cb745 | 1094 | curr |= wanted; |
332bd3a5 | 1095 | else |
5b7cb745 | 1096 | curr &= ~wanted; |
c1286050 | 1097 | |
e08a6832 | 1098 | MLX5_SET(modify_esw_vport_context_in, min, |
5b7cb745 | 1099 | esw_vport_context.fdb_to_vport_reg_c_id, curr); |
e08a6832 | 1100 | MLX5_SET(modify_esw_vport_context_in, min, |
c1286050 JL |
1101 | field_select.fdb_to_vport_reg_c_id, 1); |
1102 | ||
e08a6832 | 1103 | err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min); |
5b7cb745 PB |
1104 | if (!err) { |
1105 | if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1)) | |
1106 | esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED; | |
1107 | else | |
1108 | esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED; | |
1109 | } | |
1110 | ||
1111 | return err; | |
c1286050 JL |
1112 | } |
1113 | ||
a5641cb5 JL |
1114 | static void peer_miss_rules_setup(struct mlx5_eswitch *esw, |
1115 | struct mlx5_core_dev *peer_dev, | |
ac004b83 RD |
1116 | struct mlx5_flow_spec *spec, |
1117 | struct mlx5_flow_destination *dest) | |
1118 | { | |
a5641cb5 | 1119 | void *misc; |
ac004b83 | 1120 | |
a5641cb5 JL |
1121 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { |
1122 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1123 | misc_parameters_2); | |
0f0d3827 PB |
1124 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, |
1125 | mlx5_eswitch_get_vport_metadata_mask()); | |
ac004b83 | 1126 | |
a5641cb5 JL |
1127 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; |
1128 | } else { | |
1129 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1130 | misc_parameters); | |
ac004b83 | 1131 | |
a5641cb5 JL |
1132 | MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, |
1133 | MLX5_CAP_GEN(peer_dev, vhca_id)); | |
1134 | ||
1135 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS; | |
1136 | ||
1137 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1138 | misc_parameters); | |
1139 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
1140 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, | |
1141 | source_eswitch_owner_vhca_id); | |
1142 | } | |
ac004b83 RD |
1143 | |
1144 | dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
a1b3839a | 1145 | dest->vport.num = peer_dev->priv.eswitch->manager_vport; |
ac004b83 | 1146 | dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id); |
04de7dda | 1147 | dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID; |
ac004b83 RD |
1148 | } |
1149 | ||
a5641cb5 JL |
1150 | static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw, |
1151 | struct mlx5_eswitch *peer_esw, | |
1152 | struct mlx5_flow_spec *spec, | |
1153 | u16 vport) | |
1154 | { | |
1155 | void *misc; | |
1156 | ||
1157 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
1158 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1159 | misc_parameters_2); | |
1160 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
1161 | mlx5_eswitch_get_vport_metadata_for_match(peer_esw, | |
1162 | vport)); | |
1163 | } else { | |
1164 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1165 | misc_parameters); | |
1166 | MLX5_SET(fte_match_set_misc, misc, source_port, vport); | |
1167 | } | |
1168 | } | |
1169 | ||
ac004b83 RD |
1170 | static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw, |
1171 | struct mlx5_core_dev *peer_dev) | |
1172 | { | |
1173 | struct mlx5_flow_destination dest = {}; | |
1174 | struct mlx5_flow_act flow_act = {0}; | |
1175 | struct mlx5_flow_handle **flows; | |
ac004b83 RD |
1176 | /* total vports is the same for both e-switches */ |
1177 | int nvports = esw->total_vports; | |
47dd7e60 PP |
1178 | struct mlx5_flow_handle *flow; |
1179 | struct mlx5_flow_spec *spec; | |
1180 | struct mlx5_vport *vport; | |
1181 | unsigned long i; | |
ac004b83 | 1182 | void *misc; |
47dd7e60 | 1183 | int err; |
ac004b83 RD |
1184 | |
1185 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); | |
1186 | if (!spec) | |
1187 | return -ENOMEM; | |
1188 | ||
a5641cb5 | 1189 | peer_miss_rules_setup(esw, peer_dev, spec, &dest); |
ac004b83 RD |
1190 | |
1191 | flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL); | |
1192 | if (!flows) { | |
1193 | err = -ENOMEM; | |
1194 | goto alloc_flows_err; | |
1195 | } | |
1196 | ||
1197 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
1198 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1199 | misc_parameters); | |
1200 | ||
81cd229c | 1201 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { |
47dd7e60 | 1202 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); |
a5641cb5 JL |
1203 | esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch, |
1204 | spec, MLX5_VPORT_PF); | |
1205 | ||
81cd229c BW |
1206 | flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1207 | spec, &flow_act, &dest, 1); | |
1208 | if (IS_ERR(flow)) { | |
1209 | err = PTR_ERR(flow); | |
1210 | goto add_pf_flow_err; | |
1211 | } | |
47dd7e60 | 1212 | flows[vport->index] = flow; |
81cd229c BW |
1213 | } |
1214 | ||
1215 | if (mlx5_ecpf_vport_exists(esw->dev)) { | |
47dd7e60 | 1216 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); |
81cd229c BW |
1217 | MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF); |
1218 | flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, | |
1219 | spec, &flow_act, &dest, 1); | |
1220 | if (IS_ERR(flow)) { | |
1221 | err = PTR_ERR(flow); | |
1222 | goto add_ecpf_flow_err; | |
1223 | } | |
47dd7e60 | 1224 | flows[vport->index] = flow; |
81cd229c BW |
1225 | } |
1226 | ||
47dd7e60 | 1227 | mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) { |
a5641cb5 JL |
1228 | esw_set_peer_miss_rule_source_port(esw, |
1229 | peer_dev->priv.eswitch, | |
47dd7e60 | 1230 | spec, vport->vport); |
a5641cb5 | 1231 | |
ac004b83 RD |
1232 | flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1233 | spec, &flow_act, &dest, 1); | |
1234 | if (IS_ERR(flow)) { | |
1235 | err = PTR_ERR(flow); | |
81cd229c | 1236 | goto add_vf_flow_err; |
ac004b83 | 1237 | } |
47dd7e60 | 1238 | flows[vport->index] = flow; |
ac004b83 RD |
1239 | } |
1240 | ||
1241 | esw->fdb_table.offloads.peer_miss_rules = flows; | |
1242 | ||
1243 | kvfree(spec); | |
1244 | return 0; | |
1245 | ||
81cd229c | 1246 | add_vf_flow_err: |
47dd7e60 PP |
1247 | mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) { |
1248 | if (!flows[vport->index]) | |
1249 | continue; | |
1250 | mlx5_del_flow_rules(flows[vport->index]); | |
1251 | } | |
1252 | if (mlx5_ecpf_vport_exists(esw->dev)) { | |
1253 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); | |
1254 | mlx5_del_flow_rules(flows[vport->index]); | |
1255 | } | |
81cd229c | 1256 | add_ecpf_flow_err: |
47dd7e60 PP |
1257 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { |
1258 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); | |
1259 | mlx5_del_flow_rules(flows[vport->index]); | |
1260 | } | |
81cd229c BW |
1261 | add_pf_flow_err: |
1262 | esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err); | |
ac004b83 RD |
1263 | kvfree(flows); |
1264 | alloc_flows_err: | |
1265 | kvfree(spec); | |
1266 | return err; | |
1267 | } | |
1268 | ||
1269 | static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw) | |
1270 | { | |
1271 | struct mlx5_flow_handle **flows; | |
47dd7e60 PP |
1272 | struct mlx5_vport *vport; |
1273 | unsigned long i; | |
ac004b83 RD |
1274 | |
1275 | flows = esw->fdb_table.offloads.peer_miss_rules; | |
1276 | ||
47dd7e60 PP |
1277 | mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) |
1278 | mlx5_del_flow_rules(flows[vport->index]); | |
ac004b83 | 1279 | |
47dd7e60 PP |
1280 | if (mlx5_ecpf_vport_exists(esw->dev)) { |
1281 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); | |
1282 | mlx5_del_flow_rules(flows[vport->index]); | |
1283 | } | |
81cd229c | 1284 | |
47dd7e60 PP |
1285 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { |
1286 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); | |
1287 | mlx5_del_flow_rules(flows[vport->index]); | |
1288 | } | |
ac004b83 RD |
1289 | kvfree(flows); |
1290 | } | |
1291 | ||
3aa33572 OG |
1292 | static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw) |
1293 | { | |
66958ed9 | 1294 | struct mlx5_flow_act flow_act = {0}; |
4c5009c5 | 1295 | struct mlx5_flow_destination dest = {}; |
74491de9 | 1296 | struct mlx5_flow_handle *flow_rule = NULL; |
c5bb1730 | 1297 | struct mlx5_flow_spec *spec; |
f80be543 MB |
1298 | void *headers_c; |
1299 | void *headers_v; | |
3aa33572 | 1300 | int err = 0; |
f80be543 MB |
1301 | u8 *dmac_c; |
1302 | u8 *dmac_v; | |
3aa33572 | 1303 | |
1b9a07ee | 1304 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
c5bb1730 | 1305 | if (!spec) { |
3aa33572 OG |
1306 | err = -ENOMEM; |
1307 | goto out; | |
1308 | } | |
1309 | ||
f80be543 MB |
1310 | spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS; |
1311 | headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1312 | outer_headers); | |
1313 | dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c, | |
1314 | outer_headers.dmac_47_16); | |
1315 | dmac_c[0] = 0x01; | |
1316 | ||
3aa33572 | 1317 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; |
a1b3839a | 1318 | dest.vport.num = esw->manager_vport; |
66958ed9 | 1319 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
3aa33572 | 1320 | |
39ac237c PB |
1321 | flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1322 | spec, &flow_act, &dest, 1); | |
3aa33572 OG |
1323 | if (IS_ERR(flow_rule)) { |
1324 | err = PTR_ERR(flow_rule); | |
f80be543 | 1325 | esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err); |
3aa33572 OG |
1326 | goto out; |
1327 | } | |
1328 | ||
f80be543 MB |
1329 | esw->fdb_table.offloads.miss_rule_uni = flow_rule; |
1330 | ||
1331 | headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1332 | outer_headers); | |
1333 | dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v, | |
1334 | outer_headers.dmac_47_16); | |
1335 | dmac_v[0] = 0x01; | |
39ac237c PB |
1336 | flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1337 | spec, &flow_act, &dest, 1); | |
f80be543 MB |
1338 | if (IS_ERR(flow_rule)) { |
1339 | err = PTR_ERR(flow_rule); | |
1340 | esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err); | |
1341 | mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni); | |
1342 | goto out; | |
1343 | } | |
1344 | ||
1345 | esw->fdb_table.offloads.miss_rule_multi = flow_rule; | |
1346 | ||
3aa33572 | 1347 | out: |
c5bb1730 | 1348 | kvfree(spec); |
3aa33572 OG |
1349 | return err; |
1350 | } | |
1351 | ||
11b717d6 PB |
1352 | struct mlx5_flow_handle * |
1353 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) | |
1354 | { | |
1355 | struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, }; | |
1356 | struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore; | |
1357 | struct mlx5_flow_context *flow_context; | |
1358 | struct mlx5_flow_handle *flow_rule; | |
1359 | struct mlx5_flow_destination dest; | |
1360 | struct mlx5_flow_spec *spec; | |
1361 | void *misc; | |
1362 | ||
60acc105 PB |
1363 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw)) |
1364 | return ERR_PTR(-EOPNOTSUPP); | |
1365 | ||
9f4d9283 | 1366 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
11b717d6 PB |
1367 | if (!spec) |
1368 | return ERR_PTR(-ENOMEM); | |
1369 | ||
1370 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1371 | misc_parameters_2); | |
1372 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
a91d98a0 | 1373 | ESW_REG_C0_USER_DATA_METADATA_MASK); |
11b717d6 PB |
1374 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, |
1375 | misc_parameters_2); | |
1376 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag); | |
1377 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; | |
6724e66b PB |
1378 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | |
1379 | MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; | |
1380 | flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id; | |
11b717d6 PB |
1381 | |
1382 | flow_context = &spec->flow_context; | |
1383 | flow_context->flags |= FLOW_CONTEXT_HAS_TAG; | |
1384 | flow_context->flow_tag = tag; | |
1385 | dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
1386 | dest.ft = esw->offloads.ft_offloads; | |
1387 | ||
1388 | flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1); | |
9f4d9283 | 1389 | kvfree(spec); |
11b717d6 PB |
1390 | |
1391 | if (IS_ERR(flow_rule)) | |
1392 | esw_warn(esw->dev, | |
1393 | "Failed to create restore rule for tag: %d, err(%d)\n", | |
1394 | tag, (int)PTR_ERR(flow_rule)); | |
1395 | ||
1396 | return flow_rule; | |
1397 | } | |
1398 | ||
1967ce6e | 1399 | #define MAX_PF_SQ 256 |
cd3d07e7 | 1400 | #define MAX_SQ_NVPORTS 32 |
1967ce6e | 1401 | |
a5641cb5 JL |
1402 | static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw, |
1403 | u32 *flow_group_in) | |
1404 | { | |
1405 | void *match_criteria = MLX5_ADDR_OF(create_flow_group_in, | |
1406 | flow_group_in, | |
1407 | match_criteria); | |
1408 | ||
1409 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
1410 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1411 | match_criteria_enable, | |
1412 | MLX5_MATCH_MISC_PARAMETERS_2); | |
1413 | ||
0f0d3827 PB |
1414 | MLX5_SET(fte_match_param, match_criteria, |
1415 | misc_parameters_2.metadata_reg_c_0, | |
1416 | mlx5_eswitch_get_vport_metadata_mask()); | |
a5641cb5 JL |
1417 | } else { |
1418 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1419 | match_criteria_enable, | |
1420 | MLX5_MATCH_MISC_PARAMETERS); | |
1421 | ||
1422 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, | |
1423 | misc_parameters.source_port); | |
1424 | } | |
1425 | } | |
1426 | ||
ae430332 | 1427 | #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) |
0a9e2307 | 1428 | static void esw_vport_tbl_put(struct mlx5_eswitch *esw) |
4c7f4028 CM |
1429 | { |
1430 | struct mlx5_vport_tbl_attr attr; | |
1431 | struct mlx5_vport *vport; | |
47dd7e60 | 1432 | unsigned long i; |
4c7f4028 CM |
1433 | |
1434 | attr.chain = 0; | |
1435 | attr.prio = 1; | |
47dd7e60 | 1436 | mlx5_esw_for_each_vport(esw, i, vport) { |
4c7f4028 | 1437 | attr.vport = vport->vport; |
c796bb7c | 1438 | attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
0a9e2307 | 1439 | mlx5_esw_vporttbl_put(esw, &attr); |
4c7f4028 CM |
1440 | } |
1441 | } | |
1442 | ||
0a9e2307 | 1443 | static int esw_vport_tbl_get(struct mlx5_eswitch *esw) |
4c7f4028 CM |
1444 | { |
1445 | struct mlx5_vport_tbl_attr attr; | |
1446 | struct mlx5_flow_table *fdb; | |
1447 | struct mlx5_vport *vport; | |
47dd7e60 | 1448 | unsigned long i; |
4c7f4028 CM |
1449 | |
1450 | attr.chain = 0; | |
1451 | attr.prio = 1; | |
47dd7e60 | 1452 | mlx5_esw_for_each_vport(esw, i, vport) { |
4c7f4028 | 1453 | attr.vport = vport->vport; |
c796bb7c | 1454 | attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
0a9e2307 | 1455 | fdb = mlx5_esw_vporttbl_get(esw, &attr); |
4c7f4028 CM |
1456 | if (IS_ERR(fdb)) |
1457 | goto out; | |
1458 | } | |
1459 | return 0; | |
1460 | ||
1461 | out: | |
0a9e2307 | 1462 | esw_vport_tbl_put(esw); |
4c7f4028 CM |
1463 | return PTR_ERR(fdb); |
1464 | } | |
1465 | ||
ae430332 AL |
1466 | #define fdb_modify_header_fwd_to_table_supported(esw) \ |
1467 | (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table)) | |
1468 | static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags) | |
1469 | { | |
1470 | struct mlx5_core_dev *dev = esw->dev; | |
1471 | ||
1472 | if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level)) | |
1473 | *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED; | |
1474 | ||
1475 | if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) && | |
1476 | esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) { | |
1477 | *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1478 | esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n"); | |
1479 | } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) { | |
1480 | *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1481 | esw_warn(dev, "Tc chains and priorities offload aren't supported\n"); | |
1482 | } else if (!fdb_modify_header_fwd_to_table_supported(esw)) { | |
1483 | /* Disabled when ttl workaround is needed, e.g | |
1484 | * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig | |
1485 | */ | |
1486 | esw_warn(dev, | |
1487 | "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n"); | |
1488 | *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1489 | } else { | |
1490 | *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1491 | esw_info(dev, "Supported tc chains and prios offload\n"); | |
1492 | } | |
1493 | ||
1494 | if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) | |
1495 | *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED; | |
1496 | } | |
1497 | ||
1498 | static int | |
1499 | esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb) | |
1500 | { | |
1501 | struct mlx5_core_dev *dev = esw->dev; | |
1502 | struct mlx5_flow_table *nf_ft, *ft; | |
1503 | struct mlx5_chains_attr attr = {}; | |
1504 | struct mlx5_fs_chains *chains; | |
1505 | u32 fdb_max; | |
1506 | int err; | |
1507 | ||
1508 | fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size); | |
1509 | ||
1510 | esw_init_chains_offload_flags(esw, &attr.flags); | |
1511 | attr.ns = MLX5_FLOW_NAMESPACE_FDB; | |
1512 | attr.max_ft_sz = fdb_max; | |
1513 | attr.max_grp_num = esw->params.large_group_num; | |
1514 | attr.default_ft = miss_fdb; | |
c9355682 | 1515 | attr.mapping = esw->offloads.reg_c0_obj_pool; |
ae430332 AL |
1516 | |
1517 | chains = mlx5_chains_create(dev, &attr); | |
1518 | if (IS_ERR(chains)) { | |
1519 | err = PTR_ERR(chains); | |
1520 | esw_warn(dev, "Failed to create fdb chains err(%d)\n", err); | |
1521 | return err; | |
1522 | } | |
1523 | ||
1524 | esw->fdb_table.offloads.esw_chains_priv = chains; | |
1525 | ||
1526 | /* Create tc_end_ft which is the always created ft chain */ | |
1527 | nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains), | |
1528 | 1, 0); | |
1529 | if (IS_ERR(nf_ft)) { | |
1530 | err = PTR_ERR(nf_ft); | |
1531 | goto nf_ft_err; | |
1532 | } | |
1533 | ||
1534 | /* Always open the root for fast path */ | |
1535 | ft = mlx5_chains_get_table(chains, 0, 1, 0); | |
1536 | if (IS_ERR(ft)) { | |
1537 | err = PTR_ERR(ft); | |
1538 | goto level_0_err; | |
1539 | } | |
1540 | ||
1541 | /* Open level 1 for split fdb rules now if prios isn't supported */ | |
1542 | if (!mlx5_chains_prios_supported(chains)) { | |
0a9e2307 | 1543 | err = esw_vport_tbl_get(esw); |
ae430332 AL |
1544 | if (err) |
1545 | goto level_1_err; | |
1546 | } | |
1547 | ||
1548 | mlx5_chains_set_end_ft(chains, nf_ft); | |
1549 | ||
1550 | return 0; | |
1551 | ||
1552 | level_1_err: | |
1553 | mlx5_chains_put_table(chains, 0, 1, 0); | |
1554 | level_0_err: | |
1555 | mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0); | |
1556 | nf_ft_err: | |
1557 | mlx5_chains_destroy(chains); | |
1558 | esw->fdb_table.offloads.esw_chains_priv = NULL; | |
1559 | ||
1560 | return err; | |
1561 | } | |
1562 | ||
1563 | static void | |
1564 | esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains) | |
1565 | { | |
1566 | if (!mlx5_chains_prios_supported(chains)) | |
0a9e2307 | 1567 | esw_vport_tbl_put(esw); |
ae430332 AL |
1568 | mlx5_chains_put_table(chains, 0, 1, 0); |
1569 | mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0); | |
1570 | mlx5_chains_destroy(chains); | |
1571 | } | |
1572 | ||
1573 | #else /* CONFIG_MLX5_CLS_ACT */ | |
1574 | ||
1575 | static int | |
1576 | esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb) | |
1577 | { return 0; } | |
1578 | ||
1579 | static void | |
1580 | esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains) | |
1581 | {} | |
1582 | ||
1583 | #endif | |
1584 | ||
0da3c12d | 1585 | static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw) |
1967ce6e OG |
1586 | { |
1587 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); | |
1588 | struct mlx5_flow_table_attr ft_attr = {}; | |
8e404fef | 1589 | int num_vfs, table_size, ix, err = 0; |
1967ce6e OG |
1590 | struct mlx5_core_dev *dev = esw->dev; |
1591 | struct mlx5_flow_namespace *root_ns; | |
1592 | struct mlx5_flow_table *fdb = NULL; | |
39ac237c | 1593 | u32 flags = 0, *flow_group_in; |
1967ce6e OG |
1594 | struct mlx5_flow_group *g; |
1595 | void *match_criteria; | |
f80be543 | 1596 | u8 *dmac; |
1967ce6e OG |
1597 | |
1598 | esw_debug(esw->dev, "Create offloads FDB Tables\n"); | |
39ac237c | 1599 | |
1b9a07ee | 1600 | flow_group_in = kvzalloc(inlen, GFP_KERNEL); |
1967ce6e OG |
1601 | if (!flow_group_in) |
1602 | return -ENOMEM; | |
1603 | ||
1604 | root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB); | |
1605 | if (!root_ns) { | |
1606 | esw_warn(dev, "Failed to get FDB flow namespace\n"); | |
1607 | err = -EOPNOTSUPP; | |
1608 | goto ns_err; | |
1609 | } | |
8463daf1 MG |
1610 | esw->fdb_table.offloads.ns = root_ns; |
1611 | err = mlx5_flow_namespace_set_mode(root_ns, | |
1612 | esw->dev->priv.steering->mode); | |
1613 | if (err) { | |
1614 | esw_warn(dev, "Failed to set FDB namespace steering mode\n"); | |
1615 | goto ns_err; | |
1616 | } | |
1967ce6e | 1617 | |
898b0786 MB |
1618 | /* To be strictly correct: |
1619 | * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) | |
1620 | * should be: | |
1621 | * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ + | |
1622 | * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ | |
1623 | * but as the peer device might not be in switchdev mode it's not | |
1624 | * possible. We use the fact that by default FW sets max vfs and max sfs | |
1625 | * to the same value on both devices. If it needs to be changed in the future note | |
1626 | * the peer miss group should also be created based on the number of | |
1627 | * total vports of the peer (currently is also uses esw->total_vports). | |
1628 | */ | |
1629 | table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) + | |
8e404fef | 1630 | MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs; |
b3ba5149 | 1631 | |
e52c2802 PB |
1632 | /* create the slow path fdb with encap set, so further table instances |
1633 | * can be created at run time while VFs are probed if the FW allows that. | |
1634 | */ | |
1635 | if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) | |
1636 | flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT | | |
1637 | MLX5_FLOW_TABLE_TUNNEL_EN_DECAP); | |
1638 | ||
1639 | ft_attr.flags = flags; | |
b3ba5149 ES |
1640 | ft_attr.max_fte = table_size; |
1641 | ft_attr.prio = FDB_SLOW_PATH; | |
1642 | ||
1643 | fdb = mlx5_create_flow_table(root_ns, &ft_attr); | |
1033665e OG |
1644 | if (IS_ERR(fdb)) { |
1645 | err = PTR_ERR(fdb); | |
1646 | esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err); | |
1647 | goto slow_fdb_err; | |
1648 | } | |
52fff327 | 1649 | esw->fdb_table.offloads.slow_fdb = fdb; |
1033665e | 1650 | |
ec3be887 VB |
1651 | /* Create empty TC-miss managed table. This allows plugging in following |
1652 | * priorities without directly exposing their level 0 table to | |
1653 | * eswitch_offloads and passing it as miss_fdb to following call to | |
1654 | * esw_chains_create(). | |
1655 | */ | |
1656 | memset(&ft_attr, 0, sizeof(ft_attr)); | |
1657 | ft_attr.prio = FDB_TC_MISS; | |
1658 | esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr); | |
1659 | if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) { | |
1660 | err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table); | |
1661 | esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err); | |
1662 | goto tc_miss_table_err; | |
1663 | } | |
1664 | ||
1665 | err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table); | |
39ac237c | 1666 | if (err) { |
ae430332 | 1667 | esw_warn(dev, "Failed to open fdb chains err(%d)\n", err); |
39ac237c | 1668 | goto fdb_chains_err; |
e52c2802 PB |
1669 | } |
1670 | ||
69697b6e | 1671 | /* create send-to-vport group */ |
69697b6e OG |
1672 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, |
1673 | MLX5_MATCH_MISC_PARAMETERS); | |
1674 | ||
1675 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); | |
1676 | ||
1677 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn); | |
1678 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port); | |
7d97822a MB |
1679 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) { |
1680 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, | |
1681 | misc_parameters.source_eswitch_owner_vhca_id); | |
1682 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1683 | source_eswitch_owner_vhca_id_valid, 1); | |
1684 | } | |
69697b6e | 1685 | |
898b0786 MB |
1686 | /* See comment above table_size calculation */ |
1687 | ix = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ); | |
69697b6e OG |
1688 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); |
1689 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1); | |
1690 | ||
1691 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
1692 | if (IS_ERR(g)) { | |
1693 | err = PTR_ERR(g); | |
1694 | esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err); | |
1695 | goto send_vport_err; | |
1696 | } | |
1697 | esw->fdb_table.offloads.send_to_vport_grp = g; | |
1698 | ||
e929e3da MD |
1699 | if (esw_src_port_rewrite_supported(esw)) { |
1700 | /* meta send to vport */ | |
1701 | memset(flow_group_in, 0, inlen); | |
1702 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, | |
1703 | MLX5_MATCH_MISC_PARAMETERS_2); | |
8e404fef | 1704 | |
e929e3da | 1705 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); |
8e404fef | 1706 | |
e929e3da MD |
1707 | MLX5_SET(fte_match_param, match_criteria, |
1708 | misc_parameters_2.metadata_reg_c_0, | |
1709 | mlx5_eswitch_get_vport_metadata_mask()); | |
1710 | MLX5_SET(fte_match_param, match_criteria, | |
1711 | misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK); | |
1712 | ||
1713 | num_vfs = esw->esw_funcs.num_vfs; | |
1714 | if (num_vfs) { | |
1715 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix); | |
1716 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1717 | end_flow_index, ix + num_vfs - 1); | |
1718 | ix += num_vfs; | |
1719 | ||
1720 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
1721 | if (IS_ERR(g)) { | |
1722 | err = PTR_ERR(g); | |
1723 | esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n", | |
1724 | err); | |
1725 | goto send_vport_meta_err; | |
1726 | } | |
1727 | esw->fdb_table.offloads.send_to_vport_meta_grp = g; | |
1728 | ||
1729 | err = mlx5_eswitch_add_send_to_vport_meta_rules(esw); | |
1730 | if (err) | |
1731 | goto meta_rule_err; | |
8e404fef | 1732 | } |
8e404fef VB |
1733 | } |
1734 | ||
6cec0229 MD |
1735 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) { |
1736 | /* create peer esw miss group */ | |
1737 | memset(flow_group_in, 0, inlen); | |
ac004b83 | 1738 | |
6cec0229 | 1739 | esw_set_flow_group_source_port(esw, flow_group_in); |
a5641cb5 | 1740 | |
6cec0229 MD |
1741 | if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) { |
1742 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, | |
1743 | flow_group_in, | |
1744 | match_criteria); | |
ac004b83 | 1745 | |
6cec0229 MD |
1746 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, |
1747 | misc_parameters.source_eswitch_owner_vhca_id); | |
a5641cb5 | 1748 | |
6cec0229 MD |
1749 | MLX5_SET(create_flow_group_in, flow_group_in, |
1750 | source_eswitch_owner_vhca_id_valid, 1); | |
1751 | } | |
ac004b83 | 1752 | |
6cec0229 MD |
1753 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix); |
1754 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, | |
1755 | ix + esw->total_vports - 1); | |
1756 | ix += esw->total_vports; | |
ac004b83 | 1757 | |
6cec0229 MD |
1758 | g = mlx5_create_flow_group(fdb, flow_group_in); |
1759 | if (IS_ERR(g)) { | |
1760 | err = PTR_ERR(g); | |
1761 | esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err); | |
1762 | goto peer_miss_err; | |
1763 | } | |
1764 | esw->fdb_table.offloads.peer_miss_grp = g; | |
ac004b83 | 1765 | } |
ac004b83 | 1766 | |
69697b6e OG |
1767 | /* create miss group */ |
1768 | memset(flow_group_in, 0, inlen); | |
f80be543 MB |
1769 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, |
1770 | MLX5_MATCH_OUTER_HEADERS); | |
1771 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, | |
1772 | match_criteria); | |
1773 | dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, | |
1774 | outer_headers.dmac_47_16); | |
1775 | dmac[0] = 0x01; | |
69697b6e OG |
1776 | |
1777 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix); | |
cd7e4186 BW |
1778 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, |
1779 | ix + MLX5_ESW_MISS_FLOWS); | |
69697b6e OG |
1780 | |
1781 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
1782 | if (IS_ERR(g)) { | |
1783 | err = PTR_ERR(g); | |
1784 | esw_warn(dev, "Failed to create miss flow group err(%d)\n", err); | |
1785 | goto miss_err; | |
1786 | } | |
1787 | esw->fdb_table.offloads.miss_grp = g; | |
1788 | ||
3aa33572 OG |
1789 | err = esw_add_fdb_miss_rule(esw); |
1790 | if (err) | |
1791 | goto miss_rule_err; | |
1792 | ||
c88a026e | 1793 | kvfree(flow_group_in); |
69697b6e OG |
1794 | return 0; |
1795 | ||
3aa33572 OG |
1796 | miss_rule_err: |
1797 | mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp); | |
69697b6e | 1798 | miss_err: |
6cec0229 MD |
1799 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) |
1800 | mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp); | |
ac004b83 | 1801 | peer_miss_err: |
8e404fef VB |
1802 | mlx5_eswitch_del_send_to_vport_meta_rules(esw); |
1803 | meta_rule_err: | |
1804 | if (esw->fdb_table.offloads.send_to_vport_meta_grp) | |
1805 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp); | |
1806 | send_vport_meta_err: | |
69697b6e OG |
1807 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp); |
1808 | send_vport_err: | |
ae430332 | 1809 | esw_chains_destroy(esw, esw_chains(esw)); |
39ac237c | 1810 | fdb_chains_err: |
ec3be887 VB |
1811 | mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table); |
1812 | tc_miss_table_err: | |
52fff327 | 1813 | mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb); |
1033665e | 1814 | slow_fdb_err: |
8463daf1 MG |
1815 | /* Holds true only as long as DMFS is the default */ |
1816 | mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS); | |
69697b6e OG |
1817 | ns_err: |
1818 | kvfree(flow_group_in); | |
1819 | return err; | |
1820 | } | |
1821 | ||
1967ce6e | 1822 | static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw) |
69697b6e | 1823 | { |
e52c2802 | 1824 | if (!esw->fdb_table.offloads.slow_fdb) |
69697b6e OG |
1825 | return; |
1826 | ||
1967ce6e | 1827 | esw_debug(esw->dev, "Destroy offloads FDB Tables\n"); |
f80be543 MB |
1828 | mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi); |
1829 | mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni); | |
8e404fef | 1830 | mlx5_eswitch_del_send_to_vport_meta_rules(esw); |
69697b6e | 1831 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp); |
8e404fef VB |
1832 | if (esw->fdb_table.offloads.send_to_vport_meta_grp) |
1833 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp); | |
6cec0229 MD |
1834 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) |
1835 | mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp); | |
69697b6e OG |
1836 | mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp); |
1837 | ||
ae430332 AL |
1838 | esw_chains_destroy(esw, esw_chains(esw)); |
1839 | ||
ec3be887 | 1840 | mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table); |
52fff327 | 1841 | mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb); |
8463daf1 MG |
1842 | /* Holds true only as long as DMFS is the default */ |
1843 | mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns, | |
1844 | MLX5_FLOW_STEERING_MODE_DMFS); | |
7dc84de9 | 1845 | atomic64_set(&esw->user_count, 0); |
69697b6e | 1846 | } |
c116c6ee | 1847 | |
8d6bd3c3 | 1848 | static int esw_create_offloads_table(struct mlx5_eswitch *esw) |
c116c6ee | 1849 | { |
b3ba5149 | 1850 | struct mlx5_flow_table_attr ft_attr = {}; |
c116c6ee | 1851 | struct mlx5_core_dev *dev = esw->dev; |
b3ba5149 ES |
1852 | struct mlx5_flow_table *ft_offloads; |
1853 | struct mlx5_flow_namespace *ns; | |
c116c6ee OG |
1854 | int err = 0; |
1855 | ||
1856 | ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS); | |
1857 | if (!ns) { | |
1858 | esw_warn(esw->dev, "Failed to get offloads flow namespace\n"); | |
eff596da | 1859 | return -EOPNOTSUPP; |
c116c6ee OG |
1860 | } |
1861 | ||
8d6bd3c3 | 1862 | ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS; |
11b717d6 | 1863 | ft_attr.prio = 1; |
b3ba5149 ES |
1864 | |
1865 | ft_offloads = mlx5_create_flow_table(ns, &ft_attr); | |
c116c6ee OG |
1866 | if (IS_ERR(ft_offloads)) { |
1867 | err = PTR_ERR(ft_offloads); | |
1868 | esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err); | |
1869 | return err; | |
1870 | } | |
1871 | ||
1872 | esw->offloads.ft_offloads = ft_offloads; | |
1873 | return 0; | |
1874 | } | |
1875 | ||
1876 | static void esw_destroy_offloads_table(struct mlx5_eswitch *esw) | |
1877 | { | |
1878 | struct mlx5_esw_offload *offloads = &esw->offloads; | |
1879 | ||
1880 | mlx5_destroy_flow_table(offloads->ft_offloads); | |
1881 | } | |
fed9ce22 | 1882 | |
8d6bd3c3 | 1883 | static int esw_create_vport_rx_group(struct mlx5_eswitch *esw) |
fed9ce22 OG |
1884 | { |
1885 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); | |
1886 | struct mlx5_flow_group *g; | |
fed9ce22 | 1887 | u32 *flow_group_in; |
8d6bd3c3 | 1888 | int nvports; |
fed9ce22 | 1889 | int err = 0; |
fed9ce22 | 1890 | |
8d6bd3c3 | 1891 | nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS; |
1b9a07ee | 1892 | flow_group_in = kvzalloc(inlen, GFP_KERNEL); |
fed9ce22 OG |
1893 | if (!flow_group_in) |
1894 | return -ENOMEM; | |
1895 | ||
1896 | /* create vport rx group */ | |
a5641cb5 | 1897 | esw_set_flow_group_source_port(esw, flow_group_in); |
fed9ce22 OG |
1898 | |
1899 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); | |
1900 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1); | |
1901 | ||
1902 | g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in); | |
1903 | ||
1904 | if (IS_ERR(g)) { | |
1905 | err = PTR_ERR(g); | |
1906 | mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err); | |
1907 | goto out; | |
1908 | } | |
1909 | ||
1910 | esw->offloads.vport_rx_group = g; | |
1911 | out: | |
e574978a | 1912 | kvfree(flow_group_in); |
fed9ce22 OG |
1913 | return err; |
1914 | } | |
1915 | ||
1916 | static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw) | |
1917 | { | |
1918 | mlx5_destroy_flow_group(esw->offloads.vport_rx_group); | |
1919 | } | |
1920 | ||
74491de9 | 1921 | struct mlx5_flow_handle * |
02f3afd9 | 1922 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 1923 | struct mlx5_flow_destination *dest) |
fed9ce22 | 1924 | { |
66958ed9 | 1925 | struct mlx5_flow_act flow_act = {0}; |
74491de9 | 1926 | struct mlx5_flow_handle *flow_rule; |
c5bb1730 | 1927 | struct mlx5_flow_spec *spec; |
fed9ce22 OG |
1928 | void *misc; |
1929 | ||
1b9a07ee | 1930 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
c5bb1730 | 1931 | if (!spec) { |
fed9ce22 OG |
1932 | flow_rule = ERR_PTR(-ENOMEM); |
1933 | goto out; | |
1934 | } | |
1935 | ||
a5641cb5 JL |
1936 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { |
1937 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); | |
1938 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
1939 | mlx5_eswitch_get_vport_metadata_for_match(esw, vport)); | |
fed9ce22 | 1940 | |
a5641cb5 | 1941 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); |
0f0d3827 PB |
1942 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, |
1943 | mlx5_eswitch_get_vport_metadata_mask()); | |
fed9ce22 | 1944 | |
a5641cb5 JL |
1945 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; |
1946 | } else { | |
1947 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); | |
1948 | MLX5_SET(fte_match_set_misc, misc, source_port, vport); | |
1949 | ||
1950 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters); | |
1951 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
1952 | ||
1953 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS; | |
1954 | } | |
fed9ce22 | 1955 | |
66958ed9 | 1956 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
74491de9 | 1957 | flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec, |
c966f7d5 | 1958 | &flow_act, dest, 1); |
fed9ce22 OG |
1959 | if (IS_ERR(flow_rule)) { |
1960 | esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule)); | |
1961 | goto out; | |
1962 | } | |
1963 | ||
1964 | out: | |
c5bb1730 | 1965 | kvfree(spec); |
fed9ce22 OG |
1966 | return flow_rule; |
1967 | } | |
feae9087 | 1968 | |
47dd7e60 | 1969 | static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode) |
cc617ced PP |
1970 | { |
1971 | u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2; | |
1972 | struct mlx5_core_dev *dev = esw->dev; | |
47dd7e60 PP |
1973 | struct mlx5_vport *vport; |
1974 | unsigned long i; | |
cc617ced PP |
1975 | |
1976 | if (!MLX5_CAP_GEN(dev, vport_group_manager)) | |
1977 | return -EOPNOTSUPP; | |
1978 | ||
1979 | if (esw->mode == MLX5_ESWITCH_NONE) | |
1980 | return -EOPNOTSUPP; | |
1981 | ||
1982 | switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { | |
1983 | case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: | |
1984 | mlx5_mode = MLX5_INLINE_MODE_NONE; | |
1985 | goto out; | |
1986 | case MLX5_CAP_INLINE_MODE_L2: | |
1987 | mlx5_mode = MLX5_INLINE_MODE_L2; | |
1988 | goto out; | |
1989 | case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: | |
1990 | goto query_vports; | |
1991 | } | |
1992 | ||
1993 | query_vports: | |
1994 | mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode); | |
47dd7e60 PP |
1995 | mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) { |
1996 | mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode); | |
cc617ced PP |
1997 | if (prev_mlx5_mode != mlx5_mode) |
1998 | return -EINVAL; | |
1999 | prev_mlx5_mode = mlx5_mode; | |
2000 | } | |
2001 | ||
2002 | out: | |
2003 | *mode = mlx5_mode; | |
2004 | return 0; | |
e08a6832 | 2005 | } |
bf3347c4 | 2006 | |
11b717d6 PB |
2007 | static void esw_destroy_restore_table(struct mlx5_eswitch *esw) |
2008 | { | |
2009 | struct mlx5_esw_offload *offloads = &esw->offloads; | |
2010 | ||
60acc105 PB |
2011 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw)) |
2012 | return; | |
2013 | ||
6724e66b | 2014 | mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id); |
11b717d6 PB |
2015 | mlx5_destroy_flow_group(offloads->restore_group); |
2016 | mlx5_destroy_flow_table(offloads->ft_offloads_restore); | |
2017 | } | |
2018 | ||
2019 | static int esw_create_restore_table(struct mlx5_eswitch *esw) | |
2020 | { | |
d65dbedf | 2021 | u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {}; |
11b717d6 PB |
2022 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); |
2023 | struct mlx5_flow_table_attr ft_attr = {}; | |
2024 | struct mlx5_core_dev *dev = esw->dev; | |
2025 | struct mlx5_flow_namespace *ns; | |
6724e66b | 2026 | struct mlx5_modify_hdr *mod_hdr; |
11b717d6 PB |
2027 | void *match_criteria, *misc; |
2028 | struct mlx5_flow_table *ft; | |
2029 | struct mlx5_flow_group *g; | |
2030 | u32 *flow_group_in; | |
2031 | int err = 0; | |
2032 | ||
60acc105 PB |
2033 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw)) |
2034 | return 0; | |
2035 | ||
11b717d6 PB |
2036 | ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS); |
2037 | if (!ns) { | |
2038 | esw_warn(esw->dev, "Failed to get offloads flow namespace\n"); | |
2039 | return -EOPNOTSUPP; | |
2040 | } | |
2041 | ||
2042 | flow_group_in = kvzalloc(inlen, GFP_KERNEL); | |
2043 | if (!flow_group_in) { | |
2044 | err = -ENOMEM; | |
2045 | goto out_free; | |
2046 | } | |
2047 | ||
a91d98a0 | 2048 | ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS; |
11b717d6 PB |
2049 | ft = mlx5_create_flow_table(ns, &ft_attr); |
2050 | if (IS_ERR(ft)) { | |
2051 | err = PTR_ERR(ft); | |
2052 | esw_warn(esw->dev, "Failed to create restore table, err %d\n", | |
2053 | err); | |
2054 | goto out_free; | |
2055 | } | |
2056 | ||
11b717d6 PB |
2057 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, |
2058 | match_criteria); | |
2059 | misc = MLX5_ADDR_OF(fte_match_param, match_criteria, | |
2060 | misc_parameters_2); | |
2061 | ||
2062 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
a91d98a0 | 2063 | ESW_REG_C0_USER_DATA_METADATA_MASK); |
11b717d6 PB |
2064 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); |
2065 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, | |
2066 | ft_attr.max_fte - 1); | |
2067 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, | |
2068 | MLX5_MATCH_MISC_PARAMETERS_2); | |
2069 | g = mlx5_create_flow_group(ft, flow_group_in); | |
2070 | if (IS_ERR(g)) { | |
2071 | err = PTR_ERR(g); | |
2072 | esw_warn(dev, "Failed to create restore flow group, err: %d\n", | |
2073 | err); | |
2074 | goto err_group; | |
2075 | } | |
2076 | ||
6724e66b PB |
2077 | MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY); |
2078 | MLX5_SET(copy_action_in, modact, src_field, | |
2079 | MLX5_ACTION_IN_FIELD_METADATA_REG_C_1); | |
2080 | MLX5_SET(copy_action_in, modact, dst_field, | |
2081 | MLX5_ACTION_IN_FIELD_METADATA_REG_B); | |
2082 | mod_hdr = mlx5_modify_header_alloc(esw->dev, | |
2083 | MLX5_FLOW_NAMESPACE_KERNEL, 1, | |
2084 | modact); | |
2085 | if (IS_ERR(mod_hdr)) { | |
e9864539 | 2086 | err = PTR_ERR(mod_hdr); |
6724e66b PB |
2087 | esw_warn(dev, "Failed to create restore mod header, err: %d\n", |
2088 | err); | |
6724e66b PB |
2089 | goto err_mod_hdr; |
2090 | } | |
2091 | ||
11b717d6 PB |
2092 | esw->offloads.ft_offloads_restore = ft; |
2093 | esw->offloads.restore_group = g; | |
6724e66b | 2094 | esw->offloads.restore_copy_hdr_id = mod_hdr; |
11b717d6 | 2095 | |
c8508713 RD |
2096 | kvfree(flow_group_in); |
2097 | ||
11b717d6 PB |
2098 | return 0; |
2099 | ||
6724e66b PB |
2100 | err_mod_hdr: |
2101 | mlx5_destroy_flow_group(g); | |
11b717d6 PB |
2102 | err_group: |
2103 | mlx5_destroy_flow_table(ft); | |
2104 | out_free: | |
2105 | kvfree(flow_group_in); | |
2106 | ||
2107 | return err; | |
cc617ced PP |
2108 | } |
2109 | ||
db7ff19e EB |
2110 | static int esw_offloads_start(struct mlx5_eswitch *esw, |
2111 | struct netlink_ext_ack *extack) | |
c930a3ad | 2112 | { |
062f4bf4 | 2113 | int err, err1; |
c930a3ad | 2114 | |
8e0aa4bc PP |
2115 | mlx5_eswitch_disable_locked(esw, false); |
2116 | err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS, | |
2117 | esw->dev->priv.sriov.num_vfs); | |
6c419ba8 | 2118 | if (err) { |
8c98ee77 EB |
2119 | NL_SET_ERR_MSG_MOD(extack, |
2120 | "Failed setting eswitch to offloads"); | |
8e0aa4bc PP |
2121 | err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY, |
2122 | MLX5_ESWITCH_IGNORE_NUM_VFS); | |
8c98ee77 EB |
2123 | if (err1) { |
2124 | NL_SET_ERR_MSG_MOD(extack, | |
2125 | "Failed setting eswitch back to legacy"); | |
2126 | } | |
6c419ba8 | 2127 | } |
bffaa916 RD |
2128 | if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) { |
2129 | if (mlx5_eswitch_inline_mode_get(esw, | |
bffaa916 RD |
2130 | &esw->offloads.inline_mode)) { |
2131 | esw->offloads.inline_mode = MLX5_INLINE_MODE_L2; | |
8c98ee77 EB |
2132 | NL_SET_ERR_MSG_MOD(extack, |
2133 | "Inline mode is different between vports"); | |
bffaa916 RD |
2134 | } |
2135 | } | |
c930a3ad OG |
2136 | return err; |
2137 | } | |
2138 | ||
47dd7e60 PP |
2139 | static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw, |
2140 | struct mlx5_eswitch_rep *rep, | |
2141 | xa_mark_t mark) | |
e8d31c4d | 2142 | { |
47dd7e60 PP |
2143 | bool mark_set; |
2144 | ||
2145 | /* Copy the mark from vport to its rep */ | |
2146 | mark_set = xa_get_mark(&esw->vports, rep->vport, mark); | |
2147 | if (mark_set) | |
2148 | xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark); | |
e8d31c4d MB |
2149 | } |
2150 | ||
47dd7e60 | 2151 | static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport) |
e8d31c4d | 2152 | { |
e8d31c4d | 2153 | struct mlx5_eswitch_rep *rep; |
47dd7e60 PP |
2154 | int rep_type; |
2155 | int err; | |
e8d31c4d | 2156 | |
47dd7e60 PP |
2157 | rep = kzalloc(sizeof(*rep), GFP_KERNEL); |
2158 | if (!rep) | |
e8d31c4d MB |
2159 | return -ENOMEM; |
2160 | ||
47dd7e60 PP |
2161 | rep->vport = vport->vport; |
2162 | rep->vport_index = vport->index; | |
2163 | for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) | |
2164 | atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED); | |
f121e0ea | 2165 | |
47dd7e60 PP |
2166 | err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL); |
2167 | if (err) | |
2168 | goto insert_err; | |
2169 | ||
2170 | mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN); | |
2171 | mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF); | |
2172 | mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF); | |
2173 | return 0; | |
2174 | ||
2175 | insert_err: | |
2176 | kfree(rep); | |
2177 | return err; | |
2178 | } | |
2179 | ||
2180 | static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw, | |
2181 | struct mlx5_eswitch_rep *rep) | |
2182 | { | |
2183 | xa_erase(&esw->offloads.vport_reps, rep->vport); | |
2184 | kfree(rep); | |
2185 | } | |
2186 | ||
2187 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw) | |
2188 | { | |
2189 | struct mlx5_eswitch_rep *rep; | |
2190 | unsigned long i; | |
e8d31c4d | 2191 | |
47dd7e60 PP |
2192 | mlx5_esw_for_each_rep(esw, i, rep) |
2193 | mlx5_esw_offloads_rep_cleanup(esw, rep); | |
2194 | xa_destroy(&esw->offloads.vport_reps); | |
2195 | } | |
2196 | ||
2197 | int esw_offloads_init_reps(struct mlx5_eswitch *esw) | |
2198 | { | |
2199 | struct mlx5_vport *vport; | |
2200 | unsigned long i; | |
2201 | int err; | |
2202 | ||
2203 | xa_init(&esw->offloads.vport_reps); | |
2204 | ||
2205 | mlx5_esw_for_each_vport(esw, i, vport) { | |
2206 | err = mlx5_esw_offloads_rep_init(esw, vport); | |
2207 | if (err) | |
2208 | goto err; | |
2209 | } | |
e8d31c4d | 2210 | return 0; |
47dd7e60 PP |
2211 | |
2212 | err: | |
2213 | esw_offloads_cleanup_reps(esw); | |
2214 | return err; | |
e8d31c4d MB |
2215 | } |
2216 | ||
c9b99abc BW |
2217 | static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw, |
2218 | struct mlx5_eswitch_rep *rep, u8 rep_type) | |
2219 | { | |
8693115a | 2220 | if (atomic_cmpxchg(&rep->rep_data[rep_type].state, |
6f4e0219 | 2221 | REP_LOADED, REP_REGISTERED) == REP_LOADED) |
8693115a | 2222 | esw->offloads.rep_ops[rep_type]->unload(rep); |
c9b99abc BW |
2223 | } |
2224 | ||
d7f33a45 VP |
2225 | static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type) |
2226 | { | |
2227 | struct mlx5_eswitch_rep *rep; | |
47dd7e60 | 2228 | unsigned long i; |
d7f33a45 VP |
2229 | |
2230 | mlx5_esw_for_each_sf_rep(esw, i, rep) | |
2231 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2232 | } | |
2233 | ||
4110fc59 | 2234 | static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type) |
6ed1803a MB |
2235 | { |
2236 | struct mlx5_eswitch_rep *rep; | |
47dd7e60 | 2237 | unsigned long i; |
4110fc59 | 2238 | |
d7f33a45 VP |
2239 | __unload_reps_sf_vport(esw, rep_type); |
2240 | ||
47dd7e60 | 2241 | mlx5_esw_for_each_vf_rep(esw, i, rep) |
4110fc59 | 2242 | __esw_offloads_unload_rep(esw, rep, rep_type); |
c9b99abc | 2243 | |
81cd229c BW |
2244 | if (mlx5_ecpf_vport_exists(esw->dev)) { |
2245 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF); | |
2246 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2247 | } | |
2248 | ||
2249 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { | |
2250 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF); | |
2251 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2252 | } | |
2253 | ||
879c8f84 | 2254 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK); |
c9b99abc | 2255 | __esw_offloads_unload_rep(esw, rep, rep_type); |
6ed1803a MB |
2256 | } |
2257 | ||
d970812b | 2258 | int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num) |
a4b97ab4 | 2259 | { |
c2d7712c BW |
2260 | struct mlx5_eswitch_rep *rep; |
2261 | int rep_type; | |
a4b97ab4 MB |
2262 | int err; |
2263 | ||
c2d7712c BW |
2264 | rep = mlx5_eswitch_get_rep(esw, vport_num); |
2265 | for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) | |
2266 | if (atomic_cmpxchg(&rep->rep_data[rep_type].state, | |
2267 | REP_REGISTERED, REP_LOADED) == REP_REGISTERED) { | |
2268 | err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep); | |
2269 | if (err) | |
2270 | goto err_reps; | |
2271 | } | |
2272 | ||
2273 | return 0; | |
a4b97ab4 MB |
2274 | |
2275 | err_reps: | |
c2d7712c BW |
2276 | atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED); |
2277 | for (--rep_type; rep_type >= 0; rep_type--) | |
2278 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
6ed1803a MB |
2279 | return err; |
2280 | } | |
2281 | ||
d970812b | 2282 | void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num) |
c2d7712c BW |
2283 | { |
2284 | struct mlx5_eswitch_rep *rep; | |
2285 | int rep_type; | |
2286 | ||
c2d7712c BW |
2287 | rep = mlx5_eswitch_get_rep(esw, vport_num); |
2288 | for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--) | |
2289 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2290 | } | |
2291 | ||
38679b5a PP |
2292 | int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num) |
2293 | { | |
2294 | int err; | |
2295 | ||
2296 | if (esw->mode != MLX5_ESWITCH_OFFLOADS) | |
2297 | return 0; | |
2298 | ||
865d6d1c RD |
2299 | if (vport_num != MLX5_VPORT_UPLINK) { |
2300 | err = mlx5_esw_offloads_devlink_port_register(esw, vport_num); | |
2301 | if (err) | |
2302 | return err; | |
2303 | } | |
c7eddc60 | 2304 | |
38679b5a | 2305 | err = mlx5_esw_offloads_rep_load(esw, vport_num); |
c7eddc60 PP |
2306 | if (err) |
2307 | goto load_err; | |
2308 | return err; | |
2309 | ||
2310 | load_err: | |
865d6d1c RD |
2311 | if (vport_num != MLX5_VPORT_UPLINK) |
2312 | mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); | |
38679b5a PP |
2313 | return err; |
2314 | } | |
2315 | ||
2316 | void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num) | |
2317 | { | |
2318 | if (esw->mode != MLX5_ESWITCH_OFFLOADS) | |
2319 | return; | |
2320 | ||
2321 | mlx5_esw_offloads_rep_unload(esw, vport_num); | |
865d6d1c RD |
2322 | |
2323 | if (vport_num != MLX5_VPORT_UPLINK) | |
2324 | mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); | |
38679b5a PP |
2325 | } |
2326 | ||
db202995 MB |
2327 | static int esw_set_uplink_slave_ingress_root(struct mlx5_core_dev *master, |
2328 | struct mlx5_core_dev *slave) | |
2329 | { | |
2330 | u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {}; | |
2331 | u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {}; | |
2332 | struct mlx5_eswitch *esw; | |
2333 | struct mlx5_flow_root_namespace *root; | |
2334 | struct mlx5_flow_namespace *ns; | |
2335 | struct mlx5_vport *vport; | |
2336 | int err; | |
2337 | ||
2338 | MLX5_SET(set_flow_table_root_in, in, opcode, | |
2339 | MLX5_CMD_OP_SET_FLOW_TABLE_ROOT); | |
2340 | MLX5_SET(set_flow_table_root_in, in, table_type, FS_FT_ESW_INGRESS_ACL); | |
2341 | MLX5_SET(set_flow_table_root_in, in, other_vport, 1); | |
2342 | MLX5_SET(set_flow_table_root_in, in, vport_number, MLX5_VPORT_UPLINK); | |
2343 | ||
2344 | if (master) { | |
2345 | esw = master->priv.eswitch; | |
2346 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK); | |
2347 | MLX5_SET(set_flow_table_root_in, in, table_of_other_vport, 1); | |
2348 | MLX5_SET(set_flow_table_root_in, in, table_vport_number, | |
2349 | MLX5_VPORT_UPLINK); | |
2350 | ||
2351 | ns = mlx5_get_flow_vport_acl_namespace(master, | |
2352 | MLX5_FLOW_NAMESPACE_ESW_INGRESS, | |
2353 | vport->index); | |
2354 | root = find_root(&ns->node); | |
2355 | mutex_lock(&root->chain_lock); | |
2356 | ||
2357 | MLX5_SET(set_flow_table_root_in, in, | |
2358 | table_eswitch_owner_vhca_id_valid, 1); | |
2359 | MLX5_SET(set_flow_table_root_in, in, | |
2360 | table_eswitch_owner_vhca_id, | |
2361 | MLX5_CAP_GEN(master, vhca_id)); | |
2362 | MLX5_SET(set_flow_table_root_in, in, table_id, | |
2363 | root->root_ft->id); | |
2364 | } else { | |
2365 | esw = slave->priv.eswitch; | |
2366 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK); | |
2367 | ns = mlx5_get_flow_vport_acl_namespace(slave, | |
2368 | MLX5_FLOW_NAMESPACE_ESW_INGRESS, | |
2369 | vport->index); | |
2370 | root = find_root(&ns->node); | |
2371 | mutex_lock(&root->chain_lock); | |
2372 | MLX5_SET(set_flow_table_root_in, in, table_id, root->root_ft->id); | |
2373 | } | |
2374 | ||
2375 | err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out)); | |
2376 | mutex_unlock(&root->chain_lock); | |
2377 | ||
2378 | return err; | |
2379 | } | |
2380 | ||
2381 | static int esw_set_slave_root_fdb(struct mlx5_core_dev *master, | |
2382 | struct mlx5_core_dev *slave) | |
2383 | { | |
2384 | u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {}; | |
2385 | u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {}; | |
2386 | struct mlx5_flow_root_namespace *root; | |
2387 | struct mlx5_flow_namespace *ns; | |
2388 | int err; | |
2389 | ||
2390 | MLX5_SET(set_flow_table_root_in, in, opcode, | |
2391 | MLX5_CMD_OP_SET_FLOW_TABLE_ROOT); | |
2392 | MLX5_SET(set_flow_table_root_in, in, table_type, | |
2393 | FS_FT_FDB); | |
2394 | ||
2395 | if (master) { | |
2396 | ns = mlx5_get_flow_namespace(master, | |
2397 | MLX5_FLOW_NAMESPACE_FDB); | |
2398 | root = find_root(&ns->node); | |
2399 | mutex_lock(&root->chain_lock); | |
2400 | MLX5_SET(set_flow_table_root_in, in, | |
2401 | table_eswitch_owner_vhca_id_valid, 1); | |
2402 | MLX5_SET(set_flow_table_root_in, in, | |
2403 | table_eswitch_owner_vhca_id, | |
2404 | MLX5_CAP_GEN(master, vhca_id)); | |
2405 | MLX5_SET(set_flow_table_root_in, in, table_id, | |
2406 | root->root_ft->id); | |
2407 | } else { | |
2408 | ns = mlx5_get_flow_namespace(slave, | |
2409 | MLX5_FLOW_NAMESPACE_FDB); | |
2410 | root = find_root(&ns->node); | |
2411 | mutex_lock(&root->chain_lock); | |
2412 | MLX5_SET(set_flow_table_root_in, in, table_id, | |
2413 | root->root_ft->id); | |
2414 | } | |
2415 | ||
2416 | err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out)); | |
2417 | mutex_unlock(&root->chain_lock); | |
2418 | ||
2419 | return err; | |
2420 | } | |
2421 | ||
2422 | static int __esw_set_master_egress_rule(struct mlx5_core_dev *master, | |
2423 | struct mlx5_core_dev *slave, | |
2424 | struct mlx5_vport *vport, | |
2425 | struct mlx5_flow_table *acl) | |
2426 | { | |
2427 | struct mlx5_flow_handle *flow_rule = NULL; | |
2428 | struct mlx5_flow_destination dest = {}; | |
2429 | struct mlx5_flow_act flow_act = {}; | |
2430 | struct mlx5_flow_spec *spec; | |
2431 | int err = 0; | |
2432 | void *misc; | |
2433 | ||
2434 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); | |
2435 | if (!spec) | |
2436 | return -ENOMEM; | |
2437 | ||
2438 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS; | |
2439 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
2440 | misc_parameters); | |
2441 | MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK); | |
2442 | MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, | |
2443 | MLX5_CAP_GEN(slave, vhca_id)); | |
2444 | ||
2445 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters); | |
2446 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
2447 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, | |
2448 | source_eswitch_owner_vhca_id); | |
2449 | ||
2450 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
2451 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
2452 | dest.vport.num = slave->priv.eswitch->manager_vport; | |
2453 | dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id); | |
2454 | dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID; | |
2455 | ||
2456 | flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act, | |
2457 | &dest, 1); | |
2458 | if (IS_ERR(flow_rule)) | |
2459 | err = PTR_ERR(flow_rule); | |
2460 | else | |
2461 | vport->egress.offloads.bounce_rule = flow_rule; | |
2462 | ||
2463 | kvfree(spec); | |
2464 | return err; | |
2465 | } | |
2466 | ||
2467 | static int esw_set_master_egress_rule(struct mlx5_core_dev *master, | |
2468 | struct mlx5_core_dev *slave) | |
2469 | { | |
2470 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); | |
2471 | struct mlx5_eswitch *esw = master->priv.eswitch; | |
2472 | struct mlx5_flow_table_attr ft_attr = { | |
2473 | .max_fte = 1, .prio = 0, .level = 0, | |
037b01c2 | 2474 | .flags = MLX5_FLOW_TABLE_OTHER_VPORT, |
db202995 MB |
2475 | }; |
2476 | struct mlx5_flow_namespace *egress_ns; | |
2477 | struct mlx5_flow_table *acl; | |
2478 | struct mlx5_flow_group *g; | |
2479 | struct mlx5_vport *vport; | |
2480 | void *match_criteria; | |
2481 | u32 *flow_group_in; | |
2482 | int err; | |
2483 | ||
2484 | vport = mlx5_eswitch_get_vport(esw, esw->manager_vport); | |
2485 | if (IS_ERR(vport)) | |
2486 | return PTR_ERR(vport); | |
2487 | ||
2488 | egress_ns = mlx5_get_flow_vport_acl_namespace(master, | |
2489 | MLX5_FLOW_NAMESPACE_ESW_EGRESS, | |
2490 | vport->index); | |
2491 | if (!egress_ns) | |
2492 | return -EINVAL; | |
2493 | ||
2494 | if (vport->egress.acl) | |
2495 | return -EINVAL; | |
2496 | ||
2497 | flow_group_in = kvzalloc(inlen, GFP_KERNEL); | |
2498 | if (!flow_group_in) | |
2499 | return -ENOMEM; | |
2500 | ||
2501 | acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport); | |
2502 | if (IS_ERR(acl)) { | |
2503 | err = PTR_ERR(acl); | |
2504 | goto out; | |
2505 | } | |
2506 | ||
2507 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, | |
2508 | match_criteria); | |
2509 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, | |
2510 | misc_parameters.source_port); | |
2511 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, | |
2512 | misc_parameters.source_eswitch_owner_vhca_id); | |
2513 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, | |
2514 | MLX5_MATCH_MISC_PARAMETERS); | |
2515 | ||
2516 | MLX5_SET(create_flow_group_in, flow_group_in, | |
2517 | source_eswitch_owner_vhca_id_valid, 1); | |
2518 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); | |
2519 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0); | |
2520 | ||
2521 | g = mlx5_create_flow_group(acl, flow_group_in); | |
2522 | if (IS_ERR(g)) { | |
2523 | err = PTR_ERR(g); | |
2524 | goto err_group; | |
2525 | } | |
2526 | ||
2527 | err = __esw_set_master_egress_rule(master, slave, vport, acl); | |
2528 | if (err) | |
2529 | goto err_rule; | |
2530 | ||
2531 | vport->egress.acl = acl; | |
2532 | vport->egress.offloads.bounce_grp = g; | |
2533 | ||
2534 | kvfree(flow_group_in); | |
2535 | ||
2536 | return 0; | |
2537 | ||
2538 | err_rule: | |
2539 | mlx5_destroy_flow_group(g); | |
2540 | err_group: | |
2541 | mlx5_destroy_flow_table(acl); | |
2542 | out: | |
2543 | kvfree(flow_group_in); | |
2544 | return err; | |
2545 | } | |
2546 | ||
2547 | static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev) | |
2548 | { | |
2549 | struct mlx5_vport *vport; | |
2550 | ||
2551 | vport = mlx5_eswitch_get_vport(dev->priv.eswitch, | |
2552 | dev->priv.eswitch->manager_vport); | |
2553 | ||
2554 | esw_acl_egress_ofld_cleanup(vport); | |
2555 | } | |
2556 | ||
2557 | int mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw, | |
2558 | struct mlx5_eswitch *slave_esw) | |
2559 | { | |
2560 | int err; | |
2561 | ||
2562 | err = esw_set_uplink_slave_ingress_root(master_esw->dev, | |
2563 | slave_esw->dev); | |
2564 | if (err) | |
2565 | return -EINVAL; | |
2566 | ||
2567 | err = esw_set_slave_root_fdb(master_esw->dev, | |
2568 | slave_esw->dev); | |
2569 | if (err) | |
2570 | goto err_fdb; | |
2571 | ||
2572 | err = esw_set_master_egress_rule(master_esw->dev, | |
2573 | slave_esw->dev); | |
2574 | if (err) | |
2575 | goto err_acl; | |
2576 | ||
2577 | return err; | |
2578 | ||
2579 | err_acl: | |
2580 | esw_set_slave_root_fdb(NULL, slave_esw->dev); | |
2581 | ||
2582 | err_fdb: | |
2583 | esw_set_uplink_slave_ingress_root(NULL, slave_esw->dev); | |
2584 | ||
2585 | return err; | |
2586 | } | |
2587 | ||
2588 | void mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw, | |
2589 | struct mlx5_eswitch *slave_esw) | |
2590 | { | |
2591 | esw_unset_master_egress_rule(master_esw->dev); | |
2592 | esw_set_slave_root_fdb(NULL, slave_esw->dev); | |
2593 | esw_set_uplink_slave_ingress_root(NULL, slave_esw->dev); | |
2594 | } | |
2595 | ||
ac004b83 RD |
2596 | #define ESW_OFFLOADS_DEVCOM_PAIR (0) |
2597 | #define ESW_OFFLOADS_DEVCOM_UNPAIR (1) | |
2598 | ||
c8e6a9e6 | 2599 | static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw) |
ac004b83 | 2600 | { |
c8e6a9e6 MB |
2601 | const struct mlx5_eswitch_rep_ops *ops; |
2602 | struct mlx5_eswitch_rep *rep; | |
2603 | unsigned long i; | |
2604 | u8 rep_type; | |
2605 | ||
2606 | mlx5_esw_for_each_rep(esw, i, rep) { | |
2607 | rep_type = NUM_REP_TYPES; | |
2608 | while (rep_type--) { | |
2609 | ops = esw->offloads.rep_ops[rep_type]; | |
2610 | if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED && | |
2611 | ops->event) | |
2612 | ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, NULL); | |
2613 | } | |
2614 | } | |
ac004b83 RD |
2615 | } |
2616 | ||
2617 | static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw) | |
2618 | { | |
d956873f | 2619 | #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) |
04de7dda | 2620 | mlx5e_tc_clean_fdb_peer_flows(esw); |
d956873f | 2621 | #endif |
c8e6a9e6 | 2622 | mlx5_esw_offloads_rep_event_unpair(esw); |
ac004b83 RD |
2623 | esw_del_fdb_peer_miss_rules(esw); |
2624 | } | |
2625 | ||
c8e6a9e6 MB |
2626 | static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw, |
2627 | struct mlx5_eswitch *peer_esw) | |
2628 | { | |
2629 | const struct mlx5_eswitch_rep_ops *ops; | |
2630 | struct mlx5_eswitch_rep *rep; | |
2631 | unsigned long i; | |
2632 | u8 rep_type; | |
2633 | int err; | |
2634 | ||
2635 | err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev); | |
2636 | if (err) | |
2637 | return err; | |
2638 | ||
2639 | mlx5_esw_for_each_rep(esw, i, rep) { | |
2640 | for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) { | |
2641 | ops = esw->offloads.rep_ops[rep_type]; | |
2642 | if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED && | |
2643 | ops->event) { | |
2644 | err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw); | |
2645 | if (err) | |
2646 | goto err_out; | |
2647 | } | |
2648 | } | |
2649 | } | |
2650 | ||
2651 | return 0; | |
2652 | ||
2653 | err_out: | |
2654 | mlx5_esw_offloads_unpair(esw); | |
2655 | return err; | |
2656 | } | |
2657 | ||
8463daf1 MG |
2658 | static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw, |
2659 | struct mlx5_eswitch *peer_esw, | |
2660 | bool pair) | |
2661 | { | |
2662 | struct mlx5_flow_root_namespace *peer_ns; | |
2663 | struct mlx5_flow_root_namespace *ns; | |
2664 | int err; | |
2665 | ||
2666 | peer_ns = peer_esw->dev->priv.steering->fdb_root_ns; | |
2667 | ns = esw->dev->priv.steering->fdb_root_ns; | |
2668 | ||
2669 | if (pair) { | |
2670 | err = mlx5_flow_namespace_set_peer(ns, peer_ns); | |
2671 | if (err) | |
2672 | return err; | |
2673 | ||
e53e6655 | 2674 | err = mlx5_flow_namespace_set_peer(peer_ns, ns); |
8463daf1 MG |
2675 | if (err) { |
2676 | mlx5_flow_namespace_set_peer(ns, NULL); | |
2677 | return err; | |
2678 | } | |
2679 | } else { | |
2680 | mlx5_flow_namespace_set_peer(ns, NULL); | |
2681 | mlx5_flow_namespace_set_peer(peer_ns, NULL); | |
2682 | } | |
2683 | ||
2684 | return 0; | |
2685 | } | |
2686 | ||
ac004b83 RD |
2687 | static int mlx5_esw_offloads_devcom_event(int event, |
2688 | void *my_data, | |
2689 | void *event_data) | |
2690 | { | |
2691 | struct mlx5_eswitch *esw = my_data; | |
ac004b83 | 2692 | struct mlx5_devcom *devcom = esw->dev->priv.devcom; |
8463daf1 | 2693 | struct mlx5_eswitch *peer_esw = event_data; |
ac004b83 RD |
2694 | int err; |
2695 | ||
2696 | switch (event) { | |
2697 | case ESW_OFFLOADS_DEVCOM_PAIR: | |
dd3fddb8 RD |
2698 | if (mlx5_get_next_phys_dev(esw->dev) != peer_esw->dev) |
2699 | break; | |
2700 | ||
a5641cb5 JL |
2701 | if (mlx5_eswitch_vport_match_metadata_enabled(esw) != |
2702 | mlx5_eswitch_vport_match_metadata_enabled(peer_esw)) | |
2703 | break; | |
2704 | ||
8463daf1 | 2705 | err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true); |
ac004b83 RD |
2706 | if (err) |
2707 | goto err_out; | |
8463daf1 MG |
2708 | err = mlx5_esw_offloads_pair(esw, peer_esw); |
2709 | if (err) | |
2710 | goto err_peer; | |
ac004b83 RD |
2711 | |
2712 | err = mlx5_esw_offloads_pair(peer_esw, esw); | |
2713 | if (err) | |
2714 | goto err_pair; | |
2715 | ||
2716 | mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true); | |
2717 | break; | |
2718 | ||
2719 | case ESW_OFFLOADS_DEVCOM_UNPAIR: | |
2720 | if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS)) | |
2721 | break; | |
2722 | ||
2723 | mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false); | |
2724 | mlx5_esw_offloads_unpair(peer_esw); | |
2725 | mlx5_esw_offloads_unpair(esw); | |
8463daf1 | 2726 | mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false); |
ac004b83 RD |
2727 | break; |
2728 | } | |
2729 | ||
2730 | return 0; | |
2731 | ||
2732 | err_pair: | |
2733 | mlx5_esw_offloads_unpair(esw); | |
8463daf1 MG |
2734 | err_peer: |
2735 | mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false); | |
ac004b83 RD |
2736 | err_out: |
2737 | mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d", | |
2738 | event, err); | |
2739 | return err; | |
2740 | } | |
2741 | ||
2742 | static void esw_offloads_devcom_init(struct mlx5_eswitch *esw) | |
2743 | { | |
2744 | struct mlx5_devcom *devcom = esw->dev->priv.devcom; | |
2745 | ||
04de7dda RD |
2746 | INIT_LIST_HEAD(&esw->offloads.peer_flows); |
2747 | mutex_init(&esw->offloads.peer_mutex); | |
2748 | ||
ac004b83 RD |
2749 | if (!MLX5_CAP_ESW(esw->dev, merged_eswitch)) |
2750 | return; | |
2751 | ||
2752 | mlx5_devcom_register_component(devcom, | |
2753 | MLX5_DEVCOM_ESW_OFFLOADS, | |
2754 | mlx5_esw_offloads_devcom_event, | |
2755 | esw); | |
2756 | ||
2757 | mlx5_devcom_send_event(devcom, | |
2758 | MLX5_DEVCOM_ESW_OFFLOADS, | |
2759 | ESW_OFFLOADS_DEVCOM_PAIR, esw); | |
2760 | } | |
2761 | ||
2762 | static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw) | |
2763 | { | |
2764 | struct mlx5_devcom *devcom = esw->dev->priv.devcom; | |
2765 | ||
2766 | if (!MLX5_CAP_ESW(esw->dev, merged_eswitch)) | |
2767 | return; | |
2768 | ||
2769 | mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS, | |
2770 | ESW_OFFLOADS_DEVCOM_UNPAIR, esw); | |
2771 | ||
2772 | mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
2773 | } | |
2774 | ||
7bf481d7 | 2775 | bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw) |
92ab1eb3 JL |
2776 | { |
2777 | if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl)) | |
2778 | return false; | |
2779 | ||
2780 | if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) & | |
2781 | MLX5_FDB_TO_VPORT_REG_C_0)) | |
2782 | return false; | |
2783 | ||
2784 | if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source)) | |
2785 | return false; | |
2786 | ||
92ab1eb3 JL |
2787 | return true; |
2788 | } | |
2789 | ||
133dcfc5 VP |
2790 | u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw) |
2791 | { | |
7cd7becd | 2792 | u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1; |
2793 | u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1; | |
2794 | u32 pf_num; | |
133dcfc5 VP |
2795 | int id; |
2796 | ||
7cd7becd | 2797 | /* Only 4 bits of pf_num */ |
2798 | pf_num = PCI_FUNC(esw->dev->pdev->devfn); | |
2799 | if (pf_num > max_pf_num) | |
2800 | return 0; | |
133dcfc5 | 2801 | |
7cd7becd | 2802 | /* Metadata is 4 bits of PFNUM and 12 bits of unique id */ |
2803 | /* Use only non-zero vport_id (1-4095) for all PF's */ | |
2804 | id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL); | |
2805 | if (id < 0) | |
2806 | return 0; | |
2807 | id = (pf_num << ESW_VPORT_BITS) | id; | |
2808 | return id; | |
133dcfc5 VP |
2809 | } |
2810 | ||
2811 | void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata) | |
2812 | { | |
7cd7becd | 2813 | u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1; |
2814 | ||
2815 | /* Metadata contains only 12 bits of actual ida id */ | |
2816 | ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask); | |
133dcfc5 VP |
2817 | } |
2818 | ||
2819 | static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw, | |
2820 | struct mlx5_vport *vport) | |
2821 | { | |
133dcfc5 VP |
2822 | vport->default_metadata = mlx5_esw_match_metadata_alloc(esw); |
2823 | vport->metadata = vport->default_metadata; | |
2824 | return vport->metadata ? 0 : -ENOSPC; | |
2825 | } | |
2826 | ||
2827 | static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw, | |
2828 | struct mlx5_vport *vport) | |
2829 | { | |
406493a5 | 2830 | if (!vport->default_metadata) |
133dcfc5 VP |
2831 | return; |
2832 | ||
2833 | WARN_ON(vport->metadata != vport->default_metadata); | |
2834 | mlx5_esw_match_metadata_free(esw, vport->default_metadata); | |
2835 | } | |
2836 | ||
fc99c3d6 VP |
2837 | static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw) |
2838 | { | |
2839 | struct mlx5_vport *vport; | |
47dd7e60 | 2840 | unsigned long i; |
fc99c3d6 VP |
2841 | |
2842 | if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) | |
2843 | return; | |
2844 | ||
47dd7e60 | 2845 | mlx5_esw_for_each_vport(esw, i, vport) |
fc99c3d6 VP |
2846 | esw_offloads_vport_metadata_cleanup(esw, vport); |
2847 | } | |
2848 | ||
2849 | static int esw_offloads_metadata_init(struct mlx5_eswitch *esw) | |
2850 | { | |
2851 | struct mlx5_vport *vport; | |
47dd7e60 | 2852 | unsigned long i; |
fc99c3d6 | 2853 | int err; |
fc99c3d6 VP |
2854 | |
2855 | if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) | |
2856 | return 0; | |
2857 | ||
47dd7e60 | 2858 | mlx5_esw_for_each_vport(esw, i, vport) { |
fc99c3d6 VP |
2859 | err = esw_offloads_vport_metadata_setup(esw, vport); |
2860 | if (err) | |
2861 | goto metadata_err; | |
2862 | } | |
2863 | ||
2864 | return 0; | |
2865 | ||
2866 | metadata_err: | |
2867 | esw_offloads_metadata_uninit(esw); | |
2868 | return err; | |
2869 | } | |
2870 | ||
7bf481d7 PP |
2871 | int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable) |
2872 | { | |
2873 | int err = 0; | |
2874 | ||
2875 | down_write(&esw->mode_lock); | |
2876 | if (esw->mode != MLX5_ESWITCH_NONE) { | |
2877 | err = -EBUSY; | |
2878 | goto done; | |
2879 | } | |
2880 | if (!mlx5_esw_vport_match_metadata_supported(esw)) { | |
2881 | err = -EOPNOTSUPP; | |
2882 | goto done; | |
2883 | } | |
2884 | if (enable) | |
2885 | esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA; | |
2886 | else | |
2887 | esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA; | |
2888 | done: | |
2889 | up_write(&esw->mode_lock); | |
2890 | return err; | |
2891 | } | |
2892 | ||
748da30b | 2893 | int |
89a0f1fb PP |
2894 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, |
2895 | struct mlx5_vport *vport) | |
7445cfb1 | 2896 | { |
7445cfb1 JL |
2897 | int err; |
2898 | ||
07bab950 | 2899 | err = esw_acl_ingress_ofld_setup(esw, vport); |
89a0f1fb | 2900 | if (err) |
fc99c3d6 | 2901 | return err; |
7445cfb1 | 2902 | |
2c40db2f PP |
2903 | err = esw_acl_egress_ofld_setup(esw, vport); |
2904 | if (err) | |
2905 | goto egress_err; | |
07bab950 VP |
2906 | |
2907 | return 0; | |
2908 | ||
2909 | egress_err: | |
2910 | esw_acl_ingress_ofld_cleanup(esw, vport); | |
89a0f1fb PP |
2911 | return err; |
2912 | } | |
18486737 | 2913 | |
748da30b | 2914 | void |
89a0f1fb PP |
2915 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, |
2916 | struct mlx5_vport *vport) | |
2917 | { | |
ea651a86 | 2918 | esw_acl_egress_ofld_cleanup(vport); |
07bab950 | 2919 | esw_acl_ingress_ofld_cleanup(esw, vport); |
89a0f1fb | 2920 | } |
7445cfb1 | 2921 | |
748da30b | 2922 | static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw) |
7445cfb1 JL |
2923 | { |
2924 | struct mlx5_vport *vport; | |
18486737 | 2925 | |
748da30b | 2926 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK); |
7bef147a SM |
2927 | if (IS_ERR(vport)) |
2928 | return PTR_ERR(vport); | |
2929 | ||
4e9a9ef7 | 2930 | return esw_vport_create_offloads_acl_tables(esw, vport); |
18486737 EB |
2931 | } |
2932 | ||
748da30b | 2933 | static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw) |
18486737 | 2934 | { |
786ef904 | 2935 | struct mlx5_vport *vport; |
7445cfb1 | 2936 | |
748da30b | 2937 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK); |
7bef147a SM |
2938 | if (IS_ERR(vport)) |
2939 | return; | |
2940 | ||
748da30b | 2941 | esw_vport_destroy_offloads_acl_tables(esw, vport); |
18486737 EB |
2942 | } |
2943 | ||
db202995 MB |
2944 | int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw) |
2945 | { | |
2946 | struct mlx5_eswitch_rep *rep; | |
2947 | unsigned long i; | |
2948 | int ret; | |
2949 | ||
2950 | if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS) | |
2951 | return 0; | |
2952 | ||
2953 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK); | |
2954 | if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED) | |
2955 | return 0; | |
2956 | ||
2957 | ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK); | |
2958 | if (ret) | |
2959 | return ret; | |
2960 | ||
2961 | mlx5_esw_for_each_rep(esw, i, rep) { | |
2962 | if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED) | |
2963 | mlx5_esw_offloads_rep_load(esw, rep->vport); | |
2964 | } | |
2965 | ||
2966 | return 0; | |
2967 | } | |
2968 | ||
062f4bf4 | 2969 | static int esw_offloads_steering_init(struct mlx5_eswitch *esw) |
6ed1803a | 2970 | { |
34ca6535 | 2971 | struct mlx5_esw_indir_table *indir; |
6ed1803a MB |
2972 | int err; |
2973 | ||
5c1d260e | 2974 | memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb)); |
f8d1edda PP |
2975 | mutex_init(&esw->fdb_table.offloads.vports.lock); |
2976 | hash_init(esw->fdb_table.offloads.vports.table); | |
7dc84de9 | 2977 | atomic64_set(&esw->user_count, 0); |
e52c2802 | 2978 | |
34ca6535 VB |
2979 | indir = mlx5_esw_indir_table_init(); |
2980 | if (IS_ERR(indir)) { | |
2981 | err = PTR_ERR(indir); | |
2982 | goto create_indir_err; | |
2983 | } | |
2984 | esw->fdb_table.offloads.indir = indir; | |
2985 | ||
748da30b | 2986 | err = esw_create_uplink_offloads_acl_tables(esw); |
7445cfb1 | 2987 | if (err) |
f8d1edda | 2988 | goto create_acl_err; |
18486737 | 2989 | |
8d6bd3c3 | 2990 | err = esw_create_offloads_table(esw); |
c930a3ad | 2991 | if (err) |
11b717d6 | 2992 | goto create_offloads_err; |
c930a3ad | 2993 | |
11b717d6 | 2994 | err = esw_create_restore_table(esw); |
c930a3ad | 2995 | if (err) |
11b717d6 PB |
2996 | goto create_restore_err; |
2997 | ||
0da3c12d | 2998 | err = esw_create_offloads_fdb_tables(esw); |
11b717d6 PB |
2999 | if (err) |
3000 | goto create_fdb_err; | |
c930a3ad | 3001 | |
8d6bd3c3 | 3002 | err = esw_create_vport_rx_group(esw); |
c930a3ad OG |
3003 | if (err) |
3004 | goto create_fg_err; | |
3005 | ||
3006 | return 0; | |
3007 | ||
3008 | create_fg_err: | |
1967ce6e | 3009 | esw_destroy_offloads_fdb_tables(esw); |
7445cfb1 | 3010 | create_fdb_err: |
11b717d6 PB |
3011 | esw_destroy_restore_table(esw); |
3012 | create_restore_err: | |
3013 | esw_destroy_offloads_table(esw); | |
3014 | create_offloads_err: | |
748da30b | 3015 | esw_destroy_uplink_offloads_acl_tables(esw); |
f8d1edda | 3016 | create_acl_err: |
34ca6535 VB |
3017 | mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir); |
3018 | create_indir_err: | |
f8d1edda | 3019 | mutex_destroy(&esw->fdb_table.offloads.vports.lock); |
c930a3ad OG |
3020 | return err; |
3021 | } | |
3022 | ||
eca8cc38 BW |
3023 | static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw) |
3024 | { | |
3025 | esw_destroy_vport_rx_group(esw); | |
eca8cc38 | 3026 | esw_destroy_offloads_fdb_tables(esw); |
11b717d6 PB |
3027 | esw_destroy_restore_table(esw); |
3028 | esw_destroy_offloads_table(esw); | |
748da30b | 3029 | esw_destroy_uplink_offloads_acl_tables(esw); |
34ca6535 | 3030 | mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir); |
f8d1edda | 3031 | mutex_destroy(&esw->fdb_table.offloads.vports.lock); |
eca8cc38 BW |
3032 | } |
3033 | ||
7e736f9a PP |
3034 | static void |
3035 | esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out) | |
a3888f33 | 3036 | { |
5ccf2770 | 3037 | bool host_pf_disabled; |
7e736f9a | 3038 | u16 new_num_vfs; |
a3888f33 | 3039 | |
7e736f9a PP |
3040 | new_num_vfs = MLX5_GET(query_esw_functions_out, out, |
3041 | host_params_context.host_num_of_vfs); | |
5ccf2770 BW |
3042 | host_pf_disabled = MLX5_GET(query_esw_functions_out, out, |
3043 | host_params_context.host_pf_disabled); | |
a3888f33 | 3044 | |
7e736f9a PP |
3045 | if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled) |
3046 | return; | |
a3888f33 BW |
3047 | |
3048 | /* Number of VFs can only change from "0 to x" or "x to 0". */ | |
cd56f929 | 3049 | if (esw->esw_funcs.num_vfs > 0) { |
23bb50cf | 3050 | mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs); |
a3888f33 | 3051 | } else { |
7e736f9a | 3052 | int err; |
a3888f33 | 3053 | |
23bb50cf BW |
3054 | err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs, |
3055 | MLX5_VPORT_UC_ADDR_CHANGE); | |
a3888f33 | 3056 | if (err) |
7e736f9a | 3057 | return; |
a3888f33 | 3058 | } |
7e736f9a | 3059 | esw->esw_funcs.num_vfs = new_num_vfs; |
a3888f33 BW |
3060 | } |
3061 | ||
7e736f9a | 3062 | static void esw_functions_changed_event_handler(struct work_struct *work) |
ac35dcd6 | 3063 | { |
7e736f9a PP |
3064 | struct mlx5_host_work *host_work; |
3065 | struct mlx5_eswitch *esw; | |
dd28087c | 3066 | const u32 *out; |
ac35dcd6 | 3067 | |
7e736f9a PP |
3068 | host_work = container_of(work, struct mlx5_host_work, work); |
3069 | esw = host_work->esw; | |
a3888f33 | 3070 | |
dd28087c PP |
3071 | out = mlx5_esw_query_functions(esw->dev); |
3072 | if (IS_ERR(out)) | |
7e736f9a | 3073 | goto out; |
a3888f33 | 3074 | |
7e736f9a | 3075 | esw_vfs_changed_event_handler(esw, out); |
dd28087c | 3076 | kvfree(out); |
a3888f33 | 3077 | out: |
ac35dcd6 VP |
3078 | kfree(host_work); |
3079 | } | |
3080 | ||
16fff98a | 3081 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data) |
a3888f33 | 3082 | { |
cd56f929 | 3083 | struct mlx5_esw_functions *esw_funcs; |
a3888f33 | 3084 | struct mlx5_host_work *host_work; |
a3888f33 BW |
3085 | struct mlx5_eswitch *esw; |
3086 | ||
3087 | host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC); | |
3088 | if (!host_work) | |
3089 | return NOTIFY_DONE; | |
3090 | ||
cd56f929 VP |
3091 | esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb); |
3092 | esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs); | |
a3888f33 BW |
3093 | |
3094 | host_work->esw = esw; | |
3095 | ||
062f4bf4 | 3096 | INIT_WORK(&host_work->work, esw_functions_changed_event_handler); |
a3888f33 BW |
3097 | queue_work(esw->work_queue, &host_work->work); |
3098 | ||
3099 | return NOTIFY_OK; | |
3100 | } | |
3101 | ||
a53cf949 PP |
3102 | static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw) |
3103 | { | |
3104 | const u32 *query_host_out; | |
3105 | ||
3106 | if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) | |
3107 | return 0; | |
3108 | ||
3109 | query_host_out = mlx5_esw_query_functions(esw->dev); | |
3110 | if (IS_ERR(query_host_out)) | |
3111 | return PTR_ERR(query_host_out); | |
3112 | ||
3113 | /* Mark non local controller with non zero controller number. */ | |
3114 | esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out, | |
3115 | host_params_context.host_number); | |
3116 | kvfree(query_host_out); | |
3117 | return 0; | |
3118 | } | |
3119 | ||
f1b9acd3 PP |
3120 | bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller) |
3121 | { | |
3122 | /* Local controller is always valid */ | |
3123 | if (controller == 0) | |
3124 | return true; | |
3125 | ||
3126 | if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) | |
3127 | return false; | |
3128 | ||
3129 | /* External host number starts with zero in device */ | |
3130 | return (controller == esw->offloads.host_number + 1); | |
3131 | } | |
3132 | ||
5896b972 | 3133 | int esw_offloads_enable(struct mlx5_eswitch *esw) |
eca8cc38 | 3134 | { |
c9355682 | 3135 | struct mapping_ctx *reg_c0_obj_pool; |
3b83b6c2 | 3136 | struct mlx5_vport *vport; |
47dd7e60 | 3137 | unsigned long i; |
2198b932 | 3138 | u64 mapping_id; |
47dd7e60 | 3139 | int err; |
eca8cc38 | 3140 | |
2bb72e7e | 3141 | mutex_init(&esw->offloads.termtbl_mutex); |
8463daf1 | 3142 | mlx5_rdma_enable_roce(esw->dev); |
eca8cc38 | 3143 | |
a53cf949 PP |
3144 | err = mlx5_esw_host_number_init(esw); |
3145 | if (err) | |
cd1ef966 | 3146 | goto err_metadata; |
a53cf949 | 3147 | |
fc99c3d6 VP |
3148 | err = esw_offloads_metadata_init(esw); |
3149 | if (err) | |
3150 | goto err_metadata; | |
3151 | ||
332bd3a5 PP |
3152 | err = esw_set_passing_vport_metadata(esw, true); |
3153 | if (err) | |
3154 | goto err_vport_metadata; | |
c1286050 | 3155 | |
2198b932 RD |
3156 | mapping_id = mlx5_query_nic_system_image_guid(esw->dev); |
3157 | ||
3158 | reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN, | |
3159 | sizeof(struct mlx5_mapped_obj), | |
3160 | ESW_REG_C0_USER_DATA_METADATA_MASK, | |
3161 | true); | |
3162 | ||
c9355682 CM |
3163 | if (IS_ERR(reg_c0_obj_pool)) { |
3164 | err = PTR_ERR(reg_c0_obj_pool); | |
3165 | goto err_pool; | |
3166 | } | |
3167 | esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool; | |
3168 | ||
7983a675 PB |
3169 | err = esw_offloads_steering_init(esw); |
3170 | if (err) | |
3171 | goto err_steering_init; | |
3172 | ||
3b83b6c2 DL |
3173 | /* Representor will control the vport link state */ |
3174 | mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs) | |
3175 | vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN; | |
3176 | ||
c2d7712c BW |
3177 | /* Uplink vport rep must load first. */ |
3178 | err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK); | |
925a6acc | 3179 | if (err) |
c2d7712c | 3180 | goto err_uplink; |
c1286050 | 3181 | |
c2d7712c | 3182 | err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE); |
eca8cc38 | 3183 | if (err) |
c2d7712c | 3184 | goto err_vports; |
eca8cc38 BW |
3185 | |
3186 | esw_offloads_devcom_init(esw); | |
a3888f33 | 3187 | |
eca8cc38 BW |
3188 | return 0; |
3189 | ||
925a6acc | 3190 | err_vports: |
c2d7712c BW |
3191 | esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK); |
3192 | err_uplink: | |
7983a675 | 3193 | esw_offloads_steering_cleanup(esw); |
79949985 | 3194 | err_steering_init: |
c9355682 CM |
3195 | mapping_destroy(reg_c0_obj_pool); |
3196 | err_pool: | |
79949985 | 3197 | esw_set_passing_vport_metadata(esw, false); |
7983a675 | 3198 | err_vport_metadata: |
fc99c3d6 VP |
3199 | esw_offloads_metadata_uninit(esw); |
3200 | err_metadata: | |
8463daf1 | 3201 | mlx5_rdma_disable_roce(esw->dev); |
2bb72e7e | 3202 | mutex_destroy(&esw->offloads.termtbl_mutex); |
eca8cc38 BW |
3203 | return err; |
3204 | } | |
3205 | ||
db7ff19e EB |
3206 | static int esw_offloads_stop(struct mlx5_eswitch *esw, |
3207 | struct netlink_ext_ack *extack) | |
c930a3ad | 3208 | { |
062f4bf4 | 3209 | int err, err1; |
c930a3ad | 3210 | |
8e0aa4bc PP |
3211 | mlx5_eswitch_disable_locked(esw, false); |
3212 | err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY, | |
3213 | MLX5_ESWITCH_IGNORE_NUM_VFS); | |
6c419ba8 | 3214 | if (err) { |
8c98ee77 | 3215 | NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy"); |
8e0aa4bc PP |
3216 | err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS, |
3217 | MLX5_ESWITCH_IGNORE_NUM_VFS); | |
8c98ee77 EB |
3218 | if (err1) { |
3219 | NL_SET_ERR_MSG_MOD(extack, | |
3220 | "Failed setting eswitch back to offloads"); | |
3221 | } | |
6c419ba8 | 3222 | } |
c930a3ad OG |
3223 | |
3224 | return err; | |
3225 | } | |
3226 | ||
5896b972 | 3227 | void esw_offloads_disable(struct mlx5_eswitch *esw) |
c930a3ad | 3228 | { |
ac004b83 | 3229 | esw_offloads_devcom_cleanup(esw); |
5896b972 | 3230 | mlx5_eswitch_disable_pf_vf_vports(esw); |
c2d7712c | 3231 | esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK); |
332bd3a5 | 3232 | esw_set_passing_vport_metadata(esw, false); |
eca8cc38 | 3233 | esw_offloads_steering_cleanup(esw); |
c9355682 | 3234 | mapping_destroy(esw->offloads.reg_c0_obj_pool); |
fc99c3d6 | 3235 | esw_offloads_metadata_uninit(esw); |
8463daf1 | 3236 | mlx5_rdma_disable_roce(esw->dev); |
2bb72e7e | 3237 | mutex_destroy(&esw->offloads.termtbl_mutex); |
c930a3ad OG |
3238 | } |
3239 | ||
ef78618b | 3240 | static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode) |
c930a3ad OG |
3241 | { |
3242 | switch (mode) { | |
3243 | case DEVLINK_ESWITCH_MODE_LEGACY: | |
f6455de0 | 3244 | *mlx5_mode = MLX5_ESWITCH_LEGACY; |
c930a3ad OG |
3245 | break; |
3246 | case DEVLINK_ESWITCH_MODE_SWITCHDEV: | |
f6455de0 | 3247 | *mlx5_mode = MLX5_ESWITCH_OFFLOADS; |
c930a3ad OG |
3248 | break; |
3249 | default: | |
3250 | return -EINVAL; | |
3251 | } | |
3252 | ||
3253 | return 0; | |
3254 | } | |
3255 | ||
ef78618b OG |
3256 | static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode) |
3257 | { | |
3258 | switch (mlx5_mode) { | |
f6455de0 | 3259 | case MLX5_ESWITCH_LEGACY: |
ef78618b OG |
3260 | *mode = DEVLINK_ESWITCH_MODE_LEGACY; |
3261 | break; | |
f6455de0 | 3262 | case MLX5_ESWITCH_OFFLOADS: |
ef78618b OG |
3263 | *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV; |
3264 | break; | |
3265 | default: | |
3266 | return -EINVAL; | |
3267 | } | |
3268 | ||
3269 | return 0; | |
3270 | } | |
3271 | ||
bffaa916 RD |
3272 | static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode) |
3273 | { | |
3274 | switch (mode) { | |
3275 | case DEVLINK_ESWITCH_INLINE_MODE_NONE: | |
3276 | *mlx5_mode = MLX5_INLINE_MODE_NONE; | |
3277 | break; | |
3278 | case DEVLINK_ESWITCH_INLINE_MODE_LINK: | |
3279 | *mlx5_mode = MLX5_INLINE_MODE_L2; | |
3280 | break; | |
3281 | case DEVLINK_ESWITCH_INLINE_MODE_NETWORK: | |
3282 | *mlx5_mode = MLX5_INLINE_MODE_IP; | |
3283 | break; | |
3284 | case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT: | |
3285 | *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP; | |
3286 | break; | |
3287 | default: | |
3288 | return -EINVAL; | |
3289 | } | |
3290 | ||
3291 | return 0; | |
3292 | } | |
3293 | ||
3294 | static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode) | |
3295 | { | |
3296 | switch (mlx5_mode) { | |
3297 | case MLX5_INLINE_MODE_NONE: | |
3298 | *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE; | |
3299 | break; | |
3300 | case MLX5_INLINE_MODE_L2: | |
3301 | *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK; | |
3302 | break; | |
3303 | case MLX5_INLINE_MODE_IP: | |
3304 | *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK; | |
3305 | break; | |
3306 | case MLX5_INLINE_MODE_TCP_UDP: | |
3307 | *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT; | |
3308 | break; | |
3309 | default: | |
3310 | return -EINVAL; | |
3311 | } | |
3312 | ||
3313 | return 0; | |
3314 | } | |
3315 | ||
ae24432c PP |
3316 | static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw) |
3317 | { | |
3318 | /* devlink commands in NONE eswitch mode are currently supported only | |
3319 | * on ECPF. | |
3320 | */ | |
3321 | return (esw->mode == MLX5_ESWITCH_NONE && | |
3322 | !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0; | |
3323 | } | |
3324 | ||
db7ff19e EB |
3325 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
3326 | struct netlink_ext_ack *extack) | |
9d1cef19 | 3327 | { |
9d1cef19 | 3328 | u16 cur_mlx5_mode, mlx5_mode = 0; |
bd939753 | 3329 | struct mlx5_eswitch *esw; |
ea2128fd | 3330 | int err = 0; |
9d1cef19 | 3331 | |
bd939753 PP |
3332 | esw = mlx5_devlink_eswitch_get(devlink); |
3333 | if (IS_ERR(esw)) | |
3334 | return PTR_ERR(esw); | |
9d1cef19 | 3335 | |
ef78618b | 3336 | if (esw_mode_from_devlink(mode, &mlx5_mode)) |
c930a3ad OG |
3337 | return -EINVAL; |
3338 | ||
cac1eb2c | 3339 | mlx5_lag_disable_change(esw->dev); |
7dc84de9 RD |
3340 | err = mlx5_esw_try_lock(esw); |
3341 | if (err < 0) { | |
3342 | NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy"); | |
cac1eb2c | 3343 | goto enable_lag; |
7dc84de9 RD |
3344 | } |
3345 | cur_mlx5_mode = err; | |
3346 | err = 0; | |
3347 | ||
c930a3ad | 3348 | if (cur_mlx5_mode == mlx5_mode) |
8e0aa4bc | 3349 | goto unlock; |
c930a3ad | 3350 | |
c85a6b8f AL |
3351 | if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) { |
3352 | if (mlx5_devlink_trap_get_num_active(esw->dev)) { | |
3353 | NL_SET_ERR_MSG_MOD(extack, | |
3354 | "Can't change mode while devlink traps are active"); | |
3355 | err = -EOPNOTSUPP; | |
3356 | goto unlock; | |
3357 | } | |
8e0aa4bc | 3358 | err = esw_offloads_start(esw, extack); |
c85a6b8f | 3359 | } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) { |
8e0aa4bc | 3360 | err = esw_offloads_stop(esw, extack); |
c85a6b8f | 3361 | } else { |
8e0aa4bc | 3362 | err = -EINVAL; |
c85a6b8f | 3363 | } |
8e0aa4bc PP |
3364 | |
3365 | unlock: | |
7dc84de9 | 3366 | mlx5_esw_unlock(esw); |
cac1eb2c MB |
3367 | enable_lag: |
3368 | mlx5_lag_enable_change(esw->dev); | |
8e0aa4bc | 3369 | return err; |
feae9087 OG |
3370 | } |
3371 | ||
3372 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode) | |
3373 | { | |
bd939753 | 3374 | struct mlx5_eswitch *esw; |
9d1cef19 | 3375 | int err; |
c930a3ad | 3376 | |
bd939753 PP |
3377 | esw = mlx5_devlink_eswitch_get(devlink); |
3378 | if (IS_ERR(esw)) | |
3379 | return PTR_ERR(esw); | |
c930a3ad | 3380 | |
c55479d0 | 3381 | down_write(&esw->mode_lock); |
bd939753 | 3382 | err = eswitch_devlink_esw_mode_check(esw); |
ae24432c | 3383 | if (err) |
8e0aa4bc | 3384 | goto unlock; |
ae24432c | 3385 | |
8e0aa4bc PP |
3386 | err = esw_mode_to_devlink(esw->mode, mode); |
3387 | unlock: | |
c55479d0 | 3388 | up_write(&esw->mode_lock); |
8e0aa4bc | 3389 | return err; |
feae9087 | 3390 | } |
127ea380 | 3391 | |
47dd7e60 PP |
3392 | static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode, |
3393 | struct netlink_ext_ack *extack) | |
3394 | { | |
3395 | struct mlx5_core_dev *dev = esw->dev; | |
3396 | struct mlx5_vport *vport; | |
3397 | u16 err_vport_num = 0; | |
3398 | unsigned long i; | |
3399 | int err = 0; | |
3400 | ||
3401 | mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) { | |
3402 | err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode); | |
3403 | if (err) { | |
3404 | err_vport_num = vport->vport; | |
3405 | NL_SET_ERR_MSG_MOD(extack, | |
3406 | "Failed to set min inline on vport"); | |
3407 | goto revert_inline_mode; | |
3408 | } | |
3409 | } | |
3410 | return 0; | |
3411 | ||
3412 | revert_inline_mode: | |
3413 | mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) { | |
3414 | if (vport->vport == err_vport_num) | |
3415 | break; | |
3416 | mlx5_modify_nic_vport_min_inline(dev, | |
3417 | vport->vport, | |
3418 | esw->offloads.inline_mode); | |
3419 | } | |
3420 | return err; | |
3421 | } | |
3422 | ||
db7ff19e EB |
3423 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
3424 | struct netlink_ext_ack *extack) | |
bffaa916 RD |
3425 | { |
3426 | struct mlx5_core_dev *dev = devlink_priv(devlink); | |
bd939753 | 3427 | struct mlx5_eswitch *esw; |
bffaa916 | 3428 | u8 mlx5_mode; |
47dd7e60 | 3429 | int err; |
bffaa916 | 3430 | |
bd939753 PP |
3431 | esw = mlx5_devlink_eswitch_get(devlink); |
3432 | if (IS_ERR(esw)) | |
3433 | return PTR_ERR(esw); | |
bffaa916 | 3434 | |
c55479d0 | 3435 | down_write(&esw->mode_lock); |
ae24432c PP |
3436 | err = eswitch_devlink_esw_mode_check(esw); |
3437 | if (err) | |
8e0aa4bc | 3438 | goto out; |
ae24432c | 3439 | |
c415f704 OG |
3440 | switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { |
3441 | case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: | |
bcd68c04 JC |
3442 | if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) { |
3443 | err = 0; | |
8e0aa4bc | 3444 | goto out; |
bcd68c04 JC |
3445 | } |
3446 | ||
c8b838d1 | 3447 | fallthrough; |
c415f704 | 3448 | case MLX5_CAP_INLINE_MODE_L2: |
8c98ee77 | 3449 | NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set"); |
8e0aa4bc PP |
3450 | err = -EOPNOTSUPP; |
3451 | goto out; | |
c415f704 OG |
3452 | case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: |
3453 | break; | |
3454 | } | |
bffaa916 | 3455 | |
525e84be | 3456 | if (atomic64_read(&esw->offloads.num_flows) > 0) { |
8c98ee77 EB |
3457 | NL_SET_ERR_MSG_MOD(extack, |
3458 | "Can't set inline mode when flows are configured"); | |
8e0aa4bc PP |
3459 | err = -EOPNOTSUPP; |
3460 | goto out; | |
375f51e2 RD |
3461 | } |
3462 | ||
bffaa916 RD |
3463 | err = esw_inline_mode_from_devlink(mode, &mlx5_mode); |
3464 | if (err) | |
3465 | goto out; | |
3466 | ||
47dd7e60 PP |
3467 | err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack); |
3468 | if (err) | |
3469 | goto out; | |
bffaa916 RD |
3470 | |
3471 | esw->offloads.inline_mode = mlx5_mode; | |
c55479d0 | 3472 | up_write(&esw->mode_lock); |
bffaa916 RD |
3473 | return 0; |
3474 | ||
bffaa916 | 3475 | out: |
c55479d0 | 3476 | up_write(&esw->mode_lock); |
bffaa916 RD |
3477 | return err; |
3478 | } | |
3479 | ||
3480 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode) | |
3481 | { | |
bd939753 | 3482 | struct mlx5_eswitch *esw; |
9d1cef19 | 3483 | int err; |
bffaa916 | 3484 | |
bd939753 PP |
3485 | esw = mlx5_devlink_eswitch_get(devlink); |
3486 | if (IS_ERR(esw)) | |
3487 | return PTR_ERR(esw); | |
bffaa916 | 3488 | |
c55479d0 | 3489 | down_write(&esw->mode_lock); |
ae24432c PP |
3490 | err = eswitch_devlink_esw_mode_check(esw); |
3491 | if (err) | |
8e0aa4bc | 3492 | goto unlock; |
ae24432c | 3493 | |
8e0aa4bc PP |
3494 | err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode); |
3495 | unlock: | |
c55479d0 | 3496 | up_write(&esw->mode_lock); |
8e0aa4bc | 3497 | return err; |
bffaa916 RD |
3498 | } |
3499 | ||
98fdbea5 LR |
3500 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
3501 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 3502 | struct netlink_ext_ack *extack) |
7768d197 RD |
3503 | { |
3504 | struct mlx5_core_dev *dev = devlink_priv(devlink); | |
bd939753 | 3505 | struct mlx5_eswitch *esw; |
7768d197 RD |
3506 | int err; |
3507 | ||
bd939753 PP |
3508 | esw = mlx5_devlink_eswitch_get(devlink); |
3509 | if (IS_ERR(esw)) | |
3510 | return PTR_ERR(esw); | |
7768d197 | 3511 | |
c55479d0 | 3512 | down_write(&esw->mode_lock); |
ae24432c PP |
3513 | err = eswitch_devlink_esw_mode_check(esw); |
3514 | if (err) | |
8e0aa4bc | 3515 | goto unlock; |
ae24432c | 3516 | |
7768d197 | 3517 | if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE && |
60786f09 | 3518 | (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) || |
8e0aa4bc PP |
3519 | !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) { |
3520 | err = -EOPNOTSUPP; | |
3521 | goto unlock; | |
3522 | } | |
7768d197 | 3523 | |
8e0aa4bc PP |
3524 | if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) { |
3525 | err = -EOPNOTSUPP; | |
3526 | goto unlock; | |
3527 | } | |
7768d197 | 3528 | |
f6455de0 | 3529 | if (esw->mode == MLX5_ESWITCH_LEGACY) { |
7768d197 | 3530 | esw->offloads.encap = encap; |
8e0aa4bc | 3531 | goto unlock; |
7768d197 RD |
3532 | } |
3533 | ||
3534 | if (esw->offloads.encap == encap) | |
8e0aa4bc | 3535 | goto unlock; |
7768d197 | 3536 | |
525e84be | 3537 | if (atomic64_read(&esw->offloads.num_flows) > 0) { |
8c98ee77 EB |
3538 | NL_SET_ERR_MSG_MOD(extack, |
3539 | "Can't set encapsulation when flows are configured"); | |
8e0aa4bc PP |
3540 | err = -EOPNOTSUPP; |
3541 | goto unlock; | |
7768d197 RD |
3542 | } |
3543 | ||
e52c2802 | 3544 | esw_destroy_offloads_fdb_tables(esw); |
7768d197 RD |
3545 | |
3546 | esw->offloads.encap = encap; | |
e52c2802 | 3547 | |
0da3c12d | 3548 | err = esw_create_offloads_fdb_tables(esw); |
e52c2802 | 3549 | |
7768d197 | 3550 | if (err) { |
8c98ee77 EB |
3551 | NL_SET_ERR_MSG_MOD(extack, |
3552 | "Failed re-creating fast FDB table"); | |
7768d197 | 3553 | esw->offloads.encap = !encap; |
0da3c12d | 3554 | (void)esw_create_offloads_fdb_tables(esw); |
7768d197 | 3555 | } |
e52c2802 | 3556 | |
8e0aa4bc | 3557 | unlock: |
c55479d0 | 3558 | up_write(&esw->mode_lock); |
7768d197 RD |
3559 | return err; |
3560 | } | |
3561 | ||
98fdbea5 LR |
3562 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
3563 | enum devlink_eswitch_encap_mode *encap) | |
7768d197 | 3564 | { |
bd939753 | 3565 | struct mlx5_eswitch *esw; |
9d1cef19 | 3566 | int err; |
7768d197 | 3567 | |
bd939753 PP |
3568 | esw = mlx5_devlink_eswitch_get(devlink); |
3569 | if (IS_ERR(esw)) | |
3570 | return PTR_ERR(esw); | |
3571 | ||
7768d197 | 3572 | |
c55479d0 | 3573 | down_write(&esw->mode_lock); |
ae24432c PP |
3574 | err = eswitch_devlink_esw_mode_check(esw); |
3575 | if (err) | |
8e0aa4bc | 3576 | goto unlock; |
ae24432c | 3577 | |
7768d197 | 3578 | *encap = esw->offloads.encap; |
8e0aa4bc | 3579 | unlock: |
c55479d0 | 3580 | up_write(&esw->mode_lock); |
234fa109 | 3581 | return err; |
7768d197 RD |
3582 | } |
3583 | ||
c2d7712c BW |
3584 | static bool |
3585 | mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num) | |
3586 | { | |
3587 | /* Currently, only ECPF based device has representor for host PF. */ | |
3588 | if (vport_num == MLX5_VPORT_PF && | |
3589 | !mlx5_core_is_ecpf_esw_manager(esw->dev)) | |
3590 | return false; | |
3591 | ||
3592 | if (vport_num == MLX5_VPORT_ECPF && | |
3593 | !mlx5_ecpf_vport_exists(esw->dev)) | |
3594 | return false; | |
3595 | ||
3596 | return true; | |
3597 | } | |
3598 | ||
f8e8fa02 | 3599 | void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw, |
8693115a | 3600 | const struct mlx5_eswitch_rep_ops *ops, |
f8e8fa02 | 3601 | u8 rep_type) |
127ea380 | 3602 | { |
8693115a | 3603 | struct mlx5_eswitch_rep_data *rep_data; |
f8e8fa02 | 3604 | struct mlx5_eswitch_rep *rep; |
47dd7e60 | 3605 | unsigned long i; |
9deb2241 | 3606 | |
8693115a | 3607 | esw->offloads.rep_ops[rep_type] = ops; |
47dd7e60 PP |
3608 | mlx5_esw_for_each_rep(esw, i, rep) { |
3609 | if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) { | |
59c904c8 | 3610 | rep->esw = esw; |
c2d7712c BW |
3611 | rep_data = &rep->rep_data[rep_type]; |
3612 | atomic_set(&rep_data->state, REP_REGISTERED); | |
3613 | } | |
f8e8fa02 | 3614 | } |
127ea380 | 3615 | } |
f8e8fa02 | 3616 | EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps); |
127ea380 | 3617 | |
f8e8fa02 | 3618 | void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type) |
127ea380 | 3619 | { |
cb67b832 | 3620 | struct mlx5_eswitch_rep *rep; |
47dd7e60 | 3621 | unsigned long i; |
cb67b832 | 3622 | |
f6455de0 | 3623 | if (esw->mode == MLX5_ESWITCH_OFFLOADS) |
062f4bf4 | 3624 | __unload_reps_all_vport(esw, rep_type); |
127ea380 | 3625 | |
47dd7e60 | 3626 | mlx5_esw_for_each_rep(esw, i, rep) |
8693115a | 3627 | atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED); |
127ea380 | 3628 | } |
f8e8fa02 | 3629 | EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps); |
726293f1 | 3630 | |
a4b97ab4 | 3631 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type) |
726293f1 | 3632 | { |
726293f1 HHZ |
3633 | struct mlx5_eswitch_rep *rep; |
3634 | ||
879c8f84 | 3635 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK); |
8693115a | 3636 | return rep->rep_data[rep_type].priv; |
726293f1 | 3637 | } |
22215908 MB |
3638 | |
3639 | void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, | |
02f3afd9 | 3640 | u16 vport, |
22215908 MB |
3641 | u8 rep_type) |
3642 | { | |
22215908 MB |
3643 | struct mlx5_eswitch_rep *rep; |
3644 | ||
879c8f84 | 3645 | rep = mlx5_eswitch_get_rep(esw, vport); |
22215908 | 3646 | |
8693115a PP |
3647 | if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED && |
3648 | esw->offloads.rep_ops[rep_type]->get_proto_dev) | |
3649 | return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep); | |
22215908 MB |
3650 | return NULL; |
3651 | } | |
57cbd893 | 3652 | EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev); |
22215908 MB |
3653 | |
3654 | void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type) | |
3655 | { | |
879c8f84 | 3656 | return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type); |
22215908 | 3657 | } |
57cbd893 MB |
3658 | EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev); |
3659 | ||
3660 | struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw, | |
02f3afd9 | 3661 | u16 vport) |
57cbd893 | 3662 | { |
879c8f84 | 3663 | return mlx5_eswitch_get_rep(esw, vport); |
57cbd893 MB |
3664 | } |
3665 | EXPORT_SYMBOL(mlx5_eswitch_vport_rep); | |
91d6291c | 3666 | |
5b7cb745 PB |
3667 | bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw) |
3668 | { | |
3669 | return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED); | |
3670 | } | |
3671 | EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled); | |
3672 | ||
7445cfb1 JL |
3673 | bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw) |
3674 | { | |
3675 | return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA); | |
3676 | } | |
3677 | EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled); | |
3678 | ||
0f0d3827 | 3679 | u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, |
7445cfb1 JL |
3680 | u16 vport_num) |
3681 | { | |
133dcfc5 | 3682 | struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num); |
0f0d3827 | 3683 | |
133dcfc5 VP |
3684 | if (WARN_ON_ONCE(IS_ERR(vport))) |
3685 | return 0; | |
0f0d3827 | 3686 | |
133dcfc5 | 3687 | return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS); |
7445cfb1 JL |
3688 | } |
3689 | EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match); | |
d970812b PP |
3690 | |
3691 | int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port, | |
f1b9acd3 | 3692 | u16 vport_num, u32 controller, u32 sfnum) |
d970812b PP |
3693 | { |
3694 | int err; | |
3695 | ||
3696 | err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE); | |
3697 | if (err) | |
3698 | return err; | |
3699 | ||
f1b9acd3 | 3700 | err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum); |
d970812b PP |
3701 | if (err) |
3702 | goto devlink_err; | |
3703 | ||
3704 | err = mlx5_esw_offloads_rep_load(esw, vport_num); | |
3705 | if (err) | |
3706 | goto rep_err; | |
3707 | return 0; | |
3708 | ||
3709 | rep_err: | |
3710 | mlx5_esw_devlink_sf_port_unregister(esw, vport_num); | |
3711 | devlink_err: | |
3712 | mlx5_esw_vport_disable(esw, vport_num); | |
3713 | return err; | |
3714 | } | |
3715 | ||
3716 | void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num) | |
3717 | { | |
3718 | mlx5_esw_offloads_rep_unload(esw, vport_num); | |
3719 | mlx5_esw_devlink_sf_port_unregister(esw, vport_num); | |
3720 | mlx5_esw_vport_disable(esw, vport_num); | |
3721 | } | |
84ae9c1f VB |
3722 | |
3723 | static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id) | |
3724 | { | |
3725 | int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
3726 | void *query_ctx; | |
3727 | void *hca_caps; | |
3728 | int err; | |
3729 | ||
3730 | *vhca_id = 0; | |
3731 | if (mlx5_esw_is_manager_vport(esw, vport_num) || | |
3732 | !MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) | |
3733 | return -EPERM; | |
3734 | ||
3735 | query_ctx = kzalloc(query_out_sz, GFP_KERNEL); | |
3736 | if (!query_ctx) | |
3737 | return -ENOMEM; | |
3738 | ||
3739 | err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx); | |
3740 | if (err) | |
3741 | goto out_free; | |
3742 | ||
3743 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability); | |
3744 | *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id); | |
3745 | ||
3746 | out_free: | |
3747 | kfree(query_ctx); | |
3748 | return err; | |
3749 | } | |
3750 | ||
3751 | int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num) | |
3752 | { | |
3753 | u16 *old_entry, *vhca_map_entry, vhca_id; | |
3754 | int err; | |
3755 | ||
3756 | err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id); | |
3757 | if (err) { | |
3758 | esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n", | |
3759 | vport_num, err); | |
3760 | return err; | |
3761 | } | |
3762 | ||
3763 | vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL); | |
3764 | if (!vhca_map_entry) | |
3765 | return -ENOMEM; | |
3766 | ||
3767 | *vhca_map_entry = vport_num; | |
3768 | old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL); | |
3769 | if (xa_is_err(old_entry)) { | |
3770 | kfree(vhca_map_entry); | |
3771 | return xa_err(old_entry); | |
3772 | } | |
3773 | kfree(old_entry); | |
3774 | return 0; | |
3775 | } | |
3776 | ||
3777 | void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num) | |
3778 | { | |
3779 | u16 *vhca_map_entry, vhca_id; | |
3780 | int err; | |
3781 | ||
3782 | err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id); | |
3783 | if (err) | |
3784 | esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n", | |
3785 | vport_num, err); | |
3786 | ||
3787 | vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id); | |
3788 | kfree(vhca_map_entry); | |
3789 | } | |
3790 | ||
3791 | int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num) | |
3792 | { | |
3793 | u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id); | |
3794 | ||
3795 | if (!res) | |
3796 | return -ENOENT; | |
3797 | ||
3798 | *vport_num = *res; | |
3799 | return 0; | |
3800 | } | |
10742efc VB |
3801 | |
3802 | u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw, | |
3803 | u16 vport_num) | |
3804 | { | |
3805 | struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num); | |
3806 | ||
3807 | if (WARN_ON_ONCE(IS_ERR(vport))) | |
3808 | return 0; | |
3809 | ||
3810 | return vport->metadata; | |
3811 | } | |
3812 | EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set); |