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net/mlx5: E-Switch, Check and enable metadata support flag before using
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
ea651a86 41#include "esw/acl/ofld.h"
49964352 42#include "esw/chains.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
69697b6e 48
cd7e4186
BW		 49/* There are two match-all miss flows, one for unicast dst mac and
50 * one for multicast.
51 */
52#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 53#define UPLINK_REP_INDEX 0
54
96e32687
EC		 55/* Per vport tables */
56
57#define MLX5_ESW_VPORT_TABLE_SIZE 128
58
59/* This struct is used as a key to the hash table and we need it to be packed
60 * so hash result is consistent
61 */
62struct mlx5_vport_key {
63 u32 chain;
64 u16 prio;
65 u16 vport;
66 u16 vhca_id;
67} __packed;
68
69struct mlx5_vport_table {
70 struct hlist_node hlist;
71 struct mlx5_flow_table *fdb;
72 u32 num_rules;
73 struct mlx5_vport_key key;
74};
75
87dac697
JL		 76#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
77
96e32687
EC		 78static struct mlx5_flow_table *
79esw_vport_tbl_create(struct mlx5_eswitch *esw, struct mlx5_flow_namespace *ns)
80{
81 struct mlx5_flow_table_attr ft_attr = {};
82 struct mlx5_flow_table *fdb;
83
87dac697 84 ft_attr.autogroup.max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS;
96e32687
EC		 85 ft_attr.max_fte = MLX5_ESW_VPORT_TABLE_SIZE;
86 ft_attr.prio = FDB_PER_VPORT;
87 fdb = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
88 if (IS_ERR(fdb)) {
89 esw_warn(esw->dev, "Failed to create per vport FDB Table err %ld\n",
90 PTR_ERR(fdb));
91 }
92
93 return fdb;
94}
95
96static u32 flow_attr_to_vport_key(struct mlx5_eswitch *esw,
97 struct mlx5_esw_flow_attr *attr,
98 struct mlx5_vport_key *key)
99{
100 key->vport = attr->in_rep->vport;
101 key->chain = attr->chain;
102 key->prio = attr->prio;
103 key->vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
104 return jhash(key, sizeof(*key), 0);
105}
106
107/* caller must hold vports.lock */
108static struct mlx5_vport_table *
109esw_vport_tbl_lookup(struct mlx5_eswitch *esw, struct mlx5_vport_key *skey, u32 key)
110{
111 struct mlx5_vport_table *e;
112
113 hash_for_each_possible(esw->fdb_table.offloads.vports.table, e, hlist, key)
114 if (!memcmp(&e->key, skey, sizeof(*skey)))
115 return e;
116
117 return NULL;
118}
119
120static void
121esw_vport_tbl_put(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *attr)
122{
123 struct mlx5_vport_table *e;
124 struct mlx5_vport_key key;
125 u32 hkey;
126
127 mutex_lock(&esw->fdb_table.offloads.vports.lock);
128 hkey = flow_attr_to_vport_key(esw, attr, &key);
129 e = esw_vport_tbl_lookup(esw, &key, hkey);
130 if (!e || --e->num_rules)
131 goto out;
132
133 hash_del(&e->hlist);
134 mlx5_destroy_flow_table(e->fdb);
135 kfree(e);
136out:
137 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
138}
139
140static struct mlx5_flow_table *
141esw_vport_tbl_get(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *attr)
142{
143 struct mlx5_core_dev *dev = esw->dev;
144 struct mlx5_flow_namespace *ns;
145 struct mlx5_flow_table *fdb;
146 struct mlx5_vport_table *e;
147 struct mlx5_vport_key skey;
148 u32 hkey;
149
150 mutex_lock(&esw->fdb_table.offloads.vports.lock);
151 hkey = flow_attr_to_vport_key(esw, attr, &skey);
152 e = esw_vport_tbl_lookup(esw, &skey, hkey);
153 if (e) {
154 e->num_rules++;
155 goto out;
156 }
157
158 e = kzalloc(sizeof(*e), GFP_KERNEL);
159 if (!e) {
160 fdb = ERR_PTR(-ENOMEM);
161 goto err_alloc;
162 }
163
164 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
165 if (!ns) {
166 esw_warn(dev, "Failed to get FDB namespace\n");
167 fdb = ERR_PTR(-ENOENT);
168 goto err_ns;
169 }
170
171 fdb = esw_vport_tbl_create(esw, ns);
172 if (IS_ERR(fdb))
173 goto err_ns;
174
175 e->fdb = fdb;
176 e->num_rules = 1;
177 e->key = skey;
178 hash_add(esw->fdb_table.offloads.vports.table, &e->hlist, hkey);
179out:
180 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
181 return e->fdb;
182
183err_ns:
184 kfree(e);
185err_alloc:
186 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
187 return fdb;
188}
189
190int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw)
191{
192 struct mlx5_esw_flow_attr attr = {};
193 struct mlx5_eswitch_rep rep = {};
194 struct mlx5_flow_table *fdb;
195 struct mlx5_vport *vport;
196 int i;
197
198 attr.prio = 1;
199 attr.in_rep = &rep;
200 mlx5_esw_for_all_vports(esw, i, vport) {
201 attr.in_rep->vport = vport->vport;
202 fdb = esw_vport_tbl_get(esw, &attr);
d9fb932f 203 if (IS_ERR(fdb))
96e32687
EC		 204 goto out;
205 }
206 return 0;
207
208out:
209 mlx5_esw_vport_tbl_put(esw);
210 return PTR_ERR(fdb);
211}
212
213void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw)
214{
215 struct mlx5_esw_flow_attr attr = {};
216 struct mlx5_eswitch_rep rep = {};
217 struct mlx5_vport *vport;
218 int i;
219
220 attr.prio = 1;
221 attr.in_rep = &rep;
222 mlx5_esw_for_all_vports(esw, i, vport) {
223 attr.in_rep->vport = vport->vport;
224 esw_vport_tbl_put(esw, &attr);
225 }
226}
227
228/* End: Per vport tables */
229
879c8f84
BW		 230static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
231 u16 vport_num)
232{
02f3afd9 233 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
879c8f84
BW		 234
235 WARN_ON(idx > esw->total_vports - 1);
236 return &esw->offloads.vport_reps[idx];
237}
238
6f7bbad1
JL		 239static void
240mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
241 struct mlx5_flow_spec *spec,
242 struct mlx5_esw_flow_attr *attr)
243{
244 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
245 attr && attr->in_rep && attr->in_rep->vport == MLX5_VPORT_UPLINK)
246 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
247}
b7826076 248
c01cfd0f
JL		 249static void
250mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
251 struct mlx5_flow_spec *spec,
252 struct mlx5_esw_flow_attr *attr)
253{
254 void *misc2;
255 void *misc;
256
257 /* Use metadata matching because vport is not represented by single
258 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
259 */
260 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
261 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
262 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
263 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
264 attr->in_rep->vport));
265
266 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 267 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
268 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 269
270 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 271 } else {
272 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
273 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
274
275 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
276 MLX5_SET(fte_match_set_misc, misc,
277 source_eswitch_owner_vhca_id,
278 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
279
280 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
281 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
282 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
283 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
284 source_eswitch_owner_vhca_id);
285
286 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
287 }
c01cfd0f
JL		 288}
289
74491de9 290struct mlx5_flow_handle *
3d80d1a2
OG		 291mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
292 struct mlx5_flow_spec *spec,
776b12b6 293 struct mlx5_esw_flow_attr *attr)
3d80d1a2 294{
592d3651 295 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 296 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
e85e02ba 297 bool split = !!(attr->split_count);
74491de9 298 struct mlx5_flow_handle *rule;
e52c2802 299 struct mlx5_flow_table *fdb;
592d3651 300 int j, i = 0;
3d80d1a2 301
f6455de0 302 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 303 return ERR_PTR(-EOPNOTSUPP);
304
6acfbf38
OG		 305 flow_act.action = attr->action;
306 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 307 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 308 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
309 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
310 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
1482bd3d
JL		 311 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
312 flow_act.vlan[0].vid = attr->vlan_vid[0];
313 flow_act.vlan[0].prio = attr->vlan_prio[0];
cc495188
JL		 314 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
315 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
316 flow_act.vlan[1].vid = attr->vlan_vid[1];
317 flow_act.vlan[1].prio = attr->vlan_prio[1];
318 }
6acfbf38 319 }
776b12b6 320
66958ed9 321 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
39ac237c 322 struct mlx5_flow_table *ft;
e52c2802 323
d18296ff
PB		 324 if (attr->dest_ft) {
325 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
326 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
327 dest[i].ft = attr->dest_ft;
328 i++;
329 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
39ac237c
PB		 330 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
331 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
278d51f2 332 dest[i].ft = mlx5_esw_chains_get_tc_end_ft(esw);
39ac237c
PB		 333 i++;
334 } else if (attr->dest_chain) {
335 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
336 ft = mlx5_esw_chains_get_table(esw, attr->dest_chain,
337 1, 0);
e52c2802
PB		 338 if (IS_ERR(ft)) {
339 rule = ERR_CAST(ft);
340 goto err_create_goto_table;
341 }
342
343 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
344 dest[i].ft = ft;
592d3651 345 i++;
e52c2802 346 } else {
e85e02ba 347 for (j = attr->split_count; j < attr->out_count; j++) {
e52c2802 348 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
df65a573 349 dest[i].vport.num = attr->dests[j].rep->vport;
e52c2802 350 dest[i].vport.vhca_id =
df65a573 351 MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
aa39c2c0
EB		 352 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
353 dest[i].vport.flags |=
354 MLX5_FLOW_DEST_VPORT_VHCA_ID;
f493f155
EB		 355 if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
356 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2b688ea5 357 flow_act.pkt_reformat = attr->dests[j].pkt_reformat;
a18e879d 358 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
2b688ea5
MG		 359 dest[i].vport.pkt_reformat =
360 attr->dests[j].pkt_reformat;
f493f155 361 }
e52c2802
PB		 362 i++;
363 }
56e858df 364 }
e37a79e5 365 }
14e6b038
EC		 366
367 if (attr->decap_pkt_reformat)
368 flow_act.pkt_reformat = attr->decap_pkt_reformat;
369
66958ed9 370 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 371 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 372 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 373 i++;
3d80d1a2
OG		 374 }
375
93b3586e 376 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 377 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 378 if (attr->inner_match_level != MLX5_MATCH_NONE)
379 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 380
aa24670e 381 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 382 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 383
96e32687
EC		 384 if (split) {
385 fdb = esw_vport_tbl_get(esw, attr);
386 } else {
d18296ff
PB		 387 if (attr->chain || attr->prio)
388 fdb = mlx5_esw_chains_get_table(esw, attr->chain,
389 attr->prio, 0);
390 else
391 fdb = attr->fdb;
6fb0701a
PB		 392
393 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
394 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
96e32687 395 }
e52c2802
PB		 396 if (IS_ERR(fdb)) {
397 rule = ERR_CAST(fdb);
398 goto err_esw_get;
399 }
400
6f7bbad1
JL		 401 mlx5_eswitch_set_rule_flow_source(esw, spec, attr);
402
84be2fda 403 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
10caabda
OS		 404 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, attr,
405 &flow_act, dest, i);
84be2fda 406 else
10caabda 407 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 408 if (IS_ERR(rule))
e52c2802 409 goto err_add_rule;
375f51e2 410 else
525e84be 411 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 412
e52c2802
PB		 413 return rule;
414
415err_add_rule:
96e32687
EC		 416 if (split)
417 esw_vport_tbl_put(esw, attr);
d18296ff 418 else if (attr->chain || attr->prio)
96e32687 419 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
e52c2802 420err_esw_get:
39ac237c
PB		 421 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) && attr->dest_chain)
422 mlx5_esw_chains_put_table(esw, attr->dest_chain, 1, 0);
e52c2802 423err_create_goto_table:
aa0cbbae 424 return rule;
3d80d1a2
OG		 425}
426
e4ad91f2
CM		 427struct mlx5_flow_handle *
428mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
429 struct mlx5_flow_spec *spec,
430 struct mlx5_esw_flow_attr *attr)
431{
432 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 433 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
e52c2802
PB		 434 struct mlx5_flow_table *fast_fdb;
435 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 436 struct mlx5_flow_handle *rule;
e4ad91f2
CM		 437 int i;
438
39ac237c 439 fast_fdb = mlx5_esw_chains_get_table(esw, attr->chain, attr->prio, 0);
e52c2802
PB		 440 if (IS_ERR(fast_fdb)) {
441 rule = ERR_CAST(fast_fdb);
442 goto err_get_fast;
443 }
444
96e32687 445 fwd_fdb = esw_vport_tbl_get(esw, attr);
e52c2802
PB		 446 if (IS_ERR(fwd_fdb)) {
447 rule = ERR_CAST(fwd_fdb);
448 goto err_get_fwd;
449 }
450
e4ad91f2 451 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e85e02ba 452 for (i = 0; i < attr->split_count; i++) {
e4ad91f2 453 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
df65a573 454 dest[i].vport.num = attr->dests[i].rep->vport;
e4ad91f2 455 dest[i].vport.vhca_id =
df65a573 456 MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
aa39c2c0
EB		 457 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
458 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1cc26d74
EB		 459 if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
460 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
2b688ea5 461 dest[i].vport.pkt_reformat = attr->dests[i].pkt_reformat;
1cc26d74 462 }
e4ad91f2
CM		 463 }
464 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
e52c2802 465 dest[i].ft = fwd_fdb,
e4ad91f2
CM		 466 i++;
467
c01cfd0f 468 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
6f7bbad1 469 mlx5_eswitch_set_rule_flow_source(esw, spec, attr);
e4ad91f2 470
93b3586e 471 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 472 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 473
278d51f2 474 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 475 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 476
e52c2802
PB		 477 if (IS_ERR(rule))
478 goto add_err;
e4ad91f2 479
525e84be 480 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 481
482 return rule;
483add_err:
96e32687 484 esw_vport_tbl_put(esw, attr);
e52c2802 485err_get_fwd:
39ac237c 486 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
e52c2802 487err_get_fast:
e4ad91f2
CM		 488 return rule;
489}
490
e52c2802
PB		 491static void
492__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
493 struct mlx5_flow_handle *rule,
494 struct mlx5_esw_flow_attr *attr,
495 bool fwd_rule)
496{
e85e02ba 497 bool split = (attr->split_count > 0);
10caabda 498 int i;
e52c2802
PB		 499
500 mlx5_del_flow_rules(rule);
10caabda 501
84be2fda 502 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 503 /* unref the term table */
504 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
505 if (attr->dests[i].termtbl)
506 mlx5_eswitch_termtbl_put(esw, attr->dests[i].termtbl);
507 }
10caabda
OS		 508 }
509
525e84be 510 atomic64_dec(&esw->offloads.num_flows);
e52c2802
PB		 511
512 if (fwd_rule) {
96e32687 513 esw_vport_tbl_put(esw, attr);
39ac237c 514 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
e52c2802 515 } else {
96e32687
EC		 516 if (split)
517 esw_vport_tbl_put(esw, attr);
d18296ff 518 else if (attr->chain || attr->prio)
96e32687
EC		 519 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio,
520 0);
e52c2802 521 if (attr->dest_chain)
39ac237c 522 mlx5_esw_chains_put_table(esw, attr->dest_chain, 1, 0);
e52c2802
PB		 523 }
524}
525
d85cdccb
OG		 526void
527mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
528 struct mlx5_flow_handle *rule,
529 struct mlx5_esw_flow_attr *attr)
530{
e52c2802 531 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 532}
533
48265006
OG		 534void
535mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
536 struct mlx5_flow_handle *rule,
537 struct mlx5_esw_flow_attr *attr)
538{
e52c2802 539 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 540}
541
f5f82476
OG		 542static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
543{
544 struct mlx5_eswitch_rep *rep;
411ec9e0 545 int i, err = 0;
f5f82476
OG		 546
547 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
411ec9e0 548 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 549 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 550 continue;
551
552 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
553 if (err)
554 goto out;
555 }
556
557out:
558 return err;
559}
560
561static struct mlx5_eswitch_rep *
562esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
563{
564 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
565
566 in_rep = attr->in_rep;
df65a573 567 out_rep = attr->dests[0].rep;
f5f82476
OG		 568
569 if (push)
570 vport = in_rep;
571 else if (pop)
572 vport = out_rep;
573 else
574 vport = in_rep;
575
576 return vport;
577}
578
579static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
580 bool push, bool pop, bool fwd)
581{
582 struct mlx5_eswitch_rep *in_rep, *out_rep;
583
584 if ((push || pop) && !fwd)
585 goto out_notsupp;
586
587 in_rep = attr->in_rep;
df65a573 588 out_rep = attr->dests[0].rep;
f5f82476 589
b05af6aa 590 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 591 goto out_notsupp;
592
b05af6aa 593 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 594 goto out_notsupp;
595
596 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
597 if (!push && !pop && fwd)
b05af6aa 598 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 599 goto out_notsupp;
600
601 /* protects against (1) setting rules with different vlans to push and
602 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
603 */
1482bd3d 604 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 605 goto out_notsupp;
606
607 return 0;
608
609out_notsupp:
9eb78923 610 return -EOPNOTSUPP;
f5f82476
OG		 611}
612
613int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
614 struct mlx5_esw_flow_attr *attr)
615{
616 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
617 struct mlx5_eswitch_rep *vport = NULL;
618 bool push, pop, fwd;
619 int err = 0;
620
6acfbf38 621 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 622 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 623 return 0;
624
f5f82476
OG		 625 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
626 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 627 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
628 !attr->dest_chain);
f5f82476 629
0e18134f
VB		 630 mutex_lock(&esw->state_lock);
631
f5f82476
OG		 632 err = esw_add_vlan_action_check(attr, push, pop, fwd);
633 if (err)
0e18134f 634 goto unlock;
f5f82476 635
39ac237c 636 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 637
638 vport = esw_vlan_action_get_vport(attr, push, pop);
639
640 if (!push && !pop && fwd) {
641 /* tracks VF --> wire rules without vlan push action */
b05af6aa 642 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 643 vport->vlan_refcount++;
39ac237c 644 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 645 }
646
0e18134f 647 goto unlock;
f5f82476
OG		 648 }
649
650 if (!push && !pop)
0e18134f 651 goto unlock;
f5f82476
OG		 652
653 if (!(offloads->vlan_push_pop_refcount)) {
654 /* it's the 1st vlan rule, apply global vlan pop policy */
655 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
656 if (err)
657 goto out;
658 }
659 offloads->vlan_push_pop_refcount++;
660
661 if (push) {
662 if (vport->vlan_refcount)
663 goto skip_set_push;
664
1482bd3d 665 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
f5f82476
OG		 666 SET_VLAN_INSERT | SET_VLAN_STRIP);
667 if (err)
668 goto out;
1482bd3d 669 vport->vlan = attr->vlan_vid[0];
f5f82476
OG		 670skip_set_push:
671 vport->vlan_refcount++;
672 }
673out:
674 if (!err)
39ac237c 675 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 676unlock:
677 mutex_unlock(&esw->state_lock);
f5f82476
OG		 678 return err;
679}
680
681int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
682 struct mlx5_esw_flow_attr *attr)
683{
684 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
685 struct mlx5_eswitch_rep *vport = NULL;
686 bool push, pop, fwd;
687 int err = 0;
688
6acfbf38 689 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 690 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 691 return 0;
692
39ac237c 693 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 694 return 0;
695
696 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
697 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
698 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
699
0e18134f
VB		 700 mutex_lock(&esw->state_lock);
701
f5f82476
OG		 702 vport = esw_vlan_action_get_vport(attr, push, pop);
703
704 if (!push && !pop && fwd) {
705 /* tracks VF --> wire rules without vlan push action */
b05af6aa 706 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 707 vport->vlan_refcount--;
708
0e18134f 709 goto out;
f5f82476
OG		 710 }
711
712 if (push) {
713 vport->vlan_refcount--;
714 if (vport->vlan_refcount)
715 goto skip_unset_push;
716
717 vport->vlan = 0;
718 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
719 0, 0, SET_VLAN_STRIP);
720 if (err)
721 goto out;
722 }
723
724skip_unset_push:
725 offloads->vlan_push_pop_refcount--;
726 if (offloads->vlan_push_pop_refcount)
0e18134f 727 goto out;
f5f82476
OG		 728
729 /* no more vlan rules, stop global vlan pop policy */
730 err = esw_set_global_vlan_pop(esw, 0);
731
732out:
0e18134f 733 mutex_unlock(&esw->state_lock);
f5f82476
OG		 734 return err;
735}
736
f7a68945 737struct mlx5_flow_handle *
02f3afd9
PP		 738mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
739 u32 sqn)
ab22be9b 740{
66958ed9 741 struct mlx5_flow_act flow_act = {0};
4c5009c5 742 struct mlx5_flow_destination dest = {};
74491de9 743 struct mlx5_flow_handle *flow_rule;
c5bb1730 744 struct mlx5_flow_spec *spec;
ab22be9b
OG		 745 void *misc;
746
1b9a07ee 747 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 748 if (!spec) {
ab22be9b
OG		 749 flow_rule = ERR_PTR(-ENOMEM);
750 goto out;
751 }
752
c5bb1730 753 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 754 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a
BW		 755 /* source vport is the esw manager */
756 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
ab22be9b 757
c5bb1730 758 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 759 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
760 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
761
c5bb1730 762 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 763 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 764 dest.vport.num = vport;
66958ed9 765 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 766
39ac237c
PB		 767 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
768 spec, &flow_act, &dest, 1);
ab22be9b
OG		 769 if (IS_ERR(flow_rule))
770 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
771out:
c5bb1730 772 kvfree(spec);
ab22be9b
OG		 773 return flow_rule;
774}
57cbd893 775EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 776
159fe639
MB		 777void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
778{
779 mlx5_del_flow_rules(rule);
780}
781
5b7cb745
PB		 782static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
783{
784 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
785 MLX5_FDB_TO_VPORT_REG_C_1;
786}
787
332bd3a5 788static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 789{
790 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 791 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
792 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 793 u8 curr, wanted;
c1286050
JL		 794 int err;
795
5b7cb745
PB		 796 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
797 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 798 return 0;
c1286050 799
e08a6832
LR		 800 MLX5_SET(query_esw_vport_context_in, in, opcode,
801 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
802 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 803 if (err)
804 return err;
805
5b7cb745
PB		 806 curr = MLX5_GET(query_esw_vport_context_out, out,
807 esw_vport_context.fdb_to_vport_reg_c_id);
808 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
809 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
810 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 811
332bd3a5 812 if (enable)
5b7cb745 813 curr |= wanted;
332bd3a5 814 else
5b7cb745 815 curr &= ~wanted;
c1286050 816
e08a6832 817 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 818 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 819 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 820 field_select.fdb_to_vport_reg_c_id, 1);
821
e08a6832 822 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 823 if (!err) {
824 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
825 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
826 else
827 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
828 }
829
830 return err;
c1286050
JL		 831}
832
a5641cb5
JL		 833static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
834 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 835 struct mlx5_flow_spec *spec,
836 struct mlx5_flow_destination *dest)
837{
a5641cb5 838 void *misc;
ac004b83 839
a5641cb5
JL		 840 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
841 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
842 misc_parameters_2);
0f0d3827
PB		 843 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
844 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 845
a5641cb5
JL		 846 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
847 } else {
848 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
849 misc_parameters);
ac004b83 850
a5641cb5
JL		 851 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
852 MLX5_CAP_GEN(peer_dev, vhca_id));
853
854 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
855
856 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
857 misc_parameters);
858 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
859 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
860 source_eswitch_owner_vhca_id);
861 }
ac004b83
RD		 862
863 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 864 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 865 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 866 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 867}
868
a5641cb5
JL		 869static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
870 struct mlx5_eswitch *peer_esw,
871 struct mlx5_flow_spec *spec,
872 u16 vport)
873{
874 void *misc;
875
876 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
877 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
878 misc_parameters_2);
879 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
880 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
881 vport));
882 } else {
883 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
884 misc_parameters);
885 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
886 }
887}
888
ac004b83
RD		 889static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
890 struct mlx5_core_dev *peer_dev)
891{
892 struct mlx5_flow_destination dest = {};
893 struct mlx5_flow_act flow_act = {0};
894 struct mlx5_flow_handle **flows;
895 struct mlx5_flow_handle *flow;
896 struct mlx5_flow_spec *spec;
897 /* total vports is the same for both e-switches */
898 int nvports = esw->total_vports;
899 void *misc;
900 int err, i;
901
902 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
903 if (!spec)
904 return -ENOMEM;
905
a5641cb5 906 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 907
908 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
909 if (!flows) {
910 err = -ENOMEM;
911 goto alloc_flows_err;
912 }
913
914 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
915 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
916 misc_parameters);
917
81cd229c 918 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
a5641cb5
JL		 919 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
920 spec, MLX5_VPORT_PF);
921
81cd229c
BW		 922 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
923 spec, &flow_act, &dest, 1);
924 if (IS_ERR(flow)) {
925 err = PTR_ERR(flow);
926 goto add_pf_flow_err;
927 }
928 flows[MLX5_VPORT_PF] = flow;
929 }
930
931 if (mlx5_ecpf_vport_exists(esw->dev)) {
932 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
933 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
934 spec, &flow_act, &dest, 1);
935 if (IS_ERR(flow)) {
936 err = PTR_ERR(flow);
937 goto add_ecpf_flow_err;
938 }
939 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
940 }
941
786ef904 942 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 943 esw_set_peer_miss_rule_source_port(esw,
944 peer_dev->priv.eswitch,
945 spec, i);
946
ac004b83
RD		 947 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
948 spec, &flow_act, &dest, 1);
949 if (IS_ERR(flow)) {
950 err = PTR_ERR(flow);
81cd229c 951 goto add_vf_flow_err;
ac004b83
RD		 952 }
953 flows[i] = flow;
954 }
955
956 esw->fdb_table.offloads.peer_miss_rules = flows;
957
958 kvfree(spec);
959 return 0;
960
81cd229c 961add_vf_flow_err:
879c8f84 962 nvports = --i;
786ef904 963 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
ac004b83 964 mlx5_del_flow_rules(flows[i]);
81cd229c
BW		 965
966 if (mlx5_ecpf_vport_exists(esw->dev))
967 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
968add_ecpf_flow_err:
969 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
970 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
971add_pf_flow_err:
972 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 973 kvfree(flows);
974alloc_flows_err:
975 kvfree(spec);
976 return err;
977}
978
979static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
980{
981 struct mlx5_flow_handle **flows;
982 int i;
983
984 flows = esw->fdb_table.offloads.peer_miss_rules;
985
786ef904
PP		 986 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
987 mlx5_core_max_vfs(esw->dev))
ac004b83
RD		 988 mlx5_del_flow_rules(flows[i]);
989
81cd229c
BW		 990 if (mlx5_ecpf_vport_exists(esw->dev))
991 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
992
993 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
994 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
995
ac004b83
RD		 996 kvfree(flows);
997}
998
3aa33572
OG		 999static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1000{
66958ed9 1001 struct mlx5_flow_act flow_act = {0};
4c5009c5 1002 struct mlx5_flow_destination dest = {};
74491de9 1003 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1004 struct mlx5_flow_spec *spec;
f80be543
MB		 1005 void *headers_c;
1006 void *headers_v;
3aa33572 1007 int err = 0;
f80be543
MB		 1008 u8 *dmac_c;
1009 u8 *dmac_v;
3aa33572 1010
1b9a07ee 1011 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1012 if (!spec) {
3aa33572
OG		 1013 err = -ENOMEM;
1014 goto out;
1015 }
1016
f80be543
MB		 1017 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1018 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1019 outer_headers);
1020 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1021 outer_headers.dmac_47_16);
1022 dmac_c[0] = 0x01;
1023
3aa33572 1024 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1025 dest.vport.num = esw->manager_vport;
66958ed9 1026 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1027
39ac237c
PB		 1028 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1029 spec, &flow_act, &dest, 1);
3aa33572
OG		 1030 if (IS_ERR(flow_rule)) {
1031 err = PTR_ERR(flow_rule);
f80be543 1032 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1033 goto out;
1034 }
1035
f80be543
MB		 1036 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1037
1038 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1039 outer_headers);
1040 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1041 outer_headers.dmac_47_16);
1042 dmac_v[0] = 0x01;
39ac237c
PB		 1043 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1044 spec, &flow_act, &dest, 1);
f80be543
MB		 1045 if (IS_ERR(flow_rule)) {
1046 err = PTR_ERR(flow_rule);
1047 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1048 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1049 goto out;
1050 }
1051
1052 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1053
3aa33572 1054out:
c5bb1730 1055 kvfree(spec);
3aa33572
OG		 1056 return err;
1057}
1058
11b717d6
PB		 1059struct mlx5_flow_handle *
1060esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1061{
1062 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1063 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1064 struct mlx5_flow_context *flow_context;
1065 struct mlx5_flow_handle *flow_rule;
1066 struct mlx5_flow_destination dest;
1067 struct mlx5_flow_spec *spec;
1068 void *misc;
1069
60acc105
PB		 1070 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1071 return ERR_PTR(-EOPNOTSUPP);
1072
11b717d6
PB		 1073 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1074 if (!spec)
1075 return ERR_PTR(-ENOMEM);
1076
1077 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1078 misc_parameters_2);
1079 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1080 ESW_CHAIN_TAG_METADATA_MASK);
1081 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1082 misc_parameters_2);
1083 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1084 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1085 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1086 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1087 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1088
1089 flow_context = &spec->flow_context;
1090 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1091 flow_context->flow_tag = tag;
1092 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1093 dest.ft = esw->offloads.ft_offloads;
1094
1095 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1096 kfree(spec);
1097
1098 if (IS_ERR(flow_rule))
1099 esw_warn(esw->dev,
1100 "Failed to create restore rule for tag: %d, err(%d)\n",
1101 tag, (int)PTR_ERR(flow_rule));
1102
1103 return flow_rule;
1104}
1105
1106u32
1107esw_get_max_restore_tag(struct mlx5_eswitch *esw)
1108{
1109 return ESW_CHAIN_TAG_METADATA_MASK;
1110}
1111
1967ce6e 1112#define MAX_PF_SQ 256
cd3d07e7 1113#define MAX_SQ_NVPORTS 32
1967ce6e 1114
a5641cb5
JL		 1115static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1116 u32 *flow_group_in)
1117{
1118 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1119 flow_group_in,
1120 match_criteria);
1121
1122 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1123 MLX5_SET(create_flow_group_in, flow_group_in,
1124 match_criteria_enable,
1125 MLX5_MATCH_MISC_PARAMETERS_2);
1126
0f0d3827
PB		 1127 MLX5_SET(fte_match_param, match_criteria,
1128 misc_parameters_2.metadata_reg_c_0,
1129 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1130 } else {
1131 MLX5_SET(create_flow_group_in, flow_group_in,
1132 match_criteria_enable,
1133 MLX5_MATCH_MISC_PARAMETERS);
1134
1135 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1136 misc_parameters.source_port);
1137 }
1138}
1139
0da3c12d 1140static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1141{
1142 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1143 struct mlx5_flow_table_attr ft_attr = {};
1144 struct mlx5_core_dev *dev = esw->dev;
1145 struct mlx5_flow_namespace *root_ns;
1146 struct mlx5_flow_table *fdb = NULL;
39ac237c
PB		 1147 u32 flags = 0, *flow_group_in;
1148 int table_size, ix, err = 0;
1967ce6e
OG		 1149 struct mlx5_flow_group *g;
1150 void *match_criteria;
f80be543 1151 u8 *dmac;
1967ce6e
OG		 1152
1153 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1154
1b9a07ee 1155 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1156 if (!flow_group_in)
1157 return -ENOMEM;
1158
1159 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1160 if (!root_ns) {
1161 esw_warn(dev, "Failed to get FDB flow namespace\n");
1162 err = -EOPNOTSUPP;
1163 goto ns_err;
1164 }
8463daf1
MG		 1165 esw->fdb_table.offloads.ns = root_ns;
1166 err = mlx5_flow_namespace_set_mode(root_ns,
1167 esw->dev->priv.steering->mode);
1168 if (err) {
1169 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1170 goto ns_err;
1171 }
1967ce6e 1172
0da3c12d 1173 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
cd7e4186 1174 MLX5_ESW_MISS_FLOWS + esw->total_vports;
b3ba5149 1175
e52c2802
PB		 1176 /* create the slow path fdb with encap set, so further table instances
1177 * can be created at run time while VFs are probed if the FW allows that.
1178 */
1179 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1180 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1181 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1182
1183 ft_attr.flags = flags;
b3ba5149
ES		 1184 ft_attr.max_fte = table_size;
1185 ft_attr.prio = FDB_SLOW_PATH;
1186
1187 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1188 if (IS_ERR(fdb)) {
1189 err = PTR_ERR(fdb);
1190 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1191 goto slow_fdb_err;
1192 }
52fff327 1193 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1194
39ac237c
PB		 1195 err = mlx5_esw_chains_create(esw);
1196 if (err) {
1197 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1198 goto fdb_chains_err;
e52c2802
PB		 1199 }
1200
69697b6e 1201 /* create send-to-vport group */
69697b6e
OG		 1202 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1203 MLX5_MATCH_MISC_PARAMETERS);
1204
1205 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1206
1207 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1208 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1209
0da3c12d 1210 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1211 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1212 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1213
1214 g = mlx5_create_flow_group(fdb, flow_group_in);
1215 if (IS_ERR(g)) {
1216 err = PTR_ERR(g);
1217 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1218 goto send_vport_err;
1219 }
1220 esw->fdb_table.offloads.send_to_vport_grp = g;
1221
ac004b83
RD		 1222 /* create peer esw miss group */
1223 memset(flow_group_in, 0, inlen);
ac004b83 1224
a5641cb5
JL		 1225 esw_set_flow_group_source_port(esw, flow_group_in);
1226
1227 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1228 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1229 flow_group_in,
1230 match_criteria);
ac004b83 1231
a5641cb5
JL		 1232 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1233 misc_parameters.source_eswitch_owner_vhca_id);
1234
1235 MLX5_SET(create_flow_group_in, flow_group_in,
1236 source_eswitch_owner_vhca_id_valid, 1);
1237 }
ac004b83 1238
ac004b83
RD		 1239 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1240 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1241 ix + esw->total_vports - 1);
1242 ix += esw->total_vports;
1243
1244 g = mlx5_create_flow_group(fdb, flow_group_in);
1245 if (IS_ERR(g)) {
1246 err = PTR_ERR(g);
1247 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1248 goto peer_miss_err;
1249 }
1250 esw->fdb_table.offloads.peer_miss_grp = g;
1251
69697b6e
OG		 1252 /* create miss group */
1253 memset(flow_group_in, 0, inlen);
f80be543
MB		 1254 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1255 MLX5_MATCH_OUTER_HEADERS);
1256 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1257 match_criteria);
1258 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1259 outer_headers.dmac_47_16);
1260 dmac[0] = 0x01;
69697b6e
OG		 1261
1262 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1263 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1264 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1265
1266 g = mlx5_create_flow_group(fdb, flow_group_in);
1267 if (IS_ERR(g)) {
1268 err = PTR_ERR(g);
1269 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1270 goto miss_err;
1271 }
1272 esw->fdb_table.offloads.miss_grp = g;
1273
3aa33572
OG		 1274 err = esw_add_fdb_miss_rule(esw);
1275 if (err)
1276 goto miss_rule_err;
1277
c88a026e 1278 kvfree(flow_group_in);
69697b6e
OG		 1279 return 0;
1280
3aa33572
OG		 1281miss_rule_err:
1282 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1283miss_err:
ac004b83
RD		 1284 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1285peer_miss_err:
69697b6e
OG		 1286 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1287send_vport_err:
39ac237c
PB		 1288 mlx5_esw_chains_destroy(esw);
1289fdb_chains_err:
52fff327 1290 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1291slow_fdb_err:
8463daf1
MG		 1292 /* Holds true only as long as DMFS is the default */
1293 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1294ns_err:
1295 kvfree(flow_group_in);
1296 return err;
1297}
1298
1967ce6e 1299static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1300{
e52c2802 1301 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1302 return;
1303
1967ce6e 1304 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1305 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1306 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1307 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
ac004b83 1308 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1309 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1310
39ac237c 1311 mlx5_esw_chains_destroy(esw);
52fff327 1312 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1313 /* Holds true only as long as DMFS is the default */
1314 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1315 MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e 1316}
c116c6ee 1317
8d6bd3c3 1318static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1319{
b3ba5149 1320 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1321 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1322 struct mlx5_flow_table *ft_offloads;
1323 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1324 int err = 0;
1325
1326 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1327 if (!ns) {
1328 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1329 return -EOPNOTSUPP;
c116c6ee
OG		 1330 }
1331
8d6bd3c3 1332 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1333 ft_attr.prio = 1;
b3ba5149
ES		 1334
1335 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1336 if (IS_ERR(ft_offloads)) {
1337 err = PTR_ERR(ft_offloads);
1338 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1339 return err;
1340 }
1341
1342 esw->offloads.ft_offloads = ft_offloads;
1343 return 0;
1344}
1345
1346static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1347{
1348 struct mlx5_esw_offload *offloads = &esw->offloads;
1349
1350 mlx5_destroy_flow_table(offloads->ft_offloads);
1351}
fed9ce22 1352
8d6bd3c3 1353static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1354{
1355 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1356 struct mlx5_flow_group *g;
fed9ce22 1357 u32 *flow_group_in;
8d6bd3c3 1358 int nvports;
fed9ce22 1359 int err = 0;
fed9ce22 1360
8d6bd3c3 1361 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1362 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1363 if (!flow_group_in)
1364 return -ENOMEM;
1365
1366 /* create vport rx group */
a5641cb5 1367 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1368
1369 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1370 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1371
1372 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1373
1374 if (IS_ERR(g)) {
1375 err = PTR_ERR(g);
1376 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1377 goto out;
1378 }
1379
1380 esw->offloads.vport_rx_group = g;
1381out:
e574978a 1382 kvfree(flow_group_in);
fed9ce22
OG		 1383 return err;
1384}
1385
1386static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1387{
1388 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1389}
1390
74491de9 1391struct mlx5_flow_handle *
02f3afd9 1392mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1393 struct mlx5_flow_destination *dest)
fed9ce22 1394{
66958ed9 1395 struct mlx5_flow_act flow_act = {0};
74491de9 1396 struct mlx5_flow_handle *flow_rule;
c5bb1730 1397 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1398 void *misc;
1399
1b9a07ee 1400 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1401 if (!spec) {
fed9ce22
OG		 1402 flow_rule = ERR_PTR(-ENOMEM);
1403 goto out;
1404 }
1405
a5641cb5
JL		 1406 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1407 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1408 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1409 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1410
a5641cb5 1411 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1412 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1413 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1414
a5641cb5
JL		 1415 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1416 } else {
1417 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1418 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1419
1420 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1421 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1422
1423 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1424 }
fed9ce22 1425
66958ed9 1426 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1427 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1428 &flow_act, dest, 1);
fed9ce22
OG		 1429 if (IS_ERR(flow_rule)) {
1430 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1431 goto out;
1432 }
1433
1434out:
c5bb1730 1435 kvfree(spec);
fed9ce22
OG		 1436 return flow_rule;
1437}
feae9087 1438
bf3347c4 1439
cc617ced
PP		 1440static int mlx5_eswitch_inline_mode_get(const struct mlx5_eswitch *esw, u8 *mode)
1441{
1442 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1443 struct mlx5_core_dev *dev = esw->dev;
1444 int vport;
1445
1446 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1447 return -EOPNOTSUPP;
1448
1449 if (esw->mode == MLX5_ESWITCH_NONE)
1450 return -EOPNOTSUPP;
1451
1452 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1453 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1454 mlx5_mode = MLX5_INLINE_MODE_NONE;
1455 goto out;
1456 case MLX5_CAP_INLINE_MODE_L2:
1457 mlx5_mode = MLX5_INLINE_MODE_L2;
1458 goto out;
1459 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1460 goto query_vports;
1461 }
1462
1463query_vports:
1464 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
1465 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
1466 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
1467 if (prev_mlx5_mode != mlx5_mode)
1468 return -EINVAL;
1469 prev_mlx5_mode = mlx5_mode;
1470 }
1471
1472out:
1473 *mode = mlx5_mode;
1474 return 0;
e08a6832 1475}
bf3347c4 1476
11b717d6
PB		 1477static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1478{
1479 struct mlx5_esw_offload *offloads = &esw->offloads;
1480
60acc105
PB		 1481 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1482 return;
1483
6724e66b 1484 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 1485 mlx5_destroy_flow_group(offloads->restore_group);
1486 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
1487}
1488
1489static int esw_create_restore_table(struct mlx5_eswitch *esw)
1490{
d65dbedf 1491 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 1492 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1493 struct mlx5_flow_table_attr ft_attr = {};
1494 struct mlx5_core_dev *dev = esw->dev;
1495 struct mlx5_flow_namespace *ns;
6724e66b 1496 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 1497 void *match_criteria, *misc;
1498 struct mlx5_flow_table *ft;
1499 struct mlx5_flow_group *g;
1500 u32 *flow_group_in;
1501 int err = 0;
1502
60acc105
PB		 1503 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1504 return 0;
1505
11b717d6
PB		 1506 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1507 if (!ns) {
1508 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1509 return -EOPNOTSUPP;
1510 }
1511
1512 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1513 if (!flow_group_in) {
1514 err = -ENOMEM;
1515 goto out_free;
1516 }
1517
1518 ft_attr.max_fte = 1 << ESW_CHAIN_TAG_METADATA_BITS;
1519 ft = mlx5_create_flow_table(ns, &ft_attr);
1520 if (IS_ERR(ft)) {
1521 err = PTR_ERR(ft);
1522 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
1523 err);
1524 goto out_free;
1525 }
1526
1527 memset(flow_group_in, 0, inlen);
1528 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1529 match_criteria);
1530 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
1531 misc_parameters_2);
1532
1533 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1534 ESW_CHAIN_TAG_METADATA_MASK);
1535 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1536 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1537 ft_attr.max_fte - 1);
1538 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1539 MLX5_MATCH_MISC_PARAMETERS_2);
1540 g = mlx5_create_flow_group(ft, flow_group_in);
1541 if (IS_ERR(g)) {
1542 err = PTR_ERR(g);
1543 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
1544 err);
1545 goto err_group;
1546 }
1547
6724e66b
PB		 1548 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
1549 MLX5_SET(copy_action_in, modact, src_field,
1550 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
1551 MLX5_SET(copy_action_in, modact, dst_field,
1552 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
1553 mod_hdr = mlx5_modify_header_alloc(esw->dev,
1554 MLX5_FLOW_NAMESPACE_KERNEL, 1,
1555 modact);
1556 if (IS_ERR(mod_hdr)) {
e9864539 1557 err = PTR_ERR(mod_hdr);
6724e66b
PB		 1558 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
1559 err);
6724e66b
PB		 1560 goto err_mod_hdr;
1561 }
1562
11b717d6
PB		 1563 esw->offloads.ft_offloads_restore = ft;
1564 esw->offloads.restore_group = g;
6724e66b 1565 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 1566
c8508713
RD		 1567 kvfree(flow_group_in);
1568
11b717d6
PB		 1569 return 0;
1570
6724e66b
PB		 1571err_mod_hdr:
1572 mlx5_destroy_flow_group(g);
11b717d6
PB		 1573err_group:
1574 mlx5_destroy_flow_table(ft);
1575out_free:
1576 kvfree(flow_group_in);
1577
1578 return err;
cc617ced
PP		 1579}
1580
db7ff19e
EB		 1581static int esw_offloads_start(struct mlx5_eswitch *esw,
1582 struct netlink_ext_ack *extack)
c930a3ad 1583{
062f4bf4 1584 int err, err1;
c930a3ad 1585
8e0aa4bc
PP		 1586 mlx5_eswitch_disable_locked(esw, false);
1587 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
1588 esw->dev->priv.sriov.num_vfs);
6c419ba8 1589 if (err) {
8c98ee77
EB		 1590 NL_SET_ERR_MSG_MOD(extack,
1591 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 1592 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
1593 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 1594 if (err1) {
1595 NL_SET_ERR_MSG_MOD(extack,
1596 "Failed setting eswitch back to legacy");
1597 }
6c419ba8 1598 }
bffaa916
RD		 1599 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1600 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 1601 &esw->offloads.inline_mode)) {
1602 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 1603 NL_SET_ERR_MSG_MOD(extack,
1604 "Inline mode is different between vports");
bffaa916
RD		 1605 }
1606 }
c930a3ad
OG		 1607 return err;
1608}
1609
e8d31c4d
MB		 1610void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1611{
1612 kfree(esw->offloads.vport_reps);
1613}
1614
1615int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1616{
2752b823 1617 int total_vports = esw->total_vports;
e8d31c4d 1618 struct mlx5_eswitch_rep *rep;
d6518db2 1619 int vport_index;
ef2e4094 1620 u8 rep_type;
e8d31c4d 1621
2aca1787 1622 esw->offloads.vport_reps = kcalloc(total_vports,
e8d31c4d
MB		 1623 sizeof(struct mlx5_eswitch_rep),
1624 GFP_KERNEL);
1625 if (!esw->offloads.vport_reps)
1626 return -ENOMEM;
1627
d6518db2
BW		 1628 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1629 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
2f69e591 1630 rep->vport_index = vport_index;
f121e0ea
BW		 1631
1632 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
8693115a 1633 atomic_set(&rep->rep_data[rep_type].state,
6f4e0219 1634 REP_UNREGISTERED);
e8d31c4d
MB		 1635 }
1636
e8d31c4d
MB		 1637 return 0;
1638}
1639
c9b99abc
BW		 1640static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1641 struct mlx5_eswitch_rep *rep, u8 rep_type)
1642{
8693115a 1643 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 1644 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 1645 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 1646}
1647
4110fc59 1648static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 1649{
1650 struct mlx5_eswitch_rep *rep;
4110fc59
BW		 1651 int i;
1652
1653 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, esw->esw_funcs.num_vfs)
1654 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 1655
81cd229c
BW		 1656 if (mlx5_ecpf_vport_exists(esw->dev)) {
1657 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1658 __esw_offloads_unload_rep(esw, rep, rep_type);
1659 }
1660
1661 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1662 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1663 __esw_offloads_unload_rep(esw, rep, rep_type);
1664 }
1665
879c8f84 1666 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 1667 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1668}
1669
c2d7712c 1670int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 1671{
c2d7712c
BW		 1672 struct mlx5_eswitch_rep *rep;
1673 int rep_type;
a4b97ab4
MB		 1674 int err;
1675
c2d7712c
BW		 1676 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1677 return 0;
a4b97ab4 1678
c2d7712c
BW		 1679 rep = mlx5_eswitch_get_rep(esw, vport_num);
1680 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1681 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1682 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1683 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1684 if (err)
1685 goto err_reps;
1686 }
1687
1688 return 0;
a4b97ab4
MB		 1689
1690err_reps:
c2d7712c
BW		 1691 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
1692 for (--rep_type; rep_type >= 0; rep_type--)
1693 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1694 return err;
1695}
1696
c2d7712c
BW		 1697void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
1698{
1699 struct mlx5_eswitch_rep *rep;
1700 int rep_type;
1701
1702 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1703 return;
1704
1705 rep = mlx5_eswitch_get_rep(esw, vport_num);
1706 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
1707 __esw_offloads_unload_rep(esw, rep, rep_type);
1708}
1709
ac004b83
RD		 1710#define ESW_OFFLOADS_DEVCOM_PAIR (0)
1711#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1712
1713static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1714 struct mlx5_eswitch *peer_esw)
1715{
1716 int err;
1717
1718 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1719 if (err)
1720 return err;
1721
1722 return 0;
1723}
1724
1725static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1726{
d956873f 1727#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 1728 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 1729#endif
ac004b83
RD		 1730 esw_del_fdb_peer_miss_rules(esw);
1731}
1732
8463daf1
MG		 1733static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
1734 struct mlx5_eswitch *peer_esw,
1735 bool pair)
1736{
1737 struct mlx5_flow_root_namespace *peer_ns;
1738 struct mlx5_flow_root_namespace *ns;
1739 int err;
1740
1741 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
1742 ns = esw->dev->priv.steering->fdb_root_ns;
1743
1744 if (pair) {
1745 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
1746 if (err)
1747 return err;
1748
e53e6655 1749 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 1750 if (err) {
1751 mlx5_flow_namespace_set_peer(ns, NULL);
1752 return err;
1753 }
1754 } else {
1755 mlx5_flow_namespace_set_peer(ns, NULL);
1756 mlx5_flow_namespace_set_peer(peer_ns, NULL);
1757 }
1758
1759 return 0;
1760}
1761
ac004b83
RD		 1762static int mlx5_esw_offloads_devcom_event(int event,
1763 void *my_data,
1764 void *event_data)
1765{
1766 struct mlx5_eswitch *esw = my_data;
ac004b83 1767 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 1768 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 1769 int err;
1770
1771 switch (event) {
1772 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 1773 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1774 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1775 break;
1776
8463daf1 1777 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 1778 if (err)
1779 goto err_out;
8463daf1
MG		 1780 err = mlx5_esw_offloads_pair(esw, peer_esw);
1781 if (err)
1782 goto err_peer;
ac004b83
RD		 1783
1784 err = mlx5_esw_offloads_pair(peer_esw, esw);
1785 if (err)
1786 goto err_pair;
1787
1788 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1789 break;
1790
1791 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1792 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1793 break;
1794
1795 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1796 mlx5_esw_offloads_unpair(peer_esw);
1797 mlx5_esw_offloads_unpair(esw);
8463daf1 1798 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1799 break;
1800 }
1801
1802 return 0;
1803
1804err_pair:
1805 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 1806err_peer:
1807 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1808err_out:
1809 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1810 event, err);
1811 return err;
1812}
1813
1814static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1815{
1816 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1817
04de7dda
RD		 1818 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1819 mutex_init(&esw->offloads.peer_mutex);
1820
ac004b83
RD		 1821 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1822 return;
1823
1824 mlx5_devcom_register_component(devcom,
1825 MLX5_DEVCOM_ESW_OFFLOADS,
1826 mlx5_esw_offloads_devcom_event,
1827 esw);
1828
1829 mlx5_devcom_send_event(devcom,
1830 MLX5_DEVCOM_ESW_OFFLOADS,
1831 ESW_OFFLOADS_DEVCOM_PAIR, esw);
1832}
1833
1834static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
1835{
1836 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1837
1838 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1839 return;
1840
1841 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1842 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
1843
1844 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1845}
1846
92ab1eb3
JL		 1847static bool
1848esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
1849{
1850 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
1851 return false;
1852
1853 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1854 MLX5_FDB_TO_VPORT_REG_C_0))
1855 return false;
1856
1857 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
1858 return false;
1859
1860 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
1861 mlx5_ecpf_vport_exists(esw->dev))
1862 return false;
1863
1864 return true;
1865}
1866
1e62e222
MD		 1867static bool
1868esw_check_vport_match_metadata_mandatory(const struct mlx5_eswitch *esw)
1869{
1870 return mlx5_core_mp_enabled(esw->dev);
1871}
1872
1873static bool esw_use_vport_metadata(const struct mlx5_eswitch *esw)
1874{
1875 return esw_check_vport_match_metadata_mandatory(esw) &&
1876 esw_check_vport_match_metadata_supported(esw);
1877}
1878
133dcfc5
VP		 1879u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
1880{
1881 u32 num_vports = GENMASK(ESW_VPORT_BITS - 1, 0) - 1;
1882 u32 vhca_id_mask = GENMASK(ESW_VHCA_ID_BITS - 1, 0);
1883 u32 vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
1884 u32 start;
1885 u32 end;
1886 int id;
1887
1888 /* Make sure the vhca_id fits the ESW_VHCA_ID_BITS */
1889 WARN_ON_ONCE(vhca_id >= BIT(ESW_VHCA_ID_BITS));
1890
1891 /* Trim vhca_id to ESW_VHCA_ID_BITS */
1892 vhca_id &= vhca_id_mask;
1893
1894 start = (vhca_id << ESW_VPORT_BITS);
1895 end = start + num_vports;
1896 if (!vhca_id)
1897 start += 1; /* zero is reserved/invalid metadata */
1898 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, start, end, GFP_KERNEL);
1899
1900 return (id < 0) ? 0 : id;
1901}
1902
1903void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
1904{
1905 ida_free(&esw->offloads.vport_metadata_ida, metadata);
1906}
1907
1908static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
1909 struct mlx5_vport *vport)
1910{
1911 if (vport->vport == MLX5_VPORT_UPLINK)
1912 return 0;
1913
1914 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
1915 vport->metadata = vport->default_metadata;
1916 return vport->metadata ? 0 : -ENOSPC;
1917}
1918
1919static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
1920 struct mlx5_vport *vport)
1921{
1922 if (vport->vport == MLX5_VPORT_UPLINK || !vport->default_metadata)
1923 return;
1924
1925 WARN_ON(vport->metadata != vport->default_metadata);
1926 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
1927}
1928
748da30b 1929int
89a0f1fb
PP		 1930esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
1931 struct mlx5_vport *vport)
7445cfb1 1932{
7445cfb1
JL		 1933 int err;
1934
133dcfc5
VP		 1935 err = esw_offloads_vport_metadata_setup(esw, vport);
1936 if (err)
1937 goto metadata_err;
1938
07bab950 1939 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 1940 if (err)
133dcfc5 1941 goto ingress_err;
7445cfb1 1942
89a0f1fb 1943 if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
ea651a86 1944 err = esw_acl_egress_ofld_setup(esw, vport);
07bab950
VP		 1945 if (err)
1946 goto egress_err;
18486737 1947 }
07bab950
VP		 1948
1949 return 0;
1950
1951egress_err:
1952 esw_acl_ingress_ofld_cleanup(esw, vport);
133dcfc5
VP		 1953ingress_err:
1954 esw_offloads_vport_metadata_cleanup(esw, vport);
1955metadata_err:
89a0f1fb
PP		 1956 return err;
1957}
18486737 1958
748da30b 1959void
89a0f1fb
PP		 1960esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
1961 struct mlx5_vport *vport)
1962{
ea651a86 1963 esw_acl_egress_ofld_cleanup(vport);
07bab950 1964 esw_acl_ingress_ofld_cleanup(esw, vport);
133dcfc5 1965 esw_offloads_vport_metadata_cleanup(esw, vport);
89a0f1fb 1966}
7445cfb1 1967
748da30b 1968static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 1969{
1970 struct mlx5_vport *vport;
18486737 1971
748da30b 1972 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
4e9a9ef7 1973 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 1974}
1975
748da30b 1976static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 1977{
786ef904 1978 struct mlx5_vport *vport;
7445cfb1 1979
748da30b
VP		 1980 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
1981 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 1982}
1983
062f4bf4 1984static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a
MB		 1985{
1986 int err;
1987
5c1d260e 1988 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 1989 mutex_init(&esw->fdb_table.offloads.vports.lock);
1990 hash_init(esw->fdb_table.offloads.vports.table);
e52c2802 1991
748da30b 1992 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 1993 if (err)
f8d1edda 1994 goto create_acl_err;
18486737 1995
8d6bd3c3 1996 err = esw_create_offloads_table(esw);
c930a3ad 1997 if (err)
11b717d6 1998 goto create_offloads_err;
c930a3ad 1999
11b717d6 2000 err = esw_create_restore_table(esw);
c930a3ad 2001 if (err)
11b717d6
PB		 2002 goto create_restore_err;
2003
0da3c12d 2004 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2005 if (err)
2006 goto create_fdb_err;
c930a3ad 2007
8d6bd3c3 2008 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2009 if (err)
2010 goto create_fg_err;
2011
2012 return 0;
2013
2014create_fg_err:
1967ce6e 2015 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2016create_fdb_err:
11b717d6
PB		 2017 esw_destroy_restore_table(esw);
2018create_restore_err:
2019 esw_destroy_offloads_table(esw);
2020create_offloads_err:
748da30b 2021 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda
PP		 2022create_acl_err:
2023 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2024 return err;
2025}
2026
eca8cc38
BW		 2027static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2028{
2029 esw_destroy_vport_rx_group(esw);
eca8cc38 2030 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2031 esw_destroy_restore_table(esw);
2032 esw_destroy_offloads_table(esw);
748da30b 2033 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2034 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2035}
2036
7e736f9a
PP		 2037static void
2038esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2039{
5ccf2770 2040 bool host_pf_disabled;
7e736f9a 2041 u16 new_num_vfs;
a3888f33 2042
7e736f9a
PP		 2043 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2044 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2045 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2046 host_params_context.host_pf_disabled);
a3888f33 2047
7e736f9a
PP		 2048 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2049 return;
a3888f33
BW		 2050
2051 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2052 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2053 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2054 } else {
7e736f9a 2055 int err;
a3888f33 2056
23bb50cf
BW		 2057 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2058 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2059 if (err)
7e736f9a 2060 return;
a3888f33 2061 }
7e736f9a 2062 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2063}
2064
7e736f9a 2065static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2066{
7e736f9a
PP		 2067 struct mlx5_host_work *host_work;
2068 struct mlx5_eswitch *esw;
dd28087c 2069 const u32 *out;
ac35dcd6 2070
7e736f9a
PP		 2071 host_work = container_of(work, struct mlx5_host_work, work);
2072 esw = host_work->esw;
a3888f33 2073
dd28087c
PP		 2074 out = mlx5_esw_query_functions(esw->dev);
2075 if (IS_ERR(out))
7e736f9a 2076 goto out;
a3888f33 2077
7e736f9a 2078 esw_vfs_changed_event_handler(esw, out);
dd28087c 2079 kvfree(out);
a3888f33 2080out:
ac35dcd6
VP		 2081 kfree(host_work);
2082}
2083
16fff98a 2084int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2085{
cd56f929 2086 struct mlx5_esw_functions *esw_funcs;
a3888f33 2087 struct mlx5_host_work *host_work;
a3888f33
BW		 2088 struct mlx5_eswitch *esw;
2089
2090 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2091 if (!host_work)
2092 return NOTIFY_DONE;
2093
cd56f929
VP		 2094 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2095 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2096
2097 host_work->esw = esw;
2098
062f4bf4 2099 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2100 queue_work(esw->work_queue, &host_work->work);
2101
2102 return NOTIFY_OK;
2103}
2104
a53cf949
PP		 2105static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2106{
2107 const u32 *query_host_out;
2108
2109 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2110 return 0;
2111
2112 query_host_out = mlx5_esw_query_functions(esw->dev);
2113 if (IS_ERR(query_host_out))
2114 return PTR_ERR(query_host_out);
2115
2116 /* Mark non local controller with non zero controller number. */
2117 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2118 host_params_context.host_number);
2119 kvfree(query_host_out);
2120 return 0;
2121}
2122
5896b972 2123int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2124{
3b83b6c2
DL		 2125 struct mlx5_vport *vport;
2126 int err, i;
eca8cc38 2127
9a64144d
MG		 2128 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2129 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2130 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2131 else
2132 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2133
2bb72e7e 2134 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2135 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2136
a53cf949
PP		 2137 err = mlx5_esw_host_number_init(esw);
2138 if (err)
2139 goto err_vport_metadata;
2140
4e9a9ef7
VP		 2141 if (esw_use_vport_metadata(esw))
2142 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2143
332bd3a5
PP		 2144 err = esw_set_passing_vport_metadata(esw, true);
2145 if (err)
2146 goto err_vport_metadata;
c1286050 2147
7983a675
PB		 2148 err = esw_offloads_steering_init(esw);
2149 if (err)
2150 goto err_steering_init;
2151
3b83b6c2
DL		 2152 /* Representor will control the vport link state */
2153 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2154 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2155
c2d7712c
BW		 2156 /* Uplink vport rep must load first. */
2157 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2158 if (err)
c2d7712c 2159 goto err_uplink;
c1286050 2160
c2d7712c 2161 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2162 if (err)
c2d7712c 2163 goto err_vports;
eca8cc38
BW		 2164
2165 esw_offloads_devcom_init(esw);
a3888f33 2166
eca8cc38
BW		 2167 return 0;
2168
925a6acc 2169err_vports:
c2d7712c
BW		 2170 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2171err_uplink:
7983a675 2172 esw_offloads_steering_cleanup(esw);
79949985
PP		 2173err_steering_init:
2174 esw_set_passing_vport_metadata(esw, false);
7983a675 2175err_vport_metadata:
4e9a9ef7 2176 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2177 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2178 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2179 return err;
2180}
2181
db7ff19e
EB		 2182static int esw_offloads_stop(struct mlx5_eswitch *esw,
2183 struct netlink_ext_ack *extack)
c930a3ad 2184{
062f4bf4 2185 int err, err1;
c930a3ad 2186
8e0aa4bc
PP		 2187 mlx5_eswitch_disable_locked(esw, false);
2188 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2189 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2190 if (err) {
8c98ee77 2191 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2192 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2193 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2194 if (err1) {
2195 NL_SET_ERR_MSG_MOD(extack,
2196 "Failed setting eswitch back to offloads");
2197 }
6c419ba8 2198 }
c930a3ad
OG		 2199
2200 return err;
2201}
2202
5896b972 2203void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2204{
ac004b83 2205 esw_offloads_devcom_cleanup(esw);
5896b972 2206 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2207 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2208 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2209 esw_offloads_steering_cleanup(esw);
4e9a9ef7 2210 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2211 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2212 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2213 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2214}
2215
ef78618b 2216static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2217{
2218 switch (mode) {
2219 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2220 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2221 break;
2222 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2223 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2224 break;
2225 default:
2226 return -EINVAL;
2227 }
2228
2229 return 0;
2230}
2231
ef78618b
OG		 2232static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2233{
2234 switch (mlx5_mode) {
f6455de0 2235 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2236 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2237 break;
f6455de0 2238 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2239 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2240 break;
2241 default:
2242 return -EINVAL;
2243 }
2244
2245 return 0;
2246}
2247
bffaa916
RD		 2248static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2249{
2250 switch (mode) {
2251 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2252 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2253 break;
2254 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2255 *mlx5_mode = MLX5_INLINE_MODE_L2;
2256 break;
2257 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2258 *mlx5_mode = MLX5_INLINE_MODE_IP;
2259 break;
2260 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2261 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2262 break;
2263 default:
2264 return -EINVAL;
2265 }
2266
2267 return 0;
2268}
2269
2270static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2271{
2272 switch (mlx5_mode) {
2273 case MLX5_INLINE_MODE_NONE:
2274 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2275 break;
2276 case MLX5_INLINE_MODE_L2:
2277 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2278 break;
2279 case MLX5_INLINE_MODE_IP:
2280 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2281 break;
2282 case MLX5_INLINE_MODE_TCP_UDP:
2283 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2284 break;
2285 default:
2286 return -EINVAL;
2287 }
2288
2289 return 0;
2290}
2291
ae24432c
PP		 2292static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2293{
2294 /* devlink commands in NONE eswitch mode are currently supported only
2295 * on ECPF.
2296 */
2297 return (esw->mode == MLX5_ESWITCH_NONE &&
2298 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2299}
2300
db7ff19e
EB		 2301int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2302 struct netlink_ext_ack *extack)
9d1cef19 2303{
9d1cef19 2304 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2305 struct mlx5_eswitch *esw;
ea2128fd 2306 int err = 0;
9d1cef19 2307
bd939753
PP		 2308 esw = mlx5_devlink_eswitch_get(devlink);
2309 if (IS_ERR(esw))
2310 return PTR_ERR(esw);
9d1cef19 2311
ef78618b 2312 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2313 return -EINVAL;
2314
8e0aa4bc 2315 mutex_lock(&esw->mode_lock);
8e0aa4bc 2316 cur_mlx5_mode = esw->mode;
c930a3ad 2317 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 2318 goto unlock;
c930a3ad
OG		 2319
2320 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 2321 err = esw_offloads_start(esw, extack);
c930a3ad 2322 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 2323 err = esw_offloads_stop(esw, extack);
c930a3ad 2324 else
8e0aa4bc
PP		 2325 err = -EINVAL;
2326
2327unlock:
2328 mutex_unlock(&esw->mode_lock);
2329 return err;
feae9087
OG		 2330}
2331
2332int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2333{
bd939753 2334 struct mlx5_eswitch *esw;
9d1cef19 2335 int err;
c930a3ad 2336
bd939753
PP		 2337 esw = mlx5_devlink_eswitch_get(devlink);
2338 if (IS_ERR(esw))
2339 return PTR_ERR(esw);
c930a3ad 2340
8e0aa4bc 2341 mutex_lock(&esw->mode_lock);
bd939753 2342 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 2343 if (err)
8e0aa4bc 2344 goto unlock;
ae24432c 2345
8e0aa4bc
PP		 2346 err = esw_mode_to_devlink(esw->mode, mode);
2347unlock:
2348 mutex_unlock(&esw->mode_lock);
2349 return err;
feae9087 2350}
127ea380 2351
db7ff19e
EB		 2352int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2353 struct netlink_ext_ack *extack)
bffaa916
RD		 2354{
2355 struct mlx5_core_dev *dev = devlink_priv(devlink);
db68cc56 2356 int err, vport, num_vport;
bd939753 2357 struct mlx5_eswitch *esw;
bffaa916
RD		 2358 u8 mlx5_mode;
2359
bd939753
PP		 2360 esw = mlx5_devlink_eswitch_get(devlink);
2361 if (IS_ERR(esw))
2362 return PTR_ERR(esw);
bffaa916 2363
8e0aa4bc 2364 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2365 err = eswitch_devlink_esw_mode_check(esw);
2366 if (err)
8e0aa4bc 2367 goto out;
ae24432c 2368
c415f704
OG		 2369 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2370 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2371 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 2372 goto out;
c8b838d1 2373 fallthrough;
c415f704 2374 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 2375 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 2376 err = -EOPNOTSUPP;
2377 goto out;
c415f704
OG		 2378 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2379 break;
2380 }
bffaa916 2381
525e84be 2382 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2383 NL_SET_ERR_MSG_MOD(extack,
2384 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 2385 err = -EOPNOTSUPP;
2386 goto out;
375f51e2
RD		 2387 }
2388
bffaa916
RD		 2389 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2390 if (err)
2391 goto out;
2392
411ec9e0 2393 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
bffaa916
RD		 2394 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2395 if (err) {
8c98ee77
EB		 2396 NL_SET_ERR_MSG_MOD(extack,
2397 "Failed to set min inline on vport");
bffaa916
RD		 2398 goto revert_inline_mode;
2399 }
2400 }
2401
2402 esw->offloads.inline_mode = mlx5_mode;
8e0aa4bc 2403 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2404 return 0;
2405
2406revert_inline_mode:
db68cc56 2407 num_vport = --vport;
411ec9e0 2408 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
bffaa916
RD		 2409 mlx5_modify_nic_vport_min_inline(dev,
2410 vport,
2411 esw->offloads.inline_mode);
2412out:
8e0aa4bc 2413 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2414 return err;
2415}
2416
2417int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2418{
bd939753 2419 struct mlx5_eswitch *esw;
9d1cef19 2420 int err;
bffaa916 2421
bd939753
PP		 2422 esw = mlx5_devlink_eswitch_get(devlink);
2423 if (IS_ERR(esw))
2424 return PTR_ERR(esw);
bffaa916 2425
8e0aa4bc 2426 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2427 err = eswitch_devlink_esw_mode_check(esw);
2428 if (err)
8e0aa4bc 2429 goto unlock;
ae24432c 2430
8e0aa4bc
PP		 2431 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2432unlock:
2433 mutex_unlock(&esw->mode_lock);
2434 return err;
bffaa916
RD		 2435}
2436
98fdbea5
LR		 2437int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2438 enum devlink_eswitch_encap_mode encap,
db7ff19e 2439 struct netlink_ext_ack *extack)
7768d197
RD		 2440{
2441 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 2442 struct mlx5_eswitch *esw;
7768d197
RD		 2443 int err;
2444
bd939753
PP		 2445 esw = mlx5_devlink_eswitch_get(devlink);
2446 if (IS_ERR(esw))
2447 return PTR_ERR(esw);
7768d197 2448
8e0aa4bc 2449 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2450 err = eswitch_devlink_esw_mode_check(esw);
2451 if (err)
8e0aa4bc 2452 goto unlock;
ae24432c 2453
7768d197 2454 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 2455 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 2456 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
2457 err = -EOPNOTSUPP;
2458 goto unlock;
2459 }
7768d197 2460
8e0aa4bc
PP		 2461 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
2462 err = -EOPNOTSUPP;
2463 goto unlock;
2464 }
7768d197 2465
f6455de0 2466 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 2467 esw->offloads.encap = encap;
8e0aa4bc 2468 goto unlock;
7768d197
RD		 2469 }
2470
2471 if (esw->offloads.encap == encap)
8e0aa4bc 2472 goto unlock;
7768d197 2473
525e84be 2474 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2475 NL_SET_ERR_MSG_MOD(extack,
2476 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 2477 err = -EOPNOTSUPP;
2478 goto unlock;
7768d197
RD		 2479 }
2480
e52c2802 2481 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 2482
2483 esw->offloads.encap = encap;
e52c2802 2484
0da3c12d 2485 err = esw_create_offloads_fdb_tables(esw);
e52c2802 2486
7768d197 2487 if (err) {
8c98ee77
EB		 2488 NL_SET_ERR_MSG_MOD(extack,
2489 "Failed re-creating fast FDB table");
7768d197 2490 esw->offloads.encap = !encap;
0da3c12d 2491 (void)esw_create_offloads_fdb_tables(esw);
7768d197 2492 }
e52c2802 2493
8e0aa4bc
PP		 2494unlock:
2495 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2496 return err;
2497}
2498
98fdbea5
LR		 2499int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2500 enum devlink_eswitch_encap_mode *encap)
7768d197 2501{
bd939753 2502 struct mlx5_eswitch *esw;
9d1cef19 2503 int err;
7768d197 2504
bd939753
PP		 2505 esw = mlx5_devlink_eswitch_get(devlink);
2506 if (IS_ERR(esw))
2507 return PTR_ERR(esw);
2508
7768d197 2509
8e0aa4bc 2510 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2511 err = eswitch_devlink_esw_mode_check(esw);
2512 if (err)
8e0aa4bc 2513 goto unlock;
ae24432c 2514
7768d197 2515 *encap = esw->offloads.encap;
8e0aa4bc
PP		 2516unlock:
2517 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2518 return 0;
2519}
2520
c2d7712c
BW		 2521static bool
2522mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
2523{
2524 /* Currently, only ECPF based device has representor for host PF. */
2525 if (vport_num == MLX5_VPORT_PF &&
2526 !mlx5_core_is_ecpf_esw_manager(esw->dev))
2527 return false;
2528
2529 if (vport_num == MLX5_VPORT_ECPF &&
2530 !mlx5_ecpf_vport_exists(esw->dev))
2531 return false;
2532
2533 return true;
2534}
2535
f8e8fa02 2536void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 2537 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 2538 u8 rep_type)
127ea380 2539{
8693115a 2540 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02
BW		 2541 struct mlx5_eswitch_rep *rep;
2542 int i;
9deb2241 2543
8693115a 2544 esw->offloads.rep_ops[rep_type] = ops;
f8e8fa02 2545 mlx5_esw_for_all_reps(esw, i, rep) {
c2d7712c
BW		 2546 if (likely(mlx5_eswitch_vport_has_rep(esw, i))) {
2547 rep_data = &rep->rep_data[rep_type];
2548 atomic_set(&rep_data->state, REP_REGISTERED);
2549 }
f8e8fa02 2550 }
127ea380 2551}
f8e8fa02 2552EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 2553
f8e8fa02 2554void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 2555{
cb67b832 2556 struct mlx5_eswitch_rep *rep;
f8e8fa02 2557 int i;
cb67b832 2558
f6455de0 2559 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 2560 __unload_reps_all_vport(esw, rep_type);
127ea380 2561
f8e8fa02 2562 mlx5_esw_for_all_reps(esw, i, rep)
8693115a 2563 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 2564}
f8e8fa02 2565EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 2566
a4b97ab4 2567void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 2568{
726293f1
HHZ		 2569 struct mlx5_eswitch_rep *rep;
2570
879c8f84 2571 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 2572 return rep->rep_data[rep_type].priv;
726293f1 2573}
22215908
MB		 2574
2575void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 2576 u16 vport,
22215908
MB		 2577 u8 rep_type)
2578{
22215908
MB		 2579 struct mlx5_eswitch_rep *rep;
2580
879c8f84 2581 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 2582
8693115a
PP		 2583 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2584 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2585 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 2586 return NULL;
2587}
57cbd893 2588EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 2589
2590void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2591{
879c8f84 2592 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 2593}
57cbd893
MB		 2594EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2595
2596struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 2597 u16 vport)
57cbd893 2598{
879c8f84 2599 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 2600}
2601EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c
PP		 2602
2603bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2604{
2605 return vport_num >= MLX5_VPORT_FIRST_VF &&
2606 vport_num <= esw->dev->priv.sriov.max_vfs;
2607}
7445cfb1 2608
5b7cb745
PB		 2609bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
2610{
2611 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
2612}
2613EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
2614
7445cfb1
JL		 2615bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2616{
2617 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2618}
2619EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2620
0f0d3827 2621u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 2622 u16 vport_num)
2623{
133dcfc5 2624 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 2625
133dcfc5
VP		 2626 if (WARN_ON_ONCE(IS_ERR(vport)))
2627 return 0;
0f0d3827 2628
133dcfc5 2629 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 2630}
2631EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
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