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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
69697b6e 51
47dd7e60
PP		 52#define mlx5_esw_for_each_rep(esw, i, rep) \
53 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
54
55#define mlx5_esw_for_each_sf_rep(esw, i, rep) \
56 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
57
58#define mlx5_esw_for_each_vf_rep(esw, index, rep) \
59 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
60 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
61
cd7e4186
BW		 62/* There are two match-all miss flows, one for unicast dst mac and
63 * one for multicast.
64 */
65#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 66#define UPLINK_REP_INDEX 0
67
c796bb7c
CM		 68#define MLX5_ESW_VPORT_TBL_SIZE 128
69#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
70
71static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
72 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
73 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
74 .flags = 0,
75};
76
879c8f84
BW		 77static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
78 u16 vport_num)
79{
47dd7e60 80 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 81}
82
6f7bbad1
JL		 83static void
84mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
85 struct mlx5_flow_spec *spec,
86 struct mlx5_esw_flow_attr *attr)
87{
88 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
036e19b9
HI		 89 attr && attr->in_rep)
90 spec->flow_context.flow_source =
91 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
92 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
93 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 94}
b7826076 95
f94d6389
CM		 96/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
97 * are not needed as well in the following process. So clear them all for simplicity.
98 */
99void
100mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
101{
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
103 void *misc2;
104
105 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
106 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
107
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
110
111 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
112 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
113 }
114}
115
c01cfd0f
JL		 116static void
117mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
118 struct mlx5_flow_spec *spec,
a508728a 119 struct mlx5_flow_attr *attr,
b055ecf5
MB		 120 struct mlx5_eswitch *src_esw,
121 u16 vport)
c01cfd0f
JL		 122{
123 void *misc2;
124 void *misc;
125
126 /* Use metadata matching because vport is not represented by single
127 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
128 */
129 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 130 if (mlx5_esw_indir_table_decap_vport(attr))
131 vport = mlx5_esw_indir_table_decap_vport(attr);
c01cfd0f
JL		 132 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
133 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
b055ecf5
MB		 134 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
135 vport));
c01cfd0f
JL		 136
137 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 138 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
139 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 140
141 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 142 } else {
143 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 144 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 145
146 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
147 MLX5_SET(fte_match_set_misc, misc,
148 source_eswitch_owner_vhca_id,
b055ecf5 149 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 150
151 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
152 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
153 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
154 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
155 source_eswitch_owner_vhca_id);
156
157 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
158 }
c01cfd0f
JL		 159}
160
a508728a
VB		 161static int
162esw_setup_decap_indir(struct mlx5_eswitch *esw,
163 struct mlx5_flow_attr *attr,
164 struct mlx5_flow_spec *spec)
165{
166 struct mlx5_flow_table *ft;
167
168 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
169 return -EOPNOTSUPP;
170
171 ft = mlx5_esw_indir_table_get(esw, attr, spec,
172 mlx5_esw_indir_table_decap_vport(attr), true);
173 return PTR_ERR_OR_ZERO(ft);
174}
175
9e51c0a6 176static void
a508728a
VB		 177esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
178 struct mlx5_flow_attr *attr)
179{
180 if (mlx5_esw_indir_table_decap_vport(attr))
181 mlx5_esw_indir_table_put(esw, attr,
182 mlx5_esw_indir_table_decap_vport(attr),
183 true);
184}
185
f94d6389
CM		 186static int
187esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
188 struct mlx5_flow_act *flow_act,
189 struct mlx5_esw_flow_attr *esw_attr,
190 int i)
191{
192 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
193 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
194 dest[i].sampler_id = esw_attr->sample->sampler_id;
195
196 return 0;
197}
198
a508728a 199static int
9e51c0a6
VB		 200esw_setup_ft_dest(struct mlx5_flow_destination *dest,
201 struct mlx5_flow_act *flow_act,
a508728a 202 struct mlx5_eswitch *esw,
9e51c0a6 203 struct mlx5_flow_attr *attr,
a508728a 204 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 205 int i)
206{
207 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
208 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
209 dest[i].ft = attr->dest_ft;
a508728a
VB		 210
211 if (mlx5_esw_indir_table_decap_vport(attr))
212 return esw_setup_decap_indir(esw, attr, spec);
213 return 0;
9e51c0a6
VB		 214}
215
216static void
217esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,
218 struct mlx5_flow_act *flow_act,
219 struct mlx5_fs_chains *chains,
220 int i)
221{
2a2c84fa
RD		 222 if (mlx5_chains_ignore_flow_level_supported(chains))
223 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
9e51c0a6
VB		 224 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
225 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
226}
227
228static int
229esw_setup_chain_dest(struct mlx5_flow_destination *dest,
230 struct mlx5_flow_act *flow_act,
231 struct mlx5_fs_chains *chains,
232 u32 chain, u32 prio, u32 level,
233 int i)
234{
235 struct mlx5_flow_table *ft;
236
237 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
238 ft = mlx5_chains_get_table(chains, chain, prio, level);
239 if (IS_ERR(ft))
240 return PTR_ERR(ft);
241
242 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
243 dest[i].ft = ft;
244 return 0;
245}
246
10742efc
VB		 247static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
248 int from, int to)
249{
250 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
251 struct mlx5_fs_chains *chains = esw_chains(esw);
252 int i;
253
254 for (i = from; i < to; i++)
255 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
256 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 257 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
258 esw_attr->dests[i].mdev))
259 mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport,
260 false);
10742efc
VB		 261}
262
263static bool
264esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
265{
266 int i;
267
268 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
269 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
270 return true;
271 return false;
272}
273
274static int
275esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
276 struct mlx5_flow_act *flow_act,
277 struct mlx5_eswitch *esw,
278 struct mlx5_fs_chains *chains,
279 struct mlx5_flow_attr *attr,
280 int *i)
281{
282 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
283 int j, err;
284
285 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
286 return -EOPNOTSUPP;
287
288 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
289 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
290 if (err)
291 goto err_setup_chain;
292 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
293 flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat;
294 }
295 return 0;
296
297err_setup_chain:
298 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
299 return err;
300}
301
302static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
303 struct mlx5_flow_attr *attr)
304{
305 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
306
307 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
308}
309
a508728a
VB		 310static bool
311esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
312{
313 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
314 int i;
315
316 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
317 if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
318 esw_attr->dests[i].mdev))
319 return true;
320 return false;
321}
322
323static int
324esw_setup_indir_table(struct mlx5_flow_destination *dest,
325 struct mlx5_flow_act *flow_act,
326 struct mlx5_eswitch *esw,
327 struct mlx5_flow_attr *attr,
328 struct mlx5_flow_spec *spec,
329 bool ignore_flow_lvl,
330 int *i)
331{
332 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
333 int j, err;
334
335 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
336 return -EOPNOTSUPP;
337
338 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
339 if (ignore_flow_lvl)
340 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
341 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
342
343 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec,
344 esw_attr->dests[j].rep->vport, false);
345 if (IS_ERR(dest[*i].ft)) {
346 err = PTR_ERR(dest[*i].ft);
347 goto err_indir_tbl_get;
348 }
349 }
350
351 if (mlx5_esw_indir_table_decap_vport(attr)) {
352 err = esw_setup_decap_indir(esw, attr, spec);
353 if (err)
354 goto err_indir_tbl_get;
355 }
356
357 return 0;
358
359err_indir_tbl_get:
360 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
361 return err;
362}
363
364static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
365{
366 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
367
368 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
369 esw_cleanup_decap_indir(esw, attr);
370}
371
9e51c0a6
VB		 372static void
373esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
374{
375 mlx5_chains_put_table(chains, chain, prio, level);
376}
377
378static void
379esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
380 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
381 int attr_idx, int dest_idx, bool pkt_reformat)
382{
383 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
384 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
c6719725
MD		 385 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
386 dest[dest_idx].vport.vhca_id =
387 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
9e51c0a6 388 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
c6719725 389 }
9e51c0a6
VB		 390 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
391 if (pkt_reformat) {
392 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
393 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
394 }
395 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
396 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
397 }
398}
399
400static int
401esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
402 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
403 int i)
404{
405 int j;
406
407 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
408 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
409 return i;
410}
411
e929e3da
MD		 412static bool
413esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
414{
415 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
416 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
417 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
418}
419
9e51c0a6
VB		 420static int
421esw_setup_dests(struct mlx5_flow_destination *dest,
422 struct mlx5_flow_act *flow_act,
423 struct mlx5_eswitch *esw,
424 struct mlx5_flow_attr *attr,
10742efc 425 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 426 int *i)
427{
428 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
429 struct mlx5_fs_chains *chains = esw_chains(esw);
430 int err = 0;
431
10742efc 432 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 433 esw_src_port_rewrite_supported(esw))
10742efc
VB		 434 attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE;
435
f94d6389
CM		 436 if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) {
437 esw_setup_sampler_dest(dest, flow_act, esw_attr, *i);
438 (*i)++;
439 } else if (attr->dest_ft) {
a508728a 440 esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);
9e51c0a6
VB		 441 (*i)++;
442 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
443 esw_setup_slow_path_dest(dest, flow_act, chains, *i);
444 (*i)++;
445 } else if (attr->dest_chain) {
446 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
447 1, 0, *i);
448 (*i)++;
a508728a
VB		 449 } else if (esw_is_indir_table(esw, attr)) {
450 err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i);
10742efc
VB		 451 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
452 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 453 } else {
454 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
455 }
456
457 return err;
458}
459
460static void
461esw_cleanup_dests(struct mlx5_eswitch *esw,
462 struct mlx5_flow_attr *attr)
463{
10742efc 464 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 465 struct mlx5_fs_chains *chains = esw_chains(esw);
466
a508728a
VB		 467 if (attr->dest_ft) {
468 esw_cleanup_decap_indir(esw, attr);
469 } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
10742efc
VB		 470 if (attr->dest_chain)
471 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 472 else if (esw_is_indir_table(esw, attr))
473 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 474 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
475 esw_cleanup_chain_src_port_rewrite(esw, attr);
476 }
9e51c0a6
VB		 477}
478
74491de9 479struct mlx5_flow_handle *
3d80d1a2
OG		 480mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
481 struct mlx5_flow_spec *spec,
c620b772 482 struct mlx5_flow_attr *attr)
3d80d1a2 483{
592d3651 484 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 485 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 486 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 487 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 488 bool split = !!(esw_attr->split_count);
489 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 490 struct mlx5_flow_handle *rule;
e52c2802 491 struct mlx5_flow_table *fdb;
9e51c0a6 492 int i = 0;
3d80d1a2 493
f6455de0 494 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 495 return ERR_PTR(-EOPNOTSUPP);
496
6acfbf38
OG		 497 flow_act.action = attr->action;
498 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 499 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 500 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
501 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
502 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 503 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
504 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
505 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 506 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 507 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
508 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
509 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 510 }
6acfbf38 511 }
776b12b6 512
10742efc
VB		 513 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
514
66958ed9 515 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 516 int err;
517
10742efc 518 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 519 if (err) {
520 rule = ERR_PTR(err);
521 goto err_create_goto_table;
56e858df 522 }
e37a79e5 523 }
14e6b038 524
c620b772
AL		 525 if (esw_attr->decap_pkt_reformat)
526 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 527
66958ed9 528 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 529 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 530 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 531 i++;
3d80d1a2
OG		 532 }
533
93b3586e 534 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 535 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 536 if (attr->inner_match_level != MLX5_MATCH_NONE)
537 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 538
aa24670e 539 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 540 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 541
f94d6389
CM		 542 /* esw_attr->sample is allocated only when there is a sample action */
543 if (esw_attr->sample && esw_attr->sample->sample_default_tbl) {
544 fdb = esw_attr->sample->sample_default_tbl;
545 } else if (split) {
c620b772
AL		 546 fwd_attr.chain = attr->chain;
547 fwd_attr.prio = attr->prio;
548 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 549 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 550
0a9e2307 551 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 552 } else {
d18296ff 553 if (attr->chain || attr->prio)
ae430332
AL		 554 fdb = mlx5_chains_get_table(chains, attr->chain,
555 attr->prio, 0);
d18296ff 556 else
c620b772 557 fdb = attr->ft;
6fb0701a
PB		 558
559 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
a508728a 560 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 561 esw_attr->in_mdev->priv.eswitch,
562 esw_attr->in_rep->vport);
96e32687 563 }
e52c2802
PB		 564 if (IS_ERR(fdb)) {
565 rule = ERR_CAST(fdb);
566 goto err_esw_get;
567 }
568
84be2fda 569 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 570 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 571 &flow_act, dest, i);
84be2fda 572 else
10caabda 573 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 574 if (IS_ERR(rule))
e52c2802 575 goto err_add_rule;
375f51e2 576 else
525e84be 577 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 578
e52c2802
PB		 579 return rule;
580
581err_add_rule:
96e32687 582 if (split)
0a9e2307 583 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 584 else if (attr->chain || attr->prio)
ae430332 585 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 586err_esw_get:
9e51c0a6 587 esw_cleanup_dests(esw, attr);
e52c2802 588err_create_goto_table:
aa0cbbae 589 return rule;
3d80d1a2
OG		 590}
591
e4ad91f2
CM		 592struct mlx5_flow_handle *
593mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
594 struct mlx5_flow_spec *spec,
c620b772 595 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 596{
597 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 598 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 599 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 600 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 601 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 602 struct mlx5_flow_table *fast_fdb;
603 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 604 struct mlx5_flow_handle *rule;
10742efc 605 int i, err = 0;
e4ad91f2 606
ae430332 607 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 608 if (IS_ERR(fast_fdb)) {
609 rule = ERR_CAST(fast_fdb);
610 goto err_get_fast;
611 }
612
c620b772
AL		 613 fwd_attr.chain = attr->chain;
614 fwd_attr.prio = attr->prio;
615 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 616 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 617 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 618 if (IS_ERR(fwd_fdb)) {
619 rule = ERR_CAST(fwd_fdb);
620 goto err_get_fwd;
621 }
622
e4ad91f2 623 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 624 for (i = 0; i < esw_attr->split_count; i++) {
a508728a
VB		 625 if (esw_is_indir_table(esw, attr))
626 err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i);
627 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
10742efc
VB		 628 err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr,
629 &i);
630 else
631 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
632
633 if (err) {
634 rule = ERR_PTR(err);
635 goto err_chain_src_rewrite;
636 }
637 }
e4ad91f2 638 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 639 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 640 i++;
641
a508728a 642 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 643 esw_attr->in_mdev->priv.eswitch,
644 esw_attr->in_rep->vport);
e4ad91f2 645
93b3586e 646 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 647 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 648
278d51f2 649 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 650 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 651
10742efc
VB		 652 if (IS_ERR(rule)) {
653 i = esw_attr->split_count;
654 goto err_chain_src_rewrite;
655 }
e4ad91f2 656
525e84be 657 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 658
659 return rule;
10742efc
VB		 660err_chain_src_rewrite:
661 esw_put_dest_tables_loop(esw, attr, 0, i);
0a9e2307 662 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 663err_get_fwd:
ae430332 664 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 665err_get_fast:
e4ad91f2
CM		 666 return rule;
667}
668
e52c2802
PB		 669static void
670__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
671 struct mlx5_flow_handle *rule,
c620b772 672 struct mlx5_flow_attr *attr,
e52c2802
PB		 673 bool fwd_rule)
674{
c620b772 675 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 676 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 677 bool split = (esw_attr->split_count > 0);
678 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 679 int i;
e52c2802
PB		 680
681 mlx5_del_flow_rules(rule);
10caabda 682
84be2fda 683 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 684 /* unref the term table */
685 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 686 if (esw_attr->dests[i].termtbl)
687 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 688 }
10caabda
OS		 689 }
690
525e84be 691 atomic64_dec(&esw->offloads.num_flows);
e52c2802 692
c620b772
AL		 693 if (fwd_rule || split) {
694 fwd_attr.chain = attr->chain;
695 fwd_attr.prio = attr->prio;
696 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 697 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 698 }
699
e52c2802 700 if (fwd_rule) {
0a9e2307 701 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 702 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
10742efc 703 esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count);
e52c2802 704 } else {
96e32687 705 if (split)
0a9e2307 706 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 707 else if (attr->chain || attr->prio)
ae430332 708 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 709 esw_cleanup_dests(esw, attr);
e52c2802
PB		 710 }
711}
712
d85cdccb
OG		 713void
714mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
715 struct mlx5_flow_handle *rule,
c620b772 716 struct mlx5_flow_attr *attr)
d85cdccb 717{
e52c2802 718 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 719}
720
48265006
OG		 721void
722mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
723 struct mlx5_flow_handle *rule,
c620b772 724 struct mlx5_flow_attr *attr)
48265006 725{
e52c2802 726 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 727}
728
f5f82476
OG		 729static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
730{
731 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 732 unsigned long i;
733 int err = 0;
f5f82476
OG		 734
735 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
47dd7e60 736 mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 737 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 738 continue;
739
740 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
741 if (err)
742 goto out;
743 }
744
745out:
746 return err;
747}
748
749static struct mlx5_eswitch_rep *
750esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
751{
752 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
753
754 in_rep = attr->in_rep;
df65a573 755 out_rep = attr->dests[0].rep;
f5f82476
OG		 756
757 if (push)
758 vport = in_rep;
759 else if (pop)
760 vport = out_rep;
761 else
762 vport = in_rep;
763
764 return vport;
765}
766
767static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
768 bool push, bool pop, bool fwd)
769{
770 struct mlx5_eswitch_rep *in_rep, *out_rep;
771
772 if ((push || pop) && !fwd)
773 goto out_notsupp;
774
775 in_rep = attr->in_rep;
df65a573 776 out_rep = attr->dests[0].rep;
f5f82476 777
b05af6aa 778 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 779 goto out_notsupp;
780
b05af6aa 781 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 782 goto out_notsupp;
783
784 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
785 if (!push && !pop && fwd)
b05af6aa 786 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 787 goto out_notsupp;
788
789 /* protects against (1) setting rules with different vlans to push and
790 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
791 */
1482bd3d 792 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 793 goto out_notsupp;
794
795 return 0;
796
797out_notsupp:
9eb78923 798 return -EOPNOTSUPP;
f5f82476
OG		 799}
800
801int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 802 struct mlx5_flow_attr *attr)
f5f82476
OG		 803{
804 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 805 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 806 struct mlx5_eswitch_rep *vport = NULL;
807 bool push, pop, fwd;
808 int err = 0;
809
6acfbf38 810 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 811 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 812 return 0;
813
f5f82476
OG		 814 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
815 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 816 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
817 !attr->dest_chain);
f5f82476 818
0e18134f
VB		 819 mutex_lock(&esw->state_lock);
820
c620b772 821 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 822 if (err)
0e18134f 823 goto unlock;
f5f82476 824
39ac237c 825 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 826
c620b772 827 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 828
829 if (!push && !pop && fwd) {
830 /* tracks VF --> wire rules without vlan push action */
c620b772 831 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 832 vport->vlan_refcount++;
39ac237c 833 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 834 }
835
0e18134f 836 goto unlock;
f5f82476
OG		 837 }
838
839 if (!push && !pop)
0e18134f 840 goto unlock;
f5f82476
OG		 841
842 if (!(offloads->vlan_push_pop_refcount)) {
843 /* it's the 1st vlan rule, apply global vlan pop policy */
844 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
845 if (err)
846 goto out;
847 }
848 offloads->vlan_push_pop_refcount++;
849
850 if (push) {
851 if (vport->vlan_refcount)
852 goto skip_set_push;
853
c620b772
AL		 854 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
855 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 856 if (err)
857 goto out;
c620b772 858 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 859skip_set_push:
860 vport->vlan_refcount++;
861 }
862out:
863 if (!err)
39ac237c 864 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 865unlock:
866 mutex_unlock(&esw->state_lock);
f5f82476
OG		 867 return err;
868}
869
870int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 871 struct mlx5_flow_attr *attr)
f5f82476
OG		 872{
873 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 874 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 875 struct mlx5_eswitch_rep *vport = NULL;
876 bool push, pop, fwd;
877 int err = 0;
878
6acfbf38 879 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 880 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 881 return 0;
882
39ac237c 883 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 884 return 0;
885
886 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
887 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
888 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
889
0e18134f
VB		 890 mutex_lock(&esw->state_lock);
891
c620b772 892 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 893
894 if (!push && !pop && fwd) {
895 /* tracks VF --> wire rules without vlan push action */
c620b772 896 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 897 vport->vlan_refcount--;
898
0e18134f 899 goto out;
f5f82476
OG		 900 }
901
902 if (push) {
903 vport->vlan_refcount--;
904 if (vport->vlan_refcount)
905 goto skip_unset_push;
906
907 vport->vlan = 0;
908 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
909 0, 0, SET_VLAN_STRIP);
910 if (err)
911 goto out;
912 }
913
914skip_unset_push:
915 offloads->vlan_push_pop_refcount--;
916 if (offloads->vlan_push_pop_refcount)
0e18134f 917 goto out;
f5f82476
OG		 918
919 /* no more vlan rules, stop global vlan pop policy */
920 err = esw_set_global_vlan_pop(esw, 0);
921
922out:
0e18134f 923 mutex_unlock(&esw->state_lock);
f5f82476
OG		 924 return err;
925}
926
f7a68945 927struct mlx5_flow_handle *
3a46f4fb
MB		 928mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
929 struct mlx5_eswitch_rep *rep,
02f3afd9 930 u32 sqn)
ab22be9b 931{
66958ed9 932 struct mlx5_flow_act flow_act = {0};
4c5009c5 933 struct mlx5_flow_destination dest = {};
74491de9 934 struct mlx5_flow_handle *flow_rule;
c5bb1730 935 struct mlx5_flow_spec *spec;
ab22be9b
OG		 936 void *misc;
937
1b9a07ee 938 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 939 if (!spec) {
ab22be9b
OG		 940 flow_rule = ERR_PTR(-ENOMEM);
941 goto out;
942 }
943
c5bb1730 944 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 945 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a 946 /* source vport is the esw manager */
3a46f4fb
MB		 947 MLX5_SET(fte_match_set_misc, misc, source_port, rep->esw->manager_vport);
948 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a 949 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
3a46f4fb 950 MLX5_CAP_GEN(rep->esw->dev, vhca_id));
ab22be9b 951
c5bb1730 952 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 953 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
954 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3a46f4fb 955 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a
MB		 956 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
957 source_eswitch_owner_vhca_id);
ab22be9b 958
c5bb1730 959 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 960 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 961 dest.vport.num = rep->vport;
962 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
963 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 964 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 965
3a46f4fb 966 flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb,
39ac237c 967 spec, &flow_act, &dest, 1);
ab22be9b 968 if (IS_ERR(flow_rule))
3a46f4fb
MB		 969 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
970 PTR_ERR(flow_rule));
ab22be9b 971out:
c5bb1730 972 kvfree(spec);
ab22be9b
OG		 973 return flow_rule;
974}
57cbd893 975EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 976
159fe639
MB		 977void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
978{
979 mlx5_del_flow_rules(rule);
980}
981
8e404fef
VB		 982static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
983{
984 struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules;
47dd7e60 985 int i = 0, num_vfs = esw->esw_funcs.num_vfs;
8e404fef
VB		 986
987 if (!num_vfs || !flows)
988 return;
989
47dd7e60
PP		 990 for (i = 0; i < num_vfs; i++)
991 mlx5_del_flow_rules(flows[i]);
8e404fef
VB		 992
993 kvfree(flows);
994}
995
996static int
997mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
998{
8e404fef
VB		 999 struct mlx5_flow_destination dest = {};
1000 struct mlx5_flow_act flow_act = {0};
6308a5f0 1001 int num_vfs, rule_idx = 0, err = 0;
8e404fef
VB		 1002 struct mlx5_flow_handle *flow_rule;
1003 struct mlx5_flow_handle **flows;
1004 struct mlx5_flow_spec *spec;
47dd7e60
PP		 1005 struct mlx5_vport *vport;
1006 unsigned long i;
6308a5f0 1007 u16 vport_num;
8e404fef
VB		 1008
1009 num_vfs = esw->esw_funcs.num_vfs;
1010 flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL);
1011 if (!flows)
1012 return -ENOMEM;
1013
1014 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1015 if (!spec) {
1016 err = -ENOMEM;
1017 goto alloc_err;
1018 }
1019
1020 MLX5_SET(fte_match_param, spec->match_criteria,
1021 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1022 MLX5_SET(fte_match_param, spec->match_criteria,
1023 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1024 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1025 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1026
1027 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1028 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1029 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1030
47dd7e60
PP		 1031 mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) {
1032 vport_num = vport->vport;
8e404fef
VB		 1033 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1034 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1035 dest.vport.num = vport_num;
1036
1037 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1038 spec, &flow_act, &dest, 1);
1039 if (IS_ERR(flow_rule)) {
1040 err = PTR_ERR(flow_rule);
1041 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n",
1042 rule_idx, PTR_ERR(flow_rule));
1043 goto rule_err;
1044 }
1045 flows[rule_idx++] = flow_rule;
1046 }
1047
1048 esw->fdb_table.offloads.send_to_vport_meta_rules = flows;
1049 kvfree(spec);
1050 return 0;
1051
1052rule_err:
1053 while (--rule_idx >= 0)
1054 mlx5_del_flow_rules(flows[rule_idx]);
1055 kvfree(spec);
1056alloc_err:
1057 kvfree(flows);
1058 return err;
1059}
1060
5b7cb745
PB		 1061static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1062{
1063 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1064 MLX5_FDB_TO_VPORT_REG_C_1;
1065}
1066
332bd3a5 1067static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 1068{
1069 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 1070 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1071 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 1072 u8 curr, wanted;
c1286050
JL		 1073 int err;
1074
5b7cb745
PB		 1075 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1076 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 1077 return 0;
c1286050 1078
e08a6832
LR		 1079 MLX5_SET(query_esw_vport_context_in, in, opcode,
1080 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1081 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 1082 if (err)
1083 return err;
1084
5b7cb745
PB		 1085 curr = MLX5_GET(query_esw_vport_context_out, out,
1086 esw_vport_context.fdb_to_vport_reg_c_id);
1087 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1088 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1089 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 1090
332bd3a5 1091 if (enable)
5b7cb745 1092 curr |= wanted;
332bd3a5 1093 else
5b7cb745 1094 curr &= ~wanted;
c1286050 1095
e08a6832 1096 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 1097 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 1098 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 1099 field_select.fdb_to_vport_reg_c_id, 1);
1100
e08a6832 1101 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 1102 if (!err) {
1103 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1104 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1105 else
1106 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1107 }
1108
1109 return err;
c1286050
JL		 1110}
1111
a5641cb5
JL		 1112static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1113 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1114 struct mlx5_flow_spec *spec,
1115 struct mlx5_flow_destination *dest)
1116{
a5641cb5 1117 void *misc;
ac004b83 1118
a5641cb5
JL		 1119 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1120 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1121 misc_parameters_2);
0f0d3827
PB		 1122 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1123 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1124
a5641cb5
JL		 1125 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1126 } else {
1127 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1128 misc_parameters);
ac004b83 1129
a5641cb5
JL		 1130 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1131 MLX5_CAP_GEN(peer_dev, vhca_id));
1132
1133 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1134
1135 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1136 misc_parameters);
1137 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1138 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1139 source_eswitch_owner_vhca_id);
1140 }
ac004b83
RD		 1141
1142 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1143 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1144 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1145 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1146}
1147
a5641cb5
JL		 1148static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1149 struct mlx5_eswitch *peer_esw,
1150 struct mlx5_flow_spec *spec,
1151 u16 vport)
1152{
1153 void *misc;
1154
1155 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1156 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1157 misc_parameters_2);
1158 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1159 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1160 vport));
1161 } else {
1162 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1163 misc_parameters);
1164 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1165 }
1166}
1167
ac004b83
RD		 1168static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1169 struct mlx5_core_dev *peer_dev)
1170{
1171 struct mlx5_flow_destination dest = {};
1172 struct mlx5_flow_act flow_act = {0};
1173 struct mlx5_flow_handle **flows;
ac004b83
RD		 1174 /* total vports is the same for both e-switches */
1175 int nvports = esw->total_vports;
47dd7e60
PP		 1176 struct mlx5_flow_handle *flow;
1177 struct mlx5_flow_spec *spec;
1178 struct mlx5_vport *vport;
1179 unsigned long i;
ac004b83 1180 void *misc;
47dd7e60 1181 int err;
ac004b83
RD		 1182
1183 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1184 if (!spec)
1185 return -ENOMEM;
1186
a5641cb5 1187 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 1188
1189 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
1190 if (!flows) {
1191 err = -ENOMEM;
1192 goto alloc_flows_err;
1193 }
1194
1195 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1196 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1197 misc_parameters);
1198
81cd229c 1199 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1200 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1201 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1202 spec, MLX5_VPORT_PF);
1203
81cd229c
BW		 1204 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1205 spec, &flow_act, &dest, 1);
1206 if (IS_ERR(flow)) {
1207 err = PTR_ERR(flow);
1208 goto add_pf_flow_err;
1209 }
47dd7e60 1210 flows[vport->index] = flow;
81cd229c
BW		 1211 }
1212
1213 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1214 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c
BW		 1215 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1216 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1217 spec, &flow_act, &dest, 1);
1218 if (IS_ERR(flow)) {
1219 err = PTR_ERR(flow);
1220 goto add_ecpf_flow_err;
1221 }
47dd7e60 1222 flows[vport->index] = flow;
81cd229c
BW		 1223 }
1224
47dd7e60 1225 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1226 esw_set_peer_miss_rule_source_port(esw,
1227 peer_dev->priv.eswitch,
47dd7e60 1228 spec, vport->vport);
a5641cb5 1229
ac004b83
RD		 1230 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1231 spec, &flow_act, &dest, 1);
1232 if (IS_ERR(flow)) {
1233 err = PTR_ERR(flow);
81cd229c 1234 goto add_vf_flow_err;
ac004b83 1235 }
47dd7e60 1236 flows[vport->index] = flow;
ac004b83
RD		 1237 }
1238
1239 esw->fdb_table.offloads.peer_miss_rules = flows;
1240
1241 kvfree(spec);
1242 return 0;
1243
81cd229c 1244add_vf_flow_err:
47dd7e60
PP		 1245 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1246 if (!flows[vport->index])
1247 continue;
1248 mlx5_del_flow_rules(flows[vport->index]);
1249 }
1250 if (mlx5_ecpf_vport_exists(esw->dev)) {
1251 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1252 mlx5_del_flow_rules(flows[vport->index]);
1253 }
81cd229c 1254add_ecpf_flow_err:
47dd7e60
PP		 1255 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1256 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1257 mlx5_del_flow_rules(flows[vport->index]);
1258 }
81cd229c
BW		 1259add_pf_flow_err:
1260 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1261 kvfree(flows);
1262alloc_flows_err:
1263 kvfree(spec);
1264 return err;
1265}
1266
1267static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1268{
1269 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1270 struct mlx5_vport *vport;
1271 unsigned long i;
ac004b83
RD		 1272
1273 flows = esw->fdb_table.offloads.peer_miss_rules;
1274
47dd7e60
PP		 1275 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1276 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1277
47dd7e60
PP		 1278 if (mlx5_ecpf_vport_exists(esw->dev)) {
1279 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1280 mlx5_del_flow_rules(flows[vport->index]);
1281 }
81cd229c 1282
47dd7e60
PP		 1283 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1284 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1285 mlx5_del_flow_rules(flows[vport->index]);
1286 }
ac004b83
RD		 1287 kvfree(flows);
1288}
1289
3aa33572
OG		 1290static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1291{
66958ed9 1292 struct mlx5_flow_act flow_act = {0};
4c5009c5 1293 struct mlx5_flow_destination dest = {};
74491de9 1294 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1295 struct mlx5_flow_spec *spec;
f80be543
MB		 1296 void *headers_c;
1297 void *headers_v;
3aa33572 1298 int err = 0;
f80be543
MB		 1299 u8 *dmac_c;
1300 u8 *dmac_v;
3aa33572 1301
1b9a07ee 1302 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1303 if (!spec) {
3aa33572
OG		 1304 err = -ENOMEM;
1305 goto out;
1306 }
1307
f80be543
MB		 1308 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1309 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1310 outer_headers);
1311 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1312 outer_headers.dmac_47_16);
1313 dmac_c[0] = 0x01;
1314
3aa33572 1315 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1316 dest.vport.num = esw->manager_vport;
66958ed9 1317 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1318
39ac237c
PB		 1319 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1320 spec, &flow_act, &dest, 1);
3aa33572
OG		 1321 if (IS_ERR(flow_rule)) {
1322 err = PTR_ERR(flow_rule);
f80be543 1323 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1324 goto out;
1325 }
1326
f80be543
MB		 1327 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1328
1329 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1330 outer_headers);
1331 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1332 outer_headers.dmac_47_16);
1333 dmac_v[0] = 0x01;
39ac237c
PB		 1334 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1335 spec, &flow_act, &dest, 1);
f80be543
MB		 1336 if (IS_ERR(flow_rule)) {
1337 err = PTR_ERR(flow_rule);
1338 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1339 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1340 goto out;
1341 }
1342
1343 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1344
3aa33572 1345out:
c5bb1730 1346 kvfree(spec);
3aa33572
OG		 1347 return err;
1348}
1349
11b717d6
PB		 1350struct mlx5_flow_handle *
1351esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1352{
1353 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1354 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1355 struct mlx5_flow_context *flow_context;
1356 struct mlx5_flow_handle *flow_rule;
1357 struct mlx5_flow_destination dest;
1358 struct mlx5_flow_spec *spec;
1359 void *misc;
1360
60acc105
PB		 1361 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1362 return ERR_PTR(-EOPNOTSUPP);
1363
9f4d9283 1364 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1365 if (!spec)
1366 return ERR_PTR(-ENOMEM);
1367
1368 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1369 misc_parameters_2);
1370 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1371 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1372 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1373 misc_parameters_2);
1374 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1375 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1376 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1377 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1378 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1379
1380 flow_context = &spec->flow_context;
1381 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1382 flow_context->flow_tag = tag;
1383 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1384 dest.ft = esw->offloads.ft_offloads;
1385
1386 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1387 kvfree(spec);
11b717d6
PB		 1388
1389 if (IS_ERR(flow_rule))
1390 esw_warn(esw->dev,
1391 "Failed to create restore rule for tag: %d, err(%d)\n",
1392 tag, (int)PTR_ERR(flow_rule));
1393
1394 return flow_rule;
1395}
1396
1967ce6e 1397#define MAX_PF_SQ 256
cd3d07e7 1398#define MAX_SQ_NVPORTS 32
1967ce6e 1399
a5641cb5
JL		 1400static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1401 u32 *flow_group_in)
1402{
1403 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1404 flow_group_in,
1405 match_criteria);
1406
1407 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1408 MLX5_SET(create_flow_group_in, flow_group_in,
1409 match_criteria_enable,
1410 MLX5_MATCH_MISC_PARAMETERS_2);
1411
0f0d3827
PB		 1412 MLX5_SET(fte_match_param, match_criteria,
1413 misc_parameters_2.metadata_reg_c_0,
1414 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1415 } else {
1416 MLX5_SET(create_flow_group_in, flow_group_in,
1417 match_criteria_enable,
1418 MLX5_MATCH_MISC_PARAMETERS);
1419
1420 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1421 misc_parameters.source_port);
1422 }
1423}
1424
ae430332 1425#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1426static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1427{
1428 struct mlx5_vport_tbl_attr attr;
1429 struct mlx5_vport *vport;
47dd7e60 1430 unsigned long i;
4c7f4028
CM		 1431
1432 attr.chain = 0;
1433 attr.prio = 1;
47dd7e60 1434 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1435 attr.vport = vport->vport;
c796bb7c 1436 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1437 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1438 }
1439}
1440
0a9e2307 1441static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1442{
1443 struct mlx5_vport_tbl_attr attr;
1444 struct mlx5_flow_table *fdb;
1445 struct mlx5_vport *vport;
47dd7e60 1446 unsigned long i;
4c7f4028
CM		 1447
1448 attr.chain = 0;
1449 attr.prio = 1;
47dd7e60 1450 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1451 attr.vport = vport->vport;
c796bb7c 1452 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1453 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1454 if (IS_ERR(fdb))
1455 goto out;
1456 }
1457 return 0;
1458
1459out:
0a9e2307 1460 esw_vport_tbl_put(esw);
4c7f4028
CM		 1461 return PTR_ERR(fdb);
1462}
1463
ae430332
AL		 1464#define fdb_modify_header_fwd_to_table_supported(esw) \
1465 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1466static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1467{
1468 struct mlx5_core_dev *dev = esw->dev;
1469
1470 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1471 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1472
1473 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1474 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1475 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1476 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1477 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1478 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1479 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1480 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1481 /* Disabled when ttl workaround is needed, e.g
1482 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1483 */
1484 esw_warn(dev,
1485 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1486 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1487 } else {
1488 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1489 esw_info(dev, "Supported tc chains and prios offload\n");
1490 }
1491
1492 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1493 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1494}
1495
1496static int
1497esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1498{
1499 struct mlx5_core_dev *dev = esw->dev;
1500 struct mlx5_flow_table *nf_ft, *ft;
1501 struct mlx5_chains_attr attr = {};
1502 struct mlx5_fs_chains *chains;
1503 u32 fdb_max;
1504 int err;
1505
1506 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1507
1508 esw_init_chains_offload_flags(esw, &attr.flags);
1509 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1510 attr.max_ft_sz = fdb_max;
1511 attr.max_grp_num = esw->params.large_group_num;
1512 attr.default_ft = miss_fdb;
c9355682 1513 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1514
1515 chains = mlx5_chains_create(dev, &attr);
1516 if (IS_ERR(chains)) {
1517 err = PTR_ERR(chains);
1518 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1519 return err;
1520 }
1521
1522 esw->fdb_table.offloads.esw_chains_priv = chains;
1523
1524 /* Create tc_end_ft which is the always created ft chain */
1525 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1526 1, 0);
1527 if (IS_ERR(nf_ft)) {
1528 err = PTR_ERR(nf_ft);
1529 goto nf_ft_err;
1530 }
1531
1532 /* Always open the root for fast path */
1533 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1534 if (IS_ERR(ft)) {
1535 err = PTR_ERR(ft);
1536 goto level_0_err;
1537 }
1538
1539 /* Open level 1 for split fdb rules now if prios isn't supported */
1540 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1541 err = esw_vport_tbl_get(esw);
ae430332
AL		 1542 if (err)
1543 goto level_1_err;
1544 }
1545
1546 mlx5_chains_set_end_ft(chains, nf_ft);
1547
1548 return 0;
1549
1550level_1_err:
1551 mlx5_chains_put_table(chains, 0, 1, 0);
1552level_0_err:
1553 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1554nf_ft_err:
1555 mlx5_chains_destroy(chains);
1556 esw->fdb_table.offloads.esw_chains_priv = NULL;
1557
1558 return err;
1559}
1560
1561static void
1562esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1563{
1564 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1565 esw_vport_tbl_put(esw);
ae430332
AL		 1566 mlx5_chains_put_table(chains, 0, 1, 0);
1567 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1568 mlx5_chains_destroy(chains);
1569}
1570
1571#else /* CONFIG_MLX5_CLS_ACT */
1572
1573static int
1574esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1575{ return 0; }
1576
1577static void
1578esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1579{}
1580
1581#endif
1582
0da3c12d 1583static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1584{
1585 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1586 struct mlx5_flow_table_attr ft_attr = {};
8e404fef 1587 int num_vfs, table_size, ix, err = 0;
1967ce6e
OG		 1588 struct mlx5_core_dev *dev = esw->dev;
1589 struct mlx5_flow_namespace *root_ns;
1590 struct mlx5_flow_table *fdb = NULL;
39ac237c 1591 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1592 struct mlx5_flow_group *g;
1593 void *match_criteria;
f80be543 1594 u8 *dmac;
1967ce6e
OG		 1595
1596 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1597
1b9a07ee 1598 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1599 if (!flow_group_in)
1600 return -ENOMEM;
1601
1602 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1603 if (!root_ns) {
1604 esw_warn(dev, "Failed to get FDB flow namespace\n");
1605 err = -EOPNOTSUPP;
1606 goto ns_err;
1607 }
8463daf1
MG		 1608 esw->fdb_table.offloads.ns = root_ns;
1609 err = mlx5_flow_namespace_set_mode(root_ns,
1610 esw->dev->priv.steering->mode);
1611 if (err) {
1612 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1613 goto ns_err;
1614 }
1967ce6e 1615
0da3c12d 1616 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
8e404fef 1617 MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs;
b3ba5149 1618
e52c2802
PB		 1619 /* create the slow path fdb with encap set, so further table instances
1620 * can be created at run time while VFs are probed if the FW allows that.
1621 */
1622 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1623 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1624 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1625
1626 ft_attr.flags = flags;
b3ba5149
ES		 1627 ft_attr.max_fte = table_size;
1628 ft_attr.prio = FDB_SLOW_PATH;
1629
1630 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1631 if (IS_ERR(fdb)) {
1632 err = PTR_ERR(fdb);
1633 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1634 goto slow_fdb_err;
1635 }
52fff327 1636 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1637
ec3be887
VB		 1638 /* Create empty TC-miss managed table. This allows plugging in following
1639 * priorities without directly exposing their level 0 table to
1640 * eswitch_offloads and passing it as miss_fdb to following call to
1641 * esw_chains_create().
1642 */
1643 memset(&ft_attr, 0, sizeof(ft_attr));
1644 ft_attr.prio = FDB_TC_MISS;
1645 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1646 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1647 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1648 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1649 goto tc_miss_table_err;
1650 }
1651
1652 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
39ac237c 1653 if (err) {
ae430332 1654 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1655 goto fdb_chains_err;
e52c2802
PB		 1656 }
1657
69697b6e 1658 /* create send-to-vport group */
69697b6e
OG		 1659 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1660 MLX5_MATCH_MISC_PARAMETERS);
1661
1662 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1663
1664 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1665 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
7d97822a
MB		 1666 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1667 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1668 misc_parameters.source_eswitch_owner_vhca_id);
1669 MLX5_SET(create_flow_group_in, flow_group_in,
1670 source_eswitch_owner_vhca_id_valid, 1);
1671 }
69697b6e 1672
0da3c12d 1673 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1674 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1675 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1676
1677 g = mlx5_create_flow_group(fdb, flow_group_in);
1678 if (IS_ERR(g)) {
1679 err = PTR_ERR(g);
1680 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1681 goto send_vport_err;
1682 }
1683 esw->fdb_table.offloads.send_to_vport_grp = g;
1684
e929e3da
MD		 1685 if (esw_src_port_rewrite_supported(esw)) {
1686 /* meta send to vport */
1687 memset(flow_group_in, 0, inlen);
1688 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1689 MLX5_MATCH_MISC_PARAMETERS_2);
8e404fef 1690
e929e3da 1691 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
8e404fef 1692
e929e3da
MD		 1693 MLX5_SET(fte_match_param, match_criteria,
1694 misc_parameters_2.metadata_reg_c_0,
1695 mlx5_eswitch_get_vport_metadata_mask());
1696 MLX5_SET(fte_match_param, match_criteria,
1697 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1698
1699 num_vfs = esw->esw_funcs.num_vfs;
1700 if (num_vfs) {
1701 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1702 MLX5_SET(create_flow_group_in, flow_group_in,
1703 end_flow_index, ix + num_vfs - 1);
1704 ix += num_vfs;
1705
1706 g = mlx5_create_flow_group(fdb, flow_group_in);
1707 if (IS_ERR(g)) {
1708 err = PTR_ERR(g);
1709 esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n",
1710 err);
1711 goto send_vport_meta_err;
1712 }
1713 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1714
1715 err = mlx5_eswitch_add_send_to_vport_meta_rules(esw);
1716 if (err)
1717 goto meta_rule_err;
8e404fef 1718 }
8e404fef
VB		 1719 }
1720
6cec0229
MD		 1721 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1722 /* create peer esw miss group */
1723 memset(flow_group_in, 0, inlen);
ac004b83 1724
6cec0229 1725 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1726
6cec0229
MD		 1727 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1728 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1729 flow_group_in,
1730 match_criteria);
ac004b83 1731
6cec0229
MD		 1732 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1733 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1734
6cec0229
MD		 1735 MLX5_SET(create_flow_group_in, flow_group_in,
1736 source_eswitch_owner_vhca_id_valid, 1);
1737 }
ac004b83 1738
6cec0229
MD		 1739 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1740 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1741 ix + esw->total_vports - 1);
1742 ix += esw->total_vports;
ac004b83 1743
6cec0229
MD		 1744 g = mlx5_create_flow_group(fdb, flow_group_in);
1745 if (IS_ERR(g)) {
1746 err = PTR_ERR(g);
1747 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1748 goto peer_miss_err;
1749 }
1750 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1751 }
ac004b83 1752
69697b6e
OG		 1753 /* create miss group */
1754 memset(flow_group_in, 0, inlen);
f80be543
MB		 1755 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1756 MLX5_MATCH_OUTER_HEADERS);
1757 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1758 match_criteria);
1759 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1760 outer_headers.dmac_47_16);
1761 dmac[0] = 0x01;
69697b6e
OG		 1762
1763 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1764 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1765 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1766
1767 g = mlx5_create_flow_group(fdb, flow_group_in);
1768 if (IS_ERR(g)) {
1769 err = PTR_ERR(g);
1770 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1771 goto miss_err;
1772 }
1773 esw->fdb_table.offloads.miss_grp = g;
1774
3aa33572
OG		 1775 err = esw_add_fdb_miss_rule(esw);
1776 if (err)
1777 goto miss_rule_err;
1778
c88a026e 1779 kvfree(flow_group_in);
69697b6e
OG		 1780 return 0;
1781
3aa33572
OG		 1782miss_rule_err:
1783 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1784miss_err:
6cec0229
MD		 1785 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1786 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1787peer_miss_err:
8e404fef
VB		 1788 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1789meta_rule_err:
1790 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1791 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1792send_vport_meta_err:
69697b6e
OG		 1793 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1794send_vport_err:
ae430332 1795 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1796fdb_chains_err:
ec3be887
VB		 1797 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1798tc_miss_table_err:
52fff327 1799 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1800slow_fdb_err:
8463daf1
MG		 1801 /* Holds true only as long as DMFS is the default */
1802 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1803ns_err:
1804 kvfree(flow_group_in);
1805 return err;
1806}
1807
1967ce6e 1808static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1809{
e52c2802 1810 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1811 return;
1812
1967ce6e 1813 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1814 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1815 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
8e404fef 1816 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
69697b6e 1817 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1818 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1819 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1820 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1821 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1822 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1823
ae430332
AL		 1824 esw_chains_destroy(esw, esw_chains(esw));
1825
ec3be887 1826 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
52fff327 1827 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1828 /* Holds true only as long as DMFS is the default */
1829 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1830 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1831 atomic64_set(&esw->user_count, 0);
69697b6e 1832}
c116c6ee 1833
8d6bd3c3 1834static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1835{
b3ba5149 1836 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1837 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1838 struct mlx5_flow_table *ft_offloads;
1839 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1840 int err = 0;
1841
1842 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1843 if (!ns) {
1844 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1845 return -EOPNOTSUPP;
c116c6ee
OG		 1846 }
1847
8d6bd3c3 1848 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1849 ft_attr.prio = 1;
b3ba5149
ES		 1850
1851 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1852 if (IS_ERR(ft_offloads)) {
1853 err = PTR_ERR(ft_offloads);
1854 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1855 return err;
1856 }
1857
1858 esw->offloads.ft_offloads = ft_offloads;
1859 return 0;
1860}
1861
1862static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1863{
1864 struct mlx5_esw_offload *offloads = &esw->offloads;
1865
1866 mlx5_destroy_flow_table(offloads->ft_offloads);
1867}
fed9ce22 1868
8d6bd3c3 1869static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1870{
1871 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1872 struct mlx5_flow_group *g;
fed9ce22 1873 u32 *flow_group_in;
8d6bd3c3 1874 int nvports;
fed9ce22 1875 int err = 0;
fed9ce22 1876
8d6bd3c3 1877 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1878 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1879 if (!flow_group_in)
1880 return -ENOMEM;
1881
1882 /* create vport rx group */
a5641cb5 1883 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1884
1885 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1886 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1887
1888 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1889
1890 if (IS_ERR(g)) {
1891 err = PTR_ERR(g);
1892 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1893 goto out;
1894 }
1895
1896 esw->offloads.vport_rx_group = g;
1897out:
e574978a 1898 kvfree(flow_group_in);
fed9ce22
OG		 1899 return err;
1900}
1901
1902static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1903{
1904 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1905}
1906
74491de9 1907struct mlx5_flow_handle *
02f3afd9 1908mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1909 struct mlx5_flow_destination *dest)
fed9ce22 1910{
66958ed9 1911 struct mlx5_flow_act flow_act = {0};
74491de9 1912 struct mlx5_flow_handle *flow_rule;
c5bb1730 1913 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1914 void *misc;
1915
1b9a07ee 1916 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1917 if (!spec) {
fed9ce22
OG		 1918 flow_rule = ERR_PTR(-ENOMEM);
1919 goto out;
1920 }
1921
a5641cb5
JL		 1922 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1923 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1924 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1925 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1926
a5641cb5 1927 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1928 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1929 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1930
a5641cb5
JL		 1931 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1932 } else {
1933 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1934 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1935
1936 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1937 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1938
1939 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1940 }
fed9ce22 1941
66958ed9 1942 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1943 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1944 &flow_act, dest, 1);
fed9ce22
OG		 1945 if (IS_ERR(flow_rule)) {
1946 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1947 goto out;
1948 }
1949
1950out:
c5bb1730 1951 kvfree(spec);
fed9ce22
OG		 1952 return flow_rule;
1953}
feae9087 1954
47dd7e60 1955static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 1956{
1957 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1958 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 1959 struct mlx5_vport *vport;
1960 unsigned long i;
cc617ced
PP		 1961
1962 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1963 return -EOPNOTSUPP;
1964
1965 if (esw->mode == MLX5_ESWITCH_NONE)
1966 return -EOPNOTSUPP;
1967
1968 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1969 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1970 mlx5_mode = MLX5_INLINE_MODE_NONE;
1971 goto out;
1972 case MLX5_CAP_INLINE_MODE_L2:
1973 mlx5_mode = MLX5_INLINE_MODE_L2;
1974 goto out;
1975 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1976 goto query_vports;
1977 }
1978
1979query_vports:
1980 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 1981 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
1982 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 1983 if (prev_mlx5_mode != mlx5_mode)
1984 return -EINVAL;
1985 prev_mlx5_mode = mlx5_mode;
1986 }
1987
1988out:
1989 *mode = mlx5_mode;
1990 return 0;
e08a6832 1991}
bf3347c4 1992
11b717d6
PB		 1993static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1994{
1995 struct mlx5_esw_offload *offloads = &esw->offloads;
1996
60acc105
PB		 1997 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1998 return;
1999
6724e66b 2000 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 2001 mlx5_destroy_flow_group(offloads->restore_group);
2002 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2003}
2004
2005static int esw_create_restore_table(struct mlx5_eswitch *esw)
2006{
d65dbedf 2007 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 2008 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2009 struct mlx5_flow_table_attr ft_attr = {};
2010 struct mlx5_core_dev *dev = esw->dev;
2011 struct mlx5_flow_namespace *ns;
6724e66b 2012 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 2013 void *match_criteria, *misc;
2014 struct mlx5_flow_table *ft;
2015 struct mlx5_flow_group *g;
2016 u32 *flow_group_in;
2017 int err = 0;
2018
60acc105
PB		 2019 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2020 return 0;
2021
11b717d6
PB		 2022 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2023 if (!ns) {
2024 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2025 return -EOPNOTSUPP;
2026 }
2027
2028 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2029 if (!flow_group_in) {
2030 err = -ENOMEM;
2031 goto out_free;
2032 }
2033
a91d98a0 2034 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2035 ft = mlx5_create_flow_table(ns, &ft_attr);
2036 if (IS_ERR(ft)) {
2037 err = PTR_ERR(ft);
2038 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2039 err);
2040 goto out_free;
2041 }
2042
11b717d6
PB		 2043 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2044 match_criteria);
2045 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2046 misc_parameters_2);
2047
2048 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2049 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2050 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2051 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2052 ft_attr.max_fte - 1);
2053 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2054 MLX5_MATCH_MISC_PARAMETERS_2);
2055 g = mlx5_create_flow_group(ft, flow_group_in);
2056 if (IS_ERR(g)) {
2057 err = PTR_ERR(g);
2058 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2059 err);
2060 goto err_group;
2061 }
2062
6724e66b
PB		 2063 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2064 MLX5_SET(copy_action_in, modact, src_field,
2065 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2066 MLX5_SET(copy_action_in, modact, dst_field,
2067 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2068 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2069 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2070 modact);
2071 if (IS_ERR(mod_hdr)) {
e9864539 2072 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2073 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2074 err);
6724e66b
PB		 2075 goto err_mod_hdr;
2076 }
2077
11b717d6
PB		 2078 esw->offloads.ft_offloads_restore = ft;
2079 esw->offloads.restore_group = g;
6724e66b 2080 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2081
c8508713
RD		 2082 kvfree(flow_group_in);
2083
11b717d6
PB		 2084 return 0;
2085
6724e66b
PB		 2086err_mod_hdr:
2087 mlx5_destroy_flow_group(g);
11b717d6
PB		 2088err_group:
2089 mlx5_destroy_flow_table(ft);
2090out_free:
2091 kvfree(flow_group_in);
2092
2093 return err;
cc617ced
PP		 2094}
2095
db7ff19e
EB		 2096static int esw_offloads_start(struct mlx5_eswitch *esw,
2097 struct netlink_ext_ack *extack)
c930a3ad 2098{
062f4bf4 2099 int err, err1;
c930a3ad 2100
8e0aa4bc
PP		 2101 mlx5_eswitch_disable_locked(esw, false);
2102 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2103 esw->dev->priv.sriov.num_vfs);
6c419ba8 2104 if (err) {
8c98ee77
EB		 2105 NL_SET_ERR_MSG_MOD(extack,
2106 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 2107 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2108 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2109 if (err1) {
2110 NL_SET_ERR_MSG_MOD(extack,
2111 "Failed setting eswitch back to legacy");
2112 }
6c419ba8 2113 }
bffaa916
RD		 2114 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2115 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2116 &esw->offloads.inline_mode)) {
2117 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2118 NL_SET_ERR_MSG_MOD(extack,
2119 "Inline mode is different between vports");
bffaa916
RD		 2120 }
2121 }
c930a3ad
OG		 2122 return err;
2123}
2124
47dd7e60
PP		 2125static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2126 struct mlx5_eswitch_rep *rep,
2127 xa_mark_t mark)
e8d31c4d 2128{
47dd7e60
PP		 2129 bool mark_set;
2130
2131 /* Copy the mark from vport to its rep */
2132 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2133 if (mark_set)
2134 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
e8d31c4d
MB		 2135}
2136
47dd7e60 2137static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2138{
e8d31c4d 2139 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2140 int rep_type;
2141 int err;
e8d31c4d 2142
47dd7e60
PP		 2143 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2144 if (!rep)
e8d31c4d
MB		 2145 return -ENOMEM;
2146
47dd7e60
PP		 2147 rep->vport = vport->vport;
2148 rep->vport_index = vport->index;
2149 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2150 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2151
47dd7e60
PP		 2152 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2153 if (err)
2154 goto insert_err;
2155
2156 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2157 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2158 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2159 return 0;
2160
2161insert_err:
2162 kfree(rep);
2163 return err;
2164}
2165
2166static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2167 struct mlx5_eswitch_rep *rep)
2168{
2169 xa_erase(&esw->offloads.vport_reps, rep->vport);
2170 kfree(rep);
2171}
2172
2173void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2174{
2175 struct mlx5_eswitch_rep *rep;
2176 unsigned long i;
e8d31c4d 2177
47dd7e60
PP		 2178 mlx5_esw_for_each_rep(esw, i, rep)
2179 mlx5_esw_offloads_rep_cleanup(esw, rep);
2180 xa_destroy(&esw->offloads.vport_reps);
2181}
2182
2183int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2184{
2185 struct mlx5_vport *vport;
2186 unsigned long i;
2187 int err;
2188
2189 xa_init(&esw->offloads.vport_reps);
2190
2191 mlx5_esw_for_each_vport(esw, i, vport) {
2192 err = mlx5_esw_offloads_rep_init(esw, vport);
2193 if (err)
2194 goto err;
2195 }
e8d31c4d 2196 return 0;
47dd7e60
PP		 2197
2198err:
2199 esw_offloads_cleanup_reps(esw);
2200 return err;
e8d31c4d
MB		 2201}
2202
c9b99abc
BW		 2203static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2204 struct mlx5_eswitch_rep *rep, u8 rep_type)
2205{
8693115a 2206 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2207 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2208 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2209}
2210
d7f33a45
VP		 2211static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2212{
2213 struct mlx5_eswitch_rep *rep;
47dd7e60 2214 unsigned long i;
d7f33a45
VP		 2215
2216 mlx5_esw_for_each_sf_rep(esw, i, rep)
2217 __esw_offloads_unload_rep(esw, rep, rep_type);
2218}
2219
4110fc59 2220static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2221{
2222 struct mlx5_eswitch_rep *rep;
47dd7e60 2223 unsigned long i;
4110fc59 2224
d7f33a45
VP		 2225 __unload_reps_sf_vport(esw, rep_type);
2226
47dd7e60 2227 mlx5_esw_for_each_vf_rep(esw, i, rep)
4110fc59 2228 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 2229
81cd229c
BW		 2230 if (mlx5_ecpf_vport_exists(esw->dev)) {
2231 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2232 __esw_offloads_unload_rep(esw, rep, rep_type);
2233 }
2234
2235 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2236 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2237 __esw_offloads_unload_rep(esw, rep, rep_type);
2238 }
2239
879c8f84 2240 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 2241 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2242}
2243
d970812b 2244int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2245{
c2d7712c
BW		 2246 struct mlx5_eswitch_rep *rep;
2247 int rep_type;
a4b97ab4
MB		 2248 int err;
2249
c2d7712c
BW		 2250 rep = mlx5_eswitch_get_rep(esw, vport_num);
2251 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2252 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2253 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2254 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2255 if (err)
2256 goto err_reps;
2257 }
2258
2259 return 0;
a4b97ab4
MB		 2260
2261err_reps:
c2d7712c
BW		 2262 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2263 for (--rep_type; rep_type >= 0; rep_type--)
2264 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2265 return err;
2266}
2267
d970812b 2268void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2269{
2270 struct mlx5_eswitch_rep *rep;
2271 int rep_type;
2272
c2d7712c
BW		 2273 rep = mlx5_eswitch_get_rep(esw, vport_num);
2274 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2275 __esw_offloads_unload_rep(esw, rep, rep_type);
2276}
2277
38679b5a
PP		 2278int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2279{
2280 int err;
2281
2282 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2283 return 0;
2284
865d6d1c
RD		 2285 if (vport_num != MLX5_VPORT_UPLINK) {
2286 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2287 if (err)
2288 return err;
2289 }
c7eddc60 2290
38679b5a 2291 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2292 if (err)
2293 goto load_err;
2294 return err;
2295
2296load_err:
865d6d1c
RD		 2297 if (vport_num != MLX5_VPORT_UPLINK)
2298 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2299 return err;
2300}
2301
2302void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2303{
2304 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2305 return;
2306
2307 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c
RD		 2308
2309 if (vport_num != MLX5_VPORT_UPLINK)
2310 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2311}
2312
ac004b83
RD		 2313#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2314#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2315
2316static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2317 struct mlx5_eswitch *peer_esw)
2318{
ac004b83 2319
027d7166 2320 return esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
ac004b83
RD		 2321}
2322
2323static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
2324{
d956873f 2325#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2326 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2327#endif
ac004b83
RD		 2328 esw_del_fdb_peer_miss_rules(esw);
2329}
2330
8463daf1
MG		 2331static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2332 struct mlx5_eswitch *peer_esw,
2333 bool pair)
2334{
2335 struct mlx5_flow_root_namespace *peer_ns;
2336 struct mlx5_flow_root_namespace *ns;
2337 int err;
2338
2339 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2340 ns = esw->dev->priv.steering->fdb_root_ns;
2341
2342 if (pair) {
2343 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2344 if (err)
2345 return err;
2346
e53e6655 2347 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 2348 if (err) {
2349 mlx5_flow_namespace_set_peer(ns, NULL);
2350 return err;
2351 }
2352 } else {
2353 mlx5_flow_namespace_set_peer(ns, NULL);
2354 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2355 }
2356
2357 return 0;
2358}
2359
ac004b83
RD		 2360static int mlx5_esw_offloads_devcom_event(int event,
2361 void *my_data,
2362 void *event_data)
2363{
2364 struct mlx5_eswitch *esw = my_data;
ac004b83 2365 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 2366 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 2367 int err;
2368
2369 switch (event) {
2370 case ESW_OFFLOADS_DEVCOM_PAIR:
dd3fddb8
RD		 2371 if (mlx5_get_next_phys_dev(esw->dev) != peer_esw->dev)
2372 break;
2373
a5641cb5
JL		 2374 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2375 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2376 break;
2377
8463daf1 2378 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2379 if (err)
2380 goto err_out;
8463daf1
MG		 2381 err = mlx5_esw_offloads_pair(esw, peer_esw);
2382 if (err)
2383 goto err_peer;
ac004b83
RD		 2384
2385 err = mlx5_esw_offloads_pair(peer_esw, esw);
2386 if (err)
2387 goto err_pair;
2388
2389 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2390 break;
2391
2392 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2393 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
2394 break;
2395
2396 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2397 mlx5_esw_offloads_unpair(peer_esw);
2398 mlx5_esw_offloads_unpair(esw);
8463daf1 2399 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2400 break;
2401 }
2402
2403 return 0;
2404
2405err_pair:
2406 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 2407err_peer:
2408 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2409err_out:
2410 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2411 event, err);
2412 return err;
2413}
2414
2415static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2416{
2417 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2418
04de7dda
RD		 2419 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2420 mutex_init(&esw->offloads.peer_mutex);
2421
ac004b83
RD		 2422 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2423 return;
2424
2425 mlx5_devcom_register_component(devcom,
2426 MLX5_DEVCOM_ESW_OFFLOADS,
2427 mlx5_esw_offloads_devcom_event,
2428 esw);
2429
2430 mlx5_devcom_send_event(devcom,
2431 MLX5_DEVCOM_ESW_OFFLOADS,
2432 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2433}
2434
2435static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2436{
2437 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2438
2439 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2440 return;
2441
2442 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2443 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2444
2445 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2446}
2447
7bf481d7 2448bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 2449{
2450 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2451 return false;
2452
2453 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2454 MLX5_FDB_TO_VPORT_REG_C_0))
2455 return false;
2456
2457 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2458 return false;
2459
2460 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2461 mlx5_ecpf_vport_exists(esw->dev))
2462 return false;
2463
2464 return true;
2465}
2466
133dcfc5
VP		 2467u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2468{
7cd7becd 2469 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2470 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2471 u32 pf_num;
133dcfc5
VP		 2472 int id;
2473
7cd7becd 2474 /* Only 4 bits of pf_num */
2475 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2476 if (pf_num > max_pf_num)
2477 return 0;
133dcfc5 2478
7cd7becd 2479 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2480 /* Use only non-zero vport_id (1-4095) for all PF's */
2481 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2482 if (id < 0)
2483 return 0;
2484 id = (pf_num << ESW_VPORT_BITS) | id;
2485 return id;
133dcfc5
VP		 2486}
2487
2488void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2489{
7cd7becd 2490 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2491
2492 /* Metadata contains only 12 bits of actual ida id */
2493 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2494}
2495
2496static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2497 struct mlx5_vport *vport)
2498{
133dcfc5
VP		 2499 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2500 vport->metadata = vport->default_metadata;
2501 return vport->metadata ? 0 : -ENOSPC;
2502}
2503
2504static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2505 struct mlx5_vport *vport)
2506{
406493a5 2507 if (!vport->default_metadata)
133dcfc5
VP		 2508 return;
2509
2510 WARN_ON(vport->metadata != vport->default_metadata);
2511 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2512}
2513
fc99c3d6
VP		 2514static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2515{
2516 struct mlx5_vport *vport;
47dd7e60 2517 unsigned long i;
fc99c3d6
VP		 2518
2519 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2520 return;
2521
47dd7e60 2522 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 2523 esw_offloads_vport_metadata_cleanup(esw, vport);
2524}
2525
2526static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2527{
2528 struct mlx5_vport *vport;
47dd7e60 2529 unsigned long i;
fc99c3d6 2530 int err;
fc99c3d6
VP		 2531
2532 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2533 return 0;
2534
47dd7e60 2535 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 2536 err = esw_offloads_vport_metadata_setup(esw, vport);
2537 if (err)
2538 goto metadata_err;
2539 }
2540
2541 return 0;
2542
2543metadata_err:
2544 esw_offloads_metadata_uninit(esw);
2545 return err;
2546}
2547
7bf481d7
PP		 2548int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable)
2549{
2550 int err = 0;
2551
2552 down_write(&esw->mode_lock);
2553 if (esw->mode != MLX5_ESWITCH_NONE) {
2554 err = -EBUSY;
2555 goto done;
2556 }
2557 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2558 err = -EOPNOTSUPP;
2559 goto done;
2560 }
2561 if (enable)
2562 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2563 else
2564 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2565done:
2566 up_write(&esw->mode_lock);
2567 return err;
2568}
2569
748da30b 2570int
89a0f1fb
PP		 2571esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2572 struct mlx5_vport *vport)
7445cfb1 2573{
7445cfb1
JL		 2574 int err;
2575
07bab950 2576 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2577 if (err)
fc99c3d6 2578 return err;
7445cfb1 2579
2c40db2f
PP		 2580 err = esw_acl_egress_ofld_setup(esw, vport);
2581 if (err)
2582 goto egress_err;
07bab950
VP		 2583
2584 return 0;
2585
2586egress_err:
2587 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2588 return err;
2589}
18486737 2590
748da30b 2591void
89a0f1fb
PP		 2592esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2593 struct mlx5_vport *vport)
2594{
ea651a86 2595 esw_acl_egress_ofld_cleanup(vport);
07bab950 2596 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2597}
7445cfb1 2598
748da30b 2599static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2600{
2601 struct mlx5_vport *vport;
18486737 2602
748da30b 2603 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2604 if (IS_ERR(vport))
2605 return PTR_ERR(vport);
2606
4e9a9ef7 2607 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2608}
2609
748da30b 2610static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2611{
786ef904 2612 struct mlx5_vport *vport;
7445cfb1 2613
748da30b 2614 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2615 if (IS_ERR(vport))
2616 return;
2617
748da30b 2618 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2619}
2620
062f4bf4 2621static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 2622{
34ca6535 2623 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 2624 int err;
2625
5c1d260e 2626 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2627 mutex_init(&esw->fdb_table.offloads.vports.lock);
2628 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 2629 atomic64_set(&esw->user_count, 0);
e52c2802 2630
34ca6535
VB		 2631 indir = mlx5_esw_indir_table_init();
2632 if (IS_ERR(indir)) {
2633 err = PTR_ERR(indir);
2634 goto create_indir_err;
2635 }
2636 esw->fdb_table.offloads.indir = indir;
2637
748da30b 2638 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2639 if (err)
f8d1edda 2640 goto create_acl_err;
18486737 2641
8d6bd3c3 2642 err = esw_create_offloads_table(esw);
c930a3ad 2643 if (err)
11b717d6 2644 goto create_offloads_err;
c930a3ad 2645
11b717d6 2646 err = esw_create_restore_table(esw);
c930a3ad 2647 if (err)
11b717d6
PB		 2648 goto create_restore_err;
2649
0da3c12d 2650 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2651 if (err)
2652 goto create_fdb_err;
c930a3ad 2653
8d6bd3c3 2654 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2655 if (err)
2656 goto create_fg_err;
2657
2658 return 0;
2659
2660create_fg_err:
1967ce6e 2661 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2662create_fdb_err:
11b717d6
PB		 2663 esw_destroy_restore_table(esw);
2664create_restore_err:
2665 esw_destroy_offloads_table(esw);
2666create_offloads_err:
748da30b 2667 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2668create_acl_err:
34ca6535
VB		 2669 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
2670create_indir_err:
f8d1edda 2671 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2672 return err;
2673}
2674
eca8cc38
BW		 2675static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2676{
2677 esw_destroy_vport_rx_group(esw);
eca8cc38 2678 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2679 esw_destroy_restore_table(esw);
2680 esw_destroy_offloads_table(esw);
748da30b 2681 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 2682 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 2683 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2684}
2685
7e736f9a
PP		 2686static void
2687esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2688{
5ccf2770 2689 bool host_pf_disabled;
7e736f9a 2690 u16 new_num_vfs;
a3888f33 2691
7e736f9a
PP		 2692 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2693 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2694 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2695 host_params_context.host_pf_disabled);
a3888f33 2696
7e736f9a
PP		 2697 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2698 return;
a3888f33
BW		 2699
2700 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2701 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2702 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2703 } else {
7e736f9a 2704 int err;
a3888f33 2705
23bb50cf
BW		 2706 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2707 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2708 if (err)
7e736f9a 2709 return;
a3888f33 2710 }
7e736f9a 2711 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2712}
2713
7e736f9a 2714static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2715{
7e736f9a
PP		 2716 struct mlx5_host_work *host_work;
2717 struct mlx5_eswitch *esw;
dd28087c 2718 const u32 *out;
ac35dcd6 2719
7e736f9a
PP		 2720 host_work = container_of(work, struct mlx5_host_work, work);
2721 esw = host_work->esw;
a3888f33 2722
dd28087c
PP		 2723 out = mlx5_esw_query_functions(esw->dev);
2724 if (IS_ERR(out))
7e736f9a 2725 goto out;
a3888f33 2726
7e736f9a 2727 esw_vfs_changed_event_handler(esw, out);
dd28087c 2728 kvfree(out);
a3888f33 2729out:
ac35dcd6
VP		 2730 kfree(host_work);
2731}
2732
16fff98a 2733int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2734{
cd56f929 2735 struct mlx5_esw_functions *esw_funcs;
a3888f33 2736 struct mlx5_host_work *host_work;
a3888f33
BW		 2737 struct mlx5_eswitch *esw;
2738
2739 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2740 if (!host_work)
2741 return NOTIFY_DONE;
2742
cd56f929
VP		 2743 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2744 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2745
2746 host_work->esw = esw;
2747
062f4bf4 2748 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2749 queue_work(esw->work_queue, &host_work->work);
2750
2751 return NOTIFY_OK;
2752}
2753
a53cf949
PP		 2754static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2755{
2756 const u32 *query_host_out;
2757
2758 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2759 return 0;
2760
2761 query_host_out = mlx5_esw_query_functions(esw->dev);
2762 if (IS_ERR(query_host_out))
2763 return PTR_ERR(query_host_out);
2764
2765 /* Mark non local controller with non zero controller number. */
2766 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2767 host_params_context.host_number);
2768 kvfree(query_host_out);
2769 return 0;
2770}
2771
f1b9acd3
PP		 2772bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
2773{
2774 /* Local controller is always valid */
2775 if (controller == 0)
2776 return true;
2777
2778 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2779 return false;
2780
2781 /* External host number starts with zero in device */
2782 return (controller == esw->offloads.host_number + 1);
2783}
2784
5896b972 2785int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2786{
c9355682 2787 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 2788 struct mlx5_vport *vport;
47dd7e60
PP		 2789 unsigned long i;
2790 int err;
eca8cc38 2791
9a64144d
MG		 2792 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2793 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2794 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2795 else
2796 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2797
2bb72e7e 2798 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2799 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2800
a53cf949
PP		 2801 err = mlx5_esw_host_number_init(esw);
2802 if (err)
cd1ef966 2803 goto err_metadata;
a53cf949 2804
fc99c3d6
VP		 2805 err = esw_offloads_metadata_init(esw);
2806 if (err)
2807 goto err_metadata;
2808
332bd3a5
PP		 2809 err = esw_set_passing_vport_metadata(esw, true);
2810 if (err)
2811 goto err_vport_metadata;
c1286050 2812
c9355682
CM		 2813 reg_c0_obj_pool = mapping_create(sizeof(struct mlx5_mapped_obj),
2814 ESW_REG_C0_USER_DATA_METADATA_MASK,
2815 true);
2816 if (IS_ERR(reg_c0_obj_pool)) {
2817 err = PTR_ERR(reg_c0_obj_pool);
2818 goto err_pool;
2819 }
2820 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
2821
7983a675
PB		 2822 err = esw_offloads_steering_init(esw);
2823 if (err)
2824 goto err_steering_init;
2825
3b83b6c2
DL		 2826 /* Representor will control the vport link state */
2827 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2828 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2829
c2d7712c
BW		 2830 /* Uplink vport rep must load first. */
2831 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2832 if (err)
c2d7712c 2833 goto err_uplink;
c1286050 2834
c2d7712c 2835 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2836 if (err)
c2d7712c 2837 goto err_vports;
eca8cc38
BW		 2838
2839 esw_offloads_devcom_init(esw);
a3888f33 2840
eca8cc38
BW		 2841 return 0;
2842
925a6acc 2843err_vports:
c2d7712c
BW		 2844 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2845err_uplink:
7983a675 2846 esw_offloads_steering_cleanup(esw);
79949985 2847err_steering_init:
c9355682
CM		 2848 mapping_destroy(reg_c0_obj_pool);
2849err_pool:
79949985 2850 esw_set_passing_vport_metadata(esw, false);
7983a675 2851err_vport_metadata:
fc99c3d6
VP		 2852 esw_offloads_metadata_uninit(esw);
2853err_metadata:
8463daf1 2854 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2855 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2856 return err;
2857}
2858
db7ff19e
EB		 2859static int esw_offloads_stop(struct mlx5_eswitch *esw,
2860 struct netlink_ext_ack *extack)
c930a3ad 2861{
062f4bf4 2862 int err, err1;
c930a3ad 2863
8e0aa4bc
PP		 2864 mlx5_eswitch_disable_locked(esw, false);
2865 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2866 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2867 if (err) {
8c98ee77 2868 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2869 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2870 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2871 if (err1) {
2872 NL_SET_ERR_MSG_MOD(extack,
2873 "Failed setting eswitch back to offloads");
2874 }
6c419ba8 2875 }
c930a3ad
OG		 2876
2877 return err;
2878}
2879
5896b972 2880void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2881{
ac004b83 2882 esw_offloads_devcom_cleanup(esw);
5896b972 2883 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2884 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2885 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2886 esw_offloads_steering_cleanup(esw);
c9355682 2887 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 2888 esw_offloads_metadata_uninit(esw);
8463daf1 2889 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2890 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2891 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2892}
2893
ef78618b 2894static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2895{
2896 switch (mode) {
2897 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2898 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2899 break;
2900 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2901 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2902 break;
2903 default:
2904 return -EINVAL;
2905 }
2906
2907 return 0;
2908}
2909
ef78618b
OG		 2910static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2911{
2912 switch (mlx5_mode) {
f6455de0 2913 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2914 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2915 break;
f6455de0 2916 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2917 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2918 break;
2919 default:
2920 return -EINVAL;
2921 }
2922
2923 return 0;
2924}
2925
bffaa916
RD		 2926static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2927{
2928 switch (mode) {
2929 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2930 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2931 break;
2932 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2933 *mlx5_mode = MLX5_INLINE_MODE_L2;
2934 break;
2935 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2936 *mlx5_mode = MLX5_INLINE_MODE_IP;
2937 break;
2938 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2939 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2940 break;
2941 default:
2942 return -EINVAL;
2943 }
2944
2945 return 0;
2946}
2947
2948static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2949{
2950 switch (mlx5_mode) {
2951 case MLX5_INLINE_MODE_NONE:
2952 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2953 break;
2954 case MLX5_INLINE_MODE_L2:
2955 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2956 break;
2957 case MLX5_INLINE_MODE_IP:
2958 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2959 break;
2960 case MLX5_INLINE_MODE_TCP_UDP:
2961 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2962 break;
2963 default:
2964 return -EINVAL;
2965 }
2966
2967 return 0;
2968}
2969
ae24432c
PP		 2970static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2971{
2972 /* devlink commands in NONE eswitch mode are currently supported only
2973 * on ECPF.
2974 */
2975 return (esw->mode == MLX5_ESWITCH_NONE &&
2976 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2977}
2978
db7ff19e
EB		 2979int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2980 struct netlink_ext_ack *extack)
9d1cef19 2981{
9d1cef19 2982 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2983 struct mlx5_eswitch *esw;
ea2128fd 2984 int err = 0;
9d1cef19 2985
bd939753
PP		 2986 esw = mlx5_devlink_eswitch_get(devlink);
2987 if (IS_ERR(esw))
2988 return PTR_ERR(esw);
9d1cef19 2989
ef78618b 2990 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2991 return -EINVAL;
2992
7dc84de9
RD		 2993 err = mlx5_esw_try_lock(esw);
2994 if (err < 0) {
2995 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
2996 return err;
2997 }
2998 cur_mlx5_mode = err;
2999 err = 0;
3000
c930a3ad 3001 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 3002 goto unlock;
c930a3ad
OG		 3003
3004 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 3005 err = esw_offloads_start(esw, extack);
c930a3ad 3006 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 3007 err = esw_offloads_stop(esw, extack);
c930a3ad 3008 else
8e0aa4bc
PP		 3009 err = -EINVAL;
3010
3011unlock:
7dc84de9 3012 mlx5_esw_unlock(esw);
8e0aa4bc 3013 return err;
feae9087
OG		 3014}
3015
3016int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3017{
bd939753 3018 struct mlx5_eswitch *esw;
9d1cef19 3019 int err;
c930a3ad 3020
bd939753
PP		 3021 esw = mlx5_devlink_eswitch_get(devlink);
3022 if (IS_ERR(esw))
3023 return PTR_ERR(esw);
c930a3ad 3024
c55479d0 3025 down_write(&esw->mode_lock);
bd939753 3026 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 3027 if (err)
8e0aa4bc 3028 goto unlock;
ae24432c 3029
8e0aa4bc
PP		 3030 err = esw_mode_to_devlink(esw->mode, mode);
3031unlock:
c55479d0 3032 up_write(&esw->mode_lock);
8e0aa4bc 3033 return err;
feae9087 3034}
127ea380 3035
47dd7e60
PP		 3036static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3037 struct netlink_ext_ack *extack)
3038{
3039 struct mlx5_core_dev *dev = esw->dev;
3040 struct mlx5_vport *vport;
3041 u16 err_vport_num = 0;
3042 unsigned long i;
3043 int err = 0;
3044
3045 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3046 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3047 if (err) {
3048 err_vport_num = vport->vport;
3049 NL_SET_ERR_MSG_MOD(extack,
3050 "Failed to set min inline on vport");
3051 goto revert_inline_mode;
3052 }
3053 }
3054 return 0;
3055
3056revert_inline_mode:
3057 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3058 if (vport->vport == err_vport_num)
3059 break;
3060 mlx5_modify_nic_vport_min_inline(dev,
3061 vport->vport,
3062 esw->offloads.inline_mode);
3063 }
3064 return err;
3065}
3066
db7ff19e
EB		 3067int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3068 struct netlink_ext_ack *extack)
bffaa916
RD		 3069{
3070 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3071 struct mlx5_eswitch *esw;
bffaa916 3072 u8 mlx5_mode;
47dd7e60 3073 int err;
bffaa916 3074
bd939753
PP		 3075 esw = mlx5_devlink_eswitch_get(devlink);
3076 if (IS_ERR(esw))
3077 return PTR_ERR(esw);
bffaa916 3078
c55479d0 3079 down_write(&esw->mode_lock);
ae24432c
PP		 3080 err = eswitch_devlink_esw_mode_check(esw);
3081 if (err)
8e0aa4bc 3082 goto out;
ae24432c 3083
c415f704
OG		 3084 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3085 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3086 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 3087 goto out;
c8b838d1 3088 fallthrough;
c415f704 3089 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3090 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3091 err = -EOPNOTSUPP;
3092 goto out;
c415f704
OG		 3093 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3094 break;
3095 }
bffaa916 3096
525e84be 3097 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3098 NL_SET_ERR_MSG_MOD(extack,
3099 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3100 err = -EOPNOTSUPP;
3101 goto out;
375f51e2
RD		 3102 }
3103
bffaa916
RD		 3104 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3105 if (err)
3106 goto out;
3107
47dd7e60
PP		 3108 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3109 if (err)
3110 goto out;
bffaa916
RD		 3111
3112 esw->offloads.inline_mode = mlx5_mode;
c55479d0 3113 up_write(&esw->mode_lock);
bffaa916
RD		 3114 return 0;
3115
bffaa916 3116out:
c55479d0 3117 up_write(&esw->mode_lock);
bffaa916
RD		 3118 return err;
3119}
3120
3121int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3122{
bd939753 3123 struct mlx5_eswitch *esw;
9d1cef19 3124 int err;
bffaa916 3125
bd939753
PP		 3126 esw = mlx5_devlink_eswitch_get(devlink);
3127 if (IS_ERR(esw))
3128 return PTR_ERR(esw);
bffaa916 3129
c55479d0 3130 down_write(&esw->mode_lock);
ae24432c
PP		 3131 err = eswitch_devlink_esw_mode_check(esw);
3132 if (err)
8e0aa4bc 3133 goto unlock;
ae24432c 3134
8e0aa4bc
PP		 3135 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3136unlock:
c55479d0 3137 up_write(&esw->mode_lock);
8e0aa4bc 3138 return err;
bffaa916
RD		 3139}
3140
98fdbea5
LR		 3141int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3142 enum devlink_eswitch_encap_mode encap,
db7ff19e 3143 struct netlink_ext_ack *extack)
7768d197
RD		 3144{
3145 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3146 struct mlx5_eswitch *esw;
7768d197
RD		 3147 int err;
3148
bd939753
PP		 3149 esw = mlx5_devlink_eswitch_get(devlink);
3150 if (IS_ERR(esw))
3151 return PTR_ERR(esw);
7768d197 3152
c55479d0 3153 down_write(&esw->mode_lock);
ae24432c
PP		 3154 err = eswitch_devlink_esw_mode_check(esw);
3155 if (err)
8e0aa4bc 3156 goto unlock;
ae24432c 3157
7768d197 3158 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3159 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3160 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3161 err = -EOPNOTSUPP;
3162 goto unlock;
3163 }
7768d197 3164
8e0aa4bc
PP		 3165 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3166 err = -EOPNOTSUPP;
3167 goto unlock;
3168 }
7768d197 3169
f6455de0 3170 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3171 esw->offloads.encap = encap;
8e0aa4bc 3172 goto unlock;
7768d197
RD		 3173 }
3174
3175 if (esw->offloads.encap == encap)
8e0aa4bc 3176 goto unlock;
7768d197 3177
525e84be 3178 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3179 NL_SET_ERR_MSG_MOD(extack,
3180 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3181 err = -EOPNOTSUPP;
3182 goto unlock;
7768d197
RD		 3183 }
3184
e52c2802 3185 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3186
3187 esw->offloads.encap = encap;
e52c2802 3188
0da3c12d 3189 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3190
7768d197 3191 if (err) {
8c98ee77
EB		 3192 NL_SET_ERR_MSG_MOD(extack,
3193 "Failed re-creating fast FDB table");
7768d197 3194 esw->offloads.encap = !encap;
0da3c12d 3195 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3196 }
e52c2802 3197
8e0aa4bc 3198unlock:
c55479d0 3199 up_write(&esw->mode_lock);
7768d197
RD		 3200 return err;
3201}
3202
98fdbea5
LR		 3203int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3204 enum devlink_eswitch_encap_mode *encap)
7768d197 3205{
bd939753 3206 struct mlx5_eswitch *esw;
9d1cef19 3207 int err;
7768d197 3208
bd939753
PP		 3209 esw = mlx5_devlink_eswitch_get(devlink);
3210 if (IS_ERR(esw))
3211 return PTR_ERR(esw);
3212
7768d197 3213
c55479d0 3214 down_write(&esw->mode_lock);
ae24432c
PP		 3215 err = eswitch_devlink_esw_mode_check(esw);
3216 if (err)
8e0aa4bc 3217 goto unlock;
ae24432c 3218
7768d197 3219 *encap = esw->offloads.encap;
8e0aa4bc 3220unlock:
c55479d0 3221 up_write(&esw->mode_lock);
7768d197
RD		 3222 return 0;
3223}
3224
c2d7712c
BW		 3225static bool
3226mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3227{
3228 /* Currently, only ECPF based device has representor for host PF. */
3229 if (vport_num == MLX5_VPORT_PF &&
3230 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3231 return false;
3232
3233 if (vport_num == MLX5_VPORT_ECPF &&
3234 !mlx5_ecpf_vport_exists(esw->dev))
3235 return false;
3236
3237 return true;
3238}
3239
f8e8fa02 3240void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 3241 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 3242 u8 rep_type)
127ea380 3243{
8693115a 3244 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 3245 struct mlx5_eswitch_rep *rep;
47dd7e60 3246 unsigned long i;
9deb2241 3247
8693115a 3248 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 3249 mlx5_esw_for_each_rep(esw, i, rep) {
3250 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 3251 rep->esw = esw;
c2d7712c
BW		 3252 rep_data = &rep->rep_data[rep_type];
3253 atomic_set(&rep_data->state, REP_REGISTERED);
3254 }
f8e8fa02 3255 }
127ea380 3256}
f8e8fa02 3257EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 3258
f8e8fa02 3259void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 3260{
cb67b832 3261 struct mlx5_eswitch_rep *rep;
47dd7e60 3262 unsigned long i;
cb67b832 3263
f6455de0 3264 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 3265 __unload_reps_all_vport(esw, rep_type);
127ea380 3266
47dd7e60 3267 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 3268 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 3269}
f8e8fa02 3270EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 3271
a4b97ab4 3272void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 3273{
726293f1
HHZ		 3274 struct mlx5_eswitch_rep *rep;
3275
879c8f84 3276 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 3277 return rep->rep_data[rep_type].priv;
726293f1 3278}
22215908
MB		 3279
3280void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 3281 u16 vport,
22215908
MB		 3282 u8 rep_type)
3283{
22215908
MB		 3284 struct mlx5_eswitch_rep *rep;
3285
879c8f84 3286 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 3287
8693115a
PP		 3288 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3289 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3290 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 3291 return NULL;
3292}
57cbd893 3293EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 3294
3295void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3296{
879c8f84 3297 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 3298}
57cbd893
MB		 3299EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3300
3301struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 3302 u16 vport)
57cbd893 3303{
879c8f84 3304 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 3305}
3306EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 3307
5b7cb745
PB		 3308bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3309{
3310 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3311}
3312EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3313
7445cfb1
JL		 3314bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3315{
3316 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3317}
3318EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3319
0f0d3827 3320u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 3321 u16 vport_num)
3322{
133dcfc5 3323 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 3324
133dcfc5
VP		 3325 if (WARN_ON_ONCE(IS_ERR(vport)))
3326 return 0;
0f0d3827 3327
133dcfc5 3328 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 3329}
3330EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 3331
3332int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 3333 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 3334{
3335 int err;
3336
3337 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3338 if (err)
3339 return err;
3340
f1b9acd3 3341 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 3342 if (err)
3343 goto devlink_err;
3344
3345 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3346 if (err)
3347 goto rep_err;
3348 return 0;
3349
3350rep_err:
3351 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3352devlink_err:
3353 mlx5_esw_vport_disable(esw, vport_num);
3354 return err;
3355}
3356
3357void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3358{
3359 mlx5_esw_offloads_rep_unload(esw, vport_num);
3360 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3361 mlx5_esw_vport_disable(esw, vport_num);
3362}
84ae9c1f
VB		 3363
3364static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3365{
3366 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3367 void *query_ctx;
3368 void *hca_caps;
3369 int err;
3370
3371 *vhca_id = 0;
3372 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3373 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3374 return -EPERM;
3375
3376 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3377 if (!query_ctx)
3378 return -ENOMEM;
3379
3380 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx);
3381 if (err)
3382 goto out_free;
3383
3384 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3385 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3386
3387out_free:
3388 kfree(query_ctx);
3389 return err;
3390}
3391
3392int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3393{
3394 u16 *old_entry, *vhca_map_entry, vhca_id;
3395 int err;
3396
3397 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3398 if (err) {
3399 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3400 vport_num, err);
3401 return err;
3402 }
3403
3404 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3405 if (!vhca_map_entry)
3406 return -ENOMEM;
3407
3408 *vhca_map_entry = vport_num;
3409 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3410 if (xa_is_err(old_entry)) {
3411 kfree(vhca_map_entry);
3412 return xa_err(old_entry);
3413 }
3414 kfree(old_entry);
3415 return 0;
3416}
3417
3418void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3419{
3420 u16 *vhca_map_entry, vhca_id;
3421 int err;
3422
3423 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3424 if (err)
3425 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3426 vport_num, err);
3427
3428 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3429 kfree(vhca_map_entry);
3430}
3431
3432int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3433{
3434 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3435
3436 if (!res)
3437 return -ENOENT;
3438
3439 *vport_num = *res;
3440 return 0;
3441}
10742efc
VB		 3442
3443u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3444 u16 vport_num)
3445{
3446 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3447
3448 if (WARN_ON_ONCE(IS_ERR(vport)))
3449 return 0;
3450
3451 return vport->metadata;
3452}
3453EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
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