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net/mlx5e: Check for needed capability for cvlan matching
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
69697b6e 51
47dd7e60
PP		 52#define mlx5_esw_for_each_rep(esw, i, rep) \
53 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
54
55#define mlx5_esw_for_each_sf_rep(esw, i, rep) \
56 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
57
58#define mlx5_esw_for_each_vf_rep(esw, index, rep) \
59 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
60 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
61
cd7e4186
BW		 62/* There are two match-all miss flows, one for unicast dst mac and
63 * one for multicast.
64 */
65#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 66#define UPLINK_REP_INDEX 0
67
c796bb7c
CM		 68#define MLX5_ESW_VPORT_TBL_SIZE 128
69#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
70
71static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
72 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
73 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
74 .flags = 0,
75};
76
879c8f84
BW		 77static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
78 u16 vport_num)
79{
47dd7e60 80 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 81}
82
6f7bbad1
JL		 83static void
84mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
85 struct mlx5_flow_spec *spec,
86 struct mlx5_esw_flow_attr *attr)
87{
88 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
036e19b9
HI		 89 attr && attr->in_rep)
90 spec->flow_context.flow_source =
91 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
92 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
93 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 94}
b7826076 95
f94d6389
CM		 96/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
97 * are not needed as well in the following process. So clear them all for simplicity.
98 */
99void
100mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
101{
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
103 void *misc2;
104
105 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
106 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
107
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
110
111 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
112 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
113 }
114}
115
c01cfd0f
JL		 116static void
117mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
118 struct mlx5_flow_spec *spec,
a508728a 119 struct mlx5_flow_attr *attr,
b055ecf5
MB		 120 struct mlx5_eswitch *src_esw,
121 u16 vport)
c01cfd0f
JL		 122{
123 void *misc2;
124 void *misc;
125
126 /* Use metadata matching because vport is not represented by single
127 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
128 */
129 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 130 if (mlx5_esw_indir_table_decap_vport(attr))
131 vport = mlx5_esw_indir_table_decap_vport(attr);
c01cfd0f
JL		 132 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
133 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
b055ecf5
MB		 134 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
135 vport));
c01cfd0f
JL		 136
137 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 138 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
139 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 140
141 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 142 } else {
143 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 144 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 145
146 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
147 MLX5_SET(fte_match_set_misc, misc,
148 source_eswitch_owner_vhca_id,
b055ecf5 149 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 150
151 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
152 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
153 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
154 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
155 source_eswitch_owner_vhca_id);
156
157 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
158 }
c01cfd0f
JL		 159}
160
a508728a
VB		 161static int
162esw_setup_decap_indir(struct mlx5_eswitch *esw,
163 struct mlx5_flow_attr *attr,
164 struct mlx5_flow_spec *spec)
165{
166 struct mlx5_flow_table *ft;
167
168 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
169 return -EOPNOTSUPP;
170
171 ft = mlx5_esw_indir_table_get(esw, attr, spec,
172 mlx5_esw_indir_table_decap_vport(attr), true);
173 return PTR_ERR_OR_ZERO(ft);
174}
175
9e51c0a6 176static void
a508728a
VB		 177esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
178 struct mlx5_flow_attr *attr)
179{
180 if (mlx5_esw_indir_table_decap_vport(attr))
181 mlx5_esw_indir_table_put(esw, attr,
182 mlx5_esw_indir_table_decap_vport(attr),
183 true);
184}
185
f94d6389
CM		 186static int
187esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
188 struct mlx5_flow_act *flow_act,
189 struct mlx5_esw_flow_attr *esw_attr,
190 int i)
191{
192 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
193 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
194 dest[i].sampler_id = esw_attr->sample->sampler_id;
195
196 return 0;
197}
198
a508728a 199static int
9e51c0a6
VB		 200esw_setup_ft_dest(struct mlx5_flow_destination *dest,
201 struct mlx5_flow_act *flow_act,
a508728a 202 struct mlx5_eswitch *esw,
9e51c0a6 203 struct mlx5_flow_attr *attr,
a508728a 204 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 205 int i)
206{
207 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
208 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
209 dest[i].ft = attr->dest_ft;
a508728a
VB		 210
211 if (mlx5_esw_indir_table_decap_vport(attr))
212 return esw_setup_decap_indir(esw, attr, spec);
213 return 0;
9e51c0a6
VB		 214}
215
216static void
217esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,
218 struct mlx5_flow_act *flow_act,
219 struct mlx5_fs_chains *chains,
220 int i)
221{
222 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
223 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
224 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
225}
226
227static int
228esw_setup_chain_dest(struct mlx5_flow_destination *dest,
229 struct mlx5_flow_act *flow_act,
230 struct mlx5_fs_chains *chains,
231 u32 chain, u32 prio, u32 level,
232 int i)
233{
234 struct mlx5_flow_table *ft;
235
236 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
237 ft = mlx5_chains_get_table(chains, chain, prio, level);
238 if (IS_ERR(ft))
239 return PTR_ERR(ft);
240
241 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
242 dest[i].ft = ft;
243 return 0;
244}
245
10742efc
VB		 246static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
247 int from, int to)
248{
249 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
250 struct mlx5_fs_chains *chains = esw_chains(esw);
251 int i;
252
253 for (i = from; i < to; i++)
254 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
255 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 256 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
257 esw_attr->dests[i].mdev))
258 mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport,
259 false);
10742efc
VB		 260}
261
262static bool
263esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
264{
265 int i;
266
267 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
268 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
269 return true;
270 return false;
271}
272
273static int
274esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
275 struct mlx5_flow_act *flow_act,
276 struct mlx5_eswitch *esw,
277 struct mlx5_fs_chains *chains,
278 struct mlx5_flow_attr *attr,
279 int *i)
280{
281 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
282 int j, err;
283
284 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
285 return -EOPNOTSUPP;
286
287 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
288 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
289 if (err)
290 goto err_setup_chain;
291 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
292 flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat;
293 }
294 return 0;
295
296err_setup_chain:
297 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
298 return err;
299}
300
301static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
302 struct mlx5_flow_attr *attr)
303{
304 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
305
306 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
307}
308
a508728a
VB		 309static bool
310esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
311{
312 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
313 int i;
314
315 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
316 if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
317 esw_attr->dests[i].mdev))
318 return true;
319 return false;
320}
321
322static int
323esw_setup_indir_table(struct mlx5_flow_destination *dest,
324 struct mlx5_flow_act *flow_act,
325 struct mlx5_eswitch *esw,
326 struct mlx5_flow_attr *attr,
327 struct mlx5_flow_spec *spec,
328 bool ignore_flow_lvl,
329 int *i)
330{
331 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
332 int j, err;
333
334 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
335 return -EOPNOTSUPP;
336
337 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
338 if (ignore_flow_lvl)
339 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
340 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
341
342 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec,
343 esw_attr->dests[j].rep->vport, false);
344 if (IS_ERR(dest[*i].ft)) {
345 err = PTR_ERR(dest[*i].ft);
346 goto err_indir_tbl_get;
347 }
348 }
349
350 if (mlx5_esw_indir_table_decap_vport(attr)) {
351 err = esw_setup_decap_indir(esw, attr, spec);
352 if (err)
353 goto err_indir_tbl_get;
354 }
355
356 return 0;
357
358err_indir_tbl_get:
359 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
360 return err;
361}
362
363static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
364{
365 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
366
367 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
368 esw_cleanup_decap_indir(esw, attr);
369}
370
9e51c0a6
VB		 371static void
372esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
373{
374 mlx5_chains_put_table(chains, chain, prio, level);
375}
376
377static void
378esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
379 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
380 int attr_idx, int dest_idx, bool pkt_reformat)
381{
382 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
383 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
384 dest[dest_idx].vport.vhca_id =
385 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
386 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
387 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
388 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
389 if (pkt_reformat) {
390 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
391 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
392 }
393 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
394 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
395 }
396}
397
398static int
399esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
400 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
401 int i)
402{
403 int j;
404
405 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
406 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
407 return i;
408}
409
e929e3da
MD		 410static bool
411esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
412{
413 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
414 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
415 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
416}
417
9e51c0a6
VB		 418static int
419esw_setup_dests(struct mlx5_flow_destination *dest,
420 struct mlx5_flow_act *flow_act,
421 struct mlx5_eswitch *esw,
422 struct mlx5_flow_attr *attr,
10742efc 423 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 424 int *i)
425{
426 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
427 struct mlx5_fs_chains *chains = esw_chains(esw);
428 int err = 0;
429
10742efc 430 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 431 esw_src_port_rewrite_supported(esw))
10742efc
VB		 432 attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE;
433
f94d6389
CM		 434 if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) {
435 esw_setup_sampler_dest(dest, flow_act, esw_attr, *i);
436 (*i)++;
437 } else if (attr->dest_ft) {
a508728a 438 esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);
9e51c0a6
VB		 439 (*i)++;
440 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
441 esw_setup_slow_path_dest(dest, flow_act, chains, *i);
442 (*i)++;
443 } else if (attr->dest_chain) {
444 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
445 1, 0, *i);
446 (*i)++;
a508728a
VB		 447 } else if (esw_is_indir_table(esw, attr)) {
448 err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i);
10742efc
VB		 449 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
450 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 451 } else {
452 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
453 }
454
455 return err;
456}
457
458static void
459esw_cleanup_dests(struct mlx5_eswitch *esw,
460 struct mlx5_flow_attr *attr)
461{
10742efc 462 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 463 struct mlx5_fs_chains *chains = esw_chains(esw);
464
a508728a
VB		 465 if (attr->dest_ft) {
466 esw_cleanup_decap_indir(esw, attr);
467 } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
10742efc
VB		 468 if (attr->dest_chain)
469 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 470 else if (esw_is_indir_table(esw, attr))
471 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 472 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
473 esw_cleanup_chain_src_port_rewrite(esw, attr);
474 }
9e51c0a6
VB		 475}
476
74491de9 477struct mlx5_flow_handle *
3d80d1a2
OG		 478mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
479 struct mlx5_flow_spec *spec,
c620b772 480 struct mlx5_flow_attr *attr)
3d80d1a2 481{
592d3651 482 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 483 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 484 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 485 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 486 bool split = !!(esw_attr->split_count);
487 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 488 struct mlx5_flow_handle *rule;
e52c2802 489 struct mlx5_flow_table *fdb;
9e51c0a6 490 int i = 0;
3d80d1a2 491
f6455de0 492 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 493 return ERR_PTR(-EOPNOTSUPP);
494
6acfbf38
OG		 495 flow_act.action = attr->action;
496 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 497 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 498 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
499 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
500 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 501 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
502 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
503 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 504 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 505 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
506 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
507 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 508 }
6acfbf38 509 }
776b12b6 510
10742efc
VB		 511 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
512
66958ed9 513 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 514 int err;
515
10742efc 516 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 517 if (err) {
518 rule = ERR_PTR(err);
519 goto err_create_goto_table;
56e858df 520 }
e37a79e5 521 }
14e6b038 522
c620b772
AL		 523 if (esw_attr->decap_pkt_reformat)
524 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 525
66958ed9 526 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 527 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 528 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 529 i++;
3d80d1a2
OG		 530 }
531
93b3586e 532 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 533 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 534 if (attr->inner_match_level != MLX5_MATCH_NONE)
535 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 536
aa24670e 537 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 538 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 539
f94d6389
CM		 540 /* esw_attr->sample is allocated only when there is a sample action */
541 if (esw_attr->sample && esw_attr->sample->sample_default_tbl) {
542 fdb = esw_attr->sample->sample_default_tbl;
543 } else if (split) {
c620b772
AL		 544 fwd_attr.chain = attr->chain;
545 fwd_attr.prio = attr->prio;
546 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 547 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 548
0a9e2307 549 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 550 } else {
d18296ff 551 if (attr->chain || attr->prio)
ae430332
AL		 552 fdb = mlx5_chains_get_table(chains, attr->chain,
553 attr->prio, 0);
d18296ff 554 else
c620b772 555 fdb = attr->ft;
6fb0701a
PB		 556
557 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
a508728a 558 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 559 esw_attr->in_mdev->priv.eswitch,
560 esw_attr->in_rep->vport);
96e32687 561 }
e52c2802
PB		 562 if (IS_ERR(fdb)) {
563 rule = ERR_CAST(fdb);
564 goto err_esw_get;
565 }
566
84be2fda 567 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 568 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 569 &flow_act, dest, i);
84be2fda 570 else
10caabda 571 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 572 if (IS_ERR(rule))
e52c2802 573 goto err_add_rule;
375f51e2 574 else
525e84be 575 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 576
e52c2802
PB		 577 return rule;
578
579err_add_rule:
96e32687 580 if (split)
0a9e2307 581 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 582 else if (attr->chain || attr->prio)
ae430332 583 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 584err_esw_get:
9e51c0a6 585 esw_cleanup_dests(esw, attr);
e52c2802 586err_create_goto_table:
aa0cbbae 587 return rule;
3d80d1a2
OG		 588}
589
e4ad91f2
CM		 590struct mlx5_flow_handle *
591mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
592 struct mlx5_flow_spec *spec,
c620b772 593 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 594{
595 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 596 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 597 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 598 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 599 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 600 struct mlx5_flow_table *fast_fdb;
601 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 602 struct mlx5_flow_handle *rule;
10742efc 603 int i, err = 0;
e4ad91f2 604
ae430332 605 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 606 if (IS_ERR(fast_fdb)) {
607 rule = ERR_CAST(fast_fdb);
608 goto err_get_fast;
609 }
610
c620b772
AL		 611 fwd_attr.chain = attr->chain;
612 fwd_attr.prio = attr->prio;
613 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 614 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 615 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 616 if (IS_ERR(fwd_fdb)) {
617 rule = ERR_CAST(fwd_fdb);
618 goto err_get_fwd;
619 }
620
e4ad91f2 621 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 622 for (i = 0; i < esw_attr->split_count; i++) {
a508728a
VB		 623 if (esw_is_indir_table(esw, attr))
624 err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i);
625 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
10742efc
VB		 626 err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr,
627 &i);
628 else
629 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
630
631 if (err) {
632 rule = ERR_PTR(err);
633 goto err_chain_src_rewrite;
634 }
635 }
e4ad91f2 636 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 637 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 638 i++;
639
a508728a 640 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 641 esw_attr->in_mdev->priv.eswitch,
642 esw_attr->in_rep->vport);
e4ad91f2 643
93b3586e 644 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 645 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 646
278d51f2 647 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 648 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 649
10742efc
VB		 650 if (IS_ERR(rule)) {
651 i = esw_attr->split_count;
652 goto err_chain_src_rewrite;
653 }
e4ad91f2 654
525e84be 655 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 656
657 return rule;
10742efc
VB		 658err_chain_src_rewrite:
659 esw_put_dest_tables_loop(esw, attr, 0, i);
0a9e2307 660 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 661err_get_fwd:
ae430332 662 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 663err_get_fast:
e4ad91f2
CM		 664 return rule;
665}
666
e52c2802
PB		 667static void
668__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
669 struct mlx5_flow_handle *rule,
c620b772 670 struct mlx5_flow_attr *attr,
e52c2802
PB		 671 bool fwd_rule)
672{
c620b772 673 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 674 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 675 bool split = (esw_attr->split_count > 0);
676 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 677 int i;
e52c2802
PB		 678
679 mlx5_del_flow_rules(rule);
10caabda 680
84be2fda 681 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 682 /* unref the term table */
683 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 684 if (esw_attr->dests[i].termtbl)
685 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 686 }
10caabda
OS		 687 }
688
525e84be 689 atomic64_dec(&esw->offloads.num_flows);
e52c2802 690
c620b772
AL		 691 if (fwd_rule || split) {
692 fwd_attr.chain = attr->chain;
693 fwd_attr.prio = attr->prio;
694 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 695 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 696 }
697
e52c2802 698 if (fwd_rule) {
0a9e2307 699 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 700 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
10742efc 701 esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count);
e52c2802 702 } else {
96e32687 703 if (split)
0a9e2307 704 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 705 else if (attr->chain || attr->prio)
ae430332 706 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 707 esw_cleanup_dests(esw, attr);
e52c2802
PB		 708 }
709}
710
d85cdccb
OG		 711void
712mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
713 struct mlx5_flow_handle *rule,
c620b772 714 struct mlx5_flow_attr *attr)
d85cdccb 715{
e52c2802 716 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 717}
718
48265006
OG		 719void
720mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
721 struct mlx5_flow_handle *rule,
c620b772 722 struct mlx5_flow_attr *attr)
48265006 723{
e52c2802 724 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 725}
726
f5f82476
OG		 727static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
728{
729 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 730 unsigned long i;
731 int err = 0;
f5f82476
OG		 732
733 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
47dd7e60 734 mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 735 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 736 continue;
737
738 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
739 if (err)
740 goto out;
741 }
742
743out:
744 return err;
745}
746
747static struct mlx5_eswitch_rep *
748esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
749{
750 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
751
752 in_rep = attr->in_rep;
df65a573 753 out_rep = attr->dests[0].rep;
f5f82476
OG		 754
755 if (push)
756 vport = in_rep;
757 else if (pop)
758 vport = out_rep;
759 else
760 vport = in_rep;
761
762 return vport;
763}
764
765static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
766 bool push, bool pop, bool fwd)
767{
768 struct mlx5_eswitch_rep *in_rep, *out_rep;
769
770 if ((push || pop) && !fwd)
771 goto out_notsupp;
772
773 in_rep = attr->in_rep;
df65a573 774 out_rep = attr->dests[0].rep;
f5f82476 775
b05af6aa 776 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 777 goto out_notsupp;
778
b05af6aa 779 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 780 goto out_notsupp;
781
782 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
783 if (!push && !pop && fwd)
b05af6aa 784 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 785 goto out_notsupp;
786
787 /* protects against (1) setting rules with different vlans to push and
788 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
789 */
1482bd3d 790 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 791 goto out_notsupp;
792
793 return 0;
794
795out_notsupp:
9eb78923 796 return -EOPNOTSUPP;
f5f82476
OG		 797}
798
799int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 800 struct mlx5_flow_attr *attr)
f5f82476
OG		 801{
802 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 803 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 804 struct mlx5_eswitch_rep *vport = NULL;
805 bool push, pop, fwd;
806 int err = 0;
807
6acfbf38 808 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 809 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 810 return 0;
811
f5f82476
OG		 812 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
813 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 814 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
815 !attr->dest_chain);
f5f82476 816
0e18134f
VB		 817 mutex_lock(&esw->state_lock);
818
c620b772 819 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 820 if (err)
0e18134f 821 goto unlock;
f5f82476 822
39ac237c 823 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 824
c620b772 825 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 826
827 if (!push && !pop && fwd) {
828 /* tracks VF --> wire rules without vlan push action */
c620b772 829 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 830 vport->vlan_refcount++;
39ac237c 831 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 832 }
833
0e18134f 834 goto unlock;
f5f82476
OG		 835 }
836
837 if (!push && !pop)
0e18134f 838 goto unlock;
f5f82476
OG		 839
840 if (!(offloads->vlan_push_pop_refcount)) {
841 /* it's the 1st vlan rule, apply global vlan pop policy */
842 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
843 if (err)
844 goto out;
845 }
846 offloads->vlan_push_pop_refcount++;
847
848 if (push) {
849 if (vport->vlan_refcount)
850 goto skip_set_push;
851
c620b772
AL		 852 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
853 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 854 if (err)
855 goto out;
c620b772 856 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 857skip_set_push:
858 vport->vlan_refcount++;
859 }
860out:
861 if (!err)
39ac237c 862 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 863unlock:
864 mutex_unlock(&esw->state_lock);
f5f82476
OG		 865 return err;
866}
867
868int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 869 struct mlx5_flow_attr *attr)
f5f82476
OG		 870{
871 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 872 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 873 struct mlx5_eswitch_rep *vport = NULL;
874 bool push, pop, fwd;
875 int err = 0;
876
6acfbf38 877 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 878 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 879 return 0;
880
39ac237c 881 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 882 return 0;
883
884 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
885 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
886 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
887
0e18134f
VB		 888 mutex_lock(&esw->state_lock);
889
c620b772 890 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 891
892 if (!push && !pop && fwd) {
893 /* tracks VF --> wire rules without vlan push action */
c620b772 894 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 895 vport->vlan_refcount--;
896
0e18134f 897 goto out;
f5f82476
OG		 898 }
899
900 if (push) {
901 vport->vlan_refcount--;
902 if (vport->vlan_refcount)
903 goto skip_unset_push;
904
905 vport->vlan = 0;
906 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
907 0, 0, SET_VLAN_STRIP);
908 if (err)
909 goto out;
910 }
911
912skip_unset_push:
913 offloads->vlan_push_pop_refcount--;
914 if (offloads->vlan_push_pop_refcount)
0e18134f 915 goto out;
f5f82476
OG		 916
917 /* no more vlan rules, stop global vlan pop policy */
918 err = esw_set_global_vlan_pop(esw, 0);
919
920out:
0e18134f 921 mutex_unlock(&esw->state_lock);
f5f82476
OG		 922 return err;
923}
924
f7a68945 925struct mlx5_flow_handle *
3a46f4fb
MB		 926mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
927 struct mlx5_eswitch_rep *rep,
02f3afd9 928 u32 sqn)
ab22be9b 929{
66958ed9 930 struct mlx5_flow_act flow_act = {0};
4c5009c5 931 struct mlx5_flow_destination dest = {};
74491de9 932 struct mlx5_flow_handle *flow_rule;
c5bb1730 933 struct mlx5_flow_spec *spec;
ab22be9b
OG		 934 void *misc;
935
1b9a07ee 936 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 937 if (!spec) {
ab22be9b
OG		 938 flow_rule = ERR_PTR(-ENOMEM);
939 goto out;
940 }
941
c5bb1730 942 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 943 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a 944 /* source vport is the esw manager */
3a46f4fb
MB		 945 MLX5_SET(fte_match_set_misc, misc, source_port, rep->esw->manager_vport);
946 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a 947 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
3a46f4fb 948 MLX5_CAP_GEN(rep->esw->dev, vhca_id));
ab22be9b 949
c5bb1730 950 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 951 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
952 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3a46f4fb 953 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a
MB		 954 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
955 source_eswitch_owner_vhca_id);
ab22be9b 956
c5bb1730 957 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 958 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 959 dest.vport.num = rep->vport;
960 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
961 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 962 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 963
3a46f4fb 964 flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb,
39ac237c 965 spec, &flow_act, &dest, 1);
ab22be9b 966 if (IS_ERR(flow_rule))
3a46f4fb
MB		 967 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
968 PTR_ERR(flow_rule));
ab22be9b 969out:
c5bb1730 970 kvfree(spec);
ab22be9b
OG		 971 return flow_rule;
972}
57cbd893 973EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 974
159fe639
MB		 975void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
976{
977 mlx5_del_flow_rules(rule);
978}
979
8e404fef
VB		 980static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
981{
982 struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules;
47dd7e60 983 int i = 0, num_vfs = esw->esw_funcs.num_vfs;
8e404fef
VB		 984
985 if (!num_vfs || !flows)
986 return;
987
47dd7e60
PP		 988 for (i = 0; i < num_vfs; i++)
989 mlx5_del_flow_rules(flows[i]);
8e404fef
VB		 990
991 kvfree(flows);
992}
993
994static int
995mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
996{
8e404fef
VB		 997 struct mlx5_flow_destination dest = {};
998 struct mlx5_flow_act flow_act = {0};
6308a5f0 999 int num_vfs, rule_idx = 0, err = 0;
8e404fef
VB		 1000 struct mlx5_flow_handle *flow_rule;
1001 struct mlx5_flow_handle **flows;
1002 struct mlx5_flow_spec *spec;
47dd7e60
PP		 1003 struct mlx5_vport *vport;
1004 unsigned long i;
6308a5f0 1005 u16 vport_num;
8e404fef
VB		 1006
1007 num_vfs = esw->esw_funcs.num_vfs;
1008 flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL);
1009 if (!flows)
1010 return -ENOMEM;
1011
1012 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1013 if (!spec) {
1014 err = -ENOMEM;
1015 goto alloc_err;
1016 }
1017
1018 MLX5_SET(fte_match_param, spec->match_criteria,
1019 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1020 MLX5_SET(fte_match_param, spec->match_criteria,
1021 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1022 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1023 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1024
1025 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1026 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1027 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1028
47dd7e60
PP		 1029 mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) {
1030 vport_num = vport->vport;
8e404fef
VB		 1031 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1032 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1033 dest.vport.num = vport_num;
1034
1035 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1036 spec, &flow_act, &dest, 1);
1037 if (IS_ERR(flow_rule)) {
1038 err = PTR_ERR(flow_rule);
1039 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n",
1040 rule_idx, PTR_ERR(flow_rule));
1041 goto rule_err;
1042 }
1043 flows[rule_idx++] = flow_rule;
1044 }
1045
1046 esw->fdb_table.offloads.send_to_vport_meta_rules = flows;
1047 kvfree(spec);
1048 return 0;
1049
1050rule_err:
1051 while (--rule_idx >= 0)
1052 mlx5_del_flow_rules(flows[rule_idx]);
1053 kvfree(spec);
1054alloc_err:
1055 kvfree(flows);
1056 return err;
1057}
1058
5b7cb745
PB		 1059static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1060{
1061 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1062 MLX5_FDB_TO_VPORT_REG_C_1;
1063}
1064
332bd3a5 1065static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 1066{
1067 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 1068 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1069 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 1070 u8 curr, wanted;
c1286050
JL		 1071 int err;
1072
5b7cb745
PB		 1073 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1074 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 1075 return 0;
c1286050 1076
e08a6832
LR		 1077 MLX5_SET(query_esw_vport_context_in, in, opcode,
1078 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1079 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 1080 if (err)
1081 return err;
1082
5b7cb745
PB		 1083 curr = MLX5_GET(query_esw_vport_context_out, out,
1084 esw_vport_context.fdb_to_vport_reg_c_id);
1085 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1086 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1087 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 1088
332bd3a5 1089 if (enable)
5b7cb745 1090 curr |= wanted;
332bd3a5 1091 else
5b7cb745 1092 curr &= ~wanted;
c1286050 1093
e08a6832 1094 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 1095 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 1096 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 1097 field_select.fdb_to_vport_reg_c_id, 1);
1098
e08a6832 1099 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 1100 if (!err) {
1101 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1102 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1103 else
1104 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1105 }
1106
1107 return err;
c1286050
JL		 1108}
1109
a5641cb5
JL		 1110static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1111 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1112 struct mlx5_flow_spec *spec,
1113 struct mlx5_flow_destination *dest)
1114{
a5641cb5 1115 void *misc;
ac004b83 1116
a5641cb5
JL		 1117 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1118 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1119 misc_parameters_2);
0f0d3827
PB		 1120 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1121 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1122
a5641cb5
JL		 1123 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1124 } else {
1125 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1126 misc_parameters);
ac004b83 1127
a5641cb5
JL		 1128 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1129 MLX5_CAP_GEN(peer_dev, vhca_id));
1130
1131 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1132
1133 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1134 misc_parameters);
1135 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1136 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1137 source_eswitch_owner_vhca_id);
1138 }
ac004b83
RD		 1139
1140 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1141 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1142 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1143 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1144}
1145
a5641cb5
JL		 1146static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1147 struct mlx5_eswitch *peer_esw,
1148 struct mlx5_flow_spec *spec,
1149 u16 vport)
1150{
1151 void *misc;
1152
1153 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1154 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1155 misc_parameters_2);
1156 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1157 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1158 vport));
1159 } else {
1160 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1161 misc_parameters);
1162 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1163 }
1164}
1165
ac004b83
RD		 1166static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1167 struct mlx5_core_dev *peer_dev)
1168{
1169 struct mlx5_flow_destination dest = {};
1170 struct mlx5_flow_act flow_act = {0};
1171 struct mlx5_flow_handle **flows;
ac004b83
RD		 1172 /* total vports is the same for both e-switches */
1173 int nvports = esw->total_vports;
47dd7e60
PP		 1174 struct mlx5_flow_handle *flow;
1175 struct mlx5_flow_spec *spec;
1176 struct mlx5_vport *vport;
1177 unsigned long i;
ac004b83 1178 void *misc;
47dd7e60 1179 int err;
ac004b83
RD		 1180
1181 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1182 if (!spec)
1183 return -ENOMEM;
1184
a5641cb5 1185 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 1186
1187 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
1188 if (!flows) {
1189 err = -ENOMEM;
1190 goto alloc_flows_err;
1191 }
1192
1193 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1194 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1195 misc_parameters);
1196
81cd229c 1197 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1198 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1199 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1200 spec, MLX5_VPORT_PF);
1201
81cd229c
BW		 1202 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1203 spec, &flow_act, &dest, 1);
1204 if (IS_ERR(flow)) {
1205 err = PTR_ERR(flow);
1206 goto add_pf_flow_err;
1207 }
47dd7e60 1208 flows[vport->index] = flow;
81cd229c
BW		 1209 }
1210
1211 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1212 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c
BW		 1213 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1214 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1215 spec, &flow_act, &dest, 1);
1216 if (IS_ERR(flow)) {
1217 err = PTR_ERR(flow);
1218 goto add_ecpf_flow_err;
1219 }
47dd7e60 1220 flows[vport->index] = flow;
81cd229c
BW		 1221 }
1222
47dd7e60 1223 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1224 esw_set_peer_miss_rule_source_port(esw,
1225 peer_dev->priv.eswitch,
47dd7e60 1226 spec, vport->vport);
a5641cb5 1227
ac004b83
RD		 1228 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1229 spec, &flow_act, &dest, 1);
1230 if (IS_ERR(flow)) {
1231 err = PTR_ERR(flow);
81cd229c 1232 goto add_vf_flow_err;
ac004b83 1233 }
47dd7e60 1234 flows[vport->index] = flow;
ac004b83
RD		 1235 }
1236
1237 esw->fdb_table.offloads.peer_miss_rules = flows;
1238
1239 kvfree(spec);
1240 return 0;
1241
81cd229c 1242add_vf_flow_err:
47dd7e60
PP		 1243 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1244 if (!flows[vport->index])
1245 continue;
1246 mlx5_del_flow_rules(flows[vport->index]);
1247 }
1248 if (mlx5_ecpf_vport_exists(esw->dev)) {
1249 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1250 mlx5_del_flow_rules(flows[vport->index]);
1251 }
81cd229c 1252add_ecpf_flow_err:
47dd7e60
PP		 1253 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1254 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1255 mlx5_del_flow_rules(flows[vport->index]);
1256 }
81cd229c
BW		 1257add_pf_flow_err:
1258 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1259 kvfree(flows);
1260alloc_flows_err:
1261 kvfree(spec);
1262 return err;
1263}
1264
1265static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1266{
1267 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1268 struct mlx5_vport *vport;
1269 unsigned long i;
ac004b83
RD		 1270
1271 flows = esw->fdb_table.offloads.peer_miss_rules;
1272
47dd7e60
PP		 1273 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1274 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1275
47dd7e60
PP		 1276 if (mlx5_ecpf_vport_exists(esw->dev)) {
1277 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1278 mlx5_del_flow_rules(flows[vport->index]);
1279 }
81cd229c 1280
47dd7e60
PP		 1281 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1282 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1283 mlx5_del_flow_rules(flows[vport->index]);
1284 }
ac004b83
RD		 1285 kvfree(flows);
1286}
1287
3aa33572
OG		 1288static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1289{
66958ed9 1290 struct mlx5_flow_act flow_act = {0};
4c5009c5 1291 struct mlx5_flow_destination dest = {};
74491de9 1292 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1293 struct mlx5_flow_spec *spec;
f80be543
MB		 1294 void *headers_c;
1295 void *headers_v;
3aa33572 1296 int err = 0;
f80be543
MB		 1297 u8 *dmac_c;
1298 u8 *dmac_v;
3aa33572 1299
1b9a07ee 1300 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1301 if (!spec) {
3aa33572
OG		 1302 err = -ENOMEM;
1303 goto out;
1304 }
1305
f80be543
MB		 1306 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1307 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1308 outer_headers);
1309 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1310 outer_headers.dmac_47_16);
1311 dmac_c[0] = 0x01;
1312
3aa33572 1313 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1314 dest.vport.num = esw->manager_vport;
66958ed9 1315 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1316
39ac237c
PB		 1317 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1318 spec, &flow_act, &dest, 1);
3aa33572
OG		 1319 if (IS_ERR(flow_rule)) {
1320 err = PTR_ERR(flow_rule);
f80be543 1321 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1322 goto out;
1323 }
1324
f80be543
MB		 1325 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1326
1327 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1328 outer_headers);
1329 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1330 outer_headers.dmac_47_16);
1331 dmac_v[0] = 0x01;
39ac237c
PB		 1332 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1333 spec, &flow_act, &dest, 1);
f80be543
MB		 1334 if (IS_ERR(flow_rule)) {
1335 err = PTR_ERR(flow_rule);
1336 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1337 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1338 goto out;
1339 }
1340
1341 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1342
3aa33572 1343out:
c5bb1730 1344 kvfree(spec);
3aa33572
OG		 1345 return err;
1346}
1347
11b717d6
PB		 1348struct mlx5_flow_handle *
1349esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1350{
1351 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1352 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1353 struct mlx5_flow_context *flow_context;
1354 struct mlx5_flow_handle *flow_rule;
1355 struct mlx5_flow_destination dest;
1356 struct mlx5_flow_spec *spec;
1357 void *misc;
1358
60acc105
PB		 1359 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1360 return ERR_PTR(-EOPNOTSUPP);
1361
9f4d9283 1362 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1363 if (!spec)
1364 return ERR_PTR(-ENOMEM);
1365
1366 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1367 misc_parameters_2);
1368 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1369 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1370 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1371 misc_parameters_2);
1372 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1373 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1374 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1375 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1376 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1377
1378 flow_context = &spec->flow_context;
1379 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1380 flow_context->flow_tag = tag;
1381 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1382 dest.ft = esw->offloads.ft_offloads;
1383
1384 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1385 kvfree(spec);
11b717d6
PB		 1386
1387 if (IS_ERR(flow_rule))
1388 esw_warn(esw->dev,
1389 "Failed to create restore rule for tag: %d, err(%d)\n",
1390 tag, (int)PTR_ERR(flow_rule));
1391
1392 return flow_rule;
1393}
1394
1967ce6e 1395#define MAX_PF_SQ 256
cd3d07e7 1396#define MAX_SQ_NVPORTS 32
1967ce6e 1397
a5641cb5
JL		 1398static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1399 u32 *flow_group_in)
1400{
1401 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1402 flow_group_in,
1403 match_criteria);
1404
1405 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1406 MLX5_SET(create_flow_group_in, flow_group_in,
1407 match_criteria_enable,
1408 MLX5_MATCH_MISC_PARAMETERS_2);
1409
0f0d3827
PB		 1410 MLX5_SET(fte_match_param, match_criteria,
1411 misc_parameters_2.metadata_reg_c_0,
1412 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1413 } else {
1414 MLX5_SET(create_flow_group_in, flow_group_in,
1415 match_criteria_enable,
1416 MLX5_MATCH_MISC_PARAMETERS);
1417
1418 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1419 misc_parameters.source_port);
1420 }
1421}
1422
ae430332 1423#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1424static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1425{
1426 struct mlx5_vport_tbl_attr attr;
1427 struct mlx5_vport *vport;
47dd7e60 1428 unsigned long i;
4c7f4028
CM		 1429
1430 attr.chain = 0;
1431 attr.prio = 1;
47dd7e60 1432 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1433 attr.vport = vport->vport;
c796bb7c 1434 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1435 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1436 }
1437}
1438
0a9e2307 1439static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1440{
1441 struct mlx5_vport_tbl_attr attr;
1442 struct mlx5_flow_table *fdb;
1443 struct mlx5_vport *vport;
47dd7e60 1444 unsigned long i;
4c7f4028
CM		 1445
1446 attr.chain = 0;
1447 attr.prio = 1;
47dd7e60 1448 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1449 attr.vport = vport->vport;
c796bb7c 1450 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1451 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1452 if (IS_ERR(fdb))
1453 goto out;
1454 }
1455 return 0;
1456
1457out:
0a9e2307 1458 esw_vport_tbl_put(esw);
4c7f4028
CM		 1459 return PTR_ERR(fdb);
1460}
1461
ae430332
AL		 1462#define fdb_modify_header_fwd_to_table_supported(esw) \
1463 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1464static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1465{
1466 struct mlx5_core_dev *dev = esw->dev;
1467
1468 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1469 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1470
1471 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1472 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1473 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1474 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1475 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1476 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1477 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1478 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1479 /* Disabled when ttl workaround is needed, e.g
1480 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1481 */
1482 esw_warn(dev,
1483 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1484 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1485 } else {
1486 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1487 esw_info(dev, "Supported tc chains and prios offload\n");
1488 }
1489
1490 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1491 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1492}
1493
1494static int
1495esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1496{
1497 struct mlx5_core_dev *dev = esw->dev;
1498 struct mlx5_flow_table *nf_ft, *ft;
1499 struct mlx5_chains_attr attr = {};
1500 struct mlx5_fs_chains *chains;
1501 u32 fdb_max;
1502 int err;
1503
1504 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1505
1506 esw_init_chains_offload_flags(esw, &attr.flags);
1507 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1508 attr.max_ft_sz = fdb_max;
1509 attr.max_grp_num = esw->params.large_group_num;
1510 attr.default_ft = miss_fdb;
c9355682 1511 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1512
1513 chains = mlx5_chains_create(dev, &attr);
1514 if (IS_ERR(chains)) {
1515 err = PTR_ERR(chains);
1516 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1517 return err;
1518 }
1519
1520 esw->fdb_table.offloads.esw_chains_priv = chains;
1521
1522 /* Create tc_end_ft which is the always created ft chain */
1523 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1524 1, 0);
1525 if (IS_ERR(nf_ft)) {
1526 err = PTR_ERR(nf_ft);
1527 goto nf_ft_err;
1528 }
1529
1530 /* Always open the root for fast path */
1531 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1532 if (IS_ERR(ft)) {
1533 err = PTR_ERR(ft);
1534 goto level_0_err;
1535 }
1536
1537 /* Open level 1 for split fdb rules now if prios isn't supported */
1538 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1539 err = esw_vport_tbl_get(esw);
ae430332
AL		 1540 if (err)
1541 goto level_1_err;
1542 }
1543
1544 mlx5_chains_set_end_ft(chains, nf_ft);
1545
1546 return 0;
1547
1548level_1_err:
1549 mlx5_chains_put_table(chains, 0, 1, 0);
1550level_0_err:
1551 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1552nf_ft_err:
1553 mlx5_chains_destroy(chains);
1554 esw->fdb_table.offloads.esw_chains_priv = NULL;
1555
1556 return err;
1557}
1558
1559static void
1560esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1561{
1562 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1563 esw_vport_tbl_put(esw);
ae430332
AL		 1564 mlx5_chains_put_table(chains, 0, 1, 0);
1565 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1566 mlx5_chains_destroy(chains);
1567}
1568
1569#else /* CONFIG_MLX5_CLS_ACT */
1570
1571static int
1572esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1573{ return 0; }
1574
1575static void
1576esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1577{}
1578
1579#endif
1580
0da3c12d 1581static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1582{
1583 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1584 struct mlx5_flow_table_attr ft_attr = {};
8e404fef 1585 int num_vfs, table_size, ix, err = 0;
1967ce6e
OG		 1586 struct mlx5_core_dev *dev = esw->dev;
1587 struct mlx5_flow_namespace *root_ns;
1588 struct mlx5_flow_table *fdb = NULL;
39ac237c 1589 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1590 struct mlx5_flow_group *g;
1591 void *match_criteria;
f80be543 1592 u8 *dmac;
1967ce6e
OG		 1593
1594 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1595
1b9a07ee 1596 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1597 if (!flow_group_in)
1598 return -ENOMEM;
1599
1600 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1601 if (!root_ns) {
1602 esw_warn(dev, "Failed to get FDB flow namespace\n");
1603 err = -EOPNOTSUPP;
1604 goto ns_err;
1605 }
8463daf1
MG		 1606 esw->fdb_table.offloads.ns = root_ns;
1607 err = mlx5_flow_namespace_set_mode(root_ns,
1608 esw->dev->priv.steering->mode);
1609 if (err) {
1610 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1611 goto ns_err;
1612 }
1967ce6e 1613
0da3c12d 1614 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
8e404fef 1615 MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs;
b3ba5149 1616
e52c2802
PB		 1617 /* create the slow path fdb with encap set, so further table instances
1618 * can be created at run time while VFs are probed if the FW allows that.
1619 */
1620 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1621 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1622 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1623
1624 ft_attr.flags = flags;
b3ba5149
ES		 1625 ft_attr.max_fte = table_size;
1626 ft_attr.prio = FDB_SLOW_PATH;
1627
1628 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1629 if (IS_ERR(fdb)) {
1630 err = PTR_ERR(fdb);
1631 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1632 goto slow_fdb_err;
1633 }
52fff327 1634 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1635
ae430332 1636 err = esw_chains_create(esw, fdb);
39ac237c 1637 if (err) {
ae430332 1638 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1639 goto fdb_chains_err;
e52c2802
PB		 1640 }
1641
69697b6e 1642 /* create send-to-vport group */
69697b6e
OG		 1643 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1644 MLX5_MATCH_MISC_PARAMETERS);
1645
1646 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1647
1648 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1649 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
7d97822a
MB		 1650 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1651 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1652 misc_parameters.source_eswitch_owner_vhca_id);
1653 MLX5_SET(create_flow_group_in, flow_group_in,
1654 source_eswitch_owner_vhca_id_valid, 1);
1655 }
69697b6e 1656
0da3c12d 1657 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1658 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1659 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1660
1661 g = mlx5_create_flow_group(fdb, flow_group_in);
1662 if (IS_ERR(g)) {
1663 err = PTR_ERR(g);
1664 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1665 goto send_vport_err;
1666 }
1667 esw->fdb_table.offloads.send_to_vport_grp = g;
1668
e929e3da
MD		 1669 if (esw_src_port_rewrite_supported(esw)) {
1670 /* meta send to vport */
1671 memset(flow_group_in, 0, inlen);
1672 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1673 MLX5_MATCH_MISC_PARAMETERS_2);
8e404fef 1674
e929e3da 1675 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
8e404fef 1676
e929e3da
MD		 1677 MLX5_SET(fte_match_param, match_criteria,
1678 misc_parameters_2.metadata_reg_c_0,
1679 mlx5_eswitch_get_vport_metadata_mask());
1680 MLX5_SET(fte_match_param, match_criteria,
1681 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1682
1683 num_vfs = esw->esw_funcs.num_vfs;
1684 if (num_vfs) {
1685 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1686 MLX5_SET(create_flow_group_in, flow_group_in,
1687 end_flow_index, ix + num_vfs - 1);
1688 ix += num_vfs;
1689
1690 g = mlx5_create_flow_group(fdb, flow_group_in);
1691 if (IS_ERR(g)) {
1692 err = PTR_ERR(g);
1693 esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n",
1694 err);
1695 goto send_vport_meta_err;
1696 }
1697 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1698
1699 err = mlx5_eswitch_add_send_to_vport_meta_rules(esw);
1700 if (err)
1701 goto meta_rule_err;
8e404fef 1702 }
8e404fef
VB		 1703 }
1704
6cec0229
MD		 1705 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1706 /* create peer esw miss group */
1707 memset(flow_group_in, 0, inlen);
ac004b83 1708
6cec0229 1709 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1710
6cec0229
MD		 1711 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1712 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1713 flow_group_in,
1714 match_criteria);
ac004b83 1715
6cec0229
MD		 1716 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1717 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1718
6cec0229
MD		 1719 MLX5_SET(create_flow_group_in, flow_group_in,
1720 source_eswitch_owner_vhca_id_valid, 1);
1721 }
ac004b83 1722
6cec0229
MD		 1723 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1724 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1725 ix + esw->total_vports - 1);
1726 ix += esw->total_vports;
ac004b83 1727
6cec0229
MD		 1728 g = mlx5_create_flow_group(fdb, flow_group_in);
1729 if (IS_ERR(g)) {
1730 err = PTR_ERR(g);
1731 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1732 goto peer_miss_err;
1733 }
1734 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1735 }
ac004b83 1736
69697b6e
OG		 1737 /* create miss group */
1738 memset(flow_group_in, 0, inlen);
f80be543
MB		 1739 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1740 MLX5_MATCH_OUTER_HEADERS);
1741 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1742 match_criteria);
1743 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1744 outer_headers.dmac_47_16);
1745 dmac[0] = 0x01;
69697b6e
OG		 1746
1747 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1748 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1749 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1750
1751 g = mlx5_create_flow_group(fdb, flow_group_in);
1752 if (IS_ERR(g)) {
1753 err = PTR_ERR(g);
1754 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1755 goto miss_err;
1756 }
1757 esw->fdb_table.offloads.miss_grp = g;
1758
3aa33572
OG		 1759 err = esw_add_fdb_miss_rule(esw);
1760 if (err)
1761 goto miss_rule_err;
1762
c88a026e 1763 kvfree(flow_group_in);
69697b6e
OG		 1764 return 0;
1765
3aa33572
OG		 1766miss_rule_err:
1767 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1768miss_err:
6cec0229
MD		 1769 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1770 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1771peer_miss_err:
8e404fef
VB		 1772 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1773meta_rule_err:
1774 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1775 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1776send_vport_meta_err:
69697b6e
OG		 1777 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1778send_vport_err:
ae430332 1779 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1780fdb_chains_err:
52fff327 1781 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1782slow_fdb_err:
8463daf1
MG		 1783 /* Holds true only as long as DMFS is the default */
1784 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1785ns_err:
1786 kvfree(flow_group_in);
1787 return err;
1788}
1789
1967ce6e 1790static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1791{
e52c2802 1792 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1793 return;
1794
1967ce6e 1795 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1796 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1797 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
8e404fef 1798 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
69697b6e 1799 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1800 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1801 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1802 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1803 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1804 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1805
ae430332
AL		 1806 esw_chains_destroy(esw, esw_chains(esw));
1807
52fff327 1808 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1809 /* Holds true only as long as DMFS is the default */
1810 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1811 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1812 atomic64_set(&esw->user_count, 0);
69697b6e 1813}
c116c6ee 1814
8d6bd3c3 1815static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1816{
b3ba5149 1817 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1818 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1819 struct mlx5_flow_table *ft_offloads;
1820 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1821 int err = 0;
1822
1823 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1824 if (!ns) {
1825 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1826 return -EOPNOTSUPP;
c116c6ee
OG		 1827 }
1828
8d6bd3c3 1829 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1830 ft_attr.prio = 1;
b3ba5149
ES		 1831
1832 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1833 if (IS_ERR(ft_offloads)) {
1834 err = PTR_ERR(ft_offloads);
1835 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1836 return err;
1837 }
1838
1839 esw->offloads.ft_offloads = ft_offloads;
1840 return 0;
1841}
1842
1843static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1844{
1845 struct mlx5_esw_offload *offloads = &esw->offloads;
1846
1847 mlx5_destroy_flow_table(offloads->ft_offloads);
1848}
fed9ce22 1849
8d6bd3c3 1850static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1851{
1852 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1853 struct mlx5_flow_group *g;
fed9ce22 1854 u32 *flow_group_in;
8d6bd3c3 1855 int nvports;
fed9ce22 1856 int err = 0;
fed9ce22 1857
8d6bd3c3 1858 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1859 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1860 if (!flow_group_in)
1861 return -ENOMEM;
1862
1863 /* create vport rx group */
a5641cb5 1864 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1865
1866 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1867 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1868
1869 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1870
1871 if (IS_ERR(g)) {
1872 err = PTR_ERR(g);
1873 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1874 goto out;
1875 }
1876
1877 esw->offloads.vport_rx_group = g;
1878out:
e574978a 1879 kvfree(flow_group_in);
fed9ce22
OG		 1880 return err;
1881}
1882
1883static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1884{
1885 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1886}
1887
74491de9 1888struct mlx5_flow_handle *
02f3afd9 1889mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1890 struct mlx5_flow_destination *dest)
fed9ce22 1891{
66958ed9 1892 struct mlx5_flow_act flow_act = {0};
74491de9 1893 struct mlx5_flow_handle *flow_rule;
c5bb1730 1894 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1895 void *misc;
1896
1b9a07ee 1897 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1898 if (!spec) {
fed9ce22
OG		 1899 flow_rule = ERR_PTR(-ENOMEM);
1900 goto out;
1901 }
1902
a5641cb5
JL		 1903 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1904 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1905 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1906 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1907
a5641cb5 1908 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1909 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1910 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1911
a5641cb5
JL		 1912 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1913 } else {
1914 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1915 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1916
1917 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1918 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1919
1920 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1921 }
fed9ce22 1922
66958ed9 1923 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1924 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1925 &flow_act, dest, 1);
fed9ce22
OG		 1926 if (IS_ERR(flow_rule)) {
1927 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1928 goto out;
1929 }
1930
1931out:
c5bb1730 1932 kvfree(spec);
fed9ce22
OG		 1933 return flow_rule;
1934}
feae9087 1935
47dd7e60 1936static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 1937{
1938 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1939 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 1940 struct mlx5_vport *vport;
1941 unsigned long i;
cc617ced
PP		 1942
1943 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1944 return -EOPNOTSUPP;
1945
1946 if (esw->mode == MLX5_ESWITCH_NONE)
1947 return -EOPNOTSUPP;
1948
1949 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1950 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1951 mlx5_mode = MLX5_INLINE_MODE_NONE;
1952 goto out;
1953 case MLX5_CAP_INLINE_MODE_L2:
1954 mlx5_mode = MLX5_INLINE_MODE_L2;
1955 goto out;
1956 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1957 goto query_vports;
1958 }
1959
1960query_vports:
1961 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 1962 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
1963 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 1964 if (prev_mlx5_mode != mlx5_mode)
1965 return -EINVAL;
1966 prev_mlx5_mode = mlx5_mode;
1967 }
1968
1969out:
1970 *mode = mlx5_mode;
1971 return 0;
e08a6832 1972}
bf3347c4 1973
11b717d6
PB		 1974static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1975{
1976 struct mlx5_esw_offload *offloads = &esw->offloads;
1977
60acc105
PB		 1978 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1979 return;
1980
6724e66b 1981 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 1982 mlx5_destroy_flow_group(offloads->restore_group);
1983 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
1984}
1985
1986static int esw_create_restore_table(struct mlx5_eswitch *esw)
1987{
d65dbedf 1988 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 1989 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1990 struct mlx5_flow_table_attr ft_attr = {};
1991 struct mlx5_core_dev *dev = esw->dev;
1992 struct mlx5_flow_namespace *ns;
6724e66b 1993 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 1994 void *match_criteria, *misc;
1995 struct mlx5_flow_table *ft;
1996 struct mlx5_flow_group *g;
1997 u32 *flow_group_in;
1998 int err = 0;
1999
60acc105
PB		 2000 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2001 return 0;
2002
11b717d6
PB		 2003 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2004 if (!ns) {
2005 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2006 return -EOPNOTSUPP;
2007 }
2008
2009 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2010 if (!flow_group_in) {
2011 err = -ENOMEM;
2012 goto out_free;
2013 }
2014
a91d98a0 2015 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2016 ft = mlx5_create_flow_table(ns, &ft_attr);
2017 if (IS_ERR(ft)) {
2018 err = PTR_ERR(ft);
2019 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2020 err);
2021 goto out_free;
2022 }
2023
11b717d6
PB		 2024 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2025 match_criteria);
2026 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2027 misc_parameters_2);
2028
2029 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2030 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2031 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2032 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2033 ft_attr.max_fte - 1);
2034 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2035 MLX5_MATCH_MISC_PARAMETERS_2);
2036 g = mlx5_create_flow_group(ft, flow_group_in);
2037 if (IS_ERR(g)) {
2038 err = PTR_ERR(g);
2039 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2040 err);
2041 goto err_group;
2042 }
2043
6724e66b
PB		 2044 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2045 MLX5_SET(copy_action_in, modact, src_field,
2046 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2047 MLX5_SET(copy_action_in, modact, dst_field,
2048 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2049 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2050 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2051 modact);
2052 if (IS_ERR(mod_hdr)) {
e9864539 2053 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2054 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2055 err);
6724e66b
PB		 2056 goto err_mod_hdr;
2057 }
2058
11b717d6
PB		 2059 esw->offloads.ft_offloads_restore = ft;
2060 esw->offloads.restore_group = g;
6724e66b 2061 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2062
c8508713
RD		 2063 kvfree(flow_group_in);
2064
11b717d6
PB		 2065 return 0;
2066
6724e66b
PB		 2067err_mod_hdr:
2068 mlx5_destroy_flow_group(g);
11b717d6
PB		 2069err_group:
2070 mlx5_destroy_flow_table(ft);
2071out_free:
2072 kvfree(flow_group_in);
2073
2074 return err;
cc617ced
PP		 2075}
2076
db7ff19e
EB		 2077static int esw_offloads_start(struct mlx5_eswitch *esw,
2078 struct netlink_ext_ack *extack)
c930a3ad 2079{
062f4bf4 2080 int err, err1;
c930a3ad 2081
8e0aa4bc
PP		 2082 mlx5_eswitch_disable_locked(esw, false);
2083 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2084 esw->dev->priv.sriov.num_vfs);
6c419ba8 2085 if (err) {
8c98ee77
EB		 2086 NL_SET_ERR_MSG_MOD(extack,
2087 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 2088 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2089 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2090 if (err1) {
2091 NL_SET_ERR_MSG_MOD(extack,
2092 "Failed setting eswitch back to legacy");
2093 }
6c419ba8 2094 }
bffaa916
RD		 2095 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2096 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2097 &esw->offloads.inline_mode)) {
2098 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2099 NL_SET_ERR_MSG_MOD(extack,
2100 "Inline mode is different between vports");
bffaa916
RD		 2101 }
2102 }
c930a3ad
OG		 2103 return err;
2104}
2105
47dd7e60
PP		 2106static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2107 struct mlx5_eswitch_rep *rep,
2108 xa_mark_t mark)
e8d31c4d 2109{
47dd7e60
PP		 2110 bool mark_set;
2111
2112 /* Copy the mark from vport to its rep */
2113 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2114 if (mark_set)
2115 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
e8d31c4d
MB		 2116}
2117
47dd7e60 2118static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2119{
e8d31c4d 2120 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2121 int rep_type;
2122 int err;
e8d31c4d 2123
47dd7e60
PP		 2124 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2125 if (!rep)
e8d31c4d
MB		 2126 return -ENOMEM;
2127
47dd7e60
PP		 2128 rep->vport = vport->vport;
2129 rep->vport_index = vport->index;
2130 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2131 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2132
47dd7e60
PP		 2133 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2134 if (err)
2135 goto insert_err;
2136
2137 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2138 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2139 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2140 return 0;
2141
2142insert_err:
2143 kfree(rep);
2144 return err;
2145}
2146
2147static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2148 struct mlx5_eswitch_rep *rep)
2149{
2150 xa_erase(&esw->offloads.vport_reps, rep->vport);
2151 kfree(rep);
2152}
2153
2154void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2155{
2156 struct mlx5_eswitch_rep *rep;
2157 unsigned long i;
e8d31c4d 2158
47dd7e60
PP		 2159 mlx5_esw_for_each_rep(esw, i, rep)
2160 mlx5_esw_offloads_rep_cleanup(esw, rep);
2161 xa_destroy(&esw->offloads.vport_reps);
2162}
2163
2164int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2165{
2166 struct mlx5_vport *vport;
2167 unsigned long i;
2168 int err;
2169
2170 xa_init(&esw->offloads.vport_reps);
2171
2172 mlx5_esw_for_each_vport(esw, i, vport) {
2173 err = mlx5_esw_offloads_rep_init(esw, vport);
2174 if (err)
2175 goto err;
2176 }
e8d31c4d 2177 return 0;
47dd7e60
PP		 2178
2179err:
2180 esw_offloads_cleanup_reps(esw);
2181 return err;
e8d31c4d
MB		 2182}
2183
c9b99abc
BW		 2184static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2185 struct mlx5_eswitch_rep *rep, u8 rep_type)
2186{
8693115a 2187 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2188 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2189 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2190}
2191
d7f33a45
VP		 2192static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2193{
2194 struct mlx5_eswitch_rep *rep;
47dd7e60 2195 unsigned long i;
d7f33a45
VP		 2196
2197 mlx5_esw_for_each_sf_rep(esw, i, rep)
2198 __esw_offloads_unload_rep(esw, rep, rep_type);
2199}
2200
4110fc59 2201static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2202{
2203 struct mlx5_eswitch_rep *rep;
47dd7e60 2204 unsigned long i;
4110fc59 2205
d7f33a45
VP		 2206 __unload_reps_sf_vport(esw, rep_type);
2207
47dd7e60 2208 mlx5_esw_for_each_vf_rep(esw, i, rep)
4110fc59 2209 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 2210
81cd229c
BW		 2211 if (mlx5_ecpf_vport_exists(esw->dev)) {
2212 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2213 __esw_offloads_unload_rep(esw, rep, rep_type);
2214 }
2215
2216 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2217 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2218 __esw_offloads_unload_rep(esw, rep, rep_type);
2219 }
2220
879c8f84 2221 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 2222 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2223}
2224
d970812b 2225int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2226{
c2d7712c
BW		 2227 struct mlx5_eswitch_rep *rep;
2228 int rep_type;
a4b97ab4
MB		 2229 int err;
2230
c2d7712c
BW		 2231 rep = mlx5_eswitch_get_rep(esw, vport_num);
2232 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2233 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2234 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2235 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2236 if (err)
2237 goto err_reps;
2238 }
2239
2240 return 0;
a4b97ab4
MB		 2241
2242err_reps:
c2d7712c
BW		 2243 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2244 for (--rep_type; rep_type >= 0; rep_type--)
2245 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2246 return err;
2247}
2248
d970812b 2249void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2250{
2251 struct mlx5_eswitch_rep *rep;
2252 int rep_type;
2253
c2d7712c
BW		 2254 rep = mlx5_eswitch_get_rep(esw, vport_num);
2255 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2256 __esw_offloads_unload_rep(esw, rep, rep_type);
2257}
2258
38679b5a
PP		 2259int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2260{
2261 int err;
2262
2263 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2264 return 0;
2265
865d6d1c
RD		 2266 if (vport_num != MLX5_VPORT_UPLINK) {
2267 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2268 if (err)
2269 return err;
2270 }
c7eddc60 2271
38679b5a 2272 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2273 if (err)
2274 goto load_err;
2275 return err;
2276
2277load_err:
865d6d1c
RD		 2278 if (vport_num != MLX5_VPORT_UPLINK)
2279 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2280 return err;
2281}
2282
2283void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2284{
2285 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2286 return;
2287
2288 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c
RD		 2289
2290 if (vport_num != MLX5_VPORT_UPLINK)
2291 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2292}
2293
ac004b83
RD		 2294#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2295#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2296
2297static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2298 struct mlx5_eswitch *peer_esw)
2299{
ac004b83 2300
027d7166 2301 return esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
ac004b83
RD		 2302}
2303
2304static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
2305{
d956873f 2306#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2307 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2308#endif
ac004b83
RD		 2309 esw_del_fdb_peer_miss_rules(esw);
2310}
2311
8463daf1
MG		 2312static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2313 struct mlx5_eswitch *peer_esw,
2314 bool pair)
2315{
2316 struct mlx5_flow_root_namespace *peer_ns;
2317 struct mlx5_flow_root_namespace *ns;
2318 int err;
2319
2320 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2321 ns = esw->dev->priv.steering->fdb_root_ns;
2322
2323 if (pair) {
2324 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2325 if (err)
2326 return err;
2327
e53e6655 2328 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 2329 if (err) {
2330 mlx5_flow_namespace_set_peer(ns, NULL);
2331 return err;
2332 }
2333 } else {
2334 mlx5_flow_namespace_set_peer(ns, NULL);
2335 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2336 }
2337
2338 return 0;
2339}
2340
ac004b83
RD		 2341static int mlx5_esw_offloads_devcom_event(int event,
2342 void *my_data,
2343 void *event_data)
2344{
2345 struct mlx5_eswitch *esw = my_data;
ac004b83 2346 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 2347 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 2348 int err;
2349
2350 switch (event) {
2351 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 2352 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2353 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2354 break;
2355
8463daf1 2356 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2357 if (err)
2358 goto err_out;
8463daf1
MG		 2359 err = mlx5_esw_offloads_pair(esw, peer_esw);
2360 if (err)
2361 goto err_peer;
ac004b83
RD		 2362
2363 err = mlx5_esw_offloads_pair(peer_esw, esw);
2364 if (err)
2365 goto err_pair;
2366
2367 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2368 break;
2369
2370 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2371 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
2372 break;
2373
2374 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2375 mlx5_esw_offloads_unpair(peer_esw);
2376 mlx5_esw_offloads_unpair(esw);
8463daf1 2377 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2378 break;
2379 }
2380
2381 return 0;
2382
2383err_pair:
2384 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 2385err_peer:
2386 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2387err_out:
2388 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2389 event, err);
2390 return err;
2391}
2392
2393static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2394{
2395 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2396
04de7dda
RD		 2397 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2398 mutex_init(&esw->offloads.peer_mutex);
2399
ac004b83
RD		 2400 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2401 return;
2402
2403 mlx5_devcom_register_component(devcom,
2404 MLX5_DEVCOM_ESW_OFFLOADS,
2405 mlx5_esw_offloads_devcom_event,
2406 esw);
2407
2408 mlx5_devcom_send_event(devcom,
2409 MLX5_DEVCOM_ESW_OFFLOADS,
2410 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2411}
2412
2413static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2414{
2415 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2416
2417 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2418 return;
2419
2420 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2421 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2422
2423 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2424}
2425
7bf481d7 2426bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 2427{
2428 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2429 return false;
2430
2431 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2432 MLX5_FDB_TO_VPORT_REG_C_0))
2433 return false;
2434
2435 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2436 return false;
2437
2438 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2439 mlx5_ecpf_vport_exists(esw->dev))
2440 return false;
2441
2442 return true;
2443}
2444
133dcfc5
VP		 2445u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2446{
7cd7becd 2447 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2448 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2449 u32 pf_num;
133dcfc5
VP		 2450 int id;
2451
7cd7becd 2452 /* Only 4 bits of pf_num */
2453 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2454 if (pf_num > max_pf_num)
2455 return 0;
133dcfc5 2456
7cd7becd 2457 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2458 /* Use only non-zero vport_id (1-4095) for all PF's */
2459 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2460 if (id < 0)
2461 return 0;
2462 id = (pf_num << ESW_VPORT_BITS) | id;
2463 return id;
133dcfc5
VP		 2464}
2465
2466void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2467{
7cd7becd 2468 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2469
2470 /* Metadata contains only 12 bits of actual ida id */
2471 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2472}
2473
2474static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2475 struct mlx5_vport *vport)
2476{
133dcfc5
VP		 2477 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2478 vport->metadata = vport->default_metadata;
2479 return vport->metadata ? 0 : -ENOSPC;
2480}
2481
2482static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2483 struct mlx5_vport *vport)
2484{
406493a5 2485 if (!vport->default_metadata)
133dcfc5
VP		 2486 return;
2487
2488 WARN_ON(vport->metadata != vport->default_metadata);
2489 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2490}
2491
fc99c3d6
VP		 2492static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2493{
2494 struct mlx5_vport *vport;
47dd7e60 2495 unsigned long i;
fc99c3d6
VP		 2496
2497 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2498 return;
2499
47dd7e60 2500 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 2501 esw_offloads_vport_metadata_cleanup(esw, vport);
2502}
2503
2504static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2505{
2506 struct mlx5_vport *vport;
47dd7e60 2507 unsigned long i;
fc99c3d6 2508 int err;
fc99c3d6
VP		 2509
2510 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2511 return 0;
2512
47dd7e60 2513 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 2514 err = esw_offloads_vport_metadata_setup(esw, vport);
2515 if (err)
2516 goto metadata_err;
2517 }
2518
2519 return 0;
2520
2521metadata_err:
2522 esw_offloads_metadata_uninit(esw);
2523 return err;
2524}
2525
7bf481d7
PP		 2526int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable)
2527{
2528 int err = 0;
2529
2530 down_write(&esw->mode_lock);
2531 if (esw->mode != MLX5_ESWITCH_NONE) {
2532 err = -EBUSY;
2533 goto done;
2534 }
2535 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2536 err = -EOPNOTSUPP;
2537 goto done;
2538 }
2539 if (enable)
2540 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2541 else
2542 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2543done:
2544 up_write(&esw->mode_lock);
2545 return err;
2546}
2547
748da30b 2548int
89a0f1fb
PP		 2549esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2550 struct mlx5_vport *vport)
7445cfb1 2551{
7445cfb1
JL		 2552 int err;
2553
07bab950 2554 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2555 if (err)
fc99c3d6 2556 return err;
7445cfb1 2557
2c40db2f
PP		 2558 err = esw_acl_egress_ofld_setup(esw, vport);
2559 if (err)
2560 goto egress_err;
07bab950
VP		 2561
2562 return 0;
2563
2564egress_err:
2565 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2566 return err;
2567}
18486737 2568
748da30b 2569void
89a0f1fb
PP		 2570esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2571 struct mlx5_vport *vport)
2572{
ea651a86 2573 esw_acl_egress_ofld_cleanup(vport);
07bab950 2574 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2575}
7445cfb1 2576
748da30b 2577static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2578{
2579 struct mlx5_vport *vport;
18486737 2580
748da30b 2581 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2582 if (IS_ERR(vport))
2583 return PTR_ERR(vport);
2584
4e9a9ef7 2585 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2586}
2587
748da30b 2588static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2589{
786ef904 2590 struct mlx5_vport *vport;
7445cfb1 2591
748da30b 2592 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2593 if (IS_ERR(vport))
2594 return;
2595
748da30b 2596 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2597}
2598
062f4bf4 2599static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 2600{
34ca6535 2601 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 2602 int err;
2603
5c1d260e 2604 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2605 mutex_init(&esw->fdb_table.offloads.vports.lock);
2606 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 2607 atomic64_set(&esw->user_count, 0);
e52c2802 2608
34ca6535
VB		 2609 indir = mlx5_esw_indir_table_init();
2610 if (IS_ERR(indir)) {
2611 err = PTR_ERR(indir);
2612 goto create_indir_err;
2613 }
2614 esw->fdb_table.offloads.indir = indir;
2615
748da30b 2616 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2617 if (err)
f8d1edda 2618 goto create_acl_err;
18486737 2619
8d6bd3c3 2620 err = esw_create_offloads_table(esw);
c930a3ad 2621 if (err)
11b717d6 2622 goto create_offloads_err;
c930a3ad 2623
11b717d6 2624 err = esw_create_restore_table(esw);
c930a3ad 2625 if (err)
11b717d6
PB		 2626 goto create_restore_err;
2627
0da3c12d 2628 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2629 if (err)
2630 goto create_fdb_err;
c930a3ad 2631
8d6bd3c3 2632 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2633 if (err)
2634 goto create_fg_err;
2635
2636 return 0;
2637
2638create_fg_err:
1967ce6e 2639 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2640create_fdb_err:
11b717d6
PB		 2641 esw_destroy_restore_table(esw);
2642create_restore_err:
2643 esw_destroy_offloads_table(esw);
2644create_offloads_err:
748da30b 2645 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2646create_acl_err:
34ca6535
VB		 2647 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
2648create_indir_err:
f8d1edda 2649 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2650 return err;
2651}
2652
eca8cc38
BW		 2653static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2654{
2655 esw_destroy_vport_rx_group(esw);
eca8cc38 2656 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2657 esw_destroy_restore_table(esw);
2658 esw_destroy_offloads_table(esw);
748da30b 2659 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 2660 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 2661 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2662}
2663
7e736f9a
PP		 2664static void
2665esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2666{
5ccf2770 2667 bool host_pf_disabled;
7e736f9a 2668 u16 new_num_vfs;
a3888f33 2669
7e736f9a
PP		 2670 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2671 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2672 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2673 host_params_context.host_pf_disabled);
a3888f33 2674
7e736f9a
PP		 2675 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2676 return;
a3888f33
BW		 2677
2678 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2679 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2680 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2681 } else {
7e736f9a 2682 int err;
a3888f33 2683
23bb50cf
BW		 2684 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2685 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2686 if (err)
7e736f9a 2687 return;
a3888f33 2688 }
7e736f9a 2689 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2690}
2691
7e736f9a 2692static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2693{
7e736f9a
PP		 2694 struct mlx5_host_work *host_work;
2695 struct mlx5_eswitch *esw;
dd28087c 2696 const u32 *out;
ac35dcd6 2697
7e736f9a
PP		 2698 host_work = container_of(work, struct mlx5_host_work, work);
2699 esw = host_work->esw;
a3888f33 2700
dd28087c
PP		 2701 out = mlx5_esw_query_functions(esw->dev);
2702 if (IS_ERR(out))
7e736f9a 2703 goto out;
a3888f33 2704
7e736f9a 2705 esw_vfs_changed_event_handler(esw, out);
dd28087c 2706 kvfree(out);
a3888f33 2707out:
ac35dcd6
VP		 2708 kfree(host_work);
2709}
2710
16fff98a 2711int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2712{
cd56f929 2713 struct mlx5_esw_functions *esw_funcs;
a3888f33 2714 struct mlx5_host_work *host_work;
a3888f33
BW		 2715 struct mlx5_eswitch *esw;
2716
2717 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2718 if (!host_work)
2719 return NOTIFY_DONE;
2720
cd56f929
VP		 2721 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2722 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2723
2724 host_work->esw = esw;
2725
062f4bf4 2726 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2727 queue_work(esw->work_queue, &host_work->work);
2728
2729 return NOTIFY_OK;
2730}
2731
a53cf949
PP		 2732static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2733{
2734 const u32 *query_host_out;
2735
2736 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2737 return 0;
2738
2739 query_host_out = mlx5_esw_query_functions(esw->dev);
2740 if (IS_ERR(query_host_out))
2741 return PTR_ERR(query_host_out);
2742
2743 /* Mark non local controller with non zero controller number. */
2744 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2745 host_params_context.host_number);
2746 kvfree(query_host_out);
2747 return 0;
2748}
2749
f1b9acd3
PP		 2750bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
2751{
2752 /* Local controller is always valid */
2753 if (controller == 0)
2754 return true;
2755
2756 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2757 return false;
2758
2759 /* External host number starts with zero in device */
2760 return (controller == esw->offloads.host_number + 1);
2761}
2762
5896b972 2763int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2764{
c9355682 2765 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 2766 struct mlx5_vport *vport;
47dd7e60
PP		 2767 unsigned long i;
2768 int err;
eca8cc38 2769
9a64144d
MG		 2770 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2771 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2772 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2773 else
2774 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2775
2bb72e7e 2776 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2777 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2778
a53cf949
PP		 2779 err = mlx5_esw_host_number_init(esw);
2780 if (err)
cd1ef966 2781 goto err_metadata;
a53cf949 2782
fc99c3d6
VP		 2783 err = esw_offloads_metadata_init(esw);
2784 if (err)
2785 goto err_metadata;
2786
332bd3a5
PP		 2787 err = esw_set_passing_vport_metadata(esw, true);
2788 if (err)
2789 goto err_vport_metadata;
c1286050 2790
c9355682
CM		 2791 reg_c0_obj_pool = mapping_create(sizeof(struct mlx5_mapped_obj),
2792 ESW_REG_C0_USER_DATA_METADATA_MASK,
2793 true);
2794 if (IS_ERR(reg_c0_obj_pool)) {
2795 err = PTR_ERR(reg_c0_obj_pool);
2796 goto err_pool;
2797 }
2798 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
2799
7983a675
PB		 2800 err = esw_offloads_steering_init(esw);
2801 if (err)
2802 goto err_steering_init;
2803
3b83b6c2
DL		 2804 /* Representor will control the vport link state */
2805 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2806 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2807
c2d7712c
BW		 2808 /* Uplink vport rep must load first. */
2809 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2810 if (err)
c2d7712c 2811 goto err_uplink;
c1286050 2812
c2d7712c 2813 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2814 if (err)
c2d7712c 2815 goto err_vports;
eca8cc38
BW		 2816
2817 esw_offloads_devcom_init(esw);
a3888f33 2818
eca8cc38
BW		 2819 return 0;
2820
925a6acc 2821err_vports:
c2d7712c
BW		 2822 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2823err_uplink:
7983a675 2824 esw_offloads_steering_cleanup(esw);
79949985 2825err_steering_init:
c9355682
CM		 2826 mapping_destroy(reg_c0_obj_pool);
2827err_pool:
79949985 2828 esw_set_passing_vport_metadata(esw, false);
7983a675 2829err_vport_metadata:
fc99c3d6
VP		 2830 esw_offloads_metadata_uninit(esw);
2831err_metadata:
8463daf1 2832 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2833 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2834 return err;
2835}
2836
db7ff19e
EB		 2837static int esw_offloads_stop(struct mlx5_eswitch *esw,
2838 struct netlink_ext_ack *extack)
c930a3ad 2839{
062f4bf4 2840 int err, err1;
c930a3ad 2841
8e0aa4bc
PP		 2842 mlx5_eswitch_disable_locked(esw, false);
2843 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2844 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2845 if (err) {
8c98ee77 2846 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2847 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2848 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2849 if (err1) {
2850 NL_SET_ERR_MSG_MOD(extack,
2851 "Failed setting eswitch back to offloads");
2852 }
6c419ba8 2853 }
c930a3ad
OG		 2854
2855 return err;
2856}
2857
5896b972 2858void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2859{
ac004b83 2860 esw_offloads_devcom_cleanup(esw);
5896b972 2861 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2862 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2863 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2864 esw_offloads_steering_cleanup(esw);
c9355682 2865 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 2866 esw_offloads_metadata_uninit(esw);
8463daf1 2867 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2868 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2869 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2870}
2871
ef78618b 2872static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2873{
2874 switch (mode) {
2875 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2876 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2877 break;
2878 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2879 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2880 break;
2881 default:
2882 return -EINVAL;
2883 }
2884
2885 return 0;
2886}
2887
ef78618b
OG		 2888static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2889{
2890 switch (mlx5_mode) {
f6455de0 2891 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2892 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2893 break;
f6455de0 2894 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2895 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2896 break;
2897 default:
2898 return -EINVAL;
2899 }
2900
2901 return 0;
2902}
2903
bffaa916
RD		 2904static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2905{
2906 switch (mode) {
2907 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2908 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2909 break;
2910 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2911 *mlx5_mode = MLX5_INLINE_MODE_L2;
2912 break;
2913 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2914 *mlx5_mode = MLX5_INLINE_MODE_IP;
2915 break;
2916 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2917 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2918 break;
2919 default:
2920 return -EINVAL;
2921 }
2922
2923 return 0;
2924}
2925
2926static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2927{
2928 switch (mlx5_mode) {
2929 case MLX5_INLINE_MODE_NONE:
2930 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2931 break;
2932 case MLX5_INLINE_MODE_L2:
2933 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2934 break;
2935 case MLX5_INLINE_MODE_IP:
2936 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2937 break;
2938 case MLX5_INLINE_MODE_TCP_UDP:
2939 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2940 break;
2941 default:
2942 return -EINVAL;
2943 }
2944
2945 return 0;
2946}
2947
ae24432c
PP		 2948static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2949{
2950 /* devlink commands in NONE eswitch mode are currently supported only
2951 * on ECPF.
2952 */
2953 return (esw->mode == MLX5_ESWITCH_NONE &&
2954 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2955}
2956
db7ff19e
EB		 2957int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2958 struct netlink_ext_ack *extack)
9d1cef19 2959{
9d1cef19 2960 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2961 struct mlx5_eswitch *esw;
ea2128fd 2962 int err = 0;
9d1cef19 2963
bd939753
PP		 2964 esw = mlx5_devlink_eswitch_get(devlink);
2965 if (IS_ERR(esw))
2966 return PTR_ERR(esw);
9d1cef19 2967
ef78618b 2968 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2969 return -EINVAL;
2970
7dc84de9
RD		 2971 err = mlx5_esw_try_lock(esw);
2972 if (err < 0) {
2973 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
2974 return err;
2975 }
2976 cur_mlx5_mode = err;
2977 err = 0;
2978
c930a3ad 2979 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 2980 goto unlock;
c930a3ad
OG		 2981
2982 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 2983 err = esw_offloads_start(esw, extack);
c930a3ad 2984 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 2985 err = esw_offloads_stop(esw, extack);
c930a3ad 2986 else
8e0aa4bc
PP		 2987 err = -EINVAL;
2988
2989unlock:
7dc84de9 2990 mlx5_esw_unlock(esw);
8e0aa4bc 2991 return err;
feae9087
OG		 2992}
2993
2994int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2995{
bd939753 2996 struct mlx5_eswitch *esw;
9d1cef19 2997 int err;
c930a3ad 2998
bd939753
PP		 2999 esw = mlx5_devlink_eswitch_get(devlink);
3000 if (IS_ERR(esw))
3001 return PTR_ERR(esw);
c930a3ad 3002
c55479d0 3003 down_write(&esw->mode_lock);
bd939753 3004 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 3005 if (err)
8e0aa4bc 3006 goto unlock;
ae24432c 3007
8e0aa4bc
PP		 3008 err = esw_mode_to_devlink(esw->mode, mode);
3009unlock:
c55479d0 3010 up_write(&esw->mode_lock);
8e0aa4bc 3011 return err;
feae9087 3012}
127ea380 3013
47dd7e60
PP		 3014static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3015 struct netlink_ext_ack *extack)
3016{
3017 struct mlx5_core_dev *dev = esw->dev;
3018 struct mlx5_vport *vport;
3019 u16 err_vport_num = 0;
3020 unsigned long i;
3021 int err = 0;
3022
3023 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3024 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3025 if (err) {
3026 err_vport_num = vport->vport;
3027 NL_SET_ERR_MSG_MOD(extack,
3028 "Failed to set min inline on vport");
3029 goto revert_inline_mode;
3030 }
3031 }
3032 return 0;
3033
3034revert_inline_mode:
3035 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3036 if (vport->vport == err_vport_num)
3037 break;
3038 mlx5_modify_nic_vport_min_inline(dev,
3039 vport->vport,
3040 esw->offloads.inline_mode);
3041 }
3042 return err;
3043}
3044
db7ff19e
EB		 3045int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3046 struct netlink_ext_ack *extack)
bffaa916
RD		 3047{
3048 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3049 struct mlx5_eswitch *esw;
bffaa916 3050 u8 mlx5_mode;
47dd7e60 3051 int err;
bffaa916 3052
bd939753
PP		 3053 esw = mlx5_devlink_eswitch_get(devlink);
3054 if (IS_ERR(esw))
3055 return PTR_ERR(esw);
bffaa916 3056
c55479d0 3057 down_write(&esw->mode_lock);
ae24432c
PP		 3058 err = eswitch_devlink_esw_mode_check(esw);
3059 if (err)
8e0aa4bc 3060 goto out;
ae24432c 3061
c415f704
OG		 3062 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3063 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3064 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 3065 goto out;
c8b838d1 3066 fallthrough;
c415f704 3067 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3068 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3069 err = -EOPNOTSUPP;
3070 goto out;
c415f704
OG		 3071 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3072 break;
3073 }
bffaa916 3074
525e84be 3075 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3076 NL_SET_ERR_MSG_MOD(extack,
3077 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3078 err = -EOPNOTSUPP;
3079 goto out;
375f51e2
RD		 3080 }
3081
bffaa916
RD		 3082 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3083 if (err)
3084 goto out;
3085
47dd7e60
PP		 3086 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3087 if (err)
3088 goto out;
bffaa916
RD		 3089
3090 esw->offloads.inline_mode = mlx5_mode;
c55479d0 3091 up_write(&esw->mode_lock);
bffaa916
RD		 3092 return 0;
3093
bffaa916 3094out:
c55479d0 3095 up_write(&esw->mode_lock);
bffaa916
RD		 3096 return err;
3097}
3098
3099int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3100{
bd939753 3101 struct mlx5_eswitch *esw;
9d1cef19 3102 int err;
bffaa916 3103
bd939753
PP		 3104 esw = mlx5_devlink_eswitch_get(devlink);
3105 if (IS_ERR(esw))
3106 return PTR_ERR(esw);
bffaa916 3107
c55479d0 3108 down_write(&esw->mode_lock);
ae24432c
PP		 3109 err = eswitch_devlink_esw_mode_check(esw);
3110 if (err)
8e0aa4bc 3111 goto unlock;
ae24432c 3112
8e0aa4bc
PP		 3113 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3114unlock:
c55479d0 3115 up_write(&esw->mode_lock);
8e0aa4bc 3116 return err;
bffaa916
RD		 3117}
3118
98fdbea5
LR		 3119int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3120 enum devlink_eswitch_encap_mode encap,
db7ff19e 3121 struct netlink_ext_ack *extack)
7768d197
RD		 3122{
3123 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3124 struct mlx5_eswitch *esw;
7768d197
RD		 3125 int err;
3126
bd939753
PP		 3127 esw = mlx5_devlink_eswitch_get(devlink);
3128 if (IS_ERR(esw))
3129 return PTR_ERR(esw);
7768d197 3130
c55479d0 3131 down_write(&esw->mode_lock);
ae24432c
PP		 3132 err = eswitch_devlink_esw_mode_check(esw);
3133 if (err)
8e0aa4bc 3134 goto unlock;
ae24432c 3135
7768d197 3136 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3137 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3138 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3139 err = -EOPNOTSUPP;
3140 goto unlock;
3141 }
7768d197 3142
8e0aa4bc
PP		 3143 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3144 err = -EOPNOTSUPP;
3145 goto unlock;
3146 }
7768d197 3147
f6455de0 3148 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3149 esw->offloads.encap = encap;
8e0aa4bc 3150 goto unlock;
7768d197
RD		 3151 }
3152
3153 if (esw->offloads.encap == encap)
8e0aa4bc 3154 goto unlock;
7768d197 3155
525e84be 3156 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3157 NL_SET_ERR_MSG_MOD(extack,
3158 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3159 err = -EOPNOTSUPP;
3160 goto unlock;
7768d197
RD		 3161 }
3162
e52c2802 3163 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3164
3165 esw->offloads.encap = encap;
e52c2802 3166
0da3c12d 3167 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3168
7768d197 3169 if (err) {
8c98ee77
EB		 3170 NL_SET_ERR_MSG_MOD(extack,
3171 "Failed re-creating fast FDB table");
7768d197 3172 esw->offloads.encap = !encap;
0da3c12d 3173 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3174 }
e52c2802 3175
8e0aa4bc 3176unlock:
c55479d0 3177 up_write(&esw->mode_lock);
7768d197
RD		 3178 return err;
3179}
3180
98fdbea5
LR		 3181int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3182 enum devlink_eswitch_encap_mode *encap)
7768d197 3183{
bd939753 3184 struct mlx5_eswitch *esw;
9d1cef19 3185 int err;
7768d197 3186
bd939753
PP		 3187 esw = mlx5_devlink_eswitch_get(devlink);
3188 if (IS_ERR(esw))
3189 return PTR_ERR(esw);
3190
7768d197 3191
c55479d0 3192 down_write(&esw->mode_lock);
ae24432c
PP		 3193 err = eswitch_devlink_esw_mode_check(esw);
3194 if (err)
8e0aa4bc 3195 goto unlock;
ae24432c 3196
7768d197 3197 *encap = esw->offloads.encap;
8e0aa4bc 3198unlock:
c55479d0 3199 up_write(&esw->mode_lock);
7768d197
RD		 3200 return 0;
3201}
3202
c2d7712c
BW		 3203static bool
3204mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3205{
3206 /* Currently, only ECPF based device has representor for host PF. */
3207 if (vport_num == MLX5_VPORT_PF &&
3208 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3209 return false;
3210
3211 if (vport_num == MLX5_VPORT_ECPF &&
3212 !mlx5_ecpf_vport_exists(esw->dev))
3213 return false;
3214
3215 return true;
3216}
3217
f8e8fa02 3218void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 3219 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 3220 u8 rep_type)
127ea380 3221{
8693115a 3222 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 3223 struct mlx5_eswitch_rep *rep;
47dd7e60 3224 unsigned long i;
9deb2241 3225
8693115a 3226 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 3227 mlx5_esw_for_each_rep(esw, i, rep) {
3228 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 3229 rep->esw = esw;
c2d7712c
BW		 3230 rep_data = &rep->rep_data[rep_type];
3231 atomic_set(&rep_data->state, REP_REGISTERED);
3232 }
f8e8fa02 3233 }
127ea380 3234}
f8e8fa02 3235EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 3236
f8e8fa02 3237void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 3238{
cb67b832 3239 struct mlx5_eswitch_rep *rep;
47dd7e60 3240 unsigned long i;
cb67b832 3241
f6455de0 3242 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 3243 __unload_reps_all_vport(esw, rep_type);
127ea380 3244
47dd7e60 3245 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 3246 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 3247}
f8e8fa02 3248EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 3249
a4b97ab4 3250void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 3251{
726293f1
HHZ		 3252 struct mlx5_eswitch_rep *rep;
3253
879c8f84 3254 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 3255 return rep->rep_data[rep_type].priv;
726293f1 3256}
22215908
MB		 3257
3258void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 3259 u16 vport,
22215908
MB		 3260 u8 rep_type)
3261{
22215908
MB		 3262 struct mlx5_eswitch_rep *rep;
3263
879c8f84 3264 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 3265
8693115a
PP		 3266 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3267 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3268 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 3269 return NULL;
3270}
57cbd893 3271EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 3272
3273void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3274{
879c8f84 3275 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 3276}
57cbd893
MB		 3277EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3278
3279struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 3280 u16 vport)
57cbd893 3281{
879c8f84 3282 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 3283}
3284EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 3285
5b7cb745
PB		 3286bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3287{
3288 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3289}
3290EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3291
7445cfb1
JL		 3292bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3293{
3294 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3295}
3296EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3297
0f0d3827 3298u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 3299 u16 vport_num)
3300{
133dcfc5 3301 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 3302
133dcfc5
VP		 3303 if (WARN_ON_ONCE(IS_ERR(vport)))
3304 return 0;
0f0d3827 3305
133dcfc5 3306 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 3307}
3308EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 3309
3310int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 3311 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 3312{
3313 int err;
3314
3315 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3316 if (err)
3317 return err;
3318
f1b9acd3 3319 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 3320 if (err)
3321 goto devlink_err;
3322
3323 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3324 if (err)
3325 goto rep_err;
3326 return 0;
3327
3328rep_err:
3329 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3330devlink_err:
3331 mlx5_esw_vport_disable(esw, vport_num);
3332 return err;
3333}
3334
3335void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3336{
3337 mlx5_esw_offloads_rep_unload(esw, vport_num);
3338 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3339 mlx5_esw_vport_disable(esw, vport_num);
3340}
84ae9c1f
VB		 3341
3342static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3343{
3344 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3345 void *query_ctx;
3346 void *hca_caps;
3347 int err;
3348
3349 *vhca_id = 0;
3350 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3351 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3352 return -EPERM;
3353
3354 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3355 if (!query_ctx)
3356 return -ENOMEM;
3357
3358 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx);
3359 if (err)
3360 goto out_free;
3361
3362 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3363 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3364
3365out_free:
3366 kfree(query_ctx);
3367 return err;
3368}
3369
3370int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3371{
3372 u16 *old_entry, *vhca_map_entry, vhca_id;
3373 int err;
3374
3375 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3376 if (err) {
3377 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3378 vport_num, err);
3379 return err;
3380 }
3381
3382 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3383 if (!vhca_map_entry)
3384 return -ENOMEM;
3385
3386 *vhca_map_entry = vport_num;
3387 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3388 if (xa_is_err(old_entry)) {
3389 kfree(vhca_map_entry);
3390 return xa_err(old_entry);
3391 }
3392 kfree(old_entry);
3393 return 0;
3394}
3395
3396void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3397{
3398 u16 *vhca_map_entry, vhca_id;
3399 int err;
3400
3401 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3402 if (err)
3403 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3404 vport_num, err);
3405
3406 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3407 kfree(vhca_map_entry);
3408}
3409
3410int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3411{
3412 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3413
3414 if (!res)
3415 return -ENOENT;
3416
3417 *vport_num = *res;
3418 return 0;
3419}
10742efc
VB		 3420
3421u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3422 u16 vport_num)
3423{
3424 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3425
3426 if (WARN_ON_ONCE(IS_ERR(vport)))
3427 return 0;
3428
3429 return vport->metadata;
3430}
3431EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
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