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net/mlx5: E-Switch, Refactor setting source port
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
ea651a86 41#include "esw/acl/ofld.h"
80f09dfc 42#include "rdma.h"
e52c2802
PB		 43#include "en.h"
44#include "fs_core.h"
ac004b83 45#include "lib/devcom.h"
a3888f33 46#include "lib/eq.h"
ae430332 47#include "lib/fs_chains.h"
c620b772 48#include "en_tc.h"
69697b6e 49
cd7e4186
BW		 50/* There are two match-all miss flows, one for unicast dst mac and
51 * one for multicast.
52 */
53#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 54#define UPLINK_REP_INDEX 0
55
96e32687
EC		 56/* Per vport tables */
57
58#define MLX5_ESW_VPORT_TABLE_SIZE 128
59
60/* This struct is used as a key to the hash table and we need it to be packed
61 * so hash result is consistent
62 */
63struct mlx5_vport_key {
64 u32 chain;
65 u16 prio;
66 u16 vport;
67 u16 vhca_id;
68} __packed;
69
c620b772
AL		 70struct mlx5_vport_tbl_attr {
71 u16 chain;
72 u16 prio;
73 u16 vport;
74};
75
96e32687
EC		 76struct mlx5_vport_table {
77 struct hlist_node hlist;
78 struct mlx5_flow_table *fdb;
79 u32 num_rules;
80 struct mlx5_vport_key key;
81};
82
87dac697
JL		 83#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
84
96e32687
EC		 85static struct mlx5_flow_table *
86esw_vport_tbl_create(struct mlx5_eswitch *esw, struct mlx5_flow_namespace *ns)
87{
88 struct mlx5_flow_table_attr ft_attr = {};
89 struct mlx5_flow_table *fdb;
90
87dac697 91 ft_attr.autogroup.max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS;
96e32687
EC		 92 ft_attr.max_fte = MLX5_ESW_VPORT_TABLE_SIZE;
93 ft_attr.prio = FDB_PER_VPORT;
94 fdb = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
95 if (IS_ERR(fdb)) {
96 esw_warn(esw->dev, "Failed to create per vport FDB Table err %ld\n",
97 PTR_ERR(fdb));
98 }
99
100 return fdb;
101}
102
103static u32 flow_attr_to_vport_key(struct mlx5_eswitch *esw,
c620b772 104 struct mlx5_vport_tbl_attr *attr,
96e32687
EC		 105 struct mlx5_vport_key *key)
106{
c620b772 107 key->vport = attr->vport;
96e32687
EC		 108 key->chain = attr->chain;
109 key->prio = attr->prio;
110 key->vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
111 return jhash(key, sizeof(*key), 0);
112}
113
114/* caller must hold vports.lock */
115static struct mlx5_vport_table *
116esw_vport_tbl_lookup(struct mlx5_eswitch *esw, struct mlx5_vport_key *skey, u32 key)
117{
118 struct mlx5_vport_table *e;
119
120 hash_for_each_possible(esw->fdb_table.offloads.vports.table, e, hlist, key)
121 if (!memcmp(&e->key, skey, sizeof(*skey)))
122 return e;
123
124 return NULL;
125}
126
127static void
c620b772 128esw_vport_tbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr)
96e32687
EC		 129{
130 struct mlx5_vport_table *e;
131 struct mlx5_vport_key key;
132 u32 hkey;
133
134 mutex_lock(&esw->fdb_table.offloads.vports.lock);
135 hkey = flow_attr_to_vport_key(esw, attr, &key);
136 e = esw_vport_tbl_lookup(esw, &key, hkey);
137 if (!e || --e->num_rules)
138 goto out;
139
140 hash_del(&e->hlist);
141 mlx5_destroy_flow_table(e->fdb);
142 kfree(e);
143out:
144 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
145}
146
147static struct mlx5_flow_table *
c620b772 148esw_vport_tbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr)
96e32687
EC		 149{
150 struct mlx5_core_dev *dev = esw->dev;
151 struct mlx5_flow_namespace *ns;
152 struct mlx5_flow_table *fdb;
153 struct mlx5_vport_table *e;
154 struct mlx5_vport_key skey;
155 u32 hkey;
156
157 mutex_lock(&esw->fdb_table.offloads.vports.lock);
158 hkey = flow_attr_to_vport_key(esw, attr, &skey);
159 e = esw_vport_tbl_lookup(esw, &skey, hkey);
160 if (e) {
161 e->num_rules++;
162 goto out;
163 }
164
165 e = kzalloc(sizeof(*e), GFP_KERNEL);
166 if (!e) {
167 fdb = ERR_PTR(-ENOMEM);
168 goto err_alloc;
169 }
170
171 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
172 if (!ns) {
173 esw_warn(dev, "Failed to get FDB namespace\n");
174 fdb = ERR_PTR(-ENOENT);
175 goto err_ns;
176 }
177
178 fdb = esw_vport_tbl_create(esw, ns);
179 if (IS_ERR(fdb))
180 goto err_ns;
181
182 e->fdb = fdb;
183 e->num_rules = 1;
184 e->key = skey;
185 hash_add(esw->fdb_table.offloads.vports.table, &e->hlist, hkey);
186out:
187 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
188 return e->fdb;
189
190err_ns:
191 kfree(e);
192err_alloc:
193 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
194 return fdb;
195}
196
197int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw)
198{
c620b772 199 struct mlx5_vport_tbl_attr attr;
96e32687
EC		 200 struct mlx5_flow_table *fdb;
201 struct mlx5_vport *vport;
202 int i;
203
c620b772 204 attr.chain = 0;
96e32687 205 attr.prio = 1;
96e32687 206 mlx5_esw_for_all_vports(esw, i, vport) {
c620b772 207 attr.vport = vport->vport;
96e32687 208 fdb = esw_vport_tbl_get(esw, &attr);
d9fb932f 209 if (IS_ERR(fdb))
96e32687
EC		 210 goto out;
211 }
212 return 0;
213
214out:
215 mlx5_esw_vport_tbl_put(esw);
216 return PTR_ERR(fdb);
217}
218
219void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw)
220{
c620b772 221 struct mlx5_vport_tbl_attr attr;
96e32687
EC		 222 struct mlx5_vport *vport;
223 int i;
224
c620b772 225 attr.chain = 0;
96e32687 226 attr.prio = 1;
96e32687 227 mlx5_esw_for_all_vports(esw, i, vport) {
c620b772 228 attr.vport = vport->vport;
96e32687
EC		 229 esw_vport_tbl_put(esw, &attr);
230 }
231}
232
233/* End: Per vport tables */
234
879c8f84
BW		 235static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
236 u16 vport_num)
237{
02f3afd9 238 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
879c8f84
BW		 239
240 WARN_ON(idx > esw->total_vports - 1);
241 return &esw->offloads.vport_reps[idx];
242}
243
6f7bbad1
JL		 244static void
245mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
246 struct mlx5_flow_spec *spec,
247 struct mlx5_esw_flow_attr *attr)
248{
249 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
036e19b9
HI		 250 attr && attr->in_rep)
251 spec->flow_context.flow_source =
252 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
253 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
254 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 255}
b7826076 256
c01cfd0f
JL		 257static void
258mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
259 struct mlx5_flow_spec *spec,
b055ecf5
MB		 260 struct mlx5_eswitch *src_esw,
261 u16 vport)
c01cfd0f
JL		 262{
263 void *misc2;
264 void *misc;
265
266 /* Use metadata matching because vport is not represented by single
267 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
268 */
269 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
270 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
271 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
b055ecf5
MB		 272 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
273 vport));
c01cfd0f
JL		 274
275 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 276 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
277 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 278
279 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 280 } else {
281 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 282 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 283
284 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
285 MLX5_SET(fte_match_set_misc, misc,
286 source_eswitch_owner_vhca_id,
b055ecf5 287 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 288
289 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
290 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
291 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
292 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
293 source_eswitch_owner_vhca_id);
294
295 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
296 }
c01cfd0f
JL		 297}
298
74491de9 299struct mlx5_flow_handle *
3d80d1a2
OG		 300mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
301 struct mlx5_flow_spec *spec,
c620b772 302 struct mlx5_flow_attr *attr)
3d80d1a2 303{
592d3651 304 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 305 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 306 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 307 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 308 bool split = !!(esw_attr->split_count);
309 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 310 struct mlx5_flow_handle *rule;
e52c2802 311 struct mlx5_flow_table *fdb;
592d3651 312 int j, i = 0;
3d80d1a2 313
f6455de0 314 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 315 return ERR_PTR(-EOPNOTSUPP);
316
6acfbf38
OG		 317 flow_act.action = attr->action;
318 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 319 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 320 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
321 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
322 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 323 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
324 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
325 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 326 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 327 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
328 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
329 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 330 }
6acfbf38 331 }
776b12b6 332
66958ed9 333 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
39ac237c 334 struct mlx5_flow_table *ft;
e52c2802 335
d18296ff
PB		 336 if (attr->dest_ft) {
337 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
338 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
339 dest[i].ft = attr->dest_ft;
340 i++;
341 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
39ac237c
PB		 342 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
343 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
ae430332 344 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
39ac237c
PB		 345 i++;
346 } else if (attr->dest_chain) {
347 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
ae430332
AL		 348 ft = mlx5_chains_get_table(chains, attr->dest_chain,
349 1, 0);
e52c2802
PB		 350 if (IS_ERR(ft)) {
351 rule = ERR_CAST(ft);
352 goto err_create_goto_table;
353 }
354
355 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
356 dest[i].ft = ft;
592d3651 357 i++;
e52c2802 358 } else {
c620b772 359 for (j = esw_attr->split_count; j < esw_attr->out_count; j++) {
e52c2802 360 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
c620b772 361 dest[i].vport.num = esw_attr->dests[j].rep->vport;
e52c2802 362 dest[i].vport.vhca_id =
c620b772 363 MLX5_CAP_GEN(esw_attr->dests[j].mdev, vhca_id);
aa39c2c0
EB		 364 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
365 dest[i].vport.flags |=
366 MLX5_FLOW_DEST_VPORT_VHCA_ID;
c620b772 367 if (esw_attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
f493f155 368 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
c620b772
AL		 369 flow_act.pkt_reformat =
370 esw_attr->dests[j].pkt_reformat;
a18e879d 371 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
2b688ea5 372 dest[i].vport.pkt_reformat =
c620b772 373 esw_attr->dests[j].pkt_reformat;
f493f155 374 }
e52c2802
PB		 375 i++;
376 }
56e858df 377 }
e37a79e5 378 }
14e6b038 379
c620b772
AL		 380 if (esw_attr->decap_pkt_reformat)
381 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 382
66958ed9 383 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 384 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 385 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 386 i++;
3d80d1a2
OG		 387 }
388
93b3586e 389 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 390 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 391 if (attr->inner_match_level != MLX5_MATCH_NONE)
392 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 393
aa24670e 394 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 395 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 396
96e32687 397 if (split) {
c620b772
AL		 398 fwd_attr.chain = attr->chain;
399 fwd_attr.prio = attr->prio;
400 fwd_attr.vport = esw_attr->in_rep->vport;
401
402 fdb = esw_vport_tbl_get(esw, &fwd_attr);
96e32687 403 } else {
d18296ff 404 if (attr->chain || attr->prio)
ae430332
AL		 405 fdb = mlx5_chains_get_table(chains, attr->chain,
406 attr->prio, 0);
d18296ff 407 else
c620b772 408 fdb = attr->ft;
6fb0701a
PB		 409
410 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
b055ecf5
MB		 411 mlx5_eswitch_set_rule_source_port(esw, spec,
412 esw_attr->in_mdev->priv.eswitch,
413 esw_attr->in_rep->vport);
96e32687 414 }
e52c2802
PB		 415 if (IS_ERR(fdb)) {
416 rule = ERR_CAST(fdb);
417 goto err_esw_get;
418 }
419
c620b772 420 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
6f7bbad1 421
84be2fda 422 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 423 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 424 &flow_act, dest, i);
84be2fda 425 else
10caabda 426 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 427 if (IS_ERR(rule))
e52c2802 428 goto err_add_rule;
375f51e2 429 else
525e84be 430 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 431
e52c2802
PB		 432 return rule;
433
434err_add_rule:
96e32687 435 if (split)
c620b772 436 esw_vport_tbl_put(esw, &fwd_attr);
d18296ff 437 else if (attr->chain || attr->prio)
ae430332 438 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 439err_esw_get:
39ac237c 440 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) && attr->dest_chain)
ae430332 441 mlx5_chains_put_table(chains, attr->dest_chain, 1, 0);
e52c2802 442err_create_goto_table:
aa0cbbae 443 return rule;
3d80d1a2
OG		 444}
445
e4ad91f2
CM		 446struct mlx5_flow_handle *
447mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
448 struct mlx5_flow_spec *spec,
c620b772 449 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 450{
451 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 452 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 453 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 454 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 455 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 456 struct mlx5_flow_table *fast_fdb;
457 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 458 struct mlx5_flow_handle *rule;
e4ad91f2
CM		 459 int i;
460
ae430332 461 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 462 if (IS_ERR(fast_fdb)) {
463 rule = ERR_CAST(fast_fdb);
464 goto err_get_fast;
465 }
466
c620b772
AL		 467 fwd_attr.chain = attr->chain;
468 fwd_attr.prio = attr->prio;
469 fwd_attr.vport = esw_attr->in_rep->vport;
470 fwd_fdb = esw_vport_tbl_get(esw, &fwd_attr);
e52c2802
PB		 471 if (IS_ERR(fwd_fdb)) {
472 rule = ERR_CAST(fwd_fdb);
473 goto err_get_fwd;
474 }
475
e4ad91f2 476 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
c620b772 477 for (i = 0; i < esw_attr->split_count; i++) {
e4ad91f2 478 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
c620b772 479 dest[i].vport.num = esw_attr->dests[i].rep->vport;
e4ad91f2 480 dest[i].vport.vhca_id =
c620b772 481 MLX5_CAP_GEN(esw_attr->dests[i].mdev, vhca_id);
aa39c2c0
EB		 482 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
483 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
c620b772 484 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
1cc26d74 485 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
c620b772 486 dest[i].vport.pkt_reformat = esw_attr->dests[i].pkt_reformat;
1cc26d74 487 }
e4ad91f2
CM		 488 }
489 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 490 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 491 i++;
492
b055ecf5
MB		 493 mlx5_eswitch_set_rule_source_port(esw, spec,
494 esw_attr->in_mdev->priv.eswitch,
495 esw_attr->in_rep->vport);
e4ad91f2 496
93b3586e 497 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 498 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 499
278d51f2 500 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 501 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 502
e52c2802
PB		 503 if (IS_ERR(rule))
504 goto add_err;
e4ad91f2 505
525e84be 506 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 507
508 return rule;
509add_err:
c620b772 510 esw_vport_tbl_put(esw, &fwd_attr);
e52c2802 511err_get_fwd:
ae430332 512 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 513err_get_fast:
e4ad91f2
CM		 514 return rule;
515}
516
e52c2802
PB		 517static void
518__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
519 struct mlx5_flow_handle *rule,
c620b772 520 struct mlx5_flow_attr *attr,
e52c2802
PB		 521 bool fwd_rule)
522{
c620b772 523 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 524 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 525 bool split = (esw_attr->split_count > 0);
526 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 527 int i;
e52c2802
PB		 528
529 mlx5_del_flow_rules(rule);
10caabda 530
84be2fda 531 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 532 /* unref the term table */
533 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 534 if (esw_attr->dests[i].termtbl)
535 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 536 }
10caabda
OS		 537 }
538
525e84be 539 atomic64_dec(&esw->offloads.num_flows);
e52c2802 540
c620b772
AL		 541 if (fwd_rule || split) {
542 fwd_attr.chain = attr->chain;
543 fwd_attr.prio = attr->prio;
544 fwd_attr.vport = esw_attr->in_rep->vport;
545 }
546
e52c2802 547 if (fwd_rule) {
c620b772 548 esw_vport_tbl_put(esw, &fwd_attr);
ae430332 549 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 550 } else {
96e32687 551 if (split)
c620b772 552 esw_vport_tbl_put(esw, &fwd_attr);
d18296ff 553 else if (attr->chain || attr->prio)
ae430332 554 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 555 if (attr->dest_chain)
ae430332 556 mlx5_chains_put_table(chains, attr->dest_chain, 1, 0);
e52c2802
PB		 557 }
558}
559
d85cdccb
OG		 560void
561mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
562 struct mlx5_flow_handle *rule,
c620b772 563 struct mlx5_flow_attr *attr)
d85cdccb 564{
e52c2802 565 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 566}
567
48265006
OG		 568void
569mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
570 struct mlx5_flow_handle *rule,
c620b772 571 struct mlx5_flow_attr *attr)
48265006 572{
e52c2802 573 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 574}
575
f5f82476
OG		 576static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
577{
578 struct mlx5_eswitch_rep *rep;
411ec9e0 579 int i, err = 0;
f5f82476
OG		 580
581 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
411ec9e0 582 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 583 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 584 continue;
585
586 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
587 if (err)
588 goto out;
589 }
590
591out:
592 return err;
593}
594
595static struct mlx5_eswitch_rep *
596esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
597{
598 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
599
600 in_rep = attr->in_rep;
df65a573 601 out_rep = attr->dests[0].rep;
f5f82476
OG		 602
603 if (push)
604 vport = in_rep;
605 else if (pop)
606 vport = out_rep;
607 else
608 vport = in_rep;
609
610 return vport;
611}
612
613static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
614 bool push, bool pop, bool fwd)
615{
616 struct mlx5_eswitch_rep *in_rep, *out_rep;
617
618 if ((push || pop) && !fwd)
619 goto out_notsupp;
620
621 in_rep = attr->in_rep;
df65a573 622 out_rep = attr->dests[0].rep;
f5f82476 623
b05af6aa 624 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 625 goto out_notsupp;
626
b05af6aa 627 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 628 goto out_notsupp;
629
630 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
631 if (!push && !pop && fwd)
b05af6aa 632 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 633 goto out_notsupp;
634
635 /* protects against (1) setting rules with different vlans to push and
636 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
637 */
1482bd3d 638 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 639 goto out_notsupp;
640
641 return 0;
642
643out_notsupp:
9eb78923 644 return -EOPNOTSUPP;
f5f82476
OG		 645}
646
647int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 648 struct mlx5_flow_attr *attr)
f5f82476
OG		 649{
650 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 651 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 652 struct mlx5_eswitch_rep *vport = NULL;
653 bool push, pop, fwd;
654 int err = 0;
655
6acfbf38 656 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 657 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 658 return 0;
659
f5f82476
OG		 660 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
661 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 662 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
663 !attr->dest_chain);
f5f82476 664
0e18134f
VB		 665 mutex_lock(&esw->state_lock);
666
c620b772 667 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 668 if (err)
0e18134f 669 goto unlock;
f5f82476 670
39ac237c 671 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 672
c620b772 673 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 674
675 if (!push && !pop && fwd) {
676 /* tracks VF --> wire rules without vlan push action */
c620b772 677 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 678 vport->vlan_refcount++;
39ac237c 679 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 680 }
681
0e18134f 682 goto unlock;
f5f82476
OG		 683 }
684
685 if (!push && !pop)
0e18134f 686 goto unlock;
f5f82476
OG		 687
688 if (!(offloads->vlan_push_pop_refcount)) {
689 /* it's the 1st vlan rule, apply global vlan pop policy */
690 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
691 if (err)
692 goto out;
693 }
694 offloads->vlan_push_pop_refcount++;
695
696 if (push) {
697 if (vport->vlan_refcount)
698 goto skip_set_push;
699
c620b772
AL		 700 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
701 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 702 if (err)
703 goto out;
c620b772 704 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 705skip_set_push:
706 vport->vlan_refcount++;
707 }
708out:
709 if (!err)
39ac237c 710 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 711unlock:
712 mutex_unlock(&esw->state_lock);
f5f82476
OG		 713 return err;
714}
715
716int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 717 struct mlx5_flow_attr *attr)
f5f82476
OG		 718{
719 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 720 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 721 struct mlx5_eswitch_rep *vport = NULL;
722 bool push, pop, fwd;
723 int err = 0;
724
6acfbf38 725 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 726 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 727 return 0;
728
39ac237c 729 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 730 return 0;
731
732 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
733 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
734 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
735
0e18134f
VB		 736 mutex_lock(&esw->state_lock);
737
c620b772 738 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 739
740 if (!push && !pop && fwd) {
741 /* tracks VF --> wire rules without vlan push action */
c620b772 742 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 743 vport->vlan_refcount--;
744
0e18134f 745 goto out;
f5f82476
OG		 746 }
747
748 if (push) {
749 vport->vlan_refcount--;
750 if (vport->vlan_refcount)
751 goto skip_unset_push;
752
753 vport->vlan = 0;
754 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
755 0, 0, SET_VLAN_STRIP);
756 if (err)
757 goto out;
758 }
759
760skip_unset_push:
761 offloads->vlan_push_pop_refcount--;
762 if (offloads->vlan_push_pop_refcount)
0e18134f 763 goto out;
f5f82476
OG		 764
765 /* no more vlan rules, stop global vlan pop policy */
766 err = esw_set_global_vlan_pop(esw, 0);
767
768out:
0e18134f 769 mutex_unlock(&esw->state_lock);
f5f82476
OG		 770 return err;
771}
772
f7a68945 773struct mlx5_flow_handle *
02f3afd9
PP		 774mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
775 u32 sqn)
ab22be9b 776{
66958ed9 777 struct mlx5_flow_act flow_act = {0};
4c5009c5 778 struct mlx5_flow_destination dest = {};
74491de9 779 struct mlx5_flow_handle *flow_rule;
c5bb1730 780 struct mlx5_flow_spec *spec;
ab22be9b
OG		 781 void *misc;
782
1b9a07ee 783 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 784 if (!spec) {
ab22be9b
OG		 785 flow_rule = ERR_PTR(-ENOMEM);
786 goto out;
787 }
788
c5bb1730 789 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 790 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a
BW		 791 /* source vport is the esw manager */
792 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
ab22be9b 793
c5bb1730 794 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 795 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
796 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
797
c5bb1730 798 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 799 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 800 dest.vport.num = vport;
66958ed9 801 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 802
39ac237c
PB		 803 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
804 spec, &flow_act, &dest, 1);
ab22be9b
OG		 805 if (IS_ERR(flow_rule))
806 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
807out:
c5bb1730 808 kvfree(spec);
ab22be9b
OG		 809 return flow_rule;
810}
57cbd893 811EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 812
159fe639
MB		 813void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
814{
815 mlx5_del_flow_rules(rule);
816}
817
5b7cb745
PB		 818static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
819{
820 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
821 MLX5_FDB_TO_VPORT_REG_C_1;
822}
823
332bd3a5 824static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 825{
826 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 827 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
828 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 829 u8 curr, wanted;
c1286050
JL		 830 int err;
831
5b7cb745
PB		 832 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
833 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 834 return 0;
c1286050 835
e08a6832
LR		 836 MLX5_SET(query_esw_vport_context_in, in, opcode,
837 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
838 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 839 if (err)
840 return err;
841
5b7cb745
PB		 842 curr = MLX5_GET(query_esw_vport_context_out, out,
843 esw_vport_context.fdb_to_vport_reg_c_id);
844 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
845 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
846 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 847
332bd3a5 848 if (enable)
5b7cb745 849 curr |= wanted;
332bd3a5 850 else
5b7cb745 851 curr &= ~wanted;
c1286050 852
e08a6832 853 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 854 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 855 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 856 field_select.fdb_to_vport_reg_c_id, 1);
857
e08a6832 858 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 859 if (!err) {
860 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
861 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
862 else
863 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
864 }
865
866 return err;
c1286050
JL		 867}
868
a5641cb5
JL		 869static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
870 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 871 struct mlx5_flow_spec *spec,
872 struct mlx5_flow_destination *dest)
873{
a5641cb5 874 void *misc;
ac004b83 875
a5641cb5
JL		 876 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
877 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
878 misc_parameters_2);
0f0d3827
PB		 879 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
880 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 881
a5641cb5
JL		 882 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
883 } else {
884 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
885 misc_parameters);
ac004b83 886
a5641cb5
JL		 887 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
888 MLX5_CAP_GEN(peer_dev, vhca_id));
889
890 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
891
892 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
893 misc_parameters);
894 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
895 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
896 source_eswitch_owner_vhca_id);
897 }
ac004b83
RD		 898
899 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 900 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 901 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 902 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 903}
904
a5641cb5
JL		 905static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
906 struct mlx5_eswitch *peer_esw,
907 struct mlx5_flow_spec *spec,
908 u16 vport)
909{
910 void *misc;
911
912 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
913 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
914 misc_parameters_2);
915 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
916 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
917 vport));
918 } else {
919 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
920 misc_parameters);
921 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
922 }
923}
924
ac004b83
RD		 925static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
926 struct mlx5_core_dev *peer_dev)
927{
928 struct mlx5_flow_destination dest = {};
929 struct mlx5_flow_act flow_act = {0};
930 struct mlx5_flow_handle **flows;
931 struct mlx5_flow_handle *flow;
932 struct mlx5_flow_spec *spec;
933 /* total vports is the same for both e-switches */
934 int nvports = esw->total_vports;
935 void *misc;
936 int err, i;
937
938 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
939 if (!spec)
940 return -ENOMEM;
941
a5641cb5 942 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 943
944 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
945 if (!flows) {
946 err = -ENOMEM;
947 goto alloc_flows_err;
948 }
949
950 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
951 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
952 misc_parameters);
953
81cd229c 954 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
a5641cb5
JL		 955 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
956 spec, MLX5_VPORT_PF);
957
81cd229c
BW		 958 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
959 spec, &flow_act, &dest, 1);
960 if (IS_ERR(flow)) {
961 err = PTR_ERR(flow);
962 goto add_pf_flow_err;
963 }
964 flows[MLX5_VPORT_PF] = flow;
965 }
966
967 if (mlx5_ecpf_vport_exists(esw->dev)) {
968 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
969 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
970 spec, &flow_act, &dest, 1);
971 if (IS_ERR(flow)) {
972 err = PTR_ERR(flow);
973 goto add_ecpf_flow_err;
974 }
975 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
976 }
977
786ef904 978 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 979 esw_set_peer_miss_rule_source_port(esw,
980 peer_dev->priv.eswitch,
981 spec, i);
982
ac004b83
RD		 983 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
984 spec, &flow_act, &dest, 1);
985 if (IS_ERR(flow)) {
986 err = PTR_ERR(flow);
81cd229c 987 goto add_vf_flow_err;
ac004b83
RD		 988 }
989 flows[i] = flow;
990 }
991
992 esw->fdb_table.offloads.peer_miss_rules = flows;
993
994 kvfree(spec);
995 return 0;
996
81cd229c 997add_vf_flow_err:
879c8f84 998 nvports = --i;
786ef904 999 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
ac004b83 1000 mlx5_del_flow_rules(flows[i]);
81cd229c
BW		 1001
1002 if (mlx5_ecpf_vport_exists(esw->dev))
1003 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
1004add_ecpf_flow_err:
1005 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
1006 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
1007add_pf_flow_err:
1008 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1009 kvfree(flows);
1010alloc_flows_err:
1011 kvfree(spec);
1012 return err;
1013}
1014
1015static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1016{
1017 struct mlx5_flow_handle **flows;
1018 int i;
1019
1020 flows = esw->fdb_table.offloads.peer_miss_rules;
1021
786ef904
PP		 1022 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
1023 mlx5_core_max_vfs(esw->dev))
ac004b83
RD		 1024 mlx5_del_flow_rules(flows[i]);
1025
81cd229c
BW		 1026 if (mlx5_ecpf_vport_exists(esw->dev))
1027 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
1028
1029 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
1030 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
1031
ac004b83
RD		 1032 kvfree(flows);
1033}
1034
3aa33572
OG		 1035static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1036{
66958ed9 1037 struct mlx5_flow_act flow_act = {0};
4c5009c5 1038 struct mlx5_flow_destination dest = {};
74491de9 1039 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1040 struct mlx5_flow_spec *spec;
f80be543
MB		 1041 void *headers_c;
1042 void *headers_v;
3aa33572 1043 int err = 0;
f80be543
MB		 1044 u8 *dmac_c;
1045 u8 *dmac_v;
3aa33572 1046
1b9a07ee 1047 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1048 if (!spec) {
3aa33572
OG		 1049 err = -ENOMEM;
1050 goto out;
1051 }
1052
f80be543
MB		 1053 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1054 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1055 outer_headers);
1056 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1057 outer_headers.dmac_47_16);
1058 dmac_c[0] = 0x01;
1059
3aa33572 1060 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1061 dest.vport.num = esw->manager_vport;
66958ed9 1062 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1063
39ac237c
PB		 1064 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1065 spec, &flow_act, &dest, 1);
3aa33572
OG		 1066 if (IS_ERR(flow_rule)) {
1067 err = PTR_ERR(flow_rule);
f80be543 1068 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1069 goto out;
1070 }
1071
f80be543
MB		 1072 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1073
1074 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1075 outer_headers);
1076 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1077 outer_headers.dmac_47_16);
1078 dmac_v[0] = 0x01;
39ac237c
PB		 1079 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1080 spec, &flow_act, &dest, 1);
f80be543
MB		 1081 if (IS_ERR(flow_rule)) {
1082 err = PTR_ERR(flow_rule);
1083 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1084 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1085 goto out;
1086 }
1087
1088 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1089
3aa33572 1090out:
c5bb1730 1091 kvfree(spec);
3aa33572
OG		 1092 return err;
1093}
1094
11b717d6
PB		 1095struct mlx5_flow_handle *
1096esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1097{
1098 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1099 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1100 struct mlx5_flow_context *flow_context;
1101 struct mlx5_flow_handle *flow_rule;
1102 struct mlx5_flow_destination dest;
1103 struct mlx5_flow_spec *spec;
1104 void *misc;
1105
60acc105
PB		 1106 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1107 return ERR_PTR(-EOPNOTSUPP);
1108
11b717d6
PB		 1109 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1110 if (!spec)
1111 return ERR_PTR(-ENOMEM);
1112
1113 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1114 misc_parameters_2);
1115 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1116 ESW_CHAIN_TAG_METADATA_MASK);
1117 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1118 misc_parameters_2);
1119 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1120 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1121 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1122 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1123 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1124
1125 flow_context = &spec->flow_context;
1126 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1127 flow_context->flow_tag = tag;
1128 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1129 dest.ft = esw->offloads.ft_offloads;
1130
1131 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1132 kfree(spec);
1133
1134 if (IS_ERR(flow_rule))
1135 esw_warn(esw->dev,
1136 "Failed to create restore rule for tag: %d, err(%d)\n",
1137 tag, (int)PTR_ERR(flow_rule));
1138
1139 return flow_rule;
1140}
1141
1142u32
1143esw_get_max_restore_tag(struct mlx5_eswitch *esw)
1144{
1145 return ESW_CHAIN_TAG_METADATA_MASK;
1146}
1147
1967ce6e 1148#define MAX_PF_SQ 256
cd3d07e7 1149#define MAX_SQ_NVPORTS 32
1967ce6e 1150
a5641cb5
JL		 1151static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1152 u32 *flow_group_in)
1153{
1154 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1155 flow_group_in,
1156 match_criteria);
1157
1158 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1159 MLX5_SET(create_flow_group_in, flow_group_in,
1160 match_criteria_enable,
1161 MLX5_MATCH_MISC_PARAMETERS_2);
1162
0f0d3827
PB		 1163 MLX5_SET(fte_match_param, match_criteria,
1164 misc_parameters_2.metadata_reg_c_0,
1165 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1166 } else {
1167 MLX5_SET(create_flow_group_in, flow_group_in,
1168 match_criteria_enable,
1169 MLX5_MATCH_MISC_PARAMETERS);
1170
1171 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1172 misc_parameters.source_port);
1173 }
1174}
1175
ae430332
AL		 1176#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
1177#define fdb_modify_header_fwd_to_table_supported(esw) \
1178 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1179static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1180{
1181 struct mlx5_core_dev *dev = esw->dev;
1182
1183 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1184 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1185
1186 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1187 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1188 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1189 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1190 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1191 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1192 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1193 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1194 /* Disabled when ttl workaround is needed, e.g
1195 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1196 */
1197 esw_warn(dev,
1198 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1199 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1200 } else {
1201 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1202 esw_info(dev, "Supported tc chains and prios offload\n");
1203 }
1204
1205 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1206 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1207}
1208
1209static int
1210esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1211{
1212 struct mlx5_core_dev *dev = esw->dev;
1213 struct mlx5_flow_table *nf_ft, *ft;
1214 struct mlx5_chains_attr attr = {};
1215 struct mlx5_fs_chains *chains;
1216 u32 fdb_max;
1217 int err;
1218
1219 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1220
1221 esw_init_chains_offload_flags(esw, &attr.flags);
1222 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1223 attr.max_ft_sz = fdb_max;
1224 attr.max_grp_num = esw->params.large_group_num;
1225 attr.default_ft = miss_fdb;
1226 attr.max_restore_tag = esw_get_max_restore_tag(esw);
1227
1228 chains = mlx5_chains_create(dev, &attr);
1229 if (IS_ERR(chains)) {
1230 err = PTR_ERR(chains);
1231 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1232 return err;
1233 }
1234
1235 esw->fdb_table.offloads.esw_chains_priv = chains;
1236
1237 /* Create tc_end_ft which is the always created ft chain */
1238 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1239 1, 0);
1240 if (IS_ERR(nf_ft)) {
1241 err = PTR_ERR(nf_ft);
1242 goto nf_ft_err;
1243 }
1244
1245 /* Always open the root for fast path */
1246 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1247 if (IS_ERR(ft)) {
1248 err = PTR_ERR(ft);
1249 goto level_0_err;
1250 }
1251
1252 /* Open level 1 for split fdb rules now if prios isn't supported */
1253 if (!mlx5_chains_prios_supported(chains)) {
1254 err = mlx5_esw_vport_tbl_get(esw);
1255 if (err)
1256 goto level_1_err;
1257 }
1258
1259 mlx5_chains_set_end_ft(chains, nf_ft);
1260
1261 return 0;
1262
1263level_1_err:
1264 mlx5_chains_put_table(chains, 0, 1, 0);
1265level_0_err:
1266 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1267nf_ft_err:
1268 mlx5_chains_destroy(chains);
1269 esw->fdb_table.offloads.esw_chains_priv = NULL;
1270
1271 return err;
1272}
1273
1274static void
1275esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1276{
1277 if (!mlx5_chains_prios_supported(chains))
1278 mlx5_esw_vport_tbl_put(esw);
1279 mlx5_chains_put_table(chains, 0, 1, 0);
1280 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1281 mlx5_chains_destroy(chains);
1282}
1283
1284#else /* CONFIG_MLX5_CLS_ACT */
1285
1286static int
1287esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1288{ return 0; }
1289
1290static void
1291esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1292{}
1293
1294#endif
1295
0da3c12d 1296static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1297{
1298 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1299 struct mlx5_flow_table_attr ft_attr = {};
1300 struct mlx5_core_dev *dev = esw->dev;
1301 struct mlx5_flow_namespace *root_ns;
1302 struct mlx5_flow_table *fdb = NULL;
39ac237c
PB		 1303 u32 flags = 0, *flow_group_in;
1304 int table_size, ix, err = 0;
1967ce6e
OG		 1305 struct mlx5_flow_group *g;
1306 void *match_criteria;
f80be543 1307 u8 *dmac;
1967ce6e
OG		 1308
1309 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1310
1b9a07ee 1311 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1312 if (!flow_group_in)
1313 return -ENOMEM;
1314
1315 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1316 if (!root_ns) {
1317 esw_warn(dev, "Failed to get FDB flow namespace\n");
1318 err = -EOPNOTSUPP;
1319 goto ns_err;
1320 }
8463daf1
MG		 1321 esw->fdb_table.offloads.ns = root_ns;
1322 err = mlx5_flow_namespace_set_mode(root_ns,
1323 esw->dev->priv.steering->mode);
1324 if (err) {
1325 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1326 goto ns_err;
1327 }
1967ce6e 1328
0da3c12d 1329 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
cd7e4186 1330 MLX5_ESW_MISS_FLOWS + esw->total_vports;
b3ba5149 1331
e52c2802
PB		 1332 /* create the slow path fdb with encap set, so further table instances
1333 * can be created at run time while VFs are probed if the FW allows that.
1334 */
1335 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1336 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1337 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1338
1339 ft_attr.flags = flags;
b3ba5149
ES		 1340 ft_attr.max_fte = table_size;
1341 ft_attr.prio = FDB_SLOW_PATH;
1342
1343 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1344 if (IS_ERR(fdb)) {
1345 err = PTR_ERR(fdb);
1346 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1347 goto slow_fdb_err;
1348 }
52fff327 1349 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1350
ae430332 1351 err = esw_chains_create(esw, fdb);
39ac237c 1352 if (err) {
ae430332 1353 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1354 goto fdb_chains_err;
e52c2802
PB		 1355 }
1356
69697b6e 1357 /* create send-to-vport group */
69697b6e
OG		 1358 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1359 MLX5_MATCH_MISC_PARAMETERS);
1360
1361 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1362
1363 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1364 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1365
0da3c12d 1366 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1367 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1368 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1369
1370 g = mlx5_create_flow_group(fdb, flow_group_in);
1371 if (IS_ERR(g)) {
1372 err = PTR_ERR(g);
1373 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1374 goto send_vport_err;
1375 }
1376 esw->fdb_table.offloads.send_to_vport_grp = g;
1377
6cec0229
MD		 1378 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1379 /* create peer esw miss group */
1380 memset(flow_group_in, 0, inlen);
ac004b83 1381
6cec0229 1382 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1383
6cec0229
MD		 1384 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1385 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1386 flow_group_in,
1387 match_criteria);
ac004b83 1388
6cec0229
MD		 1389 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1390 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1391
6cec0229
MD		 1392 MLX5_SET(create_flow_group_in, flow_group_in,
1393 source_eswitch_owner_vhca_id_valid, 1);
1394 }
ac004b83 1395
6cec0229
MD		 1396 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1397 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1398 ix + esw->total_vports - 1);
1399 ix += esw->total_vports;
ac004b83 1400
6cec0229
MD		 1401 g = mlx5_create_flow_group(fdb, flow_group_in);
1402 if (IS_ERR(g)) {
1403 err = PTR_ERR(g);
1404 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1405 goto peer_miss_err;
1406 }
1407 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1408 }
ac004b83 1409
69697b6e
OG		 1410 /* create miss group */
1411 memset(flow_group_in, 0, inlen);
f80be543
MB		 1412 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1413 MLX5_MATCH_OUTER_HEADERS);
1414 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1415 match_criteria);
1416 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1417 outer_headers.dmac_47_16);
1418 dmac[0] = 0x01;
69697b6e
OG		 1419
1420 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1421 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1422 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1423
1424 g = mlx5_create_flow_group(fdb, flow_group_in);
1425 if (IS_ERR(g)) {
1426 err = PTR_ERR(g);
1427 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1428 goto miss_err;
1429 }
1430 esw->fdb_table.offloads.miss_grp = g;
1431
3aa33572
OG		 1432 err = esw_add_fdb_miss_rule(esw);
1433 if (err)
1434 goto miss_rule_err;
1435
c88a026e 1436 kvfree(flow_group_in);
69697b6e
OG		 1437 return 0;
1438
3aa33572
OG		 1439miss_rule_err:
1440 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1441miss_err:
6cec0229
MD		 1442 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1443 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1444peer_miss_err:
69697b6e
OG		 1445 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1446send_vport_err:
ae430332 1447 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1448fdb_chains_err:
52fff327 1449 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1450slow_fdb_err:
8463daf1
MG		 1451 /* Holds true only as long as DMFS is the default */
1452 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1453ns_err:
1454 kvfree(flow_group_in);
1455 return err;
1456}
1457
1967ce6e 1458static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1459{
e52c2802 1460 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1461 return;
1462
1967ce6e 1463 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1464 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1465 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1466 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
6cec0229
MD		 1467 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1468 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1469 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1470
ae430332
AL		 1471 esw_chains_destroy(esw, esw_chains(esw));
1472
52fff327 1473 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1474 /* Holds true only as long as DMFS is the default */
1475 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1476 MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e 1477}
c116c6ee 1478
8d6bd3c3 1479static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1480{
b3ba5149 1481 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1482 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1483 struct mlx5_flow_table *ft_offloads;
1484 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1485 int err = 0;
1486
1487 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1488 if (!ns) {
1489 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1490 return -EOPNOTSUPP;
c116c6ee
OG		 1491 }
1492
8d6bd3c3 1493 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1494 ft_attr.prio = 1;
b3ba5149
ES		 1495
1496 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1497 if (IS_ERR(ft_offloads)) {
1498 err = PTR_ERR(ft_offloads);
1499 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1500 return err;
1501 }
1502
1503 esw->offloads.ft_offloads = ft_offloads;
1504 return 0;
1505}
1506
1507static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1508{
1509 struct mlx5_esw_offload *offloads = &esw->offloads;
1510
1511 mlx5_destroy_flow_table(offloads->ft_offloads);
1512}
fed9ce22 1513
8d6bd3c3 1514static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1515{
1516 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1517 struct mlx5_flow_group *g;
fed9ce22 1518 u32 *flow_group_in;
8d6bd3c3 1519 int nvports;
fed9ce22 1520 int err = 0;
fed9ce22 1521
8d6bd3c3 1522 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1523 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1524 if (!flow_group_in)
1525 return -ENOMEM;
1526
1527 /* create vport rx group */
a5641cb5 1528 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1529
1530 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1531 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1532
1533 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1534
1535 if (IS_ERR(g)) {
1536 err = PTR_ERR(g);
1537 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1538 goto out;
1539 }
1540
1541 esw->offloads.vport_rx_group = g;
1542out:
e574978a 1543 kvfree(flow_group_in);
fed9ce22
OG		 1544 return err;
1545}
1546
1547static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1548{
1549 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1550}
1551
74491de9 1552struct mlx5_flow_handle *
02f3afd9 1553mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1554 struct mlx5_flow_destination *dest)
fed9ce22 1555{
66958ed9 1556 struct mlx5_flow_act flow_act = {0};
74491de9 1557 struct mlx5_flow_handle *flow_rule;
c5bb1730 1558 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1559 void *misc;
1560
1b9a07ee 1561 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1562 if (!spec) {
fed9ce22
OG		 1563 flow_rule = ERR_PTR(-ENOMEM);
1564 goto out;
1565 }
1566
a5641cb5
JL		 1567 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1568 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1569 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1570 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1571
a5641cb5 1572 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1573 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1574 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1575
a5641cb5
JL		 1576 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1577 } else {
1578 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1579 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1580
1581 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1582 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1583
1584 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1585 }
fed9ce22 1586
66958ed9 1587 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1588 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1589 &flow_act, dest, 1);
fed9ce22
OG		 1590 if (IS_ERR(flow_rule)) {
1591 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1592 goto out;
1593 }
1594
1595out:
c5bb1730 1596 kvfree(spec);
fed9ce22
OG		 1597 return flow_rule;
1598}
feae9087 1599
bf3347c4 1600
cc617ced
PP		 1601static int mlx5_eswitch_inline_mode_get(const struct mlx5_eswitch *esw, u8 *mode)
1602{
1603 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1604 struct mlx5_core_dev *dev = esw->dev;
1605 int vport;
1606
1607 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1608 return -EOPNOTSUPP;
1609
1610 if (esw->mode == MLX5_ESWITCH_NONE)
1611 return -EOPNOTSUPP;
1612
1613 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1614 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1615 mlx5_mode = MLX5_INLINE_MODE_NONE;
1616 goto out;
1617 case MLX5_CAP_INLINE_MODE_L2:
1618 mlx5_mode = MLX5_INLINE_MODE_L2;
1619 goto out;
1620 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1621 goto query_vports;
1622 }
1623
1624query_vports:
1625 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
1626 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
1627 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
1628 if (prev_mlx5_mode != mlx5_mode)
1629 return -EINVAL;
1630 prev_mlx5_mode = mlx5_mode;
1631 }
1632
1633out:
1634 *mode = mlx5_mode;
1635 return 0;
e08a6832 1636}
bf3347c4 1637
11b717d6
PB		 1638static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1639{
1640 struct mlx5_esw_offload *offloads = &esw->offloads;
1641
60acc105
PB		 1642 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1643 return;
1644
6724e66b 1645 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 1646 mlx5_destroy_flow_group(offloads->restore_group);
1647 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
1648}
1649
1650static int esw_create_restore_table(struct mlx5_eswitch *esw)
1651{
d65dbedf 1652 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 1653 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1654 struct mlx5_flow_table_attr ft_attr = {};
1655 struct mlx5_core_dev *dev = esw->dev;
1656 struct mlx5_flow_namespace *ns;
6724e66b 1657 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 1658 void *match_criteria, *misc;
1659 struct mlx5_flow_table *ft;
1660 struct mlx5_flow_group *g;
1661 u32 *flow_group_in;
1662 int err = 0;
1663
60acc105
PB		 1664 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1665 return 0;
1666
11b717d6
PB		 1667 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1668 if (!ns) {
1669 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1670 return -EOPNOTSUPP;
1671 }
1672
1673 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1674 if (!flow_group_in) {
1675 err = -ENOMEM;
1676 goto out_free;
1677 }
1678
1679 ft_attr.max_fte = 1 << ESW_CHAIN_TAG_METADATA_BITS;
1680 ft = mlx5_create_flow_table(ns, &ft_attr);
1681 if (IS_ERR(ft)) {
1682 err = PTR_ERR(ft);
1683 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
1684 err);
1685 goto out_free;
1686 }
1687
11b717d6
PB		 1688 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1689 match_criteria);
1690 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
1691 misc_parameters_2);
1692
1693 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1694 ESW_CHAIN_TAG_METADATA_MASK);
1695 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1696 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1697 ft_attr.max_fte - 1);
1698 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1699 MLX5_MATCH_MISC_PARAMETERS_2);
1700 g = mlx5_create_flow_group(ft, flow_group_in);
1701 if (IS_ERR(g)) {
1702 err = PTR_ERR(g);
1703 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
1704 err);
1705 goto err_group;
1706 }
1707
6724e66b
PB		 1708 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
1709 MLX5_SET(copy_action_in, modact, src_field,
1710 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
1711 MLX5_SET(copy_action_in, modact, dst_field,
1712 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
1713 mod_hdr = mlx5_modify_header_alloc(esw->dev,
1714 MLX5_FLOW_NAMESPACE_KERNEL, 1,
1715 modact);
1716 if (IS_ERR(mod_hdr)) {
e9864539 1717 err = PTR_ERR(mod_hdr);
6724e66b
PB		 1718 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
1719 err);
6724e66b
PB		 1720 goto err_mod_hdr;
1721 }
1722
11b717d6
PB		 1723 esw->offloads.ft_offloads_restore = ft;
1724 esw->offloads.restore_group = g;
6724e66b 1725 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 1726
c8508713
RD		 1727 kvfree(flow_group_in);
1728
11b717d6
PB		 1729 return 0;
1730
6724e66b
PB		 1731err_mod_hdr:
1732 mlx5_destroy_flow_group(g);
11b717d6
PB		 1733err_group:
1734 mlx5_destroy_flow_table(ft);
1735out_free:
1736 kvfree(flow_group_in);
1737
1738 return err;
cc617ced
PP		 1739}
1740
db7ff19e
EB		 1741static int esw_offloads_start(struct mlx5_eswitch *esw,
1742 struct netlink_ext_ack *extack)
c930a3ad 1743{
062f4bf4 1744 int err, err1;
c930a3ad 1745
8e0aa4bc
PP		 1746 mlx5_eswitch_disable_locked(esw, false);
1747 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
1748 esw->dev->priv.sriov.num_vfs);
6c419ba8 1749 if (err) {
8c98ee77
EB		 1750 NL_SET_ERR_MSG_MOD(extack,
1751 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 1752 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
1753 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 1754 if (err1) {
1755 NL_SET_ERR_MSG_MOD(extack,
1756 "Failed setting eswitch back to legacy");
1757 }
6c419ba8 1758 }
bffaa916
RD		 1759 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1760 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 1761 &esw->offloads.inline_mode)) {
1762 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 1763 NL_SET_ERR_MSG_MOD(extack,
1764 "Inline mode is different between vports");
bffaa916
RD		 1765 }
1766 }
c930a3ad
OG		 1767 return err;
1768}
1769
e8d31c4d
MB		 1770void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1771{
1772 kfree(esw->offloads.vport_reps);
1773}
1774
1775int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1776{
2752b823 1777 int total_vports = esw->total_vports;
e8d31c4d 1778 struct mlx5_eswitch_rep *rep;
d6518db2 1779 int vport_index;
ef2e4094 1780 u8 rep_type;
e8d31c4d 1781
2aca1787 1782 esw->offloads.vport_reps = kcalloc(total_vports,
e8d31c4d
MB		 1783 sizeof(struct mlx5_eswitch_rep),
1784 GFP_KERNEL);
1785 if (!esw->offloads.vport_reps)
1786 return -ENOMEM;
1787
d6518db2
BW		 1788 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1789 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
2f69e591 1790 rep->vport_index = vport_index;
f121e0ea
BW		 1791
1792 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
8693115a 1793 atomic_set(&rep->rep_data[rep_type].state,
6f4e0219 1794 REP_UNREGISTERED);
e8d31c4d
MB		 1795 }
1796
e8d31c4d
MB		 1797 return 0;
1798}
1799
c9b99abc
BW		 1800static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1801 struct mlx5_eswitch_rep *rep, u8 rep_type)
1802{
8693115a 1803 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 1804 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 1805 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 1806}
1807
d7f33a45
VP		 1808static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
1809{
1810 struct mlx5_eswitch_rep *rep;
1811 int i;
1812
1813 mlx5_esw_for_each_sf_rep(esw, i, rep)
1814 __esw_offloads_unload_rep(esw, rep, rep_type);
1815}
1816
4110fc59 1817static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 1818{
1819 struct mlx5_eswitch_rep *rep;
4110fc59
BW		 1820 int i;
1821
d7f33a45
VP		 1822 __unload_reps_sf_vport(esw, rep_type);
1823
4110fc59
BW		 1824 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, esw->esw_funcs.num_vfs)
1825 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 1826
81cd229c
BW		 1827 if (mlx5_ecpf_vport_exists(esw->dev)) {
1828 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1829 __esw_offloads_unload_rep(esw, rep, rep_type);
1830 }
1831
1832 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1833 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1834 __esw_offloads_unload_rep(esw, rep, rep_type);
1835 }
1836
879c8f84 1837 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 1838 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1839}
1840
d970812b 1841int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 1842{
c2d7712c
BW		 1843 struct mlx5_eswitch_rep *rep;
1844 int rep_type;
a4b97ab4
MB		 1845 int err;
1846
c2d7712c
BW		 1847 rep = mlx5_eswitch_get_rep(esw, vport_num);
1848 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1849 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1850 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1851 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1852 if (err)
1853 goto err_reps;
1854 }
1855
1856 return 0;
a4b97ab4
MB		 1857
1858err_reps:
c2d7712c
BW		 1859 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
1860 for (--rep_type; rep_type >= 0; rep_type--)
1861 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1862 return err;
1863}
1864
d970812b 1865void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 1866{
1867 struct mlx5_eswitch_rep *rep;
1868 int rep_type;
1869
c2d7712c
BW		 1870 rep = mlx5_eswitch_get_rep(esw, vport_num);
1871 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
1872 __esw_offloads_unload_rep(esw, rep, rep_type);
1873}
1874
38679b5a
PP		 1875int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
1876{
1877 int err;
1878
1879 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1880 return 0;
1881
c7eddc60
PP		 1882 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
1883 if (err)
1884 return err;
1885
38679b5a 1886 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 1887 if (err)
1888 goto load_err;
1889 return err;
1890
1891load_err:
1892 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 1893 return err;
1894}
1895
1896void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
1897{
1898 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1899 return;
1900
1901 mlx5_esw_offloads_rep_unload(esw, vport_num);
c7eddc60 1902 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 1903}
1904
ac004b83
RD		 1905#define ESW_OFFLOADS_DEVCOM_PAIR (0)
1906#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1907
1908static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1909 struct mlx5_eswitch *peer_esw)
1910{
1911 int err;
1912
1913 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1914 if (err)
1915 return err;
1916
1917 return 0;
1918}
1919
1920static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1921{
d956873f 1922#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 1923 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 1924#endif
ac004b83
RD		 1925 esw_del_fdb_peer_miss_rules(esw);
1926}
1927
8463daf1
MG		 1928static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
1929 struct mlx5_eswitch *peer_esw,
1930 bool pair)
1931{
1932 struct mlx5_flow_root_namespace *peer_ns;
1933 struct mlx5_flow_root_namespace *ns;
1934 int err;
1935
1936 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
1937 ns = esw->dev->priv.steering->fdb_root_ns;
1938
1939 if (pair) {
1940 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
1941 if (err)
1942 return err;
1943
e53e6655 1944 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 1945 if (err) {
1946 mlx5_flow_namespace_set_peer(ns, NULL);
1947 return err;
1948 }
1949 } else {
1950 mlx5_flow_namespace_set_peer(ns, NULL);
1951 mlx5_flow_namespace_set_peer(peer_ns, NULL);
1952 }
1953
1954 return 0;
1955}
1956
ac004b83
RD		 1957static int mlx5_esw_offloads_devcom_event(int event,
1958 void *my_data,
1959 void *event_data)
1960{
1961 struct mlx5_eswitch *esw = my_data;
ac004b83 1962 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 1963 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 1964 int err;
1965
1966 switch (event) {
1967 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 1968 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1969 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1970 break;
1971
8463daf1 1972 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 1973 if (err)
1974 goto err_out;
8463daf1
MG		 1975 err = mlx5_esw_offloads_pair(esw, peer_esw);
1976 if (err)
1977 goto err_peer;
ac004b83
RD		 1978
1979 err = mlx5_esw_offloads_pair(peer_esw, esw);
1980 if (err)
1981 goto err_pair;
1982
1983 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1984 break;
1985
1986 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1987 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1988 break;
1989
1990 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1991 mlx5_esw_offloads_unpair(peer_esw);
1992 mlx5_esw_offloads_unpair(esw);
8463daf1 1993 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1994 break;
1995 }
1996
1997 return 0;
1998
1999err_pair:
2000 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 2001err_peer:
2002 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2003err_out:
2004 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2005 event, err);
2006 return err;
2007}
2008
2009static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2010{
2011 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2012
04de7dda
RD		 2013 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2014 mutex_init(&esw->offloads.peer_mutex);
2015
ac004b83
RD		 2016 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2017 return;
2018
2019 mlx5_devcom_register_component(devcom,
2020 MLX5_DEVCOM_ESW_OFFLOADS,
2021 mlx5_esw_offloads_devcom_event,
2022 esw);
2023
2024 mlx5_devcom_send_event(devcom,
2025 MLX5_DEVCOM_ESW_OFFLOADS,
2026 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2027}
2028
2029static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2030{
2031 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2032
2033 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2034 return;
2035
2036 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2037 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2038
2039 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2040}
2041
92ab1eb3
JL		 2042static bool
2043esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
2044{
2045 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2046 return false;
2047
2048 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2049 MLX5_FDB_TO_VPORT_REG_C_0))
2050 return false;
2051
2052 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2053 return false;
2054
2055 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2056 mlx5_ecpf_vport_exists(esw->dev))
2057 return false;
2058
2059 return true;
2060}
2061
133dcfc5
VP		 2062u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2063{
7cd7becd 2064 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2065 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2066 u32 pf_num;
133dcfc5
VP		 2067 int id;
2068
7cd7becd 2069 /* Only 4 bits of pf_num */
2070 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2071 if (pf_num > max_pf_num)
2072 return 0;
133dcfc5 2073
7cd7becd 2074 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2075 /* Use only non-zero vport_id (1-4095) for all PF's */
2076 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2077 if (id < 0)
2078 return 0;
2079 id = (pf_num << ESW_VPORT_BITS) | id;
2080 return id;
133dcfc5
VP		 2081}
2082
2083void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2084{
7cd7becd 2085 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2086
2087 /* Metadata contains only 12 bits of actual ida id */
2088 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2089}
2090
2091static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2092 struct mlx5_vport *vport)
2093{
133dcfc5
VP		 2094 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2095 vport->metadata = vport->default_metadata;
2096 return vport->metadata ? 0 : -ENOSPC;
2097}
2098
2099static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2100 struct mlx5_vport *vport)
2101{
406493a5 2102 if (!vport->default_metadata)
133dcfc5
VP		 2103 return;
2104
2105 WARN_ON(vport->metadata != vport->default_metadata);
2106 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2107}
2108
fc99c3d6
VP		 2109static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2110{
2111 struct mlx5_vport *vport;
2112 int i;
2113
2114 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2115 return;
2116
2117 mlx5_esw_for_all_vports_reverse(esw, i, vport)
2118 esw_offloads_vport_metadata_cleanup(esw, vport);
2119}
2120
2121static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2122{
2123 struct mlx5_vport *vport;
2124 int err;
2125 int i;
2126
2127 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2128 return 0;
2129
2130 mlx5_esw_for_all_vports(esw, i, vport) {
2131 err = esw_offloads_vport_metadata_setup(esw, vport);
2132 if (err)
2133 goto metadata_err;
2134 }
2135
2136 return 0;
2137
2138metadata_err:
2139 esw_offloads_metadata_uninit(esw);
2140 return err;
2141}
2142
748da30b 2143int
89a0f1fb
PP		 2144esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2145 struct mlx5_vport *vport)
7445cfb1 2146{
7445cfb1
JL		 2147 int err;
2148
07bab950 2149 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2150 if (err)
fc99c3d6 2151 return err;
7445cfb1 2152
2c40db2f
PP		 2153 err = esw_acl_egress_ofld_setup(esw, vport);
2154 if (err)
2155 goto egress_err;
07bab950
VP		 2156
2157 return 0;
2158
2159egress_err:
2160 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2161 return err;
2162}
18486737 2163
748da30b 2164void
89a0f1fb
PP		 2165esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2166 struct mlx5_vport *vport)
2167{
ea651a86 2168 esw_acl_egress_ofld_cleanup(vport);
07bab950 2169 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2170}
7445cfb1 2171
748da30b 2172static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2173{
2174 struct mlx5_vport *vport;
18486737 2175
748da30b 2176 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
4e9a9ef7 2177 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2178}
2179
748da30b 2180static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2181{
786ef904 2182 struct mlx5_vport *vport;
7445cfb1 2183
748da30b
VP		 2184 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2185 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2186}
2187
062f4bf4 2188static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a
MB		 2189{
2190 int err;
2191
5c1d260e 2192 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2193 mutex_init(&esw->fdb_table.offloads.vports.lock);
2194 hash_init(esw->fdb_table.offloads.vports.table);
e52c2802 2195
748da30b 2196 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2197 if (err)
f8d1edda 2198 goto create_acl_err;
18486737 2199
8d6bd3c3 2200 err = esw_create_offloads_table(esw);
c930a3ad 2201 if (err)
11b717d6 2202 goto create_offloads_err;
c930a3ad 2203
11b717d6 2204 err = esw_create_restore_table(esw);
c930a3ad 2205 if (err)
11b717d6
PB		 2206 goto create_restore_err;
2207
0da3c12d 2208 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2209 if (err)
2210 goto create_fdb_err;
c930a3ad 2211
8d6bd3c3 2212 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2213 if (err)
2214 goto create_fg_err;
2215
2216 return 0;
2217
2218create_fg_err:
1967ce6e 2219 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2220create_fdb_err:
11b717d6
PB		 2221 esw_destroy_restore_table(esw);
2222create_restore_err:
2223 esw_destroy_offloads_table(esw);
2224create_offloads_err:
748da30b 2225 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda
PP		 2226create_acl_err:
2227 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2228 return err;
2229}
2230
eca8cc38
BW		 2231static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2232{
2233 esw_destroy_vport_rx_group(esw);
eca8cc38 2234 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2235 esw_destroy_restore_table(esw);
2236 esw_destroy_offloads_table(esw);
748da30b 2237 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2238 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2239}
2240
7e736f9a
PP		 2241static void
2242esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2243{
5ccf2770 2244 bool host_pf_disabled;
7e736f9a 2245 u16 new_num_vfs;
a3888f33 2246
7e736f9a
PP		 2247 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2248 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2249 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2250 host_params_context.host_pf_disabled);
a3888f33 2251
7e736f9a
PP		 2252 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2253 return;
a3888f33
BW		 2254
2255 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2256 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2257 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2258 } else {
7e736f9a 2259 int err;
a3888f33 2260
23bb50cf
BW		 2261 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2262 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2263 if (err)
7e736f9a 2264 return;
a3888f33 2265 }
7e736f9a 2266 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2267}
2268
7e736f9a 2269static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2270{
7e736f9a
PP		 2271 struct mlx5_host_work *host_work;
2272 struct mlx5_eswitch *esw;
dd28087c 2273 const u32 *out;
ac35dcd6 2274
7e736f9a
PP		 2275 host_work = container_of(work, struct mlx5_host_work, work);
2276 esw = host_work->esw;
a3888f33 2277
dd28087c
PP		 2278 out = mlx5_esw_query_functions(esw->dev);
2279 if (IS_ERR(out))
7e736f9a 2280 goto out;
a3888f33 2281
7e736f9a 2282 esw_vfs_changed_event_handler(esw, out);
dd28087c 2283 kvfree(out);
a3888f33 2284out:
ac35dcd6
VP		 2285 kfree(host_work);
2286}
2287
16fff98a 2288int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2289{
cd56f929 2290 struct mlx5_esw_functions *esw_funcs;
a3888f33 2291 struct mlx5_host_work *host_work;
a3888f33
BW		 2292 struct mlx5_eswitch *esw;
2293
2294 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2295 if (!host_work)
2296 return NOTIFY_DONE;
2297
cd56f929
VP		 2298 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2299 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2300
2301 host_work->esw = esw;
2302
062f4bf4 2303 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2304 queue_work(esw->work_queue, &host_work->work);
2305
2306 return NOTIFY_OK;
2307}
2308
a53cf949
PP		 2309static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2310{
2311 const u32 *query_host_out;
2312
2313 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2314 return 0;
2315
2316 query_host_out = mlx5_esw_query_functions(esw->dev);
2317 if (IS_ERR(query_host_out))
2318 return PTR_ERR(query_host_out);
2319
2320 /* Mark non local controller with non zero controller number. */
2321 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2322 host_params_context.host_number);
2323 kvfree(query_host_out);
2324 return 0;
2325}
2326
5896b972 2327int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2328{
3b83b6c2
DL		 2329 struct mlx5_vport *vport;
2330 int err, i;
eca8cc38 2331
9a64144d
MG		 2332 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2333 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2334 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2335 else
2336 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2337
2bb72e7e 2338 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2339 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2340
a53cf949
PP		 2341 err = mlx5_esw_host_number_init(esw);
2342 if (err)
cd1ef966 2343 goto err_metadata;
a53cf949 2344
cd1ef966 2345 if (esw_check_vport_match_metadata_supported(esw))
4e9a9ef7
VP		 2346 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2347
fc99c3d6
VP		 2348 err = esw_offloads_metadata_init(esw);
2349 if (err)
2350 goto err_metadata;
2351
332bd3a5
PP		 2352 err = esw_set_passing_vport_metadata(esw, true);
2353 if (err)
2354 goto err_vport_metadata;
c1286050 2355
7983a675
PB		 2356 err = esw_offloads_steering_init(esw);
2357 if (err)
2358 goto err_steering_init;
2359
3b83b6c2
DL		 2360 /* Representor will control the vport link state */
2361 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2362 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2363
c2d7712c
BW		 2364 /* Uplink vport rep must load first. */
2365 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2366 if (err)
c2d7712c 2367 goto err_uplink;
c1286050 2368
c2d7712c 2369 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2370 if (err)
c2d7712c 2371 goto err_vports;
eca8cc38
BW		 2372
2373 esw_offloads_devcom_init(esw);
a3888f33 2374
eca8cc38
BW		 2375 return 0;
2376
925a6acc 2377err_vports:
c2d7712c
BW		 2378 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2379err_uplink:
7983a675 2380 esw_offloads_steering_cleanup(esw);
79949985
PP		 2381err_steering_init:
2382 esw_set_passing_vport_metadata(esw, false);
7983a675 2383err_vport_metadata:
fc99c3d6
VP		 2384 esw_offloads_metadata_uninit(esw);
2385err_metadata:
4e9a9ef7 2386 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2387 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2388 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2389 return err;
2390}
2391
db7ff19e
EB		 2392static int esw_offloads_stop(struct mlx5_eswitch *esw,
2393 struct netlink_ext_ack *extack)
c930a3ad 2394{
062f4bf4 2395 int err, err1;
c930a3ad 2396
8e0aa4bc
PP		 2397 mlx5_eswitch_disable_locked(esw, false);
2398 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2399 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2400 if (err) {
8c98ee77 2401 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2402 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2403 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2404 if (err1) {
2405 NL_SET_ERR_MSG_MOD(extack,
2406 "Failed setting eswitch back to offloads");
2407 }
6c419ba8 2408 }
c930a3ad
OG		 2409
2410 return err;
2411}
2412
5896b972 2413void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2414{
ac004b83 2415 esw_offloads_devcom_cleanup(esw);
5896b972 2416 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2417 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2418 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2419 esw_offloads_steering_cleanup(esw);
fc99c3d6 2420 esw_offloads_metadata_uninit(esw);
4e9a9ef7 2421 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2422 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2423 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2424 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2425}
2426
ef78618b 2427static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2428{
2429 switch (mode) {
2430 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2431 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2432 break;
2433 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2434 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2435 break;
2436 default:
2437 return -EINVAL;
2438 }
2439
2440 return 0;
2441}
2442
ef78618b
OG		 2443static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2444{
2445 switch (mlx5_mode) {
f6455de0 2446 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2447 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2448 break;
f6455de0 2449 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2450 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2451 break;
2452 default:
2453 return -EINVAL;
2454 }
2455
2456 return 0;
2457}
2458
bffaa916
RD		 2459static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2460{
2461 switch (mode) {
2462 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2463 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2464 break;
2465 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2466 *mlx5_mode = MLX5_INLINE_MODE_L2;
2467 break;
2468 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2469 *mlx5_mode = MLX5_INLINE_MODE_IP;
2470 break;
2471 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2472 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2473 break;
2474 default:
2475 return -EINVAL;
2476 }
2477
2478 return 0;
2479}
2480
2481static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2482{
2483 switch (mlx5_mode) {
2484 case MLX5_INLINE_MODE_NONE:
2485 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2486 break;
2487 case MLX5_INLINE_MODE_L2:
2488 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2489 break;
2490 case MLX5_INLINE_MODE_IP:
2491 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2492 break;
2493 case MLX5_INLINE_MODE_TCP_UDP:
2494 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2495 break;
2496 default:
2497 return -EINVAL;
2498 }
2499
2500 return 0;
2501}
2502
ae24432c
PP		 2503static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2504{
2505 /* devlink commands in NONE eswitch mode are currently supported only
2506 * on ECPF.
2507 */
2508 return (esw->mode == MLX5_ESWITCH_NONE &&
2509 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2510}
2511
db7ff19e
EB		 2512int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2513 struct netlink_ext_ack *extack)
9d1cef19 2514{
9d1cef19 2515 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2516 struct mlx5_eswitch *esw;
ea2128fd 2517 int err = 0;
9d1cef19 2518
bd939753
PP		 2519 esw = mlx5_devlink_eswitch_get(devlink);
2520 if (IS_ERR(esw))
2521 return PTR_ERR(esw);
9d1cef19 2522
ef78618b 2523 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2524 return -EINVAL;
2525
8e0aa4bc 2526 mutex_lock(&esw->mode_lock);
8e0aa4bc 2527 cur_mlx5_mode = esw->mode;
c930a3ad 2528 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 2529 goto unlock;
c930a3ad
OG		 2530
2531 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 2532 err = esw_offloads_start(esw, extack);
c930a3ad 2533 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 2534 err = esw_offloads_stop(esw, extack);
c930a3ad 2535 else
8e0aa4bc
PP		 2536 err = -EINVAL;
2537
2538unlock:
2539 mutex_unlock(&esw->mode_lock);
2540 return err;
feae9087
OG		 2541}
2542
2543int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2544{
bd939753 2545 struct mlx5_eswitch *esw;
9d1cef19 2546 int err;
c930a3ad 2547
bd939753
PP		 2548 esw = mlx5_devlink_eswitch_get(devlink);
2549 if (IS_ERR(esw))
2550 return PTR_ERR(esw);
c930a3ad 2551
8e0aa4bc 2552 mutex_lock(&esw->mode_lock);
bd939753 2553 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 2554 if (err)
8e0aa4bc 2555 goto unlock;
ae24432c 2556
8e0aa4bc
PP		 2557 err = esw_mode_to_devlink(esw->mode, mode);
2558unlock:
2559 mutex_unlock(&esw->mode_lock);
2560 return err;
feae9087 2561}
127ea380 2562
db7ff19e
EB		 2563int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2564 struct netlink_ext_ack *extack)
bffaa916
RD		 2565{
2566 struct mlx5_core_dev *dev = devlink_priv(devlink);
db68cc56 2567 int err, vport, num_vport;
bd939753 2568 struct mlx5_eswitch *esw;
bffaa916
RD		 2569 u8 mlx5_mode;
2570
bd939753
PP		 2571 esw = mlx5_devlink_eswitch_get(devlink);
2572 if (IS_ERR(esw))
2573 return PTR_ERR(esw);
bffaa916 2574
8e0aa4bc 2575 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2576 err = eswitch_devlink_esw_mode_check(esw);
2577 if (err)
8e0aa4bc 2578 goto out;
ae24432c 2579
c415f704
OG		 2580 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2581 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2582 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 2583 goto out;
c8b838d1 2584 fallthrough;
c415f704 2585 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 2586 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 2587 err = -EOPNOTSUPP;
2588 goto out;
c415f704
OG		 2589 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2590 break;
2591 }
bffaa916 2592
525e84be 2593 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2594 NL_SET_ERR_MSG_MOD(extack,
2595 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 2596 err = -EOPNOTSUPP;
2597 goto out;
375f51e2
RD		 2598 }
2599
bffaa916
RD		 2600 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2601 if (err)
2602 goto out;
2603
411ec9e0 2604 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
bffaa916
RD		 2605 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2606 if (err) {
8c98ee77
EB		 2607 NL_SET_ERR_MSG_MOD(extack,
2608 "Failed to set min inline on vport");
bffaa916
RD		 2609 goto revert_inline_mode;
2610 }
2611 }
2612
2613 esw->offloads.inline_mode = mlx5_mode;
8e0aa4bc 2614 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2615 return 0;
2616
2617revert_inline_mode:
db68cc56 2618 num_vport = --vport;
411ec9e0 2619 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
bffaa916
RD		 2620 mlx5_modify_nic_vport_min_inline(dev,
2621 vport,
2622 esw->offloads.inline_mode);
2623out:
8e0aa4bc 2624 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2625 return err;
2626}
2627
2628int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2629{
bd939753 2630 struct mlx5_eswitch *esw;
9d1cef19 2631 int err;
bffaa916 2632
bd939753
PP		 2633 esw = mlx5_devlink_eswitch_get(devlink);
2634 if (IS_ERR(esw))
2635 return PTR_ERR(esw);
bffaa916 2636
8e0aa4bc 2637 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2638 err = eswitch_devlink_esw_mode_check(esw);
2639 if (err)
8e0aa4bc 2640 goto unlock;
ae24432c 2641
8e0aa4bc
PP		 2642 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2643unlock:
2644 mutex_unlock(&esw->mode_lock);
2645 return err;
bffaa916
RD		 2646}
2647
98fdbea5
LR		 2648int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2649 enum devlink_eswitch_encap_mode encap,
db7ff19e 2650 struct netlink_ext_ack *extack)
7768d197
RD		 2651{
2652 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 2653 struct mlx5_eswitch *esw;
7768d197
RD		 2654 int err;
2655
bd939753
PP		 2656 esw = mlx5_devlink_eswitch_get(devlink);
2657 if (IS_ERR(esw))
2658 return PTR_ERR(esw);
7768d197 2659
8e0aa4bc 2660 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2661 err = eswitch_devlink_esw_mode_check(esw);
2662 if (err)
8e0aa4bc 2663 goto unlock;
ae24432c 2664
7768d197 2665 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 2666 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 2667 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
2668 err = -EOPNOTSUPP;
2669 goto unlock;
2670 }
7768d197 2671
8e0aa4bc
PP		 2672 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
2673 err = -EOPNOTSUPP;
2674 goto unlock;
2675 }
7768d197 2676
f6455de0 2677 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 2678 esw->offloads.encap = encap;
8e0aa4bc 2679 goto unlock;
7768d197
RD		 2680 }
2681
2682 if (esw->offloads.encap == encap)
8e0aa4bc 2683 goto unlock;
7768d197 2684
525e84be 2685 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2686 NL_SET_ERR_MSG_MOD(extack,
2687 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 2688 err = -EOPNOTSUPP;
2689 goto unlock;
7768d197
RD		 2690 }
2691
e52c2802 2692 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 2693
2694 esw->offloads.encap = encap;
e52c2802 2695
0da3c12d 2696 err = esw_create_offloads_fdb_tables(esw);
e52c2802 2697
7768d197 2698 if (err) {
8c98ee77
EB		 2699 NL_SET_ERR_MSG_MOD(extack,
2700 "Failed re-creating fast FDB table");
7768d197 2701 esw->offloads.encap = !encap;
0da3c12d 2702 (void)esw_create_offloads_fdb_tables(esw);
7768d197 2703 }
e52c2802 2704
8e0aa4bc
PP		 2705unlock:
2706 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2707 return err;
2708}
2709
98fdbea5
LR		 2710int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2711 enum devlink_eswitch_encap_mode *encap)
7768d197 2712{
bd939753 2713 struct mlx5_eswitch *esw;
9d1cef19 2714 int err;
7768d197 2715
bd939753
PP		 2716 esw = mlx5_devlink_eswitch_get(devlink);
2717 if (IS_ERR(esw))
2718 return PTR_ERR(esw);
2719
7768d197 2720
8e0aa4bc 2721 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2722 err = eswitch_devlink_esw_mode_check(esw);
2723 if (err)
8e0aa4bc 2724 goto unlock;
ae24432c 2725
7768d197 2726 *encap = esw->offloads.encap;
8e0aa4bc
PP		 2727unlock:
2728 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2729 return 0;
2730}
2731
c2d7712c
BW		 2732static bool
2733mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
2734{
2735 /* Currently, only ECPF based device has representor for host PF. */
2736 if (vport_num == MLX5_VPORT_PF &&
2737 !mlx5_core_is_ecpf_esw_manager(esw->dev))
2738 return false;
2739
2740 if (vport_num == MLX5_VPORT_ECPF &&
2741 !mlx5_ecpf_vport_exists(esw->dev))
2742 return false;
2743
2744 return true;
2745}
2746
f8e8fa02 2747void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 2748 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 2749 u8 rep_type)
127ea380 2750{
8693115a 2751 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02
BW		 2752 struct mlx5_eswitch_rep *rep;
2753 int i;
9deb2241 2754
8693115a 2755 esw->offloads.rep_ops[rep_type] = ops;
f8e8fa02 2756 mlx5_esw_for_all_reps(esw, i, rep) {
c2d7712c
BW		 2757 if (likely(mlx5_eswitch_vport_has_rep(esw, i))) {
2758 rep_data = &rep->rep_data[rep_type];
2759 atomic_set(&rep_data->state, REP_REGISTERED);
2760 }
f8e8fa02 2761 }
127ea380 2762}
f8e8fa02 2763EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 2764
f8e8fa02 2765void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 2766{
cb67b832 2767 struct mlx5_eswitch_rep *rep;
f8e8fa02 2768 int i;
cb67b832 2769
f6455de0 2770 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 2771 __unload_reps_all_vport(esw, rep_type);
127ea380 2772
f8e8fa02 2773 mlx5_esw_for_all_reps(esw, i, rep)
8693115a 2774 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 2775}
f8e8fa02 2776EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 2777
a4b97ab4 2778void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 2779{
726293f1
HHZ		 2780 struct mlx5_eswitch_rep *rep;
2781
879c8f84 2782 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 2783 return rep->rep_data[rep_type].priv;
726293f1 2784}
22215908
MB		 2785
2786void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 2787 u16 vport,
22215908
MB		 2788 u8 rep_type)
2789{
22215908
MB		 2790 struct mlx5_eswitch_rep *rep;
2791
879c8f84 2792 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 2793
8693115a
PP		 2794 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2795 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2796 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 2797 return NULL;
2798}
57cbd893 2799EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 2800
2801void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2802{
879c8f84 2803 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 2804}
57cbd893
MB		 2805EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2806
2807struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 2808 u16 vport)
57cbd893 2809{
879c8f84 2810 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 2811}
2812EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c
PP		 2813
2814bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2815{
2816 return vport_num >= MLX5_VPORT_FIRST_VF &&
2817 vport_num <= esw->dev->priv.sriov.max_vfs;
2818}
7445cfb1 2819
5b7cb745
PB		 2820bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
2821{
2822 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
2823}
2824EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
2825
7445cfb1
JL		 2826bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2827{
2828 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2829}
2830EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2831
0f0d3827 2832u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 2833 u16 vport_num)
2834{
133dcfc5 2835 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 2836
133dcfc5
VP		 2837 if (WARN_ON_ONCE(IS_ERR(vport)))
2838 return 0;
0f0d3827 2839
133dcfc5 2840 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 2841}
2842EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 2843
2844int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
2845 u16 vport_num, u32 sfnum)
2846{
2847 int err;
2848
2849 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
2850 if (err)
2851 return err;
2852
2853 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, sfnum);
2854 if (err)
2855 goto devlink_err;
2856
2857 err = mlx5_esw_offloads_rep_load(esw, vport_num);
2858 if (err)
2859 goto rep_err;
2860 return 0;
2861
2862rep_err:
2863 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
2864devlink_err:
2865 mlx5_esw_vport_disable(esw, vport_num);
2866 return err;
2867}
2868
2869void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
2870{
2871 mlx5_esw_offloads_rep_unload(esw, vport_num);
2872 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
2873 mlx5_esw_vport_disable(esw, vport_num);
2874}
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