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net/mlx5: E-switch, Move devlink eswitch ports closer to eswitch
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
ea651a86 41#include "esw/acl/ofld.h"
80f09dfc 42#include "rdma.h"
e52c2802
PB		 43#include "en.h"
44#include "fs_core.h"
ac004b83 45#include "lib/devcom.h"
a3888f33 46#include "lib/eq.h"
ae430332 47#include "lib/fs_chains.h"
c620b772 48#include "en_tc.h"
69697b6e 49
cd7e4186
BW		 50/* There are two match-all miss flows, one for unicast dst mac and
51 * one for multicast.
52 */
53#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 54#define UPLINK_REP_INDEX 0
55
96e32687
EC		 56/* Per vport tables */
57
58#define MLX5_ESW_VPORT_TABLE_SIZE 128
59
60/* This struct is used as a key to the hash table and we need it to be packed
61 * so hash result is consistent
62 */
63struct mlx5_vport_key {
64 u32 chain;
65 u16 prio;
66 u16 vport;
67 u16 vhca_id;
68} __packed;
69
c620b772
AL		 70struct mlx5_vport_tbl_attr {
71 u16 chain;
72 u16 prio;
73 u16 vport;
74};
75
96e32687
EC		 76struct mlx5_vport_table {
77 struct hlist_node hlist;
78 struct mlx5_flow_table *fdb;
79 u32 num_rules;
80 struct mlx5_vport_key key;
81};
82
87dac697
JL		 83#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
84
96e32687
EC		 85static struct mlx5_flow_table *
86esw_vport_tbl_create(struct mlx5_eswitch *esw, struct mlx5_flow_namespace *ns)
87{
88 struct mlx5_flow_table_attr ft_attr = {};
89 struct mlx5_flow_table *fdb;
90
87dac697 91 ft_attr.autogroup.max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS;
96e32687
EC		 92 ft_attr.max_fte = MLX5_ESW_VPORT_TABLE_SIZE;
93 ft_attr.prio = FDB_PER_VPORT;
94 fdb = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
95 if (IS_ERR(fdb)) {
96 esw_warn(esw->dev, "Failed to create per vport FDB Table err %ld\n",
97 PTR_ERR(fdb));
98 }
99
100 return fdb;
101}
102
103static u32 flow_attr_to_vport_key(struct mlx5_eswitch *esw,
c620b772 104 struct mlx5_vport_tbl_attr *attr,
96e32687
EC		 105 struct mlx5_vport_key *key)
106{
c620b772 107 key->vport = attr->vport;
96e32687
EC		 108 key->chain = attr->chain;
109 key->prio = attr->prio;
110 key->vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
111 return jhash(key, sizeof(*key), 0);
112}
113
114/* caller must hold vports.lock */
115static struct mlx5_vport_table *
116esw_vport_tbl_lookup(struct mlx5_eswitch *esw, struct mlx5_vport_key *skey, u32 key)
117{
118 struct mlx5_vport_table *e;
119
120 hash_for_each_possible(esw->fdb_table.offloads.vports.table, e, hlist, key)
121 if (!memcmp(&e->key, skey, sizeof(*skey)))
122 return e;
123
124 return NULL;
125}
126
127static void
c620b772 128esw_vport_tbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr)
96e32687
EC		 129{
130 struct mlx5_vport_table *e;
131 struct mlx5_vport_key key;
132 u32 hkey;
133
134 mutex_lock(&esw->fdb_table.offloads.vports.lock);
135 hkey = flow_attr_to_vport_key(esw, attr, &key);
136 e = esw_vport_tbl_lookup(esw, &key, hkey);
137 if (!e || --e->num_rules)
138 goto out;
139
140 hash_del(&e->hlist);
141 mlx5_destroy_flow_table(e->fdb);
142 kfree(e);
143out:
144 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
145}
146
147static struct mlx5_flow_table *
c620b772 148esw_vport_tbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr)
96e32687
EC		 149{
150 struct mlx5_core_dev *dev = esw->dev;
151 struct mlx5_flow_namespace *ns;
152 struct mlx5_flow_table *fdb;
153 struct mlx5_vport_table *e;
154 struct mlx5_vport_key skey;
155 u32 hkey;
156
157 mutex_lock(&esw->fdb_table.offloads.vports.lock);
158 hkey = flow_attr_to_vport_key(esw, attr, &skey);
159 e = esw_vport_tbl_lookup(esw, &skey, hkey);
160 if (e) {
161 e->num_rules++;
162 goto out;
163 }
164
165 e = kzalloc(sizeof(*e), GFP_KERNEL);
166 if (!e) {
167 fdb = ERR_PTR(-ENOMEM);
168 goto err_alloc;
169 }
170
171 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
172 if (!ns) {
173 esw_warn(dev, "Failed to get FDB namespace\n");
174 fdb = ERR_PTR(-ENOENT);
175 goto err_ns;
176 }
177
178 fdb = esw_vport_tbl_create(esw, ns);
179 if (IS_ERR(fdb))
180 goto err_ns;
181
182 e->fdb = fdb;
183 e->num_rules = 1;
184 e->key = skey;
185 hash_add(esw->fdb_table.offloads.vports.table, &e->hlist, hkey);
186out:
187 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
188 return e->fdb;
189
190err_ns:
191 kfree(e);
192err_alloc:
193 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
194 return fdb;
195}
196
197int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw)
198{
c620b772 199 struct mlx5_vport_tbl_attr attr;
96e32687
EC		 200 struct mlx5_flow_table *fdb;
201 struct mlx5_vport *vport;
202 int i;
203
c620b772 204 attr.chain = 0;
96e32687 205 attr.prio = 1;
96e32687 206 mlx5_esw_for_all_vports(esw, i, vport) {
c620b772 207 attr.vport = vport->vport;
96e32687 208 fdb = esw_vport_tbl_get(esw, &attr);
d9fb932f 209 if (IS_ERR(fdb))
96e32687
EC		 210 goto out;
211 }
212 return 0;
213
214out:
215 mlx5_esw_vport_tbl_put(esw);
216 return PTR_ERR(fdb);
217}
218
219void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw)
220{
c620b772 221 struct mlx5_vport_tbl_attr attr;
96e32687
EC		 222 struct mlx5_vport *vport;
223 int i;
224
c620b772 225 attr.chain = 0;
96e32687 226 attr.prio = 1;
96e32687 227 mlx5_esw_for_all_vports(esw, i, vport) {
c620b772 228 attr.vport = vport->vport;
96e32687
EC		 229 esw_vport_tbl_put(esw, &attr);
230 }
231}
232
233/* End: Per vport tables */
234
879c8f84
BW		 235static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
236 u16 vport_num)
237{
02f3afd9 238 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
879c8f84
BW		 239
240 WARN_ON(idx > esw->total_vports - 1);
241 return &esw->offloads.vport_reps[idx];
242}
243
6f7bbad1
JL		 244static void
245mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
246 struct mlx5_flow_spec *spec,
247 struct mlx5_esw_flow_attr *attr)
248{
249 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
250 attr && attr->in_rep && attr->in_rep->vport == MLX5_VPORT_UPLINK)
251 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
252}
b7826076 253
c01cfd0f
JL		 254static void
255mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
256 struct mlx5_flow_spec *spec,
257 struct mlx5_esw_flow_attr *attr)
258{
259 void *misc2;
260 void *misc;
261
262 /* Use metadata matching because vport is not represented by single
263 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
264 */
265 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
266 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
267 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
268 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
269 attr->in_rep->vport));
270
271 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 272 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
273 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 274
275 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 276 } else {
277 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
278 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
279
280 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
281 MLX5_SET(fte_match_set_misc, misc,
282 source_eswitch_owner_vhca_id,
283 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
284
285 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
286 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
287 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
288 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
289 source_eswitch_owner_vhca_id);
290
291 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
292 }
c01cfd0f
JL		 293}
294
74491de9 295struct mlx5_flow_handle *
3d80d1a2
OG		 296mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
297 struct mlx5_flow_spec *spec,
c620b772 298 struct mlx5_flow_attr *attr)
3d80d1a2 299{
592d3651 300 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 301 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 302 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 303 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 304 bool split = !!(esw_attr->split_count);
305 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 306 struct mlx5_flow_handle *rule;
e52c2802 307 struct mlx5_flow_table *fdb;
592d3651 308 int j, i = 0;
3d80d1a2 309
f6455de0 310 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 311 return ERR_PTR(-EOPNOTSUPP);
312
6acfbf38
OG		 313 flow_act.action = attr->action;
314 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 315 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 316 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
317 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
318 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 319 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
320 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
321 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 322 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 323 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
324 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
325 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 326 }
6acfbf38 327 }
776b12b6 328
66958ed9 329 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
39ac237c 330 struct mlx5_flow_table *ft;
e52c2802 331
d18296ff
PB		 332 if (attr->dest_ft) {
333 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
334 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
335 dest[i].ft = attr->dest_ft;
336 i++;
337 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
39ac237c
PB		 338 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
339 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
ae430332 340 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
39ac237c
PB		 341 i++;
342 } else if (attr->dest_chain) {
343 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
ae430332
AL		 344 ft = mlx5_chains_get_table(chains, attr->dest_chain,
345 1, 0);
e52c2802
PB		 346 if (IS_ERR(ft)) {
347 rule = ERR_CAST(ft);
348 goto err_create_goto_table;
349 }
350
351 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
352 dest[i].ft = ft;
592d3651 353 i++;
e52c2802 354 } else {
c620b772 355 for (j = esw_attr->split_count; j < esw_attr->out_count; j++) {
e52c2802 356 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
c620b772 357 dest[i].vport.num = esw_attr->dests[j].rep->vport;
e52c2802 358 dest[i].vport.vhca_id =
c620b772 359 MLX5_CAP_GEN(esw_attr->dests[j].mdev, vhca_id);
aa39c2c0
EB		 360 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
361 dest[i].vport.flags |=
362 MLX5_FLOW_DEST_VPORT_VHCA_ID;
c620b772 363 if (esw_attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
f493f155 364 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
c620b772
AL		 365 flow_act.pkt_reformat =
366 esw_attr->dests[j].pkt_reformat;
a18e879d 367 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
2b688ea5 368 dest[i].vport.pkt_reformat =
c620b772 369 esw_attr->dests[j].pkt_reformat;
f493f155 370 }
e52c2802
PB		 371 i++;
372 }
56e858df 373 }
e37a79e5 374 }
14e6b038 375
c620b772
AL		 376 if (esw_attr->decap_pkt_reformat)
377 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 378
66958ed9 379 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 380 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 381 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 382 i++;
3d80d1a2
OG		 383 }
384
93b3586e 385 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 386 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 387 if (attr->inner_match_level != MLX5_MATCH_NONE)
388 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 389
aa24670e 390 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 391 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 392
96e32687 393 if (split) {
c620b772
AL		 394 fwd_attr.chain = attr->chain;
395 fwd_attr.prio = attr->prio;
396 fwd_attr.vport = esw_attr->in_rep->vport;
397
398 fdb = esw_vport_tbl_get(esw, &fwd_attr);
96e32687 399 } else {
d18296ff 400 if (attr->chain || attr->prio)
ae430332
AL		 401 fdb = mlx5_chains_get_table(chains, attr->chain,
402 attr->prio, 0);
d18296ff 403 else
c620b772 404 fdb = attr->ft;
6fb0701a
PB		 405
406 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
c620b772 407 mlx5_eswitch_set_rule_source_port(esw, spec, esw_attr);
96e32687 408 }
e52c2802
PB		 409 if (IS_ERR(fdb)) {
410 rule = ERR_CAST(fdb);
411 goto err_esw_get;
412 }
413
c620b772 414 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
6f7bbad1 415
84be2fda 416 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 417 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 418 &flow_act, dest, i);
84be2fda 419 else
10caabda 420 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 421 if (IS_ERR(rule))
e52c2802 422 goto err_add_rule;
375f51e2 423 else
525e84be 424 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 425
e52c2802
PB		 426 return rule;
427
428err_add_rule:
96e32687 429 if (split)
c620b772 430 esw_vport_tbl_put(esw, &fwd_attr);
d18296ff 431 else if (attr->chain || attr->prio)
ae430332 432 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 433err_esw_get:
39ac237c 434 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) && attr->dest_chain)
ae430332 435 mlx5_chains_put_table(chains, attr->dest_chain, 1, 0);
e52c2802 436err_create_goto_table:
aa0cbbae 437 return rule;
3d80d1a2
OG		 438}
439
e4ad91f2
CM		 440struct mlx5_flow_handle *
441mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
442 struct mlx5_flow_spec *spec,
c620b772 443 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 444{
445 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 446 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 447 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 448 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 449 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 450 struct mlx5_flow_table *fast_fdb;
451 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 452 struct mlx5_flow_handle *rule;
e4ad91f2
CM		 453 int i;
454
ae430332 455 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 456 if (IS_ERR(fast_fdb)) {
457 rule = ERR_CAST(fast_fdb);
458 goto err_get_fast;
459 }
460
c620b772
AL		 461 fwd_attr.chain = attr->chain;
462 fwd_attr.prio = attr->prio;
463 fwd_attr.vport = esw_attr->in_rep->vport;
464 fwd_fdb = esw_vport_tbl_get(esw, &fwd_attr);
e52c2802
PB		 465 if (IS_ERR(fwd_fdb)) {
466 rule = ERR_CAST(fwd_fdb);
467 goto err_get_fwd;
468 }
469
e4ad91f2 470 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
c620b772 471 for (i = 0; i < esw_attr->split_count; i++) {
e4ad91f2 472 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
c620b772 473 dest[i].vport.num = esw_attr->dests[i].rep->vport;
e4ad91f2 474 dest[i].vport.vhca_id =
c620b772 475 MLX5_CAP_GEN(esw_attr->dests[i].mdev, vhca_id);
aa39c2c0
EB		 476 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
477 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
c620b772 478 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
1cc26d74 479 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
c620b772 480 dest[i].vport.pkt_reformat = esw_attr->dests[i].pkt_reformat;
1cc26d74 481 }
e4ad91f2
CM		 482 }
483 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
e52c2802 484 dest[i].ft = fwd_fdb,
e4ad91f2
CM		 485 i++;
486
c620b772 487 mlx5_eswitch_set_rule_source_port(esw, spec, esw_attr);
e4ad91f2 488
93b3586e 489 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 490 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 491
278d51f2 492 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 493 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 494
e52c2802
PB		 495 if (IS_ERR(rule))
496 goto add_err;
e4ad91f2 497
525e84be 498 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 499
500 return rule;
501add_err:
c620b772 502 esw_vport_tbl_put(esw, &fwd_attr);
e52c2802 503err_get_fwd:
ae430332 504 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 505err_get_fast:
e4ad91f2
CM		 506 return rule;
507}
508
e52c2802
PB		 509static void
510__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
511 struct mlx5_flow_handle *rule,
c620b772 512 struct mlx5_flow_attr *attr,
e52c2802
PB		 513 bool fwd_rule)
514{
c620b772 515 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 516 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 517 bool split = (esw_attr->split_count > 0);
518 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 519 int i;
e52c2802
PB		 520
521 mlx5_del_flow_rules(rule);
10caabda 522
84be2fda 523 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 524 /* unref the term table */
525 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 526 if (esw_attr->dests[i].termtbl)
527 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 528 }
10caabda
OS		 529 }
530
525e84be 531 atomic64_dec(&esw->offloads.num_flows);
e52c2802 532
c620b772
AL		 533 if (fwd_rule || split) {
534 fwd_attr.chain = attr->chain;
535 fwd_attr.prio = attr->prio;
536 fwd_attr.vport = esw_attr->in_rep->vport;
537 }
538
e52c2802 539 if (fwd_rule) {
c620b772 540 esw_vport_tbl_put(esw, &fwd_attr);
ae430332 541 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 542 } else {
96e32687 543 if (split)
c620b772 544 esw_vport_tbl_put(esw, &fwd_attr);
d18296ff 545 else if (attr->chain || attr->prio)
ae430332 546 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 547 if (attr->dest_chain)
ae430332 548 mlx5_chains_put_table(chains, attr->dest_chain, 1, 0);
e52c2802
PB		 549 }
550}
551
d85cdccb
OG		 552void
553mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
554 struct mlx5_flow_handle *rule,
c620b772 555 struct mlx5_flow_attr *attr)
d85cdccb 556{
e52c2802 557 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 558}
559
48265006
OG		 560void
561mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
562 struct mlx5_flow_handle *rule,
c620b772 563 struct mlx5_flow_attr *attr)
48265006 564{
e52c2802 565 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 566}
567
f5f82476
OG		 568static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
569{
570 struct mlx5_eswitch_rep *rep;
411ec9e0 571 int i, err = 0;
f5f82476
OG		 572
573 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
411ec9e0 574 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 575 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 576 continue;
577
578 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
579 if (err)
580 goto out;
581 }
582
583out:
584 return err;
585}
586
587static struct mlx5_eswitch_rep *
588esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
589{
590 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
591
592 in_rep = attr->in_rep;
df65a573 593 out_rep = attr->dests[0].rep;
f5f82476
OG		 594
595 if (push)
596 vport = in_rep;
597 else if (pop)
598 vport = out_rep;
599 else
600 vport = in_rep;
601
602 return vport;
603}
604
605static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
606 bool push, bool pop, bool fwd)
607{
608 struct mlx5_eswitch_rep *in_rep, *out_rep;
609
610 if ((push || pop) && !fwd)
611 goto out_notsupp;
612
613 in_rep = attr->in_rep;
df65a573 614 out_rep = attr->dests[0].rep;
f5f82476 615
b05af6aa 616 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 617 goto out_notsupp;
618
b05af6aa 619 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 620 goto out_notsupp;
621
622 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
623 if (!push && !pop && fwd)
b05af6aa 624 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 625 goto out_notsupp;
626
627 /* protects against (1) setting rules with different vlans to push and
628 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
629 */
1482bd3d 630 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 631 goto out_notsupp;
632
633 return 0;
634
635out_notsupp:
9eb78923 636 return -EOPNOTSUPP;
f5f82476
OG		 637}
638
639int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 640 struct mlx5_flow_attr *attr)
f5f82476
OG		 641{
642 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 643 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 644 struct mlx5_eswitch_rep *vport = NULL;
645 bool push, pop, fwd;
646 int err = 0;
647
6acfbf38 648 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 649 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 650 return 0;
651
f5f82476
OG		 652 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
653 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 654 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
655 !attr->dest_chain);
f5f82476 656
0e18134f
VB		 657 mutex_lock(&esw->state_lock);
658
c620b772 659 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 660 if (err)
0e18134f 661 goto unlock;
f5f82476 662
39ac237c 663 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 664
c620b772 665 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 666
667 if (!push && !pop && fwd) {
668 /* tracks VF --> wire rules without vlan push action */
c620b772 669 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 670 vport->vlan_refcount++;
39ac237c 671 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 672 }
673
0e18134f 674 goto unlock;
f5f82476
OG		 675 }
676
677 if (!push && !pop)
0e18134f 678 goto unlock;
f5f82476
OG		 679
680 if (!(offloads->vlan_push_pop_refcount)) {
681 /* it's the 1st vlan rule, apply global vlan pop policy */
682 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
683 if (err)
684 goto out;
685 }
686 offloads->vlan_push_pop_refcount++;
687
688 if (push) {
689 if (vport->vlan_refcount)
690 goto skip_set_push;
691
c620b772
AL		 692 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
693 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 694 if (err)
695 goto out;
c620b772 696 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 697skip_set_push:
698 vport->vlan_refcount++;
699 }
700out:
701 if (!err)
39ac237c 702 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 703unlock:
704 mutex_unlock(&esw->state_lock);
f5f82476
OG		 705 return err;
706}
707
708int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 709 struct mlx5_flow_attr *attr)
f5f82476
OG		 710{
711 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 712 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 713 struct mlx5_eswitch_rep *vport = NULL;
714 bool push, pop, fwd;
715 int err = 0;
716
6acfbf38 717 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 718 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 719 return 0;
720
39ac237c 721 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 722 return 0;
723
724 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
725 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
726 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
727
0e18134f
VB		 728 mutex_lock(&esw->state_lock);
729
c620b772 730 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 731
732 if (!push && !pop && fwd) {
733 /* tracks VF --> wire rules without vlan push action */
c620b772 734 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 735 vport->vlan_refcount--;
736
0e18134f 737 goto out;
f5f82476
OG		 738 }
739
740 if (push) {
741 vport->vlan_refcount--;
742 if (vport->vlan_refcount)
743 goto skip_unset_push;
744
745 vport->vlan = 0;
746 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
747 0, 0, SET_VLAN_STRIP);
748 if (err)
749 goto out;
750 }
751
752skip_unset_push:
753 offloads->vlan_push_pop_refcount--;
754 if (offloads->vlan_push_pop_refcount)
0e18134f 755 goto out;
f5f82476
OG		 756
757 /* no more vlan rules, stop global vlan pop policy */
758 err = esw_set_global_vlan_pop(esw, 0);
759
760out:
0e18134f 761 mutex_unlock(&esw->state_lock);
f5f82476
OG		 762 return err;
763}
764
f7a68945 765struct mlx5_flow_handle *
02f3afd9
PP		 766mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
767 u32 sqn)
ab22be9b 768{
66958ed9 769 struct mlx5_flow_act flow_act = {0};
4c5009c5 770 struct mlx5_flow_destination dest = {};
74491de9 771 struct mlx5_flow_handle *flow_rule;
c5bb1730 772 struct mlx5_flow_spec *spec;
ab22be9b
OG		 773 void *misc;
774
1b9a07ee 775 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 776 if (!spec) {
ab22be9b
OG		 777 flow_rule = ERR_PTR(-ENOMEM);
778 goto out;
779 }
780
c5bb1730 781 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 782 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a
BW		 783 /* source vport is the esw manager */
784 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
ab22be9b 785
c5bb1730 786 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 787 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
788 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
789
c5bb1730 790 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 791 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 792 dest.vport.num = vport;
66958ed9 793 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 794
39ac237c
PB		 795 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
796 spec, &flow_act, &dest, 1);
ab22be9b
OG		 797 if (IS_ERR(flow_rule))
798 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
799out:
c5bb1730 800 kvfree(spec);
ab22be9b
OG		 801 return flow_rule;
802}
57cbd893 803EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 804
159fe639
MB		 805void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
806{
807 mlx5_del_flow_rules(rule);
808}
809
5b7cb745
PB		 810static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
811{
812 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
813 MLX5_FDB_TO_VPORT_REG_C_1;
814}
815
332bd3a5 816static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 817{
818 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 819 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
820 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 821 u8 curr, wanted;
c1286050
JL		 822 int err;
823
5b7cb745
PB		 824 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
825 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 826 return 0;
c1286050 827
e08a6832
LR		 828 MLX5_SET(query_esw_vport_context_in, in, opcode,
829 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
830 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 831 if (err)
832 return err;
833
5b7cb745
PB		 834 curr = MLX5_GET(query_esw_vport_context_out, out,
835 esw_vport_context.fdb_to_vport_reg_c_id);
836 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
837 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
838 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 839
332bd3a5 840 if (enable)
5b7cb745 841 curr |= wanted;
332bd3a5 842 else
5b7cb745 843 curr &= ~wanted;
c1286050 844
e08a6832 845 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 846 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 847 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 848 field_select.fdb_to_vport_reg_c_id, 1);
849
e08a6832 850 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 851 if (!err) {
852 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
853 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
854 else
855 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
856 }
857
858 return err;
c1286050
JL		 859}
860
a5641cb5
JL		 861static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
862 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 863 struct mlx5_flow_spec *spec,
864 struct mlx5_flow_destination *dest)
865{
a5641cb5 866 void *misc;
ac004b83 867
a5641cb5
JL		 868 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
869 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
870 misc_parameters_2);
0f0d3827
PB		 871 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
872 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 873
a5641cb5
JL		 874 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
875 } else {
876 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
877 misc_parameters);
ac004b83 878
a5641cb5
JL		 879 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
880 MLX5_CAP_GEN(peer_dev, vhca_id));
881
882 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
883
884 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
885 misc_parameters);
886 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
887 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
888 source_eswitch_owner_vhca_id);
889 }
ac004b83
RD		 890
891 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 892 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 893 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 894 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 895}
896
a5641cb5
JL		 897static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
898 struct mlx5_eswitch *peer_esw,
899 struct mlx5_flow_spec *spec,
900 u16 vport)
901{
902 void *misc;
903
904 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
905 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
906 misc_parameters_2);
907 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
908 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
909 vport));
910 } else {
911 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
912 misc_parameters);
913 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
914 }
915}
916
ac004b83
RD		 917static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
918 struct mlx5_core_dev *peer_dev)
919{
920 struct mlx5_flow_destination dest = {};
921 struct mlx5_flow_act flow_act = {0};
922 struct mlx5_flow_handle **flows;
923 struct mlx5_flow_handle *flow;
924 struct mlx5_flow_spec *spec;
925 /* total vports is the same for both e-switches */
926 int nvports = esw->total_vports;
927 void *misc;
928 int err, i;
929
930 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
931 if (!spec)
932 return -ENOMEM;
933
a5641cb5 934 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 935
936 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
937 if (!flows) {
938 err = -ENOMEM;
939 goto alloc_flows_err;
940 }
941
942 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
943 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
944 misc_parameters);
945
81cd229c 946 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
a5641cb5
JL		 947 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
948 spec, MLX5_VPORT_PF);
949
81cd229c
BW		 950 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
951 spec, &flow_act, &dest, 1);
952 if (IS_ERR(flow)) {
953 err = PTR_ERR(flow);
954 goto add_pf_flow_err;
955 }
956 flows[MLX5_VPORT_PF] = flow;
957 }
958
959 if (mlx5_ecpf_vport_exists(esw->dev)) {
960 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
961 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
962 spec, &flow_act, &dest, 1);
963 if (IS_ERR(flow)) {
964 err = PTR_ERR(flow);
965 goto add_ecpf_flow_err;
966 }
967 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
968 }
969
786ef904 970 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 971 esw_set_peer_miss_rule_source_port(esw,
972 peer_dev->priv.eswitch,
973 spec, i);
974
ac004b83
RD		 975 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
976 spec, &flow_act, &dest, 1);
977 if (IS_ERR(flow)) {
978 err = PTR_ERR(flow);
81cd229c 979 goto add_vf_flow_err;
ac004b83
RD		 980 }
981 flows[i] = flow;
982 }
983
984 esw->fdb_table.offloads.peer_miss_rules = flows;
985
986 kvfree(spec);
987 return 0;
988
81cd229c 989add_vf_flow_err:
879c8f84 990 nvports = --i;
786ef904 991 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
ac004b83 992 mlx5_del_flow_rules(flows[i]);
81cd229c
BW		 993
994 if (mlx5_ecpf_vport_exists(esw->dev))
995 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
996add_ecpf_flow_err:
997 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
998 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
999add_pf_flow_err:
1000 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1001 kvfree(flows);
1002alloc_flows_err:
1003 kvfree(spec);
1004 return err;
1005}
1006
1007static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1008{
1009 struct mlx5_flow_handle **flows;
1010 int i;
1011
1012 flows = esw->fdb_table.offloads.peer_miss_rules;
1013
786ef904
PP		 1014 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
1015 mlx5_core_max_vfs(esw->dev))
ac004b83
RD		 1016 mlx5_del_flow_rules(flows[i]);
1017
81cd229c
BW		 1018 if (mlx5_ecpf_vport_exists(esw->dev))
1019 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
1020
1021 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
1022 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
1023
ac004b83
RD		 1024 kvfree(flows);
1025}
1026
3aa33572
OG		 1027static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1028{
66958ed9 1029 struct mlx5_flow_act flow_act = {0};
4c5009c5 1030 struct mlx5_flow_destination dest = {};
74491de9 1031 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1032 struct mlx5_flow_spec *spec;
f80be543
MB		 1033 void *headers_c;
1034 void *headers_v;
3aa33572 1035 int err = 0;
f80be543
MB		 1036 u8 *dmac_c;
1037 u8 *dmac_v;
3aa33572 1038
1b9a07ee 1039 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1040 if (!spec) {
3aa33572
OG		 1041 err = -ENOMEM;
1042 goto out;
1043 }
1044
f80be543
MB		 1045 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1046 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1047 outer_headers);
1048 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1049 outer_headers.dmac_47_16);
1050 dmac_c[0] = 0x01;
1051
3aa33572 1052 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1053 dest.vport.num = esw->manager_vport;
66958ed9 1054 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1055
39ac237c
PB		 1056 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1057 spec, &flow_act, &dest, 1);
3aa33572
OG		 1058 if (IS_ERR(flow_rule)) {
1059 err = PTR_ERR(flow_rule);
f80be543 1060 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1061 goto out;
1062 }
1063
f80be543
MB		 1064 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1065
1066 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1067 outer_headers);
1068 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1069 outer_headers.dmac_47_16);
1070 dmac_v[0] = 0x01;
39ac237c
PB		 1071 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1072 spec, &flow_act, &dest, 1);
f80be543
MB		 1073 if (IS_ERR(flow_rule)) {
1074 err = PTR_ERR(flow_rule);
1075 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1076 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1077 goto out;
1078 }
1079
1080 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1081
3aa33572 1082out:
c5bb1730 1083 kvfree(spec);
3aa33572
OG		 1084 return err;
1085}
1086
11b717d6
PB		 1087struct mlx5_flow_handle *
1088esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1089{
1090 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1091 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1092 struct mlx5_flow_context *flow_context;
1093 struct mlx5_flow_handle *flow_rule;
1094 struct mlx5_flow_destination dest;
1095 struct mlx5_flow_spec *spec;
1096 void *misc;
1097
60acc105
PB		 1098 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1099 return ERR_PTR(-EOPNOTSUPP);
1100
11b717d6
PB		 1101 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1102 if (!spec)
1103 return ERR_PTR(-ENOMEM);
1104
1105 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1106 misc_parameters_2);
1107 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1108 ESW_CHAIN_TAG_METADATA_MASK);
1109 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1110 misc_parameters_2);
1111 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1112 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1113 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1114 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1115 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1116
1117 flow_context = &spec->flow_context;
1118 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1119 flow_context->flow_tag = tag;
1120 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1121 dest.ft = esw->offloads.ft_offloads;
1122
1123 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1124 kfree(spec);
1125
1126 if (IS_ERR(flow_rule))
1127 esw_warn(esw->dev,
1128 "Failed to create restore rule for tag: %d, err(%d)\n",
1129 tag, (int)PTR_ERR(flow_rule));
1130
1131 return flow_rule;
1132}
1133
1134u32
1135esw_get_max_restore_tag(struct mlx5_eswitch *esw)
1136{
1137 return ESW_CHAIN_TAG_METADATA_MASK;
1138}
1139
1967ce6e 1140#define MAX_PF_SQ 256
cd3d07e7 1141#define MAX_SQ_NVPORTS 32
1967ce6e 1142
a5641cb5
JL		 1143static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1144 u32 *flow_group_in)
1145{
1146 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1147 flow_group_in,
1148 match_criteria);
1149
1150 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1151 MLX5_SET(create_flow_group_in, flow_group_in,
1152 match_criteria_enable,
1153 MLX5_MATCH_MISC_PARAMETERS_2);
1154
0f0d3827
PB		 1155 MLX5_SET(fte_match_param, match_criteria,
1156 misc_parameters_2.metadata_reg_c_0,
1157 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1158 } else {
1159 MLX5_SET(create_flow_group_in, flow_group_in,
1160 match_criteria_enable,
1161 MLX5_MATCH_MISC_PARAMETERS);
1162
1163 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1164 misc_parameters.source_port);
1165 }
1166}
1167
ae430332
AL		 1168#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
1169#define fdb_modify_header_fwd_to_table_supported(esw) \
1170 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1171static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1172{
1173 struct mlx5_core_dev *dev = esw->dev;
1174
1175 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1176 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1177
1178 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1179 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1180 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1181 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1182 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1183 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1184 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1185 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1186 /* Disabled when ttl workaround is needed, e.g
1187 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1188 */
1189 esw_warn(dev,
1190 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1191 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1192 } else {
1193 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1194 esw_info(dev, "Supported tc chains and prios offload\n");
1195 }
1196
1197 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1198 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1199}
1200
1201static int
1202esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1203{
1204 struct mlx5_core_dev *dev = esw->dev;
1205 struct mlx5_flow_table *nf_ft, *ft;
1206 struct mlx5_chains_attr attr = {};
1207 struct mlx5_fs_chains *chains;
1208 u32 fdb_max;
1209 int err;
1210
1211 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1212
1213 esw_init_chains_offload_flags(esw, &attr.flags);
1214 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1215 attr.max_ft_sz = fdb_max;
1216 attr.max_grp_num = esw->params.large_group_num;
1217 attr.default_ft = miss_fdb;
1218 attr.max_restore_tag = esw_get_max_restore_tag(esw);
1219
1220 chains = mlx5_chains_create(dev, &attr);
1221 if (IS_ERR(chains)) {
1222 err = PTR_ERR(chains);
1223 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1224 return err;
1225 }
1226
1227 esw->fdb_table.offloads.esw_chains_priv = chains;
1228
1229 /* Create tc_end_ft which is the always created ft chain */
1230 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1231 1, 0);
1232 if (IS_ERR(nf_ft)) {
1233 err = PTR_ERR(nf_ft);
1234 goto nf_ft_err;
1235 }
1236
1237 /* Always open the root for fast path */
1238 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1239 if (IS_ERR(ft)) {
1240 err = PTR_ERR(ft);
1241 goto level_0_err;
1242 }
1243
1244 /* Open level 1 for split fdb rules now if prios isn't supported */
1245 if (!mlx5_chains_prios_supported(chains)) {
1246 err = mlx5_esw_vport_tbl_get(esw);
1247 if (err)
1248 goto level_1_err;
1249 }
1250
1251 mlx5_chains_set_end_ft(chains, nf_ft);
1252
1253 return 0;
1254
1255level_1_err:
1256 mlx5_chains_put_table(chains, 0, 1, 0);
1257level_0_err:
1258 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1259nf_ft_err:
1260 mlx5_chains_destroy(chains);
1261 esw->fdb_table.offloads.esw_chains_priv = NULL;
1262
1263 return err;
1264}
1265
1266static void
1267esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1268{
1269 if (!mlx5_chains_prios_supported(chains))
1270 mlx5_esw_vport_tbl_put(esw);
1271 mlx5_chains_put_table(chains, 0, 1, 0);
1272 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1273 mlx5_chains_destroy(chains);
1274}
1275
1276#else /* CONFIG_MLX5_CLS_ACT */
1277
1278static int
1279esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1280{ return 0; }
1281
1282static void
1283esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1284{}
1285
1286#endif
1287
0da3c12d 1288static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1289{
1290 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1291 struct mlx5_flow_table_attr ft_attr = {};
1292 struct mlx5_core_dev *dev = esw->dev;
1293 struct mlx5_flow_namespace *root_ns;
1294 struct mlx5_flow_table *fdb = NULL;
39ac237c
PB		 1295 u32 flags = 0, *flow_group_in;
1296 int table_size, ix, err = 0;
1967ce6e
OG		 1297 struct mlx5_flow_group *g;
1298 void *match_criteria;
f80be543 1299 u8 *dmac;
1967ce6e
OG		 1300
1301 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1302
1b9a07ee 1303 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1304 if (!flow_group_in)
1305 return -ENOMEM;
1306
1307 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1308 if (!root_ns) {
1309 esw_warn(dev, "Failed to get FDB flow namespace\n");
1310 err = -EOPNOTSUPP;
1311 goto ns_err;
1312 }
8463daf1
MG		 1313 esw->fdb_table.offloads.ns = root_ns;
1314 err = mlx5_flow_namespace_set_mode(root_ns,
1315 esw->dev->priv.steering->mode);
1316 if (err) {
1317 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1318 goto ns_err;
1319 }
1967ce6e 1320
0da3c12d 1321 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
cd7e4186 1322 MLX5_ESW_MISS_FLOWS + esw->total_vports;
b3ba5149 1323
e52c2802
PB		 1324 /* create the slow path fdb with encap set, so further table instances
1325 * can be created at run time while VFs are probed if the FW allows that.
1326 */
1327 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1328 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1329 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1330
1331 ft_attr.flags = flags;
b3ba5149
ES		 1332 ft_attr.max_fte = table_size;
1333 ft_attr.prio = FDB_SLOW_PATH;
1334
1335 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1336 if (IS_ERR(fdb)) {
1337 err = PTR_ERR(fdb);
1338 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1339 goto slow_fdb_err;
1340 }
52fff327 1341 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1342
ae430332 1343 err = esw_chains_create(esw, fdb);
39ac237c 1344 if (err) {
ae430332 1345 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1346 goto fdb_chains_err;
e52c2802
PB		 1347 }
1348
69697b6e 1349 /* create send-to-vport group */
69697b6e
OG		 1350 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1351 MLX5_MATCH_MISC_PARAMETERS);
1352
1353 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1354
1355 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1356 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1357
0da3c12d 1358 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1359 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1360 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1361
1362 g = mlx5_create_flow_group(fdb, flow_group_in);
1363 if (IS_ERR(g)) {
1364 err = PTR_ERR(g);
1365 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1366 goto send_vport_err;
1367 }
1368 esw->fdb_table.offloads.send_to_vport_grp = g;
1369
6cec0229
MD		 1370 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1371 /* create peer esw miss group */
1372 memset(flow_group_in, 0, inlen);
ac004b83 1373
6cec0229 1374 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1375
6cec0229
MD		 1376 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1377 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1378 flow_group_in,
1379 match_criteria);
ac004b83 1380
6cec0229
MD		 1381 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1382 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1383
6cec0229
MD		 1384 MLX5_SET(create_flow_group_in, flow_group_in,
1385 source_eswitch_owner_vhca_id_valid, 1);
1386 }
ac004b83 1387
6cec0229
MD		 1388 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1389 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1390 ix + esw->total_vports - 1);
1391 ix += esw->total_vports;
ac004b83 1392
6cec0229
MD		 1393 g = mlx5_create_flow_group(fdb, flow_group_in);
1394 if (IS_ERR(g)) {
1395 err = PTR_ERR(g);
1396 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1397 goto peer_miss_err;
1398 }
1399 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1400 }
ac004b83 1401
69697b6e
OG		 1402 /* create miss group */
1403 memset(flow_group_in, 0, inlen);
f80be543
MB		 1404 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1405 MLX5_MATCH_OUTER_HEADERS);
1406 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1407 match_criteria);
1408 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1409 outer_headers.dmac_47_16);
1410 dmac[0] = 0x01;
69697b6e
OG		 1411
1412 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1413 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1414 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1415
1416 g = mlx5_create_flow_group(fdb, flow_group_in);
1417 if (IS_ERR(g)) {
1418 err = PTR_ERR(g);
1419 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1420 goto miss_err;
1421 }
1422 esw->fdb_table.offloads.miss_grp = g;
1423
3aa33572
OG		 1424 err = esw_add_fdb_miss_rule(esw);
1425 if (err)
1426 goto miss_rule_err;
1427
c88a026e 1428 kvfree(flow_group_in);
69697b6e
OG		 1429 return 0;
1430
3aa33572
OG		 1431miss_rule_err:
1432 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1433miss_err:
6cec0229
MD		 1434 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1435 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1436peer_miss_err:
69697b6e
OG		 1437 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1438send_vport_err:
ae430332 1439 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1440fdb_chains_err:
52fff327 1441 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1442slow_fdb_err:
8463daf1
MG		 1443 /* Holds true only as long as DMFS is the default */
1444 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1445ns_err:
1446 kvfree(flow_group_in);
1447 return err;
1448}
1449
1967ce6e 1450static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1451{
e52c2802 1452 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1453 return;
1454
1967ce6e 1455 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1456 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1457 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1458 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
6cec0229
MD		 1459 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1460 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1461 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1462
ae430332
AL		 1463 esw_chains_destroy(esw, esw_chains(esw));
1464
52fff327 1465 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1466 /* Holds true only as long as DMFS is the default */
1467 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1468 MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e 1469}
c116c6ee 1470
8d6bd3c3 1471static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1472{
b3ba5149 1473 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1474 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1475 struct mlx5_flow_table *ft_offloads;
1476 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1477 int err = 0;
1478
1479 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1480 if (!ns) {
1481 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1482 return -EOPNOTSUPP;
c116c6ee
OG		 1483 }
1484
8d6bd3c3 1485 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1486 ft_attr.prio = 1;
b3ba5149
ES		 1487
1488 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1489 if (IS_ERR(ft_offloads)) {
1490 err = PTR_ERR(ft_offloads);
1491 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1492 return err;
1493 }
1494
1495 esw->offloads.ft_offloads = ft_offloads;
1496 return 0;
1497}
1498
1499static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1500{
1501 struct mlx5_esw_offload *offloads = &esw->offloads;
1502
1503 mlx5_destroy_flow_table(offloads->ft_offloads);
1504}
fed9ce22 1505
8d6bd3c3 1506static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1507{
1508 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1509 struct mlx5_flow_group *g;
fed9ce22 1510 u32 *flow_group_in;
8d6bd3c3 1511 int nvports;
fed9ce22 1512 int err = 0;
fed9ce22 1513
8d6bd3c3 1514 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1515 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1516 if (!flow_group_in)
1517 return -ENOMEM;
1518
1519 /* create vport rx group */
a5641cb5 1520 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1521
1522 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1523 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1524
1525 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1526
1527 if (IS_ERR(g)) {
1528 err = PTR_ERR(g);
1529 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1530 goto out;
1531 }
1532
1533 esw->offloads.vport_rx_group = g;
1534out:
e574978a 1535 kvfree(flow_group_in);
fed9ce22
OG		 1536 return err;
1537}
1538
1539static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1540{
1541 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1542}
1543
74491de9 1544struct mlx5_flow_handle *
02f3afd9 1545mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1546 struct mlx5_flow_destination *dest)
fed9ce22 1547{
66958ed9 1548 struct mlx5_flow_act flow_act = {0};
74491de9 1549 struct mlx5_flow_handle *flow_rule;
c5bb1730 1550 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1551 void *misc;
1552
1b9a07ee 1553 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1554 if (!spec) {
fed9ce22
OG		 1555 flow_rule = ERR_PTR(-ENOMEM);
1556 goto out;
1557 }
1558
a5641cb5
JL		 1559 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1560 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1561 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1562 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1563
a5641cb5 1564 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1565 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1566 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1567
a5641cb5
JL		 1568 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1569 } else {
1570 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1571 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1572
1573 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1574 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1575
1576 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1577 }
fed9ce22 1578
66958ed9 1579 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1580 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1581 &flow_act, dest, 1);
fed9ce22
OG		 1582 if (IS_ERR(flow_rule)) {
1583 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1584 goto out;
1585 }
1586
1587out:
c5bb1730 1588 kvfree(spec);
fed9ce22
OG		 1589 return flow_rule;
1590}
feae9087 1591
bf3347c4 1592
cc617ced
PP		 1593static int mlx5_eswitch_inline_mode_get(const struct mlx5_eswitch *esw, u8 *mode)
1594{
1595 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1596 struct mlx5_core_dev *dev = esw->dev;
1597 int vport;
1598
1599 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1600 return -EOPNOTSUPP;
1601
1602 if (esw->mode == MLX5_ESWITCH_NONE)
1603 return -EOPNOTSUPP;
1604
1605 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1606 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1607 mlx5_mode = MLX5_INLINE_MODE_NONE;
1608 goto out;
1609 case MLX5_CAP_INLINE_MODE_L2:
1610 mlx5_mode = MLX5_INLINE_MODE_L2;
1611 goto out;
1612 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1613 goto query_vports;
1614 }
1615
1616query_vports:
1617 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
1618 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
1619 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
1620 if (prev_mlx5_mode != mlx5_mode)
1621 return -EINVAL;
1622 prev_mlx5_mode = mlx5_mode;
1623 }
1624
1625out:
1626 *mode = mlx5_mode;
1627 return 0;
e08a6832 1628}
bf3347c4 1629
11b717d6
PB		 1630static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1631{
1632 struct mlx5_esw_offload *offloads = &esw->offloads;
1633
60acc105
PB		 1634 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1635 return;
1636
6724e66b 1637 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 1638 mlx5_destroy_flow_group(offloads->restore_group);
1639 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
1640}
1641
1642static int esw_create_restore_table(struct mlx5_eswitch *esw)
1643{
d65dbedf 1644 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 1645 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1646 struct mlx5_flow_table_attr ft_attr = {};
1647 struct mlx5_core_dev *dev = esw->dev;
1648 struct mlx5_flow_namespace *ns;
6724e66b 1649 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 1650 void *match_criteria, *misc;
1651 struct mlx5_flow_table *ft;
1652 struct mlx5_flow_group *g;
1653 u32 *flow_group_in;
1654 int err = 0;
1655
60acc105
PB		 1656 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1657 return 0;
1658
11b717d6
PB		 1659 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1660 if (!ns) {
1661 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1662 return -EOPNOTSUPP;
1663 }
1664
1665 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1666 if (!flow_group_in) {
1667 err = -ENOMEM;
1668 goto out_free;
1669 }
1670
1671 ft_attr.max_fte = 1 << ESW_CHAIN_TAG_METADATA_BITS;
1672 ft = mlx5_create_flow_table(ns, &ft_attr);
1673 if (IS_ERR(ft)) {
1674 err = PTR_ERR(ft);
1675 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
1676 err);
1677 goto out_free;
1678 }
1679
1680 memset(flow_group_in, 0, inlen);
1681 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1682 match_criteria);
1683 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
1684 misc_parameters_2);
1685
1686 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1687 ESW_CHAIN_TAG_METADATA_MASK);
1688 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1689 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1690 ft_attr.max_fte - 1);
1691 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1692 MLX5_MATCH_MISC_PARAMETERS_2);
1693 g = mlx5_create_flow_group(ft, flow_group_in);
1694 if (IS_ERR(g)) {
1695 err = PTR_ERR(g);
1696 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
1697 err);
1698 goto err_group;
1699 }
1700
6724e66b
PB		 1701 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
1702 MLX5_SET(copy_action_in, modact, src_field,
1703 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
1704 MLX5_SET(copy_action_in, modact, dst_field,
1705 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
1706 mod_hdr = mlx5_modify_header_alloc(esw->dev,
1707 MLX5_FLOW_NAMESPACE_KERNEL, 1,
1708 modact);
1709 if (IS_ERR(mod_hdr)) {
e9864539 1710 err = PTR_ERR(mod_hdr);
6724e66b
PB		 1711 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
1712 err);
6724e66b
PB		 1713 goto err_mod_hdr;
1714 }
1715
11b717d6
PB		 1716 esw->offloads.ft_offloads_restore = ft;
1717 esw->offloads.restore_group = g;
6724e66b 1718 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 1719
c8508713
RD		 1720 kvfree(flow_group_in);
1721
11b717d6
PB		 1722 return 0;
1723
6724e66b
PB		 1724err_mod_hdr:
1725 mlx5_destroy_flow_group(g);
11b717d6
PB		 1726err_group:
1727 mlx5_destroy_flow_table(ft);
1728out_free:
1729 kvfree(flow_group_in);
1730
1731 return err;
cc617ced
PP		 1732}
1733
db7ff19e
EB		 1734static int esw_offloads_start(struct mlx5_eswitch *esw,
1735 struct netlink_ext_ack *extack)
c930a3ad 1736{
062f4bf4 1737 int err, err1;
c930a3ad 1738
8e0aa4bc
PP		 1739 mlx5_eswitch_disable_locked(esw, false);
1740 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
1741 esw->dev->priv.sriov.num_vfs);
6c419ba8 1742 if (err) {
8c98ee77
EB		 1743 NL_SET_ERR_MSG_MOD(extack,
1744 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 1745 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
1746 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 1747 if (err1) {
1748 NL_SET_ERR_MSG_MOD(extack,
1749 "Failed setting eswitch back to legacy");
1750 }
6c419ba8 1751 }
bffaa916
RD		 1752 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1753 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 1754 &esw->offloads.inline_mode)) {
1755 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 1756 NL_SET_ERR_MSG_MOD(extack,
1757 "Inline mode is different between vports");
bffaa916
RD		 1758 }
1759 }
c930a3ad
OG		 1760 return err;
1761}
1762
e8d31c4d
MB		 1763void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1764{
1765 kfree(esw->offloads.vport_reps);
1766}
1767
1768int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1769{
2752b823 1770 int total_vports = esw->total_vports;
e8d31c4d 1771 struct mlx5_eswitch_rep *rep;
d6518db2 1772 int vport_index;
ef2e4094 1773 u8 rep_type;
e8d31c4d 1774
2aca1787 1775 esw->offloads.vport_reps = kcalloc(total_vports,
e8d31c4d
MB		 1776 sizeof(struct mlx5_eswitch_rep),
1777 GFP_KERNEL);
1778 if (!esw->offloads.vport_reps)
1779 return -ENOMEM;
1780
d6518db2
BW		 1781 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1782 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
2f69e591 1783 rep->vport_index = vport_index;
f121e0ea
BW		 1784
1785 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
8693115a 1786 atomic_set(&rep->rep_data[rep_type].state,
6f4e0219 1787 REP_UNREGISTERED);
e8d31c4d
MB		 1788 }
1789
e8d31c4d
MB		 1790 return 0;
1791}
1792
c9b99abc
BW		 1793static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1794 struct mlx5_eswitch_rep *rep, u8 rep_type)
1795{
8693115a 1796 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 1797 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 1798 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 1799}
1800
4110fc59 1801static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 1802{
1803 struct mlx5_eswitch_rep *rep;
4110fc59
BW		 1804 int i;
1805
1806 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, esw->esw_funcs.num_vfs)
1807 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 1808
81cd229c
BW		 1809 if (mlx5_ecpf_vport_exists(esw->dev)) {
1810 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1811 __esw_offloads_unload_rep(esw, rep, rep_type);
1812 }
1813
1814 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1815 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1816 __esw_offloads_unload_rep(esw, rep, rep_type);
1817 }
1818
879c8f84 1819 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 1820 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1821}
1822
38679b5a 1823static int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 1824{
c2d7712c
BW		 1825 struct mlx5_eswitch_rep *rep;
1826 int rep_type;
a4b97ab4
MB		 1827 int err;
1828
c2d7712c
BW		 1829 rep = mlx5_eswitch_get_rep(esw, vport_num);
1830 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1831 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1832 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1833 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1834 if (err)
1835 goto err_reps;
1836 }
1837
1838 return 0;
a4b97ab4
MB		 1839
1840err_reps:
c2d7712c
BW		 1841 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
1842 for (--rep_type; rep_type >= 0; rep_type--)
1843 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1844 return err;
1845}
1846
38679b5a 1847static void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 1848{
1849 struct mlx5_eswitch_rep *rep;
1850 int rep_type;
1851
c2d7712c
BW		 1852 rep = mlx5_eswitch_get_rep(esw, vport_num);
1853 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
1854 __esw_offloads_unload_rep(esw, rep, rep_type);
1855}
1856
38679b5a
PP		 1857int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
1858{
1859 int err;
1860
1861 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1862 return 0;
1863
c7eddc60
PP		 1864 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
1865 if (err)
1866 return err;
1867
38679b5a 1868 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 1869 if (err)
1870 goto load_err;
1871 return err;
1872
1873load_err:
1874 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 1875 return err;
1876}
1877
1878void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
1879{
1880 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1881 return;
1882
1883 mlx5_esw_offloads_rep_unload(esw, vport_num);
c7eddc60 1884 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 1885}
1886
ac004b83
RD		 1887#define ESW_OFFLOADS_DEVCOM_PAIR (0)
1888#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1889
1890static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1891 struct mlx5_eswitch *peer_esw)
1892{
1893 int err;
1894
1895 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1896 if (err)
1897 return err;
1898
1899 return 0;
1900}
1901
1902static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1903{
d956873f 1904#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 1905 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 1906#endif
ac004b83
RD		 1907 esw_del_fdb_peer_miss_rules(esw);
1908}
1909
8463daf1
MG		 1910static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
1911 struct mlx5_eswitch *peer_esw,
1912 bool pair)
1913{
1914 struct mlx5_flow_root_namespace *peer_ns;
1915 struct mlx5_flow_root_namespace *ns;
1916 int err;
1917
1918 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
1919 ns = esw->dev->priv.steering->fdb_root_ns;
1920
1921 if (pair) {
1922 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
1923 if (err)
1924 return err;
1925
e53e6655 1926 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 1927 if (err) {
1928 mlx5_flow_namespace_set_peer(ns, NULL);
1929 return err;
1930 }
1931 } else {
1932 mlx5_flow_namespace_set_peer(ns, NULL);
1933 mlx5_flow_namespace_set_peer(peer_ns, NULL);
1934 }
1935
1936 return 0;
1937}
1938
ac004b83
RD		 1939static int mlx5_esw_offloads_devcom_event(int event,
1940 void *my_data,
1941 void *event_data)
1942{
1943 struct mlx5_eswitch *esw = my_data;
ac004b83 1944 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 1945 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 1946 int err;
1947
1948 switch (event) {
1949 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 1950 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1951 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1952 break;
1953
8463daf1 1954 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 1955 if (err)
1956 goto err_out;
8463daf1
MG		 1957 err = mlx5_esw_offloads_pair(esw, peer_esw);
1958 if (err)
1959 goto err_peer;
ac004b83
RD		 1960
1961 err = mlx5_esw_offloads_pair(peer_esw, esw);
1962 if (err)
1963 goto err_pair;
1964
1965 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1966 break;
1967
1968 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1969 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1970 break;
1971
1972 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1973 mlx5_esw_offloads_unpair(peer_esw);
1974 mlx5_esw_offloads_unpair(esw);
8463daf1 1975 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1976 break;
1977 }
1978
1979 return 0;
1980
1981err_pair:
1982 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 1983err_peer:
1984 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1985err_out:
1986 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1987 event, err);
1988 return err;
1989}
1990
1991static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1992{
1993 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1994
04de7dda
RD		 1995 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1996 mutex_init(&esw->offloads.peer_mutex);
1997
ac004b83
RD		 1998 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1999 return;
2000
2001 mlx5_devcom_register_component(devcom,
2002 MLX5_DEVCOM_ESW_OFFLOADS,
2003 mlx5_esw_offloads_devcom_event,
2004 esw);
2005
2006 mlx5_devcom_send_event(devcom,
2007 MLX5_DEVCOM_ESW_OFFLOADS,
2008 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2009}
2010
2011static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2012{
2013 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2014
2015 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2016 return;
2017
2018 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2019 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2020
2021 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2022}
2023
92ab1eb3
JL		 2024static bool
2025esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
2026{
2027 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2028 return false;
2029
2030 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2031 MLX5_FDB_TO_VPORT_REG_C_0))
2032 return false;
2033
2034 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2035 return false;
2036
2037 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2038 mlx5_ecpf_vport_exists(esw->dev))
2039 return false;
2040
2041 return true;
2042}
2043
133dcfc5
VP		 2044u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2045{
7cd7becd 2046 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2047 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2048 u32 pf_num;
133dcfc5
VP		 2049 int id;
2050
7cd7becd 2051 /* Only 4 bits of pf_num */
2052 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2053 if (pf_num > max_pf_num)
2054 return 0;
133dcfc5 2055
7cd7becd 2056 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2057 /* Use only non-zero vport_id (1-4095) for all PF's */
2058 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2059 if (id < 0)
2060 return 0;
2061 id = (pf_num << ESW_VPORT_BITS) | id;
2062 return id;
133dcfc5
VP		 2063}
2064
2065void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2066{
7cd7becd 2067 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2068
2069 /* Metadata contains only 12 bits of actual ida id */
2070 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2071}
2072
2073static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2074 struct mlx5_vport *vport)
2075{
133dcfc5
VP		 2076 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2077 vport->metadata = vport->default_metadata;
2078 return vport->metadata ? 0 : -ENOSPC;
2079}
2080
2081static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2082 struct mlx5_vport *vport)
2083{
406493a5 2084 if (!vport->default_metadata)
133dcfc5
VP		 2085 return;
2086
2087 WARN_ON(vport->metadata != vport->default_metadata);
2088 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2089}
2090
fc99c3d6
VP		 2091static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2092{
2093 struct mlx5_vport *vport;
2094 int i;
2095
2096 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2097 return;
2098
2099 mlx5_esw_for_all_vports_reverse(esw, i, vport)
2100 esw_offloads_vport_metadata_cleanup(esw, vport);
2101}
2102
2103static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2104{
2105 struct mlx5_vport *vport;
2106 int err;
2107 int i;
2108
2109 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2110 return 0;
2111
2112 mlx5_esw_for_all_vports(esw, i, vport) {
2113 err = esw_offloads_vport_metadata_setup(esw, vport);
2114 if (err)
2115 goto metadata_err;
2116 }
2117
2118 return 0;
2119
2120metadata_err:
2121 esw_offloads_metadata_uninit(esw);
2122 return err;
2123}
2124
748da30b 2125int
89a0f1fb
PP		 2126esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2127 struct mlx5_vport *vport)
7445cfb1 2128{
7445cfb1
JL		 2129 int err;
2130
07bab950 2131 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2132 if (err)
fc99c3d6 2133 return err;
7445cfb1 2134
2c40db2f
PP		 2135 err = esw_acl_egress_ofld_setup(esw, vport);
2136 if (err)
2137 goto egress_err;
07bab950
VP		 2138
2139 return 0;
2140
2141egress_err:
2142 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2143 return err;
2144}
18486737 2145
748da30b 2146void
89a0f1fb
PP		 2147esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2148 struct mlx5_vport *vport)
2149{
ea651a86 2150 esw_acl_egress_ofld_cleanup(vport);
07bab950 2151 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2152}
7445cfb1 2153
748da30b 2154static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2155{
2156 struct mlx5_vport *vport;
18486737 2157
748da30b 2158 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
4e9a9ef7 2159 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2160}
2161
748da30b 2162static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2163{
786ef904 2164 struct mlx5_vport *vport;
7445cfb1 2165
748da30b
VP		 2166 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2167 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2168}
2169
062f4bf4 2170static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a
MB		 2171{
2172 int err;
2173
5c1d260e 2174 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2175 mutex_init(&esw->fdb_table.offloads.vports.lock);
2176 hash_init(esw->fdb_table.offloads.vports.table);
e52c2802 2177
748da30b 2178 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2179 if (err)
f8d1edda 2180 goto create_acl_err;
18486737 2181
8d6bd3c3 2182 err = esw_create_offloads_table(esw);
c930a3ad 2183 if (err)
11b717d6 2184 goto create_offloads_err;
c930a3ad 2185
11b717d6 2186 err = esw_create_restore_table(esw);
c930a3ad 2187 if (err)
11b717d6
PB		 2188 goto create_restore_err;
2189
0da3c12d 2190 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2191 if (err)
2192 goto create_fdb_err;
c930a3ad 2193
8d6bd3c3 2194 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2195 if (err)
2196 goto create_fg_err;
2197
2198 return 0;
2199
2200create_fg_err:
1967ce6e 2201 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2202create_fdb_err:
11b717d6
PB		 2203 esw_destroy_restore_table(esw);
2204create_restore_err:
2205 esw_destroy_offloads_table(esw);
2206create_offloads_err:
748da30b 2207 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda
PP		 2208create_acl_err:
2209 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2210 return err;
2211}
2212
eca8cc38
BW		 2213static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2214{
2215 esw_destroy_vport_rx_group(esw);
eca8cc38 2216 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2217 esw_destroy_restore_table(esw);
2218 esw_destroy_offloads_table(esw);
748da30b 2219 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2220 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2221}
2222
7e736f9a
PP		 2223static void
2224esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2225{
5ccf2770 2226 bool host_pf_disabled;
7e736f9a 2227 u16 new_num_vfs;
a3888f33 2228
7e736f9a
PP		 2229 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2230 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2231 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2232 host_params_context.host_pf_disabled);
a3888f33 2233
7e736f9a
PP		 2234 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2235 return;
a3888f33
BW		 2236
2237 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2238 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2239 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2240 } else {
7e736f9a 2241 int err;
a3888f33 2242
23bb50cf
BW		 2243 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2244 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2245 if (err)
7e736f9a 2246 return;
a3888f33 2247 }
7e736f9a 2248 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2249}
2250
7e736f9a 2251static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2252{
7e736f9a
PP		 2253 struct mlx5_host_work *host_work;
2254 struct mlx5_eswitch *esw;
dd28087c 2255 const u32 *out;
ac35dcd6 2256
7e736f9a
PP		 2257 host_work = container_of(work, struct mlx5_host_work, work);
2258 esw = host_work->esw;
a3888f33 2259
dd28087c
PP		 2260 out = mlx5_esw_query_functions(esw->dev);
2261 if (IS_ERR(out))
7e736f9a 2262 goto out;
a3888f33 2263
7e736f9a 2264 esw_vfs_changed_event_handler(esw, out);
dd28087c 2265 kvfree(out);
a3888f33 2266out:
ac35dcd6
VP		 2267 kfree(host_work);
2268}
2269
16fff98a 2270int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2271{
cd56f929 2272 struct mlx5_esw_functions *esw_funcs;
a3888f33 2273 struct mlx5_host_work *host_work;
a3888f33
BW		 2274 struct mlx5_eswitch *esw;
2275
2276 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2277 if (!host_work)
2278 return NOTIFY_DONE;
2279
cd56f929
VP		 2280 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2281 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2282
2283 host_work->esw = esw;
2284
062f4bf4 2285 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2286 queue_work(esw->work_queue, &host_work->work);
2287
2288 return NOTIFY_OK;
2289}
2290
a53cf949
PP		 2291static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2292{
2293 const u32 *query_host_out;
2294
2295 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2296 return 0;
2297
2298 query_host_out = mlx5_esw_query_functions(esw->dev);
2299 if (IS_ERR(query_host_out))
2300 return PTR_ERR(query_host_out);
2301
2302 /* Mark non local controller with non zero controller number. */
2303 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2304 host_params_context.host_number);
2305 kvfree(query_host_out);
2306 return 0;
2307}
2308
5896b972 2309int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2310{
3b83b6c2
DL		 2311 struct mlx5_vport *vport;
2312 int err, i;
eca8cc38 2313
9a64144d
MG		 2314 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2315 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2316 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2317 else
2318 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2319
2bb72e7e 2320 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2321 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2322
a53cf949
PP		 2323 err = mlx5_esw_host_number_init(esw);
2324 if (err)
cd1ef966 2325 goto err_metadata;
a53cf949 2326
cd1ef966 2327 if (esw_check_vport_match_metadata_supported(esw))
4e9a9ef7
VP		 2328 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2329
fc99c3d6
VP		 2330 err = esw_offloads_metadata_init(esw);
2331 if (err)
2332 goto err_metadata;
2333
332bd3a5
PP		 2334 err = esw_set_passing_vport_metadata(esw, true);
2335 if (err)
2336 goto err_vport_metadata;
c1286050 2337
7983a675
PB		 2338 err = esw_offloads_steering_init(esw);
2339 if (err)
2340 goto err_steering_init;
2341
3b83b6c2
DL		 2342 /* Representor will control the vport link state */
2343 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2344 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2345
c2d7712c
BW		 2346 /* Uplink vport rep must load first. */
2347 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2348 if (err)
c2d7712c 2349 goto err_uplink;
c1286050 2350
c2d7712c 2351 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2352 if (err)
c2d7712c 2353 goto err_vports;
eca8cc38
BW		 2354
2355 esw_offloads_devcom_init(esw);
a3888f33 2356
eca8cc38
BW		 2357 return 0;
2358
925a6acc 2359err_vports:
c2d7712c
BW		 2360 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2361err_uplink:
7983a675 2362 esw_offloads_steering_cleanup(esw);
79949985
PP		 2363err_steering_init:
2364 esw_set_passing_vport_metadata(esw, false);
7983a675 2365err_vport_metadata:
fc99c3d6
VP		 2366 esw_offloads_metadata_uninit(esw);
2367err_metadata:
4e9a9ef7 2368 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2369 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2370 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2371 return err;
2372}
2373
db7ff19e
EB		 2374static int esw_offloads_stop(struct mlx5_eswitch *esw,
2375 struct netlink_ext_ack *extack)
c930a3ad 2376{
062f4bf4 2377 int err, err1;
c930a3ad 2378
8e0aa4bc
PP		 2379 mlx5_eswitch_disable_locked(esw, false);
2380 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2381 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2382 if (err) {
8c98ee77 2383 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2384 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2385 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2386 if (err1) {
2387 NL_SET_ERR_MSG_MOD(extack,
2388 "Failed setting eswitch back to offloads");
2389 }
6c419ba8 2390 }
c930a3ad
OG		 2391
2392 return err;
2393}
2394
5896b972 2395void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2396{
ac004b83 2397 esw_offloads_devcom_cleanup(esw);
5896b972 2398 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2399 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2400 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2401 esw_offloads_steering_cleanup(esw);
fc99c3d6 2402 esw_offloads_metadata_uninit(esw);
4e9a9ef7 2403 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2404 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2405 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2406 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2407}
2408
ef78618b 2409static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2410{
2411 switch (mode) {
2412 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2413 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2414 break;
2415 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2416 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2417 break;
2418 default:
2419 return -EINVAL;
2420 }
2421
2422 return 0;
2423}
2424
ef78618b
OG		 2425static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2426{
2427 switch (mlx5_mode) {
f6455de0 2428 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2429 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2430 break;
f6455de0 2431 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2432 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2433 break;
2434 default:
2435 return -EINVAL;
2436 }
2437
2438 return 0;
2439}
2440
bffaa916
RD		 2441static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2442{
2443 switch (mode) {
2444 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2445 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2446 break;
2447 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2448 *mlx5_mode = MLX5_INLINE_MODE_L2;
2449 break;
2450 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2451 *mlx5_mode = MLX5_INLINE_MODE_IP;
2452 break;
2453 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2454 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2455 break;
2456 default:
2457 return -EINVAL;
2458 }
2459
2460 return 0;
2461}
2462
2463static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2464{
2465 switch (mlx5_mode) {
2466 case MLX5_INLINE_MODE_NONE:
2467 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2468 break;
2469 case MLX5_INLINE_MODE_L2:
2470 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2471 break;
2472 case MLX5_INLINE_MODE_IP:
2473 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2474 break;
2475 case MLX5_INLINE_MODE_TCP_UDP:
2476 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2477 break;
2478 default:
2479 return -EINVAL;
2480 }
2481
2482 return 0;
2483}
2484
ae24432c
PP		 2485static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2486{
2487 /* devlink commands in NONE eswitch mode are currently supported only
2488 * on ECPF.
2489 */
2490 return (esw->mode == MLX5_ESWITCH_NONE &&
2491 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2492}
2493
db7ff19e
EB		 2494int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2495 struct netlink_ext_ack *extack)
9d1cef19 2496{
9d1cef19 2497 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2498 struct mlx5_eswitch *esw;
ea2128fd 2499 int err = 0;
9d1cef19 2500
bd939753
PP		 2501 esw = mlx5_devlink_eswitch_get(devlink);
2502 if (IS_ERR(esw))
2503 return PTR_ERR(esw);
9d1cef19 2504
ef78618b 2505 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2506 return -EINVAL;
2507
8e0aa4bc 2508 mutex_lock(&esw->mode_lock);
8e0aa4bc 2509 cur_mlx5_mode = esw->mode;
c930a3ad 2510 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 2511 goto unlock;
c930a3ad
OG		 2512
2513 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 2514 err = esw_offloads_start(esw, extack);
c930a3ad 2515 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 2516 err = esw_offloads_stop(esw, extack);
c930a3ad 2517 else
8e0aa4bc
PP		 2518 err = -EINVAL;
2519
2520unlock:
2521 mutex_unlock(&esw->mode_lock);
2522 return err;
feae9087
OG		 2523}
2524
2525int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2526{
bd939753 2527 struct mlx5_eswitch *esw;
9d1cef19 2528 int err;
c930a3ad 2529
bd939753
PP		 2530 esw = mlx5_devlink_eswitch_get(devlink);
2531 if (IS_ERR(esw))
2532 return PTR_ERR(esw);
c930a3ad 2533
8e0aa4bc 2534 mutex_lock(&esw->mode_lock);
bd939753 2535 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 2536 if (err)
8e0aa4bc 2537 goto unlock;
ae24432c 2538
8e0aa4bc
PP		 2539 err = esw_mode_to_devlink(esw->mode, mode);
2540unlock:
2541 mutex_unlock(&esw->mode_lock);
2542 return err;
feae9087 2543}
127ea380 2544
db7ff19e
EB		 2545int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2546 struct netlink_ext_ack *extack)
bffaa916
RD		 2547{
2548 struct mlx5_core_dev *dev = devlink_priv(devlink);
db68cc56 2549 int err, vport, num_vport;
bd939753 2550 struct mlx5_eswitch *esw;
bffaa916
RD		 2551 u8 mlx5_mode;
2552
bd939753
PP		 2553 esw = mlx5_devlink_eswitch_get(devlink);
2554 if (IS_ERR(esw))
2555 return PTR_ERR(esw);
bffaa916 2556
8e0aa4bc 2557 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2558 err = eswitch_devlink_esw_mode_check(esw);
2559 if (err)
8e0aa4bc 2560 goto out;
ae24432c 2561
c415f704
OG		 2562 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2563 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2564 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 2565 goto out;
c8b838d1 2566 fallthrough;
c415f704 2567 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 2568 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 2569 err = -EOPNOTSUPP;
2570 goto out;
c415f704
OG		 2571 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2572 break;
2573 }
bffaa916 2574
525e84be 2575 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2576 NL_SET_ERR_MSG_MOD(extack,
2577 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 2578 err = -EOPNOTSUPP;
2579 goto out;
375f51e2
RD		 2580 }
2581
bffaa916
RD		 2582 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2583 if (err)
2584 goto out;
2585
411ec9e0 2586 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
bffaa916
RD		 2587 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2588 if (err) {
8c98ee77
EB		 2589 NL_SET_ERR_MSG_MOD(extack,
2590 "Failed to set min inline on vport");
bffaa916
RD		 2591 goto revert_inline_mode;
2592 }
2593 }
2594
2595 esw->offloads.inline_mode = mlx5_mode;
8e0aa4bc 2596 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2597 return 0;
2598
2599revert_inline_mode:
db68cc56 2600 num_vport = --vport;
411ec9e0 2601 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
bffaa916
RD		 2602 mlx5_modify_nic_vport_min_inline(dev,
2603 vport,
2604 esw->offloads.inline_mode);
2605out:
8e0aa4bc 2606 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2607 return err;
2608}
2609
2610int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2611{
bd939753 2612 struct mlx5_eswitch *esw;
9d1cef19 2613 int err;
bffaa916 2614
bd939753
PP		 2615 esw = mlx5_devlink_eswitch_get(devlink);
2616 if (IS_ERR(esw))
2617 return PTR_ERR(esw);
bffaa916 2618
8e0aa4bc 2619 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2620 err = eswitch_devlink_esw_mode_check(esw);
2621 if (err)
8e0aa4bc 2622 goto unlock;
ae24432c 2623
8e0aa4bc
PP		 2624 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2625unlock:
2626 mutex_unlock(&esw->mode_lock);
2627 return err;
bffaa916
RD		 2628}
2629
98fdbea5
LR		 2630int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2631 enum devlink_eswitch_encap_mode encap,
db7ff19e 2632 struct netlink_ext_ack *extack)
7768d197
RD		 2633{
2634 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 2635 struct mlx5_eswitch *esw;
7768d197
RD		 2636 int err;
2637
bd939753
PP		 2638 esw = mlx5_devlink_eswitch_get(devlink);
2639 if (IS_ERR(esw))
2640 return PTR_ERR(esw);
7768d197 2641
8e0aa4bc 2642 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2643 err = eswitch_devlink_esw_mode_check(esw);
2644 if (err)
8e0aa4bc 2645 goto unlock;
ae24432c 2646
7768d197 2647 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 2648 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 2649 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
2650 err = -EOPNOTSUPP;
2651 goto unlock;
2652 }
7768d197 2653
8e0aa4bc
PP		 2654 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
2655 err = -EOPNOTSUPP;
2656 goto unlock;
2657 }
7768d197 2658
f6455de0 2659 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 2660 esw->offloads.encap = encap;
8e0aa4bc 2661 goto unlock;
7768d197
RD		 2662 }
2663
2664 if (esw->offloads.encap == encap)
8e0aa4bc 2665 goto unlock;
7768d197 2666
525e84be 2667 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2668 NL_SET_ERR_MSG_MOD(extack,
2669 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 2670 err = -EOPNOTSUPP;
2671 goto unlock;
7768d197
RD		 2672 }
2673
e52c2802 2674 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 2675
2676 esw->offloads.encap = encap;
e52c2802 2677
0da3c12d 2678 err = esw_create_offloads_fdb_tables(esw);
e52c2802 2679
7768d197 2680 if (err) {
8c98ee77
EB		 2681 NL_SET_ERR_MSG_MOD(extack,
2682 "Failed re-creating fast FDB table");
7768d197 2683 esw->offloads.encap = !encap;
0da3c12d 2684 (void)esw_create_offloads_fdb_tables(esw);
7768d197 2685 }
e52c2802 2686
8e0aa4bc
PP		 2687unlock:
2688 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2689 return err;
2690}
2691
98fdbea5
LR		 2692int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2693 enum devlink_eswitch_encap_mode *encap)
7768d197 2694{
bd939753 2695 struct mlx5_eswitch *esw;
9d1cef19 2696 int err;
7768d197 2697
bd939753
PP		 2698 esw = mlx5_devlink_eswitch_get(devlink);
2699 if (IS_ERR(esw))
2700 return PTR_ERR(esw);
2701
7768d197 2702
8e0aa4bc 2703 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2704 err = eswitch_devlink_esw_mode_check(esw);
2705 if (err)
8e0aa4bc 2706 goto unlock;
ae24432c 2707
7768d197 2708 *encap = esw->offloads.encap;
8e0aa4bc
PP		 2709unlock:
2710 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2711 return 0;
2712}
2713
c2d7712c
BW		 2714static bool
2715mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
2716{
2717 /* Currently, only ECPF based device has representor for host PF. */
2718 if (vport_num == MLX5_VPORT_PF &&
2719 !mlx5_core_is_ecpf_esw_manager(esw->dev))
2720 return false;
2721
2722 if (vport_num == MLX5_VPORT_ECPF &&
2723 !mlx5_ecpf_vport_exists(esw->dev))
2724 return false;
2725
2726 return true;
2727}
2728
f8e8fa02 2729void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 2730 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 2731 u8 rep_type)
127ea380 2732{
8693115a 2733 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02
BW		 2734 struct mlx5_eswitch_rep *rep;
2735 int i;
9deb2241 2736
8693115a 2737 esw->offloads.rep_ops[rep_type] = ops;
f8e8fa02 2738 mlx5_esw_for_all_reps(esw, i, rep) {
c2d7712c
BW		 2739 if (likely(mlx5_eswitch_vport_has_rep(esw, i))) {
2740 rep_data = &rep->rep_data[rep_type];
2741 atomic_set(&rep_data->state, REP_REGISTERED);
2742 }
f8e8fa02 2743 }
127ea380 2744}
f8e8fa02 2745EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 2746
f8e8fa02 2747void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 2748{
cb67b832 2749 struct mlx5_eswitch_rep *rep;
f8e8fa02 2750 int i;
cb67b832 2751
f6455de0 2752 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 2753 __unload_reps_all_vport(esw, rep_type);
127ea380 2754
f8e8fa02 2755 mlx5_esw_for_all_reps(esw, i, rep)
8693115a 2756 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 2757}
f8e8fa02 2758EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 2759
a4b97ab4 2760void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 2761{
726293f1
HHZ		 2762 struct mlx5_eswitch_rep *rep;
2763
879c8f84 2764 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 2765 return rep->rep_data[rep_type].priv;
726293f1 2766}
22215908
MB		 2767
2768void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 2769 u16 vport,
22215908
MB		 2770 u8 rep_type)
2771{
22215908
MB		 2772 struct mlx5_eswitch_rep *rep;
2773
879c8f84 2774 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 2775
8693115a
PP		 2776 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2777 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2778 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 2779 return NULL;
2780}
57cbd893 2781EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 2782
2783void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2784{
879c8f84 2785 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 2786}
57cbd893
MB		 2787EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2788
2789struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 2790 u16 vport)
57cbd893 2791{
879c8f84 2792 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 2793}
2794EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c
PP		 2795
2796bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2797{
2798 return vport_num >= MLX5_VPORT_FIRST_VF &&
2799 vport_num <= esw->dev->priv.sriov.max_vfs;
2800}
7445cfb1 2801
5b7cb745
PB		 2802bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
2803{
2804 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
2805}
2806EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
2807
7445cfb1
JL		 2808bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2809{
2810 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2811}
2812EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2813
0f0d3827 2814u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 2815 u16 vport_num)
2816{
133dcfc5 2817 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 2818
133dcfc5
VP		 2819 if (WARN_ON_ONCE(IS_ERR(vport)))
2820 return 0;
0f0d3827 2821
133dcfc5 2822 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 2823}
2824EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
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