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CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
c85a6b8f 51#include "devlink.h"
69697b6e 52
47dd7e60
PP		 53#define mlx5_esw_for_each_rep(esw, i, rep) \
54 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
55
56#define mlx5_esw_for_each_sf_rep(esw, i, rep) \
57 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
58
59#define mlx5_esw_for_each_vf_rep(esw, index, rep) \
60 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
61 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
62
cd7e4186
BW		 63/* There are two match-all miss flows, one for unicast dst mac and
64 * one for multicast.
65 */
66#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 67#define UPLINK_REP_INDEX 0
68
c796bb7c
CM		 69#define MLX5_ESW_VPORT_TBL_SIZE 128
70#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
71
72static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
73 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
74 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
75 .flags = 0,
76};
77
879c8f84
BW		 78static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
79 u16 vport_num)
80{
47dd7e60 81 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 82}
83
6f7bbad1
JL		 84static void
85mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
86 struct mlx5_flow_spec *spec,
87 struct mlx5_esw_flow_attr *attr)
88{
89 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
036e19b9
HI		 90 attr && attr->in_rep)
91 spec->flow_context.flow_source =
92 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
93 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
94 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 95}
b7826076 96
f94d6389
CM		 97/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
98 * are not needed as well in the following process. So clear them all for simplicity.
99 */
100void
101mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
102{
103 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
104 void *misc2;
105
106 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
107 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
108
109 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
110 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
111
112 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
113 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
114 }
115}
116
c01cfd0f
JL		 117static void
118mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
119 struct mlx5_flow_spec *spec,
a508728a 120 struct mlx5_flow_attr *attr,
b055ecf5
MB		 121 struct mlx5_eswitch *src_esw,
122 u16 vport)
c01cfd0f
JL		 123{
124 void *misc2;
125 void *misc;
126
127 /* Use metadata matching because vport is not represented by single
128 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
129 */
130 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 131 if (mlx5_esw_indir_table_decap_vport(attr))
132 vport = mlx5_esw_indir_table_decap_vport(attr);
c01cfd0f
JL		 133 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
134 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
b055ecf5
MB		 135 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
136 vport));
c01cfd0f
JL		 137
138 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 139 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
140 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 141
142 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 143 } else {
144 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 145 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 146
147 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
148 MLX5_SET(fte_match_set_misc, misc,
149 source_eswitch_owner_vhca_id,
b055ecf5 150 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 151
152 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
153 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
154 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
155 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
156 source_eswitch_owner_vhca_id);
157
158 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
159 }
c01cfd0f
JL		 160}
161
a508728a
VB		 162static int
163esw_setup_decap_indir(struct mlx5_eswitch *esw,
164 struct mlx5_flow_attr *attr,
165 struct mlx5_flow_spec *spec)
166{
167 struct mlx5_flow_table *ft;
168
169 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
170 return -EOPNOTSUPP;
171
172 ft = mlx5_esw_indir_table_get(esw, attr, spec,
173 mlx5_esw_indir_table_decap_vport(attr), true);
174 return PTR_ERR_OR_ZERO(ft);
175}
176
9e51c0a6 177static void
a508728a
VB		 178esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
179 struct mlx5_flow_attr *attr)
180{
181 if (mlx5_esw_indir_table_decap_vport(attr))
182 mlx5_esw_indir_table_put(esw, attr,
183 mlx5_esw_indir_table_decap_vport(attr),
184 true);
185}
186
f94d6389
CM		 187static int
188esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
189 struct mlx5_flow_act *flow_act,
bcd6740c 190 struct mlx5_flow_attr *attr,
f94d6389
CM		 191 int i)
192{
193 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
194 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
bcd6740c 195 dest[i].sampler_id = attr->sample_attr->sampler_id;
f94d6389
CM		 196
197 return 0;
198}
199
a508728a 200static int
9e51c0a6
VB		 201esw_setup_ft_dest(struct mlx5_flow_destination *dest,
202 struct mlx5_flow_act *flow_act,
a508728a 203 struct mlx5_eswitch *esw,
9e51c0a6 204 struct mlx5_flow_attr *attr,
a508728a 205 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 206 int i)
207{
208 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
209 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
210 dest[i].ft = attr->dest_ft;
a508728a
VB		 211
212 if (mlx5_esw_indir_table_decap_vport(attr))
213 return esw_setup_decap_indir(esw, attr, spec);
214 return 0;
9e51c0a6
VB		 215}
216
217static void
218esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,
219 struct mlx5_flow_act *flow_act,
220 struct mlx5_fs_chains *chains,
221 int i)
222{
2a2c84fa
RD		 223 if (mlx5_chains_ignore_flow_level_supported(chains))
224 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
9e51c0a6
VB		 225 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
226 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
227}
228
229static int
230esw_setup_chain_dest(struct mlx5_flow_destination *dest,
231 struct mlx5_flow_act *flow_act,
232 struct mlx5_fs_chains *chains,
233 u32 chain, u32 prio, u32 level,
234 int i)
235{
236 struct mlx5_flow_table *ft;
237
238 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
239 ft = mlx5_chains_get_table(chains, chain, prio, level);
240 if (IS_ERR(ft))
241 return PTR_ERR(ft);
242
243 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
244 dest[i].ft = ft;
245 return 0;
246}
247
10742efc
VB		 248static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
249 int from, int to)
250{
251 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
252 struct mlx5_fs_chains *chains = esw_chains(esw);
253 int i;
254
255 for (i = from; i < to; i++)
256 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
257 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 258 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
259 esw_attr->dests[i].mdev))
260 mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport,
261 false);
10742efc
VB		 262}
263
264static bool
265esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
266{
267 int i;
268
269 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
270 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
271 return true;
272 return false;
273}
274
275static int
276esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
277 struct mlx5_flow_act *flow_act,
278 struct mlx5_eswitch *esw,
279 struct mlx5_fs_chains *chains,
280 struct mlx5_flow_attr *attr,
281 int *i)
282{
283 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
284 int j, err;
285
286 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
287 return -EOPNOTSUPP;
288
289 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
290 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
291 if (err)
292 goto err_setup_chain;
293 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
294 flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat;
295 }
296 return 0;
297
298err_setup_chain:
299 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
300 return err;
301}
302
303static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
304 struct mlx5_flow_attr *attr)
305{
306 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
307
308 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
309}
310
a508728a
VB		 311static bool
312esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
313{
314 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
315 int i;
316
317 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
318 if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
319 esw_attr->dests[i].mdev))
320 return true;
321 return false;
322}
323
324static int
325esw_setup_indir_table(struct mlx5_flow_destination *dest,
326 struct mlx5_flow_act *flow_act,
327 struct mlx5_eswitch *esw,
328 struct mlx5_flow_attr *attr,
329 struct mlx5_flow_spec *spec,
330 bool ignore_flow_lvl,
331 int *i)
332{
333 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
334 int j, err;
335
336 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
337 return -EOPNOTSUPP;
338
339 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
340 if (ignore_flow_lvl)
341 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
342 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
343
344 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec,
345 esw_attr->dests[j].rep->vport, false);
346 if (IS_ERR(dest[*i].ft)) {
347 err = PTR_ERR(dest[*i].ft);
348 goto err_indir_tbl_get;
349 }
350 }
351
352 if (mlx5_esw_indir_table_decap_vport(attr)) {
353 err = esw_setup_decap_indir(esw, attr, spec);
354 if (err)
355 goto err_indir_tbl_get;
356 }
357
358 return 0;
359
360err_indir_tbl_get:
361 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
362 return err;
363}
364
365static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
366{
367 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
368
369 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
370 esw_cleanup_decap_indir(esw, attr);
371}
372
9e51c0a6
VB		 373static void
374esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
375{
376 mlx5_chains_put_table(chains, chain, prio, level);
377}
378
379static void
380esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
381 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
382 int attr_idx, int dest_idx, bool pkt_reformat)
383{
384 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
385 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
c6719725
MD		 386 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
387 dest[dest_idx].vport.vhca_id =
388 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
9e51c0a6 389 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
c6719725 390 }
9e51c0a6
VB		 391 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
392 if (pkt_reformat) {
393 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
394 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
395 }
396 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
397 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
398 }
399}
400
401static int
402esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
403 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
404 int i)
405{
406 int j;
407
408 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
409 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
410 return i;
411}
412
e929e3da
MD		 413static bool
414esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
415{
416 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
417 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
418 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
419}
420
9e51c0a6
VB		 421static int
422esw_setup_dests(struct mlx5_flow_destination *dest,
423 struct mlx5_flow_act *flow_act,
424 struct mlx5_eswitch *esw,
425 struct mlx5_flow_attr *attr,
10742efc 426 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 427 int *i)
428{
429 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
430 struct mlx5_fs_chains *chains = esw_chains(esw);
431 int err = 0;
432
10742efc 433 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 434 esw_src_port_rewrite_supported(esw))
10742efc
VB		 435 attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE;
436
f94d6389 437 if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) {
bcd6740c 438 esw_setup_sampler_dest(dest, flow_act, attr, *i);
f94d6389
CM		 439 (*i)++;
440 } else if (attr->dest_ft) {
a508728a 441 esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);
9e51c0a6 442 (*i)++;
d557fbbd 443 } else if (mlx5_esw_attr_flags_skip(attr->flags)) {
9e51c0a6
VB		 444 esw_setup_slow_path_dest(dest, flow_act, chains, *i);
445 (*i)++;
446 } else if (attr->dest_chain) {
447 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
448 1, 0, *i);
449 (*i)++;
a508728a
VB		 450 } else if (esw_is_indir_table(esw, attr)) {
451 err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i);
10742efc
VB		 452 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
453 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 454 } else {
455 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
456 }
457
458 return err;
459}
460
461static void
462esw_cleanup_dests(struct mlx5_eswitch *esw,
463 struct mlx5_flow_attr *attr)
464{
10742efc 465 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 466 struct mlx5_fs_chains *chains = esw_chains(esw);
467
a508728a
VB		 468 if (attr->dest_ft) {
469 esw_cleanup_decap_indir(esw, attr);
d557fbbd 470 } else if (!mlx5_esw_attr_flags_skip(attr->flags)) {
10742efc
VB		 471 if (attr->dest_chain)
472 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 473 else if (esw_is_indir_table(esw, attr))
474 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 475 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
476 esw_cleanup_chain_src_port_rewrite(esw, attr);
477 }
9e51c0a6
VB		 478}
479
74491de9 480struct mlx5_flow_handle *
3d80d1a2
OG		 481mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
482 struct mlx5_flow_spec *spec,
c620b772 483 struct mlx5_flow_attr *attr)
3d80d1a2 484{
592d3651 485 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 486 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 487 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 488 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 489 bool split = !!(esw_attr->split_count);
490 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 491 struct mlx5_flow_handle *rule;
e52c2802 492 struct mlx5_flow_table *fdb;
9e51c0a6 493 int i = 0;
3d80d1a2 494
f6455de0 495 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 496 return ERR_PTR(-EOPNOTSUPP);
497
6acfbf38
OG		 498 flow_act.action = attr->action;
499 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 500 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 501 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
502 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
503 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 504 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
505 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
506 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 507 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 508 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
509 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
510 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 511 }
6acfbf38 512 }
776b12b6 513
10742efc
VB		 514 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
515
66958ed9 516 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 517 int err;
518
10742efc 519 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 520 if (err) {
521 rule = ERR_PTR(err);
522 goto err_create_goto_table;
56e858df 523 }
e37a79e5 524 }
14e6b038 525
c620b772
AL		 526 if (esw_attr->decap_pkt_reformat)
527 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 528
66958ed9 529 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 530 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 531 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 532 i++;
3d80d1a2
OG		 533 }
534
93b3586e 535 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 536 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 537 if (attr->inner_match_level != MLX5_MATCH_NONE)
538 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 539
aa24670e 540 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 541 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 542
2741f223 543 if (split) {
c620b772
AL		 544 fwd_attr.chain = attr->chain;
545 fwd_attr.prio = attr->prio;
546 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 547 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 548
0a9e2307 549 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 550 } else {
d18296ff 551 if (attr->chain || attr->prio)
ae430332
AL		 552 fdb = mlx5_chains_get_table(chains, attr->chain,
553 attr->prio, 0);
d18296ff 554 else
c620b772 555 fdb = attr->ft;
6fb0701a
PB		 556
557 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
a508728a 558 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 559 esw_attr->in_mdev->priv.eswitch,
560 esw_attr->in_rep->vport);
96e32687 561 }
e52c2802
PB		 562 if (IS_ERR(fdb)) {
563 rule = ERR_CAST(fdb);
564 goto err_esw_get;
565 }
566
84be2fda 567 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 568 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 569 &flow_act, dest, i);
84be2fda 570 else
10caabda 571 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 572 if (IS_ERR(rule))
e52c2802 573 goto err_add_rule;
375f51e2 574 else
525e84be 575 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 576
e52c2802
PB		 577 return rule;
578
579err_add_rule:
96e32687 580 if (split)
0a9e2307 581 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 582 else if (attr->chain || attr->prio)
ae430332 583 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 584err_esw_get:
9e51c0a6 585 esw_cleanup_dests(esw, attr);
e52c2802 586err_create_goto_table:
aa0cbbae 587 return rule;
3d80d1a2
OG		 588}
589
e4ad91f2
CM		 590struct mlx5_flow_handle *
591mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
592 struct mlx5_flow_spec *spec,
c620b772 593 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 594{
595 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 596 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 597 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 598 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 599 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 600 struct mlx5_flow_table *fast_fdb;
601 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 602 struct mlx5_flow_handle *rule;
10742efc 603 int i, err = 0;
e4ad91f2 604
ae430332 605 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 606 if (IS_ERR(fast_fdb)) {
607 rule = ERR_CAST(fast_fdb);
608 goto err_get_fast;
609 }
610
c620b772
AL		 611 fwd_attr.chain = attr->chain;
612 fwd_attr.prio = attr->prio;
613 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 614 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 615 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 616 if (IS_ERR(fwd_fdb)) {
617 rule = ERR_CAST(fwd_fdb);
618 goto err_get_fwd;
619 }
620
e4ad91f2 621 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 622 for (i = 0; i < esw_attr->split_count; i++) {
a508728a
VB		 623 if (esw_is_indir_table(esw, attr))
624 err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i);
625 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
10742efc
VB		 626 err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr,
627 &i);
628 else
629 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
630
631 if (err) {
632 rule = ERR_PTR(err);
633 goto err_chain_src_rewrite;
634 }
635 }
e4ad91f2 636 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 637 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 638 i++;
639
a508728a 640 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 641 esw_attr->in_mdev->priv.eswitch,
642 esw_attr->in_rep->vport);
e4ad91f2 643
93b3586e 644 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 645 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 646
278d51f2 647 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 648 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 649
10742efc
VB		 650 if (IS_ERR(rule)) {
651 i = esw_attr->split_count;
652 goto err_chain_src_rewrite;
653 }
e4ad91f2 654
525e84be 655 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 656
657 return rule;
10742efc
VB		 658err_chain_src_rewrite:
659 esw_put_dest_tables_loop(esw, attr, 0, i);
0a9e2307 660 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 661err_get_fwd:
ae430332 662 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 663err_get_fast:
e4ad91f2
CM		 664 return rule;
665}
666
e52c2802
PB		 667static void
668__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
669 struct mlx5_flow_handle *rule,
c620b772 670 struct mlx5_flow_attr *attr,
e52c2802
PB		 671 bool fwd_rule)
672{
c620b772 673 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 674 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 675 bool split = (esw_attr->split_count > 0);
676 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 677 int i;
e52c2802
PB		 678
679 mlx5_del_flow_rules(rule);
10caabda 680
d557fbbd 681 if (!mlx5_esw_attr_flags_skip(attr->flags)) {
d8a2034f
EC		 682 /* unref the term table */
683 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 684 if (esw_attr->dests[i].termtbl)
685 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 686 }
10caabda
OS		 687 }
688
525e84be 689 atomic64_dec(&esw->offloads.num_flows);
e52c2802 690
c620b772
AL		 691 if (fwd_rule || split) {
692 fwd_attr.chain = attr->chain;
693 fwd_attr.prio = attr->prio;
694 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 695 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 696 }
697
e52c2802 698 if (fwd_rule) {
0a9e2307 699 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 700 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
10742efc 701 esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count);
e52c2802 702 } else {
96e32687 703 if (split)
0a9e2307 704 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 705 else if (attr->chain || attr->prio)
ae430332 706 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 707 esw_cleanup_dests(esw, attr);
e52c2802
PB		 708 }
709}
710
d85cdccb
OG		 711void
712mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
713 struct mlx5_flow_handle *rule,
c620b772 714 struct mlx5_flow_attr *attr)
d85cdccb 715{
e52c2802 716 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 717}
718
48265006
OG		 719void
720mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
721 struct mlx5_flow_handle *rule,
c620b772 722 struct mlx5_flow_attr *attr)
48265006 723{
e52c2802 724 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 725}
726
f5f82476
OG		 727static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
728{
729 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 730 unsigned long i;
731 int err = 0;
f5f82476
OG		 732
733 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
47dd7e60 734 mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 735 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 736 continue;
737
738 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
739 if (err)
740 goto out;
741 }
742
743out:
744 return err;
745}
746
747static struct mlx5_eswitch_rep *
748esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
749{
750 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
751
752 in_rep = attr->in_rep;
df65a573 753 out_rep = attr->dests[0].rep;
f5f82476
OG		 754
755 if (push)
756 vport = in_rep;
757 else if (pop)
758 vport = out_rep;
759 else
760 vport = in_rep;
761
762 return vport;
763}
764
765static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
766 bool push, bool pop, bool fwd)
767{
768 struct mlx5_eswitch_rep *in_rep, *out_rep;
769
770 if ((push || pop) && !fwd)
771 goto out_notsupp;
772
773 in_rep = attr->in_rep;
df65a573 774 out_rep = attr->dests[0].rep;
f5f82476 775
b05af6aa 776 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 777 goto out_notsupp;
778
b05af6aa 779 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 780 goto out_notsupp;
781
782 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
783 if (!push && !pop && fwd)
b05af6aa 784 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 785 goto out_notsupp;
786
787 /* protects against (1) setting rules with different vlans to push and
788 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
789 */
1482bd3d 790 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 791 goto out_notsupp;
792
793 return 0;
794
795out_notsupp:
9eb78923 796 return -EOPNOTSUPP;
f5f82476
OG		 797}
798
799int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 800 struct mlx5_flow_attr *attr)
f5f82476
OG		 801{
802 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 803 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 804 struct mlx5_eswitch_rep *vport = NULL;
805 bool push, pop, fwd;
806 int err = 0;
807
6acfbf38 808 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 809 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 810 return 0;
811
f5f82476
OG		 812 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
813 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 814 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
815 !attr->dest_chain);
f5f82476 816
0e18134f
VB		 817 mutex_lock(&esw->state_lock);
818
c620b772 819 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 820 if (err)
0e18134f 821 goto unlock;
f5f82476 822
39ac237c 823 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 824
c620b772 825 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 826
827 if (!push && !pop && fwd) {
828 /* tracks VF --> wire rules without vlan push action */
c620b772 829 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 830 vport->vlan_refcount++;
39ac237c 831 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 832 }
833
0e18134f 834 goto unlock;
f5f82476
OG		 835 }
836
837 if (!push && !pop)
0e18134f 838 goto unlock;
f5f82476
OG		 839
840 if (!(offloads->vlan_push_pop_refcount)) {
841 /* it's the 1st vlan rule, apply global vlan pop policy */
842 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
843 if (err)
844 goto out;
845 }
846 offloads->vlan_push_pop_refcount++;
847
848 if (push) {
849 if (vport->vlan_refcount)
850 goto skip_set_push;
851
c620b772
AL		 852 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
853 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 854 if (err)
855 goto out;
c620b772 856 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 857skip_set_push:
858 vport->vlan_refcount++;
859 }
860out:
861 if (!err)
39ac237c 862 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 863unlock:
864 mutex_unlock(&esw->state_lock);
f5f82476
OG		 865 return err;
866}
867
868int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 869 struct mlx5_flow_attr *attr)
f5f82476
OG		 870{
871 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 872 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 873 struct mlx5_eswitch_rep *vport = NULL;
874 bool push, pop, fwd;
875 int err = 0;
876
6acfbf38 877 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 878 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 879 return 0;
880
39ac237c 881 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 882 return 0;
883
884 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
885 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
886 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
887
0e18134f
VB		 888 mutex_lock(&esw->state_lock);
889
c620b772 890 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 891
892 if (!push && !pop && fwd) {
893 /* tracks VF --> wire rules without vlan push action */
c620b772 894 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 895 vport->vlan_refcount--;
896
0e18134f 897 goto out;
f5f82476
OG		 898 }
899
900 if (push) {
901 vport->vlan_refcount--;
902 if (vport->vlan_refcount)
903 goto skip_unset_push;
904
905 vport->vlan = 0;
906 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
907 0, 0, SET_VLAN_STRIP);
908 if (err)
909 goto out;
910 }
911
912skip_unset_push:
913 offloads->vlan_push_pop_refcount--;
914 if (offloads->vlan_push_pop_refcount)
0e18134f 915 goto out;
f5f82476
OG		 916
917 /* no more vlan rules, stop global vlan pop policy */
918 err = esw_set_global_vlan_pop(esw, 0);
919
920out:
0e18134f 921 mutex_unlock(&esw->state_lock);
f5f82476
OG		 922 return err;
923}
924
f7a68945 925struct mlx5_flow_handle *
3a46f4fb 926mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
979bf468 927 struct mlx5_eswitch *from_esw,
3a46f4fb 928 struct mlx5_eswitch_rep *rep,
02f3afd9 929 u32 sqn)
ab22be9b 930{
66958ed9 931 struct mlx5_flow_act flow_act = {0};
4c5009c5 932 struct mlx5_flow_destination dest = {};
74491de9 933 struct mlx5_flow_handle *flow_rule;
c5bb1730 934 struct mlx5_flow_spec *spec;
ab22be9b
OG		 935 void *misc;
936
1b9a07ee 937 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 938 if (!spec) {
ab22be9b
OG		 939 flow_rule = ERR_PTR(-ENOMEM);
940 goto out;
941 }
942
c5bb1730 943 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 944 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a 945 /* source vport is the esw manager */
979bf468 946 MLX5_SET(fte_match_set_misc, misc, source_port, from_esw->manager_vport);
3a46f4fb 947 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a 948 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
979bf468 949 MLX5_CAP_GEN(from_esw->dev, vhca_id));
ab22be9b 950
c5bb1730 951 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 952 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
953 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3a46f4fb 954 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a
MB		 955 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
956 source_eswitch_owner_vhca_id);
ab22be9b 957
c5bb1730 958 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 959 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 960 dest.vport.num = rep->vport;
961 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
962 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 963 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 964
d0444254
AL		 965 if (rep->vport == MLX5_VPORT_UPLINK)
966 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
967
3a46f4fb 968 flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb,
39ac237c 969 spec, &flow_act, &dest, 1);
ab22be9b 970 if (IS_ERR(flow_rule))
3a46f4fb
MB		 971 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
972 PTR_ERR(flow_rule));
ab22be9b 973out:
c5bb1730 974 kvfree(spec);
ab22be9b
OG		 975 return flow_rule;
976}
57cbd893 977EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 978
159fe639
MB		 979void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
980{
981 mlx5_del_flow_rules(rule);
982}
983
8e404fef
VB		 984static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
985{
986 struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules;
47dd7e60 987 int i = 0, num_vfs = esw->esw_funcs.num_vfs;
8e404fef
VB		 988
989 if (!num_vfs || !flows)
990 return;
991
47dd7e60
PP		 992 for (i = 0; i < num_vfs; i++)
993 mlx5_del_flow_rules(flows[i]);
8e404fef
VB		 994
995 kvfree(flows);
996}
997
998static int
999mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
1000{
8e404fef
VB		 1001 struct mlx5_flow_destination dest = {};
1002 struct mlx5_flow_act flow_act = {0};
6308a5f0 1003 int num_vfs, rule_idx = 0, err = 0;
8e404fef
VB		 1004 struct mlx5_flow_handle *flow_rule;
1005 struct mlx5_flow_handle **flows;
1006 struct mlx5_flow_spec *spec;
47dd7e60
PP		 1007 struct mlx5_vport *vport;
1008 unsigned long i;
6308a5f0 1009 u16 vport_num;
8e404fef
VB		 1010
1011 num_vfs = esw->esw_funcs.num_vfs;
1012 flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL);
1013 if (!flows)
1014 return -ENOMEM;
1015
1016 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1017 if (!spec) {
1018 err = -ENOMEM;
1019 goto alloc_err;
1020 }
1021
1022 MLX5_SET(fte_match_param, spec->match_criteria,
1023 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1024 MLX5_SET(fte_match_param, spec->match_criteria,
1025 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1026 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1027 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1028
1029 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1030 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1031 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1032
47dd7e60
PP		 1033 mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) {
1034 vport_num = vport->vport;
8e404fef
VB		 1035 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1036 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1037 dest.vport.num = vport_num;
1038
1039 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1040 spec, &flow_act, &dest, 1);
1041 if (IS_ERR(flow_rule)) {
1042 err = PTR_ERR(flow_rule);
1043 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n",
1044 rule_idx, PTR_ERR(flow_rule));
1045 goto rule_err;
1046 }
1047 flows[rule_idx++] = flow_rule;
1048 }
1049
1050 esw->fdb_table.offloads.send_to_vport_meta_rules = flows;
1051 kvfree(spec);
1052 return 0;
1053
1054rule_err:
1055 while (--rule_idx >= 0)
1056 mlx5_del_flow_rules(flows[rule_idx]);
1057 kvfree(spec);
1058alloc_err:
1059 kvfree(flows);
1060 return err;
1061}
1062
5b7cb745
PB		 1063static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1064{
1065 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1066 MLX5_FDB_TO_VPORT_REG_C_1;
1067}
1068
332bd3a5 1069static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 1070{
1071 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 1072 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1073 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 1074 u8 curr, wanted;
c1286050
JL		 1075 int err;
1076
5b7cb745
PB		 1077 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1078 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 1079 return 0;
c1286050 1080
e08a6832
LR		 1081 MLX5_SET(query_esw_vport_context_in, in, opcode,
1082 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1083 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 1084 if (err)
1085 return err;
1086
5b7cb745
PB		 1087 curr = MLX5_GET(query_esw_vport_context_out, out,
1088 esw_vport_context.fdb_to_vport_reg_c_id);
1089 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1090 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1091 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 1092
332bd3a5 1093 if (enable)
5b7cb745 1094 curr |= wanted;
332bd3a5 1095 else
5b7cb745 1096 curr &= ~wanted;
c1286050 1097
e08a6832 1098 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 1099 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 1100 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 1101 field_select.fdb_to_vport_reg_c_id, 1);
1102
e08a6832 1103 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 1104 if (!err) {
1105 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1106 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1107 else
1108 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1109 }
1110
1111 return err;
c1286050
JL		 1112}
1113
a5641cb5
JL		 1114static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1115 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1116 struct mlx5_flow_spec *spec,
1117 struct mlx5_flow_destination *dest)
1118{
a5641cb5 1119 void *misc;
ac004b83 1120
a5641cb5
JL		 1121 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1122 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1123 misc_parameters_2);
0f0d3827
PB		 1124 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1125 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1126
a5641cb5
JL		 1127 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1128 } else {
1129 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1130 misc_parameters);
ac004b83 1131
a5641cb5
JL		 1132 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1133 MLX5_CAP_GEN(peer_dev, vhca_id));
1134
1135 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1136
1137 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1138 misc_parameters);
1139 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1140 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1141 source_eswitch_owner_vhca_id);
1142 }
ac004b83
RD		 1143
1144 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1145 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1146 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1147 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1148}
1149
a5641cb5
JL		 1150static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1151 struct mlx5_eswitch *peer_esw,
1152 struct mlx5_flow_spec *spec,
1153 u16 vport)
1154{
1155 void *misc;
1156
1157 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1158 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1159 misc_parameters_2);
1160 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1161 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1162 vport));
1163 } else {
1164 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1165 misc_parameters);
1166 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1167 }
1168}
1169
ac004b83
RD		 1170static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1171 struct mlx5_core_dev *peer_dev)
1172{
1173 struct mlx5_flow_destination dest = {};
1174 struct mlx5_flow_act flow_act = {0};
1175 struct mlx5_flow_handle **flows;
ac004b83
RD		 1176 /* total vports is the same for both e-switches */
1177 int nvports = esw->total_vports;
47dd7e60
PP		 1178 struct mlx5_flow_handle *flow;
1179 struct mlx5_flow_spec *spec;
1180 struct mlx5_vport *vport;
1181 unsigned long i;
ac004b83 1182 void *misc;
47dd7e60 1183 int err;
ac004b83
RD		 1184
1185 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1186 if (!spec)
1187 return -ENOMEM;
1188
a5641cb5 1189 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 1190
1191 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
1192 if (!flows) {
1193 err = -ENOMEM;
1194 goto alloc_flows_err;
1195 }
1196
1197 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1198 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1199 misc_parameters);
1200
81cd229c 1201 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1202 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1203 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1204 spec, MLX5_VPORT_PF);
1205
81cd229c
BW		 1206 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1207 spec, &flow_act, &dest, 1);
1208 if (IS_ERR(flow)) {
1209 err = PTR_ERR(flow);
1210 goto add_pf_flow_err;
1211 }
47dd7e60 1212 flows[vport->index] = flow;
81cd229c
BW		 1213 }
1214
1215 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1216 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c
BW		 1217 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1218 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1219 spec, &flow_act, &dest, 1);
1220 if (IS_ERR(flow)) {
1221 err = PTR_ERR(flow);
1222 goto add_ecpf_flow_err;
1223 }
47dd7e60 1224 flows[vport->index] = flow;
81cd229c
BW		 1225 }
1226
47dd7e60 1227 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1228 esw_set_peer_miss_rule_source_port(esw,
1229 peer_dev->priv.eswitch,
47dd7e60 1230 spec, vport->vport);
a5641cb5 1231
ac004b83
RD		 1232 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1233 spec, &flow_act, &dest, 1);
1234 if (IS_ERR(flow)) {
1235 err = PTR_ERR(flow);
81cd229c 1236 goto add_vf_flow_err;
ac004b83 1237 }
47dd7e60 1238 flows[vport->index] = flow;
ac004b83
RD		 1239 }
1240
1241 esw->fdb_table.offloads.peer_miss_rules = flows;
1242
1243 kvfree(spec);
1244 return 0;
1245
81cd229c 1246add_vf_flow_err:
47dd7e60
PP		 1247 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1248 if (!flows[vport->index])
1249 continue;
1250 mlx5_del_flow_rules(flows[vport->index]);
1251 }
1252 if (mlx5_ecpf_vport_exists(esw->dev)) {
1253 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1254 mlx5_del_flow_rules(flows[vport->index]);
1255 }
81cd229c 1256add_ecpf_flow_err:
47dd7e60
PP		 1257 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1258 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1259 mlx5_del_flow_rules(flows[vport->index]);
1260 }
81cd229c
BW		 1261add_pf_flow_err:
1262 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1263 kvfree(flows);
1264alloc_flows_err:
1265 kvfree(spec);
1266 return err;
1267}
1268
1269static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1270{
1271 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1272 struct mlx5_vport *vport;
1273 unsigned long i;
ac004b83
RD		 1274
1275 flows = esw->fdb_table.offloads.peer_miss_rules;
1276
47dd7e60
PP		 1277 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1278 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1279
47dd7e60
PP		 1280 if (mlx5_ecpf_vport_exists(esw->dev)) {
1281 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1282 mlx5_del_flow_rules(flows[vport->index]);
1283 }
81cd229c 1284
47dd7e60
PP		 1285 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1286 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1287 mlx5_del_flow_rules(flows[vport->index]);
1288 }
ac004b83
RD		 1289 kvfree(flows);
1290}
1291
3aa33572
OG		 1292static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1293{
66958ed9 1294 struct mlx5_flow_act flow_act = {0};
4c5009c5 1295 struct mlx5_flow_destination dest = {};
74491de9 1296 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1297 struct mlx5_flow_spec *spec;
f80be543
MB		 1298 void *headers_c;
1299 void *headers_v;
3aa33572 1300 int err = 0;
f80be543
MB		 1301 u8 *dmac_c;
1302 u8 *dmac_v;
3aa33572 1303
1b9a07ee 1304 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1305 if (!spec) {
3aa33572
OG		 1306 err = -ENOMEM;
1307 goto out;
1308 }
1309
f80be543
MB		 1310 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1311 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1312 outer_headers);
1313 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1314 outer_headers.dmac_47_16);
1315 dmac_c[0] = 0x01;
1316
3aa33572 1317 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1318 dest.vport.num = esw->manager_vport;
66958ed9 1319 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1320
39ac237c
PB		 1321 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1322 spec, &flow_act, &dest, 1);
3aa33572
OG		 1323 if (IS_ERR(flow_rule)) {
1324 err = PTR_ERR(flow_rule);
f80be543 1325 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1326 goto out;
1327 }
1328
f80be543
MB		 1329 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1330
1331 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1332 outer_headers);
1333 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1334 outer_headers.dmac_47_16);
1335 dmac_v[0] = 0x01;
39ac237c
PB		 1336 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1337 spec, &flow_act, &dest, 1);
f80be543
MB		 1338 if (IS_ERR(flow_rule)) {
1339 err = PTR_ERR(flow_rule);
1340 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1341 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1342 goto out;
1343 }
1344
1345 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1346
3aa33572 1347out:
c5bb1730 1348 kvfree(spec);
3aa33572
OG		 1349 return err;
1350}
1351
11b717d6
PB		 1352struct mlx5_flow_handle *
1353esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1354{
1355 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1356 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1357 struct mlx5_flow_context *flow_context;
1358 struct mlx5_flow_handle *flow_rule;
1359 struct mlx5_flow_destination dest;
1360 struct mlx5_flow_spec *spec;
1361 void *misc;
1362
60acc105
PB		 1363 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1364 return ERR_PTR(-EOPNOTSUPP);
1365
9f4d9283 1366 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1367 if (!spec)
1368 return ERR_PTR(-ENOMEM);
1369
1370 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1371 misc_parameters_2);
1372 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1373 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1374 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1375 misc_parameters_2);
1376 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1377 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1378 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1379 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1380 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1381
1382 flow_context = &spec->flow_context;
1383 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1384 flow_context->flow_tag = tag;
1385 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1386 dest.ft = esw->offloads.ft_offloads;
1387
1388 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1389 kvfree(spec);
11b717d6
PB		 1390
1391 if (IS_ERR(flow_rule))
1392 esw_warn(esw->dev,
1393 "Failed to create restore rule for tag: %d, err(%d)\n",
1394 tag, (int)PTR_ERR(flow_rule));
1395
1396 return flow_rule;
1397}
1398
1967ce6e 1399#define MAX_PF_SQ 256
cd3d07e7 1400#define MAX_SQ_NVPORTS 32
1967ce6e 1401
a5641cb5
JL		 1402static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1403 u32 *flow_group_in)
1404{
1405 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1406 flow_group_in,
1407 match_criteria);
1408
1409 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1410 MLX5_SET(create_flow_group_in, flow_group_in,
1411 match_criteria_enable,
1412 MLX5_MATCH_MISC_PARAMETERS_2);
1413
0f0d3827
PB		 1414 MLX5_SET(fte_match_param, match_criteria,
1415 misc_parameters_2.metadata_reg_c_0,
1416 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1417 } else {
1418 MLX5_SET(create_flow_group_in, flow_group_in,
1419 match_criteria_enable,
1420 MLX5_MATCH_MISC_PARAMETERS);
1421
1422 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1423 misc_parameters.source_port);
1424 }
1425}
1426
ae430332 1427#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1428static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1429{
1430 struct mlx5_vport_tbl_attr attr;
1431 struct mlx5_vport *vport;
47dd7e60 1432 unsigned long i;
4c7f4028
CM		 1433
1434 attr.chain = 0;
1435 attr.prio = 1;
47dd7e60 1436 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1437 attr.vport = vport->vport;
c796bb7c 1438 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1439 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1440 }
1441}
1442
0a9e2307 1443static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1444{
1445 struct mlx5_vport_tbl_attr attr;
1446 struct mlx5_flow_table *fdb;
1447 struct mlx5_vport *vport;
47dd7e60 1448 unsigned long i;
4c7f4028
CM		 1449
1450 attr.chain = 0;
1451 attr.prio = 1;
47dd7e60 1452 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1453 attr.vport = vport->vport;
c796bb7c 1454 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1455 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1456 if (IS_ERR(fdb))
1457 goto out;
1458 }
1459 return 0;
1460
1461out:
0a9e2307 1462 esw_vport_tbl_put(esw);
4c7f4028
CM		 1463 return PTR_ERR(fdb);
1464}
1465
ae430332
AL		 1466#define fdb_modify_header_fwd_to_table_supported(esw) \
1467 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1468static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1469{
1470 struct mlx5_core_dev *dev = esw->dev;
1471
1472 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1473 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1474
1475 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1476 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1477 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1478 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1479 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1480 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1481 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1482 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1483 /* Disabled when ttl workaround is needed, e.g
1484 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1485 */
1486 esw_warn(dev,
1487 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1488 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1489 } else {
1490 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1491 esw_info(dev, "Supported tc chains and prios offload\n");
1492 }
1493
1494 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1495 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1496}
1497
1498static int
1499esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1500{
1501 struct mlx5_core_dev *dev = esw->dev;
1502 struct mlx5_flow_table *nf_ft, *ft;
1503 struct mlx5_chains_attr attr = {};
1504 struct mlx5_fs_chains *chains;
1505 u32 fdb_max;
1506 int err;
1507
1508 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1509
1510 esw_init_chains_offload_flags(esw, &attr.flags);
1511 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1512 attr.max_ft_sz = fdb_max;
1513 attr.max_grp_num = esw->params.large_group_num;
1514 attr.default_ft = miss_fdb;
c9355682 1515 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1516
1517 chains = mlx5_chains_create(dev, &attr);
1518 if (IS_ERR(chains)) {
1519 err = PTR_ERR(chains);
1520 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1521 return err;
1522 }
1523
1524 esw->fdb_table.offloads.esw_chains_priv = chains;
1525
1526 /* Create tc_end_ft which is the always created ft chain */
1527 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1528 1, 0);
1529 if (IS_ERR(nf_ft)) {
1530 err = PTR_ERR(nf_ft);
1531 goto nf_ft_err;
1532 }
1533
1534 /* Always open the root for fast path */
1535 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1536 if (IS_ERR(ft)) {
1537 err = PTR_ERR(ft);
1538 goto level_0_err;
1539 }
1540
1541 /* Open level 1 for split fdb rules now if prios isn't supported */
1542 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1543 err = esw_vport_tbl_get(esw);
ae430332
AL		 1544 if (err)
1545 goto level_1_err;
1546 }
1547
1548 mlx5_chains_set_end_ft(chains, nf_ft);
1549
1550 return 0;
1551
1552level_1_err:
1553 mlx5_chains_put_table(chains, 0, 1, 0);
1554level_0_err:
1555 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1556nf_ft_err:
1557 mlx5_chains_destroy(chains);
1558 esw->fdb_table.offloads.esw_chains_priv = NULL;
1559
1560 return err;
1561}
1562
1563static void
1564esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1565{
1566 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1567 esw_vport_tbl_put(esw);
ae430332
AL		 1568 mlx5_chains_put_table(chains, 0, 1, 0);
1569 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1570 mlx5_chains_destroy(chains);
1571}
1572
1573#else /* CONFIG_MLX5_CLS_ACT */
1574
1575static int
1576esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1577{ return 0; }
1578
1579static void
1580esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1581{}
1582
1583#endif
1584
0da3c12d 1585static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1586{
1587 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1588 struct mlx5_flow_table_attr ft_attr = {};
8e404fef 1589 int num_vfs, table_size, ix, err = 0;
1967ce6e
OG		 1590 struct mlx5_core_dev *dev = esw->dev;
1591 struct mlx5_flow_namespace *root_ns;
1592 struct mlx5_flow_table *fdb = NULL;
39ac237c 1593 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1594 struct mlx5_flow_group *g;
1595 void *match_criteria;
f80be543 1596 u8 *dmac;
1967ce6e
OG		 1597
1598 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1599
1b9a07ee 1600 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1601 if (!flow_group_in)
1602 return -ENOMEM;
1603
1604 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1605 if (!root_ns) {
1606 esw_warn(dev, "Failed to get FDB flow namespace\n");
1607 err = -EOPNOTSUPP;
1608 goto ns_err;
1609 }
8463daf1
MG		 1610 esw->fdb_table.offloads.ns = root_ns;
1611 err = mlx5_flow_namespace_set_mode(root_ns,
1612 esw->dev->priv.steering->mode);
1613 if (err) {
1614 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1615 goto ns_err;
1616 }
1967ce6e 1617
898b0786
MB		 1618 /* To be strictly correct:
1619 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1620 * should be:
1621 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1622 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1623 * but as the peer device might not be in switchdev mode it's not
1624 * possible. We use the fact that by default FW sets max vfs and max sfs
1625 * to the same value on both devices. If it needs to be changed in the future note
1626 * the peer miss group should also be created based on the number of
1627 * total vports of the peer (currently is also uses esw->total_vports).
1628 */
1629 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
8e404fef 1630 MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs;
b3ba5149 1631
e52c2802
PB		 1632 /* create the slow path fdb with encap set, so further table instances
1633 * can be created at run time while VFs are probed if the FW allows that.
1634 */
1635 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1636 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1637 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1638
1639 ft_attr.flags = flags;
b3ba5149
ES		 1640 ft_attr.max_fte = table_size;
1641 ft_attr.prio = FDB_SLOW_PATH;
1642
1643 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1644 if (IS_ERR(fdb)) {
1645 err = PTR_ERR(fdb);
1646 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1647 goto slow_fdb_err;
1648 }
52fff327 1649 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1650
ec3be887
VB		 1651 /* Create empty TC-miss managed table. This allows plugging in following
1652 * priorities without directly exposing their level 0 table to
1653 * eswitch_offloads and passing it as miss_fdb to following call to
1654 * esw_chains_create().
1655 */
1656 memset(&ft_attr, 0, sizeof(ft_attr));
1657 ft_attr.prio = FDB_TC_MISS;
1658 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1659 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1660 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1661 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1662 goto tc_miss_table_err;
1663 }
1664
1665 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
39ac237c 1666 if (err) {
ae430332 1667 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1668 goto fdb_chains_err;
e52c2802
PB		 1669 }
1670
69697b6e 1671 /* create send-to-vport group */
69697b6e
OG		 1672 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1673 MLX5_MATCH_MISC_PARAMETERS);
1674
1675 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1676
1677 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1678 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
7d97822a
MB		 1679 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1680 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1681 misc_parameters.source_eswitch_owner_vhca_id);
1682 MLX5_SET(create_flow_group_in, flow_group_in,
1683 source_eswitch_owner_vhca_id_valid, 1);
1684 }
69697b6e 1685
898b0786
MB		 1686 /* See comment above table_size calculation */
1687 ix = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
69697b6e
OG		 1688 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1689 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1690
1691 g = mlx5_create_flow_group(fdb, flow_group_in);
1692 if (IS_ERR(g)) {
1693 err = PTR_ERR(g);
1694 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1695 goto send_vport_err;
1696 }
1697 esw->fdb_table.offloads.send_to_vport_grp = g;
1698
e929e3da
MD		 1699 if (esw_src_port_rewrite_supported(esw)) {
1700 /* meta send to vport */
1701 memset(flow_group_in, 0, inlen);
1702 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1703 MLX5_MATCH_MISC_PARAMETERS_2);
8e404fef 1704
e929e3da 1705 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
8e404fef 1706
e929e3da
MD		 1707 MLX5_SET(fte_match_param, match_criteria,
1708 misc_parameters_2.metadata_reg_c_0,
1709 mlx5_eswitch_get_vport_metadata_mask());
1710 MLX5_SET(fte_match_param, match_criteria,
1711 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1712
1713 num_vfs = esw->esw_funcs.num_vfs;
1714 if (num_vfs) {
1715 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1716 MLX5_SET(create_flow_group_in, flow_group_in,
1717 end_flow_index, ix + num_vfs - 1);
1718 ix += num_vfs;
1719
1720 g = mlx5_create_flow_group(fdb, flow_group_in);
1721 if (IS_ERR(g)) {
1722 err = PTR_ERR(g);
1723 esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n",
1724 err);
1725 goto send_vport_meta_err;
1726 }
1727 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1728
1729 err = mlx5_eswitch_add_send_to_vport_meta_rules(esw);
1730 if (err)
1731 goto meta_rule_err;
8e404fef 1732 }
8e404fef
VB		 1733 }
1734
6cec0229
MD		 1735 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1736 /* create peer esw miss group */
1737 memset(flow_group_in, 0, inlen);
ac004b83 1738
6cec0229 1739 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1740
6cec0229
MD		 1741 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1742 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1743 flow_group_in,
1744 match_criteria);
ac004b83 1745
6cec0229
MD		 1746 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1747 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1748
6cec0229
MD		 1749 MLX5_SET(create_flow_group_in, flow_group_in,
1750 source_eswitch_owner_vhca_id_valid, 1);
1751 }
ac004b83 1752
6cec0229
MD		 1753 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1754 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1755 ix + esw->total_vports - 1);
1756 ix += esw->total_vports;
ac004b83 1757
6cec0229
MD		 1758 g = mlx5_create_flow_group(fdb, flow_group_in);
1759 if (IS_ERR(g)) {
1760 err = PTR_ERR(g);
1761 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1762 goto peer_miss_err;
1763 }
1764 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1765 }
ac004b83 1766
69697b6e
OG		 1767 /* create miss group */
1768 memset(flow_group_in, 0, inlen);
f80be543
MB		 1769 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1770 MLX5_MATCH_OUTER_HEADERS);
1771 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1772 match_criteria);
1773 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1774 outer_headers.dmac_47_16);
1775 dmac[0] = 0x01;
69697b6e
OG		 1776
1777 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1778 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1779 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1780
1781 g = mlx5_create_flow_group(fdb, flow_group_in);
1782 if (IS_ERR(g)) {
1783 err = PTR_ERR(g);
1784 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1785 goto miss_err;
1786 }
1787 esw->fdb_table.offloads.miss_grp = g;
1788
3aa33572
OG		 1789 err = esw_add_fdb_miss_rule(esw);
1790 if (err)
1791 goto miss_rule_err;
1792
c88a026e 1793 kvfree(flow_group_in);
69697b6e
OG		 1794 return 0;
1795
3aa33572
OG		 1796miss_rule_err:
1797 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1798miss_err:
6cec0229
MD		 1799 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1800 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1801peer_miss_err:
8e404fef
VB		 1802 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1803meta_rule_err:
1804 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1805 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1806send_vport_meta_err:
69697b6e
OG		 1807 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1808send_vport_err:
ae430332 1809 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1810fdb_chains_err:
ec3be887
VB		 1811 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1812tc_miss_table_err:
52fff327 1813 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1814slow_fdb_err:
8463daf1
MG		 1815 /* Holds true only as long as DMFS is the default */
1816 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1817ns_err:
1818 kvfree(flow_group_in);
1819 return err;
1820}
1821
1967ce6e 1822static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1823{
e52c2802 1824 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1825 return;
1826
1967ce6e 1827 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1828 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1829 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
8e404fef 1830 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
69697b6e 1831 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1832 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1833 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1834 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1835 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1836 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1837
ae430332
AL		 1838 esw_chains_destroy(esw, esw_chains(esw));
1839
ec3be887 1840 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
52fff327 1841 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1842 /* Holds true only as long as DMFS is the default */
1843 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1844 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1845 atomic64_set(&esw->user_count, 0);
69697b6e 1846}
c116c6ee 1847
3651168c
AL		 1848static int esw_get_offloads_ft_size(struct mlx5_eswitch *esw)
1849{
1850 int nvports;
1851
1852 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1853 if (mlx5e_tc_int_port_supported(esw))
1854 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1855
1856 return nvports;
1857}
1858
8d6bd3c3 1859static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1860{
b3ba5149 1861 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1862 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1863 struct mlx5_flow_table *ft_offloads;
1864 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1865 int err = 0;
1866
1867 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1868 if (!ns) {
1869 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1870 return -EOPNOTSUPP;
c116c6ee
OG		 1871 }
1872
3651168c 1873 ft_attr.max_fte = esw_get_offloads_ft_size(esw);
11b717d6 1874 ft_attr.prio = 1;
b3ba5149
ES		 1875
1876 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1877 if (IS_ERR(ft_offloads)) {
1878 err = PTR_ERR(ft_offloads);
1879 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1880 return err;
1881 }
1882
1883 esw->offloads.ft_offloads = ft_offloads;
1884 return 0;
1885}
1886
1887static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1888{
1889 struct mlx5_esw_offload *offloads = &esw->offloads;
1890
1891 mlx5_destroy_flow_table(offloads->ft_offloads);
1892}
fed9ce22 1893
8d6bd3c3 1894static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1895{
1896 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1897 struct mlx5_flow_group *g;
fed9ce22 1898 u32 *flow_group_in;
8d6bd3c3 1899 int nvports;
fed9ce22 1900 int err = 0;
fed9ce22 1901
3651168c 1902 nvports = esw_get_offloads_ft_size(esw);
1b9a07ee 1903 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1904 if (!flow_group_in)
1905 return -ENOMEM;
1906
1907 /* create vport rx group */
a5641cb5 1908 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1909
1910 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1911 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1912
1913 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1914
1915 if (IS_ERR(g)) {
1916 err = PTR_ERR(g);
1917 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1918 goto out;
1919 }
1920
1921 esw->offloads.vport_rx_group = g;
1922out:
e574978a 1923 kvfree(flow_group_in);
fed9ce22
OG		 1924 return err;
1925}
1926
1927static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1928{
1929 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1930}
1931
74491de9 1932struct mlx5_flow_handle *
02f3afd9 1933mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1934 struct mlx5_flow_destination *dest)
fed9ce22 1935{
66958ed9 1936 struct mlx5_flow_act flow_act = {0};
74491de9 1937 struct mlx5_flow_handle *flow_rule;
c5bb1730 1938 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1939 void *misc;
1940
1b9a07ee 1941 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1942 if (!spec) {
fed9ce22
OG		 1943 flow_rule = ERR_PTR(-ENOMEM);
1944 goto out;
1945 }
1946
a5641cb5
JL		 1947 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1948 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1949 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1950 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1951
a5641cb5 1952 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1953 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1954 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1955
a5641cb5
JL		 1956 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1957 } else {
1958 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1959 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1960
1961 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1962 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1963
1964 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1965 }
fed9ce22 1966
66958ed9 1967 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1968 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1969 &flow_act, dest, 1);
fed9ce22
OG		 1970 if (IS_ERR(flow_rule)) {
1971 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1972 goto out;
1973 }
1974
1975out:
c5bb1730 1976 kvfree(spec);
fed9ce22
OG		 1977 return flow_rule;
1978}
feae9087 1979
47dd7e60 1980static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 1981{
1982 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1983 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 1984 struct mlx5_vport *vport;
1985 unsigned long i;
cc617ced
PP		 1986
1987 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1988 return -EOPNOTSUPP;
1989
1990 if (esw->mode == MLX5_ESWITCH_NONE)
1991 return -EOPNOTSUPP;
1992
1993 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1994 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1995 mlx5_mode = MLX5_INLINE_MODE_NONE;
1996 goto out;
1997 case MLX5_CAP_INLINE_MODE_L2:
1998 mlx5_mode = MLX5_INLINE_MODE_L2;
1999 goto out;
2000 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2001 goto query_vports;
2002 }
2003
2004query_vports:
2005 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 2006 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2007 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 2008 if (prev_mlx5_mode != mlx5_mode)
2009 return -EINVAL;
2010 prev_mlx5_mode = mlx5_mode;
2011 }
2012
2013out:
2014 *mode = mlx5_mode;
2015 return 0;
e08a6832 2016}
bf3347c4 2017
11b717d6
PB		 2018static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2019{
2020 struct mlx5_esw_offload *offloads = &esw->offloads;
2021
60acc105
PB		 2022 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2023 return;
2024
6724e66b 2025 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 2026 mlx5_destroy_flow_group(offloads->restore_group);
2027 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2028}
2029
2030static int esw_create_restore_table(struct mlx5_eswitch *esw)
2031{
d65dbedf 2032 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 2033 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2034 struct mlx5_flow_table_attr ft_attr = {};
2035 struct mlx5_core_dev *dev = esw->dev;
2036 struct mlx5_flow_namespace *ns;
6724e66b 2037 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 2038 void *match_criteria, *misc;
2039 struct mlx5_flow_table *ft;
2040 struct mlx5_flow_group *g;
2041 u32 *flow_group_in;
2042 int err = 0;
2043
60acc105
PB		 2044 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2045 return 0;
2046
11b717d6
PB		 2047 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2048 if (!ns) {
2049 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2050 return -EOPNOTSUPP;
2051 }
2052
2053 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2054 if (!flow_group_in) {
2055 err = -ENOMEM;
2056 goto out_free;
2057 }
2058
a91d98a0 2059 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2060 ft = mlx5_create_flow_table(ns, &ft_attr);
2061 if (IS_ERR(ft)) {
2062 err = PTR_ERR(ft);
2063 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2064 err);
2065 goto out_free;
2066 }
2067
11b717d6
PB		 2068 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2069 match_criteria);
2070 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2071 misc_parameters_2);
2072
2073 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2074 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2075 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2076 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2077 ft_attr.max_fte - 1);
2078 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2079 MLX5_MATCH_MISC_PARAMETERS_2);
2080 g = mlx5_create_flow_group(ft, flow_group_in);
2081 if (IS_ERR(g)) {
2082 err = PTR_ERR(g);
2083 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2084 err);
2085 goto err_group;
2086 }
2087
6724e66b
PB		 2088 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2089 MLX5_SET(copy_action_in, modact, src_field,
2090 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2091 MLX5_SET(copy_action_in, modact, dst_field,
2092 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2093 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2094 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2095 modact);
2096 if (IS_ERR(mod_hdr)) {
e9864539 2097 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2098 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2099 err);
6724e66b
PB		 2100 goto err_mod_hdr;
2101 }
2102
11b717d6
PB		 2103 esw->offloads.ft_offloads_restore = ft;
2104 esw->offloads.restore_group = g;
6724e66b 2105 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2106
c8508713
RD		 2107 kvfree(flow_group_in);
2108
11b717d6
PB		 2109 return 0;
2110
6724e66b
PB		 2111err_mod_hdr:
2112 mlx5_destroy_flow_group(g);
11b717d6
PB		 2113err_group:
2114 mlx5_destroy_flow_table(ft);
2115out_free:
2116 kvfree(flow_group_in);
2117
2118 return err;
cc617ced
PP		 2119}
2120
db7ff19e
EB		 2121static int esw_offloads_start(struct mlx5_eswitch *esw,
2122 struct netlink_ext_ack *extack)
c930a3ad 2123{
062f4bf4 2124 int err, err1;
c930a3ad 2125
8e0aa4bc
PP		 2126 mlx5_eswitch_disable_locked(esw, false);
2127 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2128 esw->dev->priv.sriov.num_vfs);
6c419ba8 2129 if (err) {
8c98ee77
EB		 2130 NL_SET_ERR_MSG_MOD(extack,
2131 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 2132 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2133 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2134 if (err1) {
2135 NL_SET_ERR_MSG_MOD(extack,
2136 "Failed setting eswitch back to legacy");
2137 }
6c419ba8 2138 }
bffaa916
RD		 2139 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2140 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2141 &esw->offloads.inline_mode)) {
2142 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2143 NL_SET_ERR_MSG_MOD(extack,
2144 "Inline mode is different between vports");
bffaa916
RD		 2145 }
2146 }
c930a3ad
OG		 2147 return err;
2148}
2149
47dd7e60
PP		 2150static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2151 struct mlx5_eswitch_rep *rep,
2152 xa_mark_t mark)
e8d31c4d 2153{
47dd7e60
PP		 2154 bool mark_set;
2155
2156 /* Copy the mark from vport to its rep */
2157 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2158 if (mark_set)
2159 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
e8d31c4d
MB		 2160}
2161
47dd7e60 2162static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2163{
e8d31c4d 2164 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2165 int rep_type;
2166 int err;
e8d31c4d 2167
47dd7e60
PP		 2168 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2169 if (!rep)
e8d31c4d
MB		 2170 return -ENOMEM;
2171
47dd7e60
PP		 2172 rep->vport = vport->vport;
2173 rep->vport_index = vport->index;
2174 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2175 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2176
47dd7e60
PP		 2177 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2178 if (err)
2179 goto insert_err;
2180
2181 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2182 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2183 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2184 return 0;
2185
2186insert_err:
2187 kfree(rep);
2188 return err;
2189}
2190
2191static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2192 struct mlx5_eswitch_rep *rep)
2193{
2194 xa_erase(&esw->offloads.vport_reps, rep->vport);
2195 kfree(rep);
2196}
2197
2198void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2199{
2200 struct mlx5_eswitch_rep *rep;
2201 unsigned long i;
e8d31c4d 2202
47dd7e60
PP		 2203 mlx5_esw_for_each_rep(esw, i, rep)
2204 mlx5_esw_offloads_rep_cleanup(esw, rep);
2205 xa_destroy(&esw->offloads.vport_reps);
2206}
2207
2208int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2209{
2210 struct mlx5_vport *vport;
2211 unsigned long i;
2212 int err;
2213
2214 xa_init(&esw->offloads.vport_reps);
2215
2216 mlx5_esw_for_each_vport(esw, i, vport) {
2217 err = mlx5_esw_offloads_rep_init(esw, vport);
2218 if (err)
2219 goto err;
2220 }
e8d31c4d 2221 return 0;
47dd7e60
PP		 2222
2223err:
2224 esw_offloads_cleanup_reps(esw);
2225 return err;
e8d31c4d
MB		 2226}
2227
c9b99abc
BW		 2228static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2229 struct mlx5_eswitch_rep *rep, u8 rep_type)
2230{
8693115a 2231 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2232 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2233 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2234}
2235
d7f33a45
VP		 2236static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2237{
2238 struct mlx5_eswitch_rep *rep;
47dd7e60 2239 unsigned long i;
d7f33a45
VP		 2240
2241 mlx5_esw_for_each_sf_rep(esw, i, rep)
2242 __esw_offloads_unload_rep(esw, rep, rep_type);
2243}
2244
4110fc59 2245static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2246{
2247 struct mlx5_eswitch_rep *rep;
47dd7e60 2248 unsigned long i;
4110fc59 2249
d7f33a45
VP		 2250 __unload_reps_sf_vport(esw, rep_type);
2251
47dd7e60 2252 mlx5_esw_for_each_vf_rep(esw, i, rep)
4110fc59 2253 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 2254
81cd229c
BW		 2255 if (mlx5_ecpf_vport_exists(esw->dev)) {
2256 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2257 __esw_offloads_unload_rep(esw, rep, rep_type);
2258 }
2259
2260 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2261 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2262 __esw_offloads_unload_rep(esw, rep, rep_type);
2263 }
2264
879c8f84 2265 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 2266 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2267}
2268
d970812b 2269int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2270{
c2d7712c
BW		 2271 struct mlx5_eswitch_rep *rep;
2272 int rep_type;
a4b97ab4
MB		 2273 int err;
2274
c2d7712c
BW		 2275 rep = mlx5_eswitch_get_rep(esw, vport_num);
2276 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2277 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2278 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2279 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2280 if (err)
2281 goto err_reps;
2282 }
2283
2284 return 0;
a4b97ab4
MB		 2285
2286err_reps:
c2d7712c
BW		 2287 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2288 for (--rep_type; rep_type >= 0; rep_type--)
2289 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2290 return err;
2291}
2292
d970812b 2293void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2294{
2295 struct mlx5_eswitch_rep *rep;
2296 int rep_type;
2297
c2d7712c
BW		 2298 rep = mlx5_eswitch_get_rep(esw, vport_num);
2299 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2300 __esw_offloads_unload_rep(esw, rep, rep_type);
2301}
2302
38679b5a
PP		 2303int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2304{
2305 int err;
2306
2307 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2308 return 0;
2309
865d6d1c
RD		 2310 if (vport_num != MLX5_VPORT_UPLINK) {
2311 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2312 if (err)
2313 return err;
2314 }
c7eddc60 2315
38679b5a 2316 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2317 if (err)
2318 goto load_err;
2319 return err;
2320
2321load_err:
865d6d1c
RD		 2322 if (vport_num != MLX5_VPORT_UPLINK)
2323 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2324 return err;
2325}
2326
2327void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2328{
2329 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2330 return;
2331
2332 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c
RD		 2333
2334 if (vport_num != MLX5_VPORT_UPLINK)
2335 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2336}
2337
db202995
MB		 2338static int esw_set_uplink_slave_ingress_root(struct mlx5_core_dev *master,
2339 struct mlx5_core_dev *slave)
2340{
2341 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2342 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2343 struct mlx5_eswitch *esw;
2344 struct mlx5_flow_root_namespace *root;
2345 struct mlx5_flow_namespace *ns;
2346 struct mlx5_vport *vport;
2347 int err;
2348
2349 MLX5_SET(set_flow_table_root_in, in, opcode,
2350 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2351 MLX5_SET(set_flow_table_root_in, in, table_type, FS_FT_ESW_INGRESS_ACL);
2352 MLX5_SET(set_flow_table_root_in, in, other_vport, 1);
2353 MLX5_SET(set_flow_table_root_in, in, vport_number, MLX5_VPORT_UPLINK);
2354
2355 if (master) {
2356 esw = master->priv.eswitch;
2357 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2358 MLX5_SET(set_flow_table_root_in, in, table_of_other_vport, 1);
2359 MLX5_SET(set_flow_table_root_in, in, table_vport_number,
2360 MLX5_VPORT_UPLINK);
2361
2362 ns = mlx5_get_flow_vport_acl_namespace(master,
2363 MLX5_FLOW_NAMESPACE_ESW_INGRESS,
2364 vport->index);
2365 root = find_root(&ns->node);
2366 mutex_lock(&root->chain_lock);
2367
2368 MLX5_SET(set_flow_table_root_in, in,
2369 table_eswitch_owner_vhca_id_valid, 1);
2370 MLX5_SET(set_flow_table_root_in, in,
2371 table_eswitch_owner_vhca_id,
2372 MLX5_CAP_GEN(master, vhca_id));
2373 MLX5_SET(set_flow_table_root_in, in, table_id,
2374 root->root_ft->id);
2375 } else {
2376 esw = slave->priv.eswitch;
2377 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2378 ns = mlx5_get_flow_vport_acl_namespace(slave,
2379 MLX5_FLOW_NAMESPACE_ESW_INGRESS,
2380 vport->index);
2381 root = find_root(&ns->node);
2382 mutex_lock(&root->chain_lock);
2383 MLX5_SET(set_flow_table_root_in, in, table_id, root->root_ft->id);
2384 }
2385
2386 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2387 mutex_unlock(&root->chain_lock);
2388
2389 return err;
2390}
2391
2392static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2393 struct mlx5_core_dev *slave)
2394{
2395 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2396 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2397 struct mlx5_flow_root_namespace *root;
2398 struct mlx5_flow_namespace *ns;
2399 int err;
2400
2401 MLX5_SET(set_flow_table_root_in, in, opcode,
2402 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2403 MLX5_SET(set_flow_table_root_in, in, table_type,
2404 FS_FT_FDB);
2405
2406 if (master) {
2407 ns = mlx5_get_flow_namespace(master,
2408 MLX5_FLOW_NAMESPACE_FDB);
2409 root = find_root(&ns->node);
2410 mutex_lock(&root->chain_lock);
2411 MLX5_SET(set_flow_table_root_in, in,
2412 table_eswitch_owner_vhca_id_valid, 1);
2413 MLX5_SET(set_flow_table_root_in, in,
2414 table_eswitch_owner_vhca_id,
2415 MLX5_CAP_GEN(master, vhca_id));
2416 MLX5_SET(set_flow_table_root_in, in, table_id,
2417 root->root_ft->id);
2418 } else {
2419 ns = mlx5_get_flow_namespace(slave,
2420 MLX5_FLOW_NAMESPACE_FDB);
2421 root = find_root(&ns->node);
2422 mutex_lock(&root->chain_lock);
2423 MLX5_SET(set_flow_table_root_in, in, table_id,
2424 root->root_ft->id);
2425 }
2426
2427 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2428 mutex_unlock(&root->chain_lock);
2429
2430 return err;
2431}
2432
2433static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2434 struct mlx5_core_dev *slave,
2435 struct mlx5_vport *vport,
2436 struct mlx5_flow_table *acl)
2437{
2438 struct mlx5_flow_handle *flow_rule = NULL;
2439 struct mlx5_flow_destination dest = {};
2440 struct mlx5_flow_act flow_act = {};
2441 struct mlx5_flow_spec *spec;
2442 int err = 0;
2443 void *misc;
2444
2445 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2446 if (!spec)
2447 return -ENOMEM;
2448
2449 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2450 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2451 misc_parameters);
2452 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2453 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
2454 MLX5_CAP_GEN(slave, vhca_id));
2455
2456 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2457 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2458 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2459 source_eswitch_owner_vhca_id);
2460
2461 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2462 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2463 dest.vport.num = slave->priv.eswitch->manager_vport;
2464 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2465 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2466
2467 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2468 &dest, 1);
2469 if (IS_ERR(flow_rule))
2470 err = PTR_ERR(flow_rule);
2471 else
2472 vport->egress.offloads.bounce_rule = flow_rule;
2473
2474 kvfree(spec);
2475 return err;
2476}
2477
2478static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2479 struct mlx5_core_dev *slave)
2480{
2481 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2482 struct mlx5_eswitch *esw = master->priv.eswitch;
2483 struct mlx5_flow_table_attr ft_attr = {
2484 .max_fte = 1, .prio = 0, .level = 0,
037b01c2 2485 .flags = MLX5_FLOW_TABLE_OTHER_VPORT,
db202995
MB		 2486 };
2487 struct mlx5_flow_namespace *egress_ns;
2488 struct mlx5_flow_table *acl;
2489 struct mlx5_flow_group *g;
2490 struct mlx5_vport *vport;
2491 void *match_criteria;
2492 u32 *flow_group_in;
2493 int err;
2494
2495 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2496 if (IS_ERR(vport))
2497 return PTR_ERR(vport);
2498
2499 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2500 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2501 vport->index);
2502 if (!egress_ns)
2503 return -EINVAL;
2504
2505 if (vport->egress.acl)
2506 return -EINVAL;
2507
2508 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2509 if (!flow_group_in)
2510 return -ENOMEM;
2511
2512 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2513 if (IS_ERR(acl)) {
2514 err = PTR_ERR(acl);
2515 goto out;
2516 }
2517
2518 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2519 match_criteria);
2520 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2521 misc_parameters.source_port);
2522 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2523 misc_parameters.source_eswitch_owner_vhca_id);
2524 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2525 MLX5_MATCH_MISC_PARAMETERS);
2526
2527 MLX5_SET(create_flow_group_in, flow_group_in,
2528 source_eswitch_owner_vhca_id_valid, 1);
2529 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2530 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
2531
2532 g = mlx5_create_flow_group(acl, flow_group_in);
2533 if (IS_ERR(g)) {
2534 err = PTR_ERR(g);
2535 goto err_group;
2536 }
2537
2538 err = __esw_set_master_egress_rule(master, slave, vport, acl);
2539 if (err)
2540 goto err_rule;
2541
2542 vport->egress.acl = acl;
2543 vport->egress.offloads.bounce_grp = g;
2544
2545 kvfree(flow_group_in);
2546
2547 return 0;
2548
2549err_rule:
2550 mlx5_destroy_flow_group(g);
2551err_group:
2552 mlx5_destroy_flow_table(acl);
2553out:
2554 kvfree(flow_group_in);
2555 return err;
2556}
2557
2558static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev)
2559{
2560 struct mlx5_vport *vport;
2561
2562 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2563 dev->priv.eswitch->manager_vport);
2564
2565 esw_acl_egress_ofld_cleanup(vport);
2566}
2567
2568int mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw,
2569 struct mlx5_eswitch *slave_esw)
2570{
2571 int err;
2572
2573 err = esw_set_uplink_slave_ingress_root(master_esw->dev,
2574 slave_esw->dev);
2575 if (err)
2576 return -EINVAL;
2577
2578 err = esw_set_slave_root_fdb(master_esw->dev,
2579 slave_esw->dev);
2580 if (err)
2581 goto err_fdb;
2582
2583 err = esw_set_master_egress_rule(master_esw->dev,
2584 slave_esw->dev);
2585 if (err)
2586 goto err_acl;
2587
2588 return err;
2589
2590err_acl:
2591 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2592
2593err_fdb:
2594 esw_set_uplink_slave_ingress_root(NULL, slave_esw->dev);
2595
2596 return err;
2597}
2598
2599void mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw,
2600 struct mlx5_eswitch *slave_esw)
2601{
2602 esw_unset_master_egress_rule(master_esw->dev);
2603 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2604 esw_set_uplink_slave_ingress_root(NULL, slave_esw->dev);
2605}
2606
ac004b83
RD		 2607#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2608#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2609
c8e6a9e6 2610static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw)
ac004b83 2611{
c8e6a9e6
MB		 2612 const struct mlx5_eswitch_rep_ops *ops;
2613 struct mlx5_eswitch_rep *rep;
2614 unsigned long i;
2615 u8 rep_type;
2616
2617 mlx5_esw_for_each_rep(esw, i, rep) {
2618 rep_type = NUM_REP_TYPES;
2619 while (rep_type--) {
2620 ops = esw->offloads.rep_ops[rep_type];
2621 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2622 ops->event)
2623 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, NULL);
2624 }
2625 }
ac004b83
RD		 2626}
2627
2628static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
2629{
d956873f 2630#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2631 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2632#endif
c8e6a9e6 2633 mlx5_esw_offloads_rep_event_unpair(esw);
ac004b83
RD		 2634 esw_del_fdb_peer_miss_rules(esw);
2635}
2636
c8e6a9e6
MB		 2637static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2638 struct mlx5_eswitch *peer_esw)
2639{
2640 const struct mlx5_eswitch_rep_ops *ops;
2641 struct mlx5_eswitch_rep *rep;
2642 unsigned long i;
2643 u8 rep_type;
2644 int err;
2645
2646 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2647 if (err)
2648 return err;
2649
2650 mlx5_esw_for_each_rep(esw, i, rep) {
2651 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2652 ops = esw->offloads.rep_ops[rep_type];
2653 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2654 ops->event) {
2655 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2656 if (err)
2657 goto err_out;
2658 }
2659 }
2660 }
2661
2662 return 0;
2663
2664err_out:
2665 mlx5_esw_offloads_unpair(esw);
2666 return err;
2667}
2668
8463daf1
MG		 2669static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2670 struct mlx5_eswitch *peer_esw,
2671 bool pair)
2672{
2673 struct mlx5_flow_root_namespace *peer_ns;
2674 struct mlx5_flow_root_namespace *ns;
2675 int err;
2676
2677 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2678 ns = esw->dev->priv.steering->fdb_root_ns;
2679
2680 if (pair) {
2681 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2682 if (err)
2683 return err;
2684
e53e6655 2685 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 2686 if (err) {
2687 mlx5_flow_namespace_set_peer(ns, NULL);
2688 return err;
2689 }
2690 } else {
2691 mlx5_flow_namespace_set_peer(ns, NULL);
2692 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2693 }
2694
2695 return 0;
2696}
2697
ac004b83
RD		 2698static int mlx5_esw_offloads_devcom_event(int event,
2699 void *my_data,
2700 void *event_data)
2701{
2702 struct mlx5_eswitch *esw = my_data;
ac004b83 2703 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 2704 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 2705 int err;
2706
2707 switch (event) {
2708 case ESW_OFFLOADS_DEVCOM_PAIR:
dd3fddb8
RD		 2709 if (mlx5_get_next_phys_dev(esw->dev) != peer_esw->dev)
2710 break;
2711
a5641cb5
JL		 2712 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2713 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2714 break;
2715
8463daf1 2716 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2717 if (err)
2718 goto err_out;
8463daf1
MG		 2719 err = mlx5_esw_offloads_pair(esw, peer_esw);
2720 if (err)
2721 goto err_peer;
ac004b83
RD		 2722
2723 err = mlx5_esw_offloads_pair(peer_esw, esw);
2724 if (err)
2725 goto err_pair;
2726
2727 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2728 break;
2729
2730 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2731 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
2732 break;
2733
2734 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2735 mlx5_esw_offloads_unpair(peer_esw);
2736 mlx5_esw_offloads_unpair(esw);
8463daf1 2737 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2738 break;
2739 }
2740
2741 return 0;
2742
2743err_pair:
2744 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 2745err_peer:
2746 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2747err_out:
2748 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2749 event, err);
2750 return err;
2751}
2752
2753static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2754{
2755 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2756
04de7dda
RD		 2757 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2758 mutex_init(&esw->offloads.peer_mutex);
2759
ac004b83
RD		 2760 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2761 return;
2762
2763 mlx5_devcom_register_component(devcom,
2764 MLX5_DEVCOM_ESW_OFFLOADS,
2765 mlx5_esw_offloads_devcom_event,
2766 esw);
2767
2768 mlx5_devcom_send_event(devcom,
2769 MLX5_DEVCOM_ESW_OFFLOADS,
2770 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2771}
2772
2773static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2774{
2775 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2776
2777 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2778 return;
2779
2780 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2781 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2782
2783 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2784}
2785
7bf481d7 2786bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 2787{
2788 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2789 return false;
2790
2791 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2792 MLX5_FDB_TO_VPORT_REG_C_0))
2793 return false;
2794
2795 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2796 return false;
2797
92ab1eb3
JL		 2798 return true;
2799}
2800
133dcfc5
VP		 2801u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2802{
7cd7becd 2803 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
3651168c
AL		 2804 /* Reserve 0xf for internal port offload */
2805 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
7cd7becd 2806 u32 pf_num;
133dcfc5
VP		 2807 int id;
2808
7cd7becd 2809 /* Only 4 bits of pf_num */
2810 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2811 if (pf_num > max_pf_num)
2812 return 0;
133dcfc5 2813
7cd7becd 2814 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2815 /* Use only non-zero vport_id (1-4095) for all PF's */
2816 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2817 if (id < 0)
2818 return 0;
2819 id = (pf_num << ESW_VPORT_BITS) | id;
2820 return id;
133dcfc5
VP		 2821}
2822
2823void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2824{
7cd7becd 2825 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2826
2827 /* Metadata contains only 12 bits of actual ida id */
2828 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2829}
2830
2831static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2832 struct mlx5_vport *vport)
2833{
133dcfc5
VP		 2834 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2835 vport->metadata = vport->default_metadata;
2836 return vport->metadata ? 0 : -ENOSPC;
2837}
2838
2839static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2840 struct mlx5_vport *vport)
2841{
406493a5 2842 if (!vport->default_metadata)
133dcfc5
VP		 2843 return;
2844
2845 WARN_ON(vport->metadata != vport->default_metadata);
2846 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2847}
2848
fc99c3d6
VP		 2849static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2850{
2851 struct mlx5_vport *vport;
47dd7e60 2852 unsigned long i;
fc99c3d6
VP		 2853
2854 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2855 return;
2856
47dd7e60 2857 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 2858 esw_offloads_vport_metadata_cleanup(esw, vport);
2859}
2860
2861static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2862{
2863 struct mlx5_vport *vport;
47dd7e60 2864 unsigned long i;
fc99c3d6 2865 int err;
fc99c3d6
VP		 2866
2867 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2868 return 0;
2869
47dd7e60 2870 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 2871 err = esw_offloads_vport_metadata_setup(esw, vport);
2872 if (err)
2873 goto metadata_err;
2874 }
2875
2876 return 0;
2877
2878metadata_err:
2879 esw_offloads_metadata_uninit(esw);
2880 return err;
2881}
2882
7bf481d7
PP		 2883int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable)
2884{
2885 int err = 0;
2886
2887 down_write(&esw->mode_lock);
2888 if (esw->mode != MLX5_ESWITCH_NONE) {
2889 err = -EBUSY;
2890 goto done;
2891 }
2892 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2893 err = -EOPNOTSUPP;
2894 goto done;
2895 }
2896 if (enable)
2897 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2898 else
2899 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2900done:
2901 up_write(&esw->mode_lock);
2902 return err;
2903}
2904
748da30b 2905int
89a0f1fb
PP		 2906esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2907 struct mlx5_vport *vport)
7445cfb1 2908{
7445cfb1
JL		 2909 int err;
2910
07bab950 2911 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2912 if (err)
fc99c3d6 2913 return err;
7445cfb1 2914
2c40db2f
PP		 2915 err = esw_acl_egress_ofld_setup(esw, vport);
2916 if (err)
2917 goto egress_err;
07bab950
VP		 2918
2919 return 0;
2920
2921egress_err:
2922 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2923 return err;
2924}
18486737 2925
748da30b 2926void
89a0f1fb
PP		 2927esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2928 struct mlx5_vport *vport)
2929{
ea651a86 2930 esw_acl_egress_ofld_cleanup(vport);
07bab950 2931 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2932}
7445cfb1 2933
748da30b 2934static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2935{
2936 struct mlx5_vport *vport;
18486737 2937
748da30b 2938 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2939 if (IS_ERR(vport))
2940 return PTR_ERR(vport);
2941
4e9a9ef7 2942 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2943}
2944
748da30b 2945static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2946{
786ef904 2947 struct mlx5_vport *vport;
7445cfb1 2948
748da30b 2949 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2950 if (IS_ERR(vport))
2951 return;
2952
748da30b 2953 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2954}
2955
db202995
MB		 2956int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw)
2957{
2958 struct mlx5_eswitch_rep *rep;
2959 unsigned long i;
2960 int ret;
2961
2962 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
2963 return 0;
2964
2965 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2966 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
2967 return 0;
2968
2969 ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
2970 if (ret)
2971 return ret;
2972
2973 mlx5_esw_for_each_rep(esw, i, rep) {
2974 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
2975 mlx5_esw_offloads_rep_load(esw, rep->vport);
2976 }
2977
2978 return 0;
2979}
2980
062f4bf4 2981static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 2982{
34ca6535 2983 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 2984 int err;
2985
5c1d260e 2986 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2987 mutex_init(&esw->fdb_table.offloads.vports.lock);
2988 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 2989 atomic64_set(&esw->user_count, 0);
e52c2802 2990
34ca6535
VB		 2991 indir = mlx5_esw_indir_table_init();
2992 if (IS_ERR(indir)) {
2993 err = PTR_ERR(indir);
2994 goto create_indir_err;
2995 }
2996 esw->fdb_table.offloads.indir = indir;
2997
748da30b 2998 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2999 if (err)
f8d1edda 3000 goto create_acl_err;
18486737 3001
8d6bd3c3 3002 err = esw_create_offloads_table(esw);
c930a3ad 3003 if (err)
11b717d6 3004 goto create_offloads_err;
c930a3ad 3005
11b717d6 3006 err = esw_create_restore_table(esw);
c930a3ad 3007 if (err)
11b717d6
PB		 3008 goto create_restore_err;
3009
0da3c12d 3010 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 3011 if (err)
3012 goto create_fdb_err;
c930a3ad 3013
8d6bd3c3 3014 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 3015 if (err)
3016 goto create_fg_err;
3017
3018 return 0;
3019
3020create_fg_err:
1967ce6e 3021 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 3022create_fdb_err:
11b717d6
PB		 3023 esw_destroy_restore_table(esw);
3024create_restore_err:
3025 esw_destroy_offloads_table(esw);
3026create_offloads_err:
748da30b 3027 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 3028create_acl_err:
34ca6535
VB		 3029 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3030create_indir_err:
f8d1edda 3031 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 3032 return err;
3033}
3034
eca8cc38
BW		 3035static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3036{
3037 esw_destroy_vport_rx_group(esw);
eca8cc38 3038 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 3039 esw_destroy_restore_table(esw);
3040 esw_destroy_offloads_table(esw);
748da30b 3041 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 3042 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 3043 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 3044}
3045
7e736f9a
PP		 3046static void
3047esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 3048{
5ccf2770 3049 bool host_pf_disabled;
7e736f9a 3050 u16 new_num_vfs;
a3888f33 3051
7e736f9a
PP		 3052 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3053 host_params_context.host_num_of_vfs);
5ccf2770
BW		 3054 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3055 host_params_context.host_pf_disabled);
a3888f33 3056
7e736f9a
PP		 3057 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3058 return;
a3888f33
BW		 3059
3060 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 3061 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 3062 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 3063 } else {
7e736f9a 3064 int err;
a3888f33 3065
23bb50cf
BW		 3066 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3067 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 3068 if (err)
7e736f9a 3069 return;
a3888f33 3070 }
7e736f9a 3071 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 3072}
3073
7e736f9a 3074static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 3075{
7e736f9a
PP		 3076 struct mlx5_host_work *host_work;
3077 struct mlx5_eswitch *esw;
dd28087c 3078 const u32 *out;
ac35dcd6 3079
7e736f9a
PP		 3080 host_work = container_of(work, struct mlx5_host_work, work);
3081 esw = host_work->esw;
a3888f33 3082
dd28087c
PP		 3083 out = mlx5_esw_query_functions(esw->dev);
3084 if (IS_ERR(out))
7e736f9a 3085 goto out;
a3888f33 3086
7e736f9a 3087 esw_vfs_changed_event_handler(esw, out);
dd28087c 3088 kvfree(out);
a3888f33 3089out:
ac35dcd6
VP		 3090 kfree(host_work);
3091}
3092
16fff98a 3093int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 3094{
cd56f929 3095 struct mlx5_esw_functions *esw_funcs;
a3888f33 3096 struct mlx5_host_work *host_work;
a3888f33
BW		 3097 struct mlx5_eswitch *esw;
3098
3099 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3100 if (!host_work)
3101 return NOTIFY_DONE;
3102
cd56f929
VP		 3103 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3104 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 3105
3106 host_work->esw = esw;
3107
062f4bf4 3108 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 3109 queue_work(esw->work_queue, &host_work->work);
3110
3111 return NOTIFY_OK;
3112}
3113
a53cf949
PP		 3114static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3115{
3116 const u32 *query_host_out;
3117
3118 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3119 return 0;
3120
3121 query_host_out = mlx5_esw_query_functions(esw->dev);
3122 if (IS_ERR(query_host_out))
3123 return PTR_ERR(query_host_out);
3124
3125 /* Mark non local controller with non zero controller number. */
3126 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3127 host_params_context.host_number);
3128 kvfree(query_host_out);
3129 return 0;
3130}
3131
f1b9acd3
PP		 3132bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3133{
3134 /* Local controller is always valid */
3135 if (controller == 0)
3136 return true;
3137
3138 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3139 return false;
3140
3141 /* External host number starts with zero in device */
3142 return (controller == esw->offloads.host_number + 1);
3143}
3144
5896b972 3145int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 3146{
c9355682 3147 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 3148 struct mlx5_vport *vport;
47dd7e60 3149 unsigned long i;
2198b932 3150 u64 mapping_id;
47dd7e60 3151 int err;
eca8cc38 3152
2bb72e7e 3153 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 3154 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 3155
a53cf949
PP		 3156 err = mlx5_esw_host_number_init(esw);
3157 if (err)
cd1ef966 3158 goto err_metadata;
a53cf949 3159
fc99c3d6
VP		 3160 err = esw_offloads_metadata_init(esw);
3161 if (err)
3162 goto err_metadata;
3163
332bd3a5
PP		 3164 err = esw_set_passing_vport_metadata(esw, true);
3165 if (err)
3166 goto err_vport_metadata;
c1286050 3167
2198b932
RD		 3168 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3169
3170 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3171 sizeof(struct mlx5_mapped_obj),
3172 ESW_REG_C0_USER_DATA_METADATA_MASK,
3173 true);
3174
c9355682
CM		 3175 if (IS_ERR(reg_c0_obj_pool)) {
3176 err = PTR_ERR(reg_c0_obj_pool);
3177 goto err_pool;
3178 }
3179 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3180
7983a675
PB		 3181 err = esw_offloads_steering_init(esw);
3182 if (err)
3183 goto err_steering_init;
3184
3b83b6c2
DL		 3185 /* Representor will control the vport link state */
3186 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3187 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3188
c2d7712c
BW		 3189 /* Uplink vport rep must load first. */
3190 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 3191 if (err)
c2d7712c 3192 goto err_uplink;
c1286050 3193
c2d7712c 3194 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 3195 if (err)
c2d7712c 3196 goto err_vports;
eca8cc38
BW		 3197
3198 esw_offloads_devcom_init(esw);
a3888f33 3199
eca8cc38
BW		 3200 return 0;
3201
925a6acc 3202err_vports:
c2d7712c
BW		 3203 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
3204err_uplink:
7983a675 3205 esw_offloads_steering_cleanup(esw);
79949985 3206err_steering_init:
c9355682
CM		 3207 mapping_destroy(reg_c0_obj_pool);
3208err_pool:
79949985 3209 esw_set_passing_vport_metadata(esw, false);
7983a675 3210err_vport_metadata:
fc99c3d6
VP		 3211 esw_offloads_metadata_uninit(esw);
3212err_metadata:
8463daf1 3213 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3214 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 3215 return err;
3216}
3217
db7ff19e
EB		 3218static int esw_offloads_stop(struct mlx5_eswitch *esw,
3219 struct netlink_ext_ack *extack)
c930a3ad 3220{
062f4bf4 3221 int err, err1;
c930a3ad 3222
8e0aa4bc
PP		 3223 mlx5_eswitch_disable_locked(esw, false);
3224 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
3225 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 3226 if (err) {
8c98ee77 3227 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 3228 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
3229 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 3230 if (err1) {
3231 NL_SET_ERR_MSG_MOD(extack,
3232 "Failed setting eswitch back to offloads");
3233 }
6c419ba8 3234 }
c930a3ad
OG		 3235
3236 return err;
3237}
3238
5896b972 3239void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 3240{
ac004b83 3241 esw_offloads_devcom_cleanup(esw);
5896b972 3242 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 3243 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 3244 esw_set_passing_vport_metadata(esw, false);
eca8cc38 3245 esw_offloads_steering_cleanup(esw);
c9355682 3246 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 3247 esw_offloads_metadata_uninit(esw);
8463daf1 3248 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3249 mutex_destroy(&esw->offloads.termtbl_mutex);
c930a3ad
OG		 3250}
3251
ef78618b 3252static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 3253{
3254 switch (mode) {
3255 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 3256 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 3257 break;
3258 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 3259 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 3260 break;
3261 default:
3262 return -EINVAL;
3263 }
3264
3265 return 0;
3266}
3267
ef78618b
OG		 3268static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3269{
3270 switch (mlx5_mode) {
f6455de0 3271 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 3272 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3273 break;
f6455de0 3274 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 3275 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3276 break;
3277 default:
3278 return -EINVAL;
3279 }
3280
3281 return 0;
3282}
3283
bffaa916
RD		 3284static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3285{
3286 switch (mode) {
3287 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3288 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3289 break;
3290 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3291 *mlx5_mode = MLX5_INLINE_MODE_L2;
3292 break;
3293 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3294 *mlx5_mode = MLX5_INLINE_MODE_IP;
3295 break;
3296 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3297 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3298 break;
3299 default:
3300 return -EINVAL;
3301 }
3302
3303 return 0;
3304}
3305
3306static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3307{
3308 switch (mlx5_mode) {
3309 case MLX5_INLINE_MODE_NONE:
3310 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3311 break;
3312 case MLX5_INLINE_MODE_L2:
3313 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3314 break;
3315 case MLX5_INLINE_MODE_IP:
3316 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3317 break;
3318 case MLX5_INLINE_MODE_TCP_UDP:
3319 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3320 break;
3321 default:
3322 return -EINVAL;
3323 }
3324
3325 return 0;
3326}
3327
ae24432c
PP		 3328static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
3329{
3330 /* devlink commands in NONE eswitch mode are currently supported only
3331 * on ECPF.
3332 */
3333 return (esw->mode == MLX5_ESWITCH_NONE &&
3334 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
3335}
3336
db7ff19e
EB		 3337int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3338 struct netlink_ext_ack *extack)
9d1cef19 3339{
9d1cef19 3340 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 3341 struct mlx5_eswitch *esw;
ea2128fd 3342 int err = 0;
9d1cef19 3343
bd939753
PP		 3344 esw = mlx5_devlink_eswitch_get(devlink);
3345 if (IS_ERR(esw))
3346 return PTR_ERR(esw);
9d1cef19 3347
ef78618b 3348 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 3349 return -EINVAL;
3350
cac1eb2c 3351 mlx5_lag_disable_change(esw->dev);
7dc84de9
RD		 3352 err = mlx5_esw_try_lock(esw);
3353 if (err < 0) {
3354 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
cac1eb2c 3355 goto enable_lag;
7dc84de9
RD		 3356 }
3357 cur_mlx5_mode = err;
3358 err = 0;
3359
c930a3ad 3360 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 3361 goto unlock;
c930a3ad 3362
c85a6b8f
AL		 3363 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3364 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3365 NL_SET_ERR_MSG_MOD(extack,
3366 "Can't change mode while devlink traps are active");
3367 err = -EOPNOTSUPP;
3368 goto unlock;
3369 }
8e0aa4bc 3370 err = esw_offloads_start(esw, extack);
c85a6b8f 3371 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
8e0aa4bc 3372 err = esw_offloads_stop(esw, extack);
c85a6b8f 3373 } else {
8e0aa4bc 3374 err = -EINVAL;
c85a6b8f 3375 }
8e0aa4bc
PP		 3376
3377unlock:
7dc84de9 3378 mlx5_esw_unlock(esw);
cac1eb2c
MB		 3379enable_lag:
3380 mlx5_lag_enable_change(esw->dev);
8e0aa4bc 3381 return err;
feae9087
OG		 3382}
3383
3384int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3385{
bd939753 3386 struct mlx5_eswitch *esw;
9d1cef19 3387 int err;
c930a3ad 3388
bd939753
PP		 3389 esw = mlx5_devlink_eswitch_get(devlink);
3390 if (IS_ERR(esw))
3391 return PTR_ERR(esw);
c930a3ad 3392
c55479d0 3393 down_write(&esw->mode_lock);
bd939753 3394 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 3395 if (err)
8e0aa4bc 3396 goto unlock;
ae24432c 3397
8e0aa4bc
PP		 3398 err = esw_mode_to_devlink(esw->mode, mode);
3399unlock:
c55479d0 3400 up_write(&esw->mode_lock);
8e0aa4bc 3401 return err;
feae9087 3402}
127ea380 3403
47dd7e60
PP		 3404static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3405 struct netlink_ext_ack *extack)
3406{
3407 struct mlx5_core_dev *dev = esw->dev;
3408 struct mlx5_vport *vport;
3409 u16 err_vport_num = 0;
3410 unsigned long i;
3411 int err = 0;
3412
3413 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3414 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3415 if (err) {
3416 err_vport_num = vport->vport;
3417 NL_SET_ERR_MSG_MOD(extack,
3418 "Failed to set min inline on vport");
3419 goto revert_inline_mode;
3420 }
3421 }
3422 return 0;
3423
3424revert_inline_mode:
3425 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3426 if (vport->vport == err_vport_num)
3427 break;
3428 mlx5_modify_nic_vport_min_inline(dev,
3429 vport->vport,
3430 esw->offloads.inline_mode);
3431 }
3432 return err;
3433}
3434
db7ff19e
EB		 3435int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3436 struct netlink_ext_ack *extack)
bffaa916
RD		 3437{
3438 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3439 struct mlx5_eswitch *esw;
bffaa916 3440 u8 mlx5_mode;
47dd7e60 3441 int err;
bffaa916 3442
bd939753
PP		 3443 esw = mlx5_devlink_eswitch_get(devlink);
3444 if (IS_ERR(esw))
3445 return PTR_ERR(esw);
bffaa916 3446
c55479d0 3447 down_write(&esw->mode_lock);
ae24432c
PP		 3448 err = eswitch_devlink_esw_mode_check(esw);
3449 if (err)
8e0aa4bc 3450 goto out;
ae24432c 3451
c415f704
OG		 3452 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3453 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
bcd68c04
JC		 3454 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3455 err = 0;
8e0aa4bc 3456 goto out;
bcd68c04
JC		 3457 }
3458
c8b838d1 3459 fallthrough;
c415f704 3460 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3461 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3462 err = -EOPNOTSUPP;
3463 goto out;
c415f704
OG		 3464 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3465 break;
3466 }
bffaa916 3467
525e84be 3468 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3469 NL_SET_ERR_MSG_MOD(extack,
3470 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3471 err = -EOPNOTSUPP;
3472 goto out;
375f51e2
RD		 3473 }
3474
bffaa916
RD		 3475 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3476 if (err)
3477 goto out;
3478
47dd7e60
PP		 3479 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3480 if (err)
3481 goto out;
bffaa916
RD		 3482
3483 esw->offloads.inline_mode = mlx5_mode;
c55479d0 3484 up_write(&esw->mode_lock);
bffaa916
RD		 3485 return 0;
3486
bffaa916 3487out:
c55479d0 3488 up_write(&esw->mode_lock);
bffaa916
RD		 3489 return err;
3490}
3491
3492int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3493{
bd939753 3494 struct mlx5_eswitch *esw;
9d1cef19 3495 int err;
bffaa916 3496
bd939753
PP		 3497 esw = mlx5_devlink_eswitch_get(devlink);
3498 if (IS_ERR(esw))
3499 return PTR_ERR(esw);
bffaa916 3500
c55479d0 3501 down_write(&esw->mode_lock);
ae24432c
PP		 3502 err = eswitch_devlink_esw_mode_check(esw);
3503 if (err)
8e0aa4bc 3504 goto unlock;
ae24432c 3505
8e0aa4bc
PP		 3506 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3507unlock:
c55479d0 3508 up_write(&esw->mode_lock);
8e0aa4bc 3509 return err;
bffaa916
RD		 3510}
3511
98fdbea5
LR		 3512int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3513 enum devlink_eswitch_encap_mode encap,
db7ff19e 3514 struct netlink_ext_ack *extack)
7768d197
RD		 3515{
3516 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3517 struct mlx5_eswitch *esw;
7768d197
RD		 3518 int err;
3519
bd939753
PP		 3520 esw = mlx5_devlink_eswitch_get(devlink);
3521 if (IS_ERR(esw))
3522 return PTR_ERR(esw);
7768d197 3523
c55479d0 3524 down_write(&esw->mode_lock);
ae24432c
PP		 3525 err = eswitch_devlink_esw_mode_check(esw);
3526 if (err)
8e0aa4bc 3527 goto unlock;
ae24432c 3528
7768d197 3529 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3530 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3531 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3532 err = -EOPNOTSUPP;
3533 goto unlock;
3534 }
7768d197 3535
8e0aa4bc
PP		 3536 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3537 err = -EOPNOTSUPP;
3538 goto unlock;
3539 }
7768d197 3540
f6455de0 3541 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3542 esw->offloads.encap = encap;
8e0aa4bc 3543 goto unlock;
7768d197
RD		 3544 }
3545
3546 if (esw->offloads.encap == encap)
8e0aa4bc 3547 goto unlock;
7768d197 3548
525e84be 3549 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3550 NL_SET_ERR_MSG_MOD(extack,
3551 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3552 err = -EOPNOTSUPP;
3553 goto unlock;
7768d197
RD		 3554 }
3555
e52c2802 3556 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3557
3558 esw->offloads.encap = encap;
e52c2802 3559
0da3c12d 3560 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3561
7768d197 3562 if (err) {
8c98ee77
EB		 3563 NL_SET_ERR_MSG_MOD(extack,
3564 "Failed re-creating fast FDB table");
7768d197 3565 esw->offloads.encap = !encap;
0da3c12d 3566 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3567 }
e52c2802 3568
8e0aa4bc 3569unlock:
c55479d0 3570 up_write(&esw->mode_lock);
7768d197
RD		 3571 return err;
3572}
3573
98fdbea5
LR		 3574int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3575 enum devlink_eswitch_encap_mode *encap)
7768d197 3576{
bd939753 3577 struct mlx5_eswitch *esw;
9d1cef19 3578 int err;
7768d197 3579
bd939753
PP		 3580 esw = mlx5_devlink_eswitch_get(devlink);
3581 if (IS_ERR(esw))
3582 return PTR_ERR(esw);
3583
7768d197 3584
c55479d0 3585 down_write(&esw->mode_lock);
ae24432c
PP		 3586 err = eswitch_devlink_esw_mode_check(esw);
3587 if (err)
8e0aa4bc 3588 goto unlock;
ae24432c 3589
7768d197 3590 *encap = esw->offloads.encap;
8e0aa4bc 3591unlock:
c55479d0 3592 up_write(&esw->mode_lock);
234fa109 3593 return err;
7768d197
RD		 3594}
3595
c2d7712c
BW		 3596static bool
3597mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3598{
3599 /* Currently, only ECPF based device has representor for host PF. */
3600 if (vport_num == MLX5_VPORT_PF &&
3601 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3602 return false;
3603
3604 if (vport_num == MLX5_VPORT_ECPF &&
3605 !mlx5_ecpf_vport_exists(esw->dev))
3606 return false;
3607
3608 return true;
3609}
3610
f8e8fa02 3611void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 3612 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 3613 u8 rep_type)
127ea380 3614{
8693115a 3615 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 3616 struct mlx5_eswitch_rep *rep;
47dd7e60 3617 unsigned long i;
9deb2241 3618
8693115a 3619 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 3620 mlx5_esw_for_each_rep(esw, i, rep) {
3621 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 3622 rep->esw = esw;
c2d7712c
BW		 3623 rep_data = &rep->rep_data[rep_type];
3624 atomic_set(&rep_data->state, REP_REGISTERED);
3625 }
f8e8fa02 3626 }
127ea380 3627}
f8e8fa02 3628EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 3629
f8e8fa02 3630void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 3631{
cb67b832 3632 struct mlx5_eswitch_rep *rep;
47dd7e60 3633 unsigned long i;
cb67b832 3634
f6455de0 3635 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 3636 __unload_reps_all_vport(esw, rep_type);
127ea380 3637
47dd7e60 3638 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 3639 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 3640}
f8e8fa02 3641EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 3642
a4b97ab4 3643void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 3644{
726293f1
HHZ		 3645 struct mlx5_eswitch_rep *rep;
3646
879c8f84 3647 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 3648 return rep->rep_data[rep_type].priv;
726293f1 3649}
22215908
MB		 3650
3651void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 3652 u16 vport,
22215908
MB		 3653 u8 rep_type)
3654{
22215908
MB		 3655 struct mlx5_eswitch_rep *rep;
3656
879c8f84 3657 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 3658
8693115a
PP		 3659 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3660 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3661 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 3662 return NULL;
3663}
57cbd893 3664EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 3665
3666void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3667{
879c8f84 3668 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 3669}
57cbd893
MB		 3670EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3671
3672struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 3673 u16 vport)
57cbd893 3674{
879c8f84 3675 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 3676}
3677EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 3678
5b7cb745
PB		 3679bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3680{
3681 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3682}
3683EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3684
7445cfb1
JL		 3685bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3686{
3687 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3688}
3689EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3690
0f0d3827 3691u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 3692 u16 vport_num)
3693{
133dcfc5 3694 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 3695
133dcfc5
VP		 3696 if (WARN_ON_ONCE(IS_ERR(vport)))
3697 return 0;
0f0d3827 3698
133dcfc5 3699 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 3700}
3701EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 3702
3703int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 3704 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 3705{
3706 int err;
3707
3708 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3709 if (err)
3710 return err;
3711
f1b9acd3 3712 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 3713 if (err)
3714 goto devlink_err;
3715
3716 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3717 if (err)
3718 goto rep_err;
3719 return 0;
3720
3721rep_err:
3722 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3723devlink_err:
3724 mlx5_esw_vport_disable(esw, vport_num);
3725 return err;
3726}
3727
3728void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3729{
3730 mlx5_esw_offloads_rep_unload(esw, vport_num);
3731 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3732 mlx5_esw_vport_disable(esw, vport_num);
3733}
84ae9c1f
VB		 3734
3735static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3736{
3737 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3738 void *query_ctx;
3739 void *hca_caps;
3740 int err;
3741
3742 *vhca_id = 0;
3743 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3744 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3745 return -EPERM;
3746
3747 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3748 if (!query_ctx)
3749 return -ENOMEM;
3750
3751 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx);
3752 if (err)
3753 goto out_free;
3754
3755 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3756 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3757
3758out_free:
3759 kfree(query_ctx);
3760 return err;
3761}
3762
3763int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3764{
3765 u16 *old_entry, *vhca_map_entry, vhca_id;
3766 int err;
3767
3768 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3769 if (err) {
3770 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3771 vport_num, err);
3772 return err;
3773 }
3774
3775 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3776 if (!vhca_map_entry)
3777 return -ENOMEM;
3778
3779 *vhca_map_entry = vport_num;
3780 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3781 if (xa_is_err(old_entry)) {
3782 kfree(vhca_map_entry);
3783 return xa_err(old_entry);
3784 }
3785 kfree(old_entry);
3786 return 0;
3787}
3788
3789void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3790{
3791 u16 *vhca_map_entry, vhca_id;
3792 int err;
3793
3794 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3795 if (err)
3796 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3797 vport_num, err);
3798
3799 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3800 kfree(vhca_map_entry);
3801}
3802
3803int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3804{
3805 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3806
3807 if (!res)
3808 return -ENOENT;
3809
3810 *vport_num = *res;
3811 return 0;
3812}
10742efc
VB		 3813
3814u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3815 u16 vport_num)
3816{
3817 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3818
3819 if (WARN_ON_ONCE(IS_ERR(vport)))
3820 return 0;
3821
3822 return vport->metadata;
3823}
3824EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
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