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net/mlx5: E-switch, Prepare eswitch to handle SF vport
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
ea651a86 41#include "esw/acl/ofld.h"
80f09dfc 42#include "rdma.h"
e52c2802
PB		 43#include "en.h"
44#include "fs_core.h"
ac004b83 45#include "lib/devcom.h"
a3888f33 46#include "lib/eq.h"
ae430332 47#include "lib/fs_chains.h"
c620b772 48#include "en_tc.h"
69697b6e 49
cd7e4186
BW		 50/* There are two match-all miss flows, one for unicast dst mac and
51 * one for multicast.
52 */
53#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 54#define UPLINK_REP_INDEX 0
55
96e32687
EC		 56/* Per vport tables */
57
58#define MLX5_ESW_VPORT_TABLE_SIZE 128
59
60/* This struct is used as a key to the hash table and we need it to be packed
61 * so hash result is consistent
62 */
63struct mlx5_vport_key {
64 u32 chain;
65 u16 prio;
66 u16 vport;
67 u16 vhca_id;
68} __packed;
69
c620b772
AL		 70struct mlx5_vport_tbl_attr {
71 u16 chain;
72 u16 prio;
73 u16 vport;
74};
75
96e32687
EC		 76struct mlx5_vport_table {
77 struct hlist_node hlist;
78 struct mlx5_flow_table *fdb;
79 u32 num_rules;
80 struct mlx5_vport_key key;
81};
82
87dac697
JL		 83#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
84
96e32687
EC		 85static struct mlx5_flow_table *
86esw_vport_tbl_create(struct mlx5_eswitch *esw, struct mlx5_flow_namespace *ns)
87{
88 struct mlx5_flow_table_attr ft_attr = {};
89 struct mlx5_flow_table *fdb;
90
87dac697 91 ft_attr.autogroup.max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS;
96e32687
EC		 92 ft_attr.max_fte = MLX5_ESW_VPORT_TABLE_SIZE;
93 ft_attr.prio = FDB_PER_VPORT;
94 fdb = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
95 if (IS_ERR(fdb)) {
96 esw_warn(esw->dev, "Failed to create per vport FDB Table err %ld\n",
97 PTR_ERR(fdb));
98 }
99
100 return fdb;
101}
102
103static u32 flow_attr_to_vport_key(struct mlx5_eswitch *esw,
c620b772 104 struct mlx5_vport_tbl_attr *attr,
96e32687
EC		 105 struct mlx5_vport_key *key)
106{
c620b772 107 key->vport = attr->vport;
96e32687
EC		 108 key->chain = attr->chain;
109 key->prio = attr->prio;
110 key->vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
111 return jhash(key, sizeof(*key), 0);
112}
113
114/* caller must hold vports.lock */
115static struct mlx5_vport_table *
116esw_vport_tbl_lookup(struct mlx5_eswitch *esw, struct mlx5_vport_key *skey, u32 key)
117{
118 struct mlx5_vport_table *e;
119
120 hash_for_each_possible(esw->fdb_table.offloads.vports.table, e, hlist, key)
121 if (!memcmp(&e->key, skey, sizeof(*skey)))
122 return e;
123
124 return NULL;
125}
126
127static void
c620b772 128esw_vport_tbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr)
96e32687
EC		 129{
130 struct mlx5_vport_table *e;
131 struct mlx5_vport_key key;
132 u32 hkey;
133
134 mutex_lock(&esw->fdb_table.offloads.vports.lock);
135 hkey = flow_attr_to_vport_key(esw, attr, &key);
136 e = esw_vport_tbl_lookup(esw, &key, hkey);
137 if (!e || --e->num_rules)
138 goto out;
139
140 hash_del(&e->hlist);
141 mlx5_destroy_flow_table(e->fdb);
142 kfree(e);
143out:
144 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
145}
146
147static struct mlx5_flow_table *
c620b772 148esw_vport_tbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr)
96e32687
EC		 149{
150 struct mlx5_core_dev *dev = esw->dev;
151 struct mlx5_flow_namespace *ns;
152 struct mlx5_flow_table *fdb;
153 struct mlx5_vport_table *e;
154 struct mlx5_vport_key skey;
155 u32 hkey;
156
157 mutex_lock(&esw->fdb_table.offloads.vports.lock);
158 hkey = flow_attr_to_vport_key(esw, attr, &skey);
159 e = esw_vport_tbl_lookup(esw, &skey, hkey);
160 if (e) {
161 e->num_rules++;
162 goto out;
163 }
164
165 e = kzalloc(sizeof(*e), GFP_KERNEL);
166 if (!e) {
167 fdb = ERR_PTR(-ENOMEM);
168 goto err_alloc;
169 }
170
171 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
172 if (!ns) {
173 esw_warn(dev, "Failed to get FDB namespace\n");
174 fdb = ERR_PTR(-ENOENT);
175 goto err_ns;
176 }
177
178 fdb = esw_vport_tbl_create(esw, ns);
179 if (IS_ERR(fdb))
180 goto err_ns;
181
182 e->fdb = fdb;
183 e->num_rules = 1;
184 e->key = skey;
185 hash_add(esw->fdb_table.offloads.vports.table, &e->hlist, hkey);
186out:
187 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
188 return e->fdb;
189
190err_ns:
191 kfree(e);
192err_alloc:
193 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
194 return fdb;
195}
196
197int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw)
198{
c620b772 199 struct mlx5_vport_tbl_attr attr;
96e32687
EC		 200 struct mlx5_flow_table *fdb;
201 struct mlx5_vport *vport;
202 int i;
203
c620b772 204 attr.chain = 0;
96e32687 205 attr.prio = 1;
96e32687 206 mlx5_esw_for_all_vports(esw, i, vport) {
c620b772 207 attr.vport = vport->vport;
96e32687 208 fdb = esw_vport_tbl_get(esw, &attr);
d9fb932f 209 if (IS_ERR(fdb))
96e32687
EC		 210 goto out;
211 }
212 return 0;
213
214out:
215 mlx5_esw_vport_tbl_put(esw);
216 return PTR_ERR(fdb);
217}
218
219void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw)
220{
c620b772 221 struct mlx5_vport_tbl_attr attr;
96e32687
EC		 222 struct mlx5_vport *vport;
223 int i;
224
c620b772 225 attr.chain = 0;
96e32687 226 attr.prio = 1;
96e32687 227 mlx5_esw_for_all_vports(esw, i, vport) {
c620b772 228 attr.vport = vport->vport;
96e32687
EC		 229 esw_vport_tbl_put(esw, &attr);
230 }
231}
232
233/* End: Per vport tables */
234
879c8f84
BW		 235static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
236 u16 vport_num)
237{
02f3afd9 238 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
879c8f84
BW		 239
240 WARN_ON(idx > esw->total_vports - 1);
241 return &esw->offloads.vport_reps[idx];
242}
243
6f7bbad1
JL		 244static void
245mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
246 struct mlx5_flow_spec *spec,
247 struct mlx5_esw_flow_attr *attr)
248{
249 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
036e19b9
HI		 250 attr && attr->in_rep)
251 spec->flow_context.flow_source =
252 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
253 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
254 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 255}
b7826076 256
c01cfd0f
JL		 257static void
258mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
259 struct mlx5_flow_spec *spec,
260 struct mlx5_esw_flow_attr *attr)
261{
262 void *misc2;
263 void *misc;
264
265 /* Use metadata matching because vport is not represented by single
266 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
267 */
268 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
269 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
270 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
271 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
272 attr->in_rep->vport));
273
274 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 275 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
276 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 277
278 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 279 } else {
280 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
281 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
282
283 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
284 MLX5_SET(fte_match_set_misc, misc,
285 source_eswitch_owner_vhca_id,
286 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
287
288 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
289 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
290 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
291 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
292 source_eswitch_owner_vhca_id);
293
294 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
295 }
c01cfd0f
JL		 296}
297
74491de9 298struct mlx5_flow_handle *
3d80d1a2
OG		 299mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
300 struct mlx5_flow_spec *spec,
c620b772 301 struct mlx5_flow_attr *attr)
3d80d1a2 302{
592d3651 303 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 304 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 305 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 306 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 307 bool split = !!(esw_attr->split_count);
308 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 309 struct mlx5_flow_handle *rule;
e52c2802 310 struct mlx5_flow_table *fdb;
592d3651 311 int j, i = 0;
3d80d1a2 312
f6455de0 313 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 314 return ERR_PTR(-EOPNOTSUPP);
315
6acfbf38
OG		 316 flow_act.action = attr->action;
317 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 318 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 319 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
320 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
321 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 322 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
323 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
324 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 325 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 326 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
327 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
328 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 329 }
6acfbf38 330 }
776b12b6 331
66958ed9 332 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
39ac237c 333 struct mlx5_flow_table *ft;
e52c2802 334
d18296ff
PB		 335 if (attr->dest_ft) {
336 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
337 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
338 dest[i].ft = attr->dest_ft;
339 i++;
340 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
39ac237c
PB		 341 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
342 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
ae430332 343 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
39ac237c
PB		 344 i++;
345 } else if (attr->dest_chain) {
346 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
ae430332
AL		 347 ft = mlx5_chains_get_table(chains, attr->dest_chain,
348 1, 0);
e52c2802
PB		 349 if (IS_ERR(ft)) {
350 rule = ERR_CAST(ft);
351 goto err_create_goto_table;
352 }
353
354 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
355 dest[i].ft = ft;
592d3651 356 i++;
e52c2802 357 } else {
c620b772 358 for (j = esw_attr->split_count; j < esw_attr->out_count; j++) {
e52c2802 359 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
c620b772 360 dest[i].vport.num = esw_attr->dests[j].rep->vport;
e52c2802 361 dest[i].vport.vhca_id =
c620b772 362 MLX5_CAP_GEN(esw_attr->dests[j].mdev, vhca_id);
aa39c2c0
EB		 363 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
364 dest[i].vport.flags |=
365 MLX5_FLOW_DEST_VPORT_VHCA_ID;
c620b772 366 if (esw_attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
f493f155 367 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
c620b772
AL		 368 flow_act.pkt_reformat =
369 esw_attr->dests[j].pkt_reformat;
a18e879d 370 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
2b688ea5 371 dest[i].vport.pkt_reformat =
c620b772 372 esw_attr->dests[j].pkt_reformat;
f493f155 373 }
e52c2802
PB		 374 i++;
375 }
56e858df 376 }
e37a79e5 377 }
14e6b038 378
c620b772
AL		 379 if (esw_attr->decap_pkt_reformat)
380 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 381
66958ed9 382 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 383 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 384 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 385 i++;
3d80d1a2
OG		 386 }
387
93b3586e 388 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 389 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 390 if (attr->inner_match_level != MLX5_MATCH_NONE)
391 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 392
aa24670e 393 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 394 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 395
96e32687 396 if (split) {
c620b772
AL		 397 fwd_attr.chain = attr->chain;
398 fwd_attr.prio = attr->prio;
399 fwd_attr.vport = esw_attr->in_rep->vport;
400
401 fdb = esw_vport_tbl_get(esw, &fwd_attr);
96e32687 402 } else {
d18296ff 403 if (attr->chain || attr->prio)
ae430332
AL		 404 fdb = mlx5_chains_get_table(chains, attr->chain,
405 attr->prio, 0);
d18296ff 406 else
c620b772 407 fdb = attr->ft;
6fb0701a
PB		 408
409 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
c620b772 410 mlx5_eswitch_set_rule_source_port(esw, spec, esw_attr);
96e32687 411 }
e52c2802
PB		 412 if (IS_ERR(fdb)) {
413 rule = ERR_CAST(fdb);
414 goto err_esw_get;
415 }
416
c620b772 417 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
6f7bbad1 418
84be2fda 419 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 420 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 421 &flow_act, dest, i);
84be2fda 422 else
10caabda 423 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 424 if (IS_ERR(rule))
e52c2802 425 goto err_add_rule;
375f51e2 426 else
525e84be 427 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 428
e52c2802
PB		 429 return rule;
430
431err_add_rule:
96e32687 432 if (split)
c620b772 433 esw_vport_tbl_put(esw, &fwd_attr);
d18296ff 434 else if (attr->chain || attr->prio)
ae430332 435 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 436err_esw_get:
39ac237c 437 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) && attr->dest_chain)
ae430332 438 mlx5_chains_put_table(chains, attr->dest_chain, 1, 0);
e52c2802 439err_create_goto_table:
aa0cbbae 440 return rule;
3d80d1a2
OG		 441}
442
e4ad91f2
CM		 443struct mlx5_flow_handle *
444mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
445 struct mlx5_flow_spec *spec,
c620b772 446 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 447{
448 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 449 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 450 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 451 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 452 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 453 struct mlx5_flow_table *fast_fdb;
454 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 455 struct mlx5_flow_handle *rule;
e4ad91f2
CM		 456 int i;
457
ae430332 458 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 459 if (IS_ERR(fast_fdb)) {
460 rule = ERR_CAST(fast_fdb);
461 goto err_get_fast;
462 }
463
c620b772
AL		 464 fwd_attr.chain = attr->chain;
465 fwd_attr.prio = attr->prio;
466 fwd_attr.vport = esw_attr->in_rep->vport;
467 fwd_fdb = esw_vport_tbl_get(esw, &fwd_attr);
e52c2802
PB		 468 if (IS_ERR(fwd_fdb)) {
469 rule = ERR_CAST(fwd_fdb);
470 goto err_get_fwd;
471 }
472
e4ad91f2 473 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
c620b772 474 for (i = 0; i < esw_attr->split_count; i++) {
e4ad91f2 475 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
c620b772 476 dest[i].vport.num = esw_attr->dests[i].rep->vport;
e4ad91f2 477 dest[i].vport.vhca_id =
c620b772 478 MLX5_CAP_GEN(esw_attr->dests[i].mdev, vhca_id);
aa39c2c0
EB		 479 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
480 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
c620b772 481 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
1cc26d74 482 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
c620b772 483 dest[i].vport.pkt_reformat = esw_attr->dests[i].pkt_reformat;
1cc26d74 484 }
e4ad91f2
CM		 485 }
486 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 487 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 488 i++;
489
c620b772 490 mlx5_eswitch_set_rule_source_port(esw, spec, esw_attr);
e4ad91f2 491
93b3586e 492 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 493 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 494
278d51f2 495 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 496 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 497
e52c2802
PB		 498 if (IS_ERR(rule))
499 goto add_err;
e4ad91f2 500
525e84be 501 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 502
503 return rule;
504add_err:
c620b772 505 esw_vport_tbl_put(esw, &fwd_attr);
e52c2802 506err_get_fwd:
ae430332 507 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 508err_get_fast:
e4ad91f2
CM		 509 return rule;
510}
511
e52c2802
PB		 512static void
513__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
514 struct mlx5_flow_handle *rule,
c620b772 515 struct mlx5_flow_attr *attr,
e52c2802
PB		 516 bool fwd_rule)
517{
c620b772 518 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 519 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 520 bool split = (esw_attr->split_count > 0);
521 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 522 int i;
e52c2802
PB		 523
524 mlx5_del_flow_rules(rule);
10caabda 525
84be2fda 526 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 527 /* unref the term table */
528 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 529 if (esw_attr->dests[i].termtbl)
530 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 531 }
10caabda
OS		 532 }
533
525e84be 534 atomic64_dec(&esw->offloads.num_flows);
e52c2802 535
c620b772
AL		 536 if (fwd_rule || split) {
537 fwd_attr.chain = attr->chain;
538 fwd_attr.prio = attr->prio;
539 fwd_attr.vport = esw_attr->in_rep->vport;
540 }
541
e52c2802 542 if (fwd_rule) {
c620b772 543 esw_vport_tbl_put(esw, &fwd_attr);
ae430332 544 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 545 } else {
96e32687 546 if (split)
c620b772 547 esw_vport_tbl_put(esw, &fwd_attr);
d18296ff 548 else if (attr->chain || attr->prio)
ae430332 549 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 550 if (attr->dest_chain)
ae430332 551 mlx5_chains_put_table(chains, attr->dest_chain, 1, 0);
e52c2802
PB		 552 }
553}
554
d85cdccb
OG		 555void
556mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
557 struct mlx5_flow_handle *rule,
c620b772 558 struct mlx5_flow_attr *attr)
d85cdccb 559{
e52c2802 560 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 561}
562
48265006
OG		 563void
564mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
565 struct mlx5_flow_handle *rule,
c620b772 566 struct mlx5_flow_attr *attr)
48265006 567{
e52c2802 568 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 569}
570
f5f82476
OG		 571static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
572{
573 struct mlx5_eswitch_rep *rep;
411ec9e0 574 int i, err = 0;
f5f82476
OG		 575
576 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
411ec9e0 577 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 578 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 579 continue;
580
581 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
582 if (err)
583 goto out;
584 }
585
586out:
587 return err;
588}
589
590static struct mlx5_eswitch_rep *
591esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
592{
593 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
594
595 in_rep = attr->in_rep;
df65a573 596 out_rep = attr->dests[0].rep;
f5f82476
OG		 597
598 if (push)
599 vport = in_rep;
600 else if (pop)
601 vport = out_rep;
602 else
603 vport = in_rep;
604
605 return vport;
606}
607
608static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
609 bool push, bool pop, bool fwd)
610{
611 struct mlx5_eswitch_rep *in_rep, *out_rep;
612
613 if ((push || pop) && !fwd)
614 goto out_notsupp;
615
616 in_rep = attr->in_rep;
df65a573 617 out_rep = attr->dests[0].rep;
f5f82476 618
b05af6aa 619 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 620 goto out_notsupp;
621
b05af6aa 622 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 623 goto out_notsupp;
624
625 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
626 if (!push && !pop && fwd)
b05af6aa 627 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 628 goto out_notsupp;
629
630 /* protects against (1) setting rules with different vlans to push and
631 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
632 */
1482bd3d 633 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 634 goto out_notsupp;
635
636 return 0;
637
638out_notsupp:
9eb78923 639 return -EOPNOTSUPP;
f5f82476
OG		 640}
641
642int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 643 struct mlx5_flow_attr *attr)
f5f82476
OG		 644{
645 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 646 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 647 struct mlx5_eswitch_rep *vport = NULL;
648 bool push, pop, fwd;
649 int err = 0;
650
6acfbf38 651 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 652 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 653 return 0;
654
f5f82476
OG		 655 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
656 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 657 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
658 !attr->dest_chain);
f5f82476 659
0e18134f
VB		 660 mutex_lock(&esw->state_lock);
661
c620b772 662 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 663 if (err)
0e18134f 664 goto unlock;
f5f82476 665
39ac237c 666 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 667
c620b772 668 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 669
670 if (!push && !pop && fwd) {
671 /* tracks VF --> wire rules without vlan push action */
c620b772 672 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 673 vport->vlan_refcount++;
39ac237c 674 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 675 }
676
0e18134f 677 goto unlock;
f5f82476
OG		 678 }
679
680 if (!push && !pop)
0e18134f 681 goto unlock;
f5f82476
OG		 682
683 if (!(offloads->vlan_push_pop_refcount)) {
684 /* it's the 1st vlan rule, apply global vlan pop policy */
685 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
686 if (err)
687 goto out;
688 }
689 offloads->vlan_push_pop_refcount++;
690
691 if (push) {
692 if (vport->vlan_refcount)
693 goto skip_set_push;
694
c620b772
AL		 695 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
696 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 697 if (err)
698 goto out;
c620b772 699 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 700skip_set_push:
701 vport->vlan_refcount++;
702 }
703out:
704 if (!err)
39ac237c 705 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 706unlock:
707 mutex_unlock(&esw->state_lock);
f5f82476
OG		 708 return err;
709}
710
711int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 712 struct mlx5_flow_attr *attr)
f5f82476
OG		 713{
714 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 715 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 716 struct mlx5_eswitch_rep *vport = NULL;
717 bool push, pop, fwd;
718 int err = 0;
719
6acfbf38 720 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 721 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 722 return 0;
723
39ac237c 724 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 725 return 0;
726
727 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
728 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
729 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
730
0e18134f
VB		 731 mutex_lock(&esw->state_lock);
732
c620b772 733 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 734
735 if (!push && !pop && fwd) {
736 /* tracks VF --> wire rules without vlan push action */
c620b772 737 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 738 vport->vlan_refcount--;
739
0e18134f 740 goto out;
f5f82476
OG		 741 }
742
743 if (push) {
744 vport->vlan_refcount--;
745 if (vport->vlan_refcount)
746 goto skip_unset_push;
747
748 vport->vlan = 0;
749 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
750 0, 0, SET_VLAN_STRIP);
751 if (err)
752 goto out;
753 }
754
755skip_unset_push:
756 offloads->vlan_push_pop_refcount--;
757 if (offloads->vlan_push_pop_refcount)
0e18134f 758 goto out;
f5f82476
OG		 759
760 /* no more vlan rules, stop global vlan pop policy */
761 err = esw_set_global_vlan_pop(esw, 0);
762
763out:
0e18134f 764 mutex_unlock(&esw->state_lock);
f5f82476
OG		 765 return err;
766}
767
f7a68945 768struct mlx5_flow_handle *
02f3afd9
PP		 769mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
770 u32 sqn)
ab22be9b 771{
66958ed9 772 struct mlx5_flow_act flow_act = {0};
4c5009c5 773 struct mlx5_flow_destination dest = {};
74491de9 774 struct mlx5_flow_handle *flow_rule;
c5bb1730 775 struct mlx5_flow_spec *spec;
ab22be9b
OG		 776 void *misc;
777
1b9a07ee 778 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 779 if (!spec) {
ab22be9b
OG		 780 flow_rule = ERR_PTR(-ENOMEM);
781 goto out;
782 }
783
c5bb1730 784 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 785 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a
BW		 786 /* source vport is the esw manager */
787 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
ab22be9b 788
c5bb1730 789 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 790 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
791 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
792
c5bb1730 793 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 794 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 795 dest.vport.num = vport;
66958ed9 796 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 797
39ac237c
PB		 798 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
799 spec, &flow_act, &dest, 1);
ab22be9b
OG		 800 if (IS_ERR(flow_rule))
801 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
802out:
c5bb1730 803 kvfree(spec);
ab22be9b
OG		 804 return flow_rule;
805}
57cbd893 806EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 807
159fe639
MB		 808void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
809{
810 mlx5_del_flow_rules(rule);
811}
812
5b7cb745
PB		 813static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
814{
815 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
816 MLX5_FDB_TO_VPORT_REG_C_1;
817}
818
332bd3a5 819static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 820{
821 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 822 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
823 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 824 u8 curr, wanted;
c1286050
JL		 825 int err;
826
5b7cb745
PB		 827 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
828 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 829 return 0;
c1286050 830
e08a6832
LR		 831 MLX5_SET(query_esw_vport_context_in, in, opcode,
832 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
833 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 834 if (err)
835 return err;
836
5b7cb745
PB		 837 curr = MLX5_GET(query_esw_vport_context_out, out,
838 esw_vport_context.fdb_to_vport_reg_c_id);
839 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
840 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
841 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 842
332bd3a5 843 if (enable)
5b7cb745 844 curr |= wanted;
332bd3a5 845 else
5b7cb745 846 curr &= ~wanted;
c1286050 847
e08a6832 848 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 849 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 850 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 851 field_select.fdb_to_vport_reg_c_id, 1);
852
e08a6832 853 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 854 if (!err) {
855 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
856 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
857 else
858 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
859 }
860
861 return err;
c1286050
JL		 862}
863
a5641cb5
JL		 864static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
865 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 866 struct mlx5_flow_spec *spec,
867 struct mlx5_flow_destination *dest)
868{
a5641cb5 869 void *misc;
ac004b83 870
a5641cb5
JL		 871 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
872 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
873 misc_parameters_2);
0f0d3827
PB		 874 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
875 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 876
a5641cb5
JL		 877 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
878 } else {
879 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
880 misc_parameters);
ac004b83 881
a5641cb5
JL		 882 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
883 MLX5_CAP_GEN(peer_dev, vhca_id));
884
885 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
886
887 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
888 misc_parameters);
889 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
890 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
891 source_eswitch_owner_vhca_id);
892 }
ac004b83
RD		 893
894 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 895 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 896 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 897 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 898}
899
a5641cb5
JL		 900static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
901 struct mlx5_eswitch *peer_esw,
902 struct mlx5_flow_spec *spec,
903 u16 vport)
904{
905 void *misc;
906
907 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
908 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
909 misc_parameters_2);
910 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
911 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
912 vport));
913 } else {
914 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
915 misc_parameters);
916 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
917 }
918}
919
ac004b83
RD		 920static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
921 struct mlx5_core_dev *peer_dev)
922{
923 struct mlx5_flow_destination dest = {};
924 struct mlx5_flow_act flow_act = {0};
925 struct mlx5_flow_handle **flows;
926 struct mlx5_flow_handle *flow;
927 struct mlx5_flow_spec *spec;
928 /* total vports is the same for both e-switches */
929 int nvports = esw->total_vports;
930 void *misc;
931 int err, i;
932
933 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
934 if (!spec)
935 return -ENOMEM;
936
a5641cb5 937 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 938
939 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
940 if (!flows) {
941 err = -ENOMEM;
942 goto alloc_flows_err;
943 }
944
945 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
946 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
947 misc_parameters);
948
81cd229c 949 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
a5641cb5
JL		 950 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
951 spec, MLX5_VPORT_PF);
952
81cd229c
BW		 953 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
954 spec, &flow_act, &dest, 1);
955 if (IS_ERR(flow)) {
956 err = PTR_ERR(flow);
957 goto add_pf_flow_err;
958 }
959 flows[MLX5_VPORT_PF] = flow;
960 }
961
962 if (mlx5_ecpf_vport_exists(esw->dev)) {
963 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
964 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
965 spec, &flow_act, &dest, 1);
966 if (IS_ERR(flow)) {
967 err = PTR_ERR(flow);
968 goto add_ecpf_flow_err;
969 }
970 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
971 }
972
786ef904 973 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 974 esw_set_peer_miss_rule_source_port(esw,
975 peer_dev->priv.eswitch,
976 spec, i);
977
ac004b83
RD		 978 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
979 spec, &flow_act, &dest, 1);
980 if (IS_ERR(flow)) {
981 err = PTR_ERR(flow);
81cd229c 982 goto add_vf_flow_err;
ac004b83
RD		 983 }
984 flows[i] = flow;
985 }
986
987 esw->fdb_table.offloads.peer_miss_rules = flows;
988
989 kvfree(spec);
990 return 0;
991
81cd229c 992add_vf_flow_err:
879c8f84 993 nvports = --i;
786ef904 994 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
ac004b83 995 mlx5_del_flow_rules(flows[i]);
81cd229c
BW		 996
997 if (mlx5_ecpf_vport_exists(esw->dev))
998 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
999add_ecpf_flow_err:
1000 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
1001 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
1002add_pf_flow_err:
1003 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1004 kvfree(flows);
1005alloc_flows_err:
1006 kvfree(spec);
1007 return err;
1008}
1009
1010static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1011{
1012 struct mlx5_flow_handle **flows;
1013 int i;
1014
1015 flows = esw->fdb_table.offloads.peer_miss_rules;
1016
786ef904
PP		 1017 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
1018 mlx5_core_max_vfs(esw->dev))
ac004b83
RD		 1019 mlx5_del_flow_rules(flows[i]);
1020
81cd229c
BW		 1021 if (mlx5_ecpf_vport_exists(esw->dev))
1022 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
1023
1024 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
1025 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
1026
ac004b83
RD		 1027 kvfree(flows);
1028}
1029
3aa33572
OG		 1030static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1031{
66958ed9 1032 struct mlx5_flow_act flow_act = {0};
4c5009c5 1033 struct mlx5_flow_destination dest = {};
74491de9 1034 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1035 struct mlx5_flow_spec *spec;
f80be543
MB		 1036 void *headers_c;
1037 void *headers_v;
3aa33572 1038 int err = 0;
f80be543
MB		 1039 u8 *dmac_c;
1040 u8 *dmac_v;
3aa33572 1041
1b9a07ee 1042 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1043 if (!spec) {
3aa33572
OG		 1044 err = -ENOMEM;
1045 goto out;
1046 }
1047
f80be543
MB		 1048 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1049 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1050 outer_headers);
1051 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1052 outer_headers.dmac_47_16);
1053 dmac_c[0] = 0x01;
1054
3aa33572 1055 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1056 dest.vport.num = esw->manager_vport;
66958ed9 1057 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1058
39ac237c
PB		 1059 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1060 spec, &flow_act, &dest, 1);
3aa33572
OG		 1061 if (IS_ERR(flow_rule)) {
1062 err = PTR_ERR(flow_rule);
f80be543 1063 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1064 goto out;
1065 }
1066
f80be543
MB		 1067 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1068
1069 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1070 outer_headers);
1071 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1072 outer_headers.dmac_47_16);
1073 dmac_v[0] = 0x01;
39ac237c
PB		 1074 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1075 spec, &flow_act, &dest, 1);
f80be543
MB		 1076 if (IS_ERR(flow_rule)) {
1077 err = PTR_ERR(flow_rule);
1078 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1079 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1080 goto out;
1081 }
1082
1083 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1084
3aa33572 1085out:
c5bb1730 1086 kvfree(spec);
3aa33572
OG		 1087 return err;
1088}
1089
11b717d6
PB		 1090struct mlx5_flow_handle *
1091esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1092{
1093 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1094 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1095 struct mlx5_flow_context *flow_context;
1096 struct mlx5_flow_handle *flow_rule;
1097 struct mlx5_flow_destination dest;
1098 struct mlx5_flow_spec *spec;
1099 void *misc;
1100
60acc105
PB		 1101 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1102 return ERR_PTR(-EOPNOTSUPP);
1103
11b717d6
PB		 1104 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1105 if (!spec)
1106 return ERR_PTR(-ENOMEM);
1107
1108 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1109 misc_parameters_2);
1110 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1111 ESW_CHAIN_TAG_METADATA_MASK);
1112 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1113 misc_parameters_2);
1114 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1115 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1116 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1117 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1118 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1119
1120 flow_context = &spec->flow_context;
1121 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1122 flow_context->flow_tag = tag;
1123 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1124 dest.ft = esw->offloads.ft_offloads;
1125
1126 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1127 kfree(spec);
1128
1129 if (IS_ERR(flow_rule))
1130 esw_warn(esw->dev,
1131 "Failed to create restore rule for tag: %d, err(%d)\n",
1132 tag, (int)PTR_ERR(flow_rule));
1133
1134 return flow_rule;
1135}
1136
1137u32
1138esw_get_max_restore_tag(struct mlx5_eswitch *esw)
1139{
1140 return ESW_CHAIN_TAG_METADATA_MASK;
1141}
1142
1967ce6e 1143#define MAX_PF_SQ 256
cd3d07e7 1144#define MAX_SQ_NVPORTS 32
1967ce6e 1145
a5641cb5
JL		 1146static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1147 u32 *flow_group_in)
1148{
1149 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1150 flow_group_in,
1151 match_criteria);
1152
1153 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1154 MLX5_SET(create_flow_group_in, flow_group_in,
1155 match_criteria_enable,
1156 MLX5_MATCH_MISC_PARAMETERS_2);
1157
0f0d3827
PB		 1158 MLX5_SET(fte_match_param, match_criteria,
1159 misc_parameters_2.metadata_reg_c_0,
1160 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1161 } else {
1162 MLX5_SET(create_flow_group_in, flow_group_in,
1163 match_criteria_enable,
1164 MLX5_MATCH_MISC_PARAMETERS);
1165
1166 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1167 misc_parameters.source_port);
1168 }
1169}
1170
ae430332
AL		 1171#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
1172#define fdb_modify_header_fwd_to_table_supported(esw) \
1173 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1174static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1175{
1176 struct mlx5_core_dev *dev = esw->dev;
1177
1178 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1179 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1180
1181 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1182 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1183 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1184 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1185 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1186 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1187 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1188 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1189 /* Disabled when ttl workaround is needed, e.g
1190 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1191 */
1192 esw_warn(dev,
1193 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1194 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1195 } else {
1196 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1197 esw_info(dev, "Supported tc chains and prios offload\n");
1198 }
1199
1200 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1201 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1202}
1203
1204static int
1205esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1206{
1207 struct mlx5_core_dev *dev = esw->dev;
1208 struct mlx5_flow_table *nf_ft, *ft;
1209 struct mlx5_chains_attr attr = {};
1210 struct mlx5_fs_chains *chains;
1211 u32 fdb_max;
1212 int err;
1213
1214 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1215
1216 esw_init_chains_offload_flags(esw, &attr.flags);
1217 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1218 attr.max_ft_sz = fdb_max;
1219 attr.max_grp_num = esw->params.large_group_num;
1220 attr.default_ft = miss_fdb;
1221 attr.max_restore_tag = esw_get_max_restore_tag(esw);
1222
1223 chains = mlx5_chains_create(dev, &attr);
1224 if (IS_ERR(chains)) {
1225 err = PTR_ERR(chains);
1226 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1227 return err;
1228 }
1229
1230 esw->fdb_table.offloads.esw_chains_priv = chains;
1231
1232 /* Create tc_end_ft which is the always created ft chain */
1233 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1234 1, 0);
1235 if (IS_ERR(nf_ft)) {
1236 err = PTR_ERR(nf_ft);
1237 goto nf_ft_err;
1238 }
1239
1240 /* Always open the root for fast path */
1241 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1242 if (IS_ERR(ft)) {
1243 err = PTR_ERR(ft);
1244 goto level_0_err;
1245 }
1246
1247 /* Open level 1 for split fdb rules now if prios isn't supported */
1248 if (!mlx5_chains_prios_supported(chains)) {
1249 err = mlx5_esw_vport_tbl_get(esw);
1250 if (err)
1251 goto level_1_err;
1252 }
1253
1254 mlx5_chains_set_end_ft(chains, nf_ft);
1255
1256 return 0;
1257
1258level_1_err:
1259 mlx5_chains_put_table(chains, 0, 1, 0);
1260level_0_err:
1261 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1262nf_ft_err:
1263 mlx5_chains_destroy(chains);
1264 esw->fdb_table.offloads.esw_chains_priv = NULL;
1265
1266 return err;
1267}
1268
1269static void
1270esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1271{
1272 if (!mlx5_chains_prios_supported(chains))
1273 mlx5_esw_vport_tbl_put(esw);
1274 mlx5_chains_put_table(chains, 0, 1, 0);
1275 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1276 mlx5_chains_destroy(chains);
1277}
1278
1279#else /* CONFIG_MLX5_CLS_ACT */
1280
1281static int
1282esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1283{ return 0; }
1284
1285static void
1286esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1287{}
1288
1289#endif
1290
0da3c12d 1291static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1292{
1293 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1294 struct mlx5_flow_table_attr ft_attr = {};
1295 struct mlx5_core_dev *dev = esw->dev;
1296 struct mlx5_flow_namespace *root_ns;
1297 struct mlx5_flow_table *fdb = NULL;
39ac237c
PB		 1298 u32 flags = 0, *flow_group_in;
1299 int table_size, ix, err = 0;
1967ce6e
OG		 1300 struct mlx5_flow_group *g;
1301 void *match_criteria;
f80be543 1302 u8 *dmac;
1967ce6e
OG		 1303
1304 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1305
1b9a07ee 1306 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1307 if (!flow_group_in)
1308 return -ENOMEM;
1309
1310 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1311 if (!root_ns) {
1312 esw_warn(dev, "Failed to get FDB flow namespace\n");
1313 err = -EOPNOTSUPP;
1314 goto ns_err;
1315 }
8463daf1
MG		 1316 esw->fdb_table.offloads.ns = root_ns;
1317 err = mlx5_flow_namespace_set_mode(root_ns,
1318 esw->dev->priv.steering->mode);
1319 if (err) {
1320 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1321 goto ns_err;
1322 }
1967ce6e 1323
0da3c12d 1324 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
cd7e4186 1325 MLX5_ESW_MISS_FLOWS + esw->total_vports;
b3ba5149 1326
e52c2802
PB		 1327 /* create the slow path fdb with encap set, so further table instances
1328 * can be created at run time while VFs are probed if the FW allows that.
1329 */
1330 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1331 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1332 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1333
1334 ft_attr.flags = flags;
b3ba5149
ES		 1335 ft_attr.max_fte = table_size;
1336 ft_attr.prio = FDB_SLOW_PATH;
1337
1338 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1339 if (IS_ERR(fdb)) {
1340 err = PTR_ERR(fdb);
1341 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1342 goto slow_fdb_err;
1343 }
52fff327 1344 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1345
ae430332 1346 err = esw_chains_create(esw, fdb);
39ac237c 1347 if (err) {
ae430332 1348 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1349 goto fdb_chains_err;
e52c2802
PB		 1350 }
1351
69697b6e 1352 /* create send-to-vport group */
69697b6e
OG		 1353 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1354 MLX5_MATCH_MISC_PARAMETERS);
1355
1356 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1357
1358 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1359 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1360
0da3c12d 1361 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1362 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1363 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1364
1365 g = mlx5_create_flow_group(fdb, flow_group_in);
1366 if (IS_ERR(g)) {
1367 err = PTR_ERR(g);
1368 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1369 goto send_vport_err;
1370 }
1371 esw->fdb_table.offloads.send_to_vport_grp = g;
1372
6cec0229
MD		 1373 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1374 /* create peer esw miss group */
1375 memset(flow_group_in, 0, inlen);
ac004b83 1376
6cec0229 1377 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1378
6cec0229
MD		 1379 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1380 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1381 flow_group_in,
1382 match_criteria);
ac004b83 1383
6cec0229
MD		 1384 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1385 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1386
6cec0229
MD		 1387 MLX5_SET(create_flow_group_in, flow_group_in,
1388 source_eswitch_owner_vhca_id_valid, 1);
1389 }
ac004b83 1390
6cec0229
MD		 1391 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1392 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1393 ix + esw->total_vports - 1);
1394 ix += esw->total_vports;
ac004b83 1395
6cec0229
MD		 1396 g = mlx5_create_flow_group(fdb, flow_group_in);
1397 if (IS_ERR(g)) {
1398 err = PTR_ERR(g);
1399 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1400 goto peer_miss_err;
1401 }
1402 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1403 }
ac004b83 1404
69697b6e
OG		 1405 /* create miss group */
1406 memset(flow_group_in, 0, inlen);
f80be543
MB		 1407 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1408 MLX5_MATCH_OUTER_HEADERS);
1409 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1410 match_criteria);
1411 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1412 outer_headers.dmac_47_16);
1413 dmac[0] = 0x01;
69697b6e
OG		 1414
1415 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1416 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1417 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1418
1419 g = mlx5_create_flow_group(fdb, flow_group_in);
1420 if (IS_ERR(g)) {
1421 err = PTR_ERR(g);
1422 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1423 goto miss_err;
1424 }
1425 esw->fdb_table.offloads.miss_grp = g;
1426
3aa33572
OG		 1427 err = esw_add_fdb_miss_rule(esw);
1428 if (err)
1429 goto miss_rule_err;
1430
c88a026e 1431 kvfree(flow_group_in);
69697b6e
OG		 1432 return 0;
1433
3aa33572
OG		 1434miss_rule_err:
1435 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1436miss_err:
6cec0229
MD		 1437 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1438 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1439peer_miss_err:
69697b6e
OG		 1440 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1441send_vport_err:
ae430332 1442 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1443fdb_chains_err:
52fff327 1444 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1445slow_fdb_err:
8463daf1
MG		 1446 /* Holds true only as long as DMFS is the default */
1447 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1448ns_err:
1449 kvfree(flow_group_in);
1450 return err;
1451}
1452
1967ce6e 1453static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1454{
e52c2802 1455 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1456 return;
1457
1967ce6e 1458 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1459 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1460 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1461 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
6cec0229
MD		 1462 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1463 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1464 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1465
ae430332
AL		 1466 esw_chains_destroy(esw, esw_chains(esw));
1467
52fff327 1468 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1469 /* Holds true only as long as DMFS is the default */
1470 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1471 MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e 1472}
c116c6ee 1473
8d6bd3c3 1474static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1475{
b3ba5149 1476 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1477 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1478 struct mlx5_flow_table *ft_offloads;
1479 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1480 int err = 0;
1481
1482 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1483 if (!ns) {
1484 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1485 return -EOPNOTSUPP;
c116c6ee
OG		 1486 }
1487
8d6bd3c3 1488 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1489 ft_attr.prio = 1;
b3ba5149
ES		 1490
1491 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1492 if (IS_ERR(ft_offloads)) {
1493 err = PTR_ERR(ft_offloads);
1494 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1495 return err;
1496 }
1497
1498 esw->offloads.ft_offloads = ft_offloads;
1499 return 0;
1500}
1501
1502static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1503{
1504 struct mlx5_esw_offload *offloads = &esw->offloads;
1505
1506 mlx5_destroy_flow_table(offloads->ft_offloads);
1507}
fed9ce22 1508
8d6bd3c3 1509static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1510{
1511 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1512 struct mlx5_flow_group *g;
fed9ce22 1513 u32 *flow_group_in;
8d6bd3c3 1514 int nvports;
fed9ce22 1515 int err = 0;
fed9ce22 1516
8d6bd3c3 1517 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1518 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1519 if (!flow_group_in)
1520 return -ENOMEM;
1521
1522 /* create vport rx group */
a5641cb5 1523 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1524
1525 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1526 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1527
1528 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1529
1530 if (IS_ERR(g)) {
1531 err = PTR_ERR(g);
1532 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1533 goto out;
1534 }
1535
1536 esw->offloads.vport_rx_group = g;
1537out:
e574978a 1538 kvfree(flow_group_in);
fed9ce22
OG		 1539 return err;
1540}
1541
1542static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1543{
1544 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1545}
1546
74491de9 1547struct mlx5_flow_handle *
02f3afd9 1548mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1549 struct mlx5_flow_destination *dest)
fed9ce22 1550{
66958ed9 1551 struct mlx5_flow_act flow_act = {0};
74491de9 1552 struct mlx5_flow_handle *flow_rule;
c5bb1730 1553 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1554 void *misc;
1555
1b9a07ee 1556 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1557 if (!spec) {
fed9ce22
OG		 1558 flow_rule = ERR_PTR(-ENOMEM);
1559 goto out;
1560 }
1561
a5641cb5
JL		 1562 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1563 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1564 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1565 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1566
a5641cb5 1567 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1568 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1569 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1570
a5641cb5
JL		 1571 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1572 } else {
1573 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1574 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1575
1576 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1577 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1578
1579 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1580 }
fed9ce22 1581
66958ed9 1582 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1583 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1584 &flow_act, dest, 1);
fed9ce22
OG		 1585 if (IS_ERR(flow_rule)) {
1586 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1587 goto out;
1588 }
1589
1590out:
c5bb1730 1591 kvfree(spec);
fed9ce22
OG		 1592 return flow_rule;
1593}
feae9087 1594
bf3347c4 1595
cc617ced
PP		 1596static int mlx5_eswitch_inline_mode_get(const struct mlx5_eswitch *esw, u8 *mode)
1597{
1598 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1599 struct mlx5_core_dev *dev = esw->dev;
1600 int vport;
1601
1602 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1603 return -EOPNOTSUPP;
1604
1605 if (esw->mode == MLX5_ESWITCH_NONE)
1606 return -EOPNOTSUPP;
1607
1608 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1609 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1610 mlx5_mode = MLX5_INLINE_MODE_NONE;
1611 goto out;
1612 case MLX5_CAP_INLINE_MODE_L2:
1613 mlx5_mode = MLX5_INLINE_MODE_L2;
1614 goto out;
1615 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1616 goto query_vports;
1617 }
1618
1619query_vports:
1620 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
1621 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
1622 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
1623 if (prev_mlx5_mode != mlx5_mode)
1624 return -EINVAL;
1625 prev_mlx5_mode = mlx5_mode;
1626 }
1627
1628out:
1629 *mode = mlx5_mode;
1630 return 0;
e08a6832 1631}
bf3347c4 1632
11b717d6
PB		 1633static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1634{
1635 struct mlx5_esw_offload *offloads = &esw->offloads;
1636
60acc105
PB		 1637 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1638 return;
1639
6724e66b 1640 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 1641 mlx5_destroy_flow_group(offloads->restore_group);
1642 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
1643}
1644
1645static int esw_create_restore_table(struct mlx5_eswitch *esw)
1646{
d65dbedf 1647 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 1648 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1649 struct mlx5_flow_table_attr ft_attr = {};
1650 struct mlx5_core_dev *dev = esw->dev;
1651 struct mlx5_flow_namespace *ns;
6724e66b 1652 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 1653 void *match_criteria, *misc;
1654 struct mlx5_flow_table *ft;
1655 struct mlx5_flow_group *g;
1656 u32 *flow_group_in;
1657 int err = 0;
1658
60acc105
PB		 1659 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1660 return 0;
1661
11b717d6
PB		 1662 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1663 if (!ns) {
1664 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1665 return -EOPNOTSUPP;
1666 }
1667
1668 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1669 if (!flow_group_in) {
1670 err = -ENOMEM;
1671 goto out_free;
1672 }
1673
1674 ft_attr.max_fte = 1 << ESW_CHAIN_TAG_METADATA_BITS;
1675 ft = mlx5_create_flow_table(ns, &ft_attr);
1676 if (IS_ERR(ft)) {
1677 err = PTR_ERR(ft);
1678 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
1679 err);
1680 goto out_free;
1681 }
1682
11b717d6
PB		 1683 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1684 match_criteria);
1685 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
1686 misc_parameters_2);
1687
1688 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1689 ESW_CHAIN_TAG_METADATA_MASK);
1690 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1691 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1692 ft_attr.max_fte - 1);
1693 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1694 MLX5_MATCH_MISC_PARAMETERS_2);
1695 g = mlx5_create_flow_group(ft, flow_group_in);
1696 if (IS_ERR(g)) {
1697 err = PTR_ERR(g);
1698 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
1699 err);
1700 goto err_group;
1701 }
1702
6724e66b
PB		 1703 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
1704 MLX5_SET(copy_action_in, modact, src_field,
1705 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
1706 MLX5_SET(copy_action_in, modact, dst_field,
1707 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
1708 mod_hdr = mlx5_modify_header_alloc(esw->dev,
1709 MLX5_FLOW_NAMESPACE_KERNEL, 1,
1710 modact);
1711 if (IS_ERR(mod_hdr)) {
e9864539 1712 err = PTR_ERR(mod_hdr);
6724e66b
PB		 1713 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
1714 err);
6724e66b
PB		 1715 goto err_mod_hdr;
1716 }
1717
11b717d6
PB		 1718 esw->offloads.ft_offloads_restore = ft;
1719 esw->offloads.restore_group = g;
6724e66b 1720 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 1721
c8508713
RD		 1722 kvfree(flow_group_in);
1723
11b717d6
PB		 1724 return 0;
1725
6724e66b
PB		 1726err_mod_hdr:
1727 mlx5_destroy_flow_group(g);
11b717d6
PB		 1728err_group:
1729 mlx5_destroy_flow_table(ft);
1730out_free:
1731 kvfree(flow_group_in);
1732
1733 return err;
cc617ced
PP		 1734}
1735
db7ff19e
EB		 1736static int esw_offloads_start(struct mlx5_eswitch *esw,
1737 struct netlink_ext_ack *extack)
c930a3ad 1738{
062f4bf4 1739 int err, err1;
c930a3ad 1740
8e0aa4bc
PP		 1741 mlx5_eswitch_disable_locked(esw, false);
1742 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
1743 esw->dev->priv.sriov.num_vfs);
6c419ba8 1744 if (err) {
8c98ee77
EB		 1745 NL_SET_ERR_MSG_MOD(extack,
1746 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 1747 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
1748 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 1749 if (err1) {
1750 NL_SET_ERR_MSG_MOD(extack,
1751 "Failed setting eswitch back to legacy");
1752 }
6c419ba8 1753 }
bffaa916
RD		 1754 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1755 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 1756 &esw->offloads.inline_mode)) {
1757 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 1758 NL_SET_ERR_MSG_MOD(extack,
1759 "Inline mode is different between vports");
bffaa916
RD		 1760 }
1761 }
c930a3ad
OG		 1762 return err;
1763}
1764
e8d31c4d
MB		 1765void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1766{
1767 kfree(esw->offloads.vport_reps);
1768}
1769
1770int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1771{
2752b823 1772 int total_vports = esw->total_vports;
e8d31c4d 1773 struct mlx5_eswitch_rep *rep;
d6518db2 1774 int vport_index;
ef2e4094 1775 u8 rep_type;
e8d31c4d 1776
2aca1787 1777 esw->offloads.vport_reps = kcalloc(total_vports,
e8d31c4d
MB		 1778 sizeof(struct mlx5_eswitch_rep),
1779 GFP_KERNEL);
1780 if (!esw->offloads.vport_reps)
1781 return -ENOMEM;
1782
d6518db2
BW		 1783 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1784 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
2f69e591 1785 rep->vport_index = vport_index;
f121e0ea
BW		 1786
1787 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
8693115a 1788 atomic_set(&rep->rep_data[rep_type].state,
6f4e0219 1789 REP_UNREGISTERED);
e8d31c4d
MB		 1790 }
1791
e8d31c4d
MB		 1792 return 0;
1793}
1794
c9b99abc
BW		 1795static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1796 struct mlx5_eswitch_rep *rep, u8 rep_type)
1797{
8693115a 1798 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 1799 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 1800 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 1801}
1802
d7f33a45
VP		 1803static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
1804{
1805 struct mlx5_eswitch_rep *rep;
1806 int i;
1807
1808 mlx5_esw_for_each_sf_rep(esw, i, rep)
1809 __esw_offloads_unload_rep(esw, rep, rep_type);
1810}
1811
4110fc59 1812static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 1813{
1814 struct mlx5_eswitch_rep *rep;
4110fc59
BW		 1815 int i;
1816
d7f33a45
VP		 1817 __unload_reps_sf_vport(esw, rep_type);
1818
4110fc59
BW		 1819 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, esw->esw_funcs.num_vfs)
1820 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 1821
81cd229c
BW		 1822 if (mlx5_ecpf_vport_exists(esw->dev)) {
1823 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1824 __esw_offloads_unload_rep(esw, rep, rep_type);
1825 }
1826
1827 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1828 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1829 __esw_offloads_unload_rep(esw, rep, rep_type);
1830 }
1831
879c8f84 1832 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 1833 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1834}
1835
38679b5a 1836static int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 1837{
c2d7712c
BW		 1838 struct mlx5_eswitch_rep *rep;
1839 int rep_type;
a4b97ab4
MB		 1840 int err;
1841
c2d7712c
BW		 1842 rep = mlx5_eswitch_get_rep(esw, vport_num);
1843 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1844 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1845 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1846 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1847 if (err)
1848 goto err_reps;
1849 }
1850
1851 return 0;
a4b97ab4
MB		 1852
1853err_reps:
c2d7712c
BW		 1854 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
1855 for (--rep_type; rep_type >= 0; rep_type--)
1856 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1857 return err;
1858}
1859
38679b5a 1860static void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 1861{
1862 struct mlx5_eswitch_rep *rep;
1863 int rep_type;
1864
c2d7712c
BW		 1865 rep = mlx5_eswitch_get_rep(esw, vport_num);
1866 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
1867 __esw_offloads_unload_rep(esw, rep, rep_type);
1868}
1869
38679b5a
PP		 1870int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
1871{
1872 int err;
1873
1874 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1875 return 0;
1876
c7eddc60
PP		 1877 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
1878 if (err)
1879 return err;
1880
38679b5a 1881 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 1882 if (err)
1883 goto load_err;
1884 return err;
1885
1886load_err:
1887 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 1888 return err;
1889}
1890
1891void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
1892{
1893 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1894 return;
1895
1896 mlx5_esw_offloads_rep_unload(esw, vport_num);
c7eddc60 1897 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 1898}
1899
ac004b83
RD		 1900#define ESW_OFFLOADS_DEVCOM_PAIR (0)
1901#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1902
1903static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1904 struct mlx5_eswitch *peer_esw)
1905{
1906 int err;
1907
1908 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1909 if (err)
1910 return err;
1911
1912 return 0;
1913}
1914
1915static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1916{
d956873f 1917#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 1918 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 1919#endif
ac004b83
RD		 1920 esw_del_fdb_peer_miss_rules(esw);
1921}
1922
8463daf1
MG		 1923static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
1924 struct mlx5_eswitch *peer_esw,
1925 bool pair)
1926{
1927 struct mlx5_flow_root_namespace *peer_ns;
1928 struct mlx5_flow_root_namespace *ns;
1929 int err;
1930
1931 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
1932 ns = esw->dev->priv.steering->fdb_root_ns;
1933
1934 if (pair) {
1935 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
1936 if (err)
1937 return err;
1938
e53e6655 1939 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 1940 if (err) {
1941 mlx5_flow_namespace_set_peer(ns, NULL);
1942 return err;
1943 }
1944 } else {
1945 mlx5_flow_namespace_set_peer(ns, NULL);
1946 mlx5_flow_namespace_set_peer(peer_ns, NULL);
1947 }
1948
1949 return 0;
1950}
1951
ac004b83
RD		 1952static int mlx5_esw_offloads_devcom_event(int event,
1953 void *my_data,
1954 void *event_data)
1955{
1956 struct mlx5_eswitch *esw = my_data;
ac004b83 1957 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 1958 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 1959 int err;
1960
1961 switch (event) {
1962 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 1963 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1964 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1965 break;
1966
8463daf1 1967 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 1968 if (err)
1969 goto err_out;
8463daf1
MG		 1970 err = mlx5_esw_offloads_pair(esw, peer_esw);
1971 if (err)
1972 goto err_peer;
ac004b83
RD		 1973
1974 err = mlx5_esw_offloads_pair(peer_esw, esw);
1975 if (err)
1976 goto err_pair;
1977
1978 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1979 break;
1980
1981 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1982 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1983 break;
1984
1985 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1986 mlx5_esw_offloads_unpair(peer_esw);
1987 mlx5_esw_offloads_unpair(esw);
8463daf1 1988 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1989 break;
1990 }
1991
1992 return 0;
1993
1994err_pair:
1995 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 1996err_peer:
1997 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1998err_out:
1999 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2000 event, err);
2001 return err;
2002}
2003
2004static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2005{
2006 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2007
04de7dda
RD		 2008 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2009 mutex_init(&esw->offloads.peer_mutex);
2010
ac004b83
RD		 2011 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2012 return;
2013
2014 mlx5_devcom_register_component(devcom,
2015 MLX5_DEVCOM_ESW_OFFLOADS,
2016 mlx5_esw_offloads_devcom_event,
2017 esw);
2018
2019 mlx5_devcom_send_event(devcom,
2020 MLX5_DEVCOM_ESW_OFFLOADS,
2021 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2022}
2023
2024static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2025{
2026 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2027
2028 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2029 return;
2030
2031 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2032 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2033
2034 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2035}
2036
92ab1eb3
JL		 2037static bool
2038esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
2039{
2040 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2041 return false;
2042
2043 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2044 MLX5_FDB_TO_VPORT_REG_C_0))
2045 return false;
2046
2047 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2048 return false;
2049
2050 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2051 mlx5_ecpf_vport_exists(esw->dev))
2052 return false;
2053
2054 return true;
2055}
2056
133dcfc5
VP		 2057u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2058{
7cd7becd 2059 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2060 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2061 u32 pf_num;
133dcfc5
VP		 2062 int id;
2063
7cd7becd 2064 /* Only 4 bits of pf_num */
2065 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2066 if (pf_num > max_pf_num)
2067 return 0;
133dcfc5 2068
7cd7becd 2069 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2070 /* Use only non-zero vport_id (1-4095) for all PF's */
2071 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2072 if (id < 0)
2073 return 0;
2074 id = (pf_num << ESW_VPORT_BITS) | id;
2075 return id;
133dcfc5
VP		 2076}
2077
2078void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2079{
7cd7becd 2080 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2081
2082 /* Metadata contains only 12 bits of actual ida id */
2083 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2084}
2085
2086static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2087 struct mlx5_vport *vport)
2088{
133dcfc5
VP		 2089 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2090 vport->metadata = vport->default_metadata;
2091 return vport->metadata ? 0 : -ENOSPC;
2092}
2093
2094static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2095 struct mlx5_vport *vport)
2096{
406493a5 2097 if (!vport->default_metadata)
133dcfc5
VP		 2098 return;
2099
2100 WARN_ON(vport->metadata != vport->default_metadata);
2101 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2102}
2103
fc99c3d6
VP		 2104static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2105{
2106 struct mlx5_vport *vport;
2107 int i;
2108
2109 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2110 return;
2111
2112 mlx5_esw_for_all_vports_reverse(esw, i, vport)
2113 esw_offloads_vport_metadata_cleanup(esw, vport);
2114}
2115
2116static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2117{
2118 struct mlx5_vport *vport;
2119 int err;
2120 int i;
2121
2122 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2123 return 0;
2124
2125 mlx5_esw_for_all_vports(esw, i, vport) {
2126 err = esw_offloads_vport_metadata_setup(esw, vport);
2127 if (err)
2128 goto metadata_err;
2129 }
2130
2131 return 0;
2132
2133metadata_err:
2134 esw_offloads_metadata_uninit(esw);
2135 return err;
2136}
2137
748da30b 2138int
89a0f1fb
PP		 2139esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2140 struct mlx5_vport *vport)
7445cfb1 2141{
7445cfb1
JL		 2142 int err;
2143
07bab950 2144 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2145 if (err)
fc99c3d6 2146 return err;
7445cfb1 2147
2c40db2f
PP		 2148 err = esw_acl_egress_ofld_setup(esw, vport);
2149 if (err)
2150 goto egress_err;
07bab950
VP		 2151
2152 return 0;
2153
2154egress_err:
2155 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2156 return err;
2157}
18486737 2158
748da30b 2159void
89a0f1fb
PP		 2160esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2161 struct mlx5_vport *vport)
2162{
ea651a86 2163 esw_acl_egress_ofld_cleanup(vport);
07bab950 2164 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2165}
7445cfb1 2166
748da30b 2167static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2168{
2169 struct mlx5_vport *vport;
18486737 2170
748da30b 2171 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
4e9a9ef7 2172 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2173}
2174
748da30b 2175static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2176{
786ef904 2177 struct mlx5_vport *vport;
7445cfb1 2178
748da30b
VP		 2179 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2180 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2181}
2182
062f4bf4 2183static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a
MB		 2184{
2185 int err;
2186
5c1d260e 2187 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2188 mutex_init(&esw->fdb_table.offloads.vports.lock);
2189 hash_init(esw->fdb_table.offloads.vports.table);
e52c2802 2190
748da30b 2191 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2192 if (err)
f8d1edda 2193 goto create_acl_err;
18486737 2194
8d6bd3c3 2195 err = esw_create_offloads_table(esw);
c930a3ad 2196 if (err)
11b717d6 2197 goto create_offloads_err;
c930a3ad 2198
11b717d6 2199 err = esw_create_restore_table(esw);
c930a3ad 2200 if (err)
11b717d6
PB		 2201 goto create_restore_err;
2202
0da3c12d 2203 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2204 if (err)
2205 goto create_fdb_err;
c930a3ad 2206
8d6bd3c3 2207 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2208 if (err)
2209 goto create_fg_err;
2210
2211 return 0;
2212
2213create_fg_err:
1967ce6e 2214 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2215create_fdb_err:
11b717d6
PB		 2216 esw_destroy_restore_table(esw);
2217create_restore_err:
2218 esw_destroy_offloads_table(esw);
2219create_offloads_err:
748da30b 2220 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda
PP		 2221create_acl_err:
2222 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2223 return err;
2224}
2225
eca8cc38
BW		 2226static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2227{
2228 esw_destroy_vport_rx_group(esw);
eca8cc38 2229 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2230 esw_destroy_restore_table(esw);
2231 esw_destroy_offloads_table(esw);
748da30b 2232 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2233 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2234}
2235
7e736f9a
PP		 2236static void
2237esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2238{
5ccf2770 2239 bool host_pf_disabled;
7e736f9a 2240 u16 new_num_vfs;
a3888f33 2241
7e736f9a
PP		 2242 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2243 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2244 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2245 host_params_context.host_pf_disabled);
a3888f33 2246
7e736f9a
PP		 2247 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2248 return;
a3888f33
BW		 2249
2250 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2251 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2252 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2253 } else {
7e736f9a 2254 int err;
a3888f33 2255
23bb50cf
BW		 2256 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2257 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2258 if (err)
7e736f9a 2259 return;
a3888f33 2260 }
7e736f9a 2261 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2262}
2263
7e736f9a 2264static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2265{
7e736f9a
PP		 2266 struct mlx5_host_work *host_work;
2267 struct mlx5_eswitch *esw;
dd28087c 2268 const u32 *out;
ac35dcd6 2269
7e736f9a
PP		 2270 host_work = container_of(work, struct mlx5_host_work, work);
2271 esw = host_work->esw;
a3888f33 2272
dd28087c
PP		 2273 out = mlx5_esw_query_functions(esw->dev);
2274 if (IS_ERR(out))
7e736f9a 2275 goto out;
a3888f33 2276
7e736f9a 2277 esw_vfs_changed_event_handler(esw, out);
dd28087c 2278 kvfree(out);
a3888f33 2279out:
ac35dcd6
VP		 2280 kfree(host_work);
2281}
2282
16fff98a 2283int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2284{
cd56f929 2285 struct mlx5_esw_functions *esw_funcs;
a3888f33 2286 struct mlx5_host_work *host_work;
a3888f33
BW		 2287 struct mlx5_eswitch *esw;
2288
2289 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2290 if (!host_work)
2291 return NOTIFY_DONE;
2292
cd56f929
VP		 2293 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2294 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2295
2296 host_work->esw = esw;
2297
062f4bf4 2298 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2299 queue_work(esw->work_queue, &host_work->work);
2300
2301 return NOTIFY_OK;
2302}
2303
a53cf949
PP		 2304static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2305{
2306 const u32 *query_host_out;
2307
2308 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2309 return 0;
2310
2311 query_host_out = mlx5_esw_query_functions(esw->dev);
2312 if (IS_ERR(query_host_out))
2313 return PTR_ERR(query_host_out);
2314
2315 /* Mark non local controller with non zero controller number. */
2316 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2317 host_params_context.host_number);
2318 kvfree(query_host_out);
2319 return 0;
2320}
2321
5896b972 2322int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2323{
3b83b6c2
DL		 2324 struct mlx5_vport *vport;
2325 int err, i;
eca8cc38 2326
9a64144d
MG		 2327 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2328 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2329 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2330 else
2331 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2332
2bb72e7e 2333 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2334 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2335
a53cf949
PP		 2336 err = mlx5_esw_host_number_init(esw);
2337 if (err)
cd1ef966 2338 goto err_metadata;
a53cf949 2339
cd1ef966 2340 if (esw_check_vport_match_metadata_supported(esw))
4e9a9ef7
VP		 2341 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2342
fc99c3d6
VP		 2343 err = esw_offloads_metadata_init(esw);
2344 if (err)
2345 goto err_metadata;
2346
332bd3a5
PP		 2347 err = esw_set_passing_vport_metadata(esw, true);
2348 if (err)
2349 goto err_vport_metadata;
c1286050 2350
7983a675
PB		 2351 err = esw_offloads_steering_init(esw);
2352 if (err)
2353 goto err_steering_init;
2354
3b83b6c2
DL		 2355 /* Representor will control the vport link state */
2356 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2357 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2358
c2d7712c
BW		 2359 /* Uplink vport rep must load first. */
2360 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2361 if (err)
c2d7712c 2362 goto err_uplink;
c1286050 2363
c2d7712c 2364 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2365 if (err)
c2d7712c 2366 goto err_vports;
eca8cc38
BW		 2367
2368 esw_offloads_devcom_init(esw);
a3888f33 2369
eca8cc38
BW		 2370 return 0;
2371
925a6acc 2372err_vports:
c2d7712c
BW		 2373 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2374err_uplink:
7983a675 2375 esw_offloads_steering_cleanup(esw);
79949985
PP		 2376err_steering_init:
2377 esw_set_passing_vport_metadata(esw, false);
7983a675 2378err_vport_metadata:
fc99c3d6
VP		 2379 esw_offloads_metadata_uninit(esw);
2380err_metadata:
4e9a9ef7 2381 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2382 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2383 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2384 return err;
2385}
2386
db7ff19e
EB		 2387static int esw_offloads_stop(struct mlx5_eswitch *esw,
2388 struct netlink_ext_ack *extack)
c930a3ad 2389{
062f4bf4 2390 int err, err1;
c930a3ad 2391
8e0aa4bc
PP		 2392 mlx5_eswitch_disable_locked(esw, false);
2393 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2394 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2395 if (err) {
8c98ee77 2396 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2397 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2398 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2399 if (err1) {
2400 NL_SET_ERR_MSG_MOD(extack,
2401 "Failed setting eswitch back to offloads");
2402 }
6c419ba8 2403 }
c930a3ad
OG		 2404
2405 return err;
2406}
2407
5896b972 2408void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2409{
ac004b83 2410 esw_offloads_devcom_cleanup(esw);
5896b972 2411 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2412 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2413 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2414 esw_offloads_steering_cleanup(esw);
fc99c3d6 2415 esw_offloads_metadata_uninit(esw);
4e9a9ef7 2416 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
8463daf1 2417 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2418 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2419 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2420}
2421
ef78618b 2422static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2423{
2424 switch (mode) {
2425 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2426 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2427 break;
2428 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2429 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2430 break;
2431 default:
2432 return -EINVAL;
2433 }
2434
2435 return 0;
2436}
2437
ef78618b
OG		 2438static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2439{
2440 switch (mlx5_mode) {
f6455de0 2441 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2442 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2443 break;
f6455de0 2444 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2445 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2446 break;
2447 default:
2448 return -EINVAL;
2449 }
2450
2451 return 0;
2452}
2453
bffaa916
RD		 2454static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2455{
2456 switch (mode) {
2457 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2458 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2459 break;
2460 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2461 *mlx5_mode = MLX5_INLINE_MODE_L2;
2462 break;
2463 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2464 *mlx5_mode = MLX5_INLINE_MODE_IP;
2465 break;
2466 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2467 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2468 break;
2469 default:
2470 return -EINVAL;
2471 }
2472
2473 return 0;
2474}
2475
2476static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2477{
2478 switch (mlx5_mode) {
2479 case MLX5_INLINE_MODE_NONE:
2480 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2481 break;
2482 case MLX5_INLINE_MODE_L2:
2483 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2484 break;
2485 case MLX5_INLINE_MODE_IP:
2486 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2487 break;
2488 case MLX5_INLINE_MODE_TCP_UDP:
2489 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2490 break;
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 return 0;
2496}
2497
ae24432c
PP		 2498static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2499{
2500 /* devlink commands in NONE eswitch mode are currently supported only
2501 * on ECPF.
2502 */
2503 return (esw->mode == MLX5_ESWITCH_NONE &&
2504 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2505}
2506
db7ff19e
EB		 2507int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2508 struct netlink_ext_ack *extack)
9d1cef19 2509{
9d1cef19 2510 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2511 struct mlx5_eswitch *esw;
ea2128fd 2512 int err = 0;
9d1cef19 2513
bd939753
PP		 2514 esw = mlx5_devlink_eswitch_get(devlink);
2515 if (IS_ERR(esw))
2516 return PTR_ERR(esw);
9d1cef19 2517
ef78618b 2518 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2519 return -EINVAL;
2520
8e0aa4bc 2521 mutex_lock(&esw->mode_lock);
8e0aa4bc 2522 cur_mlx5_mode = esw->mode;
c930a3ad 2523 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 2524 goto unlock;
c930a3ad
OG		 2525
2526 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 2527 err = esw_offloads_start(esw, extack);
c930a3ad 2528 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 2529 err = esw_offloads_stop(esw, extack);
c930a3ad 2530 else
8e0aa4bc
PP		 2531 err = -EINVAL;
2532
2533unlock:
2534 mutex_unlock(&esw->mode_lock);
2535 return err;
feae9087
OG		 2536}
2537
2538int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2539{
bd939753 2540 struct mlx5_eswitch *esw;
9d1cef19 2541 int err;
c930a3ad 2542
bd939753
PP		 2543 esw = mlx5_devlink_eswitch_get(devlink);
2544 if (IS_ERR(esw))
2545 return PTR_ERR(esw);
c930a3ad 2546
8e0aa4bc 2547 mutex_lock(&esw->mode_lock);
bd939753 2548 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 2549 if (err)
8e0aa4bc 2550 goto unlock;
ae24432c 2551
8e0aa4bc
PP		 2552 err = esw_mode_to_devlink(esw->mode, mode);
2553unlock:
2554 mutex_unlock(&esw->mode_lock);
2555 return err;
feae9087 2556}
127ea380 2557
db7ff19e
EB		 2558int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2559 struct netlink_ext_ack *extack)
bffaa916
RD		 2560{
2561 struct mlx5_core_dev *dev = devlink_priv(devlink);
db68cc56 2562 int err, vport, num_vport;
bd939753 2563 struct mlx5_eswitch *esw;
bffaa916
RD		 2564 u8 mlx5_mode;
2565
bd939753
PP		 2566 esw = mlx5_devlink_eswitch_get(devlink);
2567 if (IS_ERR(esw))
2568 return PTR_ERR(esw);
bffaa916 2569
8e0aa4bc 2570 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2571 err = eswitch_devlink_esw_mode_check(esw);
2572 if (err)
8e0aa4bc 2573 goto out;
ae24432c 2574
c415f704
OG		 2575 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2576 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2577 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 2578 goto out;
c8b838d1 2579 fallthrough;
c415f704 2580 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 2581 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 2582 err = -EOPNOTSUPP;
2583 goto out;
c415f704
OG		 2584 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2585 break;
2586 }
bffaa916 2587
525e84be 2588 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2589 NL_SET_ERR_MSG_MOD(extack,
2590 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 2591 err = -EOPNOTSUPP;
2592 goto out;
375f51e2
RD		 2593 }
2594
bffaa916
RD		 2595 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2596 if (err)
2597 goto out;
2598
411ec9e0 2599 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
bffaa916
RD		 2600 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2601 if (err) {
8c98ee77
EB		 2602 NL_SET_ERR_MSG_MOD(extack,
2603 "Failed to set min inline on vport");
bffaa916
RD		 2604 goto revert_inline_mode;
2605 }
2606 }
2607
2608 esw->offloads.inline_mode = mlx5_mode;
8e0aa4bc 2609 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2610 return 0;
2611
2612revert_inline_mode:
db68cc56 2613 num_vport = --vport;
411ec9e0 2614 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
bffaa916
RD		 2615 mlx5_modify_nic_vport_min_inline(dev,
2616 vport,
2617 esw->offloads.inline_mode);
2618out:
8e0aa4bc 2619 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2620 return err;
2621}
2622
2623int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2624{
bd939753 2625 struct mlx5_eswitch *esw;
9d1cef19 2626 int err;
bffaa916 2627
bd939753
PP		 2628 esw = mlx5_devlink_eswitch_get(devlink);
2629 if (IS_ERR(esw))
2630 return PTR_ERR(esw);
bffaa916 2631
8e0aa4bc 2632 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2633 err = eswitch_devlink_esw_mode_check(esw);
2634 if (err)
8e0aa4bc 2635 goto unlock;
ae24432c 2636
8e0aa4bc
PP		 2637 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2638unlock:
2639 mutex_unlock(&esw->mode_lock);
2640 return err;
bffaa916
RD		 2641}
2642
98fdbea5
LR		 2643int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2644 enum devlink_eswitch_encap_mode encap,
db7ff19e 2645 struct netlink_ext_ack *extack)
7768d197
RD		 2646{
2647 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 2648 struct mlx5_eswitch *esw;
7768d197
RD		 2649 int err;
2650
bd939753
PP		 2651 esw = mlx5_devlink_eswitch_get(devlink);
2652 if (IS_ERR(esw))
2653 return PTR_ERR(esw);
7768d197 2654
8e0aa4bc 2655 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2656 err = eswitch_devlink_esw_mode_check(esw);
2657 if (err)
8e0aa4bc 2658 goto unlock;
ae24432c 2659
7768d197 2660 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 2661 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 2662 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
2663 err = -EOPNOTSUPP;
2664 goto unlock;
2665 }
7768d197 2666
8e0aa4bc
PP		 2667 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
2668 err = -EOPNOTSUPP;
2669 goto unlock;
2670 }
7768d197 2671
f6455de0 2672 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 2673 esw->offloads.encap = encap;
8e0aa4bc 2674 goto unlock;
7768d197
RD		 2675 }
2676
2677 if (esw->offloads.encap == encap)
8e0aa4bc 2678 goto unlock;
7768d197 2679
525e84be 2680 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2681 NL_SET_ERR_MSG_MOD(extack,
2682 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 2683 err = -EOPNOTSUPP;
2684 goto unlock;
7768d197
RD		 2685 }
2686
e52c2802 2687 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 2688
2689 esw->offloads.encap = encap;
e52c2802 2690
0da3c12d 2691 err = esw_create_offloads_fdb_tables(esw);
e52c2802 2692
7768d197 2693 if (err) {
8c98ee77
EB		 2694 NL_SET_ERR_MSG_MOD(extack,
2695 "Failed re-creating fast FDB table");
7768d197 2696 esw->offloads.encap = !encap;
0da3c12d 2697 (void)esw_create_offloads_fdb_tables(esw);
7768d197 2698 }
e52c2802 2699
8e0aa4bc
PP		 2700unlock:
2701 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2702 return err;
2703}
2704
98fdbea5
LR		 2705int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2706 enum devlink_eswitch_encap_mode *encap)
7768d197 2707{
bd939753 2708 struct mlx5_eswitch *esw;
9d1cef19 2709 int err;
7768d197 2710
bd939753
PP		 2711 esw = mlx5_devlink_eswitch_get(devlink);
2712 if (IS_ERR(esw))
2713 return PTR_ERR(esw);
2714
7768d197 2715
8e0aa4bc 2716 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2717 err = eswitch_devlink_esw_mode_check(esw);
2718 if (err)
8e0aa4bc 2719 goto unlock;
ae24432c 2720
7768d197 2721 *encap = esw->offloads.encap;
8e0aa4bc
PP		 2722unlock:
2723 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2724 return 0;
2725}
2726
c2d7712c
BW		 2727static bool
2728mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
2729{
2730 /* Currently, only ECPF based device has representor for host PF. */
2731 if (vport_num == MLX5_VPORT_PF &&
2732 !mlx5_core_is_ecpf_esw_manager(esw->dev))
2733 return false;
2734
2735 if (vport_num == MLX5_VPORT_ECPF &&
2736 !mlx5_ecpf_vport_exists(esw->dev))
2737 return false;
2738
2739 return true;
2740}
2741
f8e8fa02 2742void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 2743 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 2744 u8 rep_type)
127ea380 2745{
8693115a 2746 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02
BW		 2747 struct mlx5_eswitch_rep *rep;
2748 int i;
9deb2241 2749
8693115a 2750 esw->offloads.rep_ops[rep_type] = ops;
f8e8fa02 2751 mlx5_esw_for_all_reps(esw, i, rep) {
c2d7712c
BW		 2752 if (likely(mlx5_eswitch_vport_has_rep(esw, i))) {
2753 rep_data = &rep->rep_data[rep_type];
2754 atomic_set(&rep_data->state, REP_REGISTERED);
2755 }
f8e8fa02 2756 }
127ea380 2757}
f8e8fa02 2758EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 2759
f8e8fa02 2760void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 2761{
cb67b832 2762 struct mlx5_eswitch_rep *rep;
f8e8fa02 2763 int i;
cb67b832 2764
f6455de0 2765 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 2766 __unload_reps_all_vport(esw, rep_type);
127ea380 2767
f8e8fa02 2768 mlx5_esw_for_all_reps(esw, i, rep)
8693115a 2769 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 2770}
f8e8fa02 2771EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 2772
a4b97ab4 2773void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 2774{
726293f1
HHZ		 2775 struct mlx5_eswitch_rep *rep;
2776
879c8f84 2777 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 2778 return rep->rep_data[rep_type].priv;
726293f1 2779}
22215908
MB		 2780
2781void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 2782 u16 vport,
22215908
MB		 2783 u8 rep_type)
2784{
22215908
MB		 2785 struct mlx5_eswitch_rep *rep;
2786
879c8f84 2787 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 2788
8693115a
PP		 2789 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2790 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2791 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 2792 return NULL;
2793}
57cbd893 2794EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 2795
2796void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2797{
879c8f84 2798 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 2799}
57cbd893
MB		 2800EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2801
2802struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 2803 u16 vport)
57cbd893 2804{
879c8f84 2805 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 2806}
2807EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c
PP		 2808
2809bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2810{
2811 return vport_num >= MLX5_VPORT_FIRST_VF &&
2812 vport_num <= esw->dev->priv.sriov.max_vfs;
2813}
7445cfb1 2814
5b7cb745
PB		 2815bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
2816{
2817 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
2818}
2819EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
2820
7445cfb1
JL		 2821bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2822{
2823 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2824}
2825EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2826
0f0d3827 2827u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 2828 u16 vport_num)
2829{
133dcfc5 2830 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 2831
133dcfc5
VP		 2832 if (WARN_ON_ONCE(IS_ERR(vport)))
2833 return 0;
0f0d3827 2834
133dcfc5 2835 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 2836}
2837EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
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