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net/mlx5: DR, Support EMD tag in modify header for STEv1
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
69697b6e 51
47dd7e60
PP		 52#define mlx5_esw_for_each_rep(esw, i, rep) \
53 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
54
55#define mlx5_esw_for_each_sf_rep(esw, i, rep) \
56 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
57
58#define mlx5_esw_for_each_vf_rep(esw, index, rep) \
59 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
60 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
61
cd7e4186
BW		 62/* There are two match-all miss flows, one for unicast dst mac and
63 * one for multicast.
64 */
65#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 66#define UPLINK_REP_INDEX 0
67
c796bb7c
CM		 68#define MLX5_ESW_VPORT_TBL_SIZE 128
69#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
70
71static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
72 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
73 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
74 .flags = 0,
75};
76
879c8f84
BW		 77static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
78 u16 vport_num)
79{
47dd7e60 80 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 81}
82
6f7bbad1
JL		 83static void
84mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
85 struct mlx5_flow_spec *spec,
86 struct mlx5_esw_flow_attr *attr)
87{
88 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
036e19b9
HI		 89 attr && attr->in_rep)
90 spec->flow_context.flow_source =
91 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
92 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
93 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 94}
b7826076 95
f94d6389
CM		 96/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
97 * are not needed as well in the following process. So clear them all for simplicity.
98 */
99void
100mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
101{
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
103 void *misc2;
104
105 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
106 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
107
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
110
111 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
112 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
113 }
114}
115
c01cfd0f
JL		 116static void
117mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
118 struct mlx5_flow_spec *spec,
a508728a 119 struct mlx5_flow_attr *attr,
b055ecf5
MB		 120 struct mlx5_eswitch *src_esw,
121 u16 vport)
c01cfd0f
JL		 122{
123 void *misc2;
124 void *misc;
125
126 /* Use metadata matching because vport is not represented by single
127 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
128 */
129 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 130 if (mlx5_esw_indir_table_decap_vport(attr))
131 vport = mlx5_esw_indir_table_decap_vport(attr);
c01cfd0f
JL		 132 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
133 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
b055ecf5
MB		 134 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
135 vport));
c01cfd0f
JL		 136
137 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 138 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
139 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 140
141 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 142 } else {
143 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 144 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 145
146 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
147 MLX5_SET(fte_match_set_misc, misc,
148 source_eswitch_owner_vhca_id,
b055ecf5 149 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 150
151 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
152 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
153 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
154 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
155 source_eswitch_owner_vhca_id);
156
157 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
158 }
c01cfd0f
JL		 159}
160
a508728a
VB		 161static int
162esw_setup_decap_indir(struct mlx5_eswitch *esw,
163 struct mlx5_flow_attr *attr,
164 struct mlx5_flow_spec *spec)
165{
166 struct mlx5_flow_table *ft;
167
168 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
169 return -EOPNOTSUPP;
170
171 ft = mlx5_esw_indir_table_get(esw, attr, spec,
172 mlx5_esw_indir_table_decap_vport(attr), true);
173 return PTR_ERR_OR_ZERO(ft);
174}
175
9e51c0a6 176static void
a508728a
VB		 177esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
178 struct mlx5_flow_attr *attr)
179{
180 if (mlx5_esw_indir_table_decap_vport(attr))
181 mlx5_esw_indir_table_put(esw, attr,
182 mlx5_esw_indir_table_decap_vport(attr),
183 true);
184}
185
f94d6389
CM		 186static int
187esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
188 struct mlx5_flow_act *flow_act,
189 struct mlx5_esw_flow_attr *esw_attr,
190 int i)
191{
192 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
193 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
194 dest[i].sampler_id = esw_attr->sample->sampler_id;
195
196 return 0;
197}
198
a508728a 199static int
9e51c0a6
VB		 200esw_setup_ft_dest(struct mlx5_flow_destination *dest,
201 struct mlx5_flow_act *flow_act,
a508728a 202 struct mlx5_eswitch *esw,
9e51c0a6 203 struct mlx5_flow_attr *attr,
a508728a 204 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 205 int i)
206{
207 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
208 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
209 dest[i].ft = attr->dest_ft;
a508728a
VB		 210
211 if (mlx5_esw_indir_table_decap_vport(attr))
212 return esw_setup_decap_indir(esw, attr, spec);
213 return 0;
9e51c0a6
VB		 214}
215
216static void
217esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,
218 struct mlx5_flow_act *flow_act,
219 struct mlx5_fs_chains *chains,
220 int i)
221{
2a2c84fa
RD		 222 if (mlx5_chains_ignore_flow_level_supported(chains))
223 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
9e51c0a6
VB		 224 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
225 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
226}
227
228static int
229esw_setup_chain_dest(struct mlx5_flow_destination *dest,
230 struct mlx5_flow_act *flow_act,
231 struct mlx5_fs_chains *chains,
232 u32 chain, u32 prio, u32 level,
233 int i)
234{
235 struct mlx5_flow_table *ft;
236
237 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
238 ft = mlx5_chains_get_table(chains, chain, prio, level);
239 if (IS_ERR(ft))
240 return PTR_ERR(ft);
241
242 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
243 dest[i].ft = ft;
244 return 0;
245}
246
10742efc
VB		 247static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
248 int from, int to)
249{
250 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
251 struct mlx5_fs_chains *chains = esw_chains(esw);
252 int i;
253
254 for (i = from; i < to; i++)
255 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
256 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 257 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
258 esw_attr->dests[i].mdev))
259 mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport,
260 false);
10742efc
VB		 261}
262
263static bool
264esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
265{
266 int i;
267
268 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
269 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
270 return true;
271 return false;
272}
273
274static int
275esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
276 struct mlx5_flow_act *flow_act,
277 struct mlx5_eswitch *esw,
278 struct mlx5_fs_chains *chains,
279 struct mlx5_flow_attr *attr,
280 int *i)
281{
282 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
283 int j, err;
284
285 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
286 return -EOPNOTSUPP;
287
288 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
289 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
290 if (err)
291 goto err_setup_chain;
292 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
293 flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat;
294 }
295 return 0;
296
297err_setup_chain:
298 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
299 return err;
300}
301
302static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
303 struct mlx5_flow_attr *attr)
304{
305 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
306
307 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
308}
309
a508728a
VB		 310static bool
311esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
312{
313 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
314 int i;
315
316 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
317 if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
318 esw_attr->dests[i].mdev))
319 return true;
320 return false;
321}
322
323static int
324esw_setup_indir_table(struct mlx5_flow_destination *dest,
325 struct mlx5_flow_act *flow_act,
326 struct mlx5_eswitch *esw,
327 struct mlx5_flow_attr *attr,
328 struct mlx5_flow_spec *spec,
329 bool ignore_flow_lvl,
330 int *i)
331{
332 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
333 int j, err;
334
335 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
336 return -EOPNOTSUPP;
337
338 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
339 if (ignore_flow_lvl)
340 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
341 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
342
343 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec,
344 esw_attr->dests[j].rep->vport, false);
345 if (IS_ERR(dest[*i].ft)) {
346 err = PTR_ERR(dest[*i].ft);
347 goto err_indir_tbl_get;
348 }
349 }
350
351 if (mlx5_esw_indir_table_decap_vport(attr)) {
352 err = esw_setup_decap_indir(esw, attr, spec);
353 if (err)
354 goto err_indir_tbl_get;
355 }
356
357 return 0;
358
359err_indir_tbl_get:
360 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
361 return err;
362}
363
364static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
365{
366 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
367
368 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
369 esw_cleanup_decap_indir(esw, attr);
370}
371
9e51c0a6
VB		 372static void
373esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
374{
375 mlx5_chains_put_table(chains, chain, prio, level);
376}
377
378static void
379esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
380 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
381 int attr_idx, int dest_idx, bool pkt_reformat)
382{
383 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
384 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
385 dest[dest_idx].vport.vhca_id =
386 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
387 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
388 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
389 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
390 if (pkt_reformat) {
391 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
392 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
393 }
394 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
395 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
396 }
397}
398
399static int
400esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
401 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
402 int i)
403{
404 int j;
405
406 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
407 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
408 return i;
409}
410
e929e3da
MD		 411static bool
412esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
413{
414 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
415 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
416 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
417}
418
9e51c0a6
VB		 419static int
420esw_setup_dests(struct mlx5_flow_destination *dest,
421 struct mlx5_flow_act *flow_act,
422 struct mlx5_eswitch *esw,
423 struct mlx5_flow_attr *attr,
10742efc 424 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 425 int *i)
426{
427 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
428 struct mlx5_fs_chains *chains = esw_chains(esw);
429 int err = 0;
430
10742efc 431 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 432 esw_src_port_rewrite_supported(esw))
10742efc
VB		 433 attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE;
434
f94d6389
CM		 435 if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) {
436 esw_setup_sampler_dest(dest, flow_act, esw_attr, *i);
437 (*i)++;
438 } else if (attr->dest_ft) {
a508728a 439 esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);
9e51c0a6
VB		 440 (*i)++;
441 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
442 esw_setup_slow_path_dest(dest, flow_act, chains, *i);
443 (*i)++;
444 } else if (attr->dest_chain) {
445 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
446 1, 0, *i);
447 (*i)++;
a508728a
VB		 448 } else if (esw_is_indir_table(esw, attr)) {
449 err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i);
10742efc
VB		 450 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
451 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 452 } else {
453 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
454 }
455
456 return err;
457}
458
459static void
460esw_cleanup_dests(struct mlx5_eswitch *esw,
461 struct mlx5_flow_attr *attr)
462{
10742efc 463 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 464 struct mlx5_fs_chains *chains = esw_chains(esw);
465
a508728a
VB		 466 if (attr->dest_ft) {
467 esw_cleanup_decap_indir(esw, attr);
468 } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
10742efc
VB		 469 if (attr->dest_chain)
470 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 471 else if (esw_is_indir_table(esw, attr))
472 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 473 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
474 esw_cleanup_chain_src_port_rewrite(esw, attr);
475 }
9e51c0a6
VB		 476}
477
74491de9 478struct mlx5_flow_handle *
3d80d1a2
OG		 479mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
480 struct mlx5_flow_spec *spec,
c620b772 481 struct mlx5_flow_attr *attr)
3d80d1a2 482{
592d3651 483 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 484 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 485 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 486 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 487 bool split = !!(esw_attr->split_count);
488 struct mlx5_vport_tbl_attr fwd_attr;
74491de9 489 struct mlx5_flow_handle *rule;
e52c2802 490 struct mlx5_flow_table *fdb;
9e51c0a6 491 int i = 0;
3d80d1a2 492
f6455de0 493 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 494 return ERR_PTR(-EOPNOTSUPP);
495
6acfbf38
OG		 496 flow_act.action = attr->action;
497 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 498 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 499 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
500 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
501 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 502 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
503 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
504 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 505 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 506 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
507 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
508 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 509 }
6acfbf38 510 }
776b12b6 511
10742efc
VB		 512 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
513
66958ed9 514 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 515 int err;
516
10742efc 517 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 518 if (err) {
519 rule = ERR_PTR(err);
520 goto err_create_goto_table;
56e858df 521 }
e37a79e5 522 }
14e6b038 523
c620b772
AL		 524 if (esw_attr->decap_pkt_reformat)
525 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 526
66958ed9 527 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 528 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 529 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 530 i++;
3d80d1a2
OG		 531 }
532
93b3586e 533 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 534 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 535 if (attr->inner_match_level != MLX5_MATCH_NONE)
536 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 537
aa24670e 538 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 539 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 540
f94d6389
CM		 541 /* esw_attr->sample is allocated only when there is a sample action */
542 if (esw_attr->sample && esw_attr->sample->sample_default_tbl) {
543 fdb = esw_attr->sample->sample_default_tbl;
544 } else if (split) {
c620b772
AL		 545 fwd_attr.chain = attr->chain;
546 fwd_attr.prio = attr->prio;
547 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 548 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 549
0a9e2307 550 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 551 } else {
d18296ff 552 if (attr->chain || attr->prio)
ae430332
AL		 553 fdb = mlx5_chains_get_table(chains, attr->chain,
554 attr->prio, 0);
d18296ff 555 else
c620b772 556 fdb = attr->ft;
6fb0701a
PB		 557
558 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
a508728a 559 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 560 esw_attr->in_mdev->priv.eswitch,
561 esw_attr->in_rep->vport);
96e32687 562 }
e52c2802
PB		 563 if (IS_ERR(fdb)) {
564 rule = ERR_CAST(fdb);
565 goto err_esw_get;
566 }
567
84be2fda 568 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 569 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 570 &flow_act, dest, i);
84be2fda 571 else
10caabda 572 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 573 if (IS_ERR(rule))
e52c2802 574 goto err_add_rule;
375f51e2 575 else
525e84be 576 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 577
e52c2802
PB		 578 return rule;
579
580err_add_rule:
96e32687 581 if (split)
0a9e2307 582 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 583 else if (attr->chain || attr->prio)
ae430332 584 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 585err_esw_get:
9e51c0a6 586 esw_cleanup_dests(esw, attr);
e52c2802 587err_create_goto_table:
aa0cbbae 588 return rule;
3d80d1a2
OG		 589}
590
e4ad91f2
CM		 591struct mlx5_flow_handle *
592mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
593 struct mlx5_flow_spec *spec,
c620b772 594 struct mlx5_flow_attr *attr)
e4ad91f2
CM		 595{
596 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 597 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 598 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 599 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 600 struct mlx5_vport_tbl_attr fwd_attr;
e52c2802
PB		 601 struct mlx5_flow_table *fast_fdb;
602 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 603 struct mlx5_flow_handle *rule;
10742efc 604 int i, err = 0;
e4ad91f2 605
ae430332 606 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 607 if (IS_ERR(fast_fdb)) {
608 rule = ERR_CAST(fast_fdb);
609 goto err_get_fast;
610 }
611
c620b772
AL		 612 fwd_attr.chain = attr->chain;
613 fwd_attr.prio = attr->prio;
614 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 615 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 616 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 617 if (IS_ERR(fwd_fdb)) {
618 rule = ERR_CAST(fwd_fdb);
619 goto err_get_fwd;
620 }
621
e4ad91f2 622 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 623 for (i = 0; i < esw_attr->split_count; i++) {
a508728a
VB		 624 if (esw_is_indir_table(esw, attr))
625 err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i);
626 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
10742efc
VB		 627 err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr,
628 &i);
629 else
630 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
631
632 if (err) {
633 rule = ERR_PTR(err);
634 goto err_chain_src_rewrite;
635 }
636 }
e4ad91f2 637 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 638 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 639 i++;
640
a508728a 641 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 642 esw_attr->in_mdev->priv.eswitch,
643 esw_attr->in_rep->vport);
e4ad91f2 644
93b3586e 645 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 646 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 647
278d51f2 648 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 649 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 650
10742efc
VB		 651 if (IS_ERR(rule)) {
652 i = esw_attr->split_count;
653 goto err_chain_src_rewrite;
654 }
e4ad91f2 655
525e84be 656 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 657
658 return rule;
10742efc
VB		 659err_chain_src_rewrite:
660 esw_put_dest_tables_loop(esw, attr, 0, i);
0a9e2307 661 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 662err_get_fwd:
ae430332 663 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 664err_get_fast:
e4ad91f2
CM		 665 return rule;
666}
667
e52c2802
PB		 668static void
669__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
670 struct mlx5_flow_handle *rule,
c620b772 671 struct mlx5_flow_attr *attr,
e52c2802
PB		 672 bool fwd_rule)
673{
c620b772 674 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 675 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 676 bool split = (esw_attr->split_count > 0);
677 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 678 int i;
e52c2802
PB		 679
680 mlx5_del_flow_rules(rule);
10caabda 681
84be2fda 682 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 683 /* unref the term table */
684 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 685 if (esw_attr->dests[i].termtbl)
686 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 687 }
10caabda
OS		 688 }
689
525e84be 690 atomic64_dec(&esw->offloads.num_flows);
e52c2802 691
c620b772
AL		 692 if (fwd_rule || split) {
693 fwd_attr.chain = attr->chain;
694 fwd_attr.prio = attr->prio;
695 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 696 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 697 }
698
e52c2802 699 if (fwd_rule) {
0a9e2307 700 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 701 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
10742efc 702 esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count);
e52c2802 703 } else {
96e32687 704 if (split)
0a9e2307 705 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 706 else if (attr->chain || attr->prio)
ae430332 707 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 708 esw_cleanup_dests(esw, attr);
e52c2802
PB		 709 }
710}
711
d85cdccb
OG		 712void
713mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
714 struct mlx5_flow_handle *rule,
c620b772 715 struct mlx5_flow_attr *attr)
d85cdccb 716{
e52c2802 717 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 718}
719
48265006
OG		 720void
721mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
722 struct mlx5_flow_handle *rule,
c620b772 723 struct mlx5_flow_attr *attr)
48265006 724{
e52c2802 725 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 726}
727
f5f82476
OG		 728static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
729{
730 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 731 unsigned long i;
732 int err = 0;
f5f82476
OG		 733
734 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
47dd7e60 735 mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 736 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 737 continue;
738
739 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
740 if (err)
741 goto out;
742 }
743
744out:
745 return err;
746}
747
748static struct mlx5_eswitch_rep *
749esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
750{
751 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
752
753 in_rep = attr->in_rep;
df65a573 754 out_rep = attr->dests[0].rep;
f5f82476
OG		 755
756 if (push)
757 vport = in_rep;
758 else if (pop)
759 vport = out_rep;
760 else
761 vport = in_rep;
762
763 return vport;
764}
765
766static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
767 bool push, bool pop, bool fwd)
768{
769 struct mlx5_eswitch_rep *in_rep, *out_rep;
770
771 if ((push || pop) && !fwd)
772 goto out_notsupp;
773
774 in_rep = attr->in_rep;
df65a573 775 out_rep = attr->dests[0].rep;
f5f82476 776
b05af6aa 777 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 778 goto out_notsupp;
779
b05af6aa 780 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 781 goto out_notsupp;
782
783 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
784 if (!push && !pop && fwd)
b05af6aa 785 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 786 goto out_notsupp;
787
788 /* protects against (1) setting rules with different vlans to push and
789 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
790 */
1482bd3d 791 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 792 goto out_notsupp;
793
794 return 0;
795
796out_notsupp:
9eb78923 797 return -EOPNOTSUPP;
f5f82476
OG		 798}
799
800int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
c620b772 801 struct mlx5_flow_attr *attr)
f5f82476
OG		 802{
803 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 804 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 805 struct mlx5_eswitch_rep *vport = NULL;
806 bool push, pop, fwd;
807 int err = 0;
808
6acfbf38 809 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 810 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 811 return 0;
812
f5f82476
OG		 813 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
814 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 815 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
816 !attr->dest_chain);
f5f82476 817
0e18134f
VB		 818 mutex_lock(&esw->state_lock);
819
c620b772 820 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
f5f82476 821 if (err)
0e18134f 822 goto unlock;
f5f82476 823
39ac237c 824 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476 825
c620b772 826 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 827
828 if (!push && !pop && fwd) {
829 /* tracks VF --> wire rules without vlan push action */
c620b772 830 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 831 vport->vlan_refcount++;
39ac237c 832 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 833 }
834
0e18134f 835 goto unlock;
f5f82476
OG		 836 }
837
838 if (!push && !pop)
0e18134f 839 goto unlock;
f5f82476
OG		 840
841 if (!(offloads->vlan_push_pop_refcount)) {
842 /* it's the 1st vlan rule, apply global vlan pop policy */
843 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
844 if (err)
845 goto out;
846 }
847 offloads->vlan_push_pop_refcount++;
848
849 if (push) {
850 if (vport->vlan_refcount)
851 goto skip_set_push;
852
c620b772
AL		 853 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
854 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
f5f82476
OG		 855 if (err)
856 goto out;
c620b772 857 vport->vlan = esw_attr->vlan_vid[0];
f5f82476
OG		 858skip_set_push:
859 vport->vlan_refcount++;
860 }
861out:
862 if (!err)
39ac237c 863 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 864unlock:
865 mutex_unlock(&esw->state_lock);
f5f82476
OG		 866 return err;
867}
868
869int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
c620b772 870 struct mlx5_flow_attr *attr)
f5f82476
OG		 871{
872 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
c620b772 873 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
f5f82476
OG		 874 struct mlx5_eswitch_rep *vport = NULL;
875 bool push, pop, fwd;
876 int err = 0;
877
6acfbf38 878 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 879 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 880 return 0;
881
39ac237c 882 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 883 return 0;
884
885 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
886 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
887 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
888
0e18134f
VB		 889 mutex_lock(&esw->state_lock);
890
c620b772 891 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
f5f82476
OG		 892
893 if (!push && !pop && fwd) {
894 /* tracks VF --> wire rules without vlan push action */
c620b772 895 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 896 vport->vlan_refcount--;
897
0e18134f 898 goto out;
f5f82476
OG		 899 }
900
901 if (push) {
902 vport->vlan_refcount--;
903 if (vport->vlan_refcount)
904 goto skip_unset_push;
905
906 vport->vlan = 0;
907 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
908 0, 0, SET_VLAN_STRIP);
909 if (err)
910 goto out;
911 }
912
913skip_unset_push:
914 offloads->vlan_push_pop_refcount--;
915 if (offloads->vlan_push_pop_refcount)
0e18134f 916 goto out;
f5f82476
OG		 917
918 /* no more vlan rules, stop global vlan pop policy */
919 err = esw_set_global_vlan_pop(esw, 0);
920
921out:
0e18134f 922 mutex_unlock(&esw->state_lock);
f5f82476
OG		 923 return err;
924}
925
f7a68945 926struct mlx5_flow_handle *
3a46f4fb
MB		 927mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
928 struct mlx5_eswitch_rep *rep,
02f3afd9 929 u32 sqn)
ab22be9b 930{
66958ed9 931 struct mlx5_flow_act flow_act = {0};
4c5009c5 932 struct mlx5_flow_destination dest = {};
74491de9 933 struct mlx5_flow_handle *flow_rule;
c5bb1730 934 struct mlx5_flow_spec *spec;
ab22be9b
OG		 935 void *misc;
936
1b9a07ee 937 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 938 if (!spec) {
ab22be9b
OG		 939 flow_rule = ERR_PTR(-ENOMEM);
940 goto out;
941 }
942
c5bb1730 943 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 944 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a 945 /* source vport is the esw manager */
3a46f4fb
MB		 946 MLX5_SET(fte_match_set_misc, misc, source_port, rep->esw->manager_vport);
947 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a 948 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
3a46f4fb 949 MLX5_CAP_GEN(rep->esw->dev, vhca_id));
ab22be9b 950
c5bb1730 951 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 952 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
953 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3a46f4fb 954 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
7d97822a
MB		 955 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
956 source_eswitch_owner_vhca_id);
ab22be9b 957
c5bb1730 958 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 959 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 960 dest.vport.num = rep->vport;
961 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
962 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 963 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 964
3a46f4fb 965 flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb,
39ac237c 966 spec, &flow_act, &dest, 1);
ab22be9b 967 if (IS_ERR(flow_rule))
3a46f4fb
MB		 968 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
969 PTR_ERR(flow_rule));
ab22be9b 970out:
c5bb1730 971 kvfree(spec);
ab22be9b
OG		 972 return flow_rule;
973}
57cbd893 974EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 975
159fe639
MB		 976void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
977{
978 mlx5_del_flow_rules(rule);
979}
980
8e404fef
VB		 981static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
982{
983 struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules;
47dd7e60 984 int i = 0, num_vfs = esw->esw_funcs.num_vfs;
8e404fef
VB		 985
986 if (!num_vfs || !flows)
987 return;
988
47dd7e60
PP		 989 for (i = 0; i < num_vfs; i++)
990 mlx5_del_flow_rules(flows[i]);
8e404fef
VB		 991
992 kvfree(flows);
993}
994
995static int
996mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
997{
8e404fef
VB		 998 struct mlx5_flow_destination dest = {};
999 struct mlx5_flow_act flow_act = {0};
6308a5f0 1000 int num_vfs, rule_idx = 0, err = 0;
8e404fef
VB		 1001 struct mlx5_flow_handle *flow_rule;
1002 struct mlx5_flow_handle **flows;
1003 struct mlx5_flow_spec *spec;
47dd7e60
PP		 1004 struct mlx5_vport *vport;
1005 unsigned long i;
6308a5f0 1006 u16 vport_num;
8e404fef
VB		 1007
1008 num_vfs = esw->esw_funcs.num_vfs;
1009 flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL);
1010 if (!flows)
1011 return -ENOMEM;
1012
1013 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1014 if (!spec) {
1015 err = -ENOMEM;
1016 goto alloc_err;
1017 }
1018
1019 MLX5_SET(fte_match_param, spec->match_criteria,
1020 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1021 MLX5_SET(fte_match_param, spec->match_criteria,
1022 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1023 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1024 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1025
1026 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1027 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1028 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1029
47dd7e60
PP		 1030 mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) {
1031 vport_num = vport->vport;
8e404fef
VB		 1032 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1033 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1034 dest.vport.num = vport_num;
1035
1036 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1037 spec, &flow_act, &dest, 1);
1038 if (IS_ERR(flow_rule)) {
1039 err = PTR_ERR(flow_rule);
1040 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n",
1041 rule_idx, PTR_ERR(flow_rule));
1042 goto rule_err;
1043 }
1044 flows[rule_idx++] = flow_rule;
1045 }
1046
1047 esw->fdb_table.offloads.send_to_vport_meta_rules = flows;
1048 kvfree(spec);
1049 return 0;
1050
1051rule_err:
1052 while (--rule_idx >= 0)
1053 mlx5_del_flow_rules(flows[rule_idx]);
1054 kvfree(spec);
1055alloc_err:
1056 kvfree(flows);
1057 return err;
1058}
1059
5b7cb745
PB		 1060static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1061{
1062 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1063 MLX5_FDB_TO_VPORT_REG_C_1;
1064}
1065
332bd3a5 1066static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 1067{
1068 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 1069 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1070 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 1071 u8 curr, wanted;
c1286050
JL		 1072 int err;
1073
5b7cb745
PB		 1074 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1075 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 1076 return 0;
c1286050 1077
e08a6832
LR		 1078 MLX5_SET(query_esw_vport_context_in, in, opcode,
1079 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1080 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 1081 if (err)
1082 return err;
1083
5b7cb745
PB		 1084 curr = MLX5_GET(query_esw_vport_context_out, out,
1085 esw_vport_context.fdb_to_vport_reg_c_id);
1086 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1087 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1088 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 1089
332bd3a5 1090 if (enable)
5b7cb745 1091 curr |= wanted;
332bd3a5 1092 else
5b7cb745 1093 curr &= ~wanted;
c1286050 1094
e08a6832 1095 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 1096 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 1097 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 1098 field_select.fdb_to_vport_reg_c_id, 1);
1099
e08a6832 1100 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 1101 if (!err) {
1102 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1103 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1104 else
1105 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1106 }
1107
1108 return err;
c1286050
JL		 1109}
1110
a5641cb5
JL		 1111static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1112 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1113 struct mlx5_flow_spec *spec,
1114 struct mlx5_flow_destination *dest)
1115{
a5641cb5 1116 void *misc;
ac004b83 1117
a5641cb5
JL		 1118 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1119 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1120 misc_parameters_2);
0f0d3827
PB		 1121 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1122 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1123
a5641cb5
JL		 1124 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1125 } else {
1126 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1127 misc_parameters);
ac004b83 1128
a5641cb5
JL		 1129 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1130 MLX5_CAP_GEN(peer_dev, vhca_id));
1131
1132 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1133
1134 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1135 misc_parameters);
1136 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1137 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1138 source_eswitch_owner_vhca_id);
1139 }
ac004b83
RD		 1140
1141 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1142 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1143 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1144 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1145}
1146
a5641cb5
JL		 1147static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1148 struct mlx5_eswitch *peer_esw,
1149 struct mlx5_flow_spec *spec,
1150 u16 vport)
1151{
1152 void *misc;
1153
1154 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1155 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1156 misc_parameters_2);
1157 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1158 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1159 vport));
1160 } else {
1161 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1162 misc_parameters);
1163 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1164 }
1165}
1166
ac004b83
RD		 1167static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1168 struct mlx5_core_dev *peer_dev)
1169{
1170 struct mlx5_flow_destination dest = {};
1171 struct mlx5_flow_act flow_act = {0};
1172 struct mlx5_flow_handle **flows;
ac004b83
RD		 1173 /* total vports is the same for both e-switches */
1174 int nvports = esw->total_vports;
47dd7e60
PP		 1175 struct mlx5_flow_handle *flow;
1176 struct mlx5_flow_spec *spec;
1177 struct mlx5_vport *vport;
1178 unsigned long i;
ac004b83 1179 void *misc;
47dd7e60 1180 int err;
ac004b83
RD		 1181
1182 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1183 if (!spec)
1184 return -ENOMEM;
1185
a5641cb5 1186 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 1187
1188 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
1189 if (!flows) {
1190 err = -ENOMEM;
1191 goto alloc_flows_err;
1192 }
1193
1194 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1195 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1196 misc_parameters);
1197
81cd229c 1198 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1199 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1200 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1201 spec, MLX5_VPORT_PF);
1202
81cd229c
BW		 1203 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1204 spec, &flow_act, &dest, 1);
1205 if (IS_ERR(flow)) {
1206 err = PTR_ERR(flow);
1207 goto add_pf_flow_err;
1208 }
47dd7e60 1209 flows[vport->index] = flow;
81cd229c
BW		 1210 }
1211
1212 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1213 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c
BW		 1214 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1215 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1216 spec, &flow_act, &dest, 1);
1217 if (IS_ERR(flow)) {
1218 err = PTR_ERR(flow);
1219 goto add_ecpf_flow_err;
1220 }
47dd7e60 1221 flows[vport->index] = flow;
81cd229c
BW		 1222 }
1223
47dd7e60 1224 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1225 esw_set_peer_miss_rule_source_port(esw,
1226 peer_dev->priv.eswitch,
47dd7e60 1227 spec, vport->vport);
a5641cb5 1228
ac004b83
RD		 1229 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1230 spec, &flow_act, &dest, 1);
1231 if (IS_ERR(flow)) {
1232 err = PTR_ERR(flow);
81cd229c 1233 goto add_vf_flow_err;
ac004b83 1234 }
47dd7e60 1235 flows[vport->index] = flow;
ac004b83
RD		 1236 }
1237
1238 esw->fdb_table.offloads.peer_miss_rules = flows;
1239
1240 kvfree(spec);
1241 return 0;
1242
81cd229c 1243add_vf_flow_err:
47dd7e60
PP		 1244 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1245 if (!flows[vport->index])
1246 continue;
1247 mlx5_del_flow_rules(flows[vport->index]);
1248 }
1249 if (mlx5_ecpf_vport_exists(esw->dev)) {
1250 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1251 mlx5_del_flow_rules(flows[vport->index]);
1252 }
81cd229c 1253add_ecpf_flow_err:
47dd7e60
PP		 1254 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1255 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1256 mlx5_del_flow_rules(flows[vport->index]);
1257 }
81cd229c
BW		 1258add_pf_flow_err:
1259 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1260 kvfree(flows);
1261alloc_flows_err:
1262 kvfree(spec);
1263 return err;
1264}
1265
1266static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1267{
1268 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1269 struct mlx5_vport *vport;
1270 unsigned long i;
ac004b83
RD		 1271
1272 flows = esw->fdb_table.offloads.peer_miss_rules;
1273
47dd7e60
PP		 1274 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1275 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1276
47dd7e60
PP		 1277 if (mlx5_ecpf_vport_exists(esw->dev)) {
1278 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1279 mlx5_del_flow_rules(flows[vport->index]);
1280 }
81cd229c 1281
47dd7e60
PP		 1282 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1283 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1284 mlx5_del_flow_rules(flows[vport->index]);
1285 }
ac004b83
RD		 1286 kvfree(flows);
1287}
1288
3aa33572
OG		 1289static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1290{
66958ed9 1291 struct mlx5_flow_act flow_act = {0};
4c5009c5 1292 struct mlx5_flow_destination dest = {};
74491de9 1293 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1294 struct mlx5_flow_spec *spec;
f80be543
MB		 1295 void *headers_c;
1296 void *headers_v;
3aa33572 1297 int err = 0;
f80be543
MB		 1298 u8 *dmac_c;
1299 u8 *dmac_v;
3aa33572 1300
1b9a07ee 1301 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1302 if (!spec) {
3aa33572
OG		 1303 err = -ENOMEM;
1304 goto out;
1305 }
1306
f80be543
MB		 1307 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1308 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1309 outer_headers);
1310 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1311 outer_headers.dmac_47_16);
1312 dmac_c[0] = 0x01;
1313
3aa33572 1314 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1315 dest.vport.num = esw->manager_vport;
66958ed9 1316 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1317
39ac237c
PB		 1318 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1319 spec, &flow_act, &dest, 1);
3aa33572
OG		 1320 if (IS_ERR(flow_rule)) {
1321 err = PTR_ERR(flow_rule);
f80be543 1322 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1323 goto out;
1324 }
1325
f80be543
MB		 1326 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1327
1328 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1329 outer_headers);
1330 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1331 outer_headers.dmac_47_16);
1332 dmac_v[0] = 0x01;
39ac237c
PB		 1333 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1334 spec, &flow_act, &dest, 1);
f80be543
MB		 1335 if (IS_ERR(flow_rule)) {
1336 err = PTR_ERR(flow_rule);
1337 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1338 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1339 goto out;
1340 }
1341
1342 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1343
3aa33572 1344out:
c5bb1730 1345 kvfree(spec);
3aa33572
OG		 1346 return err;
1347}
1348
11b717d6
PB		 1349struct mlx5_flow_handle *
1350esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1351{
1352 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1353 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1354 struct mlx5_flow_context *flow_context;
1355 struct mlx5_flow_handle *flow_rule;
1356 struct mlx5_flow_destination dest;
1357 struct mlx5_flow_spec *spec;
1358 void *misc;
1359
60acc105
PB		 1360 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1361 return ERR_PTR(-EOPNOTSUPP);
1362
9f4d9283 1363 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1364 if (!spec)
1365 return ERR_PTR(-ENOMEM);
1366
1367 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1368 misc_parameters_2);
1369 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1370 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1371 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1372 misc_parameters_2);
1373 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1374 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1375 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1376 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1377 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1378
1379 flow_context = &spec->flow_context;
1380 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1381 flow_context->flow_tag = tag;
1382 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1383 dest.ft = esw->offloads.ft_offloads;
1384
1385 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1386 kvfree(spec);
11b717d6
PB		 1387
1388 if (IS_ERR(flow_rule))
1389 esw_warn(esw->dev,
1390 "Failed to create restore rule for tag: %d, err(%d)\n",
1391 tag, (int)PTR_ERR(flow_rule));
1392
1393 return flow_rule;
1394}
1395
1967ce6e 1396#define MAX_PF_SQ 256
cd3d07e7 1397#define MAX_SQ_NVPORTS 32
1967ce6e 1398
a5641cb5
JL		 1399static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1400 u32 *flow_group_in)
1401{
1402 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1403 flow_group_in,
1404 match_criteria);
1405
1406 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1407 MLX5_SET(create_flow_group_in, flow_group_in,
1408 match_criteria_enable,
1409 MLX5_MATCH_MISC_PARAMETERS_2);
1410
0f0d3827
PB		 1411 MLX5_SET(fte_match_param, match_criteria,
1412 misc_parameters_2.metadata_reg_c_0,
1413 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1414 } else {
1415 MLX5_SET(create_flow_group_in, flow_group_in,
1416 match_criteria_enable,
1417 MLX5_MATCH_MISC_PARAMETERS);
1418
1419 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1420 misc_parameters.source_port);
1421 }
1422}
1423
ae430332 1424#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1425static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1426{
1427 struct mlx5_vport_tbl_attr attr;
1428 struct mlx5_vport *vport;
47dd7e60 1429 unsigned long i;
4c7f4028
CM		 1430
1431 attr.chain = 0;
1432 attr.prio = 1;
47dd7e60 1433 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1434 attr.vport = vport->vport;
c796bb7c 1435 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1436 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1437 }
1438}
1439
0a9e2307 1440static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1441{
1442 struct mlx5_vport_tbl_attr attr;
1443 struct mlx5_flow_table *fdb;
1444 struct mlx5_vport *vport;
47dd7e60 1445 unsigned long i;
4c7f4028
CM		 1446
1447 attr.chain = 0;
1448 attr.prio = 1;
47dd7e60 1449 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1450 attr.vport = vport->vport;
c796bb7c 1451 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1452 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1453 if (IS_ERR(fdb))
1454 goto out;
1455 }
1456 return 0;
1457
1458out:
0a9e2307 1459 esw_vport_tbl_put(esw);
4c7f4028
CM		 1460 return PTR_ERR(fdb);
1461}
1462
ae430332
AL		 1463#define fdb_modify_header_fwd_to_table_supported(esw) \
1464 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1465static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1466{
1467 struct mlx5_core_dev *dev = esw->dev;
1468
1469 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1470 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1471
1472 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1473 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1474 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1475 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1476 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1477 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1478 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1479 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1480 /* Disabled when ttl workaround is needed, e.g
1481 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1482 */
1483 esw_warn(dev,
1484 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1485 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1486 } else {
1487 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1488 esw_info(dev, "Supported tc chains and prios offload\n");
1489 }
1490
1491 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1492 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1493}
1494
1495static int
1496esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1497{
1498 struct mlx5_core_dev *dev = esw->dev;
1499 struct mlx5_flow_table *nf_ft, *ft;
1500 struct mlx5_chains_attr attr = {};
1501 struct mlx5_fs_chains *chains;
1502 u32 fdb_max;
1503 int err;
1504
1505 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1506
1507 esw_init_chains_offload_flags(esw, &attr.flags);
1508 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1509 attr.max_ft_sz = fdb_max;
1510 attr.max_grp_num = esw->params.large_group_num;
1511 attr.default_ft = miss_fdb;
c9355682 1512 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1513
1514 chains = mlx5_chains_create(dev, &attr);
1515 if (IS_ERR(chains)) {
1516 err = PTR_ERR(chains);
1517 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1518 return err;
1519 }
1520
1521 esw->fdb_table.offloads.esw_chains_priv = chains;
1522
1523 /* Create tc_end_ft which is the always created ft chain */
1524 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1525 1, 0);
1526 if (IS_ERR(nf_ft)) {
1527 err = PTR_ERR(nf_ft);
1528 goto nf_ft_err;
1529 }
1530
1531 /* Always open the root for fast path */
1532 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1533 if (IS_ERR(ft)) {
1534 err = PTR_ERR(ft);
1535 goto level_0_err;
1536 }
1537
1538 /* Open level 1 for split fdb rules now if prios isn't supported */
1539 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1540 err = esw_vport_tbl_get(esw);
ae430332
AL		 1541 if (err)
1542 goto level_1_err;
1543 }
1544
1545 mlx5_chains_set_end_ft(chains, nf_ft);
1546
1547 return 0;
1548
1549level_1_err:
1550 mlx5_chains_put_table(chains, 0, 1, 0);
1551level_0_err:
1552 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1553nf_ft_err:
1554 mlx5_chains_destroy(chains);
1555 esw->fdb_table.offloads.esw_chains_priv = NULL;
1556
1557 return err;
1558}
1559
1560static void
1561esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1562{
1563 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1564 esw_vport_tbl_put(esw);
ae430332
AL		 1565 mlx5_chains_put_table(chains, 0, 1, 0);
1566 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1567 mlx5_chains_destroy(chains);
1568}
1569
1570#else /* CONFIG_MLX5_CLS_ACT */
1571
1572static int
1573esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1574{ return 0; }
1575
1576static void
1577esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1578{}
1579
1580#endif
1581
0da3c12d 1582static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1583{
1584 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1585 struct mlx5_flow_table_attr ft_attr = {};
8e404fef 1586 int num_vfs, table_size, ix, err = 0;
1967ce6e
OG		 1587 struct mlx5_core_dev *dev = esw->dev;
1588 struct mlx5_flow_namespace *root_ns;
1589 struct mlx5_flow_table *fdb = NULL;
39ac237c 1590 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1591 struct mlx5_flow_group *g;
1592 void *match_criteria;
f80be543 1593 u8 *dmac;
1967ce6e
OG		 1594
1595 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1596
1b9a07ee 1597 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1598 if (!flow_group_in)
1599 return -ENOMEM;
1600
1601 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1602 if (!root_ns) {
1603 esw_warn(dev, "Failed to get FDB flow namespace\n");
1604 err = -EOPNOTSUPP;
1605 goto ns_err;
1606 }
8463daf1
MG		 1607 esw->fdb_table.offloads.ns = root_ns;
1608 err = mlx5_flow_namespace_set_mode(root_ns,
1609 esw->dev->priv.steering->mode);
1610 if (err) {
1611 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1612 goto ns_err;
1613 }
1967ce6e 1614
0da3c12d 1615 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
8e404fef 1616 MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs;
b3ba5149 1617
e52c2802
PB		 1618 /* create the slow path fdb with encap set, so further table instances
1619 * can be created at run time while VFs are probed if the FW allows that.
1620 */
1621 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1622 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1623 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1624
1625 ft_attr.flags = flags;
b3ba5149
ES		 1626 ft_attr.max_fte = table_size;
1627 ft_attr.prio = FDB_SLOW_PATH;
1628
1629 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1630 if (IS_ERR(fdb)) {
1631 err = PTR_ERR(fdb);
1632 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1633 goto slow_fdb_err;
1634 }
52fff327 1635 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1636
ae430332 1637 err = esw_chains_create(esw, fdb);
39ac237c 1638 if (err) {
ae430332 1639 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1640 goto fdb_chains_err;
e52c2802
PB		 1641 }
1642
69697b6e 1643 /* create send-to-vport group */
69697b6e
OG		 1644 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1645 MLX5_MATCH_MISC_PARAMETERS);
1646
1647 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1648
1649 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1650 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
7d97822a
MB		 1651 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1652 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1653 misc_parameters.source_eswitch_owner_vhca_id);
1654 MLX5_SET(create_flow_group_in, flow_group_in,
1655 source_eswitch_owner_vhca_id_valid, 1);
1656 }
69697b6e 1657
0da3c12d 1658 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1659 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1660 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1661
1662 g = mlx5_create_flow_group(fdb, flow_group_in);
1663 if (IS_ERR(g)) {
1664 err = PTR_ERR(g);
1665 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1666 goto send_vport_err;
1667 }
1668 esw->fdb_table.offloads.send_to_vport_grp = g;
1669
e929e3da
MD		 1670 if (esw_src_port_rewrite_supported(esw)) {
1671 /* meta send to vport */
1672 memset(flow_group_in, 0, inlen);
1673 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1674 MLX5_MATCH_MISC_PARAMETERS_2);
8e404fef 1675
e929e3da 1676 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
8e404fef 1677
e929e3da
MD		 1678 MLX5_SET(fte_match_param, match_criteria,
1679 misc_parameters_2.metadata_reg_c_0,
1680 mlx5_eswitch_get_vport_metadata_mask());
1681 MLX5_SET(fte_match_param, match_criteria,
1682 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1683
1684 num_vfs = esw->esw_funcs.num_vfs;
1685 if (num_vfs) {
1686 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1687 MLX5_SET(create_flow_group_in, flow_group_in,
1688 end_flow_index, ix + num_vfs - 1);
1689 ix += num_vfs;
1690
1691 g = mlx5_create_flow_group(fdb, flow_group_in);
1692 if (IS_ERR(g)) {
1693 err = PTR_ERR(g);
1694 esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n",
1695 err);
1696 goto send_vport_meta_err;
1697 }
1698 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1699
1700 err = mlx5_eswitch_add_send_to_vport_meta_rules(esw);
1701 if (err)
1702 goto meta_rule_err;
8e404fef 1703 }
8e404fef
VB		 1704 }
1705
6cec0229
MD		 1706 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1707 /* create peer esw miss group */
1708 memset(flow_group_in, 0, inlen);
ac004b83 1709
6cec0229 1710 esw_set_flow_group_source_port(esw, flow_group_in);
a5641cb5 1711
6cec0229
MD		 1712 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1713 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1714 flow_group_in,
1715 match_criteria);
ac004b83 1716
6cec0229
MD		 1717 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1718 misc_parameters.source_eswitch_owner_vhca_id);
a5641cb5 1719
6cec0229
MD		 1720 MLX5_SET(create_flow_group_in, flow_group_in,
1721 source_eswitch_owner_vhca_id_valid, 1);
1722 }
ac004b83 1723
6cec0229
MD		 1724 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1725 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1726 ix + esw->total_vports - 1);
1727 ix += esw->total_vports;
ac004b83 1728
6cec0229
MD		 1729 g = mlx5_create_flow_group(fdb, flow_group_in);
1730 if (IS_ERR(g)) {
1731 err = PTR_ERR(g);
1732 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1733 goto peer_miss_err;
1734 }
1735 esw->fdb_table.offloads.peer_miss_grp = g;
ac004b83 1736 }
ac004b83 1737
69697b6e
OG		 1738 /* create miss group */
1739 memset(flow_group_in, 0, inlen);
f80be543
MB		 1740 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1741 MLX5_MATCH_OUTER_HEADERS);
1742 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1743 match_criteria);
1744 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1745 outer_headers.dmac_47_16);
1746 dmac[0] = 0x01;
69697b6e
OG		 1747
1748 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1749 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1750 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1751
1752 g = mlx5_create_flow_group(fdb, flow_group_in);
1753 if (IS_ERR(g)) {
1754 err = PTR_ERR(g);
1755 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1756 goto miss_err;
1757 }
1758 esw->fdb_table.offloads.miss_grp = g;
1759
3aa33572
OG		 1760 err = esw_add_fdb_miss_rule(esw);
1761 if (err)
1762 goto miss_rule_err;
1763
c88a026e 1764 kvfree(flow_group_in);
69697b6e
OG		 1765 return 0;
1766
3aa33572
OG		 1767miss_rule_err:
1768 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1769miss_err:
6cec0229
MD		 1770 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1771 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1772peer_miss_err:
8e404fef
VB		 1773 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1774meta_rule_err:
1775 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1776 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1777send_vport_meta_err:
69697b6e
OG		 1778 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1779send_vport_err:
ae430332 1780 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1781fdb_chains_err:
52fff327 1782 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1783slow_fdb_err:
8463daf1
MG		 1784 /* Holds true only as long as DMFS is the default */
1785 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1786ns_err:
1787 kvfree(flow_group_in);
1788 return err;
1789}
1790
1967ce6e 1791static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1792{
e52c2802 1793 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1794 return;
1795
1967ce6e 1796 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1797 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1798 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
8e404fef 1799 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
69697b6e 1800 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1801 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1802 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1803 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1804 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1805 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1806
ae430332
AL		 1807 esw_chains_destroy(esw, esw_chains(esw));
1808
52fff327 1809 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1810 /* Holds true only as long as DMFS is the default */
1811 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1812 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1813 atomic64_set(&esw->user_count, 0);
69697b6e 1814}
c116c6ee 1815
8d6bd3c3 1816static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1817{
b3ba5149 1818 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1819 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1820 struct mlx5_flow_table *ft_offloads;
1821 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1822 int err = 0;
1823
1824 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1825 if (!ns) {
1826 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1827 return -EOPNOTSUPP;
c116c6ee
OG		 1828 }
1829
8d6bd3c3 1830 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
11b717d6 1831 ft_attr.prio = 1;
b3ba5149
ES		 1832
1833 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1834 if (IS_ERR(ft_offloads)) {
1835 err = PTR_ERR(ft_offloads);
1836 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1837 return err;
1838 }
1839
1840 esw->offloads.ft_offloads = ft_offloads;
1841 return 0;
1842}
1843
1844static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1845{
1846 struct mlx5_esw_offload *offloads = &esw->offloads;
1847
1848 mlx5_destroy_flow_table(offloads->ft_offloads);
1849}
fed9ce22 1850
8d6bd3c3 1851static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1852{
1853 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1854 struct mlx5_flow_group *g;
fed9ce22 1855 u32 *flow_group_in;
8d6bd3c3 1856 int nvports;
fed9ce22 1857 int err = 0;
fed9ce22 1858
8d6bd3c3 1859 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1860 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1861 if (!flow_group_in)
1862 return -ENOMEM;
1863
1864 /* create vport rx group */
a5641cb5 1865 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1866
1867 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1868 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1869
1870 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1871
1872 if (IS_ERR(g)) {
1873 err = PTR_ERR(g);
1874 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1875 goto out;
1876 }
1877
1878 esw->offloads.vport_rx_group = g;
1879out:
e574978a 1880 kvfree(flow_group_in);
fed9ce22
OG		 1881 return err;
1882}
1883
1884static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1885{
1886 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1887}
1888
74491de9 1889struct mlx5_flow_handle *
02f3afd9 1890mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1891 struct mlx5_flow_destination *dest)
fed9ce22 1892{
66958ed9 1893 struct mlx5_flow_act flow_act = {0};
74491de9 1894 struct mlx5_flow_handle *flow_rule;
c5bb1730 1895 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1896 void *misc;
1897
1b9a07ee 1898 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1899 if (!spec) {
fed9ce22
OG		 1900 flow_rule = ERR_PTR(-ENOMEM);
1901 goto out;
1902 }
1903
a5641cb5
JL		 1904 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1905 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1906 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1907 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1908
a5641cb5 1909 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1910 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1911 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1912
a5641cb5
JL		 1913 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1914 } else {
1915 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1916 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1917
1918 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1919 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1920
1921 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1922 }
fed9ce22 1923
66958ed9 1924 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1925 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1926 &flow_act, dest, 1);
fed9ce22
OG		 1927 if (IS_ERR(flow_rule)) {
1928 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1929 goto out;
1930 }
1931
1932out:
c5bb1730 1933 kvfree(spec);
fed9ce22
OG		 1934 return flow_rule;
1935}
feae9087 1936
47dd7e60 1937static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 1938{
1939 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1940 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 1941 struct mlx5_vport *vport;
1942 unsigned long i;
cc617ced
PP		 1943
1944 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1945 return -EOPNOTSUPP;
1946
1947 if (esw->mode == MLX5_ESWITCH_NONE)
1948 return -EOPNOTSUPP;
1949
1950 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1951 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1952 mlx5_mode = MLX5_INLINE_MODE_NONE;
1953 goto out;
1954 case MLX5_CAP_INLINE_MODE_L2:
1955 mlx5_mode = MLX5_INLINE_MODE_L2;
1956 goto out;
1957 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1958 goto query_vports;
1959 }
1960
1961query_vports:
1962 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 1963 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
1964 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 1965 if (prev_mlx5_mode != mlx5_mode)
1966 return -EINVAL;
1967 prev_mlx5_mode = mlx5_mode;
1968 }
1969
1970out:
1971 *mode = mlx5_mode;
1972 return 0;
e08a6832 1973}
bf3347c4 1974
11b717d6
PB		 1975static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1976{
1977 struct mlx5_esw_offload *offloads = &esw->offloads;
1978
60acc105
PB		 1979 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1980 return;
1981
6724e66b 1982 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 1983 mlx5_destroy_flow_group(offloads->restore_group);
1984 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
1985}
1986
1987static int esw_create_restore_table(struct mlx5_eswitch *esw)
1988{
d65dbedf 1989 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 1990 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1991 struct mlx5_flow_table_attr ft_attr = {};
1992 struct mlx5_core_dev *dev = esw->dev;
1993 struct mlx5_flow_namespace *ns;
6724e66b 1994 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 1995 void *match_criteria, *misc;
1996 struct mlx5_flow_table *ft;
1997 struct mlx5_flow_group *g;
1998 u32 *flow_group_in;
1999 int err = 0;
2000
60acc105
PB		 2001 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2002 return 0;
2003
11b717d6
PB		 2004 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2005 if (!ns) {
2006 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2007 return -EOPNOTSUPP;
2008 }
2009
2010 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2011 if (!flow_group_in) {
2012 err = -ENOMEM;
2013 goto out_free;
2014 }
2015
a91d98a0 2016 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2017 ft = mlx5_create_flow_table(ns, &ft_attr);
2018 if (IS_ERR(ft)) {
2019 err = PTR_ERR(ft);
2020 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2021 err);
2022 goto out_free;
2023 }
2024
11b717d6
PB		 2025 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2026 match_criteria);
2027 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2028 misc_parameters_2);
2029
2030 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2031 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2032 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2033 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2034 ft_attr.max_fte - 1);
2035 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2036 MLX5_MATCH_MISC_PARAMETERS_2);
2037 g = mlx5_create_flow_group(ft, flow_group_in);
2038 if (IS_ERR(g)) {
2039 err = PTR_ERR(g);
2040 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2041 err);
2042 goto err_group;
2043 }
2044
6724e66b
PB		 2045 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2046 MLX5_SET(copy_action_in, modact, src_field,
2047 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2048 MLX5_SET(copy_action_in, modact, dst_field,
2049 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2050 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2051 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2052 modact);
2053 if (IS_ERR(mod_hdr)) {
e9864539 2054 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2055 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2056 err);
6724e66b
PB		 2057 goto err_mod_hdr;
2058 }
2059
11b717d6
PB		 2060 esw->offloads.ft_offloads_restore = ft;
2061 esw->offloads.restore_group = g;
6724e66b 2062 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2063
c8508713
RD		 2064 kvfree(flow_group_in);
2065
11b717d6
PB		 2066 return 0;
2067
6724e66b
PB		 2068err_mod_hdr:
2069 mlx5_destroy_flow_group(g);
11b717d6
PB		 2070err_group:
2071 mlx5_destroy_flow_table(ft);
2072out_free:
2073 kvfree(flow_group_in);
2074
2075 return err;
cc617ced
PP		 2076}
2077
db7ff19e
EB		 2078static int esw_offloads_start(struct mlx5_eswitch *esw,
2079 struct netlink_ext_ack *extack)
c930a3ad 2080{
062f4bf4 2081 int err, err1;
c930a3ad 2082
8e0aa4bc
PP		 2083 mlx5_eswitch_disable_locked(esw, false);
2084 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2085 esw->dev->priv.sriov.num_vfs);
6c419ba8 2086 if (err) {
8c98ee77
EB		 2087 NL_SET_ERR_MSG_MOD(extack,
2088 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 2089 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2090 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2091 if (err1) {
2092 NL_SET_ERR_MSG_MOD(extack,
2093 "Failed setting eswitch back to legacy");
2094 }
6c419ba8 2095 }
bffaa916
RD		 2096 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2097 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2098 &esw->offloads.inline_mode)) {
2099 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2100 NL_SET_ERR_MSG_MOD(extack,
2101 "Inline mode is different between vports");
bffaa916
RD		 2102 }
2103 }
c930a3ad
OG		 2104 return err;
2105}
2106
47dd7e60
PP		 2107static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2108 struct mlx5_eswitch_rep *rep,
2109 xa_mark_t mark)
e8d31c4d 2110{
47dd7e60
PP		 2111 bool mark_set;
2112
2113 /* Copy the mark from vport to its rep */
2114 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2115 if (mark_set)
2116 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
e8d31c4d
MB		 2117}
2118
47dd7e60 2119static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2120{
e8d31c4d 2121 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2122 int rep_type;
2123 int err;
e8d31c4d 2124
47dd7e60
PP		 2125 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2126 if (!rep)
e8d31c4d
MB		 2127 return -ENOMEM;
2128
47dd7e60
PP		 2129 rep->vport = vport->vport;
2130 rep->vport_index = vport->index;
2131 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2132 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2133
47dd7e60
PP		 2134 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2135 if (err)
2136 goto insert_err;
2137
2138 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2139 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2140 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2141 return 0;
2142
2143insert_err:
2144 kfree(rep);
2145 return err;
2146}
2147
2148static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2149 struct mlx5_eswitch_rep *rep)
2150{
2151 xa_erase(&esw->offloads.vport_reps, rep->vport);
2152 kfree(rep);
2153}
2154
2155void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2156{
2157 struct mlx5_eswitch_rep *rep;
2158 unsigned long i;
e8d31c4d 2159
47dd7e60
PP		 2160 mlx5_esw_for_each_rep(esw, i, rep)
2161 mlx5_esw_offloads_rep_cleanup(esw, rep);
2162 xa_destroy(&esw->offloads.vport_reps);
2163}
2164
2165int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2166{
2167 struct mlx5_vport *vport;
2168 unsigned long i;
2169 int err;
2170
2171 xa_init(&esw->offloads.vport_reps);
2172
2173 mlx5_esw_for_each_vport(esw, i, vport) {
2174 err = mlx5_esw_offloads_rep_init(esw, vport);
2175 if (err)
2176 goto err;
2177 }
e8d31c4d 2178 return 0;
47dd7e60
PP		 2179
2180err:
2181 esw_offloads_cleanup_reps(esw);
2182 return err;
e8d31c4d
MB		 2183}
2184
c9b99abc
BW		 2185static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2186 struct mlx5_eswitch_rep *rep, u8 rep_type)
2187{
8693115a 2188 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2189 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2190 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2191}
2192
d7f33a45
VP		 2193static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2194{
2195 struct mlx5_eswitch_rep *rep;
47dd7e60 2196 unsigned long i;
d7f33a45
VP		 2197
2198 mlx5_esw_for_each_sf_rep(esw, i, rep)
2199 __esw_offloads_unload_rep(esw, rep, rep_type);
2200}
2201
4110fc59 2202static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2203{
2204 struct mlx5_eswitch_rep *rep;
47dd7e60 2205 unsigned long i;
4110fc59 2206
d7f33a45
VP		 2207 __unload_reps_sf_vport(esw, rep_type);
2208
47dd7e60 2209 mlx5_esw_for_each_vf_rep(esw, i, rep)
4110fc59 2210 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 2211
81cd229c
BW		 2212 if (mlx5_ecpf_vport_exists(esw->dev)) {
2213 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2214 __esw_offloads_unload_rep(esw, rep, rep_type);
2215 }
2216
2217 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2218 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2219 __esw_offloads_unload_rep(esw, rep, rep_type);
2220 }
2221
879c8f84 2222 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 2223 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2224}
2225
d970812b 2226int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2227{
c2d7712c
BW		 2228 struct mlx5_eswitch_rep *rep;
2229 int rep_type;
a4b97ab4
MB		 2230 int err;
2231
c2d7712c
BW		 2232 rep = mlx5_eswitch_get_rep(esw, vport_num);
2233 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2234 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2235 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2236 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2237 if (err)
2238 goto err_reps;
2239 }
2240
2241 return 0;
a4b97ab4
MB		 2242
2243err_reps:
c2d7712c
BW		 2244 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2245 for (--rep_type; rep_type >= 0; rep_type--)
2246 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2247 return err;
2248}
2249
d970812b 2250void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2251{
2252 struct mlx5_eswitch_rep *rep;
2253 int rep_type;
2254
c2d7712c
BW		 2255 rep = mlx5_eswitch_get_rep(esw, vport_num);
2256 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2257 __esw_offloads_unload_rep(esw, rep, rep_type);
2258}
2259
38679b5a
PP		 2260int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2261{
2262 int err;
2263
2264 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2265 return 0;
2266
865d6d1c
RD		 2267 if (vport_num != MLX5_VPORT_UPLINK) {
2268 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2269 if (err)
2270 return err;
2271 }
c7eddc60 2272
38679b5a 2273 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2274 if (err)
2275 goto load_err;
2276 return err;
2277
2278load_err:
865d6d1c
RD		 2279 if (vport_num != MLX5_VPORT_UPLINK)
2280 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2281 return err;
2282}
2283
2284void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2285{
2286 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2287 return;
2288
2289 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c
RD		 2290
2291 if (vport_num != MLX5_VPORT_UPLINK)
2292 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2293}
2294
ac004b83
RD		 2295#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2296#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2297
2298static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2299 struct mlx5_eswitch *peer_esw)
2300{
ac004b83 2301
027d7166 2302 return esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
ac004b83
RD		 2303}
2304
2305static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
2306{
d956873f 2307#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2308 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2309#endif
ac004b83
RD		 2310 esw_del_fdb_peer_miss_rules(esw);
2311}
2312
8463daf1
MG		 2313static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2314 struct mlx5_eswitch *peer_esw,
2315 bool pair)
2316{
2317 struct mlx5_flow_root_namespace *peer_ns;
2318 struct mlx5_flow_root_namespace *ns;
2319 int err;
2320
2321 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2322 ns = esw->dev->priv.steering->fdb_root_ns;
2323
2324 if (pair) {
2325 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2326 if (err)
2327 return err;
2328
e53e6655 2329 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 2330 if (err) {
2331 mlx5_flow_namespace_set_peer(ns, NULL);
2332 return err;
2333 }
2334 } else {
2335 mlx5_flow_namespace_set_peer(ns, NULL);
2336 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2337 }
2338
2339 return 0;
2340}
2341
ac004b83
RD		 2342static int mlx5_esw_offloads_devcom_event(int event,
2343 void *my_data,
2344 void *event_data)
2345{
2346 struct mlx5_eswitch *esw = my_data;
ac004b83 2347 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 2348 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 2349 int err;
2350
2351 switch (event) {
2352 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 2353 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2354 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2355 break;
2356
8463daf1 2357 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2358 if (err)
2359 goto err_out;
8463daf1
MG		 2360 err = mlx5_esw_offloads_pair(esw, peer_esw);
2361 if (err)
2362 goto err_peer;
ac004b83
RD		 2363
2364 err = mlx5_esw_offloads_pair(peer_esw, esw);
2365 if (err)
2366 goto err_pair;
2367
2368 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2369 break;
2370
2371 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2372 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
2373 break;
2374
2375 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2376 mlx5_esw_offloads_unpair(peer_esw);
2377 mlx5_esw_offloads_unpair(esw);
8463daf1 2378 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2379 break;
2380 }
2381
2382 return 0;
2383
2384err_pair:
2385 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 2386err_peer:
2387 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2388err_out:
2389 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2390 event, err);
2391 return err;
2392}
2393
2394static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2395{
2396 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2397
04de7dda
RD		 2398 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2399 mutex_init(&esw->offloads.peer_mutex);
2400
ac004b83
RD		 2401 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2402 return;
2403
2404 mlx5_devcom_register_component(devcom,
2405 MLX5_DEVCOM_ESW_OFFLOADS,
2406 mlx5_esw_offloads_devcom_event,
2407 esw);
2408
2409 mlx5_devcom_send_event(devcom,
2410 MLX5_DEVCOM_ESW_OFFLOADS,
2411 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2412}
2413
2414static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2415{
2416 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2417
2418 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2419 return;
2420
2421 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2422 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2423
2424 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2425}
2426
7bf481d7 2427bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 2428{
2429 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2430 return false;
2431
2432 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2433 MLX5_FDB_TO_VPORT_REG_C_0))
2434 return false;
2435
2436 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2437 return false;
2438
2439 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2440 mlx5_ecpf_vport_exists(esw->dev))
2441 return false;
2442
2443 return true;
2444}
2445
133dcfc5
VP		 2446u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2447{
7cd7becd 2448 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2449 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2450 u32 pf_num;
133dcfc5
VP		 2451 int id;
2452
7cd7becd 2453 /* Only 4 bits of pf_num */
2454 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2455 if (pf_num > max_pf_num)
2456 return 0;
133dcfc5 2457
7cd7becd 2458 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2459 /* Use only non-zero vport_id (1-4095) for all PF's */
2460 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2461 if (id < 0)
2462 return 0;
2463 id = (pf_num << ESW_VPORT_BITS) | id;
2464 return id;
133dcfc5
VP		 2465}
2466
2467void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2468{
7cd7becd 2469 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2470
2471 /* Metadata contains only 12 bits of actual ida id */
2472 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2473}
2474
2475static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2476 struct mlx5_vport *vport)
2477{
133dcfc5
VP		 2478 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2479 vport->metadata = vport->default_metadata;
2480 return vport->metadata ? 0 : -ENOSPC;
2481}
2482
2483static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2484 struct mlx5_vport *vport)
2485{
406493a5 2486 if (!vport->default_metadata)
133dcfc5
VP		 2487 return;
2488
2489 WARN_ON(vport->metadata != vport->default_metadata);
2490 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2491}
2492
fc99c3d6
VP		 2493static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2494{
2495 struct mlx5_vport *vport;
47dd7e60 2496 unsigned long i;
fc99c3d6
VP		 2497
2498 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2499 return;
2500
47dd7e60 2501 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 2502 esw_offloads_vport_metadata_cleanup(esw, vport);
2503}
2504
2505static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2506{
2507 struct mlx5_vport *vport;
47dd7e60 2508 unsigned long i;
fc99c3d6 2509 int err;
fc99c3d6
VP		 2510
2511 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2512 return 0;
2513
47dd7e60 2514 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 2515 err = esw_offloads_vport_metadata_setup(esw, vport);
2516 if (err)
2517 goto metadata_err;
2518 }
2519
2520 return 0;
2521
2522metadata_err:
2523 esw_offloads_metadata_uninit(esw);
2524 return err;
2525}
2526
7bf481d7
PP		 2527int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable)
2528{
2529 int err = 0;
2530
2531 down_write(&esw->mode_lock);
2532 if (esw->mode != MLX5_ESWITCH_NONE) {
2533 err = -EBUSY;
2534 goto done;
2535 }
2536 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2537 err = -EOPNOTSUPP;
2538 goto done;
2539 }
2540 if (enable)
2541 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2542 else
2543 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2544done:
2545 up_write(&esw->mode_lock);
2546 return err;
2547}
2548
748da30b 2549int
89a0f1fb
PP		 2550esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2551 struct mlx5_vport *vport)
7445cfb1 2552{
7445cfb1
JL		 2553 int err;
2554
07bab950 2555 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2556 if (err)
fc99c3d6 2557 return err;
7445cfb1 2558
2c40db2f
PP		 2559 err = esw_acl_egress_ofld_setup(esw, vport);
2560 if (err)
2561 goto egress_err;
07bab950
VP		 2562
2563 return 0;
2564
2565egress_err:
2566 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2567 return err;
2568}
18486737 2569
748da30b 2570void
89a0f1fb
PP		 2571esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2572 struct mlx5_vport *vport)
2573{
ea651a86 2574 esw_acl_egress_ofld_cleanup(vport);
07bab950 2575 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 2576}
7445cfb1 2577
748da30b 2578static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2579{
2580 struct mlx5_vport *vport;
18486737 2581
748da30b 2582 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2583 if (IS_ERR(vport))
2584 return PTR_ERR(vport);
2585
4e9a9ef7 2586 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 2587}
2588
748da30b 2589static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2590{
786ef904 2591 struct mlx5_vport *vport;
7445cfb1 2592
748da30b 2593 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 2594 if (IS_ERR(vport))
2595 return;
2596
748da30b 2597 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 2598}
2599
062f4bf4 2600static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 2601{
34ca6535 2602 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 2603 int err;
2604
5c1d260e 2605 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2606 mutex_init(&esw->fdb_table.offloads.vports.lock);
2607 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 2608 atomic64_set(&esw->user_count, 0);
e52c2802 2609
34ca6535
VB		 2610 indir = mlx5_esw_indir_table_init();
2611 if (IS_ERR(indir)) {
2612 err = PTR_ERR(indir);
2613 goto create_indir_err;
2614 }
2615 esw->fdb_table.offloads.indir = indir;
2616
748da30b 2617 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2618 if (err)
f8d1edda 2619 goto create_acl_err;
18486737 2620
8d6bd3c3 2621 err = esw_create_offloads_table(esw);
c930a3ad 2622 if (err)
11b717d6 2623 goto create_offloads_err;
c930a3ad 2624
11b717d6 2625 err = esw_create_restore_table(esw);
c930a3ad 2626 if (err)
11b717d6
PB		 2627 goto create_restore_err;
2628
0da3c12d 2629 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 2630 if (err)
2631 goto create_fdb_err;
c930a3ad 2632
8d6bd3c3 2633 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 2634 if (err)
2635 goto create_fg_err;
2636
2637 return 0;
2638
2639create_fg_err:
1967ce6e 2640 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2641create_fdb_err:
11b717d6
PB		 2642 esw_destroy_restore_table(esw);
2643create_restore_err:
2644 esw_destroy_offloads_table(esw);
2645create_offloads_err:
748da30b 2646 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2647create_acl_err:
34ca6535
VB		 2648 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
2649create_indir_err:
f8d1edda 2650 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2651 return err;
2652}
2653
eca8cc38
BW		 2654static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2655{
2656 esw_destroy_vport_rx_group(esw);
eca8cc38 2657 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2658 esw_destroy_restore_table(esw);
2659 esw_destroy_offloads_table(esw);
748da30b 2660 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 2661 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 2662 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2663}
2664
7e736f9a
PP		 2665static void
2666esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2667{
5ccf2770 2668 bool host_pf_disabled;
7e736f9a 2669 u16 new_num_vfs;
a3888f33 2670
7e736f9a
PP		 2671 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2672 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2673 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2674 host_params_context.host_pf_disabled);
a3888f33 2675
7e736f9a
PP		 2676 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2677 return;
a3888f33
BW		 2678
2679 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2680 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2681 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2682 } else {
7e736f9a 2683 int err;
a3888f33 2684
23bb50cf
BW		 2685 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2686 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2687 if (err)
7e736f9a 2688 return;
a3888f33 2689 }
7e736f9a 2690 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2691}
2692
7e736f9a 2693static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2694{
7e736f9a
PP		 2695 struct mlx5_host_work *host_work;
2696 struct mlx5_eswitch *esw;
dd28087c 2697 const u32 *out;
ac35dcd6 2698
7e736f9a
PP		 2699 host_work = container_of(work, struct mlx5_host_work, work);
2700 esw = host_work->esw;
a3888f33 2701
dd28087c
PP		 2702 out = mlx5_esw_query_functions(esw->dev);
2703 if (IS_ERR(out))
7e736f9a 2704 goto out;
a3888f33 2705
7e736f9a 2706 esw_vfs_changed_event_handler(esw, out);
dd28087c 2707 kvfree(out);
a3888f33 2708out:
ac35dcd6
VP		 2709 kfree(host_work);
2710}
2711
16fff98a 2712int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2713{
cd56f929 2714 struct mlx5_esw_functions *esw_funcs;
a3888f33 2715 struct mlx5_host_work *host_work;
a3888f33
BW		 2716 struct mlx5_eswitch *esw;
2717
2718 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2719 if (!host_work)
2720 return NOTIFY_DONE;
2721
cd56f929
VP		 2722 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2723 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2724
2725 host_work->esw = esw;
2726
062f4bf4 2727 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2728 queue_work(esw->work_queue, &host_work->work);
2729
2730 return NOTIFY_OK;
2731}
2732
a53cf949
PP		 2733static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2734{
2735 const u32 *query_host_out;
2736
2737 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2738 return 0;
2739
2740 query_host_out = mlx5_esw_query_functions(esw->dev);
2741 if (IS_ERR(query_host_out))
2742 return PTR_ERR(query_host_out);
2743
2744 /* Mark non local controller with non zero controller number. */
2745 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2746 host_params_context.host_number);
2747 kvfree(query_host_out);
2748 return 0;
2749}
2750
f1b9acd3
PP		 2751bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
2752{
2753 /* Local controller is always valid */
2754 if (controller == 0)
2755 return true;
2756
2757 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2758 return false;
2759
2760 /* External host number starts with zero in device */
2761 return (controller == esw->offloads.host_number + 1);
2762}
2763
5896b972 2764int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2765{
c9355682 2766 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 2767 struct mlx5_vport *vport;
47dd7e60
PP		 2768 unsigned long i;
2769 int err;
eca8cc38 2770
9a64144d
MG		 2771 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2772 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2773 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2774 else
2775 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2776
2bb72e7e 2777 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2778 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2779
a53cf949
PP		 2780 err = mlx5_esw_host_number_init(esw);
2781 if (err)
cd1ef966 2782 goto err_metadata;
a53cf949 2783
fc99c3d6
VP		 2784 err = esw_offloads_metadata_init(esw);
2785 if (err)
2786 goto err_metadata;
2787
332bd3a5
PP		 2788 err = esw_set_passing_vport_metadata(esw, true);
2789 if (err)
2790 goto err_vport_metadata;
c1286050 2791
c9355682
CM		 2792 reg_c0_obj_pool = mapping_create(sizeof(struct mlx5_mapped_obj),
2793 ESW_REG_C0_USER_DATA_METADATA_MASK,
2794 true);
2795 if (IS_ERR(reg_c0_obj_pool)) {
2796 err = PTR_ERR(reg_c0_obj_pool);
2797 goto err_pool;
2798 }
2799 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
2800
7983a675
PB		 2801 err = esw_offloads_steering_init(esw);
2802 if (err)
2803 goto err_steering_init;
2804
3b83b6c2
DL		 2805 /* Representor will control the vport link state */
2806 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2807 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2808
c2d7712c
BW		 2809 /* Uplink vport rep must load first. */
2810 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2811 if (err)
c2d7712c 2812 goto err_uplink;
c1286050 2813
c2d7712c 2814 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2815 if (err)
c2d7712c 2816 goto err_vports;
eca8cc38
BW		 2817
2818 esw_offloads_devcom_init(esw);
a3888f33 2819
eca8cc38
BW		 2820 return 0;
2821
925a6acc 2822err_vports:
c2d7712c
BW		 2823 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2824err_uplink:
7983a675 2825 esw_offloads_steering_cleanup(esw);
79949985 2826err_steering_init:
c9355682
CM		 2827 mapping_destroy(reg_c0_obj_pool);
2828err_pool:
79949985 2829 esw_set_passing_vport_metadata(esw, false);
7983a675 2830err_vport_metadata:
fc99c3d6
VP		 2831 esw_offloads_metadata_uninit(esw);
2832err_metadata:
8463daf1 2833 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2834 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2835 return err;
2836}
2837
db7ff19e
EB		 2838static int esw_offloads_stop(struct mlx5_eswitch *esw,
2839 struct netlink_ext_ack *extack)
c930a3ad 2840{
062f4bf4 2841 int err, err1;
c930a3ad 2842
8e0aa4bc
PP		 2843 mlx5_eswitch_disable_locked(esw, false);
2844 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2845 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2846 if (err) {
8c98ee77 2847 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2848 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2849 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2850 if (err1) {
2851 NL_SET_ERR_MSG_MOD(extack,
2852 "Failed setting eswitch back to offloads");
2853 }
6c419ba8 2854 }
c930a3ad
OG		 2855
2856 return err;
2857}
2858
5896b972 2859void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2860{
ac004b83 2861 esw_offloads_devcom_cleanup(esw);
5896b972 2862 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2863 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2864 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2865 esw_offloads_steering_cleanup(esw);
c9355682 2866 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 2867 esw_offloads_metadata_uninit(esw);
8463daf1 2868 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2869 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2870 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2871}
2872
ef78618b 2873static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2874{
2875 switch (mode) {
2876 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2877 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2878 break;
2879 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2880 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2881 break;
2882 default:
2883 return -EINVAL;
2884 }
2885
2886 return 0;
2887}
2888
ef78618b
OG		 2889static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2890{
2891 switch (mlx5_mode) {
f6455de0 2892 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2893 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2894 break;
f6455de0 2895 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2896 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2897 break;
2898 default:
2899 return -EINVAL;
2900 }
2901
2902 return 0;
2903}
2904
bffaa916
RD		 2905static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2906{
2907 switch (mode) {
2908 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2909 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2910 break;
2911 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2912 *mlx5_mode = MLX5_INLINE_MODE_L2;
2913 break;
2914 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2915 *mlx5_mode = MLX5_INLINE_MODE_IP;
2916 break;
2917 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2918 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2919 break;
2920 default:
2921 return -EINVAL;
2922 }
2923
2924 return 0;
2925}
2926
2927static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2928{
2929 switch (mlx5_mode) {
2930 case MLX5_INLINE_MODE_NONE:
2931 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2932 break;
2933 case MLX5_INLINE_MODE_L2:
2934 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2935 break;
2936 case MLX5_INLINE_MODE_IP:
2937 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2938 break;
2939 case MLX5_INLINE_MODE_TCP_UDP:
2940 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2941 break;
2942 default:
2943 return -EINVAL;
2944 }
2945
2946 return 0;
2947}
2948
ae24432c
PP		 2949static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2950{
2951 /* devlink commands in NONE eswitch mode are currently supported only
2952 * on ECPF.
2953 */
2954 return (esw->mode == MLX5_ESWITCH_NONE &&
2955 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2956}
2957
db7ff19e
EB		 2958int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2959 struct netlink_ext_ack *extack)
9d1cef19 2960{
9d1cef19 2961 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 2962 struct mlx5_eswitch *esw;
ea2128fd 2963 int err = 0;
9d1cef19 2964
bd939753
PP		 2965 esw = mlx5_devlink_eswitch_get(devlink);
2966 if (IS_ERR(esw))
2967 return PTR_ERR(esw);
9d1cef19 2968
ef78618b 2969 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2970 return -EINVAL;
2971
7dc84de9
RD		 2972 err = mlx5_esw_try_lock(esw);
2973 if (err < 0) {
2974 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
2975 return err;
2976 }
2977 cur_mlx5_mode = err;
2978 err = 0;
2979
c930a3ad 2980 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 2981 goto unlock;
c930a3ad
OG		 2982
2983 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 2984 err = esw_offloads_start(esw, extack);
c930a3ad 2985 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 2986 err = esw_offloads_stop(esw, extack);
c930a3ad 2987 else
8e0aa4bc
PP		 2988 err = -EINVAL;
2989
2990unlock:
7dc84de9 2991 mlx5_esw_unlock(esw);
8e0aa4bc 2992 return err;
feae9087
OG		 2993}
2994
2995int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2996{
bd939753 2997 struct mlx5_eswitch *esw;
9d1cef19 2998 int err;
c930a3ad 2999
bd939753
PP		 3000 esw = mlx5_devlink_eswitch_get(devlink);
3001 if (IS_ERR(esw))
3002 return PTR_ERR(esw);
c930a3ad 3003
c55479d0 3004 down_write(&esw->mode_lock);
bd939753 3005 err = eswitch_devlink_esw_mode_check(esw);
ae24432c 3006 if (err)
8e0aa4bc 3007 goto unlock;
ae24432c 3008
8e0aa4bc
PP		 3009 err = esw_mode_to_devlink(esw->mode, mode);
3010unlock:
c55479d0 3011 up_write(&esw->mode_lock);
8e0aa4bc 3012 return err;
feae9087 3013}
127ea380 3014
47dd7e60
PP		 3015static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3016 struct netlink_ext_ack *extack)
3017{
3018 struct mlx5_core_dev *dev = esw->dev;
3019 struct mlx5_vport *vport;
3020 u16 err_vport_num = 0;
3021 unsigned long i;
3022 int err = 0;
3023
3024 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3025 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3026 if (err) {
3027 err_vport_num = vport->vport;
3028 NL_SET_ERR_MSG_MOD(extack,
3029 "Failed to set min inline on vport");
3030 goto revert_inline_mode;
3031 }
3032 }
3033 return 0;
3034
3035revert_inline_mode:
3036 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3037 if (vport->vport == err_vport_num)
3038 break;
3039 mlx5_modify_nic_vport_min_inline(dev,
3040 vport->vport,
3041 esw->offloads.inline_mode);
3042 }
3043 return err;
3044}
3045
db7ff19e
EB		 3046int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3047 struct netlink_ext_ack *extack)
bffaa916
RD		 3048{
3049 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3050 struct mlx5_eswitch *esw;
bffaa916 3051 u8 mlx5_mode;
47dd7e60 3052 int err;
bffaa916 3053
bd939753
PP		 3054 esw = mlx5_devlink_eswitch_get(devlink);
3055 if (IS_ERR(esw))
3056 return PTR_ERR(esw);
bffaa916 3057
c55479d0 3058 down_write(&esw->mode_lock);
ae24432c
PP		 3059 err = eswitch_devlink_esw_mode_check(esw);
3060 if (err)
8e0aa4bc 3061 goto out;
ae24432c 3062
c415f704
OG		 3063 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3064 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3065 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 3066 goto out;
c8b838d1 3067 fallthrough;
c415f704 3068 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3069 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3070 err = -EOPNOTSUPP;
3071 goto out;
c415f704
OG		 3072 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3073 break;
3074 }
bffaa916 3075
525e84be 3076 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3077 NL_SET_ERR_MSG_MOD(extack,
3078 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3079 err = -EOPNOTSUPP;
3080 goto out;
375f51e2
RD		 3081 }
3082
bffaa916
RD		 3083 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3084 if (err)
3085 goto out;
3086
47dd7e60
PP		 3087 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3088 if (err)
3089 goto out;
bffaa916
RD		 3090
3091 esw->offloads.inline_mode = mlx5_mode;
c55479d0 3092 up_write(&esw->mode_lock);
bffaa916
RD		 3093 return 0;
3094
bffaa916 3095out:
c55479d0 3096 up_write(&esw->mode_lock);
bffaa916
RD		 3097 return err;
3098}
3099
3100int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3101{
bd939753 3102 struct mlx5_eswitch *esw;
9d1cef19 3103 int err;
bffaa916 3104
bd939753
PP		 3105 esw = mlx5_devlink_eswitch_get(devlink);
3106 if (IS_ERR(esw))
3107 return PTR_ERR(esw);
bffaa916 3108
c55479d0 3109 down_write(&esw->mode_lock);
ae24432c
PP		 3110 err = eswitch_devlink_esw_mode_check(esw);
3111 if (err)
8e0aa4bc 3112 goto unlock;
ae24432c 3113
8e0aa4bc
PP		 3114 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3115unlock:
c55479d0 3116 up_write(&esw->mode_lock);
8e0aa4bc 3117 return err;
bffaa916
RD		 3118}
3119
98fdbea5
LR		 3120int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3121 enum devlink_eswitch_encap_mode encap,
db7ff19e 3122 struct netlink_ext_ack *extack)
7768d197
RD		 3123{
3124 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3125 struct mlx5_eswitch *esw;
7768d197
RD		 3126 int err;
3127
bd939753
PP		 3128 esw = mlx5_devlink_eswitch_get(devlink);
3129 if (IS_ERR(esw))
3130 return PTR_ERR(esw);
7768d197 3131
c55479d0 3132 down_write(&esw->mode_lock);
ae24432c
PP		 3133 err = eswitch_devlink_esw_mode_check(esw);
3134 if (err)
8e0aa4bc 3135 goto unlock;
ae24432c 3136
7768d197 3137 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3138 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3139 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3140 err = -EOPNOTSUPP;
3141 goto unlock;
3142 }
7768d197 3143
8e0aa4bc
PP		 3144 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3145 err = -EOPNOTSUPP;
3146 goto unlock;
3147 }
7768d197 3148
f6455de0 3149 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3150 esw->offloads.encap = encap;
8e0aa4bc 3151 goto unlock;
7768d197
RD		 3152 }
3153
3154 if (esw->offloads.encap == encap)
8e0aa4bc 3155 goto unlock;
7768d197 3156
525e84be 3157 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3158 NL_SET_ERR_MSG_MOD(extack,
3159 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3160 err = -EOPNOTSUPP;
3161 goto unlock;
7768d197
RD		 3162 }
3163
e52c2802 3164 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3165
3166 esw->offloads.encap = encap;
e52c2802 3167
0da3c12d 3168 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3169
7768d197 3170 if (err) {
8c98ee77
EB		 3171 NL_SET_ERR_MSG_MOD(extack,
3172 "Failed re-creating fast FDB table");
7768d197 3173 esw->offloads.encap = !encap;
0da3c12d 3174 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3175 }
e52c2802 3176
8e0aa4bc 3177unlock:
c55479d0 3178 up_write(&esw->mode_lock);
7768d197
RD		 3179 return err;
3180}
3181
98fdbea5
LR		 3182int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3183 enum devlink_eswitch_encap_mode *encap)
7768d197 3184{
bd939753 3185 struct mlx5_eswitch *esw;
9d1cef19 3186 int err;
7768d197 3187
bd939753
PP		 3188 esw = mlx5_devlink_eswitch_get(devlink);
3189 if (IS_ERR(esw))
3190 return PTR_ERR(esw);
3191
7768d197 3192
c55479d0 3193 down_write(&esw->mode_lock);
ae24432c
PP		 3194 err = eswitch_devlink_esw_mode_check(esw);
3195 if (err)
8e0aa4bc 3196 goto unlock;
ae24432c 3197
7768d197 3198 *encap = esw->offloads.encap;
8e0aa4bc 3199unlock:
c55479d0 3200 up_write(&esw->mode_lock);
7768d197
RD		 3201 return 0;
3202}
3203
c2d7712c
BW		 3204static bool
3205mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3206{
3207 /* Currently, only ECPF based device has representor for host PF. */
3208 if (vport_num == MLX5_VPORT_PF &&
3209 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3210 return false;
3211
3212 if (vport_num == MLX5_VPORT_ECPF &&
3213 !mlx5_ecpf_vport_exists(esw->dev))
3214 return false;
3215
3216 return true;
3217}
3218
f8e8fa02 3219void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 3220 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 3221 u8 rep_type)
127ea380 3222{
8693115a 3223 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 3224 struct mlx5_eswitch_rep *rep;
47dd7e60 3225 unsigned long i;
9deb2241 3226
8693115a 3227 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 3228 mlx5_esw_for_each_rep(esw, i, rep) {
3229 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 3230 rep->esw = esw;
c2d7712c
BW		 3231 rep_data = &rep->rep_data[rep_type];
3232 atomic_set(&rep_data->state, REP_REGISTERED);
3233 }
f8e8fa02 3234 }
127ea380 3235}
f8e8fa02 3236EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 3237
f8e8fa02 3238void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 3239{
cb67b832 3240 struct mlx5_eswitch_rep *rep;
47dd7e60 3241 unsigned long i;
cb67b832 3242
f6455de0 3243 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 3244 __unload_reps_all_vport(esw, rep_type);
127ea380 3245
47dd7e60 3246 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 3247 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 3248}
f8e8fa02 3249EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 3250
a4b97ab4 3251void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 3252{
726293f1
HHZ		 3253 struct mlx5_eswitch_rep *rep;
3254
879c8f84 3255 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 3256 return rep->rep_data[rep_type].priv;
726293f1 3257}
22215908
MB		 3258
3259void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 3260 u16 vport,
22215908
MB		 3261 u8 rep_type)
3262{
22215908
MB		 3263 struct mlx5_eswitch_rep *rep;
3264
879c8f84 3265 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 3266
8693115a
PP		 3267 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3268 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3269 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 3270 return NULL;
3271}
57cbd893 3272EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 3273
3274void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3275{
879c8f84 3276 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 3277}
57cbd893
MB		 3278EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3279
3280struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 3281 u16 vport)
57cbd893 3282{
879c8f84 3283 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 3284}
3285EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 3286
5b7cb745
PB		 3287bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3288{
3289 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3290}
3291EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3292
7445cfb1
JL		 3293bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3294{
3295 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3296}
3297EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3298
0f0d3827 3299u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 3300 u16 vport_num)
3301{
133dcfc5 3302 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 3303
133dcfc5
VP		 3304 if (WARN_ON_ONCE(IS_ERR(vport)))
3305 return 0;
0f0d3827 3306
133dcfc5 3307 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 3308}
3309EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 3310
3311int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 3312 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 3313{
3314 int err;
3315
3316 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3317 if (err)
3318 return err;
3319
f1b9acd3 3320 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 3321 if (err)
3322 goto devlink_err;
3323
3324 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3325 if (err)
3326 goto rep_err;
3327 return 0;
3328
3329rep_err:
3330 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3331devlink_err:
3332 mlx5_esw_vport_disable(esw, vport_num);
3333 return err;
3334}
3335
3336void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3337{
3338 mlx5_esw_offloads_rep_unload(esw, vport_num);
3339 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3340 mlx5_esw_vport_disable(esw, vport_num);
3341}
84ae9c1f
VB		 3342
3343static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3344{
3345 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3346 void *query_ctx;
3347 void *hca_caps;
3348 int err;
3349
3350 *vhca_id = 0;
3351 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3352 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3353 return -EPERM;
3354
3355 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3356 if (!query_ctx)
3357 return -ENOMEM;
3358
3359 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx);
3360 if (err)
3361 goto out_free;
3362
3363 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3364 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3365
3366out_free:
3367 kfree(query_ctx);
3368 return err;
3369}
3370
3371int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3372{
3373 u16 *old_entry, *vhca_map_entry, vhca_id;
3374 int err;
3375
3376 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3377 if (err) {
3378 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3379 vport_num, err);
3380 return err;
3381 }
3382
3383 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3384 if (!vhca_map_entry)
3385 return -ENOMEM;
3386
3387 *vhca_map_entry = vport_num;
3388 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3389 if (xa_is_err(old_entry)) {
3390 kfree(vhca_map_entry);
3391 return xa_err(old_entry);
3392 }
3393 kfree(old_entry);
3394 return 0;
3395}
3396
3397void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3398{
3399 u16 *vhca_map_entry, vhca_id;
3400 int err;
3401
3402 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3403 if (err)
3404 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3405 vport_num, err);
3406
3407 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3408 kfree(vhca_map_entry);
3409}
3410
3411int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3412{
3413 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3414
3415 if (!res)
3416 return -ENOENT;
3417
3418 *vport_num = *res;
3419 return 0;
3420}
10742efc
VB		 3421
3422u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3423 u16 vport_num)
3424{
3425 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3426
3427 if (WARN_ON_ONCE(IS_ERR(vport)))
3428 return 0;
3429
3430 return vport->metadata;
3431}
3432EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
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