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net/mlx5: Report EQE data upon CQ completion
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / fpga / conn.c
CommitLineData
537a5057
IT		 1/*
2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <net/addrconf.h>
35#include <linux/etherdevice.h>
36#include <linux/mlx5/vport.h>
37
38#include "mlx5_core.h"
39#include "lib/mlx5.h"
40#include "fpga/conn.h"
41
42#define MLX5_FPGA_PKEY 0xFFFF
43#define MLX5_FPGA_PKEY_INDEX 0 /* RoCE PKEY 0xFFFF is always at index 0 */
44#define MLX5_FPGA_RECV_SIZE 2048
45#define MLX5_FPGA_PORT_NUM 1
46#define MLX5_FPGA_CQ_BUDGET 64
47
48static int mlx5_fpga_conn_map_buf(struct mlx5_fpga_conn *conn,
49 struct mlx5_fpga_dma_buf *buf)
50{
51 struct device *dma_device;
52 int err = 0;
53
54 if (unlikely(!buf->sg[0].data))
55 goto out;
56
57 dma_device = &conn->fdev->mdev->pdev->dev;
58 buf->sg[0].dma_addr = dma_map_single(dma_device, buf->sg[0].data,
59 buf->sg[0].size, buf->dma_dir);
60 err = dma_mapping_error(dma_device, buf->sg[0].dma_addr);
61 if (unlikely(err)) {
62 mlx5_fpga_warn(conn->fdev, "DMA error on sg 0: %d\n", err);
63 err = -ENOMEM;
64 goto out;
65 }
66
67 if (!buf->sg[1].data)
68 goto out;
69
70 buf->sg[1].dma_addr = dma_map_single(dma_device, buf->sg[1].data,
71 buf->sg[1].size, buf->dma_dir);
72 err = dma_mapping_error(dma_device, buf->sg[1].dma_addr);
73 if (unlikely(err)) {
74 mlx5_fpga_warn(conn->fdev, "DMA error on sg 1: %d\n", err);
75 dma_unmap_single(dma_device, buf->sg[0].dma_addr,
76 buf->sg[0].size, buf->dma_dir);
77 err = -ENOMEM;
78 }
79
80out:
81 return err;
82}
83
84static void mlx5_fpga_conn_unmap_buf(struct mlx5_fpga_conn *conn,
85 struct mlx5_fpga_dma_buf *buf)
86{
87 struct device *dma_device;
88
89 dma_device = &conn->fdev->mdev->pdev->dev;
90 if (buf->sg[1].data)
91 dma_unmap_single(dma_device, buf->sg[1].dma_addr,
92 buf->sg[1].size, buf->dma_dir);
93
94 if (likely(buf->sg[0].data))
95 dma_unmap_single(dma_device, buf->sg[0].dma_addr,
96 buf->sg[0].size, buf->dma_dir);
97}
98
99static int mlx5_fpga_conn_post_recv(struct mlx5_fpga_conn *conn,
100 struct mlx5_fpga_dma_buf *buf)
101{
102 struct mlx5_wqe_data_seg *data;
103 unsigned int ix;
104 int err = 0;
105
106 err = mlx5_fpga_conn_map_buf(conn, buf);
107 if (unlikely(err))
108 goto out;
109
110 if (unlikely(conn->qp.rq.pc - conn->qp.rq.cc >= conn->qp.rq.size)) {
111 mlx5_fpga_conn_unmap_buf(conn, buf);
112 return -EBUSY;
113 }
114
115 ix = conn->qp.rq.pc & (conn->qp.rq.size - 1);
116 data = mlx5_wq_cyc_get_wqe(&conn->qp.wq.rq, ix);
117 data->byte_count = cpu_to_be32(buf->sg[0].size);
118 data->lkey = cpu_to_be32(conn->fdev->conn_res.mkey.key);
119 data->addr = cpu_to_be64(buf->sg[0].dma_addr);
120
121 conn->qp.rq.pc++;
122 conn->qp.rq.bufs[ix] = buf;
123
124 /* Make sure that descriptors are written before doorbell record. */
125 dma_wmb();
126 *conn->qp.wq.rq.db = cpu_to_be32(conn->qp.rq.pc & 0xffff);
127out:
128 return err;
129}
130
131static void mlx5_fpga_conn_notify_hw(struct mlx5_fpga_conn *conn, void *wqe)
132{
133 /* ensure wqe is visible to device before updating doorbell record */
134 dma_wmb();
135 *conn->qp.wq.sq.db = cpu_to_be32(conn->qp.sq.pc);
136 /* Make sure that doorbell record is visible before ringing */
137 wmb();
bbf29f61 138 mlx5_write64(wqe, conn->fdev->conn_res.uar->map + MLX5_BF_OFFSET);
537a5057
IT		 139}
140
141static void mlx5_fpga_conn_post_send(struct mlx5_fpga_conn *conn,
142 struct mlx5_fpga_dma_buf *buf)
143{
144 struct mlx5_wqe_ctrl_seg *ctrl;
145 struct mlx5_wqe_data_seg *data;
146 unsigned int ix, sgi;
147 int size = 1;
148
149 ix = conn->qp.sq.pc & (conn->qp.sq.size - 1);
150
151 ctrl = mlx5_wq_cyc_get_wqe(&conn->qp.wq.sq, ix);
152 data = (void *)(ctrl + 1);
153
154 for (sgi = 0; sgi < ARRAY_SIZE(buf->sg); sgi++) {
155 if (!buf->sg[sgi].data)
156 break;
157 data->byte_count = cpu_to_be32(buf->sg[sgi].size);
158 data->lkey = cpu_to_be32(conn->fdev->conn_res.mkey.key);
159 data->addr = cpu_to_be64(buf->sg[sgi].dma_addr);
160 data++;
161 size++;
162 }
163
164 ctrl->imm = 0;
165 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
166 ctrl->opmod_idx_opcode = cpu_to_be32(((conn->qp.sq.pc & 0xffff) << 8) |
167 MLX5_OPCODE_SEND);
168 ctrl->qpn_ds = cpu_to_be32(size | (conn->qp.mqp.qpn << 8));
169
170 conn->qp.sq.pc++;
171 conn->qp.sq.bufs[ix] = buf;
172 mlx5_fpga_conn_notify_hw(conn, ctrl);
173}
174
175int mlx5_fpga_conn_send(struct mlx5_fpga_conn *conn,
176 struct mlx5_fpga_dma_buf *buf)
177{
178 unsigned long flags;
179 int err;
180
181 if (!conn->qp.active)
182 return -ENOTCONN;
183
ba869ee0 184 buf->dma_dir = DMA_TO_DEVICE;
537a5057
IT		 185 err = mlx5_fpga_conn_map_buf(conn, buf);
186 if (err)
187 return err;
188
189 spin_lock_irqsave(&conn->qp.sq.lock, flags);
190
191 if (conn->qp.sq.pc - conn->qp.sq.cc >= conn->qp.sq.size) {
192 list_add_tail(&buf->list, &conn->qp.sq.backlog);
193 goto out_unlock;
194 }
195
196 mlx5_fpga_conn_post_send(conn, buf);
197
198out_unlock:
199 spin_unlock_irqrestore(&conn->qp.sq.lock, flags);
200 return err;
201}
202
203static int mlx5_fpga_conn_post_recv_buf(struct mlx5_fpga_conn *conn)
204{
205 struct mlx5_fpga_dma_buf *buf;
206 int err;
207
208 buf = kzalloc(sizeof(*buf) + MLX5_FPGA_RECV_SIZE, 0);
209 if (!buf)
210 return -ENOMEM;
211
212 buf->sg[0].data = (void *)(buf + 1);
213 buf->sg[0].size = MLX5_FPGA_RECV_SIZE;
214 buf->dma_dir = DMA_FROM_DEVICE;
215
216 err = mlx5_fpga_conn_post_recv(conn, buf);
217 if (err)
218 kfree(buf);
219
220 return err;
221}
222
223static int mlx5_fpga_conn_create_mkey(struct mlx5_core_dev *mdev, u32 pdn,
224 struct mlx5_core_mkey *mkey)
225{
226 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
227 void *mkc;
228 u32 *in;
229 int err;
230
231 in = kvzalloc(inlen, GFP_KERNEL);
232 if (!in)
233 return -ENOMEM;
234
235 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
cdbd0d2b 236 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
537a5057
IT		 237 MLX5_SET(mkc, mkc, lw, 1);
238 MLX5_SET(mkc, mkc, lr, 1);
239
240 MLX5_SET(mkc, mkc, pd, pdn);
241 MLX5_SET(mkc, mkc, length64, 1);
242 MLX5_SET(mkc, mkc, qpn, 0xffffff);
243
244 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
245
246 kvfree(in);
247 return err;
248}
249
250static void mlx5_fpga_conn_rq_cqe(struct mlx5_fpga_conn *conn,
251 struct mlx5_cqe64 *cqe, u8 status)
252{
253 struct mlx5_fpga_dma_buf *buf;
254 int ix, err;
255
256 ix = be16_to_cpu(cqe->wqe_counter) & (conn->qp.rq.size - 1);
257 buf = conn->qp.rq.bufs[ix];
258 conn->qp.rq.bufs[ix] = NULL;
537a5057
IT		 259 conn->qp.rq.cc++;
260
261 if (unlikely(status && (status != MLX5_CQE_SYNDROME_WR_FLUSH_ERR)))
262 mlx5_fpga_warn(conn->fdev, "RQ buf %p on FPGA QP %u completion status %d\n",
263 buf, conn->fpga_qpn, status);
264 else
265 mlx5_fpga_dbg(conn->fdev, "RQ buf %p on FPGA QP %u completion status %d\n",
266 buf, conn->fpga_qpn, status);
267
268 mlx5_fpga_conn_unmap_buf(conn, buf);
269
270 if (unlikely(status || !conn->qp.active)) {
271 conn->qp.active = false;
272 kfree(buf);
273 return;
274 }
275
36dd4902 276 buf->sg[0].size = be32_to_cpu(cqe->byte_cnt);
537a5057
IT		 277 mlx5_fpga_dbg(conn->fdev, "Message with %u bytes received successfully\n",
278 buf->sg[0].size);
279 conn->recv_cb(conn->cb_arg, buf);
280
281 buf->sg[0].size = MLX5_FPGA_RECV_SIZE;
282 err = mlx5_fpga_conn_post_recv(conn, buf);
283 if (unlikely(err)) {
284 mlx5_fpga_warn(conn->fdev,
285 "Failed to re-post recv buf: %d\n", err);
286 kfree(buf);
287 }
288}
289
290static void mlx5_fpga_conn_sq_cqe(struct mlx5_fpga_conn *conn,
291 struct mlx5_cqe64 *cqe, u8 status)
292{
293 struct mlx5_fpga_dma_buf *buf, *nextbuf;
294 unsigned long flags;
295 int ix;
296
297 spin_lock_irqsave(&conn->qp.sq.lock, flags);
298
299 ix = be16_to_cpu(cqe->wqe_counter) & (conn->qp.sq.size - 1);
300 buf = conn->qp.sq.bufs[ix];
301 conn->qp.sq.bufs[ix] = NULL;
302 conn->qp.sq.cc++;
303
304 /* Handle backlog still under the spinlock to ensure message post order */
305 if (unlikely(!list_empty(&conn->qp.sq.backlog))) {
306 if (likely(conn->qp.active)) {
307 nextbuf = list_first_entry(&conn->qp.sq.backlog,
308 struct mlx5_fpga_dma_buf, list);
309 list_del(&nextbuf->list);
310 mlx5_fpga_conn_post_send(conn, nextbuf);
311 }
312 }
313
314 spin_unlock_irqrestore(&conn->qp.sq.lock, flags);
315
316 if (unlikely(status && (status != MLX5_CQE_SYNDROME_WR_FLUSH_ERR)))
317 mlx5_fpga_warn(conn->fdev, "SQ buf %p on FPGA QP %u completion status %d\n",
318 buf, conn->fpga_qpn, status);
319 else
320 mlx5_fpga_dbg(conn->fdev, "SQ buf %p on FPGA QP %u completion status %d\n",
321 buf, conn->fpga_qpn, status);
322
323 mlx5_fpga_conn_unmap_buf(conn, buf);
324
325 if (likely(buf->complete))
326 buf->complete(conn, conn->fdev, buf, status);
327
328 if (unlikely(status))
329 conn->qp.active = false;
330}
331
332static void mlx5_fpga_conn_handle_cqe(struct mlx5_fpga_conn *conn,
333 struct mlx5_cqe64 *cqe)
334{
335 u8 opcode, status = 0;
336
6254adeb 337 opcode = get_cqe_opcode(cqe);
537a5057
IT		 338
339 switch (opcode) {
340 case MLX5_CQE_REQ_ERR:
341 status = ((struct mlx5_err_cqe *)cqe)->syndrome;
342 /* Fall through */
343 case MLX5_CQE_REQ:
344 mlx5_fpga_conn_sq_cqe(conn, cqe, status);
345 break;
346
347 case MLX5_CQE_RESP_ERR:
348 status = ((struct mlx5_err_cqe *)cqe)->syndrome;
349 /* Fall through */
350 case MLX5_CQE_RESP_SEND:
351 mlx5_fpga_conn_rq_cqe(conn, cqe, status);
352 break;
353 default:
354 mlx5_fpga_warn(conn->fdev, "Unexpected cqe opcode %u\n",
355 opcode);
356 }
357}
358
359static void mlx5_fpga_conn_arm_cq(struct mlx5_fpga_conn *conn)
360{
361 mlx5_cq_arm(&conn->cq.mcq, MLX5_CQ_DB_REQ_NOT,
362 conn->fdev->conn_res.uar->map, conn->cq.wq.cc);
363}
364
365static void mlx5_fpga_conn_cq_event(struct mlx5_core_cq *mcq,
366 enum mlx5_event event)
367{
368 struct mlx5_fpga_conn *conn;
369
370 conn = container_of(mcq, struct mlx5_fpga_conn, cq.mcq);
371 mlx5_fpga_warn(conn->fdev, "CQ event %u on CQ #%u\n", event, mcq->cqn);
372}
373
374static void mlx5_fpga_conn_event(struct mlx5_core_qp *mqp, int event)
375{
376 struct mlx5_fpga_conn *conn;
377
378 conn = container_of(mqp, struct mlx5_fpga_conn, qp.mqp);
379 mlx5_fpga_warn(conn->fdev, "QP event %u on QP #%u\n", event, mqp->qpn);
380}
381
382static inline void mlx5_fpga_conn_cqes(struct mlx5_fpga_conn *conn,
383 unsigned int budget)
384{
385 struct mlx5_cqe64 *cqe;
386
387 while (budget) {
388 cqe = mlx5_cqwq_get_cqe(&conn->cq.wq);
389 if (!cqe)
390 break;
391
392 budget--;
393 mlx5_cqwq_pop(&conn->cq.wq);
394 mlx5_fpga_conn_handle_cqe(conn, cqe);
395 mlx5_cqwq_update_db_record(&conn->cq.wq);
396 }
397 if (!budget) {
398 tasklet_schedule(&conn->cq.tasklet);
399 return;
400 }
401
402 mlx5_fpga_dbg(conn->fdev, "Re-arming CQ with cc# %u\n", conn->cq.wq.cc);
403 /* ensure cq space is freed before enabling more cqes */
404 wmb();
405 mlx5_fpga_conn_arm_cq(conn);
406}
407
408static void mlx5_fpga_conn_cq_tasklet(unsigned long data)
409{
410 struct mlx5_fpga_conn *conn = (void *)data;
411
412 if (unlikely(!conn->qp.active))
413 return;
414 mlx5_fpga_conn_cqes(conn, MLX5_FPGA_CQ_BUDGET);
415}
416
4e0e2ea1
YH		 417static void mlx5_fpga_conn_cq_complete(struct mlx5_core_cq *mcq,
418 struct mlx5_eqe *eqe)
537a5057
IT		 419{
420 struct mlx5_fpga_conn *conn;
421
422 conn = container_of(mcq, struct mlx5_fpga_conn, cq.mcq);
423 if (unlikely(!conn->qp.active))
424 return;
425 mlx5_fpga_conn_cqes(conn, MLX5_FPGA_CQ_BUDGET);
426}
427
428static int mlx5_fpga_conn_create_cq(struct mlx5_fpga_conn *conn, int cq_size)
429{
430 struct mlx5_fpga_device *fdev = conn->fdev;
431 struct mlx5_core_dev *mdev = fdev->mdev;
432 u32 temp_cqc[MLX5_ST_SZ_DW(cqc)] = {0};
38164b77 433 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
537a5057
IT		 434 struct mlx5_wq_param wqp;
435 struct mlx5_cqe64 *cqe;
436 int inlen, err, eqn;
437 unsigned int irqn;
438 void *cqc, *in;
439 __be64 *pas;
440 u32 i;
441
442 cq_size = roundup_pow_of_two(cq_size);
443 MLX5_SET(cqc, temp_cqc, log_cq_size, ilog2(cq_size));
444
445 wqp.buf_numa_node = mdev->priv.numa_node;
446 wqp.db_numa_node = mdev->priv.numa_node;
447
448 err = mlx5_cqwq_create(mdev, &wqp, temp_cqc, &conn->cq.wq,
449 &conn->cq.wq_ctrl);
450 if (err)
451 return err;
452
453 for (i = 0; i < mlx5_cqwq_get_size(&conn->cq.wq); i++) {
454 cqe = mlx5_cqwq_get_wqe(&conn->cq.wq, i);
455 cqe->op_own = MLX5_CQE_INVALID << 4 | MLX5_CQE_OWNER_MASK;
456 }
457
458 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
3a2f7033 459 sizeof(u64) * conn->cq.wq_ctrl.buf.npages;
537a5057
IT		 460 in = kvzalloc(inlen, GFP_KERNEL);
461 if (!in) {
462 err = -ENOMEM;
463 goto err_cqwq;
464 }
465
466 err = mlx5_vector2eqn(mdev, smp_processor_id(), &eqn, &irqn);
467 if (err)
468 goto err_cqwq;
469
470 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
471 MLX5_SET(cqc, cqc, log_cq_size, ilog2(cq_size));
472 MLX5_SET(cqc, cqc, c_eqn, eqn);
473 MLX5_SET(cqc, cqc, uar_page, fdev->conn_res.uar->index);
3a2f7033 474 MLX5_SET(cqc, cqc, log_page_size, conn->cq.wq_ctrl.buf.page_shift -
537a5057
IT		 475 MLX5_ADAPTER_PAGE_SHIFT);
476 MLX5_SET64(cqc, cqc, dbr_addr, conn->cq.wq_ctrl.db.dma);
477
478 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas);
3a2f7033 479 mlx5_fill_page_frag_array(&conn->cq.wq_ctrl.buf, pas);
537a5057 480
38164b77 481 err = mlx5_core_create_cq(mdev, &conn->cq.mcq, in, inlen, out, sizeof(out));
537a5057
IT		 482 kvfree(in);
483
484 if (err)
485 goto err_cqwq;
486
487 conn->cq.mcq.cqe_sz = 64;
488 conn->cq.mcq.set_ci_db = conn->cq.wq_ctrl.db.db;
489 conn->cq.mcq.arm_db = conn->cq.wq_ctrl.db.db + 1;
490 *conn->cq.mcq.set_ci_db = 0;
491 *conn->cq.mcq.arm_db = 0;
492 conn->cq.mcq.vector = 0;
493 conn->cq.mcq.comp = mlx5_fpga_conn_cq_complete;
494 conn->cq.mcq.event = mlx5_fpga_conn_cq_event;
495 conn->cq.mcq.irqn = irqn;
496 conn->cq.mcq.uar = fdev->conn_res.uar;
497 tasklet_init(&conn->cq.tasklet, mlx5_fpga_conn_cq_tasklet,
498 (unsigned long)conn);
499
500 mlx5_fpga_dbg(fdev, "Created CQ #0x%x\n", conn->cq.mcq.cqn);
501
502 goto out;
503
504err_cqwq:
3a2f7033 505 mlx5_wq_destroy(&conn->cq.wq_ctrl);
537a5057
IT		 506out:
507 return err;
508}
509
510static void mlx5_fpga_conn_destroy_cq(struct mlx5_fpga_conn *conn)
511{
512 tasklet_disable(&conn->cq.tasklet);
513 tasklet_kill(&conn->cq.tasklet);
514 mlx5_core_destroy_cq(conn->fdev->mdev, &conn->cq.mcq);
3a2f7033 515 mlx5_wq_destroy(&conn->cq.wq_ctrl);
537a5057
IT		 516}
517
518static int mlx5_fpga_conn_create_wq(struct mlx5_fpga_conn *conn, void *qpc)
519{
520 struct mlx5_fpga_device *fdev = conn->fdev;
521 struct mlx5_core_dev *mdev = fdev->mdev;
522 struct mlx5_wq_param wqp;
523
524 wqp.buf_numa_node = mdev->priv.numa_node;
525 wqp.db_numa_node = mdev->priv.numa_node;
526
527 return mlx5_wq_qp_create(mdev, &wqp, qpc, &conn->qp.wq,
528 &conn->qp.wq_ctrl);
529}
530
531static int mlx5_fpga_conn_create_qp(struct mlx5_fpga_conn *conn,
532 unsigned int tx_size, unsigned int rx_size)
533{
534 struct mlx5_fpga_device *fdev = conn->fdev;
535 struct mlx5_core_dev *mdev = fdev->mdev;
536 u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {0};
537 void *in = NULL, *qpc;
538 int err, inlen;
539
540 conn->qp.rq.pc = 0;
541 conn->qp.rq.cc = 0;
542 conn->qp.rq.size = roundup_pow_of_two(rx_size);
543 conn->qp.sq.pc = 0;
544 conn->qp.sq.cc = 0;
545 conn->qp.sq.size = roundup_pow_of_two(tx_size);
546
547 MLX5_SET(qpc, temp_qpc, log_rq_stride, ilog2(MLX5_SEND_WQE_DS) - 4);
548 MLX5_SET(qpc, temp_qpc, log_rq_size, ilog2(conn->qp.rq.size));
549 MLX5_SET(qpc, temp_qpc, log_sq_size, ilog2(conn->qp.sq.size));
550 err = mlx5_fpga_conn_create_wq(conn, temp_qpc);
551 if (err)
552 goto out;
553
778e1cdd
KC		 554 conn->qp.rq.bufs = kvcalloc(conn->qp.rq.size,
555 sizeof(conn->qp.rq.bufs[0]),
556 GFP_KERNEL);
537a5057
IT		 557 if (!conn->qp.rq.bufs) {
558 err = -ENOMEM;
559 goto err_wq;
560 }
561
778e1cdd
KC		 562 conn->qp.sq.bufs = kvcalloc(conn->qp.sq.size,
563 sizeof(conn->qp.sq.bufs[0]),
564 GFP_KERNEL);
537a5057
IT		 565 if (!conn->qp.sq.bufs) {
566 err = -ENOMEM;
567 goto err_rq_bufs;
568 }
569
570 inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
571 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) *
572 conn->qp.wq_ctrl.buf.npages;
573 in = kvzalloc(inlen, GFP_KERNEL);
574 if (!in) {
575 err = -ENOMEM;
576 goto err_sq_bufs;
577 }
578
579 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
580 MLX5_SET(qpc, qpc, uar_page, fdev->conn_res.uar->index);
581 MLX5_SET(qpc, qpc, log_page_size,
582 conn->qp.wq_ctrl.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
583 MLX5_SET(qpc, qpc, fre, 1);
584 MLX5_SET(qpc, qpc, rlky, 1);
585 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
586 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
587 MLX5_SET(qpc, qpc, pd, fdev->conn_res.pdn);
588 MLX5_SET(qpc, qpc, log_rq_stride, ilog2(MLX5_SEND_WQE_DS) - 4);
589 MLX5_SET(qpc, qpc, log_rq_size, ilog2(conn->qp.rq.size));
590 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
591 MLX5_SET(qpc, qpc, log_sq_size, ilog2(conn->qp.sq.size));
592 MLX5_SET(qpc, qpc, cqn_snd, conn->cq.mcq.cqn);
593 MLX5_SET(qpc, qpc, cqn_rcv, conn->cq.mcq.cqn);
594 MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma);
595 if (MLX5_CAP_GEN(mdev, cqe_version) == 1)
596 MLX5_SET(qpc, qpc, user_index, 0xFFFFFF);
597
3a2f7033
TT		 598 mlx5_fill_page_frag_array(&conn->qp.wq_ctrl.buf,
599 (__be64 *)MLX5_ADDR_OF(create_qp_in, in, pas));
537a5057
IT		 600
601 err = mlx5_core_create_qp(mdev, &conn->qp.mqp, in, inlen);
602 if (err)
603 goto err_sq_bufs;
604
605 conn->qp.mqp.event = mlx5_fpga_conn_event;
606 mlx5_fpga_dbg(fdev, "Created QP #0x%x\n", conn->qp.mqp.qpn);
607
608 goto out;
609
610err_sq_bufs:
611 kvfree(conn->qp.sq.bufs);
612err_rq_bufs:
613 kvfree(conn->qp.rq.bufs);
614err_wq:
615 mlx5_wq_destroy(&conn->qp.wq_ctrl);
616out:
617 kvfree(in);
618 return err;
619}
620
621static void mlx5_fpga_conn_free_recv_bufs(struct mlx5_fpga_conn *conn)
622{
623 int ix;
624
625 for (ix = 0; ix < conn->qp.rq.size; ix++) {
626 if (!conn->qp.rq.bufs[ix])
627 continue;
628 mlx5_fpga_conn_unmap_buf(conn, conn->qp.rq.bufs[ix]);
629 kfree(conn->qp.rq.bufs[ix]);
630 conn->qp.rq.bufs[ix] = NULL;
631 }
632}
633
634static void mlx5_fpga_conn_flush_send_bufs(struct mlx5_fpga_conn *conn)
635{
636 struct mlx5_fpga_dma_buf *buf, *temp;
637 int ix;
638
639 for (ix = 0; ix < conn->qp.sq.size; ix++) {
640 buf = conn->qp.sq.bufs[ix];
641 if (!buf)
642 continue;
643 conn->qp.sq.bufs[ix] = NULL;
644 mlx5_fpga_conn_unmap_buf(conn, buf);
645 if (!buf->complete)
646 continue;
647 buf->complete(conn, conn->fdev, buf, MLX5_CQE_SYNDROME_WR_FLUSH_ERR);
648 }
649 list_for_each_entry_safe(buf, temp, &conn->qp.sq.backlog, list) {
650 mlx5_fpga_conn_unmap_buf(conn, buf);
651 if (!buf->complete)
652 continue;
653 buf->complete(conn, conn->fdev, buf, MLX5_CQE_SYNDROME_WR_FLUSH_ERR);
654 }
655}
656
657static void mlx5_fpga_conn_destroy_qp(struct mlx5_fpga_conn *conn)
658{
659 mlx5_core_destroy_qp(conn->fdev->mdev, &conn->qp.mqp);
660 mlx5_fpga_conn_free_recv_bufs(conn);
661 mlx5_fpga_conn_flush_send_bufs(conn);
662 kvfree(conn->qp.sq.bufs);
663 kvfree(conn->qp.rq.bufs);
664 mlx5_wq_destroy(&conn->qp.wq_ctrl);
665}
666
667static inline int mlx5_fpga_conn_reset_qp(struct mlx5_fpga_conn *conn)
668{
669 struct mlx5_core_dev *mdev = conn->fdev->mdev;
670
671 mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to RST\n", conn->qp.mqp.qpn);
672
673 return mlx5_core_qp_modify(mdev, MLX5_CMD_OP_2RST_QP, 0, NULL,
674 &conn->qp.mqp);
675}
676
677static inline int mlx5_fpga_conn_init_qp(struct mlx5_fpga_conn *conn)
678{
679 struct mlx5_fpga_device *fdev = conn->fdev;
680 struct mlx5_core_dev *mdev = fdev->mdev;
681 u32 *qpc = NULL;
682 int err;
683
684 mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to INIT\n", conn->qp.mqp.qpn);
685
686 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
687 if (!qpc) {
688 err = -ENOMEM;
689 goto out;
690 }
691
692 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
693 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
694 MLX5_SET(qpc, qpc, primary_address_path.pkey_index, MLX5_FPGA_PKEY_INDEX);
32f69e4b 695 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, MLX5_FPGA_PORT_NUM);
537a5057
IT		 696 MLX5_SET(qpc, qpc, pd, conn->fdev->conn_res.pdn);
697 MLX5_SET(qpc, qpc, cqn_snd, conn->cq.mcq.cqn);
698 MLX5_SET(qpc, qpc, cqn_rcv, conn->cq.mcq.cqn);
699 MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma);
700
701 err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_RST2INIT_QP, 0, qpc,
702 &conn->qp.mqp);
703 if (err) {
704 mlx5_fpga_warn(fdev, "qp_modify RST2INIT failed: %d\n", err);
705 goto out;
706 }
707
708out:
709 kfree(qpc);
710 return err;
711}
712
713static inline int mlx5_fpga_conn_rtr_qp(struct mlx5_fpga_conn *conn)
714{
715 struct mlx5_fpga_device *fdev = conn->fdev;
716 struct mlx5_core_dev *mdev = fdev->mdev;
717 u32 *qpc = NULL;
718 int err;
719
720 mlx5_fpga_dbg(conn->fdev, "QP RTR\n");
721
722 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
723 if (!qpc) {
724 err = -ENOMEM;
725 goto out;
726 }
727
728 MLX5_SET(qpc, qpc, mtu, MLX5_QPC_MTU_1K_BYTES);
729 MLX5_SET(qpc, qpc, log_msg_max, (u8)MLX5_CAP_GEN(mdev, log_max_msg));
730 MLX5_SET(qpc, qpc, remote_qpn, conn->fpga_qpn);
731 MLX5_SET(qpc, qpc, next_rcv_psn,
732 MLX5_GET(fpga_qpc, conn->fpga_qpc, next_send_psn));
733 MLX5_SET(qpc, qpc, primary_address_path.pkey_index, MLX5_FPGA_PKEY_INDEX);
32f69e4b 734 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, MLX5_FPGA_PORT_NUM);
537a5057
IT		 735 ether_addr_copy(MLX5_ADDR_OF(qpc, qpc, primary_address_path.rmac_47_32),
736 MLX5_ADDR_OF(fpga_qpc, conn->fpga_qpc, fpga_mac_47_32));
737 MLX5_SET(qpc, qpc, primary_address_path.udp_sport,
738 MLX5_CAP_ROCE(mdev, r_roce_min_src_udp_port));
739 MLX5_SET(qpc, qpc, primary_address_path.src_addr_index,
740 conn->qp.sgid_index);
741 MLX5_SET(qpc, qpc, primary_address_path.hop_limit, 0);
742 memcpy(MLX5_ADDR_OF(qpc, qpc, primary_address_path.rgid_rip),
743 MLX5_ADDR_OF(fpga_qpc, conn->fpga_qpc, fpga_ip),
744 MLX5_FLD_SZ_BYTES(qpc, primary_address_path.rgid_rip));
745
746 err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_INIT2RTR_QP, 0, qpc,
747 &conn->qp.mqp);
748 if (err) {
749 mlx5_fpga_warn(fdev, "qp_modify RST2INIT failed: %d\n", err);
750 goto out;
751 }
752
753out:
754 kfree(qpc);
755 return err;
756}
757
758static inline int mlx5_fpga_conn_rts_qp(struct mlx5_fpga_conn *conn)
759{
760 struct mlx5_fpga_device *fdev = conn->fdev;
761 struct mlx5_core_dev *mdev = fdev->mdev;
762 u32 *qpc = NULL;
763 u32 opt_mask;
764 int err;
765
766 mlx5_fpga_dbg(conn->fdev, "QP RTS\n");
767
768 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
769 if (!qpc) {
770 err = -ENOMEM;
771 goto out;
772 }
773
774 MLX5_SET(qpc, qpc, log_ack_req_freq, 8);
775 MLX5_SET(qpc, qpc, min_rnr_nak, 0x12);
776 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 0x12); /* ~1.07s */
777 MLX5_SET(qpc, qpc, next_send_psn,
778 MLX5_GET(fpga_qpc, conn->fpga_qpc, next_rcv_psn));
779 MLX5_SET(qpc, qpc, retry_count, 7);
780 MLX5_SET(qpc, qpc, rnr_retry, 7); /* Infinite retry if RNR NACK */
781
782 opt_mask = MLX5_QP_OPTPAR_RNR_TIMEOUT;
783 err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_RTR2RTS_QP, opt_mask, qpc,
784 &conn->qp.mqp);
785 if (err) {
786 mlx5_fpga_warn(fdev, "qp_modify RST2INIT failed: %d\n", err);
787 goto out;
788 }
789
790out:
791 kfree(qpc);
792 return err;
793}
794
795static int mlx5_fpga_conn_connect(struct mlx5_fpga_conn *conn)
796{
797 struct mlx5_fpga_device *fdev = conn->fdev;
798 int err;
799
800 MLX5_SET(fpga_qpc, conn->fpga_qpc, state, MLX5_FPGA_QPC_STATE_ACTIVE);
801 err = mlx5_fpga_modify_qp(conn->fdev->mdev, conn->fpga_qpn,
802 MLX5_FPGA_QPC_STATE, &conn->fpga_qpc);
803 if (err) {
804 mlx5_fpga_err(fdev, "Failed to activate FPGA RC QP: %d\n", err);
805 goto out;
806 }
807
808 err = mlx5_fpga_conn_reset_qp(conn);
809 if (err) {
810 mlx5_fpga_err(fdev, "Failed to change QP state to reset\n");
811 goto err_fpga_qp;
812 }
813
814 err = mlx5_fpga_conn_init_qp(conn);
815 if (err) {
816 mlx5_fpga_err(fdev, "Failed to modify QP from RESET to INIT\n");
817 goto err_fpga_qp;
818 }
819 conn->qp.active = true;
820
821 while (!mlx5_fpga_conn_post_recv_buf(conn))
822 ;
823
824 err = mlx5_fpga_conn_rtr_qp(conn);
825 if (err) {
826 mlx5_fpga_err(fdev, "Failed to change QP state from INIT to RTR\n");
827 goto err_recv_bufs;
828 }
829
830 err = mlx5_fpga_conn_rts_qp(conn);
831 if (err) {
832 mlx5_fpga_err(fdev, "Failed to change QP state from RTR to RTS\n");
833 goto err_recv_bufs;
834 }
835 goto out;
836
837err_recv_bufs:
838 mlx5_fpga_conn_free_recv_bufs(conn);
839err_fpga_qp:
840 MLX5_SET(fpga_qpc, conn->fpga_qpc, state, MLX5_FPGA_QPC_STATE_INIT);
841 if (mlx5_fpga_modify_qp(conn->fdev->mdev, conn->fpga_qpn,
842 MLX5_FPGA_QPC_STATE, &conn->fpga_qpc))
843 mlx5_fpga_err(fdev, "Failed to revert FPGA QP to INIT\n");
844out:
845 return err;
846}
847
848struct mlx5_fpga_conn *mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev,
849 struct mlx5_fpga_conn_attr *attr,
850 enum mlx5_ifc_fpga_qp_type qp_type)
851{
852 struct mlx5_fpga_conn *ret, *conn;
853 u8 *remote_mac, *remote_ip;
854 int err;
855
856 if (!attr->recv_cb)
857 return ERR_PTR(-EINVAL);
858
859 conn = kzalloc(sizeof(*conn), GFP_KERNEL);
860 if (!conn)
861 return ERR_PTR(-ENOMEM);
862
863 conn->fdev = fdev;
864 INIT_LIST_HEAD(&conn->qp.sq.backlog);
865
866 spin_lock_init(&conn->qp.sq.lock);
867
868 conn->recv_cb = attr->recv_cb;
869 conn->cb_arg = attr->cb_arg;
870
871 remote_mac = MLX5_ADDR_OF(fpga_qpc, conn->fpga_qpc, remote_mac_47_32);
e1d974d0 872 err = mlx5_query_mac_address(fdev->mdev, remote_mac);
537a5057
IT		 873 if (err) {
874 mlx5_fpga_err(fdev, "Failed to query local MAC: %d\n", err);
875 ret = ERR_PTR(err);
876 goto err;
877 }
878
879 /* Build Modified EUI-64 IPv6 address from the MAC address */
880 remote_ip = MLX5_ADDR_OF(fpga_qpc, conn->fpga_qpc, remote_ip);
881 remote_ip[0] = 0xfe;
882 remote_ip[1] = 0x80;
883 addrconf_addr_eui48(&remote_ip[8], remote_mac);
884
885 err = mlx5_core_reserved_gid_alloc(fdev->mdev, &conn->qp.sgid_index);
886 if (err) {
887 mlx5_fpga_err(fdev, "Failed to allocate SGID: %d\n", err);
888 ret = ERR_PTR(err);
889 goto err;
890 }
891
892 err = mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index,
893 MLX5_ROCE_VERSION_2,
894 MLX5_ROCE_L3_TYPE_IPV6,
cfe4e37f
DJ		 895 remote_ip, remote_mac, true, 0,
896 MLX5_FPGA_PORT_NUM);
537a5057
IT		 897 if (err) {
898 mlx5_fpga_err(fdev, "Failed to set SGID: %d\n", err);
899 ret = ERR_PTR(err);
900 goto err_rsvd_gid;
901 }
902 mlx5_fpga_dbg(fdev, "Reserved SGID index %u\n", conn->qp.sgid_index);
903
904 /* Allow for one cqe per rx/tx wqe, plus one cqe for the next wqe,
905 * created during processing of the cqe
906 */
907 err = mlx5_fpga_conn_create_cq(conn,
908 (attr->tx_size + attr->rx_size) * 2);
909 if (err) {
910 mlx5_fpga_err(fdev, "Failed to create CQ: %d\n", err);
911 ret = ERR_PTR(err);
912 goto err_gid;
913 }
914
915 mlx5_fpga_conn_arm_cq(conn);
916
917 err = mlx5_fpga_conn_create_qp(conn, attr->tx_size, attr->rx_size);
918 if (err) {
919 mlx5_fpga_err(fdev, "Failed to create QP: %d\n", err);
920 ret = ERR_PTR(err);
921 goto err_cq;
922 }
923
924 MLX5_SET(fpga_qpc, conn->fpga_qpc, state, MLX5_FPGA_QPC_STATE_INIT);
925 MLX5_SET(fpga_qpc, conn->fpga_qpc, qp_type, qp_type);
926 MLX5_SET(fpga_qpc, conn->fpga_qpc, st, MLX5_FPGA_QPC_ST_RC);
927 MLX5_SET(fpga_qpc, conn->fpga_qpc, ether_type, ETH_P_8021Q);
928 MLX5_SET(fpga_qpc, conn->fpga_qpc, vid, 0);
929 MLX5_SET(fpga_qpc, conn->fpga_qpc, next_rcv_psn, 1);
930 MLX5_SET(fpga_qpc, conn->fpga_qpc, next_send_psn, 0);
931 MLX5_SET(fpga_qpc, conn->fpga_qpc, pkey, MLX5_FPGA_PKEY);
932 MLX5_SET(fpga_qpc, conn->fpga_qpc, remote_qpn, conn->qp.mqp.qpn);
933 MLX5_SET(fpga_qpc, conn->fpga_qpc, rnr_retry, 7);
934 MLX5_SET(fpga_qpc, conn->fpga_qpc, retry_count, 7);
935
936 err = mlx5_fpga_create_qp(fdev->mdev, &conn->fpga_qpc,
937 &conn->fpga_qpn);
938 if (err) {
939 mlx5_fpga_err(fdev, "Failed to create FPGA RC QP: %d\n", err);
940 ret = ERR_PTR(err);
941 goto err_qp;
942 }
943
944 err = mlx5_fpga_conn_connect(conn);
945 if (err) {
946 ret = ERR_PTR(err);
947 goto err_conn;
948 }
949
950 mlx5_fpga_dbg(fdev, "FPGA QPN is %u\n", conn->fpga_qpn);
951 ret = conn;
952 goto out;
953
954err_conn:
955 mlx5_fpga_destroy_qp(conn->fdev->mdev, conn->fpga_qpn);
956err_qp:
957 mlx5_fpga_conn_destroy_qp(conn);
958err_cq:
959 mlx5_fpga_conn_destroy_cq(conn);
960err_gid:
961 mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index, 0, 0, NULL,
cfe4e37f 962 NULL, false, 0, MLX5_FPGA_PORT_NUM);
537a5057
IT		 963err_rsvd_gid:
964 mlx5_core_reserved_gid_free(fdev->mdev, conn->qp.sgid_index);
965err:
966 kfree(conn);
967out:
968 return ret;
969}
970
971void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn)
972{
973 struct mlx5_fpga_device *fdev = conn->fdev;
974 struct mlx5_core_dev *mdev = fdev->mdev;
975 int err = 0;
976
977 conn->qp.active = false;
978 tasklet_disable(&conn->cq.tasklet);
979 synchronize_irq(conn->cq.mcq.irqn);
980
981 mlx5_fpga_destroy_qp(conn->fdev->mdev, conn->fpga_qpn);
982 err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_2ERR_QP, 0, NULL,
983 &conn->qp.mqp);
984 if (err)
985 mlx5_fpga_warn(fdev, "qp_modify 2ERR failed: %d\n", err);
986 mlx5_fpga_conn_destroy_qp(conn);
987 mlx5_fpga_conn_destroy_cq(conn);
988
989 mlx5_core_roce_gid_set(conn->fdev->mdev, conn->qp.sgid_index, 0, 0,
cfe4e37f 990 NULL, NULL, false, 0, MLX5_FPGA_PORT_NUM);
537a5057
IT		 991 mlx5_core_reserved_gid_free(conn->fdev->mdev, conn->qp.sgid_index);
992 kfree(conn);
993}
994
995int mlx5_fpga_conn_device_init(struct mlx5_fpga_device *fdev)
996{
997 int err;
998
999 err = mlx5_nic_vport_enable_roce(fdev->mdev);
1000 if (err) {
1001 mlx5_fpga_err(fdev, "Failed to enable RoCE: %d\n", err);
1002 goto out;
1003 }
1004
1005 fdev->conn_res.uar = mlx5_get_uars_page(fdev->mdev);
1006 if (IS_ERR(fdev->conn_res.uar)) {
1007 err = PTR_ERR(fdev->conn_res.uar);
1008 mlx5_fpga_err(fdev, "get_uars_page failed, %d\n", err);
1009 goto err_roce;
1010 }
1011 mlx5_fpga_dbg(fdev, "Allocated UAR index %u\n",
1012 fdev->conn_res.uar->index);
1013
1014 err = mlx5_core_alloc_pd(fdev->mdev, &fdev->conn_res.pdn);
1015 if (err) {
1016 mlx5_fpga_err(fdev, "alloc pd failed, %d\n", err);
1017 goto err_uar;
1018 }
1019 mlx5_fpga_dbg(fdev, "Allocated PD %u\n", fdev->conn_res.pdn);
1020
1021 err = mlx5_fpga_conn_create_mkey(fdev->mdev, fdev->conn_res.pdn,
1022 &fdev->conn_res.mkey);
1023 if (err) {
1024 mlx5_fpga_err(fdev, "create mkey failed, %d\n", err);
1025 goto err_dealloc_pd;
1026 }
1027 mlx5_fpga_dbg(fdev, "Created mkey 0x%x\n", fdev->conn_res.mkey.key);
1028
1029 return 0;
1030
1031err_dealloc_pd:
1032 mlx5_core_dealloc_pd(fdev->mdev, fdev->conn_res.pdn);
1033err_uar:
1034 mlx5_put_uars_page(fdev->mdev, fdev->conn_res.uar);
1035err_roce:
1036 mlx5_nic_vport_disable_roce(fdev->mdev);
1037out:
1038 return err;
1039}
1040
1041void mlx5_fpga_conn_device_cleanup(struct mlx5_fpga_device *fdev)
1042{
1043 mlx5_core_destroy_mkey(fdev->mdev, &fdev->conn_res.mkey);
1044 mlx5_core_dealloc_pd(fdev->mdev, fdev->conn_res.pdn);
1045 mlx5_put_uars_page(fdev->mdev, fdev->conn_res.uar);
1046 mlx5_nic_vport_disable_roce(fdev->mdev);
1047}
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