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net/mlx5e: Fix wrong indications in DIM due to counter wraparound
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
b775516b 49#include <linux/mlx5/mlx5_ifc.h>
5a7b27eb
MG		 50#ifdef CONFIG_RFS_ACCEL
51#include <linux/cpu_rmap.h>
52#endif
feae9087 53#include <net/devlink.h>
e126ba97 54#include "mlx5_core.h"
86d722ad 55#include "fs_core.h"
073bb189
SM		 56#ifdef CONFIG_MLX5_CORE_EN
57#include "eswitch.h"
58#endif
e126ba97 59
e126ba97 60MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 61MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 62MODULE_LICENSE("Dual BSD/GPL");
63MODULE_VERSION(DRIVER_VERSION);
64
f663ad98
KH		 65unsigned int mlx5_core_debug_mask;
66module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
e126ba97
EC		 67MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
68
9603b61d 69#define MLX5_DEFAULT_PROF 2
f663ad98
KH		 70static unsigned int prof_sel = MLX5_DEFAULT_PROF;
71module_param_named(prof_sel, prof_sel, uint, 0444);
9603b61d
JM		 72MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
73
f91e6d89
EBE		 74enum {
75 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
76 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
77};
78
9603b61d
JM		 79static struct mlx5_profile profile[] = {
80 [0] = {
81 .mask = 0,
82 },
83 [1] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .log_max_qp = 12,
86 },
87 [2] = {
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
5f40b4ed 90 .log_max_qp = 18,
9603b61d
JM		 91 .mr_cache[0] = {
92 .size = 500,
93 .limit = 250
94 },
95 .mr_cache[1] = {
96 .size = 500,
97 .limit = 250
98 },
99 .mr_cache[2] = {
100 .size = 500,
101 .limit = 250
102 },
103 .mr_cache[3] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[4] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[5] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[6] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[7] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[8] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[9] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[10] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[11] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[12] = {
140 .size = 64,
141 .limit = 32
142 },
143 .mr_cache[13] = {
144 .size = 32,
145 .limit = 16
146 },
147 .mr_cache[14] = {
148 .size = 16,
149 .limit = 8
150 },
151 .mr_cache[15] = {
152 .size = 8,
153 .limit = 4
154 },
7d0cc6ed
AK		 155 .mr_cache[16] = {
156 .size = 8,
157 .limit = 4
158 },
159 .mr_cache[17] = {
160 .size = 8,
161 .limit = 4
162 },
163 .mr_cache[18] = {
164 .size = 8,
165 .limit = 4
166 },
167 .mr_cache[19] = {
168 .size = 4,
169 .limit = 2
170 },
171 .mr_cache[20] = {
172 .size = 4,
173 .limit = 2
174 },
9603b61d
JM		 175 },
176};
e126ba97 177
e3297246
EC		 178#define FW_INIT_TIMEOUT_MILI 2000
179#define FW_INIT_WAIT_MS 2
180
181static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
182{
183 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
184 int err = 0;
185
186 while (fw_initializing(dev)) {
187 if (time_after(jiffies, end)) {
188 err = -EBUSY;
189 break;
190 }
191 msleep(FW_INIT_WAIT_MS);
192 }
193
194 return err;
195}
196
012e50e1
HN		 197static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
198{
199 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
200 driver_version);
201 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
202 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
203 int remaining_size = driver_ver_sz;
204 char *string;
205
206 if (!MLX5_CAP_GEN(dev, driver_version))
207 return;
208
209 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
210
211 strncpy(string, "Linux", remaining_size);
212
213 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
214 strncat(string, ",", remaining_size);
215
216 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
217 strncat(string, DRIVER_NAME, remaining_size);
218
219 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
220 strncat(string, ",", remaining_size);
221
222 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
223 strncat(string, DRIVER_VERSION, remaining_size);
224
225 /*Send the command*/
226 MLX5_SET(set_driver_version_in, in, opcode,
227 MLX5_CMD_OP_SET_DRIVER_VERSION);
228
229 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
230}
231
e126ba97
EC		 232static int set_dma_caps(struct pci_dev *pdev)
233{
234 int err;
235
236 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
237 if (err) {
1a91de28 238 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 239 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
240 if (err) {
1a91de28 241 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 242 return err;
243 }
244 }
245
246 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
247 if (err) {
248 dev_warn(&pdev->dev,
1a91de28 249 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 250 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
251 if (err) {
252 dev_err(&pdev->dev,
1a91de28 253 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 254 return err;
255 }
256 }
257
258 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
259 return err;
260}
261
89d44f0a
MD		 262static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
263{
264 struct pci_dev *pdev = dev->pdev;
265 int err = 0;
266
267 mutex_lock(&dev->pci_status_mutex);
268 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
269 err = pci_enable_device(pdev);
270 if (!err)
271 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
272 }
273 mutex_unlock(&dev->pci_status_mutex);
274
275 return err;
276}
277
278static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
279{
280 struct pci_dev *pdev = dev->pdev;
281
282 mutex_lock(&dev->pci_status_mutex);
283 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
284 pci_disable_device(pdev);
285 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
286 }
287 mutex_unlock(&dev->pci_status_mutex);
288}
289
e126ba97
EC		 290static int request_bar(struct pci_dev *pdev)
291{
292 int err = 0;
293
294 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 295 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 296 return -ENODEV;
297 }
298
299 err = pci_request_regions(pdev, DRIVER_NAME);
300 if (err)
301 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
302
303 return err;
304}
305
306static void release_bar(struct pci_dev *pdev)
307{
308 pci_release_regions(pdev);
309}
310
311static int mlx5_enable_msix(struct mlx5_core_dev *dev)
312{
db058a18
SM		 313 struct mlx5_priv *priv = &dev->priv;
314 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 315 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 316 int nvec;
e126ba97
EC		 317 int i;
318
938fe83c
SM		 319 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
320 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 321 nvec = min_t(int, nvec, num_eqs);
322 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
323 return -ENOMEM;
324
db058a18
SM		 325 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
326
327 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
328 if (!priv->msix_arr || !priv->irq_info)
329 goto err_free_msix;
e126ba97
EC		 330
331 for (i = 0; i < nvec; i++)
db058a18 332 priv->msix_arr[i].entry = i;
e126ba97 333
db058a18 334 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 335 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 336 if (nvec < 0)
337 return nvec;
e126ba97 338
f3c9407b 339 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 340
341 return 0;
db058a18
SM		 342
343err_free_msix:
344 kfree(priv->irq_info);
345 kfree(priv->msix_arr);
346 return -ENOMEM;
e126ba97
EC		 347}
348
349static void mlx5_disable_msix(struct mlx5_core_dev *dev)
350{
db058a18 351 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 352
353 pci_disable_msix(dev->pdev);
db058a18
SM		 354 kfree(priv->irq_info);
355 kfree(priv->msix_arr);
e126ba97
EC		 356}
357
358struct mlx5_reg_host_endianess {
359 u8 he;
360 u8 rsvd[15];
361};
362
87b8de49
EC		 363
364#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
365
366enum {
c7a08ac7
EC		 367 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
368 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 369};
370
2974ab6e 371static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
c7a08ac7
EC		 372{
373 switch (size) {
374 case 128:
375 return 0;
376 case 256:
377 return 1;
378 case 512:
379 return 2;
380 case 1024:
381 return 3;
382 case 2048:
383 return 4;
384 case 4096:
385 return 5;
386 default:
2974ab6e 387 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
c7a08ac7
EC		 388 return 0;
389 }
390}
391
b06e7de8
LR		 392static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
393 enum mlx5_cap_type cap_type,
394 enum mlx5_cap_mode cap_mode)
c7a08ac7 395{
b775516b
EC		 396 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
397 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 398 void *out, *hca_caps;
399 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 400 int err;
401
b775516b
EC		 402 memset(in, 0, sizeof(in));
403 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 404 if (!out)
e126ba97 405 return -ENOMEM;
938fe83c 406
b775516b
EC		 407 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
408 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
409 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
c7a08ac7 410 if (err) {
938fe83c
SM		 411 mlx5_core_warn(dev,
412 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
413 cap_type, cap_mode, err);
e126ba97
EC		 414 goto query_ex;
415 }
c7a08ac7 416
938fe83c
SM		 417 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
418
419 switch (cap_mode) {
420 case HCA_CAP_OPMOD_GET_MAX:
701052c5 421 memcpy(dev->caps.hca_max[cap_type], hca_caps,
938fe83c
SM		 422 MLX5_UN_SZ_BYTES(hca_cap_union));
423 break;
424 case HCA_CAP_OPMOD_GET_CUR:
701052c5 425 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
938fe83c
SM		 426 MLX5_UN_SZ_BYTES(hca_cap_union));
427 break;
428 default:
429 mlx5_core_warn(dev,
430 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
431 cap_type, cap_mode);
432 err = -EINVAL;
433 break;
434 }
c7a08ac7
EC		 435query_ex:
436 kfree(out);
437 return err;
438}
439
b06e7de8
LR		 440int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
441{
442 int ret;
443
444 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
445 if (ret)
446 return ret;
447 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
448}
449
f91e6d89 450static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 451{
c4f287c4 452 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
e126ba97 453
b775516b 454 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 455 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
c4f287c4 456 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
c7a08ac7
EC		 457}
458
f91e6d89
EBE		 459static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
460{
461 void *set_ctx;
462 void *set_hca_cap;
463 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
464 int req_endianness;
465 int err;
466
467 if (MLX5_CAP_GEN(dev, atomic)) {
b06e7de8 468 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
f91e6d89
EBE		 469 if (err)
470 return err;
471 } else {
472 return 0;
473 }
474
475 req_endianness =
476 MLX5_CAP_ATOMIC(dev,
477 supported_atomic_req_8B_endianess_mode_1);
478
479 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
480 return 0;
481
482 set_ctx = kzalloc(set_sz, GFP_KERNEL);
483 if (!set_ctx)
484 return -ENOMEM;
485
486 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
487
488 /* Set requestor to host endianness */
489 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
490 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
491
492 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
493
494 kfree(set_ctx);
495 return err;
496}
497
c7a08ac7
EC		 498static int handle_hca_cap(struct mlx5_core_dev *dev)
499{
b775516b 500 void *set_ctx = NULL;
c7a08ac7 501 struct mlx5_profile *prof = dev->profile;
c7a08ac7 502 int err = -ENOMEM;
b775516b 503 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 504 void *set_hca_cap;
c7a08ac7 505
b775516b 506 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 507 if (!set_ctx)
e126ba97 508 goto query_ex;
e126ba97 509
b06e7de8 510 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
e126ba97
EC		 511 if (err)
512 goto query_ex;
513
938fe83c
SM		 514 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
515 capability);
701052c5 516 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
938fe83c
SM		 517 MLX5_ST_SZ_BYTES(cmd_hca_cap));
518
519 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 520 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 521 128);
c7a08ac7 522 /* we limit the size of the pkey table to 128 entries for now */
938fe83c 523 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
2974ab6e 524 to_fw_pkey_sz(dev, 128));
c7a08ac7 525
883371c4
NO		 526 /* Check log_max_qp from HCA caps to set in current profile */
527 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
528 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
529 profile[prof_sel].log_max_qp,
530 MLX5_CAP_GEN_MAX(dev, log_max_qp));
531 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
532 }
c7a08ac7 533 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 534 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
535 prof->log_max_qp);
c7a08ac7 536
938fe83c
SM		 537 /* disable cmdif checksum */
538 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 539
f502d834
EC		 540 /* If the HCA supports 4K UARs use it */
541 if (MLX5_CAP_GEN_MAX(dev, uar_4k))
542 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
543
fe1e1876
CS		 544 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
545
f32f5bd2
DJ		 546 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
547 MLX5_SET(cmd_hca_cap,
548 set_hca_cap,
549 cache_line_128byte,
550 cache_line_size() == 128 ? 1 : 0);
551
f91e6d89
EBE		 552 err = set_caps(dev, set_ctx, set_sz,
553 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 554
e126ba97 555query_ex:
e126ba97 556 kfree(set_ctx);
e126ba97
EC		 557 return err;
558}
559
560static int set_hca_ctrl(struct mlx5_core_dev *dev)
561{
562 struct mlx5_reg_host_endianess he_in;
563 struct mlx5_reg_host_endianess he_out;
564 int err;
565
fc50db98
EC		 566 if (!mlx5_core_is_pf(dev))
567 return 0;
568
e126ba97
EC		 569 memset(&he_in, 0, sizeof(he_in));
570 he_in.he = MLX5_SET_HOST_ENDIANNESS;
571 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
572 &he_out, sizeof(he_out),
573 MLX5_REG_HOST_ENDIANNESS, 0, 1);
574 return err;
575}
576
0b107106 577int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 578{
c4f287c4
SM		 579 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
580 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
cd23b14b 581
0b107106
EC		 582 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
583 MLX5_SET(enable_hca_in, in, function_id, func_id);
c4f287c4 584 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
cd23b14b
EC		 585}
586
0b107106 587int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 588{
c4f287c4
SM		 589 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
590 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
cd23b14b 591
0b107106
EC		 592 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
593 MLX5_SET(disable_hca_in, in, function_id, func_id);
c4f287c4 594 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
cd23b14b
EC		 595}
596
a5a1d1c2 597u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
b0844444
EBE		 598{
599 u32 timer_h, timer_h1, timer_l;
600
601 timer_h = ioread32be(&dev->iseg->internal_timer_h);
602 timer_l = ioread32be(&dev->iseg->internal_timer_l);
603 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
604 if (timer_h != timer_h1) /* wrap around */
605 timer_l = ioread32be(&dev->iseg->internal_timer_l);
606
a5a1d1c2 607 return (u64)timer_l | (u64)timer_h1 << 32;
b0844444
EBE		 608}
609
db058a18
SM		 610static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
611{
612 struct mlx5_priv *priv = &mdev->priv;
613 struct msix_entry *msix = priv->msix_arr;
614 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
db058a18
SM		 615
616 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
617 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
618 return -ENOMEM;
619 }
620
d151d73d 621 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
dda922c8 622 priv->irq_info[i].mask);
db058a18 623
f0d7ae95
AB		 624 if (IS_ENABLED(CONFIG_SMP) &&
625 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
b665d98e 626 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
db058a18
SM		 627
628 return 0;
db058a18
SM		 629}
630
631static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
632{
633 struct mlx5_priv *priv = &mdev->priv;
634 struct msix_entry *msix = priv->msix_arr;
635 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
636
637 irq_set_affinity_hint(irq, NULL);
638 free_cpumask_var(priv->irq_info[i].mask);
639}
640
641static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
642{
643 int err;
644 int i;
645
646 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
647 err = mlx5_irq_set_affinity_hint(mdev, i);
648 if (err)
649 goto err_out;
650 }
651
652 return 0;
653
654err_out:
655 for (i--; i >= 0; i--)
656 mlx5_irq_clear_affinity_hint(mdev, i);
657
658 return err;
659}
660
661static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
662{
663 int i;
664
665 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
666 mlx5_irq_clear_affinity_hint(mdev, i);
667}
668
0b6e26ce
DT		 669int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
670 unsigned int *irqn)
233d05d2
SM		 671{
672 struct mlx5_eq_table *table = &dev->priv.eq_table;
673 struct mlx5_eq *eq, *n;
674 int err = -ENOENT;
675
676 spin_lock(&table->lock);
677 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
678 if (eq->index == vector) {
679 *eqn = eq->eqn;
680 *irqn = eq->irqn;
681 err = 0;
682 break;
683 }
684 }
685 spin_unlock(&table->lock);
686
687 return err;
688}
689EXPORT_SYMBOL(mlx5_vector2eqn);
690
94c6825e
MB		 691struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
692{
693 struct mlx5_eq_table *table = &dev->priv.eq_table;
694 struct mlx5_eq *eq;
695
696 spin_lock(&table->lock);
697 list_for_each_entry(eq, &table->comp_eqs_list, list)
698 if (eq->eqn == eqn) {
699 spin_unlock(&table->lock);
700 return eq;
701 }
702
703 spin_unlock(&table->lock);
704
705 return ERR_PTR(-ENOENT);
706}
707
233d05d2
SM		 708static void free_comp_eqs(struct mlx5_core_dev *dev)
709{
710 struct mlx5_eq_table *table = &dev->priv.eq_table;
711 struct mlx5_eq *eq, *n;
712
5a7b27eb
MG		 713#ifdef CONFIG_RFS_ACCEL
714 if (dev->rmap) {
715 free_irq_cpu_rmap(dev->rmap);
716 dev->rmap = NULL;
717 }
718#endif
233d05d2
SM		 719 spin_lock(&table->lock);
720 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
721 list_del(&eq->list);
722 spin_unlock(&table->lock);
723 if (mlx5_destroy_unmap_eq(dev, eq))
724 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
725 eq->eqn);
726 kfree(eq);
727 spin_lock(&table->lock);
728 }
729 spin_unlock(&table->lock);
730}
731
732static int alloc_comp_eqs(struct mlx5_core_dev *dev)
733{
734 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 735 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 736 struct mlx5_eq *eq;
737 int ncomp_vec;
738 int nent;
739 int err;
740 int i;
741
742 INIT_LIST_HEAD(&table->comp_eqs_list);
743 ncomp_vec = table->num_comp_vectors;
744 nent = MLX5_COMP_EQ_SIZE;
5a7b27eb
MG		 745#ifdef CONFIG_RFS_ACCEL
746 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
747 if (!dev->rmap)
748 return -ENOMEM;
749#endif
233d05d2
SM		 750 for (i = 0; i < ncomp_vec; i++) {
751 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
752 if (!eq) {
753 err = -ENOMEM;
754 goto clean;
755 }
756
5a7b27eb
MG		 757#ifdef CONFIG_RFS_ACCEL
758 irq_cpu_rmap_add(dev->rmap,
759 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
760#endif
db058a18 761 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 762 err = mlx5_create_map_eq(dev, eq,
763 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
01187175 764 name, MLX5_EQ_TYPE_COMP);
233d05d2
SM		 765 if (err) {
766 kfree(eq);
767 goto clean;
768 }
769 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
770 eq->index = i;
771 spin_lock(&table->lock);
772 list_add_tail(&eq->list, &table->comp_eqs_list);
773 spin_unlock(&table->lock);
774 }
775
776 return 0;
777
778clean:
779 free_comp_eqs(dev);
780 return err;
781}
782
f62b8bb8
AV		 783static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
784{
c4f287c4
SM		 785 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
786 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
f62b8bb8 787 u32 sup_issi;
c4f287c4 788 int err;
f62b8bb8
AV		 789
790 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
c4f287c4
SM		 791 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
792 query_out, sizeof(query_out));
f62b8bb8 793 if (err) {
c4f287c4
SM		 794 u32 syndrome;
795 u8 status;
796
797 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
f9c14e46
KH		 798 if (!status || syndrome == MLX5_DRIVER_SYND) {
799 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
800 err, status, syndrome);
801 return err;
f62b8bb8
AV		 802 }
803
f9c14e46
KH		 804 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
805 dev->issi = 0;
806 return 0;
f62b8bb8
AV		 807 }
808
809 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
810
811 if (sup_issi & (1 << 1)) {
c4f287c4
SM		 812 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
813 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
f62b8bb8
AV		 814
815 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
816 MLX5_SET(set_issi_in, set_in, current_issi, 1);
c4f287c4
SM		 817 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
818 set_out, sizeof(set_out));
f62b8bb8 819 if (err) {
f9c14e46
KH		 820 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
821 err);
f62b8bb8
AV		 822 return err;
823 }
824
825 dev->issi = 1;
826
827 return 0;
e74a1db0 828 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 829 return 0;
830 }
831
9eb78923 832 return -EOPNOTSUPP;
f62b8bb8 833}
f62b8bb8 834
7907f23a 835
a31208b1
MD		 836static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
837{
838 struct pci_dev *pdev = dev->pdev;
839 int err = 0;
e126ba97 840
e126ba97
EC		 841 pci_set_drvdata(dev->pdev, dev);
842 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
843 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
844
845 mutex_init(&priv->pgdir_mutex);
846 INIT_LIST_HEAD(&priv->pgdir_list);
847 spin_lock_init(&priv->mkey_lock);
848
311c7c71
SM		 849 mutex_init(&priv->alloc_mutex);
850
851 priv->numa_node = dev_to_node(&dev->pdev->dev);
852
e126ba97
EC		 853 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
854 if (!priv->dbg_root)
855 return -ENOMEM;
856
89d44f0a 857 err = mlx5_pci_enable_device(dev);
e126ba97 858 if (err) {
1a91de28 859 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 860 goto err_dbg;
861 }
862
863 err = request_bar(pdev);
864 if (err) {
1a91de28 865 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 866 goto err_disable;
867 }
868
869 pci_set_master(pdev);
870
871 err = set_dma_caps(pdev);
872 if (err) {
873 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
874 goto err_clr_master;
875 }
876
877 dev->iseg_base = pci_resource_start(dev->pdev, 0);
878 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
879 if (!dev->iseg) {
880 err = -ENOMEM;
881 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
882 goto err_clr_master;
883 }
a31208b1
MD		 884
885 return 0;
886
887err_clr_master:
888 pci_clear_master(dev->pdev);
889 release_bar(dev->pdev);
890err_disable:
89d44f0a 891 mlx5_pci_disable_device(dev);
a31208b1
MD		 892
893err_dbg:
894 debugfs_remove(priv->dbg_root);
895 return err;
896}
897
898static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
899{
900 iounmap(dev->iseg);
901 pci_clear_master(dev->pdev);
902 release_bar(dev->pdev);
89d44f0a 903 mlx5_pci_disable_device(dev);
a31208b1
MD		 904 debugfs_remove(priv->dbg_root);
905}
906
59211bd3
MHY		 907static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
908{
909 struct pci_dev *pdev = dev->pdev;
910 int err;
911
59211bd3
MHY		 912 err = mlx5_query_board_id(dev);
913 if (err) {
914 dev_err(&pdev->dev, "query board id failed\n");
915 goto out;
916 }
917
918 err = mlx5_eq_init(dev);
919 if (err) {
920 dev_err(&pdev->dev, "failed to initialize eq\n");
921 goto out;
922 }
923
59211bd3
MHY		 924 err = mlx5_init_cq_table(dev);
925 if (err) {
926 dev_err(&pdev->dev, "failed to initialize cq table\n");
927 goto err_eq_cleanup;
928 }
929
930 mlx5_init_qp_table(dev);
931
932 mlx5_init_srq_table(dev);
933
934 mlx5_init_mkey_table(dev);
935
936 err = mlx5_init_rl_table(dev);
937 if (err) {
938 dev_err(&pdev->dev, "Failed to init rate limiting\n");
939 goto err_tables_cleanup;
940 }
941
c2d6e31a
MHY		 942#ifdef CONFIG_MLX5_CORE_EN
943 err = mlx5_eswitch_init(dev);
944 if (err) {
945 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
946 goto err_rl_cleanup;
947 }
948#endif
949
950 err = mlx5_sriov_init(dev);
951 if (err) {
952 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
953 goto err_eswitch_cleanup;
954 }
955
59211bd3
MHY		 956 return 0;
957
c2d6e31a
MHY		 958err_eswitch_cleanup:
959#ifdef CONFIG_MLX5_CORE_EN
960 mlx5_eswitch_cleanup(dev->priv.eswitch);
961
962err_rl_cleanup:
963#endif
964 mlx5_cleanup_rl_table(dev);
965
59211bd3
MHY		 966err_tables_cleanup:
967 mlx5_cleanup_mkey_table(dev);
968 mlx5_cleanup_srq_table(dev);
969 mlx5_cleanup_qp_table(dev);
970 mlx5_cleanup_cq_table(dev);
971
972err_eq_cleanup:
973 mlx5_eq_cleanup(dev);
974
975out:
976 return err;
977}
978
979static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
980{
c2d6e31a
MHY		 981 mlx5_sriov_cleanup(dev);
982#ifdef CONFIG_MLX5_CORE_EN
983 mlx5_eswitch_cleanup(dev->priv.eswitch);
984#endif
59211bd3
MHY		 985 mlx5_cleanup_rl_table(dev);
986 mlx5_cleanup_mkey_table(dev);
987 mlx5_cleanup_srq_table(dev);
988 mlx5_cleanup_qp_table(dev);
989 mlx5_cleanup_cq_table(dev);
990 mlx5_eq_cleanup(dev);
991}
992
993static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
994 bool boot)
a31208b1
MD		 995{
996 struct pci_dev *pdev = dev->pdev;
997 int err;
998
89d44f0a 999 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1000 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 1001 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1002 __func__);
1003 goto out;
1004 }
1005
e126ba97
EC		 1006 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1007 fw_rev_min(dev), fw_rev_sub(dev));
1008
89d44f0a
MD		 1009 /* on load removing any previous indication of internal error, device is
1010 * up
1011 */
1012 dev->state = MLX5_DEVICE_STATE_UP;
1013
e126ba97
EC		 1014 err = mlx5_cmd_init(dev);
1015 if (err) {
1016 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 1017 goto out_err;
e126ba97
EC		 1018 }
1019
e3297246
EC		 1020 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1021 if (err) {
1022 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1023 FW_INIT_TIMEOUT_MILI);
55378a23 1024 goto err_cmd_cleanup;
e3297246
EC		 1025 }
1026
0b107106 1027 err = mlx5_core_enable_hca(dev, 0);
cd23b14b
EC		 1028 if (err) {
1029 dev_err(&pdev->dev, "enable hca failed\n");
59211bd3 1030 goto err_cmd_cleanup;
cd23b14b
EC		 1031 }
1032
f62b8bb8
AV		 1033 err = mlx5_core_set_issi(dev);
1034 if (err) {
1035 dev_err(&pdev->dev, "failed to set issi\n");
1036 goto err_disable_hca;
1037 }
f62b8bb8 1038
cd23b14b
EC		 1039 err = mlx5_satisfy_startup_pages(dev, 1);
1040 if (err) {
1041 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1042 goto err_disable_hca;
1043 }
1044
e126ba97
EC		 1045 err = set_hca_ctrl(dev);
1046 if (err) {
1047 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1048 goto reclaim_boot_pages;
e126ba97
EC		 1049 }
1050
1051 err = handle_hca_cap(dev);
1052 if (err) {
1053 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1054 goto reclaim_boot_pages;
e126ba97
EC		 1055 }
1056
f91e6d89
EBE		 1057 err = handle_hca_cap_atomic(dev);
1058 if (err) {
1059 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1060 goto reclaim_boot_pages;
e126ba97
EC		 1061 }
1062
cd23b14b 1063 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1064 if (err) {
cd23b14b
EC		 1065 dev_err(&pdev->dev, "failed to allocate init pages\n");
1066 goto reclaim_boot_pages;
e126ba97
EC		 1067 }
1068
1069 err = mlx5_pagealloc_start(dev);
1070 if (err) {
1071 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1072 goto reclaim_boot_pages;
e126ba97
EC		 1073 }
1074
1075 err = mlx5_cmd_init_hca(dev);
1076 if (err) {
1077 dev_err(&pdev->dev, "init hca failed\n");
1078 goto err_pagealloc_stop;
1079 }
1080
012e50e1
HN		 1081 mlx5_set_driver_version(dev);
1082
e126ba97
EC		 1083 mlx5_start_health_poll(dev);
1084
bba1574c
DJ		 1085 err = mlx5_query_hca_caps(dev);
1086 if (err) {
1087 dev_err(&pdev->dev, "query hca failed\n");
1088 goto err_stop_poll;
1089 }
1090
59211bd3
MHY		 1091 if (boot && mlx5_init_once(dev, priv)) {
1092 dev_err(&pdev->dev, "sw objs init failed\n");
e126ba97
EC		 1093 goto err_stop_poll;
1094 }
1095
1096 err = mlx5_enable_msix(dev);
1097 if (err) {
1098 dev_err(&pdev->dev, "enable msix failed\n");
59211bd3 1099 goto err_cleanup_once;
e126ba97
EC		 1100 }
1101
01187175
EC		 1102 dev->priv.uar = mlx5_get_uars_page(dev);
1103 if (!dev->priv.uar) {
e126ba97 1104 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
59211bd3 1105 goto err_disable_msix;
e126ba97
EC		 1106 }
1107
1108 err = mlx5_start_eqs(dev);
1109 if (err) {
1110 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
5fe9dec0 1111 goto err_put_uars;
e126ba97
EC		 1112 }
1113
233d05d2
SM		 1114 err = alloc_comp_eqs(dev);
1115 if (err) {
1116 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1117 goto err_stop_eqs;
1118 }
1119
db058a18 1120 err = mlx5_irq_set_affinity_hints(dev);
59211bd3 1121 if (err) {
db058a18 1122 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
59211bd3
MHY		 1123 goto err_affinity_hints;
1124 }
e126ba97 1125
86d722ad
MG		 1126 err = mlx5_init_fs(dev);
1127 if (err) {
1128 dev_err(&pdev->dev, "Failed to init flow steering\n");
1129 goto err_fs;
1130 }
1466cc5b 1131
073bb189 1132#ifdef CONFIG_MLX5_CORE_EN
c2d6e31a 1133 mlx5_eswitch_attach(dev->priv.eswitch);
073bb189
SM		 1134#endif
1135
c2d6e31a 1136 err = mlx5_sriov_attach(dev);
fc50db98
EC		 1137 if (err) {
1138 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1139 goto err_sriov;
1140 }
1141
737a234b
MHY		 1142 if (mlx5_device_registered(dev)) {
1143 mlx5_attach_device(dev);
1144 } else {
1145 err = mlx5_register_device(dev);
1146 if (err) {
1147 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1148 goto err_reg_dev;
1149 }
a31208b1
MD		 1150 }
1151
5fc7197d
MD		 1152 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1153 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
89d44f0a
MD		 1154out:
1155 mutex_unlock(&dev->intf_state_mutex);
1156
e126ba97
EC		 1157 return 0;
1158
59211bd3 1159err_reg_dev:
c2d6e31a 1160 mlx5_sriov_detach(dev);
fc50db98 1161
59211bd3 1162err_sriov:
073bb189 1163#ifdef CONFIG_MLX5_CORE_EN
c2d6e31a 1164 mlx5_eswitch_detach(dev->priv.eswitch);
073bb189 1165#endif
86d722ad 1166 mlx5_cleanup_fs(dev);
59211bd3 1167
86d722ad 1168err_fs:
a31208b1 1169 mlx5_irq_clear_affinity_hints(dev);
59211bd3
MHY		 1170
1171err_affinity_hints:
db058a18
SM		 1172 free_comp_eqs(dev);
1173
233d05d2
SM		 1174err_stop_eqs:
1175 mlx5_stop_eqs(dev);
1176
5fe9dec0 1177err_put_uars:
01187175 1178 mlx5_put_uars_page(dev, priv->uar);
e126ba97 1179
59211bd3 1180err_disable_msix:
e126ba97
EC		 1181 mlx5_disable_msix(dev);
1182
59211bd3
MHY		 1183err_cleanup_once:
1184 if (boot)
1185 mlx5_cleanup_once(dev);
1186
e126ba97
EC		 1187err_stop_poll:
1188 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1189 if (mlx5_cmd_teardown_hca(dev)) {
1190 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1191 goto out_err;
1bde6e30 1192 }
e126ba97
EC		 1193
1194err_pagealloc_stop:
1195 mlx5_pagealloc_stop(dev);
1196
cd23b14b 1197reclaim_boot_pages:
e126ba97
EC		 1198 mlx5_reclaim_startup_pages(dev);
1199
cd23b14b 1200err_disable_hca:
0b107106 1201 mlx5_core_disable_hca(dev, 0);
cd23b14b 1202
59211bd3 1203err_cmd_cleanup:
e126ba97
EC		 1204 mlx5_cmd_cleanup(dev);
1205
89d44f0a
MD		 1206out_err:
1207 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1208 mutex_unlock(&dev->intf_state_mutex);
1209
e126ba97
EC		 1210 return err;
1211}
e126ba97 1212
59211bd3
MHY		 1213static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1214 bool cleanup)
e126ba97 1215{
89d44f0a 1216 int err = 0;
e126ba97 1217
5e44fca5
DJ		 1218 if (cleanup)
1219 mlx5_drain_health_wq(dev);
689a248d 1220
89d44f0a 1221 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1222 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
89d44f0a
MD		 1223 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1224 __func__);
59211bd3
MHY		 1225 if (cleanup)
1226 mlx5_cleanup_once(dev);
89d44f0a
MD		 1227 goto out;
1228 }
6b6adee3 1229
737a234b
MHY		 1230 if (mlx5_device_registered(dev))
1231 mlx5_detach_device(dev);
1232
c2d6e31a 1233 mlx5_sriov_detach(dev);
073bb189 1234#ifdef CONFIG_MLX5_CORE_EN
c2d6e31a 1235 mlx5_eswitch_detach(dev->priv.eswitch);
073bb189 1236#endif
86d722ad 1237 mlx5_cleanup_fs(dev);
db058a18 1238 mlx5_irq_clear_affinity_hints(dev);
233d05d2 1239 free_comp_eqs(dev);
e126ba97 1240 mlx5_stop_eqs(dev);
01187175 1241 mlx5_put_uars_page(dev, priv->uar);
e126ba97 1242 mlx5_disable_msix(dev);
59211bd3
MHY		 1243 if (cleanup)
1244 mlx5_cleanup_once(dev);
e126ba97 1245 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1246 err = mlx5_cmd_teardown_hca(dev);
1247 if (err) {
1bde6e30 1248 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1249 goto out;
1bde6e30 1250 }
e126ba97
EC		 1251 mlx5_pagealloc_stop(dev);
1252 mlx5_reclaim_startup_pages(dev);
0b107106 1253 mlx5_core_disable_hca(dev, 0);
e126ba97 1254 mlx5_cmd_cleanup(dev);
9603b61d 1255
ac6ea6e8 1256out:
5fc7197d
MD		 1257 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1258 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
89d44f0a 1259 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1260 return err;
9603b61d 1261}
64613d94 1262
9603b61d
JM		 1263struct mlx5_core_event_handler {
1264 void (*event)(struct mlx5_core_dev *dev,
1265 enum mlx5_dev_event event,
1266 void *data);
1267};
1268
feae9087
OG		 1269static const struct devlink_ops mlx5_devlink_ops = {
1270#ifdef CONFIG_MLX5_CORE_EN
1271 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1272 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
bffaa916
RD		 1273 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1274 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
7768d197
RD		 1275 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1276 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
feae9087
OG		 1277#endif
1278};
f66f049f 1279
59211bd3 1280#define MLX5_IB_MOD "mlx5_ib"
9603b61d
JM		 1281static int init_one(struct pci_dev *pdev,
1282 const struct pci_device_id *id)
1283{
1284 struct mlx5_core_dev *dev;
feae9087 1285 struct devlink *devlink;
9603b61d
JM		 1286 struct mlx5_priv *priv;
1287 int err;
1288
feae9087
OG		 1289 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1290 if (!devlink) {
9603b61d
JM		 1291 dev_err(&pdev->dev, "kzalloc failed\n");
1292 return -ENOMEM;
1293 }
feae9087
OG		 1294
1295 dev = devlink_priv(devlink);
9603b61d 1296 priv = &dev->priv;
fc50db98 1297 priv->pci_dev_data = id->driver_data;
9603b61d
JM		 1298
1299 pci_set_drvdata(pdev, dev);
1300
0e97a340
HN		 1301 dev->pdev = pdev;
1302 dev->event = mlx5_core_event;
9603b61d 1303 dev->profile = &profile[prof_sel];
9603b61d 1304
364d1798
EC		 1305 INIT_LIST_HEAD(&priv->ctx_list);
1306 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1307 mutex_init(&dev->pci_status_mutex);
1308 mutex_init(&dev->intf_state_mutex);
d9aaed83
AK		 1309
1310#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1311 err = init_srcu_struct(&priv->pfault_srcu);
1312 if (err) {
1313 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1314 err);
1315 goto clean_dev;
1316 }
1317#endif
01187175
EC		 1318 mutex_init(&priv->bfregs.reg_head.lock);
1319 mutex_init(&priv->bfregs.wc_head.lock);
1320 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1321 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1322
a31208b1 1323 err = mlx5_pci_init(dev, priv);
9603b61d 1324 if (err) {
a31208b1 1325 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
d9aaed83 1326 goto clean_srcu;
9603b61d
JM		 1327 }
1328
ac6ea6e8
EC		 1329 err = mlx5_health_init(dev);
1330 if (err) {
1331 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1332 goto close_pci;
1333 }
1334
59211bd3
MHY		 1335 mlx5_pagealloc_init(dev);
1336
1337 err = mlx5_load_one(dev, priv, true);
9603b61d 1338 if (err) {
a31208b1 1339 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1340 goto clean_health;
9603b61d 1341 }
59211bd3 1342
f82eed45 1343 request_module_nowait(MLX5_IB_MOD);
9603b61d 1344
feae9087
OG		 1345 err = devlink_register(devlink, &pdev->dev);
1346 if (err)
1347 goto clean_load;
1348
5d47f6c8 1349 pci_save_state(pdev);
9603b61d
JM		 1350 return 0;
1351
feae9087 1352clean_load:
59211bd3 1353 mlx5_unload_one(dev, priv, true);
ac6ea6e8 1354clean_health:
59211bd3 1355 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1356 mlx5_health_cleanup(dev);
a31208b1
MD		 1357close_pci:
1358 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1359clean_srcu:
1360#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1361 cleanup_srcu_struct(&priv->pfault_srcu);
a31208b1 1362clean_dev:
d9aaed83 1363#endif
a31208b1 1364 pci_set_drvdata(pdev, NULL);
feae9087 1365 devlink_free(devlink);
a31208b1 1366
9603b61d
JM		 1367 return err;
1368}
a31208b1 1369
9603b61d
JM		 1370static void remove_one(struct pci_dev *pdev)
1371{
1372 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
feae9087 1373 struct devlink *devlink = priv_to_devlink(dev);
a31208b1 1374 struct mlx5_priv *priv = &dev->priv;
9603b61d 1375
feae9087 1376 devlink_unregister(devlink);
737a234b
MHY		 1377 mlx5_unregister_device(dev);
1378
59211bd3 1379 if (mlx5_unload_one(dev, priv, true)) {
a31208b1 1380 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1381 mlx5_health_cleanup(dev);
a31208b1
MD		 1382 return;
1383 }
737a234b 1384
59211bd3 1385 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1386 mlx5_health_cleanup(dev);
a31208b1 1387 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1388#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1389 cleanup_srcu_struct(&priv->pfault_srcu);
1390#endif
a31208b1 1391 pci_set_drvdata(pdev, NULL);
feae9087 1392 devlink_free(devlink);
9603b61d
JM		 1393}
1394
89d44f0a
MD		 1395static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1396 pci_channel_state_t state)
1397{
1398 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1399 struct mlx5_priv *priv = &dev->priv;
1400
1401 dev_info(&pdev->dev, "%s was called\n", __func__);
04c0c1ab 1402
89d44f0a 1403 mlx5_enter_error_state(dev);
59211bd3 1404 mlx5_unload_one(dev, priv, false);
5d47f6c8 1405 /* In case of kernel call drain the health wq */
05ac2c0b 1406 if (state) {
5e44fca5 1407 mlx5_drain_health_wq(dev);
05ac2c0b
MHY		 1408 mlx5_pci_disable_device(dev);
1409 }
1410
89d44f0a
MD		 1411 return state == pci_channel_io_perm_failure ?
1412 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1413}
1414
d57847dc
DJ		 1415/* wait for the device to show vital signs by waiting
1416 * for the health counter to start counting.
89d44f0a 1417 */
d57847dc 1418static int wait_vital(struct pci_dev *pdev)
89d44f0a
MD		 1419{
1420 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1421 struct mlx5_core_health *health = &dev->priv.health;
1422 const int niter = 100;
d57847dc 1423 u32 last_count = 0;
89d44f0a 1424 u32 count;
89d44f0a
MD		 1425 int i;
1426
89d44f0a
MD		 1427 for (i = 0; i < niter; i++) {
1428 count = ioread32be(health->health_counter);
1429 if (count && count != 0xffffffff) {
d57847dc
DJ		 1430 if (last_count && last_count != count) {
1431 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1432 return 0;
1433 }
1434 last_count = count;
89d44f0a
MD		 1435 }
1436 msleep(50);
1437 }
1438
d57847dc 1439 return -ETIMEDOUT;
89d44f0a
MD		 1440}
1441
1061c90f 1442static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
89d44f0a
MD		 1443{
1444 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
89d44f0a
MD		 1445 int err;
1446
1447 dev_info(&pdev->dev, "%s was called\n", __func__);
1448
1061c90f 1449 err = mlx5_pci_enable_device(dev);
d57847dc 1450 if (err) {
1061c90f
MHY		 1451 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1452 , __func__, err);
1453 return PCI_ERS_RESULT_DISCONNECT;
1454 }
1455
1456 pci_set_master(pdev);
1457 pci_restore_state(pdev);
5d47f6c8 1458 pci_save_state(pdev);
1061c90f
MHY		 1459
1460 if (wait_vital(pdev)) {
d57847dc 1461 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1061c90f 1462 return PCI_ERS_RESULT_DISCONNECT;
d57847dc 1463 }
89d44f0a 1464
1061c90f
MHY		 1465 return PCI_ERS_RESULT_RECOVERED;
1466}
1467
1061c90f
MHY		 1468static void mlx5_pci_resume(struct pci_dev *pdev)
1469{
1470 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1471 struct mlx5_priv *priv = &dev->priv;
1472 int err;
1473
1474 dev_info(&pdev->dev, "%s was called\n", __func__);
1475
59211bd3 1476 err = mlx5_load_one(dev, priv, false);
89d44f0a
MD		 1477 if (err)
1478 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1479 , __func__, err);
1480 else
1481 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1482}
1483
1484static const struct pci_error_handlers mlx5_err_handler = {
1485 .error_detected = mlx5_pci_err_detected,
1486 .slot_reset = mlx5_pci_slot_reset,
1487 .resume = mlx5_pci_resume
1488};
1489
5fc7197d
MD		 1490static void shutdown(struct pci_dev *pdev)
1491{
1492 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1493 struct mlx5_priv *priv = &dev->priv;
1494
1495 dev_info(&pdev->dev, "Shutdown was called\n");
1496 /* Notify mlx5 clients that the kernel is being shut down */
1497 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
59211bd3 1498 mlx5_unload_one(dev, priv, false);
5fc7197d
MD		 1499 mlx5_pci_disable_device(dev);
1500}
1501
9603b61d 1502static const struct pci_device_id mlx5_core_pci_table[] = {
fc50db98
EC		 1503 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1504 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1505 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1506 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1507 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1508 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
7092fe86 1509 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
64dbbdfe 1510 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
d0dd989f
MD		 1511 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1512 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1513 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1514 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
9603b61d
JM		 1515 { 0, }
1516};
1517
1518MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1519
04c0c1ab
MHY		 1520void mlx5_disable_device(struct mlx5_core_dev *dev)
1521{
1522 mlx5_pci_err_detected(dev->pdev, 0);
1523}
1524
1525void mlx5_recover_device(struct mlx5_core_dev *dev)
1526{
1527 mlx5_pci_disable_device(dev);
1528 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1529 mlx5_pci_resume(dev->pdev);
1530}
1531
9603b61d
JM		 1532static struct pci_driver mlx5_core_driver = {
1533 .name = DRIVER_NAME,
1534 .id_table = mlx5_core_pci_table,
1535 .probe = init_one,
89d44f0a 1536 .remove = remove_one,
5fc7197d 1537 .shutdown = shutdown,
fc50db98
EC		 1538 .err_handler = &mlx5_err_handler,
1539 .sriov_configure = mlx5_core_sriov_configure,
9603b61d 1540};
e126ba97 1541
f663ad98
KH		 1542static void mlx5_core_verify_params(void)
1543{
1544 if (prof_sel >= ARRAY_SIZE(profile)) {
1545 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1546 prof_sel,
1547 ARRAY_SIZE(profile) - 1,
1548 MLX5_DEFAULT_PROF);
1549 prof_sel = MLX5_DEFAULT_PROF;
1550 }
1551}
1552
e126ba97
EC		 1553static int __init init(void)
1554{
1555 int err;
1556
f663ad98 1557 mlx5_core_verify_params();
e126ba97 1558 mlx5_register_debugfs();
e126ba97 1559
9603b61d
JM		 1560 err = pci_register_driver(&mlx5_core_driver);
1561 if (err)
ac6ea6e8 1562 goto err_debug;
9603b61d 1563
f62b8bb8
AV		 1564#ifdef CONFIG_MLX5_CORE_EN
1565 mlx5e_init();
1566#endif
1567
e126ba97
EC		 1568 return 0;
1569
e126ba97
EC		 1570err_debug:
1571 mlx5_unregister_debugfs();
1572 return err;
1573}
1574
1575static void __exit cleanup(void)
1576{
f62b8bb8
AV		 1577#ifdef CONFIG_MLX5_CORE_EN
1578 mlx5e_cleanup();
1579#endif
9603b61d 1580 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1581 mlx5_unregister_debugfs();
1582}
1583
1584module_init(init);
1585module_exit(cleanup);
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