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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
b775516b | 49 | #include <linux/mlx5/mlx5_ifc.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
86d722ad | 55 | #include "fs_core.h" |
073bb189 SM |
56 | #ifdef CONFIG_MLX5_CORE_EN |
57 | #include "eswitch.h" | |
58 | #endif | |
e29341fb | 59 | #include "fpga/core.h" |
e126ba97 | 60 | |
e126ba97 | 61 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 62 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
63 | MODULE_LICENSE("Dual BSD/GPL"); |
64 | MODULE_VERSION(DRIVER_VERSION); | |
65 | ||
f663ad98 KH |
66 | unsigned int mlx5_core_debug_mask; |
67 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
68 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
69 | ||
9603b61d | 70 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
71 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
72 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
73 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
74 | ||
f91e6d89 EBE |
75 | enum { |
76 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
77 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
78 | }; | |
79 | ||
9603b61d JM |
80 | static struct mlx5_profile profile[] = { |
81 | [0] = { | |
82 | .mask = 0, | |
83 | }, | |
84 | [1] = { | |
85 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
86 | .log_max_qp = 12, | |
87 | }, | |
88 | [2] = { | |
89 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
90 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 91 | .log_max_qp = 18, |
9603b61d JM |
92 | .mr_cache[0] = { |
93 | .size = 500, | |
94 | .limit = 250 | |
95 | }, | |
96 | .mr_cache[1] = { | |
97 | .size = 500, | |
98 | .limit = 250 | |
99 | }, | |
100 | .mr_cache[2] = { | |
101 | .size = 500, | |
102 | .limit = 250 | |
103 | }, | |
104 | .mr_cache[3] = { | |
105 | .size = 500, | |
106 | .limit = 250 | |
107 | }, | |
108 | .mr_cache[4] = { | |
109 | .size = 500, | |
110 | .limit = 250 | |
111 | }, | |
112 | .mr_cache[5] = { | |
113 | .size = 500, | |
114 | .limit = 250 | |
115 | }, | |
116 | .mr_cache[6] = { | |
117 | .size = 500, | |
118 | .limit = 250 | |
119 | }, | |
120 | .mr_cache[7] = { | |
121 | .size = 500, | |
122 | .limit = 250 | |
123 | }, | |
124 | .mr_cache[8] = { | |
125 | .size = 500, | |
126 | .limit = 250 | |
127 | }, | |
128 | .mr_cache[9] = { | |
129 | .size = 500, | |
130 | .limit = 250 | |
131 | }, | |
132 | .mr_cache[10] = { | |
133 | .size = 500, | |
134 | .limit = 250 | |
135 | }, | |
136 | .mr_cache[11] = { | |
137 | .size = 500, | |
138 | .limit = 250 | |
139 | }, | |
140 | .mr_cache[12] = { | |
141 | .size = 64, | |
142 | .limit = 32 | |
143 | }, | |
144 | .mr_cache[13] = { | |
145 | .size = 32, | |
146 | .limit = 16 | |
147 | }, | |
148 | .mr_cache[14] = { | |
149 | .size = 16, | |
150 | .limit = 8 | |
151 | }, | |
152 | .mr_cache[15] = { | |
153 | .size = 8, | |
154 | .limit = 4 | |
155 | }, | |
7d0cc6ed AK |
156 | .mr_cache[16] = { |
157 | .size = 8, | |
158 | .limit = 4 | |
159 | }, | |
160 | .mr_cache[17] = { | |
161 | .size = 8, | |
162 | .limit = 4 | |
163 | }, | |
164 | .mr_cache[18] = { | |
165 | .size = 8, | |
166 | .limit = 4 | |
167 | }, | |
168 | .mr_cache[19] = { | |
169 | .size = 4, | |
170 | .limit = 2 | |
171 | }, | |
172 | .mr_cache[20] = { | |
173 | .size = 4, | |
174 | .limit = 2 | |
175 | }, | |
9603b61d JM |
176 | }, |
177 | }; | |
e126ba97 | 178 | |
e3297246 EC |
179 | #define FW_INIT_TIMEOUT_MILI 2000 |
180 | #define FW_INIT_WAIT_MS 2 | |
181 | ||
182 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
183 | { | |
184 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
185 | int err = 0; | |
186 | ||
187 | while (fw_initializing(dev)) { | |
188 | if (time_after(jiffies, end)) { | |
189 | err = -EBUSY; | |
190 | break; | |
191 | } | |
192 | msleep(FW_INIT_WAIT_MS); | |
193 | } | |
194 | ||
195 | return err; | |
196 | } | |
197 | ||
012e50e1 HN |
198 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
199 | { | |
200 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
201 | driver_version); | |
202 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
203 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
204 | int remaining_size = driver_ver_sz; | |
205 | char *string; | |
206 | ||
207 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
208 | return; | |
209 | ||
210 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
211 | ||
212 | strncpy(string, "Linux", remaining_size); | |
213 | ||
214 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
215 | strncat(string, ",", remaining_size); | |
216 | ||
217 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
218 | strncat(string, DRIVER_NAME, remaining_size); | |
219 | ||
220 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
221 | strncat(string, ",", remaining_size); | |
222 | ||
223 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
224 | strncat(string, DRIVER_VERSION, remaining_size); | |
225 | ||
226 | /*Send the command*/ | |
227 | MLX5_SET(set_driver_version_in, in, opcode, | |
228 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
229 | ||
230 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
231 | } | |
232 | ||
e126ba97 EC |
233 | static int set_dma_caps(struct pci_dev *pdev) |
234 | { | |
235 | int err; | |
236 | ||
237 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
238 | if (err) { | |
1a91de28 | 239 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
240 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
241 | if (err) { | |
1a91de28 | 242 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
243 | return err; |
244 | } | |
245 | } | |
246 | ||
247 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
248 | if (err) { | |
249 | dev_warn(&pdev->dev, | |
1a91de28 | 250 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
251 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
252 | if (err) { | |
253 | dev_err(&pdev->dev, | |
1a91de28 | 254 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
255 | return err; |
256 | } | |
257 | } | |
258 | ||
259 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
260 | return err; | |
261 | } | |
262 | ||
89d44f0a MD |
263 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
264 | { | |
265 | struct pci_dev *pdev = dev->pdev; | |
266 | int err = 0; | |
267 | ||
268 | mutex_lock(&dev->pci_status_mutex); | |
269 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
270 | err = pci_enable_device(pdev); | |
271 | if (!err) | |
272 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
273 | } | |
274 | mutex_unlock(&dev->pci_status_mutex); | |
275 | ||
276 | return err; | |
277 | } | |
278 | ||
279 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
280 | { | |
281 | struct pci_dev *pdev = dev->pdev; | |
282 | ||
283 | mutex_lock(&dev->pci_status_mutex); | |
284 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
285 | pci_disable_device(pdev); | |
286 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
287 | } | |
288 | mutex_unlock(&dev->pci_status_mutex); | |
289 | } | |
290 | ||
e126ba97 EC |
291 | static int request_bar(struct pci_dev *pdev) |
292 | { | |
293 | int err = 0; | |
294 | ||
295 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 296 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
297 | return -ENODEV; |
298 | } | |
299 | ||
300 | err = pci_request_regions(pdev, DRIVER_NAME); | |
301 | if (err) | |
302 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
303 | ||
304 | return err; | |
305 | } | |
306 | ||
307 | static void release_bar(struct pci_dev *pdev) | |
308 | { | |
309 | pci_release_regions(pdev); | |
310 | } | |
311 | ||
312 | static int mlx5_enable_msix(struct mlx5_core_dev *dev) | |
313 | { | |
db058a18 SM |
314 | struct mlx5_priv *priv = &dev->priv; |
315 | struct mlx5_eq_table *table = &priv->eq_table; | |
938fe83c | 316 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 317 | int nvec; |
e126ba97 EC |
318 | int i; |
319 | ||
938fe83c SM |
320 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
321 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
322 | nvec = min_t(int, nvec, num_eqs); |
323 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
324 | return -ENOMEM; | |
325 | ||
db058a18 SM |
326 | priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); |
327 | ||
328 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); | |
329 | if (!priv->msix_arr || !priv->irq_info) | |
330 | goto err_free_msix; | |
e126ba97 EC |
331 | |
332 | for (i = 0; i < nvec; i++) | |
db058a18 | 333 | priv->msix_arr[i].entry = i; |
e126ba97 | 334 | |
db058a18 | 335 | nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, |
3a9e161a | 336 | MLX5_EQ_VEC_COMP_BASE + 1, nvec); |
f3c9407b AG |
337 | if (nvec < 0) |
338 | return nvec; | |
e126ba97 | 339 | |
f3c9407b | 340 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
341 | |
342 | return 0; | |
db058a18 SM |
343 | |
344 | err_free_msix: | |
345 | kfree(priv->irq_info); | |
346 | kfree(priv->msix_arr); | |
347 | return -ENOMEM; | |
e126ba97 EC |
348 | } |
349 | ||
350 | static void mlx5_disable_msix(struct mlx5_core_dev *dev) | |
351 | { | |
db058a18 | 352 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 EC |
353 | |
354 | pci_disable_msix(dev->pdev); | |
db058a18 SM |
355 | kfree(priv->irq_info); |
356 | kfree(priv->msix_arr); | |
e126ba97 EC |
357 | } |
358 | ||
bd10838a | 359 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
360 | u8 he; |
361 | u8 rsvd[15]; | |
362 | }; | |
363 | ||
87b8de49 EC |
364 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
365 | ||
366 | enum { | |
c7a08ac7 EC |
367 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
368 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
369 | }; |
370 | ||
2974ab6e | 371 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
372 | { |
373 | switch (size) { | |
374 | case 128: | |
375 | return 0; | |
376 | case 256: | |
377 | return 1; | |
378 | case 512: | |
379 | return 2; | |
380 | case 1024: | |
381 | return 3; | |
382 | case 2048: | |
383 | return 4; | |
384 | case 4096: | |
385 | return 5; | |
386 | default: | |
2974ab6e | 387 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
388 | return 0; |
389 | } | |
390 | } | |
391 | ||
b06e7de8 LR |
392 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
393 | enum mlx5_cap_type cap_type, | |
394 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 395 | { |
b775516b EC |
396 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
397 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
398 | void *out, *hca_caps; |
399 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
400 | int err; |
401 | ||
b775516b EC |
402 | memset(in, 0, sizeof(in)); |
403 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 404 | if (!out) |
e126ba97 | 405 | return -ENOMEM; |
938fe83c | 406 | |
b775516b EC |
407 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
408 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
409 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 410 | if (err) { |
938fe83c SM |
411 | mlx5_core_warn(dev, |
412 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
413 | cap_type, cap_mode, err); | |
e126ba97 EC |
414 | goto query_ex; |
415 | } | |
c7a08ac7 | 416 | |
938fe83c SM |
417 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
418 | ||
419 | switch (cap_mode) { | |
420 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 421 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
422 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
423 | break; | |
424 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 425 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
426 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
427 | break; | |
428 | default: | |
429 | mlx5_core_warn(dev, | |
430 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
431 | cap_type, cap_mode); | |
432 | err = -EINVAL; | |
433 | break; | |
434 | } | |
c7a08ac7 EC |
435 | query_ex: |
436 | kfree(out); | |
437 | return err; | |
438 | } | |
439 | ||
b06e7de8 LR |
440 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
441 | { | |
442 | int ret; | |
443 | ||
444 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
445 | if (ret) | |
446 | return ret; | |
447 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
448 | } | |
449 | ||
f91e6d89 | 450 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 451 | { |
c4f287c4 | 452 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 453 | |
b775516b | 454 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 455 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 456 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
457 | } |
458 | ||
f91e6d89 EBE |
459 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
460 | { | |
461 | void *set_ctx; | |
462 | void *set_hca_cap; | |
463 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
464 | int req_endianness; | |
465 | int err; | |
466 | ||
467 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 468 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
469 | if (err) |
470 | return err; | |
471 | } else { | |
472 | return 0; | |
473 | } | |
474 | ||
475 | req_endianness = | |
476 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 477 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
478 | |
479 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
480 | return 0; | |
481 | ||
482 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
483 | if (!set_ctx) | |
484 | return -ENOMEM; | |
485 | ||
486 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
487 | ||
488 | /* Set requestor to host endianness */ | |
bd10838a | 489 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
490 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
491 | ||
492 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
493 | ||
494 | kfree(set_ctx); | |
495 | return err; | |
496 | } | |
497 | ||
c7a08ac7 EC |
498 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
499 | { | |
b775516b | 500 | void *set_ctx = NULL; |
c7a08ac7 | 501 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 502 | int err = -ENOMEM; |
b775516b | 503 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 504 | void *set_hca_cap; |
c7a08ac7 | 505 | |
b775516b | 506 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 507 | if (!set_ctx) |
e126ba97 | 508 | goto query_ex; |
e126ba97 | 509 | |
b06e7de8 | 510 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
511 | if (err) |
512 | goto query_ex; | |
513 | ||
938fe83c SM |
514 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
515 | capability); | |
701052c5 | 516 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
517 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
518 | ||
519 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 520 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 521 | 128); |
c7a08ac7 | 522 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 523 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 524 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 525 | |
883371c4 NO |
526 | /* Check log_max_qp from HCA caps to set in current profile */ |
527 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
528 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
529 | profile[prof_sel].log_max_qp, | |
530 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
531 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
532 | } | |
c7a08ac7 | 533 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
534 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
535 | prof->log_max_qp); | |
c7a08ac7 | 536 | |
938fe83c SM |
537 | /* disable cmdif checksum */ |
538 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 539 | |
91828bd8 MD |
540 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
541 | * than 4K. | |
542 | */ | |
543 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
544 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
545 | ||
fe1e1876 CS |
546 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
547 | ||
f32f5bd2 DJ |
548 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
549 | MLX5_SET(cmd_hca_cap, | |
550 | set_hca_cap, | |
551 | cache_line_128byte, | |
552 | cache_line_size() == 128 ? 1 : 0); | |
553 | ||
f91e6d89 EBE |
554 | err = set_caps(dev, set_ctx, set_sz, |
555 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 556 | |
e126ba97 | 557 | query_ex: |
e126ba97 | 558 | kfree(set_ctx); |
e126ba97 EC |
559 | return err; |
560 | } | |
561 | ||
562 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
563 | { | |
bd10838a OG |
564 | struct mlx5_reg_host_endianness he_in; |
565 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
566 | int err; |
567 | ||
fc50db98 EC |
568 | if (!mlx5_core_is_pf(dev)) |
569 | return 0; | |
570 | ||
e126ba97 EC |
571 | memset(&he_in, 0, sizeof(he_in)); |
572 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
573 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
574 | &he_out, sizeof(he_out), | |
575 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
576 | return err; | |
577 | } | |
578 | ||
0b107106 | 579 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 580 | { |
c4f287c4 SM |
581 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
582 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 583 | |
0b107106 EC |
584 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
585 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 586 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
587 | } |
588 | ||
0b107106 | 589 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 590 | { |
c4f287c4 SM |
591 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
592 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 593 | |
0b107106 EC |
594 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
595 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 596 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
597 | } |
598 | ||
a5a1d1c2 | 599 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
b0844444 EBE |
600 | { |
601 | u32 timer_h, timer_h1, timer_l; | |
602 | ||
603 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
604 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
605 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
606 | if (timer_h != timer_h1) /* wrap around */ | |
607 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
608 | ||
a5a1d1c2 | 609 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
610 | } |
611 | ||
db058a18 SM |
612 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) |
613 | { | |
614 | struct mlx5_priv *priv = &mdev->priv; | |
615 | struct msix_entry *msix = priv->msix_arr; | |
616 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
db058a18 SM |
617 | |
618 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | |
619 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | |
620 | return -ENOMEM; | |
621 | } | |
622 | ||
d151d73d | 623 | cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node), |
dda922c8 | 624 | priv->irq_info[i].mask); |
db058a18 | 625 | |
f0d7ae95 AB |
626 | if (IS_ENABLED(CONFIG_SMP) && |
627 | irq_set_affinity_hint(irq, priv->irq_info[i].mask)) | |
b665d98e | 628 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq); |
db058a18 SM |
629 | |
630 | return 0; | |
db058a18 SM |
631 | } |
632 | ||
633 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | |
634 | { | |
635 | struct mlx5_priv *priv = &mdev->priv; | |
636 | struct msix_entry *msix = priv->msix_arr; | |
637 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
638 | ||
639 | irq_set_affinity_hint(irq, NULL); | |
640 | free_cpumask_var(priv->irq_info[i].mask); | |
641 | } | |
642 | ||
643 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | |
644 | { | |
645 | int err; | |
646 | int i; | |
647 | ||
648 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | |
649 | err = mlx5_irq_set_affinity_hint(mdev, i); | |
650 | if (err) | |
651 | goto err_out; | |
652 | } | |
653 | ||
654 | return 0; | |
655 | ||
656 | err_out: | |
657 | for (i--; i >= 0; i--) | |
658 | mlx5_irq_clear_affinity_hint(mdev, i); | |
659 | ||
660 | return err; | |
661 | } | |
662 | ||
663 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | |
664 | { | |
665 | int i; | |
666 | ||
667 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | |
668 | mlx5_irq_clear_affinity_hint(mdev, i); | |
669 | } | |
670 | ||
0b6e26ce DT |
671 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
672 | unsigned int *irqn) | |
233d05d2 SM |
673 | { |
674 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
675 | struct mlx5_eq *eq, *n; | |
676 | int err = -ENOENT; | |
677 | ||
678 | spin_lock(&table->lock); | |
679 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
680 | if (eq->index == vector) { | |
681 | *eqn = eq->eqn; | |
682 | *irqn = eq->irqn; | |
683 | err = 0; | |
684 | break; | |
685 | } | |
686 | } | |
687 | spin_unlock(&table->lock); | |
688 | ||
689 | return err; | |
690 | } | |
691 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
692 | ||
94c6825e MB |
693 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
694 | { | |
695 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
696 | struct mlx5_eq *eq; | |
697 | ||
698 | spin_lock(&table->lock); | |
699 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
700 | if (eq->eqn == eqn) { | |
701 | spin_unlock(&table->lock); | |
702 | return eq; | |
703 | } | |
704 | ||
705 | spin_unlock(&table->lock); | |
706 | ||
707 | return ERR_PTR(-ENOENT); | |
708 | } | |
709 | ||
233d05d2 SM |
710 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
711 | { | |
712 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
713 | struct mlx5_eq *eq, *n; | |
714 | ||
5a7b27eb MG |
715 | #ifdef CONFIG_RFS_ACCEL |
716 | if (dev->rmap) { | |
717 | free_irq_cpu_rmap(dev->rmap); | |
718 | dev->rmap = NULL; | |
719 | } | |
720 | #endif | |
233d05d2 SM |
721 | spin_lock(&table->lock); |
722 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
723 | list_del(&eq->list); | |
724 | spin_unlock(&table->lock); | |
725 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
726 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
727 | eq->eqn); | |
728 | kfree(eq); | |
729 | spin_lock(&table->lock); | |
730 | } | |
731 | spin_unlock(&table->lock); | |
732 | } | |
733 | ||
734 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
735 | { | |
736 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 737 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
738 | struct mlx5_eq *eq; |
739 | int ncomp_vec; | |
740 | int nent; | |
741 | int err; | |
742 | int i; | |
743 | ||
744 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
745 | ncomp_vec = table->num_comp_vectors; | |
746 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
747 | #ifdef CONFIG_RFS_ACCEL |
748 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
749 | if (!dev->rmap) | |
750 | return -ENOMEM; | |
751 | #endif | |
233d05d2 SM |
752 | for (i = 0; i < ncomp_vec; i++) { |
753 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
754 | if (!eq) { | |
755 | err = -ENOMEM; | |
756 | goto clean; | |
757 | } | |
758 | ||
5a7b27eb MG |
759 | #ifdef CONFIG_RFS_ACCEL |
760 | irq_cpu_rmap_add(dev->rmap, | |
761 | dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector); | |
762 | #endif | |
db058a18 | 763 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
764 | err = mlx5_create_map_eq(dev, eq, |
765 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
01187175 | 766 | name, MLX5_EQ_TYPE_COMP); |
233d05d2 SM |
767 | if (err) { |
768 | kfree(eq); | |
769 | goto clean; | |
770 | } | |
771 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
772 | eq->index = i; | |
773 | spin_lock(&table->lock); | |
774 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
775 | spin_unlock(&table->lock); | |
776 | } | |
777 | ||
778 | return 0; | |
779 | ||
780 | clean: | |
781 | free_comp_eqs(dev); | |
782 | return err; | |
783 | } | |
784 | ||
f62b8bb8 AV |
785 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
786 | { | |
c4f287c4 SM |
787 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
788 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 789 | u32 sup_issi; |
c4f287c4 | 790 | int err; |
f62b8bb8 AV |
791 | |
792 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
793 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
794 | query_out, sizeof(query_out)); | |
f62b8bb8 | 795 | if (err) { |
c4f287c4 SM |
796 | u32 syndrome; |
797 | u8 status; | |
798 | ||
799 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
800 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
801 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
802 | err, status, syndrome); | |
803 | return err; | |
f62b8bb8 AV |
804 | } |
805 | ||
f9c14e46 KH |
806 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
807 | dev->issi = 0; | |
808 | return 0; | |
f62b8bb8 AV |
809 | } |
810 | ||
811 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
812 | ||
813 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
814 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
815 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
816 | |
817 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
818 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
819 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
820 | set_out, sizeof(set_out)); | |
f62b8bb8 | 821 | if (err) { |
f9c14e46 KH |
822 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
823 | err); | |
f62b8bb8 AV |
824 | return err; |
825 | } | |
826 | ||
827 | dev->issi = 1; | |
828 | ||
829 | return 0; | |
e74a1db0 | 830 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
831 | return 0; |
832 | } | |
833 | ||
9eb78923 | 834 | return -EOPNOTSUPP; |
f62b8bb8 | 835 | } |
f62b8bb8 | 836 | |
7907f23a | 837 | |
a31208b1 MD |
838 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
839 | { | |
840 | struct pci_dev *pdev = dev->pdev; | |
841 | int err = 0; | |
e126ba97 | 842 | |
e126ba97 EC |
843 | pci_set_drvdata(dev->pdev, dev); |
844 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
845 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
846 | ||
847 | mutex_init(&priv->pgdir_mutex); | |
848 | INIT_LIST_HEAD(&priv->pgdir_list); | |
849 | spin_lock_init(&priv->mkey_lock); | |
850 | ||
311c7c71 SM |
851 | mutex_init(&priv->alloc_mutex); |
852 | ||
853 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
854 | ||
e126ba97 EC |
855 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
856 | if (!priv->dbg_root) | |
857 | return -ENOMEM; | |
858 | ||
89d44f0a | 859 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 860 | if (err) { |
1a91de28 | 861 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
862 | goto err_dbg; |
863 | } | |
864 | ||
865 | err = request_bar(pdev); | |
866 | if (err) { | |
1a91de28 | 867 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
868 | goto err_disable; |
869 | } | |
870 | ||
871 | pci_set_master(pdev); | |
872 | ||
873 | err = set_dma_caps(pdev); | |
874 | if (err) { | |
875 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
876 | goto err_clr_master; | |
877 | } | |
878 | ||
879 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
880 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
881 | if (!dev->iseg) { | |
882 | err = -ENOMEM; | |
883 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
884 | goto err_clr_master; | |
885 | } | |
a31208b1 MD |
886 | |
887 | return 0; | |
888 | ||
889 | err_clr_master: | |
890 | pci_clear_master(dev->pdev); | |
891 | release_bar(dev->pdev); | |
892 | err_disable: | |
89d44f0a | 893 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
894 | |
895 | err_dbg: | |
896 | debugfs_remove(priv->dbg_root); | |
897 | return err; | |
898 | } | |
899 | ||
900 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
901 | { | |
902 | iounmap(dev->iseg); | |
903 | pci_clear_master(dev->pdev); | |
904 | release_bar(dev->pdev); | |
89d44f0a | 905 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
906 | debugfs_remove(priv->dbg_root); |
907 | } | |
908 | ||
59211bd3 MHY |
909 | static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
910 | { | |
911 | struct pci_dev *pdev = dev->pdev; | |
912 | int err; | |
913 | ||
59211bd3 MHY |
914 | err = mlx5_query_board_id(dev); |
915 | if (err) { | |
916 | dev_err(&pdev->dev, "query board id failed\n"); | |
917 | goto out; | |
918 | } | |
919 | ||
920 | err = mlx5_eq_init(dev); | |
921 | if (err) { | |
922 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
923 | goto out; | |
924 | } | |
925 | ||
59211bd3 MHY |
926 | err = mlx5_init_cq_table(dev); |
927 | if (err) { | |
928 | dev_err(&pdev->dev, "failed to initialize cq table\n"); | |
929 | goto err_eq_cleanup; | |
930 | } | |
931 | ||
932 | mlx5_init_qp_table(dev); | |
933 | ||
934 | mlx5_init_srq_table(dev); | |
935 | ||
936 | mlx5_init_mkey_table(dev); | |
937 | ||
938 | err = mlx5_init_rl_table(dev); | |
939 | if (err) { | |
940 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
941 | goto err_tables_cleanup; | |
942 | } | |
943 | ||
c2d6e31a MHY |
944 | #ifdef CONFIG_MLX5_CORE_EN |
945 | err = mlx5_eswitch_init(dev); | |
946 | if (err) { | |
947 | dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); | |
948 | goto err_rl_cleanup; | |
949 | } | |
950 | #endif | |
951 | ||
952 | err = mlx5_sriov_init(dev); | |
953 | if (err) { | |
954 | dev_err(&pdev->dev, "Failed to init sriov %d\n", err); | |
955 | goto err_eswitch_cleanup; | |
956 | } | |
957 | ||
59211bd3 MHY |
958 | return 0; |
959 | ||
c2d6e31a MHY |
960 | err_eswitch_cleanup: |
961 | #ifdef CONFIG_MLX5_CORE_EN | |
962 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
963 | ||
964 | err_rl_cleanup: | |
965 | #endif | |
966 | mlx5_cleanup_rl_table(dev); | |
967 | ||
59211bd3 MHY |
968 | err_tables_cleanup: |
969 | mlx5_cleanup_mkey_table(dev); | |
970 | mlx5_cleanup_srq_table(dev); | |
971 | mlx5_cleanup_qp_table(dev); | |
972 | mlx5_cleanup_cq_table(dev); | |
973 | ||
974 | err_eq_cleanup: | |
975 | mlx5_eq_cleanup(dev); | |
976 | ||
977 | out: | |
978 | return err; | |
979 | } | |
980 | ||
981 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
982 | { | |
c2d6e31a MHY |
983 | mlx5_sriov_cleanup(dev); |
984 | #ifdef CONFIG_MLX5_CORE_EN | |
985 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
986 | #endif | |
59211bd3 MHY |
987 | mlx5_cleanup_rl_table(dev); |
988 | mlx5_cleanup_mkey_table(dev); | |
989 | mlx5_cleanup_srq_table(dev); | |
990 | mlx5_cleanup_qp_table(dev); | |
991 | mlx5_cleanup_cq_table(dev); | |
992 | mlx5_eq_cleanup(dev); | |
993 | } | |
994 | ||
995 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |
996 | bool boot) | |
a31208b1 MD |
997 | { |
998 | struct pci_dev *pdev = dev->pdev; | |
999 | int err; | |
1000 | ||
89d44f0a | 1001 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1002 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1003 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
1004 | __func__); | |
1005 | goto out; | |
1006 | } | |
1007 | ||
e126ba97 EC |
1008 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
1009 | fw_rev_min(dev), fw_rev_sub(dev)); | |
1010 | ||
89d44f0a MD |
1011 | /* on load removing any previous indication of internal error, device is |
1012 | * up | |
1013 | */ | |
1014 | dev->state = MLX5_DEVICE_STATE_UP; | |
1015 | ||
e126ba97 EC |
1016 | err = mlx5_cmd_init(dev); |
1017 | if (err) { | |
1018 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 1019 | goto out_err; |
e126ba97 EC |
1020 | } |
1021 | ||
e3297246 EC |
1022 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
1023 | if (err) { | |
1024 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
1025 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 1026 | goto err_cmd_cleanup; |
e3297246 EC |
1027 | } |
1028 | ||
0b107106 | 1029 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1030 | if (err) { |
1031 | dev_err(&pdev->dev, "enable hca failed\n"); | |
59211bd3 | 1032 | goto err_cmd_cleanup; |
cd23b14b EC |
1033 | } |
1034 | ||
f62b8bb8 AV |
1035 | err = mlx5_core_set_issi(dev); |
1036 | if (err) { | |
1037 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1038 | goto err_disable_hca; | |
1039 | } | |
f62b8bb8 | 1040 | |
cd23b14b EC |
1041 | err = mlx5_satisfy_startup_pages(dev, 1); |
1042 | if (err) { | |
1043 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1044 | goto err_disable_hca; | |
1045 | } | |
1046 | ||
e126ba97 EC |
1047 | err = set_hca_ctrl(dev); |
1048 | if (err) { | |
1049 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1050 | goto reclaim_boot_pages; |
e126ba97 EC |
1051 | } |
1052 | ||
1053 | err = handle_hca_cap(dev); | |
1054 | if (err) { | |
1055 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1056 | goto reclaim_boot_pages; |
e126ba97 EC |
1057 | } |
1058 | ||
f91e6d89 EBE |
1059 | err = handle_hca_cap_atomic(dev); |
1060 | if (err) { | |
1061 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1062 | goto reclaim_boot_pages; | |
e126ba97 EC |
1063 | } |
1064 | ||
cd23b14b | 1065 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1066 | if (err) { |
cd23b14b EC |
1067 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1068 | goto reclaim_boot_pages; | |
e126ba97 EC |
1069 | } |
1070 | ||
1071 | err = mlx5_pagealloc_start(dev); | |
1072 | if (err) { | |
1073 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1074 | goto reclaim_boot_pages; |
e126ba97 EC |
1075 | } |
1076 | ||
1077 | err = mlx5_cmd_init_hca(dev); | |
1078 | if (err) { | |
1079 | dev_err(&pdev->dev, "init hca failed\n"); | |
1080 | goto err_pagealloc_stop; | |
1081 | } | |
1082 | ||
012e50e1 HN |
1083 | mlx5_set_driver_version(dev); |
1084 | ||
e126ba97 EC |
1085 | mlx5_start_health_poll(dev); |
1086 | ||
bba1574c DJ |
1087 | err = mlx5_query_hca_caps(dev); |
1088 | if (err) { | |
1089 | dev_err(&pdev->dev, "query hca failed\n"); | |
1090 | goto err_stop_poll; | |
1091 | } | |
1092 | ||
59211bd3 MHY |
1093 | if (boot && mlx5_init_once(dev, priv)) { |
1094 | dev_err(&pdev->dev, "sw objs init failed\n"); | |
e126ba97 EC |
1095 | goto err_stop_poll; |
1096 | } | |
1097 | ||
1098 | err = mlx5_enable_msix(dev); | |
1099 | if (err) { | |
1100 | dev_err(&pdev->dev, "enable msix failed\n"); | |
59211bd3 | 1101 | goto err_cleanup_once; |
e126ba97 EC |
1102 | } |
1103 | ||
01187175 EC |
1104 | dev->priv.uar = mlx5_get_uars_page(dev); |
1105 | if (!dev->priv.uar) { | |
e126ba97 | 1106 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); |
59211bd3 | 1107 | goto err_disable_msix; |
e126ba97 EC |
1108 | } |
1109 | ||
e29341fb IT |
1110 | err = mlx5_fpga_device_init(dev); |
1111 | if (err) { | |
1112 | dev_err(&pdev->dev, "fpga device init failed %d\n", err); | |
1113 | goto err_put_uars; | |
1114 | } | |
1115 | ||
e126ba97 EC |
1116 | err = mlx5_start_eqs(dev); |
1117 | if (err) { | |
1118 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
e29341fb | 1119 | goto err_fpga_init; |
e126ba97 EC |
1120 | } |
1121 | ||
233d05d2 SM |
1122 | err = alloc_comp_eqs(dev); |
1123 | if (err) { | |
1124 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1125 | goto err_stop_eqs; | |
1126 | } | |
1127 | ||
db058a18 | 1128 | err = mlx5_irq_set_affinity_hints(dev); |
59211bd3 | 1129 | if (err) { |
db058a18 | 1130 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); |
59211bd3 MHY |
1131 | goto err_affinity_hints; |
1132 | } | |
e126ba97 | 1133 | |
86d722ad MG |
1134 | err = mlx5_init_fs(dev); |
1135 | if (err) { | |
1136 | dev_err(&pdev->dev, "Failed to init flow steering\n"); | |
1137 | goto err_fs; | |
1138 | } | |
1466cc5b | 1139 | |
073bb189 | 1140 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1141 | mlx5_eswitch_attach(dev->priv.eswitch); |
073bb189 SM |
1142 | #endif |
1143 | ||
c2d6e31a | 1144 | err = mlx5_sriov_attach(dev); |
fc50db98 EC |
1145 | if (err) { |
1146 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1147 | goto err_sriov; | |
1148 | } | |
1149 | ||
e29341fb IT |
1150 | err = mlx5_fpga_device_start(dev); |
1151 | if (err) { | |
1152 | dev_err(&pdev->dev, "fpga device start failed %d\n", err); | |
1153 | goto err_reg_dev; | |
1154 | } | |
1155 | ||
737a234b MHY |
1156 | if (mlx5_device_registered(dev)) { |
1157 | mlx5_attach_device(dev); | |
1158 | } else { | |
1159 | err = mlx5_register_device(dev); | |
1160 | if (err) { | |
1161 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1162 | goto err_reg_dev; | |
1163 | } | |
a31208b1 MD |
1164 | } |
1165 | ||
5fc7197d MD |
1166 | clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); |
1167 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
89d44f0a MD |
1168 | out: |
1169 | mutex_unlock(&dev->intf_state_mutex); | |
1170 | ||
e126ba97 EC |
1171 | return 0; |
1172 | ||
59211bd3 | 1173 | err_reg_dev: |
c2d6e31a | 1174 | mlx5_sriov_detach(dev); |
fc50db98 | 1175 | |
59211bd3 | 1176 | err_sriov: |
073bb189 | 1177 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1178 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1179 | #endif |
86d722ad | 1180 | mlx5_cleanup_fs(dev); |
59211bd3 | 1181 | |
86d722ad | 1182 | err_fs: |
a31208b1 | 1183 | mlx5_irq_clear_affinity_hints(dev); |
59211bd3 MHY |
1184 | |
1185 | err_affinity_hints: | |
db058a18 SM |
1186 | free_comp_eqs(dev); |
1187 | ||
233d05d2 SM |
1188 | err_stop_eqs: |
1189 | mlx5_stop_eqs(dev); | |
1190 | ||
e29341fb IT |
1191 | err_fpga_init: |
1192 | mlx5_fpga_device_cleanup(dev); | |
1193 | ||
5fe9dec0 | 1194 | err_put_uars: |
01187175 | 1195 | mlx5_put_uars_page(dev, priv->uar); |
e126ba97 | 1196 | |
59211bd3 | 1197 | err_disable_msix: |
e126ba97 EC |
1198 | mlx5_disable_msix(dev); |
1199 | ||
59211bd3 MHY |
1200 | err_cleanup_once: |
1201 | if (boot) | |
1202 | mlx5_cleanup_once(dev); | |
1203 | ||
e126ba97 EC |
1204 | err_stop_poll: |
1205 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1206 | if (mlx5_cmd_teardown_hca(dev)) { |
1207 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1208 | goto out_err; |
1bde6e30 | 1209 | } |
e126ba97 EC |
1210 | |
1211 | err_pagealloc_stop: | |
1212 | mlx5_pagealloc_stop(dev); | |
1213 | ||
cd23b14b | 1214 | reclaim_boot_pages: |
e126ba97 EC |
1215 | mlx5_reclaim_startup_pages(dev); |
1216 | ||
cd23b14b | 1217 | err_disable_hca: |
0b107106 | 1218 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1219 | |
59211bd3 | 1220 | err_cmd_cleanup: |
e126ba97 EC |
1221 | mlx5_cmd_cleanup(dev); |
1222 | ||
89d44f0a MD |
1223 | out_err: |
1224 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1225 | mutex_unlock(&dev->intf_state_mutex); | |
1226 | ||
e126ba97 EC |
1227 | return err; |
1228 | } | |
e126ba97 | 1229 | |
59211bd3 MHY |
1230 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, |
1231 | bool cleanup) | |
e126ba97 | 1232 | { |
89d44f0a | 1233 | int err = 0; |
e126ba97 | 1234 | |
5e44fca5 DJ |
1235 | if (cleanup) |
1236 | mlx5_drain_health_wq(dev); | |
689a248d | 1237 | |
89d44f0a | 1238 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1239 | if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { |
89d44f0a MD |
1240 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1241 | __func__); | |
59211bd3 MHY |
1242 | if (cleanup) |
1243 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1244 | goto out; |
1245 | } | |
6b6adee3 | 1246 | |
737a234b MHY |
1247 | if (mlx5_device_registered(dev)) |
1248 | mlx5_detach_device(dev); | |
1249 | ||
c2d6e31a | 1250 | mlx5_sriov_detach(dev); |
073bb189 | 1251 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1252 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1253 | #endif |
86d722ad | 1254 | mlx5_cleanup_fs(dev); |
db058a18 | 1255 | mlx5_irq_clear_affinity_hints(dev); |
233d05d2 | 1256 | free_comp_eqs(dev); |
e126ba97 | 1257 | mlx5_stop_eqs(dev); |
e29341fb | 1258 | mlx5_fpga_device_cleanup(dev); |
01187175 | 1259 | mlx5_put_uars_page(dev, priv->uar); |
e126ba97 | 1260 | mlx5_disable_msix(dev); |
59211bd3 MHY |
1261 | if (cleanup) |
1262 | mlx5_cleanup_once(dev); | |
e126ba97 | 1263 | mlx5_stop_health_poll(dev); |
ac6ea6e8 EC |
1264 | err = mlx5_cmd_teardown_hca(dev); |
1265 | if (err) { | |
1bde6e30 | 1266 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1267 | goto out; |
1bde6e30 | 1268 | } |
e126ba97 EC |
1269 | mlx5_pagealloc_stop(dev); |
1270 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1271 | mlx5_core_disable_hca(dev, 0); |
e126ba97 | 1272 | mlx5_cmd_cleanup(dev); |
9603b61d | 1273 | |
ac6ea6e8 | 1274 | out: |
5fc7197d MD |
1275 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1276 | set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); | |
89d44f0a | 1277 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1278 | return err; |
9603b61d | 1279 | } |
64613d94 | 1280 | |
9603b61d JM |
1281 | struct mlx5_core_event_handler { |
1282 | void (*event)(struct mlx5_core_dev *dev, | |
1283 | enum mlx5_dev_event event, | |
1284 | void *data); | |
1285 | }; | |
1286 | ||
feae9087 OG |
1287 | static const struct devlink_ops mlx5_devlink_ops = { |
1288 | #ifdef CONFIG_MLX5_CORE_EN | |
1289 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, | |
1290 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1291 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1292 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
7768d197 RD |
1293 | .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, |
1294 | .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, | |
feae9087 OG |
1295 | #endif |
1296 | }; | |
f66f049f | 1297 | |
59211bd3 | 1298 | #define MLX5_IB_MOD "mlx5_ib" |
9603b61d JM |
1299 | static int init_one(struct pci_dev *pdev, |
1300 | const struct pci_device_id *id) | |
1301 | { | |
1302 | struct mlx5_core_dev *dev; | |
feae9087 | 1303 | struct devlink *devlink; |
9603b61d JM |
1304 | struct mlx5_priv *priv; |
1305 | int err; | |
1306 | ||
feae9087 OG |
1307 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1308 | if (!devlink) { | |
9603b61d JM |
1309 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1310 | return -ENOMEM; | |
1311 | } | |
feae9087 OG |
1312 | |
1313 | dev = devlink_priv(devlink); | |
9603b61d | 1314 | priv = &dev->priv; |
fc50db98 | 1315 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1316 | |
1317 | pci_set_drvdata(pdev, dev); | |
1318 | ||
0e97a340 HN |
1319 | dev->pdev = pdev; |
1320 | dev->event = mlx5_core_event; | |
9603b61d | 1321 | dev->profile = &profile[prof_sel]; |
9603b61d | 1322 | |
364d1798 EC |
1323 | INIT_LIST_HEAD(&priv->ctx_list); |
1324 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1325 | mutex_init(&dev->pci_status_mutex); |
1326 | mutex_init(&dev->intf_state_mutex); | |
d9aaed83 AK |
1327 | |
1328 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1329 | err = init_srcu_struct(&priv->pfault_srcu); | |
1330 | if (err) { | |
1331 | dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n", | |
1332 | err); | |
1333 | goto clean_dev; | |
1334 | } | |
1335 | #endif | |
01187175 EC |
1336 | mutex_init(&priv->bfregs.reg_head.lock); |
1337 | mutex_init(&priv->bfregs.wc_head.lock); | |
1338 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1339 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1340 | ||
a31208b1 | 1341 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1342 | if (err) { |
a31208b1 | 1343 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
d9aaed83 | 1344 | goto clean_srcu; |
9603b61d JM |
1345 | } |
1346 | ||
ac6ea6e8 EC |
1347 | err = mlx5_health_init(dev); |
1348 | if (err) { | |
1349 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1350 | goto close_pci; | |
1351 | } | |
1352 | ||
59211bd3 MHY |
1353 | mlx5_pagealloc_init(dev); |
1354 | ||
1355 | err = mlx5_load_one(dev, priv, true); | |
9603b61d | 1356 | if (err) { |
a31208b1 | 1357 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1358 | goto clean_health; |
9603b61d | 1359 | } |
59211bd3 | 1360 | |
f82eed45 | 1361 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1362 | |
feae9087 OG |
1363 | err = devlink_register(devlink, &pdev->dev); |
1364 | if (err) | |
1365 | goto clean_load; | |
1366 | ||
5d47f6c8 | 1367 | pci_save_state(pdev); |
9603b61d JM |
1368 | return 0; |
1369 | ||
feae9087 | 1370 | clean_load: |
59211bd3 | 1371 | mlx5_unload_one(dev, priv, true); |
ac6ea6e8 | 1372 | clean_health: |
59211bd3 | 1373 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1374 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1375 | close_pci: |
1376 | mlx5_pci_close(dev, priv); | |
d9aaed83 AK |
1377 | clean_srcu: |
1378 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1379 | cleanup_srcu_struct(&priv->pfault_srcu); | |
a31208b1 | 1380 | clean_dev: |
d9aaed83 | 1381 | #endif |
a31208b1 | 1382 | pci_set_drvdata(pdev, NULL); |
feae9087 | 1383 | devlink_free(devlink); |
a31208b1 | 1384 | |
9603b61d JM |
1385 | return err; |
1386 | } | |
a31208b1 | 1387 | |
9603b61d JM |
1388 | static void remove_one(struct pci_dev *pdev) |
1389 | { | |
1390 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1391 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1392 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1393 | |
feae9087 | 1394 | devlink_unregister(devlink); |
737a234b MHY |
1395 | mlx5_unregister_device(dev); |
1396 | ||
59211bd3 | 1397 | if (mlx5_unload_one(dev, priv, true)) { |
a31208b1 | 1398 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); |
ac6ea6e8 | 1399 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1400 | return; |
1401 | } | |
737a234b | 1402 | |
59211bd3 | 1403 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1404 | mlx5_health_cleanup(dev); |
a31208b1 | 1405 | mlx5_pci_close(dev, priv); |
d9aaed83 AK |
1406 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1407 | cleanup_srcu_struct(&priv->pfault_srcu); | |
1408 | #endif | |
a31208b1 | 1409 | pci_set_drvdata(pdev, NULL); |
feae9087 | 1410 | devlink_free(devlink); |
9603b61d JM |
1411 | } |
1412 | ||
89d44f0a MD |
1413 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1414 | pci_channel_state_t state) | |
1415 | { | |
1416 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1417 | struct mlx5_priv *priv = &dev->priv; | |
1418 | ||
1419 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
04c0c1ab | 1420 | |
8812c24d | 1421 | mlx5_enter_error_state(dev, false); |
59211bd3 | 1422 | mlx5_unload_one(dev, priv, false); |
5d47f6c8 | 1423 | /* In case of kernel call drain the health wq */ |
05ac2c0b | 1424 | if (state) { |
5e44fca5 | 1425 | mlx5_drain_health_wq(dev); |
05ac2c0b MHY |
1426 | mlx5_pci_disable_device(dev); |
1427 | } | |
1428 | ||
89d44f0a MD |
1429 | return state == pci_channel_io_perm_failure ? |
1430 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1431 | } | |
1432 | ||
d57847dc DJ |
1433 | /* wait for the device to show vital signs by waiting |
1434 | * for the health counter to start counting. | |
89d44f0a | 1435 | */ |
d57847dc | 1436 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1437 | { |
1438 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1439 | struct mlx5_core_health *health = &dev->priv.health; | |
1440 | const int niter = 100; | |
d57847dc | 1441 | u32 last_count = 0; |
89d44f0a | 1442 | u32 count; |
89d44f0a MD |
1443 | int i; |
1444 | ||
89d44f0a MD |
1445 | for (i = 0; i < niter; i++) { |
1446 | count = ioread32be(health->health_counter); | |
1447 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1448 | if (last_count && last_count != count) { |
1449 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1450 | return 0; | |
1451 | } | |
1452 | last_count = count; | |
89d44f0a MD |
1453 | } |
1454 | msleep(50); | |
1455 | } | |
1456 | ||
d57847dc | 1457 | return -ETIMEDOUT; |
89d44f0a MD |
1458 | } |
1459 | ||
1061c90f | 1460 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1461 | { |
1462 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1463 | int err; |
1464 | ||
1465 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1466 | ||
1061c90f | 1467 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1468 | if (err) { |
1061c90f MHY |
1469 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1470 | , __func__, err); | |
1471 | return PCI_ERS_RESULT_DISCONNECT; | |
1472 | } | |
1473 | ||
1474 | pci_set_master(pdev); | |
1475 | pci_restore_state(pdev); | |
5d47f6c8 | 1476 | pci_save_state(pdev); |
1061c90f MHY |
1477 | |
1478 | if (wait_vital(pdev)) { | |
d57847dc | 1479 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1480 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1481 | } |
89d44f0a | 1482 | |
1061c90f MHY |
1483 | return PCI_ERS_RESULT_RECOVERED; |
1484 | } | |
1485 | ||
1061c90f MHY |
1486 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1487 | { | |
1488 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1489 | struct mlx5_priv *priv = &dev->priv; | |
1490 | int err; | |
1491 | ||
1492 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1493 | ||
59211bd3 | 1494 | err = mlx5_load_one(dev, priv, false); |
89d44f0a MD |
1495 | if (err) |
1496 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1497 | , __func__, err); | |
1498 | else | |
1499 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1500 | } | |
1501 | ||
1502 | static const struct pci_error_handlers mlx5_err_handler = { | |
1503 | .error_detected = mlx5_pci_err_detected, | |
1504 | .slot_reset = mlx5_pci_slot_reset, | |
1505 | .resume = mlx5_pci_resume | |
1506 | }; | |
1507 | ||
8812c24d MD |
1508 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1509 | { | |
1510 | int ret; | |
1511 | ||
1512 | if (!MLX5_CAP_GEN(dev, force_teardown)) { | |
1513 | mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); | |
1514 | return -EOPNOTSUPP; | |
1515 | } | |
1516 | ||
1517 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1518 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1519 | return -EAGAIN; | |
1520 | } | |
1521 | ||
1522 | ret = mlx5_cmd_force_teardown_hca(dev); | |
1523 | if (ret) { | |
1524 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1525 | return ret; | |
1526 | } | |
1527 | ||
1528 | mlx5_enter_error_state(dev, true); | |
1529 | ||
1530 | return 0; | |
1531 | } | |
1532 | ||
5fc7197d MD |
1533 | static void shutdown(struct pci_dev *pdev) |
1534 | { | |
1535 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1536 | struct mlx5_priv *priv = &dev->priv; | |
8812c24d | 1537 | int err; |
5fc7197d MD |
1538 | |
1539 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
1540 | /* Notify mlx5 clients that the kernel is being shut down */ | |
1541 | set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); | |
8812c24d MD |
1542 | err = mlx5_try_fast_unload(dev); |
1543 | if (err) | |
1544 | mlx5_unload_one(dev, priv, false); | |
5fc7197d MD |
1545 | mlx5_pci_disable_device(dev); |
1546 | } | |
1547 | ||
9603b61d | 1548 | static const struct pci_device_id mlx5_core_pci_table[] = { |
fc50db98 EC |
1549 | { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */ |
1550 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ | |
1551 | { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */ | |
1552 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ | |
1553 | { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */ | |
1554 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ | |
7092fe86 | 1555 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1556 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1557 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1558 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1559 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1560 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
2e9d3e83 NO |
1561 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1562 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
9603b61d JM |
1563 | { 0, } |
1564 | }; | |
1565 | ||
1566 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1567 | ||
04c0c1ab MHY |
1568 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1569 | { | |
1570 | mlx5_pci_err_detected(dev->pdev, 0); | |
1571 | } | |
1572 | ||
1573 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1574 | { | |
1575 | mlx5_pci_disable_device(dev); | |
1576 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1577 | mlx5_pci_resume(dev->pdev); | |
1578 | } | |
1579 | ||
9603b61d JM |
1580 | static struct pci_driver mlx5_core_driver = { |
1581 | .name = DRIVER_NAME, | |
1582 | .id_table = mlx5_core_pci_table, | |
1583 | .probe = init_one, | |
89d44f0a | 1584 | .remove = remove_one, |
5fc7197d | 1585 | .shutdown = shutdown, |
fc50db98 EC |
1586 | .err_handler = &mlx5_err_handler, |
1587 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1588 | }; |
e126ba97 | 1589 | |
f663ad98 KH |
1590 | static void mlx5_core_verify_params(void) |
1591 | { | |
1592 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1593 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1594 | prof_sel, | |
1595 | ARRAY_SIZE(profile) - 1, | |
1596 | MLX5_DEFAULT_PROF); | |
1597 | prof_sel = MLX5_DEFAULT_PROF; | |
1598 | } | |
1599 | } | |
1600 | ||
e126ba97 EC |
1601 | static int __init init(void) |
1602 | { | |
1603 | int err; | |
1604 | ||
f663ad98 | 1605 | mlx5_core_verify_params(); |
e126ba97 | 1606 | mlx5_register_debugfs(); |
e126ba97 | 1607 | |
9603b61d JM |
1608 | err = pci_register_driver(&mlx5_core_driver); |
1609 | if (err) | |
ac6ea6e8 | 1610 | goto err_debug; |
9603b61d | 1611 | |
f62b8bb8 AV |
1612 | #ifdef CONFIG_MLX5_CORE_EN |
1613 | mlx5e_init(); | |
1614 | #endif | |
1615 | ||
e126ba97 EC |
1616 | return 0; |
1617 | ||
e126ba97 EC |
1618 | err_debug: |
1619 | mlx5_unregister_debugfs(); | |
1620 | return err; | |
1621 | } | |
1622 | ||
1623 | static void __exit cleanup(void) | |
1624 | { | |
f62b8bb8 AV |
1625 | #ifdef CONFIG_MLX5_CORE_EN |
1626 | mlx5e_cleanup(); | |
1627 | #endif | |
9603b61d | 1628 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1629 | mlx5_unregister_debugfs(); |
1630 | } | |
1631 | ||
1632 | module_init(init); | |
1633 | module_exit(cleanup); |