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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
e126ba97 | 46 | #include <linux/debugfs.h> |
f66f049f | 47 | #include <linux/kmod.h> |
b775516b | 48 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 49 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
f2f3df55 | 55 | #include "lib/eq.h" |
16d76083 | 56 | #include "fs_core.h" |
eeb66cdb | 57 | #include "lib/mpfs.h" |
073bb189 | 58 | #include "eswitch.h" |
52ec462e | 59 | #include "lib/mlx5.h" |
e29341fb | 60 | #include "fpga/core.h" |
05564d0a | 61 | #include "fpga/ipsec.h" |
bebb23e6 | 62 | #include "accel/ipsec.h" |
1ae17322 | 63 | #include "accel/tls.h" |
7c39afb3 | 64 | #include "lib/clock.h" |
358aa5ce | 65 | #include "lib/vxlan.h" |
fadd59fc | 66 | #include "lib/devcom.h" |
24406953 | 67 | #include "diag/fw_tracer.h" |
591905ba | 68 | #include "ecpf.h" |
e126ba97 | 69 | |
e126ba97 | 70 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
048f3143 | 71 | MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); |
e126ba97 EC |
72 | MODULE_LICENSE("Dual BSD/GPL"); |
73 | MODULE_VERSION(DRIVER_VERSION); | |
74 | ||
f663ad98 KH |
75 | unsigned int mlx5_core_debug_mask; |
76 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
77 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
78 | ||
9603b61d | 79 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
80 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
81 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
82 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
83 | ||
8737f818 DJ |
84 | static u32 sw_owner_id[4]; |
85 | ||
f91e6d89 EBE |
86 | enum { |
87 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
88 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
89 | }; | |
90 | ||
9603b61d JM |
91 | static struct mlx5_profile profile[] = { |
92 | [0] = { | |
93 | .mask = 0, | |
94 | }, | |
95 | [1] = { | |
96 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
97 | .log_max_qp = 12, | |
98 | }, | |
99 | [2] = { | |
100 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
101 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 102 | .log_max_qp = 18, |
9603b61d JM |
103 | .mr_cache[0] = { |
104 | .size = 500, | |
105 | .limit = 250 | |
106 | }, | |
107 | .mr_cache[1] = { | |
108 | .size = 500, | |
109 | .limit = 250 | |
110 | }, | |
111 | .mr_cache[2] = { | |
112 | .size = 500, | |
113 | .limit = 250 | |
114 | }, | |
115 | .mr_cache[3] = { | |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[4] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[5] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[6] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[7] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[8] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[9] = { | |
140 | .size = 500, | |
141 | .limit = 250 | |
142 | }, | |
143 | .mr_cache[10] = { | |
144 | .size = 500, | |
145 | .limit = 250 | |
146 | }, | |
147 | .mr_cache[11] = { | |
148 | .size = 500, | |
149 | .limit = 250 | |
150 | }, | |
151 | .mr_cache[12] = { | |
152 | .size = 64, | |
153 | .limit = 32 | |
154 | }, | |
155 | .mr_cache[13] = { | |
156 | .size = 32, | |
157 | .limit = 16 | |
158 | }, | |
159 | .mr_cache[14] = { | |
160 | .size = 16, | |
161 | .limit = 8 | |
162 | }, | |
163 | .mr_cache[15] = { | |
164 | .size = 8, | |
165 | .limit = 4 | |
166 | }, | |
167 | }, | |
168 | }; | |
e126ba97 | 169 | |
6c780a02 EC |
170 | #define FW_INIT_TIMEOUT_MILI 2000 |
171 | #define FW_INIT_WAIT_MS 2 | |
172 | #define FW_PRE_INIT_TIMEOUT_MILI 10000 | |
e3297246 EC |
173 | |
174 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
175 | { | |
176 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
177 | int err = 0; | |
178 | ||
179 | while (fw_initializing(dev)) { | |
180 | if (time_after(jiffies, end)) { | |
181 | err = -EBUSY; | |
182 | break; | |
183 | } | |
184 | msleep(FW_INIT_WAIT_MS); | |
185 | } | |
186 | ||
187 | return err; | |
188 | } | |
189 | ||
012e50e1 HN |
190 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
191 | { | |
192 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
193 | driver_version); | |
194 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
195 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
196 | int remaining_size = driver_ver_sz; | |
197 | char *string; | |
198 | ||
199 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
200 | return; | |
201 | ||
202 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
203 | ||
204 | strncpy(string, "Linux", remaining_size); | |
205 | ||
206 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
207 | strncat(string, ",", remaining_size); | |
208 | ||
209 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
210 | strncat(string, DRIVER_NAME, remaining_size); | |
211 | ||
212 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
213 | strncat(string, ",", remaining_size); | |
214 | ||
215 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
216 | strncat(string, DRIVER_VERSION, remaining_size); | |
217 | ||
218 | /*Send the command*/ | |
219 | MLX5_SET(set_driver_version_in, in, opcode, | |
220 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
221 | ||
222 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
223 | } | |
224 | ||
e126ba97 EC |
225 | static int set_dma_caps(struct pci_dev *pdev) |
226 | { | |
227 | int err; | |
228 | ||
229 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
230 | if (err) { | |
1a91de28 | 231 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
232 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
233 | if (err) { | |
1a91de28 | 234 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
235 | return err; |
236 | } | |
237 | } | |
238 | ||
239 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
240 | if (err) { | |
241 | dev_warn(&pdev->dev, | |
1a91de28 | 242 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
243 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
244 | if (err) { | |
245 | dev_err(&pdev->dev, | |
1a91de28 | 246 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
247 | return err; |
248 | } | |
249 | } | |
250 | ||
251 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
252 | return err; | |
253 | } | |
254 | ||
89d44f0a MD |
255 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
256 | { | |
257 | struct pci_dev *pdev = dev->pdev; | |
258 | int err = 0; | |
259 | ||
260 | mutex_lock(&dev->pci_status_mutex); | |
261 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
262 | err = pci_enable_device(pdev); | |
263 | if (!err) | |
264 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
265 | } | |
266 | mutex_unlock(&dev->pci_status_mutex); | |
267 | ||
268 | return err; | |
269 | } | |
270 | ||
271 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
272 | { | |
273 | struct pci_dev *pdev = dev->pdev; | |
274 | ||
275 | mutex_lock(&dev->pci_status_mutex); | |
276 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
277 | pci_disable_device(pdev); | |
278 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
279 | } | |
280 | mutex_unlock(&dev->pci_status_mutex); | |
281 | } | |
282 | ||
e126ba97 EC |
283 | static int request_bar(struct pci_dev *pdev) |
284 | { | |
285 | int err = 0; | |
286 | ||
287 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 288 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
289 | return -ENODEV; |
290 | } | |
291 | ||
292 | err = pci_request_regions(pdev, DRIVER_NAME); | |
293 | if (err) | |
294 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
295 | ||
296 | return err; | |
297 | } | |
298 | ||
299 | static void release_bar(struct pci_dev *pdev) | |
300 | { | |
301 | pci_release_regions(pdev); | |
302 | } | |
303 | ||
bd10838a | 304 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
305 | u8 he; |
306 | u8 rsvd[15]; | |
307 | }; | |
308 | ||
87b8de49 EC |
309 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
310 | ||
311 | enum { | |
c7a08ac7 EC |
312 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
313 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
314 | }; |
315 | ||
2974ab6e | 316 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
317 | { |
318 | switch (size) { | |
319 | case 128: | |
320 | return 0; | |
321 | case 256: | |
322 | return 1; | |
323 | case 512: | |
324 | return 2; | |
325 | case 1024: | |
326 | return 3; | |
327 | case 2048: | |
328 | return 4; | |
329 | case 4096: | |
330 | return 5; | |
331 | default: | |
2974ab6e | 332 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
333 | return 0; |
334 | } | |
335 | } | |
336 | ||
b06e7de8 LR |
337 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
338 | enum mlx5_cap_type cap_type, | |
339 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 340 | { |
b775516b EC |
341 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
342 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
343 | void *out, *hca_caps; |
344 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
345 | int err; |
346 | ||
b775516b EC |
347 | memset(in, 0, sizeof(in)); |
348 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 349 | if (!out) |
e126ba97 | 350 | return -ENOMEM; |
938fe83c | 351 | |
b775516b EC |
352 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
353 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
354 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 355 | if (err) { |
938fe83c SM |
356 | mlx5_core_warn(dev, |
357 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
358 | cap_type, cap_mode, err); | |
e126ba97 EC |
359 | goto query_ex; |
360 | } | |
c7a08ac7 | 361 | |
938fe83c SM |
362 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
363 | ||
364 | switch (cap_mode) { | |
365 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 366 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
367 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
368 | break; | |
369 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 370 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
371 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
372 | break; | |
373 | default: | |
374 | mlx5_core_warn(dev, | |
375 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
376 | cap_type, cap_mode); | |
377 | err = -EINVAL; | |
378 | break; | |
379 | } | |
c7a08ac7 EC |
380 | query_ex: |
381 | kfree(out); | |
382 | return err; | |
383 | } | |
384 | ||
b06e7de8 LR |
385 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
386 | { | |
387 | int ret; | |
388 | ||
389 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
390 | if (ret) | |
391 | return ret; | |
392 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
393 | } | |
394 | ||
f91e6d89 | 395 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 396 | { |
c4f287c4 | 397 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 398 | |
b775516b | 399 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 400 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 401 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
402 | } |
403 | ||
f91e6d89 EBE |
404 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
405 | { | |
406 | void *set_ctx; | |
407 | void *set_hca_cap; | |
408 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
409 | int req_endianness; | |
410 | int err; | |
411 | ||
412 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 413 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
414 | if (err) |
415 | return err; | |
416 | } else { | |
417 | return 0; | |
418 | } | |
419 | ||
420 | req_endianness = | |
421 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 422 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
423 | |
424 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
425 | return 0; | |
426 | ||
427 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
428 | if (!set_ctx) | |
429 | return -ENOMEM; | |
430 | ||
431 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
432 | ||
433 | /* Set requestor to host endianness */ | |
bd10838a | 434 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
435 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
436 | ||
437 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
438 | ||
439 | kfree(set_ctx); | |
440 | return err; | |
441 | } | |
442 | ||
46861e3e MS |
443 | static int handle_hca_cap_odp(struct mlx5_core_dev *dev) |
444 | { | |
46861e3e | 445 | void *set_hca_cap; |
224d71cc LR |
446 | void *set_ctx; |
447 | int set_sz; | |
fca22e7e | 448 | bool do_set = false; |
46861e3e MS |
449 | int err; |
450 | ||
37b6bb77 LR |
451 | if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || |
452 | !MLX5_CAP_GEN(dev, pg)) | |
46861e3e MS |
453 | return 0; |
454 | ||
455 | err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); | |
456 | if (err) | |
457 | return err; | |
458 | ||
224d71cc | 459 | set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
46861e3e MS |
460 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
461 | if (!set_ctx) | |
462 | return -ENOMEM; | |
463 | ||
464 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
465 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], | |
466 | MLX5_ST_SZ_BYTES(odp_cap)); | |
467 | ||
fca22e7e MS |
468 | #define ODP_CAP_SET_MAX(dev, field) \ |
469 | do { \ | |
470 | u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ | |
471 | if (_res) { \ | |
472 | do_set = true; \ | |
473 | MLX5_SET(odp_cap, set_hca_cap, field, _res); \ | |
474 | } \ | |
475 | } while (0) | |
476 | ||
477 | ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); | |
478 | ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); | |
479 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); | |
480 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); | |
481 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); | |
482 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); | |
483 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); | |
484 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); | |
485 | ||
486 | if (do_set) | |
487 | err = set_caps(dev, set_ctx, set_sz, | |
488 | MLX5_SET_HCA_CAP_OP_MOD_ODP); | |
46861e3e MS |
489 | |
490 | kfree(set_ctx); | |
fca22e7e | 491 | |
46861e3e MS |
492 | return err; |
493 | } | |
494 | ||
c7a08ac7 EC |
495 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
496 | { | |
b775516b | 497 | void *set_ctx = NULL; |
c7a08ac7 | 498 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 499 | int err = -ENOMEM; |
b775516b | 500 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 501 | void *set_hca_cap; |
c7a08ac7 | 502 | |
b775516b | 503 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 504 | if (!set_ctx) |
e126ba97 | 505 | goto query_ex; |
e126ba97 | 506 | |
b06e7de8 | 507 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
508 | if (err) |
509 | goto query_ex; | |
510 | ||
938fe83c SM |
511 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
512 | capability); | |
701052c5 | 513 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
514 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
515 | ||
516 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 517 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 518 | 128); |
c7a08ac7 | 519 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 520 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 521 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 522 | |
883371c4 NO |
523 | /* Check log_max_qp from HCA caps to set in current profile */ |
524 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
525 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
526 | profile[prof_sel].log_max_qp, | |
527 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
528 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
529 | } | |
c7a08ac7 | 530 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
531 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
532 | prof->log_max_qp); | |
c7a08ac7 | 533 | |
938fe83c SM |
534 | /* disable cmdif checksum */ |
535 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 536 | |
91828bd8 MD |
537 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
538 | * than 4K. | |
539 | */ | |
540 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
541 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
542 | ||
fe1e1876 CS |
543 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
544 | ||
f32f5bd2 DJ |
545 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
546 | MLX5_SET(cmd_hca_cap, | |
547 | set_hca_cap, | |
548 | cache_line_128byte, | |
c67f100e | 549 | cache_line_size() >= 128 ? 1 : 0); |
f32f5bd2 | 550 | |
dd44572a MS |
551 | if (MLX5_CAP_GEN_MAX(dev, dct)) |
552 | MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); | |
553 | ||
c4b76d8d DJ |
554 | if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) |
555 | MLX5_SET(cmd_hca_cap, | |
556 | set_hca_cap, | |
557 | num_vhca_ports, | |
558 | MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); | |
559 | ||
f91e6d89 EBE |
560 | err = set_caps(dev, set_ctx, set_sz, |
561 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 562 | |
e126ba97 | 563 | query_ex: |
e126ba97 | 564 | kfree(set_ctx); |
e126ba97 EC |
565 | return err; |
566 | } | |
567 | ||
37b6bb77 LR |
568 | static int set_hca_cap(struct mlx5_core_dev *dev) |
569 | { | |
37b6bb77 LR |
570 | int err; |
571 | ||
572 | err = handle_hca_cap(dev); | |
573 | if (err) { | |
98a8e6fc | 574 | mlx5_core_err(dev, "handle_hca_cap failed\n"); |
37b6bb77 LR |
575 | goto out; |
576 | } | |
577 | ||
578 | err = handle_hca_cap_atomic(dev); | |
579 | if (err) { | |
98a8e6fc | 580 | mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); |
37b6bb77 LR |
581 | goto out; |
582 | } | |
583 | ||
584 | err = handle_hca_cap_odp(dev); | |
585 | if (err) { | |
98a8e6fc | 586 | mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); |
37b6bb77 LR |
587 | goto out; |
588 | } | |
589 | ||
590 | out: | |
591 | return err; | |
592 | } | |
593 | ||
e126ba97 EC |
594 | static int set_hca_ctrl(struct mlx5_core_dev *dev) |
595 | { | |
bd10838a OG |
596 | struct mlx5_reg_host_endianness he_in; |
597 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
598 | int err; |
599 | ||
fc50db98 EC |
600 | if (!mlx5_core_is_pf(dev)) |
601 | return 0; | |
602 | ||
e126ba97 EC |
603 | memset(&he_in, 0, sizeof(he_in)); |
604 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
605 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
606 | &he_out, sizeof(he_out), | |
607 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
608 | return err; | |
609 | } | |
610 | ||
c85023e1 HN |
611 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
612 | { | |
613 | int ret = 0; | |
614 | ||
615 | /* Disable local_lb by default */ | |
8978cc92 | 616 | if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) |
c85023e1 HN |
617 | ret = mlx5_nic_vport_update_local_lb(dev, false); |
618 | ||
619 | return ret; | |
620 | } | |
621 | ||
0b107106 | 622 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 623 | { |
c4f287c4 SM |
624 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
625 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 626 | |
0b107106 EC |
627 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
628 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
629 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
630 | dev->caps.embedded_cpu); | |
c4f287c4 | 631 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
632 | } |
633 | ||
0b107106 | 634 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 635 | { |
c4f287c4 SM |
636 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
637 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 638 | |
0b107106 EC |
639 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
640 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
641 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
642 | dev->caps.embedded_cpu); | |
c4f287c4 | 643 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
644 | } |
645 | ||
4a0475d5 ML |
646 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, |
647 | struct ptp_system_timestamp *sts) | |
b0844444 EBE |
648 | { |
649 | u32 timer_h, timer_h1, timer_l; | |
650 | ||
651 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
4a0475d5 | 652 | ptp_read_system_prets(sts); |
b0844444 | 653 | timer_l = ioread32be(&dev->iseg->internal_timer_l); |
4a0475d5 | 654 | ptp_read_system_postts(sts); |
b0844444 | 655 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); |
4a0475d5 ML |
656 | if (timer_h != timer_h1) { |
657 | /* wrap around */ | |
658 | ptp_read_system_prets(sts); | |
b0844444 | 659 | timer_l = ioread32be(&dev->iseg->internal_timer_l); |
4a0475d5 ML |
660 | ptp_read_system_postts(sts); |
661 | } | |
b0844444 | 662 | |
a5a1d1c2 | 663 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
664 | } |
665 | ||
f62b8bb8 AV |
666 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
667 | { | |
c4f287c4 SM |
668 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
669 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 670 | u32 sup_issi; |
c4f287c4 | 671 | int err; |
f62b8bb8 AV |
672 | |
673 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
674 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
675 | query_out, sizeof(query_out)); | |
f62b8bb8 | 676 | if (err) { |
c4f287c4 SM |
677 | u32 syndrome; |
678 | u8 status; | |
679 | ||
680 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
681 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
682 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
683 | err, status, syndrome); | |
684 | return err; | |
f62b8bb8 AV |
685 | } |
686 | ||
f9c14e46 KH |
687 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
688 | dev->issi = 0; | |
689 | return 0; | |
f62b8bb8 AV |
690 | } |
691 | ||
692 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
693 | ||
694 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
695 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
696 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
697 | |
698 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
699 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
700 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
701 | set_out, sizeof(set_out)); | |
f62b8bb8 | 702 | if (err) { |
f9c14e46 KH |
703 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
704 | err); | |
f62b8bb8 AV |
705 | return err; |
706 | } | |
707 | ||
708 | dev->issi = 1; | |
709 | ||
710 | return 0; | |
e74a1db0 | 711 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
712 | return 0; |
713 | } | |
714 | ||
9eb78923 | 715 | return -EOPNOTSUPP; |
f62b8bb8 | 716 | } |
f62b8bb8 | 717 | |
11f3b84d SM |
718 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, |
719 | const struct pci_device_id *id) | |
a31208b1 | 720 | { |
868bc06b | 721 | struct mlx5_priv *priv = &dev->priv; |
a31208b1 | 722 | int err = 0; |
e126ba97 | 723 | |
11f3b84d | 724 | priv->pci_dev_data = id->driver_data; |
e126ba97 | 725 | |
11f3b84d | 726 | pci_set_drvdata(dev->pdev, dev); |
311c7c71 | 727 | |
aa8106f1 | 728 | dev->bar_addr = pci_resource_start(pdev, 0); |
311c7c71 SM |
729 | priv->numa_node = dev_to_node(&dev->pdev->dev); |
730 | ||
89d44f0a | 731 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 732 | if (err) { |
98a8e6fc | 733 | mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); |
11f3b84d | 734 | return err; |
e126ba97 EC |
735 | } |
736 | ||
737 | err = request_bar(pdev); | |
738 | if (err) { | |
98a8e6fc | 739 | mlx5_core_err(dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
740 | goto err_disable; |
741 | } | |
742 | ||
743 | pci_set_master(pdev); | |
744 | ||
745 | err = set_dma_caps(pdev); | |
746 | if (err) { | |
98a8e6fc | 747 | mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); |
e126ba97 EC |
748 | goto err_clr_master; |
749 | } | |
750 | ||
ce4eee53 MG |
751 | if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && |
752 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && | |
753 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) | |
754 | mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); | |
755 | ||
aa8106f1 | 756 | dev->iseg_base = dev->bar_addr; |
e126ba97 EC |
757 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); |
758 | if (!dev->iseg) { | |
759 | err = -ENOMEM; | |
98a8e6fc | 760 | mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); |
e126ba97 EC |
761 | goto err_clr_master; |
762 | } | |
a31208b1 MD |
763 | |
764 | return 0; | |
765 | ||
766 | err_clr_master: | |
767 | pci_clear_master(dev->pdev); | |
768 | release_bar(dev->pdev); | |
769 | err_disable: | |
89d44f0a | 770 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
771 | return err; |
772 | } | |
773 | ||
868bc06b | 774 | static void mlx5_pci_close(struct mlx5_core_dev *dev) |
a31208b1 MD |
775 | { |
776 | iounmap(dev->iseg); | |
777 | pci_clear_master(dev->pdev); | |
778 | release_bar(dev->pdev); | |
89d44f0a | 779 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
780 | } |
781 | ||
868bc06b | 782 | static int mlx5_init_once(struct mlx5_core_dev *dev) |
59211bd3 | 783 | { |
59211bd3 MHY |
784 | int err; |
785 | ||
868bc06b SM |
786 | dev->priv.devcom = mlx5_devcom_register_device(dev); |
787 | if (IS_ERR(dev->priv.devcom)) | |
98a8e6fc HN |
788 | mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", |
789 | dev->priv.devcom); | |
fadd59fc | 790 | |
59211bd3 MHY |
791 | err = mlx5_query_board_id(dev); |
792 | if (err) { | |
98a8e6fc | 793 | mlx5_core_err(dev, "query board id failed\n"); |
fadd59fc | 794 | goto err_devcom; |
59211bd3 MHY |
795 | } |
796 | ||
f2f3df55 | 797 | err = mlx5_eq_table_init(dev); |
59211bd3 | 798 | if (err) { |
98a8e6fc | 799 | mlx5_core_err(dev, "failed to initialize eq\n"); |
fadd59fc | 800 | goto err_devcom; |
59211bd3 MHY |
801 | } |
802 | ||
69c1280b SM |
803 | err = mlx5_events_init(dev); |
804 | if (err) { | |
98a8e6fc | 805 | mlx5_core_err(dev, "failed to initialize events\n"); |
69c1280b SM |
806 | goto err_eq_cleanup; |
807 | } | |
808 | ||
02d92f79 | 809 | err = mlx5_cq_debugfs_init(dev); |
59211bd3 | 810 | if (err) { |
98a8e6fc | 811 | mlx5_core_err(dev, "failed to initialize cq debugfs\n"); |
69c1280b | 812 | goto err_events_cleanup; |
59211bd3 MHY |
813 | } |
814 | ||
815 | mlx5_init_qp_table(dev); | |
816 | ||
59211bd3 MHY |
817 | mlx5_init_mkey_table(dev); |
818 | ||
52ec462e IT |
819 | mlx5_init_reserved_gids(dev); |
820 | ||
7c39afb3 FD |
821 | mlx5_init_clock(dev); |
822 | ||
358aa5ce SM |
823 | dev->vxlan = mlx5_vxlan_create(dev); |
824 | ||
59211bd3 MHY |
825 | err = mlx5_init_rl_table(dev); |
826 | if (err) { | |
98a8e6fc | 827 | mlx5_core_err(dev, "Failed to init rate limiting\n"); |
59211bd3 MHY |
828 | goto err_tables_cleanup; |
829 | } | |
830 | ||
eeb66cdb SM |
831 | err = mlx5_mpfs_init(dev); |
832 | if (err) { | |
98a8e6fc | 833 | mlx5_core_err(dev, "Failed to init l2 table %d\n", err); |
eeb66cdb SM |
834 | goto err_rl_cleanup; |
835 | } | |
836 | ||
c2d6e31a MHY |
837 | err = mlx5_eswitch_init(dev); |
838 | if (err) { | |
98a8e6fc | 839 | mlx5_core_err(dev, "Failed to init eswitch %d\n", err); |
eeb66cdb | 840 | goto err_mpfs_cleanup; |
c2d6e31a | 841 | } |
c2d6e31a MHY |
842 | |
843 | err = mlx5_sriov_init(dev); | |
844 | if (err) { | |
98a8e6fc | 845 | mlx5_core_err(dev, "Failed to init sriov %d\n", err); |
c2d6e31a MHY |
846 | goto err_eswitch_cleanup; |
847 | } | |
848 | ||
9410733c IT |
849 | err = mlx5_fpga_init(dev); |
850 | if (err) { | |
98a8e6fc | 851 | mlx5_core_err(dev, "Failed to init fpga device %d\n", err); |
9410733c IT |
852 | goto err_sriov_cleanup; |
853 | } | |
854 | ||
24406953 FD |
855 | dev->tracer = mlx5_fw_tracer_create(dev); |
856 | ||
59211bd3 MHY |
857 | return 0; |
858 | ||
9410733c IT |
859 | err_sriov_cleanup: |
860 | mlx5_sriov_cleanup(dev); | |
c2d6e31a | 861 | err_eswitch_cleanup: |
c2d6e31a | 862 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 863 | err_mpfs_cleanup: |
eeb66cdb | 864 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 865 | err_rl_cleanup: |
c2d6e31a | 866 | mlx5_cleanup_rl_table(dev); |
59211bd3 | 867 | err_tables_cleanup: |
358aa5ce | 868 | mlx5_vxlan_destroy(dev->vxlan); |
59211bd3 | 869 | mlx5_cleanup_mkey_table(dev); |
59211bd3 | 870 | mlx5_cleanup_qp_table(dev); |
02d92f79 | 871 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b SM |
872 | err_events_cleanup: |
873 | mlx5_events_cleanup(dev); | |
59211bd3 | 874 | err_eq_cleanup: |
f2f3df55 | 875 | mlx5_eq_table_cleanup(dev); |
fadd59fc AH |
876 | err_devcom: |
877 | mlx5_devcom_unregister_device(dev->priv.devcom); | |
59211bd3 | 878 | |
59211bd3 MHY |
879 | return err; |
880 | } | |
881 | ||
882 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
883 | { | |
24406953 | 884 | mlx5_fw_tracer_destroy(dev->tracer); |
9410733c | 885 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 886 | mlx5_sriov_cleanup(dev); |
c2d6e31a | 887 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 888 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 889 | mlx5_cleanup_rl_table(dev); |
358aa5ce | 890 | mlx5_vxlan_destroy(dev->vxlan); |
7c39afb3 | 891 | mlx5_cleanup_clock(dev); |
52ec462e | 892 | mlx5_cleanup_reserved_gids(dev); |
59211bd3 | 893 | mlx5_cleanup_mkey_table(dev); |
59211bd3 | 894 | mlx5_cleanup_qp_table(dev); |
02d92f79 | 895 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b | 896 | mlx5_events_cleanup(dev); |
f2f3df55 | 897 | mlx5_eq_table_cleanup(dev); |
fadd59fc | 898 | mlx5_devcom_unregister_device(dev->priv.devcom); |
59211bd3 MHY |
899 | } |
900 | ||
e161105e | 901 | static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) |
a31208b1 | 902 | { |
a31208b1 MD |
903 | int err; |
904 | ||
98a8e6fc HN |
905 | mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
906 | fw_rev_min(dev), fw_rev_sub(dev)); | |
e126ba97 | 907 | |
00c6bcb0 TG |
908 | /* Only PFs hold the relevant PCIe information for this query */ |
909 | if (mlx5_core_is_pf(dev)) | |
910 | pcie_print_link_status(dev->pdev); | |
911 | ||
6c780a02 EC |
912 | /* wait for firmware to accept initialization segments configurations |
913 | */ | |
914 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); | |
915 | if (err) { | |
98a8e6fc HN |
916 | mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", |
917 | FW_PRE_INIT_TIMEOUT_MILI); | |
e161105e | 918 | return err; |
6c780a02 EC |
919 | } |
920 | ||
e126ba97 EC |
921 | err = mlx5_cmd_init(dev); |
922 | if (err) { | |
98a8e6fc | 923 | mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); |
e161105e | 924 | return err; |
e126ba97 EC |
925 | } |
926 | ||
e3297246 EC |
927 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
928 | if (err) { | |
98a8e6fc HN |
929 | mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", |
930 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 931 | goto err_cmd_cleanup; |
e3297246 EC |
932 | } |
933 | ||
0b107106 | 934 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b | 935 | if (err) { |
98a8e6fc | 936 | mlx5_core_err(dev, "enable hca failed\n"); |
59211bd3 | 937 | goto err_cmd_cleanup; |
cd23b14b EC |
938 | } |
939 | ||
f62b8bb8 AV |
940 | err = mlx5_core_set_issi(dev); |
941 | if (err) { | |
98a8e6fc | 942 | mlx5_core_err(dev, "failed to set issi\n"); |
f62b8bb8 AV |
943 | goto err_disable_hca; |
944 | } | |
f62b8bb8 | 945 | |
cd23b14b EC |
946 | err = mlx5_satisfy_startup_pages(dev, 1); |
947 | if (err) { | |
98a8e6fc | 948 | mlx5_core_err(dev, "failed to allocate boot pages\n"); |
cd23b14b EC |
949 | goto err_disable_hca; |
950 | } | |
951 | ||
e126ba97 EC |
952 | err = set_hca_ctrl(dev); |
953 | if (err) { | |
98a8e6fc | 954 | mlx5_core_err(dev, "set_hca_ctrl failed\n"); |
cd23b14b | 955 | goto reclaim_boot_pages; |
e126ba97 EC |
956 | } |
957 | ||
37b6bb77 | 958 | err = set_hca_cap(dev); |
f91e6d89 | 959 | if (err) { |
98a8e6fc | 960 | mlx5_core_err(dev, "set_hca_cap failed\n"); |
46861e3e MS |
961 | goto reclaim_boot_pages; |
962 | } | |
963 | ||
cd23b14b | 964 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 965 | if (err) { |
98a8e6fc | 966 | mlx5_core_err(dev, "failed to allocate init pages\n"); |
cd23b14b | 967 | goto reclaim_boot_pages; |
e126ba97 EC |
968 | } |
969 | ||
8737f818 | 970 | err = mlx5_cmd_init_hca(dev, sw_owner_id); |
e126ba97 | 971 | if (err) { |
98a8e6fc | 972 | mlx5_core_err(dev, "init hca failed\n"); |
0cf53c12 | 973 | goto reclaim_boot_pages; |
e126ba97 EC |
974 | } |
975 | ||
012e50e1 HN |
976 | mlx5_set_driver_version(dev); |
977 | ||
e126ba97 EC |
978 | mlx5_start_health_poll(dev); |
979 | ||
bba1574c DJ |
980 | err = mlx5_query_hca_caps(dev); |
981 | if (err) { | |
98a8e6fc | 982 | mlx5_core_err(dev, "query hca failed\n"); |
e161105e | 983 | goto stop_health; |
bba1574c DJ |
984 | } |
985 | ||
e161105e SM |
986 | return 0; |
987 | ||
988 | stop_health: | |
989 | mlx5_stop_health_poll(dev, boot); | |
990 | reclaim_boot_pages: | |
991 | mlx5_reclaim_startup_pages(dev); | |
992 | err_disable_hca: | |
993 | mlx5_core_disable_hca(dev, 0); | |
994 | err_cmd_cleanup: | |
995 | mlx5_cmd_cleanup(dev); | |
996 | ||
997 | return err; | |
998 | } | |
999 | ||
1000 | static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) | |
1001 | { | |
1002 | int err; | |
1003 | ||
1004 | mlx5_stop_health_poll(dev, boot); | |
1005 | err = mlx5_cmd_teardown_hca(dev); | |
1006 | if (err) { | |
98a8e6fc | 1007 | mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); |
e161105e | 1008 | return err; |
e126ba97 | 1009 | } |
e161105e SM |
1010 | mlx5_reclaim_startup_pages(dev); |
1011 | mlx5_core_disable_hca(dev, 0); | |
1012 | mlx5_cmd_cleanup(dev); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
a80d1b68 | 1017 | static int mlx5_load(struct mlx5_core_dev *dev) |
e161105e | 1018 | { |
e161105e | 1019 | int err; |
e126ba97 | 1020 | |
01187175 | 1021 | dev->priv.uar = mlx5_get_uars_page(dev); |
72f36be0 | 1022 | if (IS_ERR(dev->priv.uar)) { |
98a8e6fc | 1023 | mlx5_core_err(dev, "Failed allocating uar, aborting\n"); |
72f36be0 | 1024 | err = PTR_ERR(dev->priv.uar); |
a80d1b68 | 1025 | return err; |
e126ba97 EC |
1026 | } |
1027 | ||
69c1280b | 1028 | mlx5_events_start(dev); |
0cf53c12 SM |
1029 | mlx5_pagealloc_start(dev); |
1030 | ||
c8e21b3b | 1031 | err = mlx5_eq_table_create(dev); |
e126ba97 | 1032 | if (err) { |
98a8e6fc | 1033 | mlx5_core_err(dev, "Failed to create EQs\n"); |
c8e21b3b | 1034 | goto err_eq_table; |
e126ba97 EC |
1035 | } |
1036 | ||
24406953 FD |
1037 | err = mlx5_fw_tracer_init(dev->tracer); |
1038 | if (err) { | |
98a8e6fc | 1039 | mlx5_core_err(dev, "Failed to init FW tracer\n"); |
24406953 FD |
1040 | goto err_fw_tracer; |
1041 | } | |
1042 | ||
04e87170 MB |
1043 | err = mlx5_fpga_device_start(dev); |
1044 | if (err) { | |
98a8e6fc | 1045 | mlx5_core_err(dev, "fpga device start failed %d\n", err); |
04e87170 MB |
1046 | goto err_fpga_start; |
1047 | } | |
1048 | ||
1049 | err = mlx5_accel_ipsec_init(dev); | |
1050 | if (err) { | |
98a8e6fc | 1051 | mlx5_core_err(dev, "IPSec device start failed %d\n", err); |
04e87170 MB |
1052 | goto err_ipsec_start; |
1053 | } | |
1054 | ||
1ae17322 IL |
1055 | err = mlx5_accel_tls_init(dev); |
1056 | if (err) { | |
98a8e6fc | 1057 | mlx5_core_err(dev, "TLS device start failed %d\n", err); |
1ae17322 IL |
1058 | goto err_tls_start; |
1059 | } | |
1060 | ||
86d722ad | 1061 | err = mlx5_init_fs(dev); |
59211bd3 | 1062 | if (err) { |
98a8e6fc | 1063 | mlx5_core_err(dev, "Failed to init flow steering\n"); |
c85023e1 | 1064 | goto err_fs; |
59211bd3 | 1065 | } |
e126ba97 | 1066 | |
c85023e1 | 1067 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1068 | if (err) { |
98a8e6fc | 1069 | mlx5_core_err(dev, "Failed to set hca defaults\n"); |
87883929 | 1070 | goto err_sriov; |
86d722ad | 1071 | } |
1466cc5b | 1072 | |
c2d6e31a | 1073 | err = mlx5_sriov_attach(dev); |
fc50db98 | 1074 | if (err) { |
98a8e6fc | 1075 | mlx5_core_err(dev, "sriov init failed %d\n", err); |
fc50db98 EC |
1076 | goto err_sriov; |
1077 | } | |
1078 | ||
22e939a9 BW |
1079 | err = mlx5_ec_init(dev); |
1080 | if (err) { | |
98a8e6fc | 1081 | mlx5_core_err(dev, "Failed to init embedded CPU\n"); |
22e939a9 BW |
1082 | goto err_ec; |
1083 | } | |
1084 | ||
e126ba97 EC |
1085 | return 0; |
1086 | ||
22e939a9 | 1087 | err_ec: |
c2d6e31a | 1088 | mlx5_sriov_detach(dev); |
59211bd3 | 1089 | err_sriov: |
86d722ad MG |
1090 | mlx5_cleanup_fs(dev); |
1091 | err_fs: | |
1ae17322 | 1092 | mlx5_accel_tls_cleanup(dev); |
1ae17322 | 1093 | err_tls_start: |
04e87170 | 1094 | mlx5_accel_ipsec_cleanup(dev); |
04e87170 MB |
1095 | err_ipsec_start: |
1096 | mlx5_fpga_device_stop(dev); | |
04e87170 | 1097 | err_fpga_start: |
24406953 | 1098 | mlx5_fw_tracer_cleanup(dev->tracer); |
24406953 | 1099 | err_fw_tracer: |
c8e21b3b | 1100 | mlx5_eq_table_destroy(dev); |
c8e21b3b | 1101 | err_eq_table: |
0cf53c12 | 1102 | mlx5_pagealloc_stop(dev); |
69c1280b | 1103 | mlx5_events_stop(dev); |
868bc06b | 1104 | mlx5_put_uars_page(dev, dev->priv.uar); |
a80d1b68 SM |
1105 | return err; |
1106 | } | |
e126ba97 | 1107 | |
a80d1b68 SM |
1108 | static void mlx5_unload(struct mlx5_core_dev *dev) |
1109 | { | |
1110 | mlx5_ec_cleanup(dev); | |
1111 | mlx5_sriov_detach(dev); | |
1112 | mlx5_cleanup_fs(dev); | |
1113 | mlx5_accel_ipsec_cleanup(dev); | |
1114 | mlx5_accel_tls_cleanup(dev); | |
1115 | mlx5_fpga_device_stop(dev); | |
1116 | mlx5_fw_tracer_cleanup(dev->tracer); | |
1117 | mlx5_eq_table_destroy(dev); | |
1118 | mlx5_pagealloc_stop(dev); | |
1119 | mlx5_events_stop(dev); | |
1120 | mlx5_put_uars_page(dev, dev->priv.uar); | |
1121 | } | |
59211bd3 | 1122 | |
a80d1b68 SM |
1123 | static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) |
1124 | { | |
a80d1b68 SM |
1125 | int err = 0; |
1126 | ||
1127 | dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); | |
1128 | mutex_lock(&dev->intf_state_mutex); | |
1129 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { | |
1130 | mlx5_core_warn(dev, "interface is up, NOP\n"); | |
1131 | goto out; | |
1bde6e30 | 1132 | } |
a80d1b68 SM |
1133 | /* remove any previous indication of internal error */ |
1134 | dev->state = MLX5_DEVICE_STATE_UP; | |
e126ba97 | 1135 | |
a80d1b68 SM |
1136 | err = mlx5_function_setup(dev, boot); |
1137 | if (err) | |
1138 | goto out; | |
e126ba97 | 1139 | |
a80d1b68 SM |
1140 | if (boot) { |
1141 | err = mlx5_init_once(dev); | |
1142 | if (err) { | |
98a8e6fc | 1143 | mlx5_core_err(dev, "sw objs init failed\n"); |
a80d1b68 SM |
1144 | goto function_teardown; |
1145 | } | |
1146 | } | |
cd23b14b | 1147 | |
a80d1b68 SM |
1148 | err = mlx5_load(dev); |
1149 | if (err) | |
1150 | goto err_load; | |
e126ba97 | 1151 | |
a80d1b68 SM |
1152 | if (mlx5_device_registered(dev)) { |
1153 | mlx5_attach_device(dev); | |
1154 | } else { | |
1155 | err = mlx5_register_device(dev); | |
1156 | if (err) { | |
98a8e6fc | 1157 | mlx5_core_err(dev, "register device failed %d\n", err); |
a80d1b68 SM |
1158 | goto err_reg_dev; |
1159 | } | |
1160 | } | |
1161 | ||
1162 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
1163 | out: | |
1164 | mutex_unlock(&dev->intf_state_mutex); | |
e126ba97 | 1165 | |
a80d1b68 SM |
1166 | return err; |
1167 | ||
1168 | err_reg_dev: | |
1169 | mlx5_unload(dev); | |
1170 | err_load: | |
59211bd3 MHY |
1171 | if (boot) |
1172 | mlx5_cleanup_once(dev); | |
e161105e SM |
1173 | function_teardown: |
1174 | mlx5_function_teardown(dev, boot); | |
89d44f0a MD |
1175 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; |
1176 | mutex_unlock(&dev->intf_state_mutex); | |
1177 | ||
e126ba97 EC |
1178 | return err; |
1179 | } | |
e126ba97 | 1180 | |
868bc06b | 1181 | static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) |
e126ba97 | 1182 | { |
89d44f0a | 1183 | int err = 0; |
e126ba97 | 1184 | |
5e44fca5 | 1185 | if (cleanup) |
2a0165a0 | 1186 | mlx5_drain_health_recovery(dev); |
689a248d | 1187 | |
89d44f0a | 1188 | mutex_lock(&dev->intf_state_mutex); |
b3cb5388 | 1189 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
98a8e6fc HN |
1190 | mlx5_core_warn(dev, "%s: interface is down, NOP\n", |
1191 | __func__); | |
59211bd3 MHY |
1192 | if (cleanup) |
1193 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1194 | goto out; |
1195 | } | |
6b6adee3 | 1196 | |
9ade8c7c | 1197 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
9ade8c7c | 1198 | |
737a234b MHY |
1199 | if (mlx5_device_registered(dev)) |
1200 | mlx5_detach_device(dev); | |
1201 | ||
a80d1b68 SM |
1202 | mlx5_unload(dev); |
1203 | ||
59211bd3 MHY |
1204 | if (cleanup) |
1205 | mlx5_cleanup_once(dev); | |
9603b61d | 1206 | |
e161105e | 1207 | mlx5_function_teardown(dev, cleanup); |
ac6ea6e8 | 1208 | out: |
89d44f0a | 1209 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1210 | return err; |
9603b61d | 1211 | } |
64613d94 | 1212 | |
feae9087 | 1213 | static const struct devlink_ops mlx5_devlink_ops = { |
e80541ec | 1214 | #ifdef CONFIG_MLX5_ESWITCH |
feae9087 OG |
1215 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, |
1216 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1217 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1218 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
7768d197 RD |
1219 | .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, |
1220 | .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, | |
feae9087 OG |
1221 | #endif |
1222 | }; | |
f66f049f | 1223 | |
27b942fb | 1224 | static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) |
9603b61d | 1225 | { |
11f3b84d | 1226 | struct mlx5_priv *priv = &dev->priv; |
9603b61d JM |
1227 | int err; |
1228 | ||
11f3b84d | 1229 | dev->profile = &profile[profile_idx]; |
9603b61d | 1230 | |
364d1798 EC |
1231 | INIT_LIST_HEAD(&priv->ctx_list); |
1232 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1233 | mutex_init(&dev->pci_status_mutex); |
1234 | mutex_init(&dev->intf_state_mutex); | |
d9aaed83 | 1235 | |
01187175 EC |
1236 | mutex_init(&priv->bfregs.reg_head.lock); |
1237 | mutex_init(&priv->bfregs.wc_head.lock); | |
1238 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1239 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1240 | ||
11f3b84d SM |
1241 | mutex_init(&priv->alloc_mutex); |
1242 | mutex_init(&priv->pgdir_mutex); | |
1243 | INIT_LIST_HEAD(&priv->pgdir_list); | |
1244 | spin_lock_init(&priv->mkey_lock); | |
1245 | ||
27b942fb PP |
1246 | priv->dbg_root = debugfs_create_dir(dev_name(dev->device), |
1247 | mlx5_debugfs_root); | |
11f3b84d | 1248 | if (!priv->dbg_root) { |
27b942fb | 1249 | dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); |
11f3b84d | 1250 | return -ENOMEM; |
9603b61d JM |
1251 | } |
1252 | ||
ac6ea6e8 | 1253 | err = mlx5_health_init(dev); |
52c368dc SM |
1254 | if (err) |
1255 | goto err_health_init; | |
ac6ea6e8 | 1256 | |
0cf53c12 SM |
1257 | err = mlx5_pagealloc_init(dev); |
1258 | if (err) | |
1259 | goto err_pagealloc_init; | |
59211bd3 | 1260 | |
11f3b84d | 1261 | return 0; |
52c368dc SM |
1262 | |
1263 | err_pagealloc_init: | |
1264 | mlx5_health_cleanup(dev); | |
1265 | err_health_init: | |
1266 | debugfs_remove(dev->priv.dbg_root); | |
1267 | ||
1268 | return err; | |
11f3b84d SM |
1269 | } |
1270 | ||
1271 | static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) | |
1272 | { | |
52c368dc SM |
1273 | mlx5_pagealloc_cleanup(dev); |
1274 | mlx5_health_cleanup(dev); | |
11f3b84d SM |
1275 | debugfs_remove_recursive(dev->priv.dbg_root); |
1276 | } | |
1277 | ||
59211bd3 | 1278 | #define MLX5_IB_MOD "mlx5_ib" |
11f3b84d | 1279 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
9603b61d JM |
1280 | { |
1281 | struct mlx5_core_dev *dev; | |
feae9087 | 1282 | struct devlink *devlink; |
9603b61d JM |
1283 | int err; |
1284 | ||
feae9087 OG |
1285 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1286 | if (!devlink) { | |
9603b61d JM |
1287 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1288 | return -ENOMEM; | |
1289 | } | |
feae9087 OG |
1290 | |
1291 | dev = devlink_priv(devlink); | |
27b942fb PP |
1292 | dev->device = &pdev->dev; |
1293 | dev->pdev = pdev; | |
9603b61d | 1294 | |
27b942fb | 1295 | err = mlx5_mdev_init(dev, prof_sel); |
11f3b84d SM |
1296 | if (err) |
1297 | goto mdev_init_err; | |
01187175 | 1298 | |
11f3b84d | 1299 | err = mlx5_pci_init(dev, pdev, id); |
9603b61d | 1300 | if (err) { |
98a8e6fc HN |
1301 | mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", |
1302 | err); | |
11f3b84d | 1303 | goto pci_init_err; |
9603b61d JM |
1304 | } |
1305 | ||
868bc06b | 1306 | err = mlx5_load_one(dev, true); |
9603b61d | 1307 | if (err) { |
98a8e6fc HN |
1308 | mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", |
1309 | err); | |
0cf53c12 | 1310 | goto err_load_one; |
9603b61d | 1311 | } |
59211bd3 | 1312 | |
f82eed45 | 1313 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1314 | |
feae9087 OG |
1315 | err = devlink_register(devlink, &pdev->dev); |
1316 | if (err) | |
1317 | goto clean_load; | |
1318 | ||
5d47f6c8 | 1319 | pci_save_state(pdev); |
9603b61d JM |
1320 | return 0; |
1321 | ||
feae9087 | 1322 | clean_load: |
868bc06b | 1323 | mlx5_unload_one(dev, true); |
52c368dc | 1324 | |
0cf53c12 | 1325 | err_load_one: |
868bc06b | 1326 | mlx5_pci_close(dev); |
11f3b84d SM |
1327 | pci_init_err: |
1328 | mlx5_mdev_uninit(dev); | |
1329 | mdev_init_err: | |
feae9087 | 1330 | devlink_free(devlink); |
a31208b1 | 1331 | |
9603b61d JM |
1332 | return err; |
1333 | } | |
a31208b1 | 1334 | |
9603b61d JM |
1335 | static void remove_one(struct pci_dev *pdev) |
1336 | { | |
1337 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1338 | struct devlink *devlink = priv_to_devlink(dev); |
9603b61d | 1339 | |
feae9087 | 1340 | devlink_unregister(devlink); |
737a234b MHY |
1341 | mlx5_unregister_device(dev); |
1342 | ||
868bc06b | 1343 | if (mlx5_unload_one(dev, true)) { |
98a8e6fc | 1344 | mlx5_core_err(dev, "mlx5_unload_one failed\n"); |
52c368dc | 1345 | mlx5_health_flush(dev); |
a31208b1 MD |
1346 | return; |
1347 | } | |
737a234b | 1348 | |
868bc06b | 1349 | mlx5_pci_close(dev); |
11f3b84d | 1350 | mlx5_mdev_uninit(dev); |
feae9087 | 1351 | devlink_free(devlink); |
9603b61d JM |
1352 | } |
1353 | ||
89d44f0a MD |
1354 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1355 | pci_channel_state_t state) | |
1356 | { | |
1357 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a | 1358 | |
98a8e6fc | 1359 | mlx5_core_info(dev, "%s was called\n", __func__); |
04c0c1ab | 1360 | |
8812c24d | 1361 | mlx5_enter_error_state(dev, false); |
868bc06b | 1362 | mlx5_unload_one(dev, false); |
5d47f6c8 | 1363 | /* In case of kernel call drain the health wq */ |
05ac2c0b | 1364 | if (state) { |
5e44fca5 | 1365 | mlx5_drain_health_wq(dev); |
05ac2c0b MHY |
1366 | mlx5_pci_disable_device(dev); |
1367 | } | |
1368 | ||
89d44f0a MD |
1369 | return state == pci_channel_io_perm_failure ? |
1370 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1371 | } | |
1372 | ||
d57847dc DJ |
1373 | /* wait for the device to show vital signs by waiting |
1374 | * for the health counter to start counting. | |
89d44f0a | 1375 | */ |
d57847dc | 1376 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1377 | { |
1378 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1379 | struct mlx5_core_health *health = &dev->priv.health; | |
1380 | const int niter = 100; | |
d57847dc | 1381 | u32 last_count = 0; |
89d44f0a | 1382 | u32 count; |
89d44f0a MD |
1383 | int i; |
1384 | ||
89d44f0a MD |
1385 | for (i = 0; i < niter; i++) { |
1386 | count = ioread32be(health->health_counter); | |
1387 | if (count && count != 0xffffffff) { | |
d57847dc | 1388 | if (last_count && last_count != count) { |
98a8e6fc HN |
1389 | mlx5_core_info(dev, |
1390 | "wait vital counter value 0x%x after %d iterations\n", | |
1391 | count, i); | |
d57847dc DJ |
1392 | return 0; |
1393 | } | |
1394 | last_count = count; | |
89d44f0a MD |
1395 | } |
1396 | msleep(50); | |
1397 | } | |
1398 | ||
d57847dc | 1399 | return -ETIMEDOUT; |
89d44f0a MD |
1400 | } |
1401 | ||
1061c90f | 1402 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1403 | { |
1404 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1405 | int err; |
1406 | ||
98a8e6fc | 1407 | mlx5_core_info(dev, "%s was called\n", __func__); |
89d44f0a | 1408 | |
1061c90f | 1409 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1410 | if (err) { |
98a8e6fc HN |
1411 | mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", |
1412 | __func__, err); | |
1061c90f MHY |
1413 | return PCI_ERS_RESULT_DISCONNECT; |
1414 | } | |
1415 | ||
1416 | pci_set_master(pdev); | |
1417 | pci_restore_state(pdev); | |
5d47f6c8 | 1418 | pci_save_state(pdev); |
1061c90f MHY |
1419 | |
1420 | if (wait_vital(pdev)) { | |
98a8e6fc | 1421 | mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1422 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1423 | } |
89d44f0a | 1424 | |
1061c90f MHY |
1425 | return PCI_ERS_RESULT_RECOVERED; |
1426 | } | |
1427 | ||
1061c90f MHY |
1428 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1429 | { | |
1430 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1061c90f MHY |
1431 | int err; |
1432 | ||
98a8e6fc | 1433 | mlx5_core_info(dev, "%s was called\n", __func__); |
1061c90f | 1434 | |
868bc06b | 1435 | err = mlx5_load_one(dev, false); |
89d44f0a | 1436 | if (err) |
98a8e6fc HN |
1437 | mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", |
1438 | __func__, err); | |
89d44f0a | 1439 | else |
98a8e6fc | 1440 | mlx5_core_info(dev, "%s: device recovered\n", __func__); |
89d44f0a MD |
1441 | } |
1442 | ||
1443 | static const struct pci_error_handlers mlx5_err_handler = { | |
1444 | .error_detected = mlx5_pci_err_detected, | |
1445 | .slot_reset = mlx5_pci_slot_reset, | |
1446 | .resume = mlx5_pci_resume | |
1447 | }; | |
1448 | ||
8812c24d MD |
1449 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1450 | { | |
fcd29ad1 FD |
1451 | bool fast_teardown = false, force_teardown = false; |
1452 | int ret = 1; | |
1453 | ||
1454 | fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); | |
1455 | force_teardown = MLX5_CAP_GEN(dev, force_teardown); | |
1456 | ||
1457 | mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); | |
1458 | mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); | |
8812c24d | 1459 | |
fcd29ad1 | 1460 | if (!fast_teardown && !force_teardown) |
8812c24d | 1461 | return -EOPNOTSUPP; |
8812c24d MD |
1462 | |
1463 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1464 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1465 | return -EAGAIN; | |
1466 | } | |
1467 | ||
d2aa060d HN |
1468 | /* Panic tear down fw command will stop the PCI bus communication |
1469 | * with the HCA, so the health polll is no longer needed. | |
1470 | */ | |
1471 | mlx5_drain_health_wq(dev); | |
76d5581c | 1472 | mlx5_stop_health_poll(dev, false); |
d2aa060d | 1473 | |
fcd29ad1 FD |
1474 | ret = mlx5_cmd_fast_teardown_hca(dev); |
1475 | if (!ret) | |
1476 | goto succeed; | |
1477 | ||
8812c24d | 1478 | ret = mlx5_cmd_force_teardown_hca(dev); |
fcd29ad1 FD |
1479 | if (!ret) |
1480 | goto succeed; | |
1481 | ||
1482 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1483 | mlx5_start_health_poll(dev); | |
1484 | return ret; | |
8812c24d | 1485 | |
fcd29ad1 | 1486 | succeed: |
8812c24d MD |
1487 | mlx5_enter_error_state(dev, true); |
1488 | ||
1ef903bf DJ |
1489 | /* Some platforms requiring freeing the IRQ's in the shutdown |
1490 | * flow. If they aren't freed they can't be allocated after | |
1491 | * kexec. There is no need to cleanup the mlx5_core software | |
1492 | * contexts. | |
1493 | */ | |
1ef903bf DJ |
1494 | mlx5_core_eq_free_irqs(dev); |
1495 | ||
8812c24d MD |
1496 | return 0; |
1497 | } | |
1498 | ||
5fc7197d MD |
1499 | static void shutdown(struct pci_dev *pdev) |
1500 | { | |
1501 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
8812c24d | 1502 | int err; |
5fc7197d | 1503 | |
98a8e6fc | 1504 | mlx5_core_info(dev, "Shutdown was called\n"); |
8812c24d MD |
1505 | err = mlx5_try_fast_unload(dev); |
1506 | if (err) | |
868bc06b | 1507 | mlx5_unload_one(dev, false); |
5fc7197d MD |
1508 | mlx5_pci_disable_device(dev); |
1509 | } | |
1510 | ||
9603b61d | 1511 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1512 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1513 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1514 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1515 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1516 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1517 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1518 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1519 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1520 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1521 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1522 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1523 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
85327a9c EBE |
1524 | { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ |
1525 | { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ | |
2e9d3e83 NO |
1526 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1527 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
9603b61d JM |
1528 | { 0, } |
1529 | }; | |
1530 | ||
1531 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1532 | ||
04c0c1ab MHY |
1533 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1534 | { | |
1535 | mlx5_pci_err_detected(dev->pdev, 0); | |
1536 | } | |
1537 | ||
1538 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1539 | { | |
1540 | mlx5_pci_disable_device(dev); | |
1541 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1542 | mlx5_pci_resume(dev->pdev); | |
1543 | } | |
1544 | ||
9603b61d JM |
1545 | static struct pci_driver mlx5_core_driver = { |
1546 | .name = DRIVER_NAME, | |
1547 | .id_table = mlx5_core_pci_table, | |
1548 | .probe = init_one, | |
89d44f0a | 1549 | .remove = remove_one, |
5fc7197d | 1550 | .shutdown = shutdown, |
fc50db98 EC |
1551 | .err_handler = &mlx5_err_handler, |
1552 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1553 | }; |
e126ba97 | 1554 | |
f663ad98 KH |
1555 | static void mlx5_core_verify_params(void) |
1556 | { | |
1557 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1558 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1559 | prof_sel, | |
1560 | ARRAY_SIZE(profile) - 1, | |
1561 | MLX5_DEFAULT_PROF); | |
1562 | prof_sel = MLX5_DEFAULT_PROF; | |
1563 | } | |
1564 | } | |
1565 | ||
e126ba97 EC |
1566 | static int __init init(void) |
1567 | { | |
1568 | int err; | |
1569 | ||
8737f818 DJ |
1570 | get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); |
1571 | ||
f663ad98 | 1572 | mlx5_core_verify_params(); |
05564d0a | 1573 | mlx5_fpga_ipsec_build_fs_cmds(); |
e126ba97 | 1574 | mlx5_register_debugfs(); |
e126ba97 | 1575 | |
9603b61d JM |
1576 | err = pci_register_driver(&mlx5_core_driver); |
1577 | if (err) | |
ac6ea6e8 | 1578 | goto err_debug; |
9603b61d | 1579 | |
f62b8bb8 AV |
1580 | #ifdef CONFIG_MLX5_CORE_EN |
1581 | mlx5e_init(); | |
1582 | #endif | |
1583 | ||
e126ba97 EC |
1584 | return 0; |
1585 | ||
e126ba97 EC |
1586 | err_debug: |
1587 | mlx5_unregister_debugfs(); | |
1588 | return err; | |
1589 | } | |
1590 | ||
1591 | static void __exit cleanup(void) | |
1592 | { | |
f62b8bb8 AV |
1593 | #ifdef CONFIG_MLX5_CORE_EN |
1594 | mlx5e_cleanup(); | |
1595 | #endif | |
9603b61d | 1596 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1597 | mlx5_unregister_debugfs(); |
1598 | } | |
1599 | ||
1600 | module_init(init); | |
1601 | module_exit(cleanup); |