[mirror_ubuntu-kernels.git] / drivers / net / ethernet / mellanox / mlx5 / core / mlx5_core.h

/*
 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_CORE_H__
#define __MLX5_CORE_H__

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/if_link.h>
#include <linux/firmware.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/mlx5/cq.h>
#include <linux/mlx5/fs.h>

#define DRIVER_NAME "mlx5_core"
#define DRIVER_VERSION "5.0-0"

extern uint mlx5_core_debug_mask;

#define mlx5_core_dbg(__dev, format, ...)				\
	dev_dbg(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format,		\
		 __func__, __LINE__, current->pid,			\
		 ##__VA_ARGS__)

#define mlx5_core_dbg_once(__dev, format, ...)				\
	dev_dbg_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format,	\
		     __func__, __LINE__, current->pid,			\
		     ##__VA_ARGS__)

#define mlx5_core_dbg_mask(__dev, mask, format, ...)			\
do {									\
	if ((mask) & mlx5_core_debug_mask)				\
		mlx5_core_dbg(__dev, format, ##__VA_ARGS__);		\
} while (0)

#define mlx5_core_err(__dev, format, ...)				\
	dev_err(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format,	\
		__func__, __LINE__, current->pid,	\
	       ##__VA_ARGS__)

#define mlx5_core_err_rl(__dev, format, ...)				\
	dev_err_ratelimited(&(__dev)->pdev->dev,			\
			   "%s:%d:(pid %d): " format,			\
			   __func__, __LINE__, current->pid,		\
			   ##__VA_ARGS__)

#define mlx5_core_warn(__dev, format, ...)				\
	dev_warn(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format,	\
		 __func__, __LINE__, current->pid,			\
		##__VA_ARGS__)

#define mlx5_core_warn_once(__dev, format, ...)				\
	dev_warn_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format,	\
		      __func__, __LINE__, current->pid,			\
		      ##__VA_ARGS__)

#define mlx5_core_info(__dev, format, ...)				\
	dev_info(&(__dev)->pdev->dev, format, ##__VA_ARGS__)

enum {
	MLX5_CMD_DATA, /* print command payload only */
	MLX5_CMD_TIME, /* print command execution time */
};

enum {
	MLX5_DRIVER_STATUS_ABORTED = 0xfe,
	MLX5_DRIVER_SYND = 0xbadd00de,
};

int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
int mlx5_query_board_id(struct mlx5_core_dev *dev);
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
void mlx5_disable_device(struct mlx5_core_dev *dev);
void mlx5_recover_device(struct mlx5_core_dev *dev);
int mlx5_sriov_init(struct mlx5_core_dev *dev);
void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
int mlx5_sriov_attach(struct mlx5_core_dev *dev);
void mlx5_sriov_detach(struct mlx5_core_dev *dev);
int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev);
int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
				       void *context, u32 *element_id);
int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
				       void *context, u32 element_id,
				       u32 modify_bitmask);
int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
					u32 element_id);
int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
			     struct ptp_system_timestamp *sts);

void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
void mlx5_cmd_flush(struct mlx5_core_dev *dev);
int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);

int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
			u8 access_reg_group);
int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
			u8 access_reg_group);
int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
			u8 feature_group, u8 access_reg_group);

void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
void mlx5_lag_remove(struct mlx5_core_dev *dev);

int mlx5_events_init(struct mlx5_core_dev *dev);
void mlx5_events_cleanup(struct mlx5_core_dev *dev);
void mlx5_events_start(struct mlx5_core_dev *dev);
void mlx5_events_stop(struct mlx5_core_dev *dev);

void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
void mlx5_attach_device(struct mlx5_core_dev *dev);
void mlx5_detach_device(struct mlx5_core_dev *dev);
bool mlx5_device_registered(struct mlx5_core_dev *dev);
int mlx5_register_device(struct mlx5_core_dev *dev);
void mlx5_unregister_device(struct mlx5_core_dev *dev);
void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
void mlx5_dev_list_lock(void);
void mlx5_dev_list_unlock(void);
int mlx5_dev_list_trylock(void);

bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv);

int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);

#define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) &&		\
			    MLX5_CAP_GEN((mdev), pps_modify) &&		\
			    MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) &&	\
			    MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))

int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw);

void mlx5e_init(void);
void mlx5e_cleanup(void);

static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
{
	/* LACP owner conditions:
	 * 1) Function is physical.
	 * 2) LAG is supported by FW.
	 * 3) LAG is managed by driver (currently the only option).
	 */
	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
		    MLX5_CAP_GEN(dev, lag_master);
}

void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol);
void mlx5_lag_update(struct mlx5_core_dev *dev);

enum {
	MLX5_NIC_IFC_FULL		= 0,
	MLX5_NIC_IFC_DISABLED		= 1,
	MLX5_NIC_IFC_NO_DRAM_NIC	= 2,
	MLX5_NIC_IFC_INVALID		= 3
};

u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
#endif /* __MLX5_CORE_H__ */
Commit	Line	Data
e126ba97	1	/*
f62b8bb8	2	* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_CORE_H__
	34	#define __MLX5_CORE_H__
	35
	36	#include <linux/types.h>
	37	#include <linux/kernel.h>
	38	#include <linux/sched.h>
81848731	39	#include <linux/if_link.h>
62bd22cf	40	#include <linux/firmware.h>
4a0475d5	41	#include <linux/ptp_clock_kernel.h>
d5c07157	42	#include <linux/mlx5/cq.h>
31ca3648	43	#include <linux/mlx5/fs.h>
e126ba97	44
f62b8bb8	45	#define DRIVER_NAME "mlx5_core"
7913d205	46	#define DRIVER_VERSION "5.0-0"
f62b8bb8	47
f663ad98	48	extern uint mlx5_core_debug_mask;
e126ba97	49
5a788398	50	#define mlx5_core_dbg(__dev, format, ...) \
9e5b2fc1 KH	51	dev_dbg(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
9e5b2fc1 KH	52	__func__, __LINE__, current->pid, \
1a91de28	53	##__VA_ARGS__)
e126ba97	54
0608d4db TT	55	#define mlx5_core_dbg_once(__dev, format, ...) \
	56	dev_dbg_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
	57	__func__, __LINE__, current->pid, \
	58	##__VA_ARGS__)
	59
5a788398	60	#define mlx5_core_dbg_mask(__dev, mask, format, ...) \
1a91de28 JP	61	do { \
1a91de28 JP	62	if ((mask) & mlx5_core_debug_mask) \
5a788398	63	mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
e126ba97 EC	64	} while (0)
e126ba97 EC	65
5a788398	66	#define mlx5_core_err(__dev, format, ...) \
2974ab6e SM	67	dev_err(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
2974ab6e SM	68	__func__, __LINE__, current->pid, \
1a91de28	69	##__VA_ARGS__)
e126ba97	70
b30408d7 LR	71	#define mlx5_core_err_rl(__dev, format, ...) \
	72	dev_err_ratelimited(&(__dev)->pdev->dev, \
	73	"%s:%d:(pid %d): " format, \
	74	__func__, __LINE__, current->pid, \
	75	##__VA_ARGS__)
	76
5a788398	77	#define mlx5_core_warn(__dev, format, ...) \
9e5b2fc1 KH	78	dev_warn(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
9e5b2fc1 KH	79	__func__, __LINE__, current->pid, \
1a91de28	80	##__VA_ARGS__)
e126ba97	81
0f597ed4 SM	82	#define mlx5_core_warn_once(__dev, format, ...) \
	83	dev_warn_once(&(__dev)->pdev->dev, "%s:%d:(pid %d): " format, \
	84	__func__, __LINE__, current->pid, \
	85	##__VA_ARGS__)
	86
108805fc SM	87	#define mlx5_core_info(__dev, format, ...) \
	88	dev_info(&(__dev)->pdev->dev, format, ##__VA_ARGS__)
	89
e126ba97 EC	90	enum {
	91	MLX5_CMD_DATA, /* print command payload only */
	92	MLX5_CMD_TIME, /* print command execution time */
	93	};
	94
f9c14e46 KH	95	enum {
	96	MLX5_DRIVER_STATUS_ABORTED = 0xfe,
	97	MLX5_DRIVER_SYND = 0xbadd00de,
	98	};
	99
938fe83c	100	int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
211e6c80	101	int mlx5_query_board_id(struct mlx5_core_dev *dev);
8737f818	102	int mlx5_cmd_init_hca(struct mlx5_core_dev dev, uint32_t sw_owner_id);
e126ba97	103	int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
8812c24d	104	int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
fcd29ad1	105	int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
8812c24d	106	void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
89d44f0a	107	void mlx5_disable_device(struct mlx5_core_dev *dev);
04c0c1ab	108	void mlx5_recover_device(struct mlx5_core_dev *dev);
6b6adee3 MHY	109	int mlx5_sriov_init(struct mlx5_core_dev *dev);
6b6adee3 MHY	110	void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
acab721b MHY	111	int mlx5_sriov_attach(struct mlx5_core_dev *dev);
acab721b MHY	112	void mlx5_sriov_detach(struct mlx5_core_dev *dev);
fc50db98	113	int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
edb31b16	114	bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev);
0b107106 EC	115	int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
0b107106 EC	116	int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
813f8540 MHY	117	int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
	118	void context, u32 element_id);
	119	int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
	120	void *context, u32 element_id,
	121	u32 modify_bitmask);
	122	int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
	123	u32 element_id);
591905ba	124	int mlx5_wait_for_pages(struct mlx5_core_dev dev, int pages);
4a0475d5 ML	125	u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
4a0475d5 ML	126	struct ptp_system_timestamp *sts);
d5c07157	127
71edc69c	128	void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
4cab346b	129	void mlx5_cmd_flush(struct mlx5_core_dev *dev);
3ec5693b SM	130	int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
3ec5693b SM	131	void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
e126ba97	132
c835ad64 GP	133	int mlx5_query_pcam_reg(struct mlx5_core_dev dev, u32 pcam, u8 feature_group,
	134	u8 access_reg_group);
	135	int mlx5_query_mcam_reg(struct mlx5_core_dev dev, u32 mcap, u8 feature_group,
	136	u8 access_reg_group);
c02762eb HN	137	int mlx5_query_qcam_reg(struct mlx5_core_dev mdev, u32 qcam,
c02762eb HN	138	u8 feature_group, u8 access_reg_group);
c835ad64	139
7907f23a AH	140	void mlx5_lag_add(struct mlx5_core_dev dev, struct net_device netdev);
	141	void mlx5_lag_remove(struct mlx5_core_dev *dev);
	142
69c1280b SM	143	int mlx5_events_init(struct mlx5_core_dev *dev);
	144	void mlx5_events_cleanup(struct mlx5_core_dev *dev);
	145	void mlx5_events_start(struct mlx5_core_dev *dev);
	146	void mlx5_events_stop(struct mlx5_core_dev *dev);
	147
f1ee87fe MHY	148	void mlx5_add_device(struct mlx5_interface intf, struct mlx5_priv priv);
	149	void mlx5_remove_device(struct mlx5_interface intf, struct mlx5_priv priv);
	150	void mlx5_attach_device(struct mlx5_core_dev *dev);
	151	void mlx5_detach_device(struct mlx5_core_dev *dev);
	152	bool mlx5_device_registered(struct mlx5_core_dev *dev);
	153	int mlx5_register_device(struct mlx5_core_dev *dev);
	154	void mlx5_unregister_device(struct mlx5_core_dev *dev);
7907f23a AH	155	void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
7907f23a AH	156	void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
f1ee87fe MHY	157	struct mlx5_core_dev mlx5_get_next_phys_dev(struct mlx5_core_dev dev);
	158	void mlx5_dev_list_lock(void);
	159	void mlx5_dev_list_unlock(void);
	160	int mlx5_dev_list_trylock(void);
2de24fed	161
917b41aa AH	162	bool mlx5_lag_intf_add(struct mlx5_interface intf, struct mlx5_priv priv);
917b41aa AH	163
f9a1ef72 EE	164	int mlx5_query_mtpps(struct mlx5_core_dev dev, u32 mtpps, u32 mtpps_size);
	165	int mlx5_set_mtpps(struct mlx5_core_dev mdev, u32 mtpps, u32 mtpps_size);
	166	int mlx5_query_mtppse(struct mlx5_core_dev mdev, u8 pin, u8 arm, u8 *mode);
	167	int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
	168
fa367688 EE	169	#define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
	170	MLX5_CAP_GEN((mdev), pps_modify) && \
	171	MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
	172	MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
	173
62bd22cf OG	174	int mlx5_firmware_flash(struct mlx5_core_dev dev, const struct firmware fw);
62bd22cf OG	175
f62b8bb8 AV	176	void mlx5e_init(void);
	177	void mlx5e_cleanup(void);
	178
db60b802 AH	179	static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
	180	{
	181	/* LACP owner conditions:
	182	* 1) Function is physical.
	183	* 2) LAG is supported by FW.
	184	* 3) LAG is managed by driver (currently the only option).
	185	*/
	186	return MLX5_CAP_GEN(dev, vport_group_manager) &&
	187	(MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
	188	MLX5_CAP_GEN(dev, lag_master);
	189	}
	190
c5447c70	191	void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol);
eff849b2	192	void mlx5_lag_update(struct mlx5_core_dev *dev);
fcd29ad1 FD	193
	194	enum {
	195	MLX5_NIC_IFC_FULL = 0,
	196	MLX5_NIC_IFC_DISABLED = 1,
	197	MLX5_NIC_IFC_NO_DRAM_NIC = 2,
	198	MLX5_NIC_IFC_INVALID = 3
	199	};
	200
	201	u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
	202	void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
e126ba97	203	#endif /* __MLX5_CORE_H__ */