[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / qp.c

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */


#include <linux/gfp.h>
#include <linux/export.h>
#include <linux/mlx5/cmd.h>
#include <linux/mlx5/qp.h>
#include <linux/mlx5/driver.h>

#include "mlx5_core.h"

static struct mlx5_core_rsc_common *mlx5_get_rsc(struct mlx5_core_dev *dev,
						 u32 rsn)
{
	struct mlx5_qp_table *table = &dev->priv.qp_table;
	struct mlx5_core_rsc_common *common;

	spin_lock(&table->lock);

	common = radix_tree_lookup(&table->tree, rsn);
	if (common)
		atomic_inc(&common->refcount);

	spin_unlock(&table->lock);

	if (!common) {
		mlx5_core_warn(dev, "Async event for bogus resource 0x%x\n",
			       rsn);
		return NULL;
	}
	return common;
}

void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
{
	if (atomic_dec_and_test(&common->refcount))
		complete(&common->free);
}

void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
{
	struct mlx5_core_rsc_common *common = mlx5_get_rsc(dev, rsn);
	struct mlx5_core_qp *qp;

	if (!common)
		return;

	switch (common->res) {
	case MLX5_RES_QP:
		qp = (struct mlx5_core_qp *)common;
		qp->event(qp, event_type);
		break;

	default:
		mlx5_core_warn(dev, "invalid resource type for 0x%x\n", rsn);
	}

	mlx5_core_put_rsc(common);
}

#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe)
{
	struct mlx5_eqe_page_fault *pf_eqe = &eqe->data.page_fault;
	int qpn = be32_to_cpu(pf_eqe->flags_qpn) & MLX5_QPN_MASK;
	struct mlx5_core_rsc_common *common = mlx5_get_rsc(dev, qpn);
	struct mlx5_core_qp *qp =
		container_of(common, struct mlx5_core_qp, common);
	struct mlx5_pagefault pfault;

	if (!qp) {
		mlx5_core_warn(dev, "ODP event for non-existent QP %06x\n",
			       qpn);
		return;
	}

	pfault.event_subtype = eqe->sub_type;
	pfault.flags = (be32_to_cpu(pf_eqe->flags_qpn) >> MLX5_QPN_BITS) &
		(MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE | MLX5_PFAULT_RDMA);
	pfault.bytes_committed = be32_to_cpu(
		pf_eqe->bytes_committed);

	mlx5_core_dbg(dev,
		      "PAGE_FAULT: subtype: 0x%02x, flags: 0x%02x,\n",
		      eqe->sub_type, pfault.flags);

	switch (eqe->sub_type) {
	case MLX5_PFAULT_SUBTYPE_RDMA:
		/* RDMA based event */
		pfault.rdma.r_key =
			be32_to_cpu(pf_eqe->rdma.r_key);
		pfault.rdma.packet_size =
			be16_to_cpu(pf_eqe->rdma.packet_length);
		pfault.rdma.rdma_op_len =
			be32_to_cpu(pf_eqe->rdma.rdma_op_len);
		pfault.rdma.rdma_va =
			be64_to_cpu(pf_eqe->rdma.rdma_va);
		mlx5_core_dbg(dev,
			      "PAGE_FAULT: qpn: 0x%06x, r_key: 0x%08x,\n",
			      qpn, pfault.rdma.r_key);
		mlx5_core_dbg(dev,
			      "PAGE_FAULT: rdma_op_len: 0x%08x,\n",
			      pfault.rdma.rdma_op_len);
		mlx5_core_dbg(dev,
			      "PAGE_FAULT: rdma_va: 0x%016llx,\n",
			      pfault.rdma.rdma_va);
		mlx5_core_dbg(dev,
			      "PAGE_FAULT: bytes_committed: 0x%06x\n",
			      pfault.bytes_committed);
		break;

	case MLX5_PFAULT_SUBTYPE_WQE:
		/* WQE based event */
		pfault.wqe.wqe_index =
			be16_to_cpu(pf_eqe->wqe.wqe_index);
		pfault.wqe.packet_size =
			be16_to_cpu(pf_eqe->wqe.packet_length);
		mlx5_core_dbg(dev,
			      "PAGE_FAULT: qpn: 0x%06x, wqe_index: 0x%04x,\n",
			      qpn, pfault.wqe.wqe_index);
		mlx5_core_dbg(dev,
			      "PAGE_FAULT: bytes_committed: 0x%06x\n",
			      pfault.bytes_committed);
		break;

	default:
		mlx5_core_warn(dev,
			       "Unsupported page fault event sub-type: 0x%02hhx, QP %06x\n",
			       eqe->sub_type, qpn);
		/* Unsupported page faults should still be resolved by the
		 * page fault handler
		 */
	}

	if (qp->pfault_handler) {
		qp->pfault_handler(qp, &pfault);
	} else {
		mlx5_core_err(dev,
			      "ODP event for QP %08x, without a fault handler in QP\n",
			      qpn);
		/* Page fault will remain unresolved. QP will hang until it is
		 * destroyed
		 */
	}

	mlx5_core_put_rsc(common);
}
#endif

int mlx5_core_create_qp(struct mlx5_core_dev *dev,
			struct mlx5_core_qp *qp,
			struct mlx5_create_qp_mbox_in *in,
			int inlen)
{
	struct mlx5_qp_table *table = &dev->priv.qp_table;
	struct mlx5_create_qp_mbox_out out;
	struct mlx5_destroy_qp_mbox_in din;
	struct mlx5_destroy_qp_mbox_out dout;
	int err;

	memset(&out, 0, sizeof(out));
	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_QP);

	err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
	if (err) {
		mlx5_core_warn(dev, "ret %d\n", err);
		return err;
	}

	if (out.hdr.status) {
		mlx5_core_warn(dev, "current num of QPs 0x%x\n",
			       atomic_read(&dev->num_qps));
		return mlx5_cmd_status_to_err(&out.hdr);
	}

	qp->qpn = be32_to_cpu(out.qpn) & 0xffffff;
	mlx5_core_dbg(dev, "qpn = 0x%x\n", qp->qpn);

	qp->common.res = MLX5_RES_QP;
	spin_lock_irq(&table->lock);
	err = radix_tree_insert(&table->tree, qp->qpn, qp);
	spin_unlock_irq(&table->lock);
	if (err) {
		mlx5_core_warn(dev, "err %d\n", err);
		goto err_cmd;
	}

	err = mlx5_debug_qp_add(dev, qp);
	if (err)
		mlx5_core_dbg(dev, "failed adding QP 0x%x to debug file system\n",
			      qp->qpn);

	qp->pid = current->pid;
	atomic_set(&qp->common.refcount, 1);
	atomic_inc(&dev->num_qps);
	init_completion(&qp->common.free);

	return 0;

err_cmd:
	memset(&din, 0, sizeof(din));
	memset(&dout, 0, sizeof(dout));
	din.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
	din.qpn = cpu_to_be32(qp->qpn);
	mlx5_cmd_exec(dev, &din, sizeof(din), &out, sizeof(dout));

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_create_qp);

int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
			 struct mlx5_core_qp *qp)
{
	struct mlx5_destroy_qp_mbox_in in;
	struct mlx5_destroy_qp_mbox_out out;
	struct mlx5_qp_table *table = &dev->priv.qp_table;
	unsigned long flags;
	int err;

	mlx5_debug_qp_remove(dev, qp);

	spin_lock_irqsave(&table->lock, flags);
	radix_tree_delete(&table->tree, qp->qpn);
	spin_unlock_irqrestore(&table->lock, flags);

	mlx5_core_put_rsc((struct mlx5_core_rsc_common *)qp);
	wait_for_completion(&qp->common.free);

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
	in.qpn = cpu_to_be32(qp->qpn);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		return mlx5_cmd_status_to_err(&out.hdr);

	atomic_dec(&dev->num_qps);
	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_core_destroy_qp);

int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
			enum mlx5_qp_state new_state,
			struct mlx5_modify_qp_mbox_in *in, int sqd_event,
			struct mlx5_core_qp *qp)
{
	static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
		[MLX5_QP_STATE_RST] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_RST2INIT_QP,
		},
		[MLX5_QP_STATE_INIT]  = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_INIT2INIT_QP,
			[MLX5_QP_STATE_RTR]	= MLX5_CMD_OP_INIT2RTR_QP,
		},
		[MLX5_QP_STATE_RTR]   = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTR2RTS_QP,
		},
		[MLX5_QP_STATE_RTS]   = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTS2RTS_QP,
		},
		[MLX5_QP_STATE_SQD] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
		},
		[MLX5_QP_STATE_SQER] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_SQERR2RTS_QP,
		},
		[MLX5_QP_STATE_ERR] = {
			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
		}
	};

	struct mlx5_modify_qp_mbox_out out;
	int err = 0;
	u16 op;

	if (cur_state >= MLX5_QP_NUM_STATE || new_state >= MLX5_QP_NUM_STATE ||
	    !optab[cur_state][new_state])
		return -EINVAL;

	memset(&out, 0, sizeof(out));
	op = optab[cur_state][new_state];
	in->hdr.opcode = cpu_to_be16(op);
	in->qpn = cpu_to_be32(qp->qpn);
	err = mlx5_cmd_exec(dev, in, sizeof(*in), &out, sizeof(out));
	if (err)
		return err;

	return mlx5_cmd_status_to_err(&out.hdr);
}
EXPORT_SYMBOL_GPL(mlx5_core_qp_modify);

void mlx5_init_qp_table(struct mlx5_core_dev *dev)
{
	struct mlx5_qp_table *table = &dev->priv.qp_table;

	memset(table, 0, sizeof(*table));
	spin_lock_init(&table->lock);
	INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
	mlx5_qp_debugfs_init(dev);
}

void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev)
{
	mlx5_qp_debugfs_cleanup(dev);
}

int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
		       struct mlx5_query_qp_mbox_out *out, int outlen)
{
	struct mlx5_query_qp_mbox_in in;
	int err;

	memset(&in, 0, sizeof(in));
	memset(out, 0, outlen);
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_QP);
	in.qpn = cpu_to_be32(qp->qpn);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
	if (err)
		return err;

	if (out->hdr.status)
		return mlx5_cmd_status_to_err(&out->hdr);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_qp_query);

int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn)
{
	struct mlx5_alloc_xrcd_mbox_in in;
	struct mlx5_alloc_xrcd_mbox_out out;
	int err;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_XRCD);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		err = mlx5_cmd_status_to_err(&out.hdr);
	else
		*xrcdn = be32_to_cpu(out.xrcdn);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_xrcd_alloc);

int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn)
{
	struct mlx5_dealloc_xrcd_mbox_in in;
	struct mlx5_dealloc_xrcd_mbox_out out;
	int err;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_XRCD);
	in.xrcdn = cpu_to_be32(xrcdn);
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		err = mlx5_cmd_status_to_err(&out.hdr);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_xrcd_dealloc);

#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
				u8 flags, int error)
{
	struct mlx5_page_fault_resume_mbox_in in;
	struct mlx5_page_fault_resume_mbox_out out;
	int err;

	memset(&in, 0, sizeof(in));
	memset(&out, 0, sizeof(out));
	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_PAGE_FAULT_RESUME);
	in.hdr.opmod = 0;
	flags &= (MLX5_PAGE_FAULT_RESUME_REQUESTOR |
		  MLX5_PAGE_FAULT_RESUME_WRITE	   |
		  MLX5_PAGE_FAULT_RESUME_RDMA);
	flags |= (error ? MLX5_PAGE_FAULT_RESUME_ERROR : 0);
	in.flags_qpn = cpu_to_be32((qpn & MLX5_QPN_MASK) |
				   (flags << MLX5_QPN_BITS));
	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	if (err)
		return err;

	if (out.hdr.status)
		err = mlx5_cmd_status_to_err(&out.hdr);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
#endif
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33
	34	#include <linux/gfp.h>
	35	#include <linux/export.h>
	36	#include <linux/mlx5/cmd.h>
	37	#include <linux/mlx5/qp.h>
	38	#include <linux/mlx5/driver.h>
	39
	40	#include "mlx5_core.h"
	41
5903325a EC	42	static struct mlx5_core_rsc_common mlx5_get_rsc(struct mlx5_core_dev dev,
5903325a EC	43	u32 rsn)
e126ba97 EC	44	{
e126ba97 EC	45	struct mlx5_qp_table *table = &dev->priv.qp_table;
5903325a	46	struct mlx5_core_rsc_common *common;
e126ba97 EC	47
	48	spin_lock(&table->lock);
	49
5903325a EC	50	common = radix_tree_lookup(&table->tree, rsn);
	51	if (common)
	52	atomic_inc(&common->refcount);
e126ba97 EC	53
	54	spin_unlock(&table->lock);
	55
5903325a EC	56	if (!common) {
	57	mlx5_core_warn(dev, "Async event for bogus resource 0x%x\n",
	58	rsn);
	59	return NULL;
e126ba97	60	}
5903325a EC	61	return common;
5903325a EC	62	}
e126ba97	63
5903325a EC	64	void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
	65	{
	66	if (atomic_dec_and_test(&common->refcount))
	67	complete(&common->free);
	68	}
	69
	70	void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
	71	{
	72	struct mlx5_core_rsc_common *common = mlx5_get_rsc(dev, rsn);
	73	struct mlx5_core_qp *qp;
	74
	75	if (!common)
	76	return;
	77
	78	switch (common->res) {
	79	case MLX5_RES_QP:
	80	qp = (struct mlx5_core_qp *)common;
	81	qp->event(qp, event_type);
	82	break;
	83
	84	default:
	85	mlx5_core_warn(dev, "invalid resource type for 0x%x\n", rsn);
	86	}
e126ba97	87
5903325a	88	mlx5_core_put_rsc(common);
e126ba97 EC	89	}
e126ba97 EC	90
e420f0c0 HE	91	#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	92	void mlx5_eq_pagefault(struct mlx5_core_dev dev, struct mlx5_eqe eqe)
	93	{
	94	struct mlx5_eqe_page_fault *pf_eqe = &eqe->data.page_fault;
	95	int qpn = be32_to_cpu(pf_eqe->flags_qpn) & MLX5_QPN_MASK;
	96	struct mlx5_core_rsc_common *common = mlx5_get_rsc(dev, qpn);
	97	struct mlx5_core_qp *qp =
	98	container_of(common, struct mlx5_core_qp, common);
	99	struct mlx5_pagefault pfault;
	100
	101	if (!qp) {
	102	mlx5_core_warn(dev, "ODP event for non-existent QP %06x\n",
	103	qpn);
	104	return;
	105	}
	106
	107	pfault.event_subtype = eqe->sub_type;
	108	pfault.flags = (be32_to_cpu(pf_eqe->flags_qpn) >> MLX5_QPN_BITS) &
	109	(MLX5_PFAULT_REQUESTOR \| MLX5_PFAULT_WRITE \| MLX5_PFAULT_RDMA);
	110	pfault.bytes_committed = be32_to_cpu(
	111	pf_eqe->bytes_committed);
	112
	113	mlx5_core_dbg(dev,
	114	"PAGE_FAULT: subtype: 0x%02x, flags: 0x%02x,\n",
	115	eqe->sub_type, pfault.flags);
	116
	117	switch (eqe->sub_type) {
	118	case MLX5_PFAULT_SUBTYPE_RDMA:
	119	/* RDMA based event */
	120	pfault.rdma.r_key =
	121	be32_to_cpu(pf_eqe->rdma.r_key);
	122	pfault.rdma.packet_size =
	123	be16_to_cpu(pf_eqe->rdma.packet_length);
	124	pfault.rdma.rdma_op_len =
	125	be32_to_cpu(pf_eqe->rdma.rdma_op_len);
	126	pfault.rdma.rdma_va =
	127	be64_to_cpu(pf_eqe->rdma.rdma_va);
	128	mlx5_core_dbg(dev,
	129	"PAGE_FAULT: qpn: 0x%06x, r_key: 0x%08x,\n",
	130	qpn, pfault.rdma.r_key);
	131	mlx5_core_dbg(dev,
	132	"PAGE_FAULT: rdma_op_len: 0x%08x,\n",
	133	pfault.rdma.rdma_op_len);
	134	mlx5_core_dbg(dev,
	135	"PAGE_FAULT: rdma_va: 0x%016llx,\n",
	136	pfault.rdma.rdma_va);
	137	mlx5_core_dbg(dev,
	138	"PAGE_FAULT: bytes_committed: 0x%06x\n",
	139	pfault.bytes_committed);
	140	break;
	141
	142	case MLX5_PFAULT_SUBTYPE_WQE:
	143	/* WQE based event */
	144	pfault.wqe.wqe_index =
	145	be16_to_cpu(pf_eqe->wqe.wqe_index);
	146	pfault.wqe.packet_size =
	147	be16_to_cpu(pf_eqe->wqe.packet_length);
	148	mlx5_core_dbg(dev,
	149	"PAGE_FAULT: qpn: 0x%06x, wqe_index: 0x%04x,\n",
	150	qpn, pfault.wqe.wqe_index);
	151	mlx5_core_dbg(dev,
	152	"PAGE_FAULT: bytes_committed: 0x%06x\n",
	153	pfault.bytes_committed);
	154	break;
155
156	default:
157	mlx5_core_warn(dev,
158	"Unsupported page fault event sub-type: 0x%02hhx, QP %06x\n",
159	eqe->sub_type, qpn);
160	/* Unsupported page faults should still be resolved by the
161	* page fault handler
162	*/
163	}
164
165	if (qp->pfault_handler) {
166	qp->pfault_handler(qp, &pfault);
167	} else {
168	mlx5_core_err(dev,
169	"ODP event for QP %08x, without a fault handler in QP\n",
170	qpn);
171	/* Page fault will remain unresolved. QP will hang until it is
172	* destroyed
173	*/
174	}
175
176	mlx5_core_put_rsc(common);
177	}
178	#endif
179
e126ba97 EC	180	int mlx5_core_create_qp(struct mlx5_core_dev *dev,
	181	struct mlx5_core_qp *qp,
	182	struct mlx5_create_qp_mbox_in *in,
	183	int inlen)
	184	{
	185	struct mlx5_qp_table *table = &dev->priv.qp_table;
	186	struct mlx5_create_qp_mbox_out out;
	187	struct mlx5_destroy_qp_mbox_in din;
	188	struct mlx5_destroy_qp_mbox_out dout;
	189	int err;
	190
0b6e81b9	191	memset(&out, 0, sizeof(out));
e126ba97 EC	192	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_QP);
	193
	194	err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
	195	if (err) {
1a91de28	196	mlx5_core_warn(dev, "ret %d\n", err);
e126ba97 EC	197	return err;
	198	}
	199
	200	if (out.hdr.status) {
042b9ada EC	201	mlx5_core_warn(dev, "current num of QPs 0x%x\n",
042b9ada EC	202	atomic_read(&dev->num_qps));
e126ba97 EC	203	return mlx5_cmd_status_to_err(&out.hdr);
	204	}
	205
	206	qp->qpn = be32_to_cpu(out.qpn) & 0xffffff;
	207	mlx5_core_dbg(dev, "qpn = 0x%x\n", qp->qpn);
	208
5903325a	209	qp->common.res = MLX5_RES_QP;
e126ba97 EC	210	spin_lock_irq(&table->lock);
	211	err = radix_tree_insert(&table->tree, qp->qpn, qp);
	212	spin_unlock_irq(&table->lock);
	213	if (err) {
1a91de28	214	mlx5_core_warn(dev, "err %d\n", err);
e126ba97 EC	215	goto err_cmd;
	216	}
	217
	218	err = mlx5_debug_qp_add(dev, qp);
	219	if (err)
	220	mlx5_core_dbg(dev, "failed adding QP 0x%x to debug file system\n",
	221	qp->qpn);
	222
	223	qp->pid = current->pid;
5903325a	224	atomic_set(&qp->common.refcount, 1);
e126ba97	225	atomic_inc(&dev->num_qps);
5903325a	226	init_completion(&qp->common.free);
e126ba97 EC	227
	228	return 0;
	229
	230	err_cmd:
	231	memset(&din, 0, sizeof(din));
	232	memset(&dout, 0, sizeof(dout));
	233	din.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
	234	din.qpn = cpu_to_be32(qp->qpn);
	235	mlx5_cmd_exec(dev, &din, sizeof(din), &out, sizeof(dout));
	236
	237	return err;
	238	}
	239	EXPORT_SYMBOL_GPL(mlx5_core_create_qp);
	240
	241	int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
	242	struct mlx5_core_qp *qp)
	243	{
	244	struct mlx5_destroy_qp_mbox_in in;
	245	struct mlx5_destroy_qp_mbox_out out;
	246	struct mlx5_qp_table *table = &dev->priv.qp_table;
	247	unsigned long flags;
	248	int err;
	249
	250	mlx5_debug_qp_remove(dev, qp);
	251
	252	spin_lock_irqsave(&table->lock, flags);
	253	radix_tree_delete(&table->tree, qp->qpn);
	254	spin_unlock_irqrestore(&table->lock, flags);
	255
5903325a EC	256	mlx5_core_put_rsc((struct mlx5_core_rsc_common *)qp);
5903325a EC	257	wait_for_completion(&qp->common.free);
e126ba97 EC	258
	259	memset(&in, 0, sizeof(in));
	260	memset(&out, 0, sizeof(out));
	261	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
	262	in.qpn = cpu_to_be32(qp->qpn);
	263	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	264	if (err)
	265	return err;
	266
	267	if (out.hdr.status)
	268	return mlx5_cmd_status_to_err(&out.hdr);
	269
	270	atomic_dec(&dev->num_qps);
	271	return 0;
	272	}
	273	EXPORT_SYMBOL_GPL(mlx5_core_destroy_qp);
	274
	275	int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
	276	enum mlx5_qp_state new_state,
	277	struct mlx5_modify_qp_mbox_in *in, int sqd_event,
	278	struct mlx5_core_qp *qp)
	279	{
	280	static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
	281	[MLX5_QP_STATE_RST] = {
	282	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
	283	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
	284	[MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
	285	},
	286	[MLX5_QP_STATE_INIT] = {
	287	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
	288	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
	289	[MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
	290	[MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
	291	},
	292	[MLX5_QP_STATE_RTR] = {
	293	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
	294	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
	295	[MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
	296	},
	297	[MLX5_QP_STATE_RTS] = {
	298	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
	299	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
	300	[MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
e126ba97 EC	301	},
	302	[MLX5_QP_STATE_SQD] = {
	303	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
	304	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
e126ba97 EC	305	},
	306	[MLX5_QP_STATE_SQER] = {
	307	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
	308	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
	309	[MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
	310	},
	311	[MLX5_QP_STATE_ERR] = {
	312	[MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
	313	[MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
	314	}
	315	};
	316
	317	struct mlx5_modify_qp_mbox_out out;
	318	int err = 0;
	319	u16 op;
	320
	321	if (cur_state >= MLX5_QP_NUM_STATE \|\| new_state >= MLX5_QP_NUM_STATE \|\|
	322	!optab[cur_state][new_state])
	323	return -EINVAL;
	324
	325	memset(&out, 0, sizeof(out));
	326	op = optab[cur_state][new_state];
	327	in->hdr.opcode = cpu_to_be16(op);
	328	in->qpn = cpu_to_be32(qp->qpn);
	329	err = mlx5_cmd_exec(dev, in, sizeof(*in), &out, sizeof(out));
	330	if (err)
	331	return err;
	332
	333	return mlx5_cmd_status_to_err(&out.hdr);
	334	}
	335	EXPORT_SYMBOL_GPL(mlx5_core_qp_modify);
	336
	337	void mlx5_init_qp_table(struct mlx5_core_dev *dev)
	338	{
	339	struct mlx5_qp_table *table = &dev->priv.qp_table;
	340
a31208b1	341	memset(table, 0, sizeof(*table));
e126ba97 EC	342	spin_lock_init(&table->lock);
	343	INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
	344	mlx5_qp_debugfs_init(dev);
	345	}
	346
	347	void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev)
	348	{
	349	mlx5_qp_debugfs_cleanup(dev);
	350	}
	351
	352	int mlx5_core_qp_query(struct mlx5_core_dev dev, struct mlx5_core_qp qp,
	353	struct mlx5_query_qp_mbox_out *out, int outlen)
	354	{
	355	struct mlx5_query_qp_mbox_in in;
	356	int err;
	357
	358	memset(&in, 0, sizeof(in));
	359	memset(out, 0, outlen);
	360	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_QP);
	361	in.qpn = cpu_to_be32(qp->qpn);
	362	err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
	363	if (err)
	364	return err;
	365
	366	if (out->hdr.status)
	367	return mlx5_cmd_status_to_err(&out->hdr);
	368
	369	return err;
	370	}
	371	EXPORT_SYMBOL_GPL(mlx5_core_qp_query);
	372
	373	int mlx5_core_xrcd_alloc(struct mlx5_core_dev dev, u32 xrcdn)
	374	{
	375	struct mlx5_alloc_xrcd_mbox_in in;
	376	struct mlx5_alloc_xrcd_mbox_out out;
	377	int err;
	378
	379	memset(&in, 0, sizeof(in));
	380	memset(&out, 0, sizeof(out));
	381	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_XRCD);
	382	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	383	if (err)
	384	return err;
	385
	386	if (out.hdr.status)
	387	err = mlx5_cmd_status_to_err(&out.hdr);
	388	else
	389	*xrcdn = be32_to_cpu(out.xrcdn);
	390
	391	return err;
	392	}
	393	EXPORT_SYMBOL_GPL(mlx5_core_xrcd_alloc);
	394
	395	int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn)
	396	{
	397	struct mlx5_dealloc_xrcd_mbox_in in;
	398	struct mlx5_dealloc_xrcd_mbox_out out;
	399	int err;
	400
	401	memset(&in, 0, sizeof(in));
	402	memset(&out, 0, sizeof(out));
	403	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_XRCD);
	404	in.xrcdn = cpu_to_be32(xrcdn);
	405	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
406	if (err)
407	return err;
408
409	if (out.hdr.status)
410	err = mlx5_cmd_status_to_err(&out.hdr);
411
412	return err;
413	}
414	EXPORT_SYMBOL_GPL(mlx5_core_xrcd_dealloc);
e420f0c0 HE	415
	416	#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	417	int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
	418	u8 flags, int error)
	419	{
	420	struct mlx5_page_fault_resume_mbox_in in;
	421	struct mlx5_page_fault_resume_mbox_out out;
	422	int err;
	423
	424	memset(&in, 0, sizeof(in));
	425	memset(&out, 0, sizeof(out));
	426	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_PAGE_FAULT_RESUME);
	427	in.hdr.opmod = 0;
	428	flags &= (MLX5_PAGE_FAULT_RESUME_REQUESTOR \|
	429	MLX5_PAGE_FAULT_RESUME_WRITE \|
	430	MLX5_PAGE_FAULT_RESUME_RDMA);
	431	flags \|= (error ? MLX5_PAGE_FAULT_RESUME_ERROR : 0);
	432	in.flags_qpn = cpu_to_be32((qpn & MLX5_QPN_MASK) \|
	433	(flags << MLX5_QPN_BITS));
	434	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
	435	if (err)
	436	return err;
	437
	438	if (out.hdr.status)
	439	err = mlx5_cmd_status_to_err(&out.hdr);
	440
	441	return err;
	442	}
	443	EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
	444	#endif