[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / rl.c

/*
 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/cmd.h>
#include "mlx5_core.h"

/* Scheduling element fw management */
int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
				       void *ctx, u32 *element_id)
{
	u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)]  = {0};
	u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0};
	void *schedc;
	int err;

	schedc = MLX5_ADDR_OF(create_scheduling_element_in, in,
			      scheduling_context);
	MLX5_SET(create_scheduling_element_in, in, opcode,
		 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT);
	MLX5_SET(create_scheduling_element_in, in, scheduling_hierarchy,
		 hierarchy);
	memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));

	err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
	if (err)
		return err;

	*element_id = MLX5_GET(create_scheduling_element_out, out,
			       scheduling_element_id);
	return 0;
}

int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
				       void *ctx, u32 element_id,
				       u32 modify_bitmask)
{
	u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)]  = {0};
	u32 out[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0};
	void *schedc;

	schedc = MLX5_ADDR_OF(modify_scheduling_element_in, in,
			      scheduling_context);
	MLX5_SET(modify_scheduling_element_in, in, opcode,
		 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT);
	MLX5_SET(modify_scheduling_element_in, in, scheduling_element_id,
		 element_id);
	MLX5_SET(modify_scheduling_element_in, in, modify_bitmask,
		 modify_bitmask);
	MLX5_SET(modify_scheduling_element_in, in, scheduling_hierarchy,
		 hierarchy);
	memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));

	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
}

int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
					u32 element_id)
{
	u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)]  = {0};
	u32 out[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0};

	MLX5_SET(destroy_scheduling_element_in, in, opcode,
		 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT);
	MLX5_SET(destroy_scheduling_element_in, in, scheduling_element_id,
		 element_id);
	MLX5_SET(destroy_scheduling_element_in, in, scheduling_hierarchy,
		 hierarchy);

	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
}

/* Finds an entry where we can register the given rate
 * If the rate already exists, return the entry where it is registered,
 * otherwise return the first available entry.
 * If the table is full, return NULL
 */
static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
					   u32 rate)
{
	struct mlx5_rl_entry *ret_entry = NULL;
	bool empty_found = false;
	int i;

	for (i = 0; i < table->max_size; i++) {
		if (table->rl_entry[i].rate == rate)
			return &table->rl_entry[i];
		if (!empty_found && !table->rl_entry[i].rate) {
			empty_found = true;
			ret_entry = &table->rl_entry[i];
		}
	}

	return ret_entry;
}

static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev,
				   u32 rate, u16 index)
{
	u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)]   = {0};
	u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0};

	MLX5_SET(set_pp_rate_limit_in, in, opcode,
		 MLX5_CMD_OP_SET_PP_RATE_LIMIT);
	MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, index);
	MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rate);
	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
}

bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate)
{
	struct mlx5_rl_table *table = &dev->priv.rl_table;

	return (rate <= table->max_rate && rate >= table->min_rate);
}
EXPORT_SYMBOL(mlx5_rl_is_in_range);

int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index)
{
	struct mlx5_rl_table *table = &dev->priv.rl_table;
	struct mlx5_rl_entry *entry;
	int err = 0;

	mutex_lock(&table->rl_lock);

	if (!rate || !mlx5_rl_is_in_range(dev, rate)) {
		mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n",
			      rate, table->min_rate, table->max_rate);
		err = -EINVAL;
		goto out;
	}

	entry = find_rl_entry(table, rate);
	if (!entry) {
		mlx5_core_err(dev, "Max number of %u rates reached\n",
			      table->max_size);
		err = -ENOSPC;
		goto out;
	}
	if (entry->refcount) {
		/* rate already configured */
		entry->refcount++;
	} else {
		/* new rate limit */
		err = mlx5_set_pp_rate_limit_cmd(dev, rate, entry->index);
		if (err) {
			mlx5_core_err(dev, "Failed configuring rate: %u (%d)\n",
				      rate, err);
			goto out;
		}
		entry->rate = rate;
		entry->refcount = 1;
	}
	*index = entry->index;

out:
	mutex_unlock(&table->rl_lock);
	return err;
}
EXPORT_SYMBOL(mlx5_rl_add_rate);

void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate)
{
	struct mlx5_rl_table *table = &dev->priv.rl_table;
	struct mlx5_rl_entry *entry = NULL;

	/* 0 is a reserved value for unlimited rate */
	if (rate == 0)
		return;

	mutex_lock(&table->rl_lock);
	entry = find_rl_entry(table, rate);
	if (!entry || !entry->refcount) {
		mlx5_core_warn(dev, "Rate %u is not configured\n", rate);
		goto out;
	}

	entry->refcount--;
	if (!entry->refcount) {
		/* need to remove rate */
		mlx5_set_pp_rate_limit_cmd(dev, 0, entry->index);
		entry->rate = 0;
	}

out:
	mutex_unlock(&table->rl_lock);
}
EXPORT_SYMBOL(mlx5_rl_remove_rate);

int mlx5_init_rl_table(struct mlx5_core_dev *dev)
{
	struct mlx5_rl_table *table = &dev->priv.rl_table;
	int i;

	mutex_init(&table->rl_lock);
	if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) {
		table->max_size = 0;
		return 0;
	}

	/* First entry is reserved for unlimited rate */
	table->max_size = MLX5_CAP_QOS(dev, packet_pacing_rate_table_size) - 1;
	table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate);
	table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate);

	table->rl_entry = kcalloc(table->max_size, sizeof(struct mlx5_rl_entry),
				  GFP_KERNEL);
	if (!table->rl_entry)
		return -ENOMEM;

	/* The index represents the index in HW rate limit table
	 * Index 0 is reserved for unlimited rate
	 */
	for (i = 0; i < table->max_size; i++)
		table->rl_entry[i].index = i + 1;

	/* Index 0 is reserved */
	mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n",
		       table->max_size,
		       table->min_rate >> 10,
		       table->max_rate >> 10);

	return 0;
}

void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
{
	struct mlx5_rl_table *table = &dev->priv.rl_table;
	int i;

	/* Clear all configured rates */
	for (i = 0; i < table->max_size; i++)
		if (table->rl_entry[i].rate)
			mlx5_set_pp_rate_limit_cmd(dev, 0,
						   table->rl_entry[i].index);

	kfree(dev->priv.rl_table.rl_entry);
}
Commit	Line	Data
1466cc5b YP	1	/*
	2	* Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/mlx5/driver.h>
	36	#include <linux/mlx5/cmd.h>
	37	#include "mlx5_core.h"
	38
813f8540 MHY	39	/* Scheduling element fw management */
	40	int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
	41	void ctx, u32 element_id)
	42	{
	43	u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0};
	44	u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0};
	45	void *schedc;
	46	int err;
	47
	48	schedc = MLX5_ADDR_OF(create_scheduling_element_in, in,
	49	scheduling_context);
	50	MLX5_SET(create_scheduling_element_in, in, opcode,
	51	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT);
	52	MLX5_SET(create_scheduling_element_in, in, scheduling_hierarchy,
	53	hierarchy);
	54	memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
	55
	56	err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
	57	if (err)
	58	return err;
	59
	60	*element_id = MLX5_GET(create_scheduling_element_out, out,
	61	scheduling_element_id);
	62	return 0;
	63	}
	64
	65	int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
	66	void *ctx, u32 element_id,
	67	u32 modify_bitmask)
	68	{
	69	u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0};
	70	u32 out[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0};
	71	void *schedc;
	72
	73	schedc = MLX5_ADDR_OF(modify_scheduling_element_in, in,
	74	scheduling_context);
	75	MLX5_SET(modify_scheduling_element_in, in, opcode,
	76	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT);
	77	MLX5_SET(modify_scheduling_element_in, in, scheduling_element_id,
	78	element_id);
	79	MLX5_SET(modify_scheduling_element_in, in, modify_bitmask,
	80	modify_bitmask);
	81	MLX5_SET(modify_scheduling_element_in, in, scheduling_hierarchy,
	82	hierarchy);
	83	memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
	84
	85	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
	86	}
	87
	88	int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
	89	u32 element_id)
	90	{
	91	u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0};
	92	u32 out[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0};
	93
	94	MLX5_SET(destroy_scheduling_element_in, in, opcode,
	95	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT);
	96	MLX5_SET(destroy_scheduling_element_in, in, scheduling_element_id,
	97	element_id);
	98	MLX5_SET(destroy_scheduling_element_in, in, scheduling_hierarchy,
	99	hierarchy);
	100
	101	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
	102	}
103
1466cc5b YP	104	/* Finds an entry where we can register the given rate
	105	* If the rate already exists, return the entry where it is registered,
	106	* otherwise return the first available entry.
	107	* If the table is full, return NULL
	108	*/
	109	static struct mlx5_rl_entry find_rl_entry(struct mlx5_rl_table table,
	110	u32 rate)
	111	{
	112	struct mlx5_rl_entry *ret_entry = NULL;
	113	bool empty_found = false;
	114	int i;
	115
	116	for (i = 0; i < table->max_size; i++) {
	117	if (table->rl_entry[i].rate == rate)
	118	return &table->rl_entry[i];
	119	if (!empty_found && !table->rl_entry[i].rate) {
	120	empty_found = true;
	121	ret_entry = &table->rl_entry[i];
	122	}
	123	}
	124
	125	return ret_entry;
	126	}
	127
37e92a9d	128	static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev,
1466cc5b YP	129	u32 rate, u16 index)
1466cc5b YP	130	{
37e92a9d EBE	131	u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0};
37e92a9d EBE	132	u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0};
1466cc5b	133
37e92a9d EBE	134	MLX5_SET(set_pp_rate_limit_in, in, opcode,
	135	MLX5_CMD_OP_SET_PP_RATE_LIMIT);
	136	MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, index);
	137	MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rate);
c4f287c4	138	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
1466cc5b YP	139	}
	140
	141	bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate)
	142	{
	143	struct mlx5_rl_table *table = &dev->priv.rl_table;
	144
	145	return (rate <= table->max_rate && rate >= table->min_rate);
	146	}
	147	EXPORT_SYMBOL(mlx5_rl_is_in_range);
	148
	149	int mlx5_rl_add_rate(struct mlx5_core_dev dev, u32 rate, u16 index)
	150	{
	151	struct mlx5_rl_table *table = &dev->priv.rl_table;
	152	struct mlx5_rl_entry *entry;
	153	int err = 0;
	154
	155	mutex_lock(&table->rl_lock);
	156
	157	if (!rate \|\| !mlx5_rl_is_in_range(dev, rate)) {
	158	mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n",
	159	rate, table->min_rate, table->max_rate);
	160	err = -EINVAL;
	161	goto out;
	162	}
	163
	164	entry = find_rl_entry(table, rate);
	165	if (!entry) {
	166	mlx5_core_err(dev, "Max number of %u rates reached\n",
	167	table->max_size);
	168	err = -ENOSPC;
	169	goto out;
	170	}
	171	if (entry->refcount) {
	172	/* rate already configured */
	173	entry->refcount++;
	174	} else {
	175	/* new rate limit */
37e92a9d	176	err = mlx5_set_pp_rate_limit_cmd(dev, rate, entry->index);
1466cc5b YP	177	if (err) {
	178	mlx5_core_err(dev, "Failed configuring rate: %u (%d)\n",
	179	rate, err);
	180	goto out;
	181	}
	182	entry->rate = rate;
	183	entry->refcount = 1;
	184	}
	185	*index = entry->index;
	186
	187	out:
	188	mutex_unlock(&table->rl_lock);
	189	return err;
	190	}
	191	EXPORT_SYMBOL(mlx5_rl_add_rate);
	192
	193	void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate)
	194	{
	195	struct mlx5_rl_table *table = &dev->priv.rl_table;
	196	struct mlx5_rl_entry *entry = NULL;
	197
	198	/* 0 is a reserved value for unlimited rate */
	199	if (rate == 0)
	200	return;
	201
	202	mutex_lock(&table->rl_lock);
	203	entry = find_rl_entry(table, rate);
	204	if (!entry \|\| !entry->refcount) {
	205	mlx5_core_warn(dev, "Rate %u is not configured\n", rate);
	206	goto out;
	207	}
	208
	209	entry->refcount--;
	210	if (!entry->refcount) {
	211	/* need to remove rate */
37e92a9d	212	mlx5_set_pp_rate_limit_cmd(dev, 0, entry->index);
1466cc5b YP	213	entry->rate = 0;
	214	}
	215
	216	out:
	217	mutex_unlock(&table->rl_lock);
	218	}
	219	EXPORT_SYMBOL(mlx5_rl_remove_rate);
	220
	221	int mlx5_init_rl_table(struct mlx5_core_dev *dev)
	222	{
	223	struct mlx5_rl_table *table = &dev->priv.rl_table;
	224	int i;
	225
	226	mutex_init(&table->rl_lock);
	227	if (!MLX5_CAP_GEN(dev, qos) \|\| !MLX5_CAP_QOS(dev, packet_pacing)) {
	228	table->max_size = 0;
	229	return 0;
	230	}
	231
	232	/* First entry is reserved for unlimited rate */
	233	table->max_size = MLX5_CAP_QOS(dev, packet_pacing_rate_table_size) - 1;
	234	table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate);
	235	table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate);
	236
	237	table->rl_entry = kcalloc(table->max_size, sizeof(struct mlx5_rl_entry),
	238	GFP_KERNEL);
	239	if (!table->rl_entry)
	240	return -ENOMEM;
	241
	242	/* The index represents the index in HW rate limit table
	243	* Index 0 is reserved for unlimited rate
	244	*/
	245	for (i = 0; i < table->max_size; i++)
	246	table->rl_entry[i].index = i + 1;
	247
	248	/* Index 0 is reserved */
	249	mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n",
	250	table->max_size,
	251	table->min_rate >> 10,
	252	table->max_rate >> 10);
	253
	254	return 0;
	255	}
	256
	257	void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
	258	{
	259	struct mlx5_rl_table *table = &dev->priv.rl_table;
	260	int i;
	261
	262	/* Clear all configured rates */
	263	for (i = 0; i < table->max_size; i++)
	264	if (table->rl_entry[i].rate)
37e92a9d EBE	265	mlx5_set_pp_rate_limit_cmd(dev, 0,
37e92a9d EBE	266	table->rl_entry[i].index);
1466cc5b YP	267
	268	kfree(dev->priv.rl_table.rl_entry);
	269	}