[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / sriov.c

/*
 * Copyright (c) 2014, Mellanox Technologies inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/pci.h>
#include <linux/mlx5/driver.h>
#include "mlx5_core.h"
#ifdef CONFIG_MLX5_CORE_EN
#include "eswitch.h"
#endif

bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
{
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;

	return !!sriov->num_vfs;
}

static int mlx5_device_enable_sriov(struct mlx5_core_dev *dev, int num_vfs)
{
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	int err;
	int vf;

	if (sriov->enabled_vfs) {
		mlx5_core_warn(dev,
			       "failed to enable SRIOV on device, already enabled with %d vfs\n",
			       sriov->enabled_vfs);
		return -EBUSY;
	}

#ifdef CONFIG_MLX5_CORE_EN
	err = mlx5_eswitch_enable_sriov(dev->priv.eswitch, num_vfs, SRIOV_LEGACY);
	if (err) {
		mlx5_core_warn(dev,
			       "failed to enable eswitch SRIOV (%d)\n", err);
		return err;
	}
#endif

	for (vf = 0; vf < num_vfs; vf++) {
		err = mlx5_core_enable_hca(dev, vf + 1);
		if (err) {
			mlx5_core_warn(dev, "failed to enable VF %d (%d)\n", vf, err);
			continue;
		}
		sriov->vfs_ctx[vf].enabled = 1;
		sriov->enabled_vfs++;
		mlx5_core_dbg(dev, "successfully enabled VF* %d\n", vf);

	}

	return 0;
}

static void mlx5_device_disable_sriov(struct mlx5_core_dev *dev)
{
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	int err;
	int vf;

	if (!sriov->enabled_vfs)
#ifdef CONFIG_MLX5_CORE_EN
		goto disable_sriov_resources;
#else
		return;
#endif

	for (vf = 0; vf < sriov->num_vfs; vf++) {
		if (!sriov->vfs_ctx[vf].enabled)
			continue;
		err = mlx5_core_disable_hca(dev, vf + 1);
		if (err) {
			mlx5_core_warn(dev, "failed to disable VF %d\n", vf);
			continue;
		}
		sriov->vfs_ctx[vf].enabled = 0;
		sriov->enabled_vfs--;
	}

#ifdef CONFIG_MLX5_CORE_EN
disable_sriov_resources:
	mlx5_eswitch_disable_sriov(dev->priv.eswitch);
#endif

	if (mlx5_wait_for_vf_pages(dev))
		mlx5_core_warn(dev, "timeout reclaiming VFs pages\n");
}

static int mlx5_pci_enable_sriov(struct pci_dev *pdev, int num_vfs)
{
	struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
	int err = 0;

	if (pci_num_vf(pdev)) {
		mlx5_core_warn(dev, "Unable to enable pci sriov, already enabled\n");
		return -EBUSY;
	}

	err = pci_enable_sriov(pdev, num_vfs);
	if (err)
		mlx5_core_warn(dev, "pci_enable_sriov failed : %d\n", err);

	return err;
}

static void mlx5_pci_disable_sriov(struct pci_dev *pdev)
{
	pci_disable_sriov(pdev);
}

static int mlx5_sriov_enable(struct pci_dev *pdev, int num_vfs)
{
	struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	int err = 0;

	err = mlx5_device_enable_sriov(dev, num_vfs);
	if (err) {
		mlx5_core_warn(dev, "mlx5_device_enable_sriov failed : %d\n", err);
		return err;
	}

	err = mlx5_pci_enable_sriov(pdev, num_vfs);
	if (err) {
		mlx5_core_warn(dev, "mlx5_pci_enable_sriov failed : %d\n", err);
		mlx5_device_disable_sriov(dev);
		return err;
	}

	sriov->num_vfs = num_vfs;

	return 0;
}

static void mlx5_sriov_disable(struct pci_dev *pdev)
{
	struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;

	mlx5_pci_disable_sriov(pdev);
	mlx5_device_disable_sriov(dev);
	sriov->num_vfs = 0;
}

int mlx5_core_sriov_configure(struct pci_dev *pdev, int num_vfs)
{
	struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
	int err = 0;

	mlx5_core_dbg(dev, "requested num_vfs %d\n", num_vfs);
	if (!mlx5_core_is_pf(dev))
		return -EPERM;

	if (num_vfs) {
		int ret;

		ret = mlx5_lag_forbid(dev);
		if (ret && (ret != -ENODEV))
			return ret;
	}

	if (num_vfs) {
		err = mlx5_sriov_enable(pdev, num_vfs);
	} else {
		mlx5_sriov_disable(pdev);
		mlx5_lag_allow(dev);
	}

	return err ? err : num_vfs;
}

int mlx5_sriov_attach(struct mlx5_core_dev *dev)
{
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;

	if (!mlx5_core_is_pf(dev) || !sriov->num_vfs)
		return 0;

	/* If sriov VFs exist in PCI level, enable them in device level */
	return mlx5_device_enable_sriov(dev, sriov->num_vfs);
}

void mlx5_sriov_detach(struct mlx5_core_dev *dev)
{
	if (!mlx5_core_is_pf(dev))
		return;

	mlx5_device_disable_sriov(dev);
}

int mlx5_sriov_init(struct mlx5_core_dev *dev)
{
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	struct pci_dev *pdev = dev->pdev;
	int total_vfs;

	if (!mlx5_core_is_pf(dev))
		return 0;

	total_vfs = pci_sriov_get_totalvfs(pdev);
	sriov->num_vfs = pci_num_vf(pdev);
	sriov->vfs_ctx = kcalloc(total_vfs, sizeof(*sriov->vfs_ctx), GFP_KERNEL);
	if (!sriov->vfs_ctx)
		return -ENOMEM;

	return 0;
}

void mlx5_sriov_cleanup(struct mlx5_core_dev *dev)
{
	struct mlx5_core_sriov *sriov = &dev->priv.sriov;

	if (!mlx5_core_is_pf(dev))
		return;

	kfree(sriov->vfs_ctx);
}
Commit	Line	Data
fc50db98 EC	1	/*
	2	* Copyright (c) 2014, Mellanox Technologies inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/pci.h>
	34	#include <linux/mlx5/driver.h>
	35	#include "mlx5_core.h"
81848731 SM	36	#ifdef CONFIG_MLX5_CORE_EN
	37	#include "eswitch.h"
	38	#endif
fc50db98	39
edb31b16 AH	40	bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
	41	{
	42	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	43
	44	return !!sriov->num_vfs;
	45	}
	46
6b6adee3	47	static int mlx5_device_enable_sriov(struct mlx5_core_dev *dev, int num_vfs)
fc50db98 EC	48	{
	49	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	50	int err;
	51	int vf;
	52
6b6adee3 MHY	53	if (sriov->enabled_vfs) {
	54	mlx5_core_warn(dev,
	55	"failed to enable SRIOV on device, already enabled with %d vfs\n",
	56	sriov->enabled_vfs);
	57	return -EBUSY;
	58	}
	59
	60	#ifdef CONFIG_MLX5_CORE_EN
	61	err = mlx5_eswitch_enable_sriov(dev->priv.eswitch, num_vfs, SRIOV_LEGACY);
	62	if (err) {
	63	mlx5_core_warn(dev,
	64	"failed to enable eswitch SRIOV (%d)\n", err);
	65	return err;
	66	}
	67	#endif
	68
	69	for (vf = 0; vf < num_vfs; vf++) {
	70	err = mlx5_core_enable_hca(dev, vf + 1);
fc50db98	71	if (err) {
6b6adee3 MHY	72	mlx5_core_warn(dev, "failed to enable VF %d (%d)\n", vf, err);
6b6adee3 MHY	73	continue;
fc50db98	74	}
6b6adee3 MHY	75	sriov->vfs_ctx[vf].enabled = 1;
	76	sriov->enabled_vfs++;
	77	mlx5_core_dbg(dev, "successfully enabled VF* %d\n", vf);
	78
fc50db98	79	}
6b6adee3 MHY	80
6b6adee3 MHY	81	return 0;
fc50db98 EC	82	}
fc50db98 EC	83
6b6adee3	84	static void mlx5_device_disable_sriov(struct mlx5_core_dev *dev)
fc50db98 EC	85	{
fc50db98 EC	86	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
6b6adee3	87	int err;
fc50db98 EC	88	int vf;
fc50db98 EC	89
6b6adee3	90	if (!sriov->enabled_vfs)
079adf05 EBE	91	#ifdef CONFIG_MLX5_CORE_EN
	92	goto disable_sriov_resources;
	93	#else
6b6adee3	94	return;
079adf05	95	#endif
6b6adee3 MHY	96
	97	for (vf = 0; vf < sriov->num_vfs; vf++) {
	98	if (!sriov->vfs_ctx[vf].enabled)
	99	continue;
	100	err = mlx5_core_disable_hca(dev, vf + 1);
	101	if (err) {
	102	mlx5_core_warn(dev, "failed to disable VF %d\n", vf);
	103	continue;
fc50db98	104	}
6b6adee3 MHY	105	sriov->vfs_ctx[vf].enabled = 0;
6b6adee3 MHY	106	sriov->enabled_vfs--;
fc50db98	107	}
6b6adee3 MHY	108
6b6adee3 MHY	109	#ifdef CONFIG_MLX5_CORE_EN
079adf05	110	disable_sriov_resources:
6b6adee3 MHY	111	mlx5_eswitch_disable_sriov(dev->priv.eswitch);
	112	#endif
	113
	114	if (mlx5_wait_for_vf_pages(dev))
	115	mlx5_core_warn(dev, "timeout reclaiming VFs pages\n");
fc50db98 EC	116	}
fc50db98 EC	117
6b6adee3	118	static int mlx5_pci_enable_sriov(struct pci_dev *pdev, int num_vfs)
fc50db98 EC	119	{
fc50db98 EC	120	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
6b6adee3	121	int err = 0;
fc50db98	122
6b6adee3 MHY	123	if (pci_num_vf(pdev)) {
	124	mlx5_core_warn(dev, "Unable to enable pci sriov, already enabled\n");
	125	return -EBUSY;
fc50db98 EC	126	}
fc50db98 EC	127
6b6adee3 MHY	128	err = pci_enable_sriov(pdev, num_vfs);
	129	if (err)
	130	mlx5_core_warn(dev, "pci_enable_sriov failed : %d\n", err);
fc50db98	131
fc50db98 EC	132	return err;
	133	}
	134
6b6adee3 MHY	135	static void mlx5_pci_disable_sriov(struct pci_dev *pdev)
	136	{
	137	pci_disable_sriov(pdev);
	138	}
	139
	140	static int mlx5_sriov_enable(struct pci_dev *pdev, int num_vfs)
fc50db98 EC	141	{
	142	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
	143	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
6b6adee3	144	int err = 0;
fc50db98	145
6b6adee3 MHY	146	err = mlx5_device_enable_sriov(dev, num_vfs);
	147	if (err) {
	148	mlx5_core_warn(dev, "mlx5_device_enable_sriov failed : %d\n", err);
	149	return err;
	150	}
fc50db98	151
6b6adee3	152	err = mlx5_pci_enable_sriov(pdev, num_vfs);
fc50db98	153	if (err) {
6b6adee3 MHY	154	mlx5_core_warn(dev, "mlx5_pci_enable_sriov failed : %d\n", err);
6b6adee3 MHY	155	mlx5_device_disable_sriov(dev);
fc50db98 EC	156	return err;
	157	}
	158
6b6adee3 MHY	159	sriov->num_vfs = num_vfs;
6b6adee3 MHY	160
fc50db98 EC	161	return 0;
	162	}
	163
6b6adee3	164	static void mlx5_sriov_disable(struct pci_dev *pdev)
fc50db98	165	{
6b6adee3	166	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
fc50db98 EC	167	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
fc50db98 EC	168
6b6adee3 MHY	169	mlx5_pci_disable_sriov(pdev);
6b6adee3 MHY	170	mlx5_device_disable_sriov(dev);
fc50db98 EC	171	sriov->num_vfs = 0;
	172	}
	173
	174	int mlx5_core_sriov_configure(struct pci_dev *pdev, int num_vfs)
	175	{
	176	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
6b6adee3	177	int err = 0;
fc50db98	178
c19ca6cb	179	mlx5_core_dbg(dev, "requested num_vfs %d\n", num_vfs);
fc50db98 EC	180	if (!mlx5_core_is_pf(dev))
	181	return -EPERM;
	182
552db7bc MS	183	if (num_vfs) {
	184	int ret;
	185
	186	ret = mlx5_lag_forbid(dev);
	187	if (ret && (ret != -ENODEV))
	188	return ret;
edb31b16 AH	189	}
edb31b16 AH	190
552db7bc	191	if (num_vfs) {
6b6adee3	192	err = mlx5_sriov_enable(pdev, num_vfs);
552db7bc	193	} else {
6b6adee3	194	mlx5_sriov_disable(pdev);
552db7bc MS	195	mlx5_lag_allow(dev);
552db7bc MS	196	}
fc50db98	197
6b6adee3	198	return err ? err : num_vfs;
fc50db98 EC	199	}
fc50db98 EC	200
acab721b MHY	201	int mlx5_sriov_attach(struct mlx5_core_dev *dev)
	202	{
	203	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	204
	205	if (!mlx5_core_is_pf(dev) \|\| !sriov->num_vfs)
	206	return 0;
	207
	208	/* If sriov VFs exist in PCI level, enable them in device level */
	209	return mlx5_device_enable_sriov(dev, sriov->num_vfs);
	210	}
	211
	212	void mlx5_sriov_detach(struct mlx5_core_dev *dev)
	213	{
	214	if (!mlx5_core_is_pf(dev))
	215	return;
	216
	217	mlx5_device_disable_sriov(dev);
	218	}
	219
fc50db98 EC	220	int mlx5_sriov_init(struct mlx5_core_dev *dev)
	221	{
	222	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
	223	struct pci_dev *pdev = dev->pdev;
6b6adee3	224	int total_vfs;
fc50db98 EC	225
	226	if (!mlx5_core_is_pf(dev))
	227	return 0;
	228
6b6adee3 MHY	229	total_vfs = pci_sriov_get_totalvfs(pdev);
	230	sriov->num_vfs = pci_num_vf(pdev);
	231	sriov->vfs_ctx = kcalloc(total_vfs, sizeof(*sriov->vfs_ctx), GFP_KERNEL);
fc50db98 EC	232	if (!sriov->vfs_ctx)
	233	return -ENOMEM;
	234
c2d6e31a	235	return 0;
fc50db98 EC	236	}
fc50db98 EC	237
6b6adee3	238	void mlx5_sriov_cleanup(struct mlx5_core_dev *dev)
fc50db98	239	{
6b6adee3	240	struct mlx5_core_sriov *sriov = &dev->priv.sriov;
fc50db98 EC	241
fc50db98 EC	242	if (!mlx5_core_is_pf(dev))
6b6adee3	243	return;
c2d6e31a	244
6b6adee3	245	kfree(sriov->vfs_ctx);
fc50db98	246	}