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4ec14b76 IS |
1 | /* |
2 | * drivers/net/ethernet/mellanox/mlxsw/reg.h | |
3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. | |
69c407aa | 4 | * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com> |
4ec14b76 | 5 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> |
6f9fc3ce | 6 | * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com> |
4457b3df | 7 | * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com> |
4ec14b76 IS |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions are met: | |
11 | * | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions and the following disclaimer. | |
14 | * 2. Redistributions in binary form must reproduce the above copyright | |
15 | * notice, this list of conditions and the following disclaimer in the | |
16 | * documentation and/or other materials provided with the distribution. | |
17 | * 3. Neither the names of the copyright holders nor the names of its | |
18 | * contributors may be used to endorse or promote products derived from | |
19 | * this software without specific prior written permission. | |
20 | * | |
21 | * Alternatively, this software may be distributed under the terms of the | |
22 | * GNU General Public License ("GPL") version 2 as published by the Free | |
23 | * Software Foundation. | |
24 | * | |
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
28 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
29 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
35 | * POSSIBILITY OF SUCH DAMAGE. | |
36 | */ | |
37 | ||
38 | #ifndef _MLXSW_REG_H | |
39 | #define _MLXSW_REG_H | |
40 | ||
41 | #include <linux/string.h> | |
42 | #include <linux/bitops.h> | |
43 | #include <linux/if_vlan.h> | |
44 | ||
45 | #include "item.h" | |
46 | #include "port.h" | |
47 | ||
48 | struct mlxsw_reg_info { | |
49 | u16 id; | |
50 | u16 len; /* In u8 */ | |
8e9658d5 | 51 | const char *name; |
4ec14b76 IS |
52 | }; |
53 | ||
21978dcf JP |
54 | #define MLXSW_REG_DEFINE(_name, _id, _len) \ |
55 | static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ | |
56 | .id = _id, \ | |
57 | .len = _len, \ | |
8e9658d5 | 58 | .name = #_name, \ |
21978dcf JP |
59 | } |
60 | ||
4ec14b76 IS |
61 | #define MLXSW_REG(type) (&mlxsw_reg_##type) |
62 | #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len | |
63 | #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) | |
64 | ||
65 | /* SGCR - Switch General Configuration Register | |
66 | * -------------------------------------------- | |
67 | * This register is used for configuration of the switch capabilities. | |
68 | */ | |
69 | #define MLXSW_REG_SGCR_ID 0x2000 | |
70 | #define MLXSW_REG_SGCR_LEN 0x10 | |
71 | ||
21978dcf | 72 | MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); |
4ec14b76 IS |
73 | |
74 | /* reg_sgcr_llb | |
75 | * Link Local Broadcast (Default=0) | |
76 | * When set, all Link Local packets (224.0.0.X) will be treated as broadcast | |
77 | * packets and ignore the IGMP snooping entries. | |
78 | * Access: RW | |
79 | */ | |
80 | MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); | |
81 | ||
82 | static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) | |
83 | { | |
84 | MLXSW_REG_ZERO(sgcr, payload); | |
85 | mlxsw_reg_sgcr_llb_set(payload, !!llb); | |
86 | } | |
87 | ||
88 | /* SPAD - Switch Physical Address Register | |
89 | * --------------------------------------- | |
90 | * The SPAD register configures the switch physical MAC address. | |
91 | */ | |
92 | #define MLXSW_REG_SPAD_ID 0x2002 | |
93 | #define MLXSW_REG_SPAD_LEN 0x10 | |
94 | ||
21978dcf | 95 | MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); |
4ec14b76 IS |
96 | |
97 | /* reg_spad_base_mac | |
98 | * Base MAC address for the switch partitions. | |
99 | * Per switch partition MAC address is equal to: | |
100 | * base_mac + swid | |
101 | * Access: RW | |
102 | */ | |
103 | MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); | |
104 | ||
fabe5483 ER |
105 | /* SMID - Switch Multicast ID |
106 | * -------------------------- | |
107 | * The MID record maps from a MID (Multicast ID), which is a unique identifier | |
108 | * of the multicast group within the stacking domain, into a list of local | |
109 | * ports into which the packet is replicated. | |
110 | */ | |
111 | #define MLXSW_REG_SMID_ID 0x2007 | |
112 | #define MLXSW_REG_SMID_LEN 0x240 | |
113 | ||
21978dcf | 114 | MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); |
fabe5483 ER |
115 | |
116 | /* reg_smid_swid | |
117 | * Switch partition ID. | |
118 | * Access: Index | |
119 | */ | |
120 | MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); | |
121 | ||
122 | /* reg_smid_mid | |
123 | * Multicast identifier - global identifier that represents the multicast group | |
124 | * across all devices. | |
125 | * Access: Index | |
126 | */ | |
127 | MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); | |
128 | ||
129 | /* reg_smid_port | |
130 | * Local port memebership (1 bit per port). | |
131 | * Access: RW | |
132 | */ | |
133 | MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); | |
134 | ||
135 | /* reg_smid_port_mask | |
136 | * Local port mask (1 bit per port). | |
137 | * Access: W | |
138 | */ | |
139 | MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); | |
140 | ||
141 | static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, | |
142 | u8 port, bool set) | |
143 | { | |
144 | MLXSW_REG_ZERO(smid, payload); | |
145 | mlxsw_reg_smid_swid_set(payload, 0); | |
146 | mlxsw_reg_smid_mid_set(payload, mid); | |
147 | mlxsw_reg_smid_port_set(payload, port, set); | |
148 | mlxsw_reg_smid_port_mask_set(payload, port, 1); | |
149 | } | |
150 | ||
e61011b5 IS |
151 | /* SSPR - Switch System Port Record Register |
152 | * ----------------------------------------- | |
153 | * Configures the system port to local port mapping. | |
154 | */ | |
155 | #define MLXSW_REG_SSPR_ID 0x2008 | |
156 | #define MLXSW_REG_SSPR_LEN 0x8 | |
157 | ||
21978dcf | 158 | MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); |
e61011b5 IS |
159 | |
160 | /* reg_sspr_m | |
161 | * Master - if set, then the record describes the master system port. | |
162 | * This is needed in case a local port is mapped into several system ports | |
163 | * (for multipathing). That number will be reported as the source system | |
164 | * port when packets are forwarded to the CPU. Only one master port is allowed | |
165 | * per local port. | |
166 | * | |
167 | * Note: Must be set for Spectrum. | |
168 | * Access: RW | |
169 | */ | |
170 | MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); | |
171 | ||
172 | /* reg_sspr_local_port | |
173 | * Local port number. | |
174 | * | |
175 | * Access: RW | |
176 | */ | |
177 | MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); | |
178 | ||
179 | /* reg_sspr_sub_port | |
180 | * Virtual port within the physical port. | |
181 | * Should be set to 0 when virtual ports are not enabled on the port. | |
182 | * | |
183 | * Access: RW | |
184 | */ | |
185 | MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); | |
186 | ||
187 | /* reg_sspr_system_port | |
188 | * Unique identifier within the stacking domain that represents all the ports | |
189 | * that are available in the system (external ports). | |
190 | * | |
191 | * Currently, only single-ASIC configurations are supported, so we default to | |
192 | * 1:1 mapping between system ports and local ports. | |
193 | * Access: Index | |
194 | */ | |
195 | MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); | |
196 | ||
197 | static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) | |
198 | { | |
199 | MLXSW_REG_ZERO(sspr, payload); | |
200 | mlxsw_reg_sspr_m_set(payload, 1); | |
201 | mlxsw_reg_sspr_local_port_set(payload, local_port); | |
202 | mlxsw_reg_sspr_sub_port_set(payload, 0); | |
203 | mlxsw_reg_sspr_system_port_set(payload, local_port); | |
204 | } | |
205 | ||
e534a56a JP |
206 | /* SFDAT - Switch Filtering Database Aging Time |
207 | * -------------------------------------------- | |
208 | * Controls the Switch aging time. Aging time is able to be set per Switch | |
209 | * Partition. | |
210 | */ | |
211 | #define MLXSW_REG_SFDAT_ID 0x2009 | |
212 | #define MLXSW_REG_SFDAT_LEN 0x8 | |
213 | ||
21978dcf | 214 | MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); |
e534a56a JP |
215 | |
216 | /* reg_sfdat_swid | |
217 | * Switch partition ID. | |
218 | * Access: Index | |
219 | */ | |
220 | MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); | |
221 | ||
222 | /* reg_sfdat_age_time | |
223 | * Aging time in seconds | |
224 | * Min - 10 seconds | |
225 | * Max - 1,000,000 seconds | |
226 | * Default is 300 seconds. | |
227 | * Access: RW | |
228 | */ | |
229 | MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); | |
230 | ||
231 | static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) | |
232 | { | |
233 | MLXSW_REG_ZERO(sfdat, payload); | |
234 | mlxsw_reg_sfdat_swid_set(payload, 0); | |
235 | mlxsw_reg_sfdat_age_time_set(payload, age_time); | |
236 | } | |
237 | ||
236033b3 JP |
238 | /* SFD - Switch Filtering Database |
239 | * ------------------------------- | |
240 | * The following register defines the access to the filtering database. | |
241 | * The register supports querying, adding, removing and modifying the database. | |
242 | * The access is optimized for bulk updates in which case more than one | |
243 | * FDB record is present in the same command. | |
244 | */ | |
245 | #define MLXSW_REG_SFD_ID 0x200A | |
246 | #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ | |
247 | #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ | |
248 | #define MLXSW_REG_SFD_REC_MAX_COUNT 64 | |
249 | #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ | |
250 | MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) | |
251 | ||
21978dcf | 252 | MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); |
236033b3 JP |
253 | |
254 | /* reg_sfd_swid | |
255 | * Switch partition ID for queries. Reserved on Write. | |
256 | * Access: Index | |
257 | */ | |
258 | MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); | |
259 | ||
260 | enum mlxsw_reg_sfd_op { | |
261 | /* Dump entire FDB a (process according to record_locator) */ | |
262 | MLXSW_REG_SFD_OP_QUERY_DUMP = 0, | |
263 | /* Query records by {MAC, VID/FID} value */ | |
264 | MLXSW_REG_SFD_OP_QUERY_QUERY = 1, | |
265 | /* Query and clear activity. Query records by {MAC, VID/FID} value */ | |
266 | MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, | |
267 | /* Test. Response indicates if each of the records could be | |
268 | * added to the FDB. | |
269 | */ | |
270 | MLXSW_REG_SFD_OP_WRITE_TEST = 0, | |
271 | /* Add/modify. Aged-out records cannot be added. This command removes | |
272 | * the learning notification of the {MAC, VID/FID}. Response includes | |
273 | * the entries that were added to the FDB. | |
274 | */ | |
275 | MLXSW_REG_SFD_OP_WRITE_EDIT = 1, | |
276 | /* Remove record by {MAC, VID/FID}. This command also removes | |
277 | * the learning notification and aged-out notifications | |
278 | * of the {MAC, VID/FID}. The response provides current (pre-removal) | |
279 | * entries as non-aged-out. | |
280 | */ | |
281 | MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, | |
282 | /* Remove learned notification by {MAC, VID/FID}. The response provides | |
283 | * the removed learning notification. | |
284 | */ | |
285 | MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, | |
286 | }; | |
287 | ||
288 | /* reg_sfd_op | |
289 | * Operation. | |
290 | * Access: OP | |
291 | */ | |
292 | MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); | |
293 | ||
294 | /* reg_sfd_record_locator | |
295 | * Used for querying the FDB. Use record_locator=0 to initiate the | |
296 | * query. When a record is returned, a new record_locator is | |
297 | * returned to be used in the subsequent query. | |
298 | * Reserved for database update. | |
299 | * Access: Index | |
300 | */ | |
301 | MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); | |
302 | ||
303 | /* reg_sfd_num_rec | |
304 | * Request: Number of records to read/add/modify/remove | |
305 | * Response: Number of records read/added/replaced/removed | |
306 | * See above description for more details. | |
307 | * Ranges 0..64 | |
308 | * Access: RW | |
309 | */ | |
310 | MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); | |
311 | ||
312 | static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, | |
313 | u32 record_locator) | |
314 | { | |
315 | MLXSW_REG_ZERO(sfd, payload); | |
316 | mlxsw_reg_sfd_op_set(payload, op); | |
317 | mlxsw_reg_sfd_record_locator_set(payload, record_locator); | |
318 | } | |
319 | ||
320 | /* reg_sfd_rec_swid | |
321 | * Switch partition ID. | |
322 | * Access: Index | |
323 | */ | |
324 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, | |
325 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
326 | ||
327 | enum mlxsw_reg_sfd_rec_type { | |
328 | MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, | |
e4bfbae2 | 329 | MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, |
5230b25f | 330 | MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, |
236033b3 JP |
331 | }; |
332 | ||
333 | /* reg_sfd_rec_type | |
334 | * FDB record type. | |
335 | * Access: RW | |
336 | */ | |
337 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, | |
338 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
339 | ||
340 | enum mlxsw_reg_sfd_rec_policy { | |
341 | /* Replacement disabled, aging disabled. */ | |
342 | MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, | |
343 | /* (mlag remote): Replacement enabled, aging disabled, | |
344 | * learning notification enabled on this port. | |
345 | */ | |
346 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, | |
347 | /* (ingress device): Replacement enabled, aging enabled. */ | |
348 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, | |
349 | }; | |
350 | ||
351 | /* reg_sfd_rec_policy | |
352 | * Policy. | |
353 | * Access: RW | |
354 | */ | |
355 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, | |
356 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
357 | ||
358 | /* reg_sfd_rec_a | |
359 | * Activity. Set for new static entries. Set for static entries if a frame SMAC | |
360 | * lookup hits on the entry. | |
361 | * To clear the a bit, use "query and clear activity" op. | |
362 | * Access: RO | |
363 | */ | |
364 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, | |
365 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
366 | ||
367 | /* reg_sfd_rec_mac | |
368 | * MAC address. | |
369 | * Access: Index | |
370 | */ | |
371 | MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, | |
372 | MLXSW_REG_SFD_REC_LEN, 0x02); | |
373 | ||
374 | enum mlxsw_reg_sfd_rec_action { | |
375 | /* forward */ | |
376 | MLXSW_REG_SFD_REC_ACTION_NOP = 0, | |
377 | /* forward and trap, trap_id is FDB_TRAP */ | |
378 | MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, | |
379 | /* trap and do not forward, trap_id is FDB_TRAP */ | |
d82d8c06 IS |
380 | MLXSW_REG_SFD_REC_ACTION_TRAP = 2, |
381 | /* forward to IP router */ | |
382 | MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, | |
236033b3 JP |
383 | MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, |
384 | }; | |
385 | ||
386 | /* reg_sfd_rec_action | |
387 | * Action to apply on the packet. | |
388 | * Note: Dynamic entries can only be configured with NOP action. | |
389 | * Access: RW | |
390 | */ | |
391 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, | |
392 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
393 | ||
394 | /* reg_sfd_uc_sub_port | |
4e9ec083 JP |
395 | * VEPA channel on local port. |
396 | * Valid only if local port is a non-stacking port. Must be 0 if multichannel | |
397 | * VEPA is not enabled. | |
236033b3 JP |
398 | * Access: RW |
399 | */ | |
400 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, | |
401 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
402 | ||
403 | /* reg_sfd_uc_fid_vid | |
404 | * Filtering ID or VLAN ID | |
405 | * For SwitchX and SwitchX-2: | |
406 | * - Dynamic entries (policy 2,3) use FID | |
407 | * - Static entries (policy 0) use VID | |
408 | * - When independent learning is configured, VID=FID | |
409 | * For Spectrum: use FID for both Dynamic and Static entries. | |
410 | * VID should not be used. | |
411 | * Access: Index | |
412 | */ | |
413 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
414 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
415 | ||
416 | /* reg_sfd_uc_system_port | |
417 | * Unique port identifier for the final destination of the packet. | |
418 | * Access: RW | |
419 | */ | |
420 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
421 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
422 | ||
e4bfbae2 JP |
423 | static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, |
424 | enum mlxsw_reg_sfd_rec_type rec_type, | |
e4bfbae2 JP |
425 | const char *mac, |
426 | enum mlxsw_reg_sfd_rec_action action) | |
236033b3 JP |
427 | { |
428 | u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); | |
429 | ||
430 | if (rec_index >= num_rec) | |
431 | mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); | |
432 | mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); | |
e4bfbae2 | 433 | mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); |
236033b3 | 434 | mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); |
e4bfbae2 JP |
435 | mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); |
436 | } | |
437 | ||
438 | static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, | |
439 | enum mlxsw_reg_sfd_rec_policy policy, | |
9de6a80e | 440 | const char *mac, u16 fid_vid, |
e4bfbae2 JP |
441 | enum mlxsw_reg_sfd_rec_action action, |
442 | u8 local_port) | |
443 | { | |
444 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
5230b25f ER |
445 | MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); |
446 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
236033b3 | 447 | mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); |
9de6a80e | 448 | mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); |
236033b3 JP |
449 | mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); |
450 | } | |
451 | ||
75c09280 | 452 | static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, |
9de6a80e | 453 | char *mac, u16 *p_fid_vid, |
75c09280 | 454 | u8 *p_local_port) |
236033b3 JP |
455 | { |
456 | mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); | |
9de6a80e | 457 | *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); |
236033b3 JP |
458 | *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); |
459 | } | |
460 | ||
e4bfbae2 JP |
461 | /* reg_sfd_uc_lag_sub_port |
462 | * LAG sub port. | |
463 | * Must be 0 if multichannel VEPA is not enabled. | |
464 | * Access: RW | |
465 | */ | |
466 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, | |
467 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
468 | ||
469 | /* reg_sfd_uc_lag_fid_vid | |
470 | * Filtering ID or VLAN ID | |
471 | * For SwitchX and SwitchX-2: | |
472 | * - Dynamic entries (policy 2,3) use FID | |
473 | * - Static entries (policy 0) use VID | |
474 | * - When independent learning is configured, VID=FID | |
475 | * For Spectrum: use FID for both Dynamic and Static entries. | |
476 | * VID should not be used. | |
477 | * Access: Index | |
478 | */ | |
479 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
480 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
481 | ||
afd7f979 IS |
482 | /* reg_sfd_uc_lag_lag_vid |
483 | * Indicates VID in case of vFIDs. Reserved for FIDs. | |
484 | * Access: RW | |
485 | */ | |
486 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, | |
487 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
488 | ||
e4bfbae2 JP |
489 | /* reg_sfd_uc_lag_lag_id |
490 | * LAG Identifier - pointer into the LAG descriptor table. | |
491 | * Access: RW | |
492 | */ | |
493 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, | |
494 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
495 | ||
496 | static inline void | |
497 | mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, | |
498 | enum mlxsw_reg_sfd_rec_policy policy, | |
9de6a80e | 499 | const char *mac, u16 fid_vid, |
afd7f979 | 500 | enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, |
e4bfbae2 JP |
501 | u16 lag_id) |
502 | { | |
503 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
504 | MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, | |
5230b25f ER |
505 | mac, action); |
506 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
e4bfbae2 | 507 | mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); |
9de6a80e | 508 | mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); |
afd7f979 | 509 | mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); |
e4bfbae2 JP |
510 | mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); |
511 | } | |
512 | ||
513 | static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, | |
514 | char *mac, u16 *p_vid, | |
515 | u16 *p_lag_id) | |
516 | { | |
517 | mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); | |
518 | *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); | |
519 | *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); | |
520 | } | |
521 | ||
5230b25f ER |
522 | /* reg_sfd_mc_pgi |
523 | * | |
524 | * Multicast port group index - index into the port group table. | |
525 | * Value 0x1FFF indicates the pgi should point to the MID entry. | |
526 | * For Spectrum this value must be set to 0x1FFF | |
527 | * Access: RW | |
528 | */ | |
529 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, | |
530 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
531 | ||
532 | /* reg_sfd_mc_fid_vid | |
533 | * | |
534 | * Filtering ID or VLAN ID | |
535 | * Access: Index | |
536 | */ | |
537 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
538 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
539 | ||
540 | /* reg_sfd_mc_mid | |
541 | * | |
542 | * Multicast identifier - global identifier that represents the multicast | |
543 | * group across all devices. | |
544 | * Access: RW | |
545 | */ | |
546 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
547 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
548 | ||
549 | static inline void | |
550 | mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, | |
551 | const char *mac, u16 fid_vid, | |
552 | enum mlxsw_reg_sfd_rec_action action, u16 mid) | |
553 | { | |
554 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
555 | MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); | |
556 | mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); | |
557 | mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); | |
558 | mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); | |
559 | } | |
560 | ||
f5d88f58 JP |
561 | /* SFN - Switch FDB Notification Register |
562 | * ------------------------------------------- | |
563 | * The switch provides notifications on newly learned FDB entries and | |
564 | * aged out entries. The notifications can be polled by software. | |
565 | */ | |
566 | #define MLXSW_REG_SFN_ID 0x200B | |
567 | #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ | |
568 | #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ | |
569 | #define MLXSW_REG_SFN_REC_MAX_COUNT 64 | |
570 | #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ | |
571 | MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) | |
572 | ||
21978dcf | 573 | MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); |
f5d88f58 JP |
574 | |
575 | /* reg_sfn_swid | |
576 | * Switch partition ID. | |
577 | * Access: Index | |
578 | */ | |
579 | MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); | |
580 | ||
1803e0fb IS |
581 | /* reg_sfn_end |
582 | * Forces the current session to end. | |
583 | * Access: OP | |
584 | */ | |
585 | MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); | |
586 | ||
f5d88f58 JP |
587 | /* reg_sfn_num_rec |
588 | * Request: Number of learned notifications and aged-out notification | |
589 | * records requested. | |
590 | * Response: Number of notification records returned (must be smaller | |
591 | * than or equal to the value requested) | |
592 | * Ranges 0..64 | |
593 | * Access: OP | |
594 | */ | |
595 | MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); | |
596 | ||
597 | static inline void mlxsw_reg_sfn_pack(char *payload) | |
598 | { | |
599 | MLXSW_REG_ZERO(sfn, payload); | |
600 | mlxsw_reg_sfn_swid_set(payload, 0); | |
1803e0fb | 601 | mlxsw_reg_sfn_end_set(payload, 1); |
f5d88f58 JP |
602 | mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); |
603 | } | |
604 | ||
605 | /* reg_sfn_rec_swid | |
606 | * Switch partition ID. | |
607 | * Access: RO | |
608 | */ | |
609 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, | |
610 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
611 | ||
612 | enum mlxsw_reg_sfn_rec_type { | |
613 | /* MAC addresses learned on a regular port. */ | |
614 | MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, | |
3b71571c JP |
615 | /* MAC addresses learned on a LAG port. */ |
616 | MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, | |
617 | /* Aged-out MAC address on a regular port. */ | |
f5d88f58 | 618 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, |
3b71571c JP |
619 | /* Aged-out MAC address on a LAG port. */ |
620 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, | |
f5d88f58 JP |
621 | }; |
622 | ||
623 | /* reg_sfn_rec_type | |
624 | * Notification record type. | |
625 | * Access: RO | |
626 | */ | |
627 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, | |
628 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
629 | ||
630 | /* reg_sfn_rec_mac | |
631 | * MAC address. | |
632 | * Access: RO | |
633 | */ | |
634 | MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, | |
635 | MLXSW_REG_SFN_REC_LEN, 0x02); | |
636 | ||
8316f087 | 637 | /* reg_sfn_mac_sub_port |
f5d88f58 JP |
638 | * VEPA channel on the local port. |
639 | * 0 if multichannel VEPA is not enabled. | |
640 | * Access: RO | |
641 | */ | |
642 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, | |
643 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
644 | ||
8316f087 | 645 | /* reg_sfn_mac_fid |
f5d88f58 JP |
646 | * Filtering identifier. |
647 | * Access: RO | |
648 | */ | |
649 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
650 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
651 | ||
8316f087 | 652 | /* reg_sfn_mac_system_port |
f5d88f58 JP |
653 | * Unique port identifier for the final destination of the packet. |
654 | * Access: RO | |
655 | */ | |
656 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
657 | MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
658 | ||
659 | static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, | |
660 | char *mac, u16 *p_vid, | |
661 | u8 *p_local_port) | |
662 | { | |
663 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
664 | *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
665 | *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); | |
666 | } | |
667 | ||
3b71571c JP |
668 | /* reg_sfn_mac_lag_lag_id |
669 | * LAG ID (pointer into the LAG descriptor table). | |
670 | * Access: RO | |
671 | */ | |
672 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, | |
673 | MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
674 | ||
675 | static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, | |
676 | char *mac, u16 *p_vid, | |
677 | u16 *p_lag_id) | |
678 | { | |
679 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
680 | *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
681 | *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); | |
682 | } | |
683 | ||
4ec14b76 IS |
684 | /* SPMS - Switch Port MSTP/RSTP State Register |
685 | * ------------------------------------------- | |
686 | * Configures the spanning tree state of a physical port. | |
687 | */ | |
3f0effd1 | 688 | #define MLXSW_REG_SPMS_ID 0x200D |
4ec14b76 IS |
689 | #define MLXSW_REG_SPMS_LEN 0x404 |
690 | ||
21978dcf | 691 | MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); |
4ec14b76 IS |
692 | |
693 | /* reg_spms_local_port | |
694 | * Local port number. | |
695 | * Access: Index | |
696 | */ | |
697 | MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); | |
698 | ||
699 | enum mlxsw_reg_spms_state { | |
700 | MLXSW_REG_SPMS_STATE_NO_CHANGE, | |
701 | MLXSW_REG_SPMS_STATE_DISCARDING, | |
702 | MLXSW_REG_SPMS_STATE_LEARNING, | |
703 | MLXSW_REG_SPMS_STATE_FORWARDING, | |
704 | }; | |
705 | ||
706 | /* reg_spms_state | |
707 | * Spanning tree state of each VLAN ID (VID) of the local port. | |
708 | * 0 - Do not change spanning tree state (used only when writing). | |
709 | * 1 - Discarding. No learning or forwarding to/from this port (default). | |
710 | * 2 - Learning. Port is learning, but not forwarding. | |
711 | * 3 - Forwarding. Port is learning and forwarding. | |
712 | * Access: RW | |
713 | */ | |
714 | MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); | |
715 | ||
ebb7963f | 716 | static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) |
4ec14b76 IS |
717 | { |
718 | MLXSW_REG_ZERO(spms, payload); | |
719 | mlxsw_reg_spms_local_port_set(payload, local_port); | |
ebb7963f JP |
720 | } |
721 | ||
722 | static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, | |
723 | enum mlxsw_reg_spms_state state) | |
724 | { | |
4ec14b76 IS |
725 | mlxsw_reg_spms_state_set(payload, vid, state); |
726 | } | |
727 | ||
b2e345f9 ER |
728 | /* SPVID - Switch Port VID |
729 | * ----------------------- | |
730 | * The switch port VID configures the default VID for a port. | |
731 | */ | |
732 | #define MLXSW_REG_SPVID_ID 0x200E | |
733 | #define MLXSW_REG_SPVID_LEN 0x08 | |
734 | ||
21978dcf | 735 | MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); |
b2e345f9 ER |
736 | |
737 | /* reg_spvid_local_port | |
738 | * Local port number. | |
739 | * Access: Index | |
740 | */ | |
741 | MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); | |
742 | ||
743 | /* reg_spvid_sub_port | |
744 | * Virtual port within the physical port. | |
745 | * Should be set to 0 when virtual ports are not enabled on the port. | |
746 | * Access: Index | |
747 | */ | |
748 | MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); | |
749 | ||
750 | /* reg_spvid_pvid | |
751 | * Port default VID | |
752 | * Access: RW | |
753 | */ | |
754 | MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); | |
755 | ||
756 | static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) | |
757 | { | |
758 | MLXSW_REG_ZERO(spvid, payload); | |
759 | mlxsw_reg_spvid_local_port_set(payload, local_port); | |
760 | mlxsw_reg_spvid_pvid_set(payload, pvid); | |
761 | } | |
762 | ||
763 | /* SPVM - Switch Port VLAN Membership | |
764 | * ---------------------------------- | |
765 | * The Switch Port VLAN Membership register configures the VLAN membership | |
766 | * of a port in a VLAN denoted by VID. VLAN membership is managed per | |
767 | * virtual port. The register can be used to add and remove VID(s) from a port. | |
768 | */ | |
769 | #define MLXSW_REG_SPVM_ID 0x200F | |
770 | #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ | |
771 | #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ | |
772 | #define MLXSW_REG_SPVM_REC_MAX_COUNT 256 | |
773 | #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ | |
774 | MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) | |
775 | ||
21978dcf | 776 | MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); |
b2e345f9 ER |
777 | |
778 | /* reg_spvm_pt | |
779 | * Priority tagged. If this bit is set, packets forwarded to the port with | |
780 | * untagged VLAN membership (u bit is set) will be tagged with priority tag | |
781 | * (VID=0) | |
782 | * Access: RW | |
783 | */ | |
784 | MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); | |
785 | ||
786 | /* reg_spvm_pte | |
787 | * Priority Tagged Update Enable. On Write operations, if this bit is cleared, | |
788 | * the pt bit will NOT be updated. To update the pt bit, pte must be set. | |
789 | * Access: WO | |
790 | */ | |
791 | MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); | |
792 | ||
793 | /* reg_spvm_local_port | |
794 | * Local port number. | |
795 | * Access: Index | |
796 | */ | |
797 | MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); | |
798 | ||
799 | /* reg_spvm_sub_port | |
800 | * Virtual port within the physical port. | |
801 | * Should be set to 0 when virtual ports are not enabled on the port. | |
802 | * Access: Index | |
803 | */ | |
804 | MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); | |
805 | ||
806 | /* reg_spvm_num_rec | |
807 | * Number of records to update. Each record contains: i, e, u, vid. | |
808 | * Access: OP | |
809 | */ | |
810 | MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); | |
811 | ||
812 | /* reg_spvm_rec_i | |
813 | * Ingress membership in VLAN ID. | |
814 | * Access: Index | |
815 | */ | |
816 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, | |
817 | MLXSW_REG_SPVM_BASE_LEN, 14, 1, | |
818 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
819 | ||
820 | /* reg_spvm_rec_e | |
821 | * Egress membership in VLAN ID. | |
822 | * Access: Index | |
823 | */ | |
824 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, | |
825 | MLXSW_REG_SPVM_BASE_LEN, 13, 1, | |
826 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
827 | ||
828 | /* reg_spvm_rec_u | |
829 | * Untagged - port is an untagged member - egress transmission uses untagged | |
830 | * frames on VID<n> | |
831 | * Access: Index | |
832 | */ | |
833 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, | |
834 | MLXSW_REG_SPVM_BASE_LEN, 12, 1, | |
835 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
836 | ||
837 | /* reg_spvm_rec_vid | |
838 | * Egress membership in VLAN ID. | |
839 | * Access: Index | |
840 | */ | |
841 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, | |
842 | MLXSW_REG_SPVM_BASE_LEN, 0, 12, | |
843 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
844 | ||
845 | static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, | |
846 | u16 vid_begin, u16 vid_end, | |
847 | bool is_member, bool untagged) | |
848 | { | |
849 | int size = vid_end - vid_begin + 1; | |
850 | int i; | |
851 | ||
852 | MLXSW_REG_ZERO(spvm, payload); | |
853 | mlxsw_reg_spvm_local_port_set(payload, local_port); | |
854 | mlxsw_reg_spvm_num_rec_set(payload, size); | |
855 | ||
856 | for (i = 0; i < size; i++) { | |
857 | mlxsw_reg_spvm_rec_i_set(payload, i, is_member); | |
858 | mlxsw_reg_spvm_rec_e_set(payload, i, is_member); | |
859 | mlxsw_reg_spvm_rec_u_set(payload, i, untagged); | |
860 | mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); | |
861 | } | |
862 | } | |
863 | ||
148f472d IS |
864 | /* SPAFT - Switch Port Acceptable Frame Types |
865 | * ------------------------------------------ | |
866 | * The Switch Port Acceptable Frame Types register configures the frame | |
867 | * admittance of the port. | |
868 | */ | |
869 | #define MLXSW_REG_SPAFT_ID 0x2010 | |
870 | #define MLXSW_REG_SPAFT_LEN 0x08 | |
871 | ||
21978dcf | 872 | MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); |
148f472d IS |
873 | |
874 | /* reg_spaft_local_port | |
875 | * Local port number. | |
876 | * Access: Index | |
877 | * | |
878 | * Note: CPU port is not supported (all tag types are allowed). | |
879 | */ | |
880 | MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); | |
881 | ||
882 | /* reg_spaft_sub_port | |
883 | * Virtual port within the physical port. | |
884 | * Should be set to 0 when virtual ports are not enabled on the port. | |
885 | * Access: RW | |
886 | */ | |
887 | MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); | |
888 | ||
889 | /* reg_spaft_allow_untagged | |
890 | * When set, untagged frames on the ingress are allowed (default). | |
891 | * Access: RW | |
892 | */ | |
893 | MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); | |
894 | ||
895 | /* reg_spaft_allow_prio_tagged | |
896 | * When set, priority tagged frames on the ingress are allowed (default). | |
897 | * Access: RW | |
898 | */ | |
899 | MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); | |
900 | ||
901 | /* reg_spaft_allow_tagged | |
902 | * When set, tagged frames on the ingress are allowed (default). | |
903 | * Access: RW | |
904 | */ | |
905 | MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); | |
906 | ||
907 | static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, | |
908 | bool allow_untagged) | |
909 | { | |
910 | MLXSW_REG_ZERO(spaft, payload); | |
911 | mlxsw_reg_spaft_local_port_set(payload, local_port); | |
912 | mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); | |
913 | mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); | |
914 | mlxsw_reg_spaft_allow_tagged_set(payload, true); | |
915 | } | |
916 | ||
4ec14b76 IS |
917 | /* SFGC - Switch Flooding Group Configuration |
918 | * ------------------------------------------ | |
919 | * The following register controls the association of flooding tables and MIDs | |
920 | * to packet types used for flooding. | |
921 | */ | |
36b78e8a | 922 | #define MLXSW_REG_SFGC_ID 0x2011 |
4ec14b76 IS |
923 | #define MLXSW_REG_SFGC_LEN 0x10 |
924 | ||
21978dcf | 925 | MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); |
4ec14b76 IS |
926 | |
927 | enum mlxsw_reg_sfgc_type { | |
fa6ad058 IS |
928 | MLXSW_REG_SFGC_TYPE_BROADCAST, |
929 | MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, | |
930 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, | |
931 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, | |
932 | MLXSW_REG_SFGC_TYPE_RESERVED, | |
933 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, | |
934 | MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, | |
935 | MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, | |
936 | MLXSW_REG_SFGC_TYPE_MAX, | |
4ec14b76 IS |
937 | }; |
938 | ||
939 | /* reg_sfgc_type | |
940 | * The traffic type to reach the flooding table. | |
941 | * Access: Index | |
942 | */ | |
943 | MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); | |
944 | ||
945 | enum mlxsw_reg_sfgc_bridge_type { | |
946 | MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, | |
947 | MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, | |
948 | }; | |
949 | ||
950 | /* reg_sfgc_bridge_type | |
951 | * Access: Index | |
952 | * | |
953 | * Note: SwitchX-2 only supports 802.1Q mode. | |
954 | */ | |
955 | MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); | |
956 | ||
957 | enum mlxsw_flood_table_type { | |
958 | MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, | |
959 | MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, | |
960 | MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, | |
961 | MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3, | |
962 | MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, | |
963 | }; | |
964 | ||
965 | /* reg_sfgc_table_type | |
966 | * See mlxsw_flood_table_type | |
967 | * Access: RW | |
968 | * | |
969 | * Note: FID offset and FID types are not supported in SwitchX-2. | |
970 | */ | |
971 | MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); | |
972 | ||
973 | /* reg_sfgc_flood_table | |
974 | * Flooding table index to associate with the specific type on the specific | |
975 | * switch partition. | |
976 | * Access: RW | |
977 | */ | |
978 | MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); | |
979 | ||
980 | /* reg_sfgc_mid | |
981 | * The multicast ID for the swid. Not supported for Spectrum | |
982 | * Access: RW | |
983 | */ | |
984 | MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); | |
985 | ||
986 | /* reg_sfgc_counter_set_type | |
987 | * Counter Set Type for flow counters. | |
988 | * Access: RW | |
989 | */ | |
990 | MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); | |
991 | ||
992 | /* reg_sfgc_counter_index | |
993 | * Counter Index for flow counters. | |
994 | * Access: RW | |
995 | */ | |
996 | MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); | |
997 | ||
998 | static inline void | |
999 | mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, | |
1000 | enum mlxsw_reg_sfgc_bridge_type bridge_type, | |
1001 | enum mlxsw_flood_table_type table_type, | |
1002 | unsigned int flood_table) | |
1003 | { | |
1004 | MLXSW_REG_ZERO(sfgc, payload); | |
1005 | mlxsw_reg_sfgc_type_set(payload, type); | |
1006 | mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); | |
1007 | mlxsw_reg_sfgc_table_type_set(payload, table_type); | |
1008 | mlxsw_reg_sfgc_flood_table_set(payload, flood_table); | |
1009 | mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); | |
1010 | } | |
1011 | ||
1012 | /* SFTR - Switch Flooding Table Register | |
1013 | * ------------------------------------- | |
1014 | * The switch flooding table is used for flooding packet replication. The table | |
1015 | * defines a bit mask of ports for packet replication. | |
1016 | */ | |
1017 | #define MLXSW_REG_SFTR_ID 0x2012 | |
1018 | #define MLXSW_REG_SFTR_LEN 0x420 | |
1019 | ||
21978dcf | 1020 | MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); |
4ec14b76 IS |
1021 | |
1022 | /* reg_sftr_swid | |
1023 | * Switch partition ID with which to associate the port. | |
1024 | * Access: Index | |
1025 | */ | |
1026 | MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); | |
1027 | ||
1028 | /* reg_sftr_flood_table | |
1029 | * Flooding table index to associate with the specific type on the specific | |
1030 | * switch partition. | |
1031 | * Access: Index | |
1032 | */ | |
1033 | MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); | |
1034 | ||
1035 | /* reg_sftr_index | |
1036 | * Index. Used as an index into the Flooding Table in case the table is | |
1037 | * configured to use VID / FID or FID Offset. | |
1038 | * Access: Index | |
1039 | */ | |
1040 | MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); | |
1041 | ||
1042 | /* reg_sftr_table_type | |
1043 | * See mlxsw_flood_table_type | |
1044 | * Access: RW | |
1045 | */ | |
1046 | MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); | |
1047 | ||
1048 | /* reg_sftr_range | |
1049 | * Range of entries to update | |
1050 | * Access: Index | |
1051 | */ | |
1052 | MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); | |
1053 | ||
1054 | /* reg_sftr_port | |
1055 | * Local port membership (1 bit per port). | |
1056 | * Access: RW | |
1057 | */ | |
1058 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); | |
1059 | ||
1060 | /* reg_sftr_cpu_port_mask | |
1061 | * CPU port mask (1 bit per port). | |
1062 | * Access: W | |
1063 | */ | |
1064 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); | |
1065 | ||
1066 | static inline void mlxsw_reg_sftr_pack(char *payload, | |
1067 | unsigned int flood_table, | |
1068 | unsigned int index, | |
1069 | enum mlxsw_flood_table_type table_type, | |
bc2055f8 | 1070 | unsigned int range, u8 port, bool set) |
4ec14b76 IS |
1071 | { |
1072 | MLXSW_REG_ZERO(sftr, payload); | |
1073 | mlxsw_reg_sftr_swid_set(payload, 0); | |
1074 | mlxsw_reg_sftr_flood_table_set(payload, flood_table); | |
1075 | mlxsw_reg_sftr_index_set(payload, index); | |
1076 | mlxsw_reg_sftr_table_type_set(payload, table_type); | |
1077 | mlxsw_reg_sftr_range_set(payload, range); | |
bc2055f8 IS |
1078 | mlxsw_reg_sftr_port_set(payload, port, set); |
1079 | mlxsw_reg_sftr_port_mask_set(payload, port, 1); | |
4ec14b76 IS |
1080 | } |
1081 | ||
41933271 IS |
1082 | /* SFDF - Switch Filtering DB Flush |
1083 | * -------------------------------- | |
1084 | * The switch filtering DB flush register is used to flush the FDB. | |
1085 | * Note that FDB notifications are flushed as well. | |
1086 | */ | |
1087 | #define MLXSW_REG_SFDF_ID 0x2013 | |
1088 | #define MLXSW_REG_SFDF_LEN 0x14 | |
1089 | ||
21978dcf | 1090 | MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); |
41933271 IS |
1091 | |
1092 | /* reg_sfdf_swid | |
1093 | * Switch partition ID. | |
1094 | * Access: Index | |
1095 | */ | |
1096 | MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); | |
1097 | ||
1098 | enum mlxsw_reg_sfdf_flush_type { | |
1099 | MLXSW_REG_SFDF_FLUSH_PER_SWID, | |
1100 | MLXSW_REG_SFDF_FLUSH_PER_FID, | |
1101 | MLXSW_REG_SFDF_FLUSH_PER_PORT, | |
1102 | MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, | |
1103 | MLXSW_REG_SFDF_FLUSH_PER_LAG, | |
1104 | MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, | |
1105 | }; | |
1106 | ||
1107 | /* reg_sfdf_flush_type | |
1108 | * Flush type. | |
1109 | * 0 - All SWID dynamic entries are flushed. | |
1110 | * 1 - All FID dynamic entries are flushed. | |
1111 | * 2 - All dynamic entries pointing to port are flushed. | |
1112 | * 3 - All FID dynamic entries pointing to port are flushed. | |
1113 | * 4 - All dynamic entries pointing to LAG are flushed. | |
1114 | * 5 - All FID dynamic entries pointing to LAG are flushed. | |
1115 | * Access: RW | |
1116 | */ | |
1117 | MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); | |
1118 | ||
1119 | /* reg_sfdf_flush_static | |
1120 | * Static. | |
1121 | * 0 - Flush only dynamic entries. | |
1122 | * 1 - Flush both dynamic and static entries. | |
1123 | * Access: RW | |
1124 | */ | |
1125 | MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); | |
1126 | ||
1127 | static inline void mlxsw_reg_sfdf_pack(char *payload, | |
1128 | enum mlxsw_reg_sfdf_flush_type type) | |
1129 | { | |
1130 | MLXSW_REG_ZERO(sfdf, payload); | |
1131 | mlxsw_reg_sfdf_flush_type_set(payload, type); | |
1132 | mlxsw_reg_sfdf_flush_static_set(payload, true); | |
1133 | } | |
1134 | ||
1135 | /* reg_sfdf_fid | |
1136 | * FID to flush. | |
1137 | * Access: RW | |
1138 | */ | |
1139 | MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); | |
1140 | ||
1141 | /* reg_sfdf_system_port | |
1142 | * Port to flush. | |
1143 | * Access: RW | |
1144 | */ | |
1145 | MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); | |
1146 | ||
1147 | /* reg_sfdf_port_fid_system_port | |
1148 | * Port to flush, pointed to by FID. | |
1149 | * Access: RW | |
1150 | */ | |
1151 | MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); | |
1152 | ||
1153 | /* reg_sfdf_lag_id | |
1154 | * LAG ID to flush. | |
1155 | * Access: RW | |
1156 | */ | |
1157 | MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); | |
1158 | ||
1159 | /* reg_sfdf_lag_fid_lag_id | |
1160 | * LAG ID to flush, pointed to by FID. | |
1161 | * Access: RW | |
1162 | */ | |
1163 | MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); | |
1164 | ||
d1d40be0 JP |
1165 | /* SLDR - Switch LAG Descriptor Register |
1166 | * ----------------------------------------- | |
1167 | * The switch LAG descriptor register is populated by LAG descriptors. | |
1168 | * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to | |
1169 | * max_lag-1. | |
1170 | */ | |
1171 | #define MLXSW_REG_SLDR_ID 0x2014 | |
1172 | #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ | |
1173 | ||
21978dcf | 1174 | MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); |
d1d40be0 JP |
1175 | |
1176 | enum mlxsw_reg_sldr_op { | |
1177 | /* Indicates a creation of a new LAG-ID, lag_id must be valid */ | |
1178 | MLXSW_REG_SLDR_OP_LAG_CREATE, | |
1179 | MLXSW_REG_SLDR_OP_LAG_DESTROY, | |
1180 | /* Ports that appear in the list have the Distributor enabled */ | |
1181 | MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, | |
1182 | /* Removes ports from the disributor list */ | |
1183 | MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, | |
1184 | }; | |
1185 | ||
1186 | /* reg_sldr_op | |
1187 | * Operation. | |
1188 | * Access: RW | |
1189 | */ | |
1190 | MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); | |
1191 | ||
1192 | /* reg_sldr_lag_id | |
1193 | * LAG identifier. The lag_id is the index into the LAG descriptor table. | |
1194 | * Access: Index | |
1195 | */ | |
1196 | MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); | |
1197 | ||
1198 | static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) | |
1199 | { | |
1200 | MLXSW_REG_ZERO(sldr, payload); | |
1201 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); | |
1202 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1203 | } | |
1204 | ||
1205 | static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) | |
1206 | { | |
1207 | MLXSW_REG_ZERO(sldr, payload); | |
1208 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); | |
1209 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1210 | } | |
1211 | ||
1212 | /* reg_sldr_num_ports | |
1213 | * The number of member ports of the LAG. | |
1214 | * Reserved for Create / Destroy operations | |
1215 | * For Add / Remove operations - indicates the number of ports in the list. | |
1216 | * Access: RW | |
1217 | */ | |
1218 | MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); | |
1219 | ||
1220 | /* reg_sldr_system_port | |
1221 | * System port. | |
1222 | * Access: RW | |
1223 | */ | |
1224 | MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); | |
1225 | ||
1226 | static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, | |
1227 | u8 local_port) | |
1228 | { | |
1229 | MLXSW_REG_ZERO(sldr, payload); | |
1230 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); | |
1231 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1232 | mlxsw_reg_sldr_num_ports_set(payload, 1); | |
1233 | mlxsw_reg_sldr_system_port_set(payload, 0, local_port); | |
1234 | } | |
1235 | ||
1236 | static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, | |
1237 | u8 local_port) | |
1238 | { | |
1239 | MLXSW_REG_ZERO(sldr, payload); | |
1240 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); | |
1241 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1242 | mlxsw_reg_sldr_num_ports_set(payload, 1); | |
1243 | mlxsw_reg_sldr_system_port_set(payload, 0, local_port); | |
1244 | } | |
1245 | ||
1246 | /* SLCR - Switch LAG Configuration 2 Register | |
1247 | * ------------------------------------------- | |
1248 | * The Switch LAG Configuration register is used for configuring the | |
1249 | * LAG properties of the switch. | |
1250 | */ | |
1251 | #define MLXSW_REG_SLCR_ID 0x2015 | |
1252 | #define MLXSW_REG_SLCR_LEN 0x10 | |
1253 | ||
21978dcf | 1254 | MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); |
d1d40be0 JP |
1255 | |
1256 | enum mlxsw_reg_slcr_pp { | |
1257 | /* Global Configuration (for all ports) */ | |
1258 | MLXSW_REG_SLCR_PP_GLOBAL, | |
1259 | /* Per port configuration, based on local_port field */ | |
1260 | MLXSW_REG_SLCR_PP_PER_PORT, | |
1261 | }; | |
1262 | ||
1263 | /* reg_slcr_pp | |
1264 | * Per Port Configuration | |
1265 | * Note: Reading at Global mode results in reading port 1 configuration. | |
1266 | * Access: Index | |
1267 | */ | |
1268 | MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); | |
1269 | ||
1270 | /* reg_slcr_local_port | |
1271 | * Local port number | |
1272 | * Supported from CPU port | |
1273 | * Not supported from router port | |
1274 | * Reserved when pp = Global Configuration | |
1275 | * Access: Index | |
1276 | */ | |
1277 | MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); | |
1278 | ||
1279 | enum mlxsw_reg_slcr_type { | |
1280 | MLXSW_REG_SLCR_TYPE_CRC, /* default */ | |
1281 | MLXSW_REG_SLCR_TYPE_XOR, | |
1282 | MLXSW_REG_SLCR_TYPE_RANDOM, | |
1283 | }; | |
1284 | ||
1285 | /* reg_slcr_type | |
1286 | * Hash type | |
1287 | * Access: RW | |
1288 | */ | |
1289 | MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); | |
1290 | ||
1291 | /* Ingress port */ | |
1292 | #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) | |
1293 | /* SMAC - for IPv4 and IPv6 packets */ | |
1294 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) | |
1295 | /* SMAC - for non-IP packets */ | |
1296 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) | |
1297 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ | |
1298 | (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ | |
1299 | MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) | |
1300 | /* DMAC - for IPv4 and IPv6 packets */ | |
1301 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) | |
1302 | /* DMAC - for non-IP packets */ | |
1303 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) | |
1304 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ | |
1305 | (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ | |
1306 | MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) | |
1307 | /* Ethertype - for IPv4 and IPv6 packets */ | |
1308 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) | |
1309 | /* Ethertype - for non-IP packets */ | |
1310 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) | |
1311 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ | |
1312 | (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ | |
1313 | MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) | |
1314 | /* VLAN ID - for IPv4 and IPv6 packets */ | |
1315 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) | |
1316 | /* VLAN ID - for non-IP packets */ | |
1317 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) | |
1318 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ | |
1319 | (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ | |
1320 | MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) | |
1321 | /* Source IP address (can be IPv4 or IPv6) */ | |
1322 | #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) | |
1323 | /* Destination IP address (can be IPv4 or IPv6) */ | |
1324 | #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) | |
1325 | /* TCP/UDP source port */ | |
1326 | #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) | |
1327 | /* TCP/UDP destination port*/ | |
1328 | #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) | |
1329 | /* IPv4 Protocol/IPv6 Next Header */ | |
1330 | #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) | |
1331 | /* IPv6 Flow label */ | |
1332 | #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) | |
1333 | /* SID - FCoE source ID */ | |
1334 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) | |
1335 | /* DID - FCoE destination ID */ | |
1336 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) | |
1337 | /* OXID - FCoE originator exchange ID */ | |
1338 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) | |
1339 | /* Destination QP number - for RoCE packets */ | |
1340 | #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) | |
1341 | ||
1342 | /* reg_slcr_lag_hash | |
1343 | * LAG hashing configuration. This is a bitmask, in which each set | |
1344 | * bit includes the corresponding item in the LAG hash calculation. | |
1345 | * The default lag_hash contains SMAC, DMAC, VLANID and | |
1346 | * Ethertype (for all packet types). | |
1347 | * Access: RW | |
1348 | */ | |
1349 | MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); | |
1350 | ||
1351 | static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) | |
1352 | { | |
1353 | MLXSW_REG_ZERO(slcr, payload); | |
1354 | mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); | |
18c2d2c1 | 1355 | mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); |
d1d40be0 JP |
1356 | mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); |
1357 | } | |
1358 | ||
1359 | /* SLCOR - Switch LAG Collector Register | |
1360 | * ------------------------------------- | |
1361 | * The Switch LAG Collector register controls the Local Port membership | |
1362 | * in a LAG and enablement of the collector. | |
1363 | */ | |
1364 | #define MLXSW_REG_SLCOR_ID 0x2016 | |
1365 | #define MLXSW_REG_SLCOR_LEN 0x10 | |
1366 | ||
21978dcf | 1367 | MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); |
d1d40be0 JP |
1368 | |
1369 | enum mlxsw_reg_slcor_col { | |
1370 | /* Port is added with collector disabled */ | |
1371 | MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, | |
1372 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, | |
1373 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, | |
1374 | MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, | |
1375 | }; | |
1376 | ||
1377 | /* reg_slcor_col | |
1378 | * Collector configuration | |
1379 | * Access: RW | |
1380 | */ | |
1381 | MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); | |
1382 | ||
1383 | /* reg_slcor_local_port | |
1384 | * Local port number | |
1385 | * Not supported for CPU port | |
1386 | * Access: Index | |
1387 | */ | |
1388 | MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); | |
1389 | ||
1390 | /* reg_slcor_lag_id | |
1391 | * LAG Identifier. Index into the LAG descriptor table. | |
1392 | * Access: Index | |
1393 | */ | |
1394 | MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); | |
1395 | ||
1396 | /* reg_slcor_port_index | |
1397 | * Port index in the LAG list. Only valid on Add Port to LAG col. | |
1398 | * Valid range is from 0 to cap_max_lag_members-1 | |
1399 | * Access: RW | |
1400 | */ | |
1401 | MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); | |
1402 | ||
1403 | static inline void mlxsw_reg_slcor_pack(char *payload, | |
1404 | u8 local_port, u16 lag_id, | |
1405 | enum mlxsw_reg_slcor_col col) | |
1406 | { | |
1407 | MLXSW_REG_ZERO(slcor, payload); | |
1408 | mlxsw_reg_slcor_col_set(payload, col); | |
1409 | mlxsw_reg_slcor_local_port_set(payload, local_port); | |
1410 | mlxsw_reg_slcor_lag_id_set(payload, lag_id); | |
1411 | } | |
1412 | ||
1413 | static inline void mlxsw_reg_slcor_port_add_pack(char *payload, | |
1414 | u8 local_port, u16 lag_id, | |
1415 | u8 port_index) | |
1416 | { | |
1417 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1418 | MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); | |
1419 | mlxsw_reg_slcor_port_index_set(payload, port_index); | |
1420 | } | |
1421 | ||
1422 | static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, | |
1423 | u8 local_port, u16 lag_id) | |
1424 | { | |
1425 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1426 | MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); | |
1427 | } | |
1428 | ||
1429 | static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, | |
1430 | u8 local_port, u16 lag_id) | |
1431 | { | |
1432 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1433 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); | |
1434 | } | |
1435 | ||
1436 | static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, | |
1437 | u8 local_port, u16 lag_id) | |
1438 | { | |
1439 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1440 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); | |
1441 | } | |
1442 | ||
4ec14b76 IS |
1443 | /* SPMLR - Switch Port MAC Learning Register |
1444 | * ----------------------------------------- | |
1445 | * Controls the Switch MAC learning policy per port. | |
1446 | */ | |
1447 | #define MLXSW_REG_SPMLR_ID 0x2018 | |
1448 | #define MLXSW_REG_SPMLR_LEN 0x8 | |
1449 | ||
21978dcf | 1450 | MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); |
4ec14b76 IS |
1451 | |
1452 | /* reg_spmlr_local_port | |
1453 | * Local port number. | |
1454 | * Access: Index | |
1455 | */ | |
1456 | MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); | |
1457 | ||
1458 | /* reg_spmlr_sub_port | |
1459 | * Virtual port within the physical port. | |
1460 | * Should be set to 0 when virtual ports are not enabled on the port. | |
1461 | * Access: Index | |
1462 | */ | |
1463 | MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); | |
1464 | ||
1465 | enum mlxsw_reg_spmlr_learn_mode { | |
1466 | MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, | |
1467 | MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, | |
1468 | MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, | |
1469 | }; | |
1470 | ||
1471 | /* reg_spmlr_learn_mode | |
1472 | * Learning mode on the port. | |
1473 | * 0 - Learning disabled. | |
1474 | * 2 - Learning enabled. | |
1475 | * 3 - Security mode. | |
1476 | * | |
1477 | * In security mode the switch does not learn MACs on the port, but uses the | |
1478 | * SMAC to see if it exists on another ingress port. If so, the packet is | |
1479 | * classified as a bad packet and is discarded unless the software registers | |
1480 | * to receive port security error packets usign HPKT. | |
1481 | */ | |
1482 | MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); | |
1483 | ||
1484 | static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, | |
1485 | enum mlxsw_reg_spmlr_learn_mode mode) | |
1486 | { | |
1487 | MLXSW_REG_ZERO(spmlr, payload); | |
1488 | mlxsw_reg_spmlr_local_port_set(payload, local_port); | |
1489 | mlxsw_reg_spmlr_sub_port_set(payload, 0); | |
1490 | mlxsw_reg_spmlr_learn_mode_set(payload, mode); | |
1491 | } | |
1492 | ||
64790239 IS |
1493 | /* SVFA - Switch VID to FID Allocation Register |
1494 | * -------------------------------------------- | |
1495 | * Controls the VID to FID mapping and {Port, VID} to FID mapping for | |
1496 | * virtualized ports. | |
1497 | */ | |
1498 | #define MLXSW_REG_SVFA_ID 0x201C | |
1499 | #define MLXSW_REG_SVFA_LEN 0x10 | |
1500 | ||
21978dcf | 1501 | MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); |
64790239 IS |
1502 | |
1503 | /* reg_svfa_swid | |
1504 | * Switch partition ID. | |
1505 | * Access: Index | |
1506 | */ | |
1507 | MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); | |
1508 | ||
1509 | /* reg_svfa_local_port | |
1510 | * Local port number. | |
1511 | * Access: Index | |
1512 | * | |
1513 | * Note: Reserved for 802.1Q FIDs. | |
1514 | */ | |
1515 | MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); | |
1516 | ||
1517 | enum mlxsw_reg_svfa_mt { | |
1518 | MLXSW_REG_SVFA_MT_VID_TO_FID, | |
1519 | MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, | |
1520 | }; | |
1521 | ||
1522 | /* reg_svfa_mapping_table | |
1523 | * Mapping table: | |
1524 | * 0 - VID to FID | |
1525 | * 1 - {Port, VID} to FID | |
1526 | * Access: Index | |
1527 | * | |
1528 | * Note: Reserved for SwitchX-2. | |
1529 | */ | |
1530 | MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); | |
1531 | ||
1532 | /* reg_svfa_v | |
1533 | * Valid. | |
1534 | * Valid if set. | |
1535 | * Access: RW | |
1536 | * | |
1537 | * Note: Reserved for SwitchX-2. | |
1538 | */ | |
1539 | MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); | |
1540 | ||
1541 | /* reg_svfa_fid | |
1542 | * Filtering ID. | |
1543 | * Access: RW | |
1544 | */ | |
1545 | MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); | |
1546 | ||
1547 | /* reg_svfa_vid | |
1548 | * VLAN ID. | |
1549 | * Access: Index | |
1550 | */ | |
1551 | MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); | |
1552 | ||
1553 | /* reg_svfa_counter_set_type | |
1554 | * Counter set type for flow counters. | |
1555 | * Access: RW | |
1556 | * | |
1557 | * Note: Reserved for SwitchX-2. | |
1558 | */ | |
1559 | MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); | |
1560 | ||
1561 | /* reg_svfa_counter_index | |
1562 | * Counter index for flow counters. | |
1563 | * Access: RW | |
1564 | * | |
1565 | * Note: Reserved for SwitchX-2. | |
1566 | */ | |
1567 | MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); | |
1568 | ||
1569 | static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, | |
1570 | enum mlxsw_reg_svfa_mt mt, bool valid, | |
1571 | u16 fid, u16 vid) | |
1572 | { | |
1573 | MLXSW_REG_ZERO(svfa, payload); | |
1574 | local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; | |
1575 | mlxsw_reg_svfa_swid_set(payload, 0); | |
1576 | mlxsw_reg_svfa_local_port_set(payload, local_port); | |
1577 | mlxsw_reg_svfa_mapping_table_set(payload, mt); | |
1578 | mlxsw_reg_svfa_v_set(payload, valid); | |
1579 | mlxsw_reg_svfa_fid_set(payload, fid); | |
1580 | mlxsw_reg_svfa_vid_set(payload, vid); | |
1581 | } | |
1582 | ||
1f65da74 IS |
1583 | /* SVPE - Switch Virtual-Port Enabling Register |
1584 | * -------------------------------------------- | |
1585 | * Enables port virtualization. | |
1586 | */ | |
1587 | #define MLXSW_REG_SVPE_ID 0x201E | |
1588 | #define MLXSW_REG_SVPE_LEN 0x4 | |
1589 | ||
21978dcf | 1590 | MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); |
1f65da74 IS |
1591 | |
1592 | /* reg_svpe_local_port | |
1593 | * Local port number | |
1594 | * Access: Index | |
1595 | * | |
1596 | * Note: CPU port is not supported (uses VLAN mode only). | |
1597 | */ | |
1598 | MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); | |
1599 | ||
1600 | /* reg_svpe_vp_en | |
1601 | * Virtual port enable. | |
1602 | * 0 - Disable, VLAN mode (VID to FID). | |
1603 | * 1 - Enable, Virtual port mode ({Port, VID} to FID). | |
1604 | * Access: RW | |
1605 | */ | |
1606 | MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); | |
1607 | ||
1608 | static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, | |
1609 | bool enable) | |
1610 | { | |
1611 | MLXSW_REG_ZERO(svpe, payload); | |
1612 | mlxsw_reg_svpe_local_port_set(payload, local_port); | |
1613 | mlxsw_reg_svpe_vp_en_set(payload, enable); | |
1614 | } | |
1615 | ||
f1fb693a IS |
1616 | /* SFMR - Switch FID Management Register |
1617 | * ------------------------------------- | |
1618 | * Creates and configures FIDs. | |
1619 | */ | |
1620 | #define MLXSW_REG_SFMR_ID 0x201F | |
1621 | #define MLXSW_REG_SFMR_LEN 0x18 | |
1622 | ||
21978dcf | 1623 | MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); |
f1fb693a IS |
1624 | |
1625 | enum mlxsw_reg_sfmr_op { | |
1626 | MLXSW_REG_SFMR_OP_CREATE_FID, | |
1627 | MLXSW_REG_SFMR_OP_DESTROY_FID, | |
1628 | }; | |
1629 | ||
1630 | /* reg_sfmr_op | |
1631 | * Operation. | |
1632 | * 0 - Create or edit FID. | |
1633 | * 1 - Destroy FID. | |
1634 | * Access: WO | |
1635 | */ | |
1636 | MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); | |
1637 | ||
1638 | /* reg_sfmr_fid | |
1639 | * Filtering ID. | |
1640 | * Access: Index | |
1641 | */ | |
1642 | MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); | |
1643 | ||
1644 | /* reg_sfmr_fid_offset | |
1645 | * FID offset. | |
1646 | * Used to point into the flooding table selected by SFGC register if | |
1647 | * the table is of type FID-Offset. Otherwise, this field is reserved. | |
1648 | * Access: RW | |
1649 | */ | |
1650 | MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); | |
1651 | ||
1652 | /* reg_sfmr_vtfp | |
1653 | * Valid Tunnel Flood Pointer. | |
1654 | * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. | |
1655 | * Access: RW | |
1656 | * | |
1657 | * Note: Reserved for 802.1Q FIDs. | |
1658 | */ | |
1659 | MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); | |
1660 | ||
1661 | /* reg_sfmr_nve_tunnel_flood_ptr | |
1662 | * Underlay Flooding and BC Pointer. | |
1663 | * Used as a pointer to the first entry of the group based link lists of | |
1664 | * flooding or BC entries (for NVE tunnels). | |
1665 | * Access: RW | |
1666 | */ | |
1667 | MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); | |
1668 | ||
1669 | /* reg_sfmr_vv | |
1670 | * VNI Valid. | |
1671 | * If not set, then vni is reserved. | |
1672 | * Access: RW | |
1673 | * | |
1674 | * Note: Reserved for 802.1Q FIDs. | |
1675 | */ | |
1676 | MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); | |
1677 | ||
1678 | /* reg_sfmr_vni | |
1679 | * Virtual Network Identifier. | |
1680 | * Access: RW | |
1681 | * | |
1682 | * Note: A given VNI can only be assigned to one FID. | |
1683 | */ | |
1684 | MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); | |
1685 | ||
1686 | static inline void mlxsw_reg_sfmr_pack(char *payload, | |
1687 | enum mlxsw_reg_sfmr_op op, u16 fid, | |
1688 | u16 fid_offset) | |
1689 | { | |
1690 | MLXSW_REG_ZERO(sfmr, payload); | |
1691 | mlxsw_reg_sfmr_op_set(payload, op); | |
1692 | mlxsw_reg_sfmr_fid_set(payload, fid); | |
1693 | mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); | |
1694 | mlxsw_reg_sfmr_vtfp_set(payload, false); | |
1695 | mlxsw_reg_sfmr_vv_set(payload, false); | |
1696 | } | |
1697 | ||
a4feea74 IS |
1698 | /* SPVMLR - Switch Port VLAN MAC Learning Register |
1699 | * ----------------------------------------------- | |
1700 | * Controls the switch MAC learning policy per {Port, VID}. | |
1701 | */ | |
1702 | #define MLXSW_REG_SPVMLR_ID 0x2020 | |
1703 | #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ | |
1704 | #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ | |
1705 | #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256 | |
1706 | #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ | |
1707 | MLXSW_REG_SPVMLR_REC_LEN * \ | |
1708 | MLXSW_REG_SPVMLR_REC_MAX_COUNT) | |
1709 | ||
21978dcf | 1710 | MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); |
a4feea74 IS |
1711 | |
1712 | /* reg_spvmlr_local_port | |
1713 | * Local ingress port. | |
1714 | * Access: Index | |
1715 | * | |
1716 | * Note: CPU port is not supported. | |
1717 | */ | |
1718 | MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); | |
1719 | ||
1720 | /* reg_spvmlr_num_rec | |
1721 | * Number of records to update. | |
1722 | * Access: OP | |
1723 | */ | |
1724 | MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); | |
1725 | ||
1726 | /* reg_spvmlr_rec_learn_enable | |
1727 | * 0 - Disable learning for {Port, VID}. | |
1728 | * 1 - Enable learning for {Port, VID}. | |
1729 | * Access: RW | |
1730 | */ | |
1731 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, | |
1732 | 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1733 | ||
1734 | /* reg_spvmlr_rec_vid | |
1735 | * VLAN ID to be added/removed from port or for querying. | |
1736 | * Access: Index | |
1737 | */ | |
1738 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, | |
1739 | MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1740 | ||
1741 | static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, | |
1742 | u16 vid_begin, u16 vid_end, | |
1743 | bool learn_enable) | |
1744 | { | |
1745 | int num_rec = vid_end - vid_begin + 1; | |
1746 | int i; | |
1747 | ||
1748 | WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); | |
1749 | ||
1750 | MLXSW_REG_ZERO(spvmlr, payload); | |
1751 | mlxsw_reg_spvmlr_local_port_set(payload, local_port); | |
1752 | mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); | |
1753 | ||
1754 | for (i = 0; i < num_rec; i++) { | |
1755 | mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); | |
1756 | mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); | |
1757 | } | |
1758 | } | |
1759 | ||
76a4c7d3 NF |
1760 | /* QPCR - QoS Policer Configuration Register |
1761 | * ----------------------------------------- | |
1762 | * The QPCR register is used to create policers - that limit | |
1763 | * the rate of bytes or packets via some trap group. | |
1764 | */ | |
1765 | #define MLXSW_REG_QPCR_ID 0x4004 | |
1766 | #define MLXSW_REG_QPCR_LEN 0x28 | |
1767 | ||
1768 | MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); | |
1769 | ||
1770 | enum mlxsw_reg_qpcr_g { | |
1771 | MLXSW_REG_QPCR_G_GLOBAL = 2, | |
1772 | MLXSW_REG_QPCR_G_STORM_CONTROL = 3, | |
1773 | }; | |
1774 | ||
1775 | /* reg_qpcr_g | |
1776 | * The policer type. | |
1777 | * Access: Index | |
1778 | */ | |
1779 | MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); | |
1780 | ||
1781 | /* reg_qpcr_pid | |
1782 | * Policer ID. | |
1783 | * Access: Index | |
1784 | */ | |
1785 | MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); | |
1786 | ||
1787 | /* reg_qpcr_color_aware | |
1788 | * Is the policer aware of colors. | |
1789 | * Must be 0 (unaware) for cpu port. | |
1790 | * Access: RW for unbounded policer. RO for bounded policer. | |
1791 | */ | |
1792 | MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); | |
1793 | ||
1794 | /* reg_qpcr_bytes | |
1795 | * Is policer limit is for bytes per sec or packets per sec. | |
1796 | * 0 - packets | |
1797 | * 1 - bytes | |
1798 | * Access: RW for unbounded policer. RO for bounded policer. | |
1799 | */ | |
1800 | MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); | |
1801 | ||
1802 | enum mlxsw_reg_qpcr_ir_units { | |
1803 | MLXSW_REG_QPCR_IR_UNITS_M, | |
1804 | MLXSW_REG_QPCR_IR_UNITS_K, | |
1805 | }; | |
1806 | ||
1807 | /* reg_qpcr_ir_units | |
1808 | * Policer's units for cir and eir fields (for bytes limits only) | |
1809 | * 1 - 10^3 | |
1810 | * 0 - 10^6 | |
1811 | * Access: OP | |
1812 | */ | |
1813 | MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); | |
1814 | ||
1815 | enum mlxsw_reg_qpcr_rate_type { | |
1816 | MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, | |
1817 | MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, | |
1818 | }; | |
1819 | ||
1820 | /* reg_qpcr_rate_type | |
1821 | * Policer can have one limit (single rate) or 2 limits with specific operation | |
1822 | * for packets that exceed the lower rate but not the upper one. | |
1823 | * (For cpu port must be single rate) | |
1824 | * Access: RW for unbounded policer. RO for bounded policer. | |
1825 | */ | |
1826 | MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); | |
1827 | ||
1828 | /* reg_qpc_cbs | |
1829 | * Policer's committed burst size. | |
1830 | * The policer is working with time slices of 50 nano sec. By default every | |
1831 | * slice is granted the proportionate share of the committed rate. If we want to | |
1832 | * allow a slice to exceed that share (while still keeping the rate per sec) we | |
1833 | * can allow burst. The burst size is between the default proportionate share | |
1834 | * (and no lower than 8) to 32Gb. (Even though giving a number higher than the | |
1835 | * committed rate will result in exceeding the rate). The burst size must be a | |
1836 | * log of 2 and will be determined by 2^cbs. | |
1837 | * Access: RW | |
1838 | */ | |
1839 | MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); | |
1840 | ||
1841 | /* reg_qpcr_cir | |
1842 | * Policer's committed rate. | |
1843 | * The rate used for sungle rate, the lower rate for double rate. | |
1844 | * For bytes limits, the rate will be this value * the unit from ir_units. | |
1845 | * (Resolution error is up to 1%). | |
1846 | * Access: RW | |
1847 | */ | |
1848 | MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); | |
1849 | ||
1850 | /* reg_qpcr_eir | |
1851 | * Policer's exceed rate. | |
1852 | * The higher rate for double rate, reserved for single rate. | |
1853 | * Lower rate for double rate policer. | |
1854 | * For bytes limits, the rate will be this value * the unit from ir_units. | |
1855 | * (Resolution error is up to 1%). | |
1856 | * Access: RW | |
1857 | */ | |
1858 | MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); | |
1859 | ||
1860 | #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 | |
1861 | ||
1862 | /* reg_qpcr_exceed_action. | |
1863 | * What to do with packets between the 2 limits for double rate. | |
1864 | * Access: RW for unbounded policer. RO for bounded policer. | |
1865 | */ | |
1866 | MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); | |
1867 | ||
1868 | enum mlxsw_reg_qpcr_action { | |
1869 | /* Discard */ | |
1870 | MLXSW_REG_QPCR_ACTION_DISCARD = 1, | |
1871 | /* Forward and set color to red. | |
1872 | * If the packet is intended to cpu port, it will be dropped. | |
1873 | */ | |
1874 | MLXSW_REG_QPCR_ACTION_FORWARD = 2, | |
1875 | }; | |
1876 | ||
1877 | /* reg_qpcr_violate_action | |
1878 | * What to do with packets that cross the cir limit (for single rate) or the eir | |
1879 | * limit (for double rate). | |
1880 | * Access: RW for unbounded policer. RO for bounded policer. | |
1881 | */ | |
1882 | MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); | |
1883 | ||
1884 | static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, | |
1885 | enum mlxsw_reg_qpcr_ir_units ir_units, | |
1886 | bool bytes, u32 cir, u16 cbs) | |
1887 | { | |
1888 | MLXSW_REG_ZERO(qpcr, payload); | |
1889 | mlxsw_reg_qpcr_pid_set(payload, pid); | |
1890 | mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); | |
1891 | mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); | |
1892 | mlxsw_reg_qpcr_violate_action_set(payload, | |
1893 | MLXSW_REG_QPCR_ACTION_DISCARD); | |
1894 | mlxsw_reg_qpcr_cir_set(payload, cir); | |
1895 | mlxsw_reg_qpcr_ir_units_set(payload, ir_units); | |
1896 | mlxsw_reg_qpcr_bytes_set(payload, bytes); | |
1897 | mlxsw_reg_qpcr_cbs_set(payload, cbs); | |
1898 | } | |
1899 | ||
2c63a555 IS |
1900 | /* QTCT - QoS Switch Traffic Class Table |
1901 | * ------------------------------------- | |
1902 | * Configures the mapping between the packet switch priority and the | |
1903 | * traffic class on the transmit port. | |
1904 | */ | |
1905 | #define MLXSW_REG_QTCT_ID 0x400A | |
1906 | #define MLXSW_REG_QTCT_LEN 0x08 | |
1907 | ||
21978dcf | 1908 | MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); |
2c63a555 IS |
1909 | |
1910 | /* reg_qtct_local_port | |
1911 | * Local port number. | |
1912 | * Access: Index | |
1913 | * | |
1914 | * Note: CPU port is not supported. | |
1915 | */ | |
1916 | MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); | |
1917 | ||
1918 | /* reg_qtct_sub_port | |
1919 | * Virtual port within the physical port. | |
1920 | * Should be set to 0 when virtual ports are not enabled on the port. | |
1921 | * Access: Index | |
1922 | */ | |
1923 | MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); | |
1924 | ||
1925 | /* reg_qtct_switch_prio | |
1926 | * Switch priority. | |
1927 | * Access: Index | |
1928 | */ | |
1929 | MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); | |
1930 | ||
1931 | /* reg_qtct_tclass | |
1932 | * Traffic class. | |
1933 | * Default values: | |
1934 | * switch_prio 0 : tclass 1 | |
1935 | * switch_prio 1 : tclass 0 | |
1936 | * switch_prio i : tclass i, for i > 1 | |
1937 | * Access: RW | |
1938 | */ | |
1939 | MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); | |
1940 | ||
1941 | static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, | |
1942 | u8 switch_prio, u8 tclass) | |
1943 | { | |
1944 | MLXSW_REG_ZERO(qtct, payload); | |
1945 | mlxsw_reg_qtct_local_port_set(payload, local_port); | |
1946 | mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); | |
1947 | mlxsw_reg_qtct_tclass_set(payload, tclass); | |
1948 | } | |
1949 | ||
b9b7cee4 IS |
1950 | /* QEEC - QoS ETS Element Configuration Register |
1951 | * --------------------------------------------- | |
1952 | * Configures the ETS elements. | |
1953 | */ | |
1954 | #define MLXSW_REG_QEEC_ID 0x400D | |
1955 | #define MLXSW_REG_QEEC_LEN 0x1C | |
1956 | ||
21978dcf | 1957 | MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); |
b9b7cee4 IS |
1958 | |
1959 | /* reg_qeec_local_port | |
1960 | * Local port number. | |
1961 | * Access: Index | |
1962 | * | |
1963 | * Note: CPU port is supported. | |
1964 | */ | |
1965 | MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); | |
1966 | ||
1967 | enum mlxsw_reg_qeec_hr { | |
1968 | MLXSW_REG_QEEC_HIERARCY_PORT, | |
1969 | MLXSW_REG_QEEC_HIERARCY_GROUP, | |
1970 | MLXSW_REG_QEEC_HIERARCY_SUBGROUP, | |
1971 | MLXSW_REG_QEEC_HIERARCY_TC, | |
1972 | }; | |
1973 | ||
1974 | /* reg_qeec_element_hierarchy | |
1975 | * 0 - Port | |
1976 | * 1 - Group | |
1977 | * 2 - Subgroup | |
1978 | * 3 - Traffic Class | |
1979 | * Access: Index | |
1980 | */ | |
1981 | MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); | |
1982 | ||
1983 | /* reg_qeec_element_index | |
1984 | * The index of the element in the hierarchy. | |
1985 | * Access: Index | |
1986 | */ | |
1987 | MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); | |
1988 | ||
1989 | /* reg_qeec_next_element_index | |
1990 | * The index of the next (lower) element in the hierarchy. | |
1991 | * Access: RW | |
1992 | * | |
1993 | * Note: Reserved for element_hierarchy 0. | |
1994 | */ | |
1995 | MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); | |
1996 | ||
1997 | enum { | |
1998 | MLXSW_REG_QEEC_BYTES_MODE, | |
1999 | MLXSW_REG_QEEC_PACKETS_MODE, | |
2000 | }; | |
2001 | ||
2002 | /* reg_qeec_pb | |
2003 | * Packets or bytes mode. | |
2004 | * 0 - Bytes mode | |
2005 | * 1 - Packets mode | |
2006 | * Access: RW | |
2007 | * | |
2008 | * Note: Used for max shaper configuration. For Spectrum, packets mode | |
2009 | * is supported only for traffic classes of CPU port. | |
2010 | */ | |
2011 | MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); | |
2012 | ||
2013 | /* reg_qeec_mase | |
2014 | * Max shaper configuration enable. Enables configuration of the max | |
2015 | * shaper on this ETS element. | |
2016 | * 0 - Disable | |
2017 | * 1 - Enable | |
2018 | * Access: RW | |
2019 | */ | |
2020 | MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); | |
2021 | ||
2022 | /* A large max rate will disable the max shaper. */ | |
2023 | #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ | |
2024 | ||
2025 | /* reg_qeec_max_shaper_rate | |
2026 | * Max shaper information rate. | |
2027 | * For CPU port, can only be configured for port hierarchy. | |
2028 | * When in bytes mode, value is specified in units of 1000bps. | |
2029 | * Access: RW | |
2030 | */ | |
2031 | MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); | |
2032 | ||
2033 | /* reg_qeec_de | |
2034 | * DWRR configuration enable. Enables configuration of the dwrr and | |
2035 | * dwrr_weight. | |
2036 | * 0 - Disable | |
2037 | * 1 - Enable | |
2038 | * Access: RW | |
2039 | */ | |
2040 | MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); | |
2041 | ||
2042 | /* reg_qeec_dwrr | |
2043 | * Transmission selection algorithm to use on the link going down from | |
2044 | * the ETS element. | |
2045 | * 0 - Strict priority | |
2046 | * 1 - DWRR | |
2047 | * Access: RW | |
2048 | */ | |
2049 | MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); | |
2050 | ||
2051 | /* reg_qeec_dwrr_weight | |
2052 | * DWRR weight on the link going down from the ETS element. The | |
2053 | * percentage of bandwidth guaranteed to an ETS element within | |
2054 | * its hierarchy. The sum of all weights across all ETS elements | |
2055 | * within one hierarchy should be equal to 100. Reserved when | |
2056 | * transmission selection algorithm is strict priority. | |
2057 | * Access: RW | |
2058 | */ | |
2059 | MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); | |
2060 | ||
2061 | static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, | |
2062 | enum mlxsw_reg_qeec_hr hr, u8 index, | |
2063 | u8 next_index) | |
2064 | { | |
2065 | MLXSW_REG_ZERO(qeec, payload); | |
2066 | mlxsw_reg_qeec_local_port_set(payload, local_port); | |
2067 | mlxsw_reg_qeec_element_hierarchy_set(payload, hr); | |
2068 | mlxsw_reg_qeec_element_index_set(payload, index); | |
2069 | mlxsw_reg_qeec_next_element_index_set(payload, next_index); | |
2070 | } | |
2071 | ||
4ec14b76 IS |
2072 | /* PMLP - Ports Module to Local Port Register |
2073 | * ------------------------------------------ | |
2074 | * Configures the assignment of modules to local ports. | |
2075 | */ | |
2076 | #define MLXSW_REG_PMLP_ID 0x5002 | |
2077 | #define MLXSW_REG_PMLP_LEN 0x40 | |
2078 | ||
21978dcf | 2079 | MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); |
4ec14b76 IS |
2080 | |
2081 | /* reg_pmlp_rxtx | |
2082 | * 0 - Tx value is used for both Tx and Rx. | |
2083 | * 1 - Rx value is taken from a separte field. | |
2084 | * Access: RW | |
2085 | */ | |
2086 | MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); | |
2087 | ||
2088 | /* reg_pmlp_local_port | |
2089 | * Local port number. | |
2090 | * Access: Index | |
2091 | */ | |
2092 | MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); | |
2093 | ||
2094 | /* reg_pmlp_width | |
2095 | * 0 - Unmap local port. | |
2096 | * 1 - Lane 0 is used. | |
2097 | * 2 - Lanes 0 and 1 are used. | |
2098 | * 4 - Lanes 0, 1, 2 and 3 are used. | |
2099 | * Access: RW | |
2100 | */ | |
2101 | MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); | |
2102 | ||
2103 | /* reg_pmlp_module | |
2104 | * Module number. | |
2105 | * Access: RW | |
2106 | */ | |
bbeeda27 | 2107 | MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); |
4ec14b76 IS |
2108 | |
2109 | /* reg_pmlp_tx_lane | |
2110 | * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. | |
2111 | * Access: RW | |
2112 | */ | |
bbeeda27 | 2113 | MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); |
4ec14b76 IS |
2114 | |
2115 | /* reg_pmlp_rx_lane | |
2116 | * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is | |
2117 | * equal to Tx lane. | |
2118 | * Access: RW | |
2119 | */ | |
bbeeda27 | 2120 | MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); |
4ec14b76 IS |
2121 | |
2122 | static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) | |
2123 | { | |
2124 | MLXSW_REG_ZERO(pmlp, payload); | |
2125 | mlxsw_reg_pmlp_local_port_set(payload, local_port); | |
2126 | } | |
2127 | ||
2128 | /* PMTU - Port MTU Register | |
2129 | * ------------------------ | |
2130 | * Configures and reports the port MTU. | |
2131 | */ | |
2132 | #define MLXSW_REG_PMTU_ID 0x5003 | |
2133 | #define MLXSW_REG_PMTU_LEN 0x10 | |
2134 | ||
21978dcf | 2135 | MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); |
4ec14b76 IS |
2136 | |
2137 | /* reg_pmtu_local_port | |
2138 | * Local port number. | |
2139 | * Access: Index | |
2140 | */ | |
2141 | MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); | |
2142 | ||
2143 | /* reg_pmtu_max_mtu | |
2144 | * Maximum MTU. | |
2145 | * When port type (e.g. Ethernet) is configured, the relevant MTU is | |
2146 | * reported, otherwise the minimum between the max_mtu of the different | |
2147 | * types is reported. | |
2148 | * Access: RO | |
2149 | */ | |
2150 | MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); | |
2151 | ||
2152 | /* reg_pmtu_admin_mtu | |
2153 | * MTU value to set port to. Must be smaller or equal to max_mtu. | |
2154 | * Note: If port type is Infiniband, then port must be disabled, when its | |
2155 | * MTU is set. | |
2156 | * Access: RW | |
2157 | */ | |
2158 | MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); | |
2159 | ||
2160 | /* reg_pmtu_oper_mtu | |
2161 | * The actual MTU configured on the port. Packets exceeding this size | |
2162 | * will be dropped. | |
2163 | * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband | |
2164 | * oper_mtu might be smaller than admin_mtu. | |
2165 | * Access: RO | |
2166 | */ | |
2167 | MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); | |
2168 | ||
2169 | static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, | |
2170 | u16 new_mtu) | |
2171 | { | |
2172 | MLXSW_REG_ZERO(pmtu, payload); | |
2173 | mlxsw_reg_pmtu_local_port_set(payload, local_port); | |
2174 | mlxsw_reg_pmtu_max_mtu_set(payload, 0); | |
2175 | mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); | |
2176 | mlxsw_reg_pmtu_oper_mtu_set(payload, 0); | |
2177 | } | |
2178 | ||
2179 | /* PTYS - Port Type and Speed Register | |
2180 | * ----------------------------------- | |
2181 | * Configures and reports the port speed type. | |
2182 | * | |
2183 | * Note: When set while the link is up, the changes will not take effect | |
2184 | * until the port transitions from down to up state. | |
2185 | */ | |
2186 | #define MLXSW_REG_PTYS_ID 0x5004 | |
2187 | #define MLXSW_REG_PTYS_LEN 0x40 | |
2188 | ||
21978dcf | 2189 | MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); |
4ec14b76 IS |
2190 | |
2191 | /* reg_ptys_local_port | |
2192 | * Local port number. | |
2193 | * Access: Index | |
2194 | */ | |
2195 | MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); | |
2196 | ||
79417702 | 2197 | #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) |
4ec14b76 IS |
2198 | #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) |
2199 | ||
2200 | /* reg_ptys_proto_mask | |
2201 | * Protocol mask. Indicates which protocol is used. | |
2202 | * 0 - Infiniband. | |
2203 | * 1 - Fibre Channel. | |
2204 | * 2 - Ethernet. | |
2205 | * Access: Index | |
2206 | */ | |
2207 | MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); | |
2208 | ||
4149b97f IS |
2209 | enum { |
2210 | MLXSW_REG_PTYS_AN_STATUS_NA, | |
2211 | MLXSW_REG_PTYS_AN_STATUS_OK, | |
2212 | MLXSW_REG_PTYS_AN_STATUS_FAIL, | |
2213 | }; | |
2214 | ||
2215 | /* reg_ptys_an_status | |
2216 | * Autonegotiation status. | |
2217 | * Access: RO | |
2218 | */ | |
2219 | MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); | |
2220 | ||
4ec14b76 IS |
2221 | #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) |
2222 | #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) | |
2223 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) | |
2224 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) | |
2225 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) | |
2226 | #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) | |
2227 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) | |
2228 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) | |
2229 | #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) | |
2230 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) | |
2231 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) | |
2232 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) | |
2233 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) | |
2234 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) | |
b9d66a36 | 2235 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) |
4ec14b76 IS |
2236 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) |
2237 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) | |
2238 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) | |
2239 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) | |
2240 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) | |
2241 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) | |
2242 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) | |
2243 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) | |
2244 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) | |
2245 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) | |
2246 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) | |
2247 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) | |
2248 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) | |
2249 | ||
2250 | /* reg_ptys_eth_proto_cap | |
2251 | * Ethernet port supported speeds and protocols. | |
2252 | * Access: RO | |
2253 | */ | |
2254 | MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); | |
2255 | ||
79417702 ER |
2256 | /* reg_ptys_ib_link_width_cap |
2257 | * IB port supported widths. | |
2258 | * Access: RO | |
2259 | */ | |
2260 | MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); | |
2261 | ||
2262 | #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) | |
2263 | #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) | |
2264 | #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) | |
2265 | #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) | |
2266 | #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) | |
2267 | #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) | |
2268 | ||
2269 | /* reg_ptys_ib_proto_cap | |
2270 | * IB port supported speeds and protocols. | |
2271 | * Access: RO | |
2272 | */ | |
2273 | MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); | |
2274 | ||
4ec14b76 IS |
2275 | /* reg_ptys_eth_proto_admin |
2276 | * Speed and protocol to set port to. | |
2277 | * Access: RW | |
2278 | */ | |
2279 | MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); | |
2280 | ||
79417702 ER |
2281 | /* reg_ptys_ib_link_width_admin |
2282 | * IB width to set port to. | |
2283 | * Access: RW | |
2284 | */ | |
2285 | MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); | |
2286 | ||
2287 | /* reg_ptys_ib_proto_admin | |
2288 | * IB speeds and protocols to set port to. | |
2289 | * Access: RW | |
2290 | */ | |
2291 | MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); | |
2292 | ||
4ec14b76 IS |
2293 | /* reg_ptys_eth_proto_oper |
2294 | * The current speed and protocol configured for the port. | |
2295 | * Access: RO | |
2296 | */ | |
2297 | MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); | |
2298 | ||
79417702 ER |
2299 | /* reg_ptys_ib_link_width_oper |
2300 | * The current IB width to set port to. | |
2301 | * Access: RO | |
2302 | */ | |
2303 | MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); | |
2304 | ||
2305 | /* reg_ptys_ib_proto_oper | |
2306 | * The current IB speed and protocol. | |
2307 | * Access: RO | |
2308 | */ | |
2309 | MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); | |
2310 | ||
4149b97f IS |
2311 | /* reg_ptys_eth_proto_lp_advertise |
2312 | * The protocols that were advertised by the link partner during | |
2313 | * autonegotiation. | |
2314 | * Access: RO | |
2315 | */ | |
2316 | MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); | |
2317 | ||
401c8b4e ER |
2318 | static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, |
2319 | u32 proto_admin) | |
4ec14b76 IS |
2320 | { |
2321 | MLXSW_REG_ZERO(ptys, payload); | |
2322 | mlxsw_reg_ptys_local_port_set(payload, local_port); | |
2323 | mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); | |
2324 | mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); | |
2325 | } | |
2326 | ||
401c8b4e ER |
2327 | static inline void mlxsw_reg_ptys_eth_unpack(char *payload, |
2328 | u32 *p_eth_proto_cap, | |
2329 | u32 *p_eth_proto_adm, | |
2330 | u32 *p_eth_proto_oper) | |
4ec14b76 IS |
2331 | { |
2332 | if (p_eth_proto_cap) | |
2333 | *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); | |
2334 | if (p_eth_proto_adm) | |
2335 | *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); | |
2336 | if (p_eth_proto_oper) | |
2337 | *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); | |
2338 | } | |
2339 | ||
79417702 ER |
2340 | static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, |
2341 | u16 proto_admin, u16 link_width) | |
2342 | { | |
2343 | MLXSW_REG_ZERO(ptys, payload); | |
2344 | mlxsw_reg_ptys_local_port_set(payload, local_port); | |
2345 | mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); | |
2346 | mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); | |
2347 | mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); | |
2348 | } | |
2349 | ||
2350 | static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, | |
2351 | u16 *p_ib_link_width_cap, | |
2352 | u16 *p_ib_proto_oper, | |
2353 | u16 *p_ib_link_width_oper) | |
2354 | { | |
2355 | if (p_ib_proto_cap) | |
2356 | *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); | |
2357 | if (p_ib_link_width_cap) | |
2358 | *p_ib_link_width_cap = | |
2359 | mlxsw_reg_ptys_ib_link_width_cap_get(payload); | |
2360 | if (p_ib_proto_oper) | |
2361 | *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); | |
2362 | if (p_ib_link_width_oper) | |
2363 | *p_ib_link_width_oper = | |
2364 | mlxsw_reg_ptys_ib_link_width_oper_get(payload); | |
2365 | } | |
2366 | ||
4ec14b76 IS |
2367 | /* PPAD - Port Physical Address Register |
2368 | * ------------------------------------- | |
2369 | * The PPAD register configures the per port physical MAC address. | |
2370 | */ | |
2371 | #define MLXSW_REG_PPAD_ID 0x5005 | |
2372 | #define MLXSW_REG_PPAD_LEN 0x10 | |
2373 | ||
21978dcf | 2374 | MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); |
4ec14b76 IS |
2375 | |
2376 | /* reg_ppad_single_base_mac | |
2377 | * 0: base_mac, local port should be 0 and mac[7:0] is | |
2378 | * reserved. HW will set incremental | |
2379 | * 1: single_mac - mac of the local_port | |
2380 | * Access: RW | |
2381 | */ | |
2382 | MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); | |
2383 | ||
2384 | /* reg_ppad_local_port | |
2385 | * port number, if single_base_mac = 0 then local_port is reserved | |
2386 | * Access: RW | |
2387 | */ | |
2388 | MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); | |
2389 | ||
2390 | /* reg_ppad_mac | |
2391 | * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. | |
2392 | * If single_base_mac = 1 - the per port MAC address | |
2393 | * Access: RW | |
2394 | */ | |
2395 | MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); | |
2396 | ||
2397 | static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, | |
2398 | u8 local_port) | |
2399 | { | |
2400 | MLXSW_REG_ZERO(ppad, payload); | |
2401 | mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); | |
2402 | mlxsw_reg_ppad_local_port_set(payload, local_port); | |
2403 | } | |
2404 | ||
2405 | /* PAOS - Ports Administrative and Operational Status Register | |
2406 | * ----------------------------------------------------------- | |
2407 | * Configures and retrieves per port administrative and operational status. | |
2408 | */ | |
2409 | #define MLXSW_REG_PAOS_ID 0x5006 | |
2410 | #define MLXSW_REG_PAOS_LEN 0x10 | |
2411 | ||
21978dcf | 2412 | MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); |
4ec14b76 IS |
2413 | |
2414 | /* reg_paos_swid | |
2415 | * Switch partition ID with which to associate the port. | |
2416 | * Note: while external ports uses unique local port numbers (and thus swid is | |
2417 | * redundant), router ports use the same local port number where swid is the | |
2418 | * only indication for the relevant port. | |
2419 | * Access: Index | |
2420 | */ | |
2421 | MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); | |
2422 | ||
2423 | /* reg_paos_local_port | |
2424 | * Local port number. | |
2425 | * Access: Index | |
2426 | */ | |
2427 | MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); | |
2428 | ||
2429 | /* reg_paos_admin_status | |
2430 | * Port administrative state (the desired state of the port): | |
2431 | * 1 - Up. | |
2432 | * 2 - Down. | |
2433 | * 3 - Up once. This means that in case of link failure, the port won't go | |
2434 | * into polling mode, but will wait to be re-enabled by software. | |
2435 | * 4 - Disabled by system. Can only be set by hardware. | |
2436 | * Access: RW | |
2437 | */ | |
2438 | MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); | |
2439 | ||
2440 | /* reg_paos_oper_status | |
2441 | * Port operational state (the current state): | |
2442 | * 1 - Up. | |
2443 | * 2 - Down. | |
2444 | * 3 - Down by port failure. This means that the device will not let the | |
2445 | * port up again until explicitly specified by software. | |
2446 | * Access: RO | |
2447 | */ | |
2448 | MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); | |
2449 | ||
2450 | /* reg_paos_ase | |
2451 | * Admin state update enabled. | |
2452 | * Access: WO | |
2453 | */ | |
2454 | MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); | |
2455 | ||
2456 | /* reg_paos_ee | |
2457 | * Event update enable. If this bit is set, event generation will be | |
2458 | * updated based on the e field. | |
2459 | * Access: WO | |
2460 | */ | |
2461 | MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); | |
2462 | ||
2463 | /* reg_paos_e | |
2464 | * Event generation on operational state change: | |
2465 | * 0 - Do not generate event. | |
2466 | * 1 - Generate Event. | |
2467 | * 2 - Generate Single Event. | |
2468 | * Access: RW | |
2469 | */ | |
2470 | MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); | |
2471 | ||
2472 | static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, | |
2473 | enum mlxsw_port_admin_status status) | |
2474 | { | |
2475 | MLXSW_REG_ZERO(paos, payload); | |
2476 | mlxsw_reg_paos_swid_set(payload, 0); | |
2477 | mlxsw_reg_paos_local_port_set(payload, local_port); | |
2478 | mlxsw_reg_paos_admin_status_set(payload, status); | |
2479 | mlxsw_reg_paos_oper_status_set(payload, 0); | |
2480 | mlxsw_reg_paos_ase_set(payload, 1); | |
2481 | mlxsw_reg_paos_ee_set(payload, 1); | |
2482 | mlxsw_reg_paos_e_set(payload, 1); | |
2483 | } | |
2484 | ||
6f253d83 IS |
2485 | /* PFCC - Ports Flow Control Configuration Register |
2486 | * ------------------------------------------------ | |
2487 | * Configures and retrieves the per port flow control configuration. | |
2488 | */ | |
2489 | #define MLXSW_REG_PFCC_ID 0x5007 | |
2490 | #define MLXSW_REG_PFCC_LEN 0x20 | |
2491 | ||
21978dcf | 2492 | MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); |
6f253d83 IS |
2493 | |
2494 | /* reg_pfcc_local_port | |
2495 | * Local port number. | |
2496 | * Access: Index | |
2497 | */ | |
2498 | MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); | |
2499 | ||
2500 | /* reg_pfcc_pnat | |
2501 | * Port number access type. Determines the way local_port is interpreted: | |
2502 | * 0 - Local port number. | |
2503 | * 1 - IB / label port number. | |
2504 | * Access: Index | |
2505 | */ | |
2506 | MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); | |
2507 | ||
2508 | /* reg_pfcc_shl_cap | |
2509 | * Send to higher layers capabilities: | |
2510 | * 0 - No capability of sending Pause and PFC frames to higher layers. | |
2511 | * 1 - Device has capability of sending Pause and PFC frames to higher | |
2512 | * layers. | |
2513 | * Access: RO | |
2514 | */ | |
2515 | MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); | |
2516 | ||
2517 | /* reg_pfcc_shl_opr | |
2518 | * Send to higher layers operation: | |
2519 | * 0 - Pause and PFC frames are handled by the port (default). | |
2520 | * 1 - Pause and PFC frames are handled by the port and also sent to | |
2521 | * higher layers. Only valid if shl_cap = 1. | |
2522 | * Access: RW | |
2523 | */ | |
2524 | MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); | |
2525 | ||
2526 | /* reg_pfcc_ppan | |
2527 | * Pause policy auto negotiation. | |
2528 | * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. | |
2529 | * 1 - Enabled. When auto-negotiation is performed, set the Pause policy | |
2530 | * based on the auto-negotiation resolution. | |
2531 | * Access: RW | |
2532 | * | |
2533 | * Note: The auto-negotiation advertisement is set according to pptx and | |
2534 | * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. | |
2535 | */ | |
2536 | MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); | |
2537 | ||
2538 | /* reg_pfcc_prio_mask_tx | |
2539 | * Bit per priority indicating if Tx flow control policy should be | |
2540 | * updated based on bit pfctx. | |
2541 | * Access: WO | |
2542 | */ | |
2543 | MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); | |
2544 | ||
2545 | /* reg_pfcc_prio_mask_rx | |
2546 | * Bit per priority indicating if Rx flow control policy should be | |
2547 | * updated based on bit pfcrx. | |
2548 | * Access: WO | |
2549 | */ | |
2550 | MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); | |
2551 | ||
2552 | /* reg_pfcc_pptx | |
2553 | * Admin Pause policy on Tx. | |
2554 | * 0 - Never generate Pause frames (default). | |
2555 | * 1 - Generate Pause frames according to Rx buffer threshold. | |
2556 | * Access: RW | |
2557 | */ | |
2558 | MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); | |
2559 | ||
2560 | /* reg_pfcc_aptx | |
2561 | * Active (operational) Pause policy on Tx. | |
2562 | * 0 - Never generate Pause frames. | |
2563 | * 1 - Generate Pause frames according to Rx buffer threshold. | |
2564 | * Access: RO | |
2565 | */ | |
2566 | MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); | |
2567 | ||
2568 | /* reg_pfcc_pfctx | |
2569 | * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: | |
2570 | * 0 - Never generate priority Pause frames on the specified priority | |
2571 | * (default). | |
2572 | * 1 - Generate priority Pause frames according to Rx buffer threshold on | |
2573 | * the specified priority. | |
2574 | * Access: RW | |
2575 | * | |
2576 | * Note: pfctx and pptx must be mutually exclusive. | |
2577 | */ | |
2578 | MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); | |
2579 | ||
2580 | /* reg_pfcc_pprx | |
2581 | * Admin Pause policy on Rx. | |
2582 | * 0 - Ignore received Pause frames (default). | |
2583 | * 1 - Respect received Pause frames. | |
2584 | * Access: RW | |
2585 | */ | |
2586 | MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); | |
2587 | ||
2588 | /* reg_pfcc_aprx | |
2589 | * Active (operational) Pause policy on Rx. | |
2590 | * 0 - Ignore received Pause frames. | |
2591 | * 1 - Respect received Pause frames. | |
2592 | * Access: RO | |
2593 | */ | |
2594 | MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); | |
2595 | ||
2596 | /* reg_pfcc_pfcrx | |
2597 | * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: | |
2598 | * 0 - Ignore incoming priority Pause frames on the specified priority | |
2599 | * (default). | |
2600 | * 1 - Respect incoming priority Pause frames on the specified priority. | |
2601 | * Access: RW | |
2602 | */ | |
2603 | MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); | |
2604 | ||
d81a6bdb IS |
2605 | #define MLXSW_REG_PFCC_ALL_PRIO 0xFF |
2606 | ||
2607 | static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) | |
2608 | { | |
2609 | mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); | |
2610 | mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); | |
2611 | mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); | |
2612 | mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); | |
2613 | } | |
2614 | ||
6f253d83 IS |
2615 | static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) |
2616 | { | |
2617 | MLXSW_REG_ZERO(pfcc, payload); | |
2618 | mlxsw_reg_pfcc_local_port_set(payload, local_port); | |
2619 | } | |
2620 | ||
4ec14b76 IS |
2621 | /* PPCNT - Ports Performance Counters Register |
2622 | * ------------------------------------------- | |
2623 | * The PPCNT register retrieves per port performance counters. | |
2624 | */ | |
2625 | #define MLXSW_REG_PPCNT_ID 0x5008 | |
2626 | #define MLXSW_REG_PPCNT_LEN 0x100 | |
2627 | ||
21978dcf | 2628 | MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); |
4ec14b76 IS |
2629 | |
2630 | /* reg_ppcnt_swid | |
2631 | * For HCA: must be always 0. | |
2632 | * Switch partition ID to associate port with. | |
2633 | * Switch partitions are numbered from 0 to 7 inclusively. | |
2634 | * Switch partition 254 indicates stacking ports. | |
2635 | * Switch partition 255 indicates all switch partitions. | |
2636 | * Only valid on Set() operation with local_port=255. | |
2637 | * Access: Index | |
2638 | */ | |
2639 | MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); | |
2640 | ||
2641 | /* reg_ppcnt_local_port | |
2642 | * Local port number. | |
2643 | * 255 indicates all ports on the device, and is only allowed | |
2644 | * for Set() operation. | |
2645 | * Access: Index | |
2646 | */ | |
2647 | MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); | |
2648 | ||
2649 | /* reg_ppcnt_pnat | |
2650 | * Port number access type: | |
2651 | * 0 - Local port number | |
2652 | * 1 - IB port number | |
2653 | * Access: Index | |
2654 | */ | |
2655 | MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); | |
2656 | ||
34dba0a5 IS |
2657 | enum mlxsw_reg_ppcnt_grp { |
2658 | MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, | |
2659 | MLXSW_REG_PPCNT_PRIO_CNT = 0x10, | |
df4750e8 | 2660 | MLXSW_REG_PPCNT_TC_CNT = 0x11, |
34dba0a5 IS |
2661 | }; |
2662 | ||
4ec14b76 IS |
2663 | /* reg_ppcnt_grp |
2664 | * Performance counter group. | |
2665 | * Group 63 indicates all groups. Only valid on Set() operation with | |
2666 | * clr bit set. | |
2667 | * 0x0: IEEE 802.3 Counters | |
2668 | * 0x1: RFC 2863 Counters | |
2669 | * 0x2: RFC 2819 Counters | |
2670 | * 0x3: RFC 3635 Counters | |
2671 | * 0x5: Ethernet Extended Counters | |
2672 | * 0x8: Link Level Retransmission Counters | |
2673 | * 0x10: Per Priority Counters | |
2674 | * 0x11: Per Traffic Class Counters | |
2675 | * 0x12: Physical Layer Counters | |
2676 | * Access: Index | |
2677 | */ | |
2678 | MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); | |
2679 | ||
2680 | /* reg_ppcnt_clr | |
2681 | * Clear counters. Setting the clr bit will reset the counter value | |
2682 | * for all counters in the counter group. This bit can be set | |
2683 | * for both Set() and Get() operation. | |
2684 | * Access: OP | |
2685 | */ | |
2686 | MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); | |
2687 | ||
2688 | /* reg_ppcnt_prio_tc | |
2689 | * Priority for counter set that support per priority, valid values: 0-7. | |
2690 | * Traffic class for counter set that support per traffic class, | |
2691 | * valid values: 0- cap_max_tclass-1 . | |
2692 | * For HCA: cap_max_tclass is always 8. | |
2693 | * Otherwise must be 0. | |
2694 | * Access: Index | |
2695 | */ | |
2696 | MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); | |
2697 | ||
34dba0a5 IS |
2698 | /* Ethernet IEEE 802.3 Counter Group */ |
2699 | ||
4ec14b76 IS |
2700 | /* reg_ppcnt_a_frames_transmitted_ok |
2701 | * Access: RO | |
2702 | */ | |
2703 | MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, | |
2704 | 0x08 + 0x00, 0, 64); | |
2705 | ||
2706 | /* reg_ppcnt_a_frames_received_ok | |
2707 | * Access: RO | |
2708 | */ | |
2709 | MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, | |
2710 | 0x08 + 0x08, 0, 64); | |
2711 | ||
2712 | /* reg_ppcnt_a_frame_check_sequence_errors | |
2713 | * Access: RO | |
2714 | */ | |
2715 | MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, | |
2716 | 0x08 + 0x10, 0, 64); | |
2717 | ||
2718 | /* reg_ppcnt_a_alignment_errors | |
2719 | * Access: RO | |
2720 | */ | |
2721 | MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, | |
2722 | 0x08 + 0x18, 0, 64); | |
2723 | ||
2724 | /* reg_ppcnt_a_octets_transmitted_ok | |
2725 | * Access: RO | |
2726 | */ | |
2727 | MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, | |
2728 | 0x08 + 0x20, 0, 64); | |
2729 | ||
2730 | /* reg_ppcnt_a_octets_received_ok | |
2731 | * Access: RO | |
2732 | */ | |
2733 | MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, | |
2734 | 0x08 + 0x28, 0, 64); | |
2735 | ||
2736 | /* reg_ppcnt_a_multicast_frames_xmitted_ok | |
2737 | * Access: RO | |
2738 | */ | |
2739 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, | |
2740 | 0x08 + 0x30, 0, 64); | |
2741 | ||
2742 | /* reg_ppcnt_a_broadcast_frames_xmitted_ok | |
2743 | * Access: RO | |
2744 | */ | |
2745 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, | |
2746 | 0x08 + 0x38, 0, 64); | |
2747 | ||
2748 | /* reg_ppcnt_a_multicast_frames_received_ok | |
2749 | * Access: RO | |
2750 | */ | |
2751 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, | |
2752 | 0x08 + 0x40, 0, 64); | |
2753 | ||
2754 | /* reg_ppcnt_a_broadcast_frames_received_ok | |
2755 | * Access: RO | |
2756 | */ | |
2757 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, | |
2758 | 0x08 + 0x48, 0, 64); | |
2759 | ||
2760 | /* reg_ppcnt_a_in_range_length_errors | |
2761 | * Access: RO | |
2762 | */ | |
2763 | MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, | |
2764 | 0x08 + 0x50, 0, 64); | |
2765 | ||
2766 | /* reg_ppcnt_a_out_of_range_length_field | |
2767 | * Access: RO | |
2768 | */ | |
2769 | MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, | |
2770 | 0x08 + 0x58, 0, 64); | |
2771 | ||
2772 | /* reg_ppcnt_a_frame_too_long_errors | |
2773 | * Access: RO | |
2774 | */ | |
2775 | MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, | |
2776 | 0x08 + 0x60, 0, 64); | |
2777 | ||
2778 | /* reg_ppcnt_a_symbol_error_during_carrier | |
2779 | * Access: RO | |
2780 | */ | |
2781 | MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, | |
2782 | 0x08 + 0x68, 0, 64); | |
2783 | ||
2784 | /* reg_ppcnt_a_mac_control_frames_transmitted | |
2785 | * Access: RO | |
2786 | */ | |
2787 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, | |
2788 | 0x08 + 0x70, 0, 64); | |
2789 | ||
2790 | /* reg_ppcnt_a_mac_control_frames_received | |
2791 | * Access: RO | |
2792 | */ | |
2793 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, | |
2794 | 0x08 + 0x78, 0, 64); | |
2795 | ||
2796 | /* reg_ppcnt_a_unsupported_opcodes_received | |
2797 | * Access: RO | |
2798 | */ | |
2799 | MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, | |
2800 | 0x08 + 0x80, 0, 64); | |
2801 | ||
2802 | /* reg_ppcnt_a_pause_mac_ctrl_frames_received | |
2803 | * Access: RO | |
2804 | */ | |
2805 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, | |
2806 | 0x08 + 0x88, 0, 64); | |
2807 | ||
2808 | /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted | |
2809 | * Access: RO | |
2810 | */ | |
2811 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, | |
2812 | 0x08 + 0x90, 0, 64); | |
2813 | ||
34dba0a5 IS |
2814 | /* Ethernet Per Priority Group Counters */ |
2815 | ||
2816 | /* reg_ppcnt_rx_octets | |
2817 | * Access: RO | |
2818 | */ | |
2819 | MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64); | |
2820 | ||
2821 | /* reg_ppcnt_rx_frames | |
2822 | * Access: RO | |
2823 | */ | |
2824 | MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64); | |
2825 | ||
2826 | /* reg_ppcnt_tx_octets | |
2827 | * Access: RO | |
2828 | */ | |
2829 | MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64); | |
2830 | ||
2831 | /* reg_ppcnt_tx_frames | |
2832 | * Access: RO | |
2833 | */ | |
2834 | MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64); | |
2835 | ||
2836 | /* reg_ppcnt_rx_pause | |
2837 | * Access: RO | |
2838 | */ | |
2839 | MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64); | |
2840 | ||
2841 | /* reg_ppcnt_rx_pause_duration | |
2842 | * Access: RO | |
2843 | */ | |
2844 | MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64); | |
2845 | ||
2846 | /* reg_ppcnt_tx_pause | |
2847 | * Access: RO | |
2848 | */ | |
2849 | MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64); | |
2850 | ||
2851 | /* reg_ppcnt_tx_pause_duration | |
2852 | * Access: RO | |
2853 | */ | |
2854 | MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64); | |
2855 | ||
2856 | /* reg_ppcnt_rx_pause_transition | |
2857 | * Access: RO | |
2858 | */ | |
2859 | MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64); | |
2860 | ||
df4750e8 IS |
2861 | /* Ethernet Per Traffic Group Counters */ |
2862 | ||
2863 | /* reg_ppcnt_tc_transmit_queue | |
2864 | * Contains the transmit queue depth in cells of traffic class | |
2865 | * selected by prio_tc and the port selected by local_port. | |
2866 | * The field cannot be cleared. | |
2867 | * Access: RO | |
2868 | */ | |
2869 | MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64); | |
2870 | ||
2871 | /* reg_ppcnt_tc_no_buffer_discard_uc | |
2872 | * The number of unicast packets dropped due to lack of shared | |
2873 | * buffer resources. | |
2874 | * Access: RO | |
2875 | */ | |
2876 | MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64); | |
2877 | ||
34dba0a5 IS |
2878 | static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, |
2879 | enum mlxsw_reg_ppcnt_grp grp, | |
2880 | u8 prio_tc) | |
4ec14b76 IS |
2881 | { |
2882 | MLXSW_REG_ZERO(ppcnt, payload); | |
2883 | mlxsw_reg_ppcnt_swid_set(payload, 0); | |
2884 | mlxsw_reg_ppcnt_local_port_set(payload, local_port); | |
2885 | mlxsw_reg_ppcnt_pnat_set(payload, 0); | |
34dba0a5 | 2886 | mlxsw_reg_ppcnt_grp_set(payload, grp); |
4ec14b76 | 2887 | mlxsw_reg_ppcnt_clr_set(payload, 0); |
34dba0a5 | 2888 | mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); |
4ec14b76 IS |
2889 | } |
2890 | ||
7136793e ER |
2891 | /* PLIB - Port Local to InfiniBand Port |
2892 | * ------------------------------------ | |
2893 | * The PLIB register performs mapping from Local Port into InfiniBand Port. | |
2894 | */ | |
2895 | #define MLXSW_REG_PLIB_ID 0x500A | |
2896 | #define MLXSW_REG_PLIB_LEN 0x10 | |
2897 | ||
2898 | MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); | |
2899 | ||
2900 | /* reg_plib_local_port | |
2901 | * Local port number. | |
2902 | * Access: Index | |
2903 | */ | |
2904 | MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); | |
2905 | ||
2906 | /* reg_plib_ib_port | |
2907 | * InfiniBand port remapping for local_port. | |
2908 | * Access: RW | |
2909 | */ | |
2910 | MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); | |
2911 | ||
b98ff151 IS |
2912 | /* PPTB - Port Prio To Buffer Register |
2913 | * ----------------------------------- | |
2914 | * Configures the switch priority to buffer table. | |
2915 | */ | |
2916 | #define MLXSW_REG_PPTB_ID 0x500B | |
11719a58 | 2917 | #define MLXSW_REG_PPTB_LEN 0x10 |
b98ff151 | 2918 | |
21978dcf | 2919 | MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); |
b98ff151 IS |
2920 | |
2921 | enum { | |
2922 | MLXSW_REG_PPTB_MM_UM, | |
2923 | MLXSW_REG_PPTB_MM_UNICAST, | |
2924 | MLXSW_REG_PPTB_MM_MULTICAST, | |
2925 | }; | |
2926 | ||
2927 | /* reg_pptb_mm | |
2928 | * Mapping mode. | |
2929 | * 0 - Map both unicast and multicast packets to the same buffer. | |
2930 | * 1 - Map only unicast packets. | |
2931 | * 2 - Map only multicast packets. | |
2932 | * Access: Index | |
2933 | * | |
2934 | * Note: SwitchX-2 only supports the first option. | |
2935 | */ | |
2936 | MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); | |
2937 | ||
2938 | /* reg_pptb_local_port | |
2939 | * Local port number. | |
2940 | * Access: Index | |
2941 | */ | |
2942 | MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); | |
2943 | ||
2944 | /* reg_pptb_um | |
2945 | * Enables the update of the untagged_buf field. | |
2946 | * Access: RW | |
2947 | */ | |
2948 | MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); | |
2949 | ||
2950 | /* reg_pptb_pm | |
2951 | * Enables the update of the prio_to_buff field. | |
2952 | * Bit <i> is a flag for updating the mapping for switch priority <i>. | |
2953 | * Access: RW | |
2954 | */ | |
2955 | MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); | |
2956 | ||
2957 | /* reg_pptb_prio_to_buff | |
2958 | * Mapping of switch priority <i> to one of the allocated receive port | |
2959 | * buffers. | |
2960 | * Access: RW | |
2961 | */ | |
2962 | MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); | |
2963 | ||
2964 | /* reg_pptb_pm_msb | |
2965 | * Enables the update of the prio_to_buff field. | |
2966 | * Bit <i> is a flag for updating the mapping for switch priority <i+8>. | |
2967 | * Access: RW | |
2968 | */ | |
2969 | MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); | |
2970 | ||
2971 | /* reg_pptb_untagged_buff | |
2972 | * Mapping of untagged frames to one of the allocated receive port buffers. | |
2973 | * Access: RW | |
2974 | * | |
2975 | * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for | |
2976 | * Spectrum, as it maps untagged packets based on the default switch priority. | |
2977 | */ | |
2978 | MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); | |
2979 | ||
11719a58 IS |
2980 | /* reg_pptb_prio_to_buff_msb |
2981 | * Mapping of switch priority <i+8> to one of the allocated receive port | |
2982 | * buffers. | |
2983 | * Access: RW | |
2984 | */ | |
2985 | MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); | |
2986 | ||
b98ff151 IS |
2987 | #define MLXSW_REG_PPTB_ALL_PRIO 0xFF |
2988 | ||
2989 | static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) | |
2990 | { | |
2991 | MLXSW_REG_ZERO(pptb, payload); | |
2992 | mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); | |
2993 | mlxsw_reg_pptb_local_port_set(payload, local_port); | |
2994 | mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); | |
11719a58 IS |
2995 | mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); |
2996 | } | |
2997 | ||
2998 | static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, | |
2999 | u8 buff) | |
3000 | { | |
3001 | mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); | |
3002 | mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); | |
b98ff151 IS |
3003 | } |
3004 | ||
e0594369 JP |
3005 | /* PBMC - Port Buffer Management Control Register |
3006 | * ---------------------------------------------- | |
3007 | * The PBMC register configures and retrieves the port packet buffer | |
3008 | * allocation for different Prios, and the Pause threshold management. | |
3009 | */ | |
3010 | #define MLXSW_REG_PBMC_ID 0x500C | |
7ad7cd61 | 3011 | #define MLXSW_REG_PBMC_LEN 0x6C |
e0594369 | 3012 | |
21978dcf | 3013 | MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); |
e0594369 JP |
3014 | |
3015 | /* reg_pbmc_local_port | |
3016 | * Local port number. | |
3017 | * Access: Index | |
3018 | */ | |
3019 | MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); | |
3020 | ||
3021 | /* reg_pbmc_xoff_timer_value | |
3022 | * When device generates a pause frame, it uses this value as the pause | |
3023 | * timer (time for the peer port to pause in quota-512 bit time). | |
3024 | * Access: RW | |
3025 | */ | |
3026 | MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); | |
3027 | ||
3028 | /* reg_pbmc_xoff_refresh | |
3029 | * The time before a new pause frame should be sent to refresh the pause RW | |
3030 | * state. Using the same units as xoff_timer_value above (in quota-512 bit | |
3031 | * time). | |
3032 | * Access: RW | |
3033 | */ | |
3034 | MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); | |
3035 | ||
d6b7c13b IS |
3036 | #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 |
3037 | ||
e0594369 JP |
3038 | /* reg_pbmc_buf_lossy |
3039 | * The field indicates if the buffer is lossy. | |
3040 | * 0 - Lossless | |
3041 | * 1 - Lossy | |
3042 | * Access: RW | |
3043 | */ | |
3044 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); | |
3045 | ||
3046 | /* reg_pbmc_buf_epsb | |
3047 | * Eligible for Port Shared buffer. | |
3048 | * If epsb is set, packets assigned to buffer are allowed to insert the port | |
3049 | * shared buffer. | |
3050 | * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. | |
3051 | * Access: RW | |
3052 | */ | |
3053 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); | |
3054 | ||
3055 | /* reg_pbmc_buf_size | |
3056 | * The part of the packet buffer array is allocated for the specific buffer. | |
3057 | * Units are represented in cells. | |
3058 | * Access: RW | |
3059 | */ | |
3060 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); | |
3061 | ||
155f9de2 IS |
3062 | /* reg_pbmc_buf_xoff_threshold |
3063 | * Once the amount of data in the buffer goes above this value, device | |
3064 | * starts sending PFC frames for all priorities associated with the | |
3065 | * buffer. Units are represented in cells. Reserved in case of lossy | |
3066 | * buffer. | |
3067 | * Access: RW | |
3068 | * | |
3069 | * Note: In Spectrum, reserved for buffer[9]. | |
3070 | */ | |
3071 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, | |
3072 | 0x08, 0x04, false); | |
3073 | ||
3074 | /* reg_pbmc_buf_xon_threshold | |
3075 | * When the amount of data in the buffer goes below this value, device | |
3076 | * stops sending PFC frames for the priorities associated with the | |
3077 | * buffer. Units are represented in cells. Reserved in case of lossy | |
3078 | * buffer. | |
3079 | * Access: RW | |
3080 | * | |
3081 | * Note: In Spectrum, reserved for buffer[9]. | |
3082 | */ | |
3083 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, | |
3084 | 0x08, 0x04, false); | |
3085 | ||
e0594369 JP |
3086 | static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, |
3087 | u16 xoff_timer_value, u16 xoff_refresh) | |
3088 | { | |
3089 | MLXSW_REG_ZERO(pbmc, payload); | |
3090 | mlxsw_reg_pbmc_local_port_set(payload, local_port); | |
3091 | mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); | |
3092 | mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); | |
3093 | } | |
3094 | ||
3095 | static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, | |
3096 | int buf_index, | |
3097 | u16 size) | |
3098 | { | |
3099 | mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); | |
3100 | mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); | |
3101 | mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); | |
3102 | } | |
3103 | ||
155f9de2 IS |
3104 | static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, |
3105 | int buf_index, u16 size, | |
3106 | u16 threshold) | |
3107 | { | |
3108 | mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); | |
3109 | mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); | |
3110 | mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); | |
3111 | mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); | |
3112 | mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); | |
3113 | } | |
3114 | ||
4ec14b76 IS |
3115 | /* PSPA - Port Switch Partition Allocation |
3116 | * --------------------------------------- | |
3117 | * Controls the association of a port with a switch partition and enables | |
3118 | * configuring ports as stacking ports. | |
3119 | */ | |
3f0effd1 | 3120 | #define MLXSW_REG_PSPA_ID 0x500D |
4ec14b76 IS |
3121 | #define MLXSW_REG_PSPA_LEN 0x8 |
3122 | ||
21978dcf | 3123 | MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); |
4ec14b76 IS |
3124 | |
3125 | /* reg_pspa_swid | |
3126 | * Switch partition ID. | |
3127 | * Access: RW | |
3128 | */ | |
3129 | MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); | |
3130 | ||
3131 | /* reg_pspa_local_port | |
3132 | * Local port number. | |
3133 | * Access: Index | |
3134 | */ | |
3135 | MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); | |
3136 | ||
3137 | /* reg_pspa_sub_port | |
3138 | * Virtual port within the local port. Set to 0 when virtual ports are | |
3139 | * disabled on the local port. | |
3140 | * Access: Index | |
3141 | */ | |
3142 | MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); | |
3143 | ||
3144 | static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) | |
3145 | { | |
3146 | MLXSW_REG_ZERO(pspa, payload); | |
3147 | mlxsw_reg_pspa_swid_set(payload, swid); | |
3148 | mlxsw_reg_pspa_local_port_set(payload, local_port); | |
3149 | mlxsw_reg_pspa_sub_port_set(payload, 0); | |
3150 | } | |
3151 | ||
3152 | /* HTGT - Host Trap Group Table | |
3153 | * ---------------------------- | |
3154 | * Configures the properties for forwarding to CPU. | |
3155 | */ | |
3156 | #define MLXSW_REG_HTGT_ID 0x7002 | |
3157 | #define MLXSW_REG_HTGT_LEN 0x100 | |
3158 | ||
21978dcf | 3159 | MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); |
4ec14b76 IS |
3160 | |
3161 | /* reg_htgt_swid | |
3162 | * Switch partition ID. | |
3163 | * Access: Index | |
3164 | */ | |
3165 | MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); | |
3166 | ||
3167 | #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ | |
3168 | ||
3169 | /* reg_htgt_type | |
3170 | * CPU path type. | |
3171 | * Access: RW | |
3172 | */ | |
3173 | MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); | |
3174 | ||
801bd3de IS |
3175 | enum mlxsw_reg_htgt_trap_group { |
3176 | MLXSW_REG_HTGT_TRAP_GROUP_EMAD, | |
117b0dad NF |
3177 | MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, |
3178 | MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, | |
3179 | MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, | |
3180 | MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, | |
3181 | MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, | |
3182 | MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, | |
3183 | MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4, | |
3184 | MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, | |
3185 | MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, | |
3186 | MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS, | |
3187 | MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, | |
3188 | MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, | |
3189 | MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, | |
3190 | MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, | |
3191 | MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, | |
801bd3de | 3192 | }; |
4ec14b76 IS |
3193 | |
3194 | /* reg_htgt_trap_group | |
3195 | * Trap group number. User defined number specifying which trap groups | |
3196 | * should be forwarded to the CPU. The mapping between trap IDs and trap | |
3197 | * groups is configured using HPKT register. | |
3198 | * Access: Index | |
3199 | */ | |
3200 | MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); | |
3201 | ||
3202 | enum { | |
3203 | MLXSW_REG_HTGT_POLICER_DISABLE, | |
3204 | MLXSW_REG_HTGT_POLICER_ENABLE, | |
3205 | }; | |
3206 | ||
3207 | /* reg_htgt_pide | |
3208 | * Enable policer ID specified using 'pid' field. | |
3209 | * Access: RW | |
3210 | */ | |
3211 | MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); | |
3212 | ||
579c82e4 NF |
3213 | #define MLXSW_REG_HTGT_INVALID_POLICER 0xff |
3214 | ||
4ec14b76 IS |
3215 | /* reg_htgt_pid |
3216 | * Policer ID for the trap group. | |
3217 | * Access: RW | |
3218 | */ | |
3219 | MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); | |
3220 | ||
3221 | #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 | |
3222 | ||
3223 | /* reg_htgt_mirror_action | |
3224 | * Mirror action to use. | |
3225 | * 0 - Trap to CPU. | |
3226 | * 1 - Trap to CPU and mirror to a mirroring agent. | |
3227 | * 2 - Mirror to a mirroring agent and do not trap to CPU. | |
3228 | * Access: RW | |
3229 | * | |
3230 | * Note: Mirroring to a mirroring agent is only supported in Spectrum. | |
3231 | */ | |
3232 | MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); | |
3233 | ||
3234 | /* reg_htgt_mirroring_agent | |
3235 | * Mirroring agent. | |
3236 | * Access: RW | |
3237 | */ | |
3238 | MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); | |
3239 | ||
579c82e4 NF |
3240 | #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 |
3241 | ||
4ec14b76 IS |
3242 | /* reg_htgt_priority |
3243 | * Trap group priority. | |
3244 | * In case a packet matches multiple classification rules, the packet will | |
3245 | * only be trapped once, based on the trap ID associated with the group (via | |
3246 | * register HPKT) with the highest priority. | |
3247 | * Supported values are 0-7, with 7 represnting the highest priority. | |
3248 | * Access: RW | |
3249 | * | |
3250 | * Note: In SwitchX-2 this field is ignored and the priority value is replaced | |
3251 | * by the 'trap_group' field. | |
3252 | */ | |
3253 | MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); | |
3254 | ||
579c82e4 NF |
3255 | #define MLXSW_REG_HTGT_DEFAULT_TC 7 |
3256 | ||
4ec14b76 IS |
3257 | /* reg_htgt_local_path_cpu_tclass |
3258 | * CPU ingress traffic class for the trap group. | |
3259 | * Access: RW | |
3260 | */ | |
3261 | MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); | |
3262 | ||
579c82e4 NF |
3263 | enum mlxsw_reg_htgt_local_path_rdq { |
3264 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, | |
3265 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, | |
3266 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, | |
3267 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, | |
3268 | }; | |
4ec14b76 IS |
3269 | /* reg_htgt_local_path_rdq |
3270 | * Receive descriptor queue (RDQ) to use for the trap group. | |
3271 | * Access: RW | |
3272 | */ | |
3273 | MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); | |
3274 | ||
579c82e4 NF |
3275 | static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, |
3276 | u8 priority, u8 tc) | |
4ec14b76 | 3277 | { |
4ec14b76 | 3278 | MLXSW_REG_ZERO(htgt, payload); |
579c82e4 NF |
3279 | |
3280 | if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { | |
3281 | mlxsw_reg_htgt_pide_set(payload, | |
3282 | MLXSW_REG_HTGT_POLICER_DISABLE); | |
3283 | } else { | |
3284 | mlxsw_reg_htgt_pide_set(payload, | |
3285 | MLXSW_REG_HTGT_POLICER_ENABLE); | |
3286 | mlxsw_reg_htgt_pid_set(payload, policer_id); | |
4ec14b76 | 3287 | } |
579c82e4 | 3288 | |
4ec14b76 | 3289 | mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); |
801bd3de | 3290 | mlxsw_reg_htgt_trap_group_set(payload, group); |
4ec14b76 IS |
3291 | mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); |
3292 | mlxsw_reg_htgt_mirroring_agent_set(payload, 0); | |
579c82e4 NF |
3293 | mlxsw_reg_htgt_priority_set(payload, priority); |
3294 | mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); | |
3295 | mlxsw_reg_htgt_local_path_rdq_set(payload, group); | |
4ec14b76 IS |
3296 | } |
3297 | ||
3298 | /* HPKT - Host Packet Trap | |
3299 | * ----------------------- | |
3300 | * Configures trap IDs inside trap groups. | |
3301 | */ | |
3302 | #define MLXSW_REG_HPKT_ID 0x7003 | |
3303 | #define MLXSW_REG_HPKT_LEN 0x10 | |
3304 | ||
21978dcf | 3305 | MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); |
4ec14b76 IS |
3306 | |
3307 | enum { | |
3308 | MLXSW_REG_HPKT_ACK_NOT_REQUIRED, | |
3309 | MLXSW_REG_HPKT_ACK_REQUIRED, | |
3310 | }; | |
3311 | ||
3312 | /* reg_hpkt_ack | |
3313 | * Require acknowledgements from the host for events. | |
3314 | * If set, then the device will wait for the event it sent to be acknowledged | |
3315 | * by the host. This option is only relevant for event trap IDs. | |
3316 | * Access: RW | |
3317 | * | |
3318 | * Note: Currently not supported by firmware. | |
3319 | */ | |
3320 | MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); | |
3321 | ||
3322 | enum mlxsw_reg_hpkt_action { | |
3323 | MLXSW_REG_HPKT_ACTION_FORWARD, | |
3324 | MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, | |
3325 | MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, | |
3326 | MLXSW_REG_HPKT_ACTION_DISCARD, | |
3327 | MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, | |
3328 | MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, | |
3329 | }; | |
3330 | ||
3331 | /* reg_hpkt_action | |
3332 | * Action to perform on packet when trapped. | |
3333 | * 0 - No action. Forward to CPU based on switching rules. | |
3334 | * 1 - Trap to CPU (CPU receives sole copy). | |
3335 | * 2 - Mirror to CPU (CPU receives a replica of the packet). | |
3336 | * 3 - Discard. | |
3337 | * 4 - Soft discard (allow other traps to act on the packet). | |
3338 | * 5 - Trap and soft discard (allow other traps to overwrite this trap). | |
3339 | * Access: RW | |
3340 | * | |
3341 | * Note: Must be set to 0 (forward) for event trap IDs, as they are already | |
3342 | * addressed to the CPU. | |
3343 | */ | |
3344 | MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); | |
3345 | ||
3346 | /* reg_hpkt_trap_group | |
3347 | * Trap group to associate the trap with. | |
3348 | * Access: RW | |
3349 | */ | |
3350 | MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); | |
3351 | ||
3352 | /* reg_hpkt_trap_id | |
3353 | * Trap ID. | |
3354 | * Access: Index | |
3355 | * | |
3356 | * Note: A trap ID can only be associated with a single trap group. The device | |
3357 | * will associate the trap ID with the last trap group configured. | |
3358 | */ | |
3359 | MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); | |
3360 | ||
3361 | enum { | |
3362 | MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, | |
3363 | MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, | |
3364 | MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, | |
3365 | }; | |
3366 | ||
3367 | /* reg_hpkt_ctrl | |
3368 | * Configure dedicated buffer resources for control packets. | |
d570b7ee | 3369 | * Ignored by SwitchX-2. |
4ec14b76 IS |
3370 | * 0 - Keep factory defaults. |
3371 | * 1 - Do not use control buffer for this trap ID. | |
3372 | * 2 - Use control buffer for this trap ID. | |
3373 | * Access: RW | |
3374 | */ | |
3375 | MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); | |
3376 | ||
d570b7ee NF |
3377 | static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, |
3378 | enum mlxsw_reg_htgt_trap_group trap_group, | |
3379 | bool is_ctrl) | |
4ec14b76 IS |
3380 | { |
3381 | MLXSW_REG_ZERO(hpkt, payload); | |
3382 | mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); | |
3383 | mlxsw_reg_hpkt_action_set(payload, action); | |
3384 | mlxsw_reg_hpkt_trap_group_set(payload, trap_group); | |
3385 | mlxsw_reg_hpkt_trap_id_set(payload, trap_id); | |
d570b7ee NF |
3386 | mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? |
3387 | MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : | |
3388 | MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); | |
4ec14b76 IS |
3389 | } |
3390 | ||
69c407aa IS |
3391 | /* RGCR - Router General Configuration Register |
3392 | * -------------------------------------------- | |
3393 | * The register is used for setting up the router configuration. | |
3394 | */ | |
3395 | #define MLXSW_REG_RGCR_ID 0x8001 | |
3396 | #define MLXSW_REG_RGCR_LEN 0x28 | |
3397 | ||
21978dcf | 3398 | MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); |
69c407aa IS |
3399 | |
3400 | /* reg_rgcr_ipv4_en | |
3401 | * IPv4 router enable. | |
3402 | * Access: RW | |
3403 | */ | |
3404 | MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); | |
3405 | ||
3406 | /* reg_rgcr_ipv6_en | |
3407 | * IPv6 router enable. | |
3408 | * Access: RW | |
3409 | */ | |
3410 | MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); | |
3411 | ||
3412 | /* reg_rgcr_max_router_interfaces | |
3413 | * Defines the maximum number of active router interfaces for all virtual | |
3414 | * routers. | |
3415 | * Access: RW | |
3416 | */ | |
3417 | MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); | |
3418 | ||
3419 | /* reg_rgcr_usp | |
3420 | * Update switch priority and packet color. | |
3421 | * 0 - Preserve the value of Switch Priority and packet color. | |
3422 | * 1 - Recalculate the value of Switch Priority and packet color. | |
3423 | * Access: RW | |
3424 | * | |
3425 | * Note: Not supported by SwitchX and SwitchX-2. | |
3426 | */ | |
3427 | MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); | |
3428 | ||
3429 | /* reg_rgcr_pcp_rw | |
3430 | * Indicates how to handle the pcp_rewrite_en value: | |
3431 | * 0 - Preserve the value of pcp_rewrite_en. | |
3432 | * 2 - Disable PCP rewrite. | |
3433 | * 3 - Enable PCP rewrite. | |
3434 | * Access: RW | |
3435 | * | |
3436 | * Note: Not supported by SwitchX and SwitchX-2. | |
3437 | */ | |
3438 | MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); | |
3439 | ||
3440 | /* reg_rgcr_activity_dis | |
3441 | * Activity disable: | |
3442 | * 0 - Activity will be set when an entry is hit (default). | |
3443 | * 1 - Activity will not be set when an entry is hit. | |
3444 | * | |
3445 | * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry | |
3446 | * (RALUE). | |
3447 | * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host | |
3448 | * Entry (RAUHT). | |
3449 | * Bits 2:7 are reserved. | |
3450 | * Access: RW | |
3451 | * | |
3452 | * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. | |
3453 | */ | |
3454 | MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); | |
3455 | ||
3456 | static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en) | |
3457 | { | |
3458 | MLXSW_REG_ZERO(rgcr, payload); | |
3459 | mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); | |
3460 | } | |
3461 | ||
3dc26689 IS |
3462 | /* RITR - Router Interface Table Register |
3463 | * -------------------------------------- | |
3464 | * The register is used to configure the router interface table. | |
3465 | */ | |
3466 | #define MLXSW_REG_RITR_ID 0x8002 | |
3467 | #define MLXSW_REG_RITR_LEN 0x40 | |
3468 | ||
21978dcf | 3469 | MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); |
3dc26689 IS |
3470 | |
3471 | /* reg_ritr_enable | |
3472 | * Enables routing on the router interface. | |
3473 | * Access: RW | |
3474 | */ | |
3475 | MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); | |
3476 | ||
3477 | /* reg_ritr_ipv4 | |
3478 | * IPv4 routing enable. Enables routing of IPv4 traffic on the router | |
3479 | * interface. | |
3480 | * Access: RW | |
3481 | */ | |
3482 | MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); | |
3483 | ||
3484 | /* reg_ritr_ipv6 | |
3485 | * IPv6 routing enable. Enables routing of IPv6 traffic on the router | |
3486 | * interface. | |
3487 | * Access: RW | |
3488 | */ | |
3489 | MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); | |
3490 | ||
3491 | enum mlxsw_reg_ritr_if_type { | |
3492 | MLXSW_REG_RITR_VLAN_IF, | |
3493 | MLXSW_REG_RITR_FID_IF, | |
3494 | MLXSW_REG_RITR_SP_IF, | |
3495 | }; | |
3496 | ||
3497 | /* reg_ritr_type | |
3498 | * Router interface type. | |
3499 | * 0 - VLAN interface. | |
3500 | * 1 - FID interface. | |
3501 | * 2 - Sub-port interface. | |
3502 | * Access: RW | |
3503 | */ | |
3504 | MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); | |
3505 | ||
3506 | enum { | |
3507 | MLXSW_REG_RITR_RIF_CREATE, | |
3508 | MLXSW_REG_RITR_RIF_DEL, | |
3509 | }; | |
3510 | ||
3511 | /* reg_ritr_op | |
3512 | * Opcode: | |
3513 | * 0 - Create or edit RIF. | |
3514 | * 1 - Delete RIF. | |
3515 | * Reserved for SwitchX-2. For Spectrum, editing of interface properties | |
3516 | * is not supported. An interface must be deleted and re-created in order | |
3517 | * to update properties. | |
3518 | * Access: WO | |
3519 | */ | |
3520 | MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); | |
3521 | ||
3522 | /* reg_ritr_rif | |
3523 | * Router interface index. A pointer to the Router Interface Table. | |
3524 | * Access: Index | |
3525 | */ | |
3526 | MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); | |
3527 | ||
3528 | /* reg_ritr_ipv4_fe | |
3529 | * IPv4 Forwarding Enable. | |
3530 | * Enables routing of IPv4 traffic on the router interface. When disabled, | |
3531 | * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. | |
3532 | * Not supported in SwitchX-2. | |
3533 | * Access: RW | |
3534 | */ | |
3535 | MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); | |
3536 | ||
3537 | /* reg_ritr_ipv6_fe | |
3538 | * IPv6 Forwarding Enable. | |
3539 | * Enables routing of IPv6 traffic on the router interface. When disabled, | |
3540 | * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. | |
3541 | * Not supported in SwitchX-2. | |
3542 | * Access: RW | |
3543 | */ | |
3544 | MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); | |
3545 | ||
a94a614f IS |
3546 | /* reg_ritr_lb_en |
3547 | * Loop-back filter enable for unicast packets. | |
3548 | * If the flag is set then loop-back filter for unicast packets is | |
3549 | * implemented on the RIF. Multicast packets are always subject to | |
3550 | * loop-back filtering. | |
3551 | * Access: RW | |
3552 | */ | |
3553 | MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); | |
3554 | ||
3dc26689 IS |
3555 | /* reg_ritr_virtual_router |
3556 | * Virtual router ID associated with the router interface. | |
3557 | * Access: RW | |
3558 | */ | |
3559 | MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); | |
3560 | ||
3561 | /* reg_ritr_mtu | |
3562 | * Router interface MTU. | |
3563 | * Access: RW | |
3564 | */ | |
3565 | MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); | |
3566 | ||
3567 | /* reg_ritr_if_swid | |
3568 | * Switch partition ID. | |
3569 | * Access: RW | |
3570 | */ | |
3571 | MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); | |
3572 | ||
3573 | /* reg_ritr_if_mac | |
3574 | * Router interface MAC address. | |
3575 | * In Spectrum, all MAC addresses must have the same 38 MSBits. | |
3576 | * Access: RW | |
3577 | */ | |
3578 | MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); | |
3579 | ||
3580 | /* VLAN Interface */ | |
3581 | ||
3582 | /* reg_ritr_vlan_if_vid | |
3583 | * VLAN ID. | |
3584 | * Access: RW | |
3585 | */ | |
3586 | MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); | |
3587 | ||
3588 | /* FID Interface */ | |
3589 | ||
3590 | /* reg_ritr_fid_if_fid | |
3591 | * Filtering ID. Used to connect a bridge to the router. Only FIDs from | |
3592 | * the vFID range are supported. | |
3593 | * Access: RW | |
3594 | */ | |
3595 | MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); | |
3596 | ||
3597 | static inline void mlxsw_reg_ritr_fid_set(char *payload, | |
3598 | enum mlxsw_reg_ritr_if_type rif_type, | |
3599 | u16 fid) | |
3600 | { | |
3601 | if (rif_type == MLXSW_REG_RITR_FID_IF) | |
3602 | mlxsw_reg_ritr_fid_if_fid_set(payload, fid); | |
3603 | else | |
3604 | mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); | |
3605 | } | |
3606 | ||
3607 | /* Sub-port Interface */ | |
3608 | ||
3609 | /* reg_ritr_sp_if_lag | |
3610 | * LAG indication. When this bit is set the system_port field holds the | |
3611 | * LAG identifier. | |
3612 | * Access: RW | |
3613 | */ | |
3614 | MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); | |
3615 | ||
3616 | /* reg_ritr_sp_system_port | |
3617 | * Port unique indentifier. When lag bit is set, this field holds the | |
3618 | * lag_id in bits 0:9. | |
3619 | * Access: RW | |
3620 | */ | |
3621 | MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); | |
3622 | ||
3623 | /* reg_ritr_sp_if_vid | |
3624 | * VLAN ID. | |
3625 | * Access: RW | |
3626 | */ | |
3627 | MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); | |
3628 | ||
3629 | static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) | |
3630 | { | |
3631 | MLXSW_REG_ZERO(ritr, payload); | |
3632 | mlxsw_reg_ritr_rif_set(payload, rif); | |
3633 | } | |
3634 | ||
3635 | static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, | |
3636 | u16 system_port, u16 vid) | |
3637 | { | |
3638 | mlxsw_reg_ritr_sp_if_lag_set(payload, lag); | |
3639 | mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); | |
3640 | mlxsw_reg_ritr_sp_if_vid_set(payload, vid); | |
3641 | } | |
3642 | ||
3643 | static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, | |
3644 | enum mlxsw_reg_ritr_if_type type, | |
3645 | u16 rif, u16 mtu, const char *mac) | |
3646 | { | |
3647 | bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; | |
3648 | ||
3649 | MLXSW_REG_ZERO(ritr, payload); | |
3650 | mlxsw_reg_ritr_enable_set(payload, enable); | |
3651 | mlxsw_reg_ritr_ipv4_set(payload, 1); | |
3652 | mlxsw_reg_ritr_type_set(payload, type); | |
3653 | mlxsw_reg_ritr_op_set(payload, op); | |
3654 | mlxsw_reg_ritr_rif_set(payload, rif); | |
3655 | mlxsw_reg_ritr_ipv4_fe_set(payload, 1); | |
a94a614f | 3656 | mlxsw_reg_ritr_lb_en_set(payload, 1); |
3dc26689 IS |
3657 | mlxsw_reg_ritr_mtu_set(payload, mtu); |
3658 | mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); | |
3659 | } | |
3660 | ||
089f9816 YG |
3661 | /* RATR - Router Adjacency Table Register |
3662 | * -------------------------------------- | |
3663 | * The RATR register is used to configure the Router Adjacency (next-hop) | |
3664 | * Table. | |
3665 | */ | |
3666 | #define MLXSW_REG_RATR_ID 0x8008 | |
3667 | #define MLXSW_REG_RATR_LEN 0x2C | |
3668 | ||
21978dcf | 3669 | MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); |
089f9816 YG |
3670 | |
3671 | enum mlxsw_reg_ratr_op { | |
3672 | /* Read */ | |
3673 | MLXSW_REG_RATR_OP_QUERY_READ = 0, | |
3674 | /* Read and clear activity */ | |
3675 | MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, | |
3676 | /* Write Adjacency entry */ | |
3677 | MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, | |
3678 | /* Write Adjacency entry only if the activity is cleared. | |
3679 | * The write may not succeed if the activity is set. There is not | |
3680 | * direct feedback if the write has succeeded or not, however | |
3681 | * the get will reveal the actual entry (SW can compare the get | |
3682 | * response to the set command). | |
3683 | */ | |
3684 | MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, | |
3685 | }; | |
3686 | ||
3687 | /* reg_ratr_op | |
3688 | * Note that Write operation may also be used for updating | |
3689 | * counter_set_type and counter_index. In this case all other | |
3690 | * fields must not be updated. | |
3691 | * Access: OP | |
3692 | */ | |
3693 | MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); | |
3694 | ||
3695 | /* reg_ratr_v | |
3696 | * Valid bit. Indicates if the adjacency entry is valid. | |
3697 | * Note: the device may need some time before reusing an invalidated | |
3698 | * entry. During this time the entry can not be reused. It is | |
3699 | * recommended to use another entry before reusing an invalidated | |
3700 | * entry (e.g. software can put it at the end of the list for | |
3701 | * reusing). Trying to access an invalidated entry not yet cleared | |
3702 | * by the device results with failure indicating "Try Again" status. | |
3703 | * When valid is '0' then egress_router_interface,trap_action, | |
3704 | * adjacency_parameters and counters are reserved | |
3705 | * Access: RW | |
3706 | */ | |
3707 | MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); | |
3708 | ||
3709 | /* reg_ratr_a | |
3710 | * Activity. Set for new entries. Set if a packet lookup has hit on | |
3711 | * the specific entry. To clear the a bit, use "clear activity". | |
3712 | * Access: RO | |
3713 | */ | |
3714 | MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); | |
3715 | ||
3716 | /* reg_ratr_adjacency_index_low | |
3717 | * Bits 15:0 of index into the adjacency table. | |
3718 | * For SwitchX and SwitchX-2, the adjacency table is linear and | |
3719 | * used for adjacency entries only. | |
3720 | * For Spectrum, the index is to the KVD linear. | |
3721 | * Access: Index | |
3722 | */ | |
3723 | MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); | |
3724 | ||
3725 | /* reg_ratr_egress_router_interface | |
3726 | * Range is 0 .. cap_max_router_interfaces - 1 | |
3727 | * Access: RW | |
3728 | */ | |
3729 | MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); | |
3730 | ||
3731 | enum mlxsw_reg_ratr_trap_action { | |
3732 | MLXSW_REG_RATR_TRAP_ACTION_NOP, | |
3733 | MLXSW_REG_RATR_TRAP_ACTION_TRAP, | |
3734 | MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, | |
3735 | MLXSW_REG_RATR_TRAP_ACTION_MIRROR, | |
3736 | MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, | |
3737 | }; | |
3738 | ||
3739 | /* reg_ratr_trap_action | |
3740 | * see mlxsw_reg_ratr_trap_action | |
3741 | * Access: RW | |
3742 | */ | |
3743 | MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); | |
3744 | ||
3745 | enum mlxsw_reg_ratr_trap_id { | |
3746 | MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0, | |
3747 | MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1, | |
3748 | }; | |
3749 | ||
3750 | /* reg_ratr_adjacency_index_high | |
3751 | * Bits 23:16 of the adjacency_index. | |
3752 | * Access: Index | |
3753 | */ | |
3754 | MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); | |
3755 | ||
3756 | /* reg_ratr_trap_id | |
3757 | * Trap ID to be reported to CPU. | |
3758 | * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. | |
3759 | * For trap_action of NOP, MIRROR and DISCARD_ERROR | |
3760 | * Access: RW | |
3761 | */ | |
3762 | MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); | |
3763 | ||
3764 | /* reg_ratr_eth_destination_mac | |
3765 | * MAC address of the destination next-hop. | |
3766 | * Access: RW | |
3767 | */ | |
3768 | MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); | |
3769 | ||
3770 | static inline void | |
3771 | mlxsw_reg_ratr_pack(char *payload, | |
3772 | enum mlxsw_reg_ratr_op op, bool valid, | |
3773 | u32 adjacency_index, u16 egress_rif) | |
3774 | { | |
3775 | MLXSW_REG_ZERO(ratr, payload); | |
3776 | mlxsw_reg_ratr_op_set(payload, op); | |
3777 | mlxsw_reg_ratr_v_set(payload, valid); | |
3778 | mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); | |
3779 | mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); | |
3780 | mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); | |
3781 | } | |
3782 | ||
3783 | static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, | |
3784 | const char *dest_mac) | |
3785 | { | |
3786 | mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); | |
3787 | } | |
3788 | ||
6f9fc3ce JP |
3789 | /* RALTA - Router Algorithmic LPM Tree Allocation Register |
3790 | * ------------------------------------------------------- | |
3791 | * RALTA is used to allocate the LPM trees of the SHSPM method. | |
3792 | */ | |
3793 | #define MLXSW_REG_RALTA_ID 0x8010 | |
3794 | #define MLXSW_REG_RALTA_LEN 0x04 | |
3795 | ||
21978dcf | 3796 | MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); |
6f9fc3ce JP |
3797 | |
3798 | /* reg_ralta_op | |
3799 | * opcode (valid for Write, must be 0 on Read) | |
3800 | * 0 - allocate a tree | |
3801 | * 1 - deallocate a tree | |
3802 | * Access: OP | |
3803 | */ | |
3804 | MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); | |
3805 | ||
3806 | enum mlxsw_reg_ralxx_protocol { | |
3807 | MLXSW_REG_RALXX_PROTOCOL_IPV4, | |
3808 | MLXSW_REG_RALXX_PROTOCOL_IPV6, | |
3809 | }; | |
3810 | ||
3811 | /* reg_ralta_protocol | |
3812 | * Protocol. | |
3813 | * Deallocation opcode: Reserved. | |
3814 | * Access: RW | |
3815 | */ | |
3816 | MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); | |
3817 | ||
3818 | /* reg_ralta_tree_id | |
3819 | * An identifier (numbered from 1..cap_shspm_max_trees-1) representing | |
3820 | * the tree identifier (managed by software). | |
3821 | * Note that tree_id 0 is allocated for a default-route tree. | |
3822 | * Access: Index | |
3823 | */ | |
3824 | MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); | |
3825 | ||
3826 | static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, | |
3827 | enum mlxsw_reg_ralxx_protocol protocol, | |
3828 | u8 tree_id) | |
3829 | { | |
3830 | MLXSW_REG_ZERO(ralta, payload); | |
3831 | mlxsw_reg_ralta_op_set(payload, !alloc); | |
3832 | mlxsw_reg_ralta_protocol_set(payload, protocol); | |
3833 | mlxsw_reg_ralta_tree_id_set(payload, tree_id); | |
3834 | } | |
3835 | ||
a9823359 JP |
3836 | /* RALST - Router Algorithmic LPM Structure Tree Register |
3837 | * ------------------------------------------------------ | |
3838 | * RALST is used to set and query the structure of an LPM tree. | |
3839 | * The structure of the tree must be sorted as a sorted binary tree, while | |
3840 | * each node is a bin that is tagged as the length of the prefixes the lookup | |
3841 | * will refer to. Therefore, bin X refers to a set of entries with prefixes | |
3842 | * of X bits to match with the destination address. The bin 0 indicates | |
3843 | * the default action, when there is no match of any prefix. | |
3844 | */ | |
3845 | #define MLXSW_REG_RALST_ID 0x8011 | |
3846 | #define MLXSW_REG_RALST_LEN 0x104 | |
3847 | ||
21978dcf | 3848 | MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); |
a9823359 JP |
3849 | |
3850 | /* reg_ralst_root_bin | |
3851 | * The bin number of the root bin. | |
3852 | * 0<root_bin=<(length of IP address) | |
3853 | * For a default-route tree configure 0xff | |
3854 | * Access: RW | |
3855 | */ | |
3856 | MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); | |
3857 | ||
3858 | /* reg_ralst_tree_id | |
3859 | * Tree identifier numbered from 1..(cap_shspm_max_trees-1). | |
3860 | * Access: Index | |
3861 | */ | |
3862 | MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); | |
3863 | ||
3864 | #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff | |
3865 | #define MLXSW_REG_RALST_BIN_OFFSET 0x04 | |
3866 | #define MLXSW_REG_RALST_BIN_COUNT 128 | |
3867 | ||
3868 | /* reg_ralst_left_child_bin | |
3869 | * Holding the children of the bin according to the stored tree's structure. | |
3870 | * For trees composed of less than 4 blocks, the bins in excess are reserved. | |
3871 | * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff | |
3872 | * Access: RW | |
3873 | */ | |
3874 | MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); | |
3875 | ||
3876 | /* reg_ralst_right_child_bin | |
3877 | * Holding the children of the bin according to the stored tree's structure. | |
3878 | * For trees composed of less than 4 blocks, the bins in excess are reserved. | |
3879 | * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff | |
3880 | * Access: RW | |
3881 | */ | |
3882 | MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, | |
3883 | false); | |
3884 | ||
3885 | static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) | |
3886 | { | |
3887 | MLXSW_REG_ZERO(ralst, payload); | |
3888 | ||
3889 | /* Initialize all bins to have no left or right child */ | |
3890 | memset(payload + MLXSW_REG_RALST_BIN_OFFSET, | |
3891 | MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); | |
3892 | ||
3893 | mlxsw_reg_ralst_root_bin_set(payload, root_bin); | |
3894 | mlxsw_reg_ralst_tree_id_set(payload, tree_id); | |
3895 | } | |
3896 | ||
3897 | static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, | |
3898 | u8 left_child_bin, | |
3899 | u8 right_child_bin) | |
3900 | { | |
3901 | int bin_index = bin_number - 1; | |
3902 | ||
3903 | mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); | |
3904 | mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, | |
3905 | right_child_bin); | |
3906 | } | |
3907 | ||
20ae4053 JP |
3908 | /* RALTB - Router Algorithmic LPM Tree Binding Register |
3909 | * ---------------------------------------------------- | |
3910 | * RALTB is used to bind virtual router and protocol to an allocated LPM tree. | |
3911 | */ | |
3912 | #define MLXSW_REG_RALTB_ID 0x8012 | |
3913 | #define MLXSW_REG_RALTB_LEN 0x04 | |
3914 | ||
21978dcf | 3915 | MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); |
20ae4053 JP |
3916 | |
3917 | /* reg_raltb_virtual_router | |
3918 | * Virtual Router ID | |
3919 | * Range is 0..cap_max_virtual_routers-1 | |
3920 | * Access: Index | |
3921 | */ | |
3922 | MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); | |
3923 | ||
3924 | /* reg_raltb_protocol | |
3925 | * Protocol. | |
3926 | * Access: Index | |
3927 | */ | |
3928 | MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); | |
3929 | ||
3930 | /* reg_raltb_tree_id | |
3931 | * Tree to be used for the {virtual_router, protocol} | |
3932 | * Tree identifier numbered from 1..(cap_shspm_max_trees-1). | |
3933 | * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. | |
3934 | * Access: RW | |
3935 | */ | |
3936 | MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); | |
3937 | ||
3938 | static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, | |
3939 | enum mlxsw_reg_ralxx_protocol protocol, | |
3940 | u8 tree_id) | |
3941 | { | |
3942 | MLXSW_REG_ZERO(raltb, payload); | |
3943 | mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); | |
3944 | mlxsw_reg_raltb_protocol_set(payload, protocol); | |
3945 | mlxsw_reg_raltb_tree_id_set(payload, tree_id); | |
3946 | } | |
3947 | ||
d5a1c749 JP |
3948 | /* RALUE - Router Algorithmic LPM Unicast Entry Register |
3949 | * ----------------------------------------------------- | |
3950 | * RALUE is used to configure and query LPM entries that serve | |
3951 | * the Unicast protocols. | |
3952 | */ | |
3953 | #define MLXSW_REG_RALUE_ID 0x8013 | |
3954 | #define MLXSW_REG_RALUE_LEN 0x38 | |
3955 | ||
21978dcf | 3956 | MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); |
d5a1c749 JP |
3957 | |
3958 | /* reg_ralue_protocol | |
3959 | * Protocol. | |
3960 | * Access: Index | |
3961 | */ | |
3962 | MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); | |
3963 | ||
3964 | enum mlxsw_reg_ralue_op { | |
3965 | /* Read operation. If entry doesn't exist, the operation fails. */ | |
3966 | MLXSW_REG_RALUE_OP_QUERY_READ = 0, | |
3967 | /* Clear on read operation. Used to read entry and | |
3968 | * clear Activity bit. | |
3969 | */ | |
3970 | MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, | |
3971 | /* Write operation. Used to write a new entry to the table. All RW | |
3972 | * fields are written for new entry. Activity bit is set | |
3973 | * for new entries. | |
3974 | */ | |
3975 | MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, | |
3976 | /* Update operation. Used to update an existing route entry and | |
3977 | * only update the RW fields that are detailed in the field | |
3978 | * op_u_mask. If entry doesn't exist, the operation fails. | |
3979 | */ | |
3980 | MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, | |
3981 | /* Clear activity. The Activity bit (the field a) is cleared | |
3982 | * for the entry. | |
3983 | */ | |
3984 | MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, | |
3985 | /* Delete operation. Used to delete an existing entry. If entry | |
3986 | * doesn't exist, the operation fails. | |
3987 | */ | |
3988 | MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, | |
3989 | }; | |
3990 | ||
3991 | /* reg_ralue_op | |
3992 | * Operation. | |
3993 | * Access: OP | |
3994 | */ | |
3995 | MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); | |
3996 | ||
3997 | /* reg_ralue_a | |
3998 | * Activity. Set for new entries. Set if a packet lookup has hit on the | |
3999 | * specific entry, only if the entry is a route. To clear the a bit, use | |
4000 | * "clear activity" op. | |
4001 | * Enabled by activity_dis in RGCR | |
4002 | * Access: RO | |
4003 | */ | |
4004 | MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); | |
4005 | ||
4006 | /* reg_ralue_virtual_router | |
4007 | * Virtual Router ID | |
4008 | * Range is 0..cap_max_virtual_routers-1 | |
4009 | * Access: Index | |
4010 | */ | |
4011 | MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); | |
4012 | ||
4013 | #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) | |
4014 | #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) | |
4015 | #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) | |
4016 | ||
4017 | /* reg_ralue_op_u_mask | |
4018 | * opcode update mask. | |
4019 | * On read operation, this field is reserved. | |
4020 | * This field is valid for update opcode, otherwise - reserved. | |
4021 | * This field is a bitmask of the fields that should be updated. | |
4022 | * Access: WO | |
4023 | */ | |
4024 | MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); | |
4025 | ||
4026 | /* reg_ralue_prefix_len | |
4027 | * Number of bits in the prefix of the LPM route. | |
4028 | * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes | |
4029 | * two entries in the physical HW table. | |
4030 | * Access: Index | |
4031 | */ | |
4032 | MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); | |
4033 | ||
4034 | /* reg_ralue_dip* | |
4035 | * The prefix of the route or of the marker that the object of the LPM | |
4036 | * is compared with. The most significant bits of the dip are the prefix. | |
4037 | * The list significant bits must be '0' if the prefix_len is smaller | |
4038 | * than 128 for IPv6 or smaller than 32 for IPv4. | |
4039 | * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. | |
4040 | * Access: Index | |
4041 | */ | |
4042 | MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); | |
4043 | ||
4044 | enum mlxsw_reg_ralue_entry_type { | |
4045 | MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, | |
4046 | MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, | |
4047 | MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, | |
4048 | }; | |
4049 | ||
4050 | /* reg_ralue_entry_type | |
4051 | * Entry type. | |
4052 | * Note - for Marker entries, the action_type and action fields are reserved. | |
4053 | * Access: RW | |
4054 | */ | |
4055 | MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); | |
4056 | ||
4057 | /* reg_ralue_bmp_len | |
4058 | * The best match prefix length in the case that there is no match for | |
4059 | * longer prefixes. | |
4060 | * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len | |
4061 | * Note for any update operation with entry_type modification this | |
4062 | * field must be set. | |
4063 | * Access: RW | |
4064 | */ | |
4065 | MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); | |
4066 | ||
4067 | enum mlxsw_reg_ralue_action_type { | |
4068 | MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, | |
4069 | MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, | |
4070 | MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, | |
4071 | }; | |
4072 | ||
4073 | /* reg_ralue_action_type | |
4074 | * Action Type | |
4075 | * Indicates how the IP address is connected. | |
4076 | * It can be connected to a local subnet through local_erif or can be | |
4077 | * on a remote subnet connected through a next-hop router, | |
4078 | * or transmitted to the CPU. | |
4079 | * Reserved when entry_type = MARKER_ENTRY | |
4080 | * Access: RW | |
4081 | */ | |
4082 | MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); | |
4083 | ||
4084 | enum mlxsw_reg_ralue_trap_action { | |
4085 | MLXSW_REG_RALUE_TRAP_ACTION_NOP, | |
4086 | MLXSW_REG_RALUE_TRAP_ACTION_TRAP, | |
4087 | MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, | |
4088 | MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, | |
4089 | MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, | |
4090 | }; | |
4091 | ||
4092 | /* reg_ralue_trap_action | |
4093 | * Trap action. | |
4094 | * For IP2ME action, only NOP and MIRROR are possible. | |
4095 | * Access: RW | |
4096 | */ | |
4097 | MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); | |
4098 | ||
4099 | /* reg_ralue_trap_id | |
4100 | * Trap ID to be reported to CPU. | |
4101 | * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. | |
4102 | * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. | |
4103 | * Access: RW | |
4104 | */ | |
4105 | MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); | |
4106 | ||
4107 | /* reg_ralue_adjacency_index | |
4108 | * Points to the first entry of the group-based ECMP. | |
4109 | * Only relevant in case of REMOTE action. | |
4110 | * Access: RW | |
4111 | */ | |
4112 | MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); | |
4113 | ||
4114 | /* reg_ralue_ecmp_size | |
4115 | * Amount of sequential entries starting | |
4116 | * from the adjacency_index (the number of ECMPs). | |
4117 | * The valid range is 1-64, 512, 1024, 2048 and 4096. | |
4118 | * Reserved when trap_action is TRAP or DISCARD_ERROR. | |
4119 | * Only relevant in case of REMOTE action. | |
4120 | * Access: RW | |
4121 | */ | |
4122 | MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); | |
4123 | ||
4124 | /* reg_ralue_local_erif | |
4125 | * Egress Router Interface. | |
4126 | * Only relevant in case of LOCAL action. | |
4127 | * Access: RW | |
4128 | */ | |
4129 | MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); | |
4130 | ||
4131 | /* reg_ralue_v | |
4132 | * Valid bit for the tunnel_ptr field. | |
4133 | * If valid = 0 then trap to CPU as IP2ME trap ID. | |
4134 | * If valid = 1 and the packet format allows NVE or IPinIP tunnel | |
4135 | * decapsulation then tunnel decapsulation is done. | |
4136 | * If valid = 1 and packet format does not allow NVE or IPinIP tunnel | |
4137 | * decapsulation then trap as IP2ME trap ID. | |
4138 | * Only relevant in case of IP2ME action. | |
4139 | * Access: RW | |
4140 | */ | |
4141 | MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1); | |
4142 | ||
4143 | /* reg_ralue_tunnel_ptr | |
4144 | * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. | |
4145 | * For Spectrum, pointer to KVD Linear. | |
4146 | * Only relevant in case of IP2ME action. | |
4147 | * Access: RW | |
4148 | */ | |
4149 | MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24); | |
4150 | ||
4151 | static inline void mlxsw_reg_ralue_pack(char *payload, | |
4152 | enum mlxsw_reg_ralxx_protocol protocol, | |
4153 | enum mlxsw_reg_ralue_op op, | |
4154 | u16 virtual_router, u8 prefix_len) | |
4155 | { | |
4156 | MLXSW_REG_ZERO(ralue, payload); | |
4157 | mlxsw_reg_ralue_protocol_set(payload, protocol); | |
0e7df1a2 | 4158 | mlxsw_reg_ralue_op_set(payload, op); |
d5a1c749 JP |
4159 | mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); |
4160 | mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); | |
4161 | mlxsw_reg_ralue_entry_type_set(payload, | |
4162 | MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); | |
4163 | mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); | |
4164 | } | |
4165 | ||
4166 | static inline void mlxsw_reg_ralue_pack4(char *payload, | |
4167 | enum mlxsw_reg_ralxx_protocol protocol, | |
4168 | enum mlxsw_reg_ralue_op op, | |
4169 | u16 virtual_router, u8 prefix_len, | |
4170 | u32 dip) | |
4171 | { | |
4172 | mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); | |
4173 | mlxsw_reg_ralue_dip4_set(payload, dip); | |
4174 | } | |
4175 | ||
4176 | static inline void | |
4177 | mlxsw_reg_ralue_act_remote_pack(char *payload, | |
4178 | enum mlxsw_reg_ralue_trap_action trap_action, | |
4179 | u16 trap_id, u32 adjacency_index, u16 ecmp_size) | |
4180 | { | |
4181 | mlxsw_reg_ralue_action_type_set(payload, | |
4182 | MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); | |
4183 | mlxsw_reg_ralue_trap_action_set(payload, trap_action); | |
4184 | mlxsw_reg_ralue_trap_id_set(payload, trap_id); | |
4185 | mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); | |
4186 | mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); | |
4187 | } | |
4188 | ||
4189 | static inline void | |
4190 | mlxsw_reg_ralue_act_local_pack(char *payload, | |
4191 | enum mlxsw_reg_ralue_trap_action trap_action, | |
4192 | u16 trap_id, u16 local_erif) | |
4193 | { | |
4194 | mlxsw_reg_ralue_action_type_set(payload, | |
4195 | MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); | |
4196 | mlxsw_reg_ralue_trap_action_set(payload, trap_action); | |
4197 | mlxsw_reg_ralue_trap_id_set(payload, trap_id); | |
4198 | mlxsw_reg_ralue_local_erif_set(payload, local_erif); | |
4199 | } | |
4200 | ||
4201 | static inline void | |
4202 | mlxsw_reg_ralue_act_ip2me_pack(char *payload) | |
4203 | { | |
4204 | mlxsw_reg_ralue_action_type_set(payload, | |
4205 | MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); | |
4206 | } | |
4207 | ||
4457b3df YG |
4208 | /* RAUHT - Router Algorithmic LPM Unicast Host Table Register |
4209 | * ---------------------------------------------------------- | |
4210 | * The RAUHT register is used to configure and query the Unicast Host table in | |
4211 | * devices that implement the Algorithmic LPM. | |
4212 | */ | |
4213 | #define MLXSW_REG_RAUHT_ID 0x8014 | |
4214 | #define MLXSW_REG_RAUHT_LEN 0x74 | |
4215 | ||
21978dcf | 4216 | MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); |
4457b3df YG |
4217 | |
4218 | enum mlxsw_reg_rauht_type { | |
4219 | MLXSW_REG_RAUHT_TYPE_IPV4, | |
4220 | MLXSW_REG_RAUHT_TYPE_IPV6, | |
4221 | }; | |
4222 | ||
4223 | /* reg_rauht_type | |
4224 | * Access: Index | |
4225 | */ | |
4226 | MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); | |
4227 | ||
4228 | enum mlxsw_reg_rauht_op { | |
4229 | MLXSW_REG_RAUHT_OP_QUERY_READ = 0, | |
4230 | /* Read operation */ | |
4231 | MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, | |
4232 | /* Clear on read operation. Used to read entry and clear | |
4233 | * activity bit. | |
4234 | */ | |
4235 | MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, | |
4236 | /* Add. Used to write a new entry to the table. All R/W fields are | |
4237 | * relevant for new entry. Activity bit is set for new entries. | |
4238 | */ | |
4239 | MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, | |
4240 | /* Update action. Used to update an existing route entry and | |
4241 | * only update the following fields: | |
4242 | * trap_action, trap_id, mac, counter_set_type, counter_index | |
4243 | */ | |
4244 | MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, | |
4245 | /* Clear activity. A bit is cleared for the entry. */ | |
4246 | MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, | |
4247 | /* Delete entry */ | |
4248 | MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, | |
4249 | /* Delete all host entries on a RIF. In this command, dip | |
4250 | * field is reserved. | |
4251 | */ | |
4252 | }; | |
4253 | ||
4254 | /* reg_rauht_op | |
4255 | * Access: OP | |
4256 | */ | |
4257 | MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); | |
4258 | ||
4259 | /* reg_rauht_a | |
4260 | * Activity. Set for new entries. Set if a packet lookup has hit on | |
4261 | * the specific entry. | |
4262 | * To clear the a bit, use "clear activity" op. | |
4263 | * Enabled by activity_dis in RGCR | |
4264 | * Access: RO | |
4265 | */ | |
4266 | MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); | |
4267 | ||
4268 | /* reg_rauht_rif | |
4269 | * Router Interface | |
4270 | * Access: Index | |
4271 | */ | |
4272 | MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); | |
4273 | ||
4274 | /* reg_rauht_dip* | |
4275 | * Destination address. | |
4276 | * Access: Index | |
4277 | */ | |
4278 | MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); | |
4279 | ||
4280 | enum mlxsw_reg_rauht_trap_action { | |
4281 | MLXSW_REG_RAUHT_TRAP_ACTION_NOP, | |
4282 | MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, | |
4283 | MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, | |
4284 | MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, | |
4285 | MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, | |
4286 | }; | |
4287 | ||
4288 | /* reg_rauht_trap_action | |
4289 | * Access: RW | |
4290 | */ | |
4291 | MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); | |
4292 | ||
4293 | enum mlxsw_reg_rauht_trap_id { | |
4294 | MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, | |
4295 | MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, | |
4296 | }; | |
4297 | ||
4298 | /* reg_rauht_trap_id | |
4299 | * Trap ID to be reported to CPU. | |
4300 | * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. | |
4301 | * For trap_action of NOP, MIRROR and DISCARD_ERROR, | |
4302 | * trap_id is reserved. | |
4303 | * Access: RW | |
4304 | */ | |
4305 | MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); | |
4306 | ||
4307 | /* reg_rauht_counter_set_type | |
4308 | * Counter set type for flow counters | |
4309 | * Access: RW | |
4310 | */ | |
4311 | MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); | |
4312 | ||
4313 | /* reg_rauht_counter_index | |
4314 | * Counter index for flow counters | |
4315 | * Access: RW | |
4316 | */ | |
4317 | MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); | |
4318 | ||
4319 | /* reg_rauht_mac | |
4320 | * MAC address. | |
4321 | * Access: RW | |
4322 | */ | |
4323 | MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); | |
4324 | ||
4325 | static inline void mlxsw_reg_rauht_pack(char *payload, | |
4326 | enum mlxsw_reg_rauht_op op, u16 rif, | |
4327 | const char *mac) | |
4328 | { | |
4329 | MLXSW_REG_ZERO(rauht, payload); | |
4330 | mlxsw_reg_rauht_op_set(payload, op); | |
4331 | mlxsw_reg_rauht_rif_set(payload, rif); | |
4332 | mlxsw_reg_rauht_mac_memcpy_to(payload, mac); | |
4333 | } | |
4334 | ||
4335 | static inline void mlxsw_reg_rauht_pack4(char *payload, | |
4336 | enum mlxsw_reg_rauht_op op, u16 rif, | |
4337 | const char *mac, u32 dip) | |
4338 | { | |
4339 | mlxsw_reg_rauht_pack(payload, op, rif, mac); | |
4340 | mlxsw_reg_rauht_dip4_set(payload, dip); | |
4341 | } | |
4342 | ||
a59f0b31 JP |
4343 | /* RALEU - Router Algorithmic LPM ECMP Update Register |
4344 | * --------------------------------------------------- | |
4345 | * The register enables updating the ECMP section in the action for multiple | |
4346 | * LPM Unicast entries in a single operation. The update is executed to | |
4347 | * all entries of a {virtual router, protocol} tuple using the same ECMP group. | |
4348 | */ | |
4349 | #define MLXSW_REG_RALEU_ID 0x8015 | |
4350 | #define MLXSW_REG_RALEU_LEN 0x28 | |
4351 | ||
21978dcf | 4352 | MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); |
a59f0b31 JP |
4353 | |
4354 | /* reg_raleu_protocol | |
4355 | * Protocol. | |
4356 | * Access: Index | |
4357 | */ | |
4358 | MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); | |
4359 | ||
4360 | /* reg_raleu_virtual_router | |
4361 | * Virtual Router ID | |
4362 | * Range is 0..cap_max_virtual_routers-1 | |
4363 | * Access: Index | |
4364 | */ | |
4365 | MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); | |
4366 | ||
4367 | /* reg_raleu_adjacency_index | |
4368 | * Adjacency Index used for matching on the existing entries. | |
4369 | * Access: Index | |
4370 | */ | |
4371 | MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); | |
4372 | ||
4373 | /* reg_raleu_ecmp_size | |
4374 | * ECMP Size used for matching on the existing entries. | |
4375 | * Access: Index | |
4376 | */ | |
4377 | MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); | |
4378 | ||
4379 | /* reg_raleu_new_adjacency_index | |
4380 | * New Adjacency Index. | |
4381 | * Access: WO | |
4382 | */ | |
4383 | MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); | |
4384 | ||
4385 | /* reg_raleu_new_ecmp_size | |
4386 | * New ECMP Size. | |
4387 | * Access: WO | |
4388 | */ | |
4389 | MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); | |
4390 | ||
4391 | static inline void mlxsw_reg_raleu_pack(char *payload, | |
4392 | enum mlxsw_reg_ralxx_protocol protocol, | |
4393 | u16 virtual_router, | |
4394 | u32 adjacency_index, u16 ecmp_size, | |
4395 | u32 new_adjacency_index, | |
4396 | u16 new_ecmp_size) | |
4397 | { | |
4398 | MLXSW_REG_ZERO(raleu, payload); | |
4399 | mlxsw_reg_raleu_protocol_set(payload, protocol); | |
4400 | mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); | |
4401 | mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); | |
4402 | mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); | |
4403 | mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); | |
4404 | mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); | |
4405 | } | |
4406 | ||
7cf2c205 YG |
4407 | /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register |
4408 | * ---------------------------------------------------------------- | |
4409 | * The RAUHTD register allows dumping entries from the Router Unicast Host | |
4410 | * Table. For a given session an entry is dumped no more than one time. The | |
4411 | * first RAUHTD access after reset is a new session. A session ends when the | |
4412 | * num_rec response is smaller than num_rec request or for IPv4 when the | |
4413 | * num_entries is smaller than 4. The clear activity affect the current session | |
4414 | * or the last session if a new session has not started. | |
4415 | */ | |
4416 | #define MLXSW_REG_RAUHTD_ID 0x8018 | |
4417 | #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 | |
4418 | #define MLXSW_REG_RAUHTD_REC_LEN 0x20 | |
4419 | #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 | |
4420 | #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ | |
4421 | MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) | |
4422 | #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 | |
4423 | ||
21978dcf | 4424 | MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); |
7cf2c205 YG |
4425 | |
4426 | #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) | |
4427 | #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) | |
4428 | ||
4429 | /* reg_rauhtd_filter_fields | |
4430 | * if a bit is '0' then the relevant field is ignored and dump is done | |
4431 | * regardless of the field value | |
4432 | * Bit0 - filter by activity: entry_a | |
4433 | * Bit3 - filter by entry rip: entry_rif | |
4434 | * Access: Index | |
4435 | */ | |
4436 | MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); | |
4437 | ||
4438 | enum mlxsw_reg_rauhtd_op { | |
4439 | MLXSW_REG_RAUHTD_OP_DUMP, | |
4440 | MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, | |
4441 | }; | |
4442 | ||
4443 | /* reg_rauhtd_op | |
4444 | * Access: OP | |
4445 | */ | |
4446 | MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); | |
4447 | ||
4448 | /* reg_rauhtd_num_rec | |
4449 | * At request: number of records requested | |
4450 | * At response: number of records dumped | |
4451 | * For IPv4, each record has 4 entries at request and up to 4 entries | |
4452 | * at response | |
4453 | * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM | |
4454 | * Access: Index | |
4455 | */ | |
4456 | MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); | |
4457 | ||
4458 | /* reg_rauhtd_entry_a | |
4459 | * Dump only if activity has value of entry_a | |
4460 | * Reserved if filter_fields bit0 is '0' | |
4461 | * Access: Index | |
4462 | */ | |
4463 | MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); | |
4464 | ||
4465 | enum mlxsw_reg_rauhtd_type { | |
4466 | MLXSW_REG_RAUHTD_TYPE_IPV4, | |
4467 | MLXSW_REG_RAUHTD_TYPE_IPV6, | |
4468 | }; | |
4469 | ||
4470 | /* reg_rauhtd_type | |
4471 | * Dump only if record type is: | |
4472 | * 0 - IPv4 | |
4473 | * 1 - IPv6 | |
4474 | * Access: Index | |
4475 | */ | |
4476 | MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); | |
4477 | ||
4478 | /* reg_rauhtd_entry_rif | |
4479 | * Dump only if RIF has value of entry_rif | |
4480 | * Reserved if filter_fields bit3 is '0' | |
4481 | * Access: Index | |
4482 | */ | |
4483 | MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); | |
4484 | ||
4485 | static inline void mlxsw_reg_rauhtd_pack(char *payload, | |
4486 | enum mlxsw_reg_rauhtd_type type) | |
4487 | { | |
4488 | MLXSW_REG_ZERO(rauhtd, payload); | |
4489 | mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); | |
4490 | mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); | |
4491 | mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); | |
4492 | mlxsw_reg_rauhtd_entry_a_set(payload, 1); | |
4493 | mlxsw_reg_rauhtd_type_set(payload, type); | |
4494 | } | |
4495 | ||
4496 | /* reg_rauhtd_ipv4_rec_num_entries | |
4497 | * Number of valid entries in this record: | |
4498 | * 0 - 1 valid entry | |
4499 | * 1 - 2 valid entries | |
4500 | * 2 - 3 valid entries | |
4501 | * 3 - 4 valid entries | |
4502 | * Access: RO | |
4503 | */ | |
4504 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, | |
4505 | MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, | |
4506 | MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); | |
4507 | ||
4508 | /* reg_rauhtd_rec_type | |
4509 | * Record type. | |
4510 | * 0 - IPv4 | |
4511 | * 1 - IPv6 | |
4512 | * Access: RO | |
4513 | */ | |
4514 | MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, | |
4515 | MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); | |
4516 | ||
4517 | #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 | |
4518 | ||
4519 | /* reg_rauhtd_ipv4_ent_a | |
4520 | * Activity. Set for new entries. Set if a packet lookup has hit on the | |
4521 | * specific entry. | |
4522 | * Access: RO | |
4523 | */ | |
4524 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, | |
4525 | MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); | |
4526 | ||
4527 | /* reg_rauhtd_ipv4_ent_rif | |
4528 | * Router interface. | |
4529 | * Access: RO | |
4530 | */ | |
4531 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, | |
4532 | 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); | |
4533 | ||
4534 | /* reg_rauhtd_ipv4_ent_dip | |
4535 | * Destination IPv4 address. | |
4536 | * Access: RO | |
4537 | */ | |
4538 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, | |
4539 | 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); | |
4540 | ||
4541 | static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, | |
4542 | int ent_index, u16 *p_rif, | |
4543 | u32 *p_dip) | |
4544 | { | |
4545 | *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); | |
4546 | *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); | |
4547 | } | |
4548 | ||
5246f2e2 JP |
4549 | /* MFCR - Management Fan Control Register |
4550 | * -------------------------------------- | |
4551 | * This register controls the settings of the Fan Speed PWM mechanism. | |
4552 | */ | |
4553 | #define MLXSW_REG_MFCR_ID 0x9001 | |
4554 | #define MLXSW_REG_MFCR_LEN 0x08 | |
4555 | ||
21978dcf | 4556 | MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); |
5246f2e2 JP |
4557 | |
4558 | enum mlxsw_reg_mfcr_pwm_frequency { | |
4559 | MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, | |
4560 | MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, | |
4561 | MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, | |
4562 | MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, | |
4563 | MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, | |
4564 | MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, | |
4565 | MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, | |
4566 | MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, | |
4567 | }; | |
4568 | ||
4569 | /* reg_mfcr_pwm_frequency | |
4570 | * Controls the frequency of the PWM signal. | |
4571 | * Access: RW | |
4572 | */ | |
f7ad3d4b | 4573 | MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); |
5246f2e2 JP |
4574 | |
4575 | #define MLXSW_MFCR_TACHOS_MAX 10 | |
4576 | ||
4577 | /* reg_mfcr_tacho_active | |
4578 | * Indicates which of the tachometer is active (bit per tachometer). | |
4579 | * Access: RO | |
4580 | */ | |
4581 | MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); | |
4582 | ||
4583 | #define MLXSW_MFCR_PWMS_MAX 5 | |
4584 | ||
4585 | /* reg_mfcr_pwm_active | |
4586 | * Indicates which of the PWM control is active (bit per PWM). | |
4587 | * Access: RO | |
4588 | */ | |
4589 | MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); | |
4590 | ||
4591 | static inline void | |
4592 | mlxsw_reg_mfcr_pack(char *payload, | |
4593 | enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) | |
4594 | { | |
4595 | MLXSW_REG_ZERO(mfcr, payload); | |
4596 | mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); | |
4597 | } | |
4598 | ||
4599 | static inline void | |
4600 | mlxsw_reg_mfcr_unpack(char *payload, | |
4601 | enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, | |
4602 | u16 *p_tacho_active, u8 *p_pwm_active) | |
4603 | { | |
4604 | *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); | |
4605 | *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); | |
4606 | *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); | |
4607 | } | |
4608 | ||
4609 | /* MFSC - Management Fan Speed Control Register | |
4610 | * -------------------------------------------- | |
4611 | * This register controls the settings of the Fan Speed PWM mechanism. | |
4612 | */ | |
4613 | #define MLXSW_REG_MFSC_ID 0x9002 | |
4614 | #define MLXSW_REG_MFSC_LEN 0x08 | |
4615 | ||
21978dcf | 4616 | MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); |
5246f2e2 JP |
4617 | |
4618 | /* reg_mfsc_pwm | |
4619 | * Fan pwm to control / monitor. | |
4620 | * Access: Index | |
4621 | */ | |
4622 | MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); | |
4623 | ||
4624 | /* reg_mfsc_pwm_duty_cycle | |
4625 | * Controls the duty cycle of the PWM. Value range from 0..255 to | |
4626 | * represent duty cycle of 0%...100%. | |
4627 | * Access: RW | |
4628 | */ | |
4629 | MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); | |
4630 | ||
4631 | static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, | |
4632 | u8 pwm_duty_cycle) | |
4633 | { | |
4634 | MLXSW_REG_ZERO(mfsc, payload); | |
4635 | mlxsw_reg_mfsc_pwm_set(payload, pwm); | |
4636 | mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); | |
4637 | } | |
4638 | ||
4639 | /* MFSM - Management Fan Speed Measurement | |
4640 | * --------------------------------------- | |
4641 | * This register controls the settings of the Tacho measurements and | |
4642 | * enables reading the Tachometer measurements. | |
4643 | */ | |
4644 | #define MLXSW_REG_MFSM_ID 0x9003 | |
4645 | #define MLXSW_REG_MFSM_LEN 0x08 | |
4646 | ||
21978dcf | 4647 | MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); |
5246f2e2 JP |
4648 | |
4649 | /* reg_mfsm_tacho | |
4650 | * Fan tachometer index. | |
4651 | * Access: Index | |
4652 | */ | |
4653 | MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); | |
4654 | ||
4655 | /* reg_mfsm_rpm | |
4656 | * Fan speed (round per minute). | |
4657 | * Access: RO | |
4658 | */ | |
4659 | MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); | |
4660 | ||
4661 | static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) | |
4662 | { | |
4663 | MLXSW_REG_ZERO(mfsm, payload); | |
4664 | mlxsw_reg_mfsm_tacho_set(payload, tacho); | |
4665 | } | |
4666 | ||
55c63aaa JP |
4667 | /* MFSL - Management Fan Speed Limit Register |
4668 | * ------------------------------------------ | |
4669 | * The Fan Speed Limit register is used to configure the fan speed | |
4670 | * event / interrupt notification mechanism. Fan speed threshold are | |
4671 | * defined for both under-speed and over-speed. | |
4672 | */ | |
4673 | #define MLXSW_REG_MFSL_ID 0x9004 | |
4674 | #define MLXSW_REG_MFSL_LEN 0x0C | |
4675 | ||
4676 | MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); | |
4677 | ||
4678 | /* reg_mfsl_tacho | |
4679 | * Fan tachometer index. | |
4680 | * Access: Index | |
4681 | */ | |
4682 | MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); | |
4683 | ||
4684 | /* reg_mfsl_tach_min | |
4685 | * Tachometer minimum value (minimum RPM). | |
4686 | * Access: RW | |
4687 | */ | |
4688 | MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); | |
4689 | ||
4690 | /* reg_mfsl_tach_max | |
4691 | * Tachometer maximum value (maximum RPM). | |
4692 | * Access: RW | |
4693 | */ | |
4694 | MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); | |
4695 | ||
4696 | static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, | |
4697 | u16 tach_min, u16 tach_max) | |
4698 | { | |
4699 | MLXSW_REG_ZERO(mfsl, payload); | |
4700 | mlxsw_reg_mfsl_tacho_set(payload, tacho); | |
4701 | mlxsw_reg_mfsl_tach_min_set(payload, tach_min); | |
4702 | mlxsw_reg_mfsl_tach_max_set(payload, tach_max); | |
4703 | } | |
4704 | ||
4705 | static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, | |
4706 | u16 *p_tach_min, u16 *p_tach_max) | |
4707 | { | |
4708 | if (p_tach_min) | |
4709 | *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); | |
4710 | ||
4711 | if (p_tach_max) | |
4712 | *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); | |
4713 | } | |
4714 | ||
85926f87 JP |
4715 | /* MTCAP - Management Temperature Capabilities |
4716 | * ------------------------------------------- | |
4717 | * This register exposes the capabilities of the device and | |
4718 | * system temperature sensing. | |
4719 | */ | |
4720 | #define MLXSW_REG_MTCAP_ID 0x9009 | |
4721 | #define MLXSW_REG_MTCAP_LEN 0x08 | |
4722 | ||
21978dcf | 4723 | MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); |
85926f87 JP |
4724 | |
4725 | /* reg_mtcap_sensor_count | |
4726 | * Number of sensors supported by the device. | |
4727 | * This includes the QSFP module sensors (if exists in the QSFP module). | |
4728 | * Access: RO | |
4729 | */ | |
4730 | MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); | |
4731 | ||
4732 | /* MTMP - Management Temperature | |
4733 | * ----------------------------- | |
4734 | * This register controls the settings of the temperature measurements | |
4735 | * and enables reading the temperature measurements. Note that temperature | |
4736 | * is in 0.125 degrees Celsius. | |
4737 | */ | |
4738 | #define MLXSW_REG_MTMP_ID 0x900A | |
4739 | #define MLXSW_REG_MTMP_LEN 0x20 | |
4740 | ||
21978dcf | 4741 | MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); |
85926f87 JP |
4742 | |
4743 | /* reg_mtmp_sensor_index | |
4744 | * Sensors index to access. | |
4745 | * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially | |
4746 | * (module 0 is mapped to sensor_index 64). | |
4747 | * Access: Index | |
4748 | */ | |
4749 | MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); | |
4750 | ||
4751 | /* Convert to milli degrees Celsius */ | |
4752 | #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) | |
4753 | ||
4754 | /* reg_mtmp_temperature | |
4755 | * Temperature reading from the sensor. Reading is in 0.125 Celsius | |
4756 | * degrees units. | |
4757 | * Access: RO | |
4758 | */ | |
4759 | MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); | |
4760 | ||
4761 | /* reg_mtmp_mte | |
4762 | * Max Temperature Enable - enables measuring the max temperature on a sensor. | |
4763 | * Access: RW | |
4764 | */ | |
4765 | MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); | |
4766 | ||
4767 | /* reg_mtmp_mtr | |
4768 | * Max Temperature Reset - clears the value of the max temperature register. | |
4769 | * Access: WO | |
4770 | */ | |
4771 | MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); | |
4772 | ||
4773 | /* reg_mtmp_max_temperature | |
4774 | * The highest measured temperature from the sensor. | |
4775 | * When the bit mte is cleared, the field max_temperature is reserved. | |
4776 | * Access: RO | |
4777 | */ | |
4778 | MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); | |
4779 | ||
4780 | #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 | |
4781 | ||
4782 | /* reg_mtmp_sensor_name | |
4783 | * Sensor Name | |
4784 | * Access: RO | |
4785 | */ | |
4786 | MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); | |
4787 | ||
4788 | static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, | |
4789 | bool max_temp_enable, | |
4790 | bool max_temp_reset) | |
4791 | { | |
4792 | MLXSW_REG_ZERO(mtmp, payload); | |
4793 | mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); | |
4794 | mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); | |
4795 | mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); | |
4796 | } | |
4797 | ||
4798 | static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, | |
4799 | unsigned int *p_max_temp, | |
4800 | char *sensor_name) | |
4801 | { | |
4802 | u16 temp; | |
4803 | ||
4804 | if (p_temp) { | |
4805 | temp = mlxsw_reg_mtmp_temperature_get(payload); | |
4806 | *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); | |
4807 | } | |
4808 | if (p_max_temp) { | |
acf35a4e | 4809 | temp = mlxsw_reg_mtmp_max_temperature_get(payload); |
85926f87 JP |
4810 | *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); |
4811 | } | |
4812 | if (sensor_name) | |
4813 | mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); | |
4814 | } | |
4815 | ||
43a46856 YG |
4816 | /* MPAT - Monitoring Port Analyzer Table |
4817 | * ------------------------------------- | |
4818 | * MPAT Register is used to query and configure the Switch PortAnalyzer Table. | |
4819 | * For an enabled analyzer, all fields except e (enable) cannot be modified. | |
4820 | */ | |
4821 | #define MLXSW_REG_MPAT_ID 0x901A | |
4822 | #define MLXSW_REG_MPAT_LEN 0x78 | |
4823 | ||
21978dcf | 4824 | MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); |
43a46856 YG |
4825 | |
4826 | /* reg_mpat_pa_id | |
4827 | * Port Analyzer ID. | |
4828 | * Access: Index | |
4829 | */ | |
4830 | MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); | |
4831 | ||
4832 | /* reg_mpat_system_port | |
4833 | * A unique port identifier for the final destination of the packet. | |
4834 | * Access: RW | |
4835 | */ | |
4836 | MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); | |
4837 | ||
4838 | /* reg_mpat_e | |
4839 | * Enable. Indicating the Port Analyzer is enabled. | |
4840 | * Access: RW | |
4841 | */ | |
4842 | MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); | |
4843 | ||
4844 | /* reg_mpat_qos | |
4845 | * Quality Of Service Mode. | |
4846 | * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation | |
4847 | * PCP, DEI, DSCP or VL) are configured. | |
4848 | * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the | |
4849 | * same as in the original packet that has triggered the mirroring. For | |
4850 | * SPAN also the pcp,dei are maintained. | |
4851 | * Access: RW | |
4852 | */ | |
4853 | MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); | |
4854 | ||
23019054 YG |
4855 | /* reg_mpat_be |
4856 | * Best effort mode. Indicates mirroring traffic should not cause packet | |
4857 | * drop or back pressure, but will discard the mirrored packets. Mirrored | |
4858 | * packets will be forwarded on a best effort manner. | |
4859 | * 0: Do not discard mirrored packets | |
4860 | * 1: Discard mirrored packets if causing congestion | |
4861 | * Access: RW | |
4862 | */ | |
4863 | MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); | |
4864 | ||
43a46856 YG |
4865 | static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, |
4866 | u16 system_port, bool e) | |
4867 | { | |
4868 | MLXSW_REG_ZERO(mpat, payload); | |
4869 | mlxsw_reg_mpat_pa_id_set(payload, pa_id); | |
4870 | mlxsw_reg_mpat_system_port_set(payload, system_port); | |
4871 | mlxsw_reg_mpat_e_set(payload, e); | |
4872 | mlxsw_reg_mpat_qos_set(payload, 1); | |
23019054 YG |
4873 | mlxsw_reg_mpat_be_set(payload, 1); |
4874 | } | |
4875 | ||
4876 | /* MPAR - Monitoring Port Analyzer Register | |
4877 | * ---------------------------------------- | |
4878 | * MPAR register is used to query and configure the port analyzer port mirroring | |
4879 | * properties. | |
4880 | */ | |
4881 | #define MLXSW_REG_MPAR_ID 0x901B | |
4882 | #define MLXSW_REG_MPAR_LEN 0x08 | |
4883 | ||
21978dcf | 4884 | MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); |
23019054 YG |
4885 | |
4886 | /* reg_mpar_local_port | |
4887 | * The local port to mirror the packets from. | |
4888 | * Access: Index | |
4889 | */ | |
4890 | MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); | |
4891 | ||
4892 | enum mlxsw_reg_mpar_i_e { | |
4893 | MLXSW_REG_MPAR_TYPE_EGRESS, | |
4894 | MLXSW_REG_MPAR_TYPE_INGRESS, | |
4895 | }; | |
4896 | ||
4897 | /* reg_mpar_i_e | |
4898 | * Ingress/Egress | |
4899 | * Access: Index | |
4900 | */ | |
4901 | MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); | |
4902 | ||
4903 | /* reg_mpar_enable | |
4904 | * Enable mirroring | |
4905 | * By default, port mirroring is disabled for all ports. | |
4906 | * Access: RW | |
4907 | */ | |
4908 | MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); | |
4909 | ||
4910 | /* reg_mpar_pa_id | |
4911 | * Port Analyzer ID. | |
4912 | * Access: RW | |
4913 | */ | |
4914 | MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); | |
4915 | ||
4916 | static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, | |
4917 | enum mlxsw_reg_mpar_i_e i_e, | |
4918 | bool enable, u8 pa_id) | |
4919 | { | |
4920 | MLXSW_REG_ZERO(mpar, payload); | |
4921 | mlxsw_reg_mpar_local_port_set(payload, local_port); | |
4922 | mlxsw_reg_mpar_enable_set(payload, enable); | |
4923 | mlxsw_reg_mpar_i_e_set(payload, i_e); | |
4924 | mlxsw_reg_mpar_pa_id_set(payload, pa_id); | |
43a46856 YG |
4925 | } |
4926 | ||
3161c159 IS |
4927 | /* MLCR - Management LED Control Register |
4928 | * -------------------------------------- | |
4929 | * Controls the system LEDs. | |
4930 | */ | |
4931 | #define MLXSW_REG_MLCR_ID 0x902B | |
4932 | #define MLXSW_REG_MLCR_LEN 0x0C | |
4933 | ||
21978dcf | 4934 | MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); |
3161c159 IS |
4935 | |
4936 | /* reg_mlcr_local_port | |
4937 | * Local port number. | |
4938 | * Access: RW | |
4939 | */ | |
4940 | MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); | |
4941 | ||
4942 | #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF | |
4943 | ||
4944 | /* reg_mlcr_beacon_duration | |
4945 | * Duration of the beacon to be active, in seconds. | |
4946 | * 0x0 - Will turn off the beacon. | |
4947 | * 0xFFFF - Will turn on the beacon until explicitly turned off. | |
4948 | * Access: RW | |
4949 | */ | |
4950 | MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); | |
4951 | ||
4952 | /* reg_mlcr_beacon_remain | |
4953 | * Remaining duration of the beacon, in seconds. | |
4954 | * 0xFFFF indicates an infinite amount of time. | |
4955 | * Access: RO | |
4956 | */ | |
4957 | MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); | |
4958 | ||
4959 | static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, | |
4960 | bool active) | |
4961 | { | |
4962 | MLXSW_REG_ZERO(mlcr, payload); | |
4963 | mlxsw_reg_mlcr_local_port_set(payload, local_port); | |
4964 | mlxsw_reg_mlcr_beacon_duration_set(payload, active ? | |
4965 | MLXSW_REG_MLCR_DURATION_MAX : 0); | |
4966 | } | |
4967 | ||
e0594369 JP |
4968 | /* SBPR - Shared Buffer Pools Register |
4969 | * ----------------------------------- | |
4970 | * The SBPR configures and retrieves the shared buffer pools and configuration. | |
4971 | */ | |
4972 | #define MLXSW_REG_SBPR_ID 0xB001 | |
4973 | #define MLXSW_REG_SBPR_LEN 0x14 | |
4974 | ||
21978dcf | 4975 | MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); |
e0594369 | 4976 | |
497e8592 JP |
4977 | /* shared direstion enum for SBPR, SBCM, SBPM */ |
4978 | enum mlxsw_reg_sbxx_dir { | |
4979 | MLXSW_REG_SBXX_DIR_INGRESS, | |
4980 | MLXSW_REG_SBXX_DIR_EGRESS, | |
e0594369 JP |
4981 | }; |
4982 | ||
4983 | /* reg_sbpr_dir | |
4984 | * Direction. | |
4985 | * Access: Index | |
4986 | */ | |
4987 | MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); | |
4988 | ||
4989 | /* reg_sbpr_pool | |
4990 | * Pool index. | |
4991 | * Access: Index | |
4992 | */ | |
4993 | MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); | |
4994 | ||
4995 | /* reg_sbpr_size | |
4996 | * Pool size in buffer cells. | |
4997 | * Access: RW | |
4998 | */ | |
4999 | MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); | |
5000 | ||
5001 | enum mlxsw_reg_sbpr_mode { | |
5002 | MLXSW_REG_SBPR_MODE_STATIC, | |
5003 | MLXSW_REG_SBPR_MODE_DYNAMIC, | |
5004 | }; | |
5005 | ||
5006 | /* reg_sbpr_mode | |
5007 | * Pool quota calculation mode. | |
5008 | * Access: RW | |
5009 | */ | |
5010 | MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); | |
5011 | ||
5012 | static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, | |
497e8592 | 5013 | enum mlxsw_reg_sbxx_dir dir, |
e0594369 JP |
5014 | enum mlxsw_reg_sbpr_mode mode, u32 size) |
5015 | { | |
5016 | MLXSW_REG_ZERO(sbpr, payload); | |
5017 | mlxsw_reg_sbpr_pool_set(payload, pool); | |
5018 | mlxsw_reg_sbpr_dir_set(payload, dir); | |
5019 | mlxsw_reg_sbpr_mode_set(payload, mode); | |
5020 | mlxsw_reg_sbpr_size_set(payload, size); | |
5021 | } | |
5022 | ||
5023 | /* SBCM - Shared Buffer Class Management Register | |
5024 | * ---------------------------------------------- | |
5025 | * The SBCM register configures and retrieves the shared buffer allocation | |
5026 | * and configuration according to Port-PG, including the binding to pool | |
5027 | * and definition of the associated quota. | |
5028 | */ | |
5029 | #define MLXSW_REG_SBCM_ID 0xB002 | |
5030 | #define MLXSW_REG_SBCM_LEN 0x28 | |
5031 | ||
21978dcf | 5032 | MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); |
e0594369 JP |
5033 | |
5034 | /* reg_sbcm_local_port | |
5035 | * Local port number. | |
5036 | * For Ingress: excludes CPU port and Router port | |
5037 | * For Egress: excludes IP Router | |
5038 | * Access: Index | |
5039 | */ | |
5040 | MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); | |
5041 | ||
5042 | /* reg_sbcm_pg_buff | |
5043 | * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) | |
5044 | * For PG buffer: range is 0..cap_max_pg_buffers - 1 | |
5045 | * For traffic class: range is 0..cap_max_tclass - 1 | |
5046 | * Note that when traffic class is in MC aware mode then the traffic | |
5047 | * classes which are MC aware cannot be configured. | |
5048 | * Access: Index | |
5049 | */ | |
5050 | MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); | |
5051 | ||
e0594369 JP |
5052 | /* reg_sbcm_dir |
5053 | * Direction. | |
5054 | * Access: Index | |
5055 | */ | |
5056 | MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); | |
5057 | ||
5058 | /* reg_sbcm_min_buff | |
5059 | * Minimum buffer size for the limiter, in cells. | |
5060 | * Access: RW | |
5061 | */ | |
5062 | MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); | |
5063 | ||
c30a53c7 JP |
5064 | /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ |
5065 | #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 | |
5066 | #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 | |
5067 | ||
e0594369 JP |
5068 | /* reg_sbcm_max_buff |
5069 | * When the pool associated to the port-pg/tclass is configured to | |
5070 | * static, Maximum buffer size for the limiter configured in cells. | |
5071 | * When the pool associated to the port-pg/tclass is configured to | |
5072 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
5073 | * the following values: | |
5074 | * 0: 0 | |
5075 | * i: (1/128)*2^(i-1), for i=1..14 | |
5076 | * 0xFF: Infinity | |
5077 | * Access: RW | |
5078 | */ | |
5079 | MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); | |
5080 | ||
5081 | /* reg_sbcm_pool | |
5082 | * Association of the port-priority to a pool. | |
5083 | * Access: RW | |
5084 | */ | |
5085 | MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); | |
5086 | ||
5087 | static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, | |
497e8592 | 5088 | enum mlxsw_reg_sbxx_dir dir, |
e0594369 JP |
5089 | u32 min_buff, u32 max_buff, u8 pool) |
5090 | { | |
5091 | MLXSW_REG_ZERO(sbcm, payload); | |
5092 | mlxsw_reg_sbcm_local_port_set(payload, local_port); | |
5093 | mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); | |
5094 | mlxsw_reg_sbcm_dir_set(payload, dir); | |
5095 | mlxsw_reg_sbcm_min_buff_set(payload, min_buff); | |
5096 | mlxsw_reg_sbcm_max_buff_set(payload, max_buff); | |
5097 | mlxsw_reg_sbcm_pool_set(payload, pool); | |
5098 | } | |
5099 | ||
9efc8f65 JP |
5100 | /* SBPM - Shared Buffer Port Management Register |
5101 | * --------------------------------------------- | |
e0594369 JP |
5102 | * The SBPM register configures and retrieves the shared buffer allocation |
5103 | * and configuration according to Port-Pool, including the definition | |
5104 | * of the associated quota. | |
5105 | */ | |
5106 | #define MLXSW_REG_SBPM_ID 0xB003 | |
5107 | #define MLXSW_REG_SBPM_LEN 0x28 | |
5108 | ||
21978dcf | 5109 | MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); |
e0594369 JP |
5110 | |
5111 | /* reg_sbpm_local_port | |
5112 | * Local port number. | |
5113 | * For Ingress: excludes CPU port and Router port | |
5114 | * For Egress: excludes IP Router | |
5115 | * Access: Index | |
5116 | */ | |
5117 | MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); | |
5118 | ||
5119 | /* reg_sbpm_pool | |
5120 | * The pool associated to quota counting on the local_port. | |
5121 | * Access: Index | |
5122 | */ | |
5123 | MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); | |
5124 | ||
e0594369 JP |
5125 | /* reg_sbpm_dir |
5126 | * Direction. | |
5127 | * Access: Index | |
5128 | */ | |
5129 | MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); | |
5130 | ||
42a7f1d7 JP |
5131 | /* reg_sbpm_buff_occupancy |
5132 | * Current buffer occupancy in cells. | |
5133 | * Access: RO | |
5134 | */ | |
5135 | MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); | |
5136 | ||
5137 | /* reg_sbpm_clr | |
5138 | * Clear Max Buffer Occupancy | |
5139 | * When this bit is set, max_buff_occupancy field is cleared (and a | |
5140 | * new max value is tracked from the time the clear was performed). | |
5141 | * Access: OP | |
5142 | */ | |
5143 | MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); | |
5144 | ||
5145 | /* reg_sbpm_max_buff_occupancy | |
5146 | * Maximum value of buffer occupancy in cells monitored. Cleared by | |
5147 | * writing to the clr field. | |
5148 | * Access: RO | |
5149 | */ | |
5150 | MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); | |
5151 | ||
e0594369 JP |
5152 | /* reg_sbpm_min_buff |
5153 | * Minimum buffer size for the limiter, in cells. | |
5154 | * Access: RW | |
5155 | */ | |
5156 | MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); | |
5157 | ||
5158 | /* reg_sbpm_max_buff | |
5159 | * When the pool associated to the port-pg/tclass is configured to | |
5160 | * static, Maximum buffer size for the limiter configured in cells. | |
5161 | * When the pool associated to the port-pg/tclass is configured to | |
5162 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
5163 | * the following values: | |
5164 | * 0: 0 | |
5165 | * i: (1/128)*2^(i-1), for i=1..14 | |
5166 | * 0xFF: Infinity | |
5167 | * Access: RW | |
5168 | */ | |
5169 | MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); | |
5170 | ||
5171 | static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, | |
42a7f1d7 | 5172 | enum mlxsw_reg_sbxx_dir dir, bool clr, |
e0594369 JP |
5173 | u32 min_buff, u32 max_buff) |
5174 | { | |
5175 | MLXSW_REG_ZERO(sbpm, payload); | |
5176 | mlxsw_reg_sbpm_local_port_set(payload, local_port); | |
5177 | mlxsw_reg_sbpm_pool_set(payload, pool); | |
5178 | mlxsw_reg_sbpm_dir_set(payload, dir); | |
42a7f1d7 | 5179 | mlxsw_reg_sbpm_clr_set(payload, clr); |
e0594369 JP |
5180 | mlxsw_reg_sbpm_min_buff_set(payload, min_buff); |
5181 | mlxsw_reg_sbpm_max_buff_set(payload, max_buff); | |
5182 | } | |
5183 | ||
42a7f1d7 JP |
5184 | static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, |
5185 | u32 *p_max_buff_occupancy) | |
5186 | { | |
5187 | *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); | |
5188 | *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); | |
5189 | } | |
5190 | ||
e0594369 JP |
5191 | /* SBMM - Shared Buffer Multicast Management Register |
5192 | * -------------------------------------------------- | |
5193 | * The SBMM register configures and retrieves the shared buffer allocation | |
5194 | * and configuration for MC packets according to Switch-Priority, including | |
5195 | * the binding to pool and definition of the associated quota. | |
5196 | */ | |
5197 | #define MLXSW_REG_SBMM_ID 0xB004 | |
5198 | #define MLXSW_REG_SBMM_LEN 0x28 | |
5199 | ||
21978dcf | 5200 | MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); |
e0594369 JP |
5201 | |
5202 | /* reg_sbmm_prio | |
5203 | * Switch Priority. | |
5204 | * Access: Index | |
5205 | */ | |
5206 | MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); | |
5207 | ||
5208 | /* reg_sbmm_min_buff | |
5209 | * Minimum buffer size for the limiter, in cells. | |
5210 | * Access: RW | |
5211 | */ | |
5212 | MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); | |
5213 | ||
5214 | /* reg_sbmm_max_buff | |
5215 | * When the pool associated to the port-pg/tclass is configured to | |
5216 | * static, Maximum buffer size for the limiter configured in cells. | |
5217 | * When the pool associated to the port-pg/tclass is configured to | |
5218 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
5219 | * the following values: | |
5220 | * 0: 0 | |
5221 | * i: (1/128)*2^(i-1), for i=1..14 | |
5222 | * 0xFF: Infinity | |
5223 | * Access: RW | |
5224 | */ | |
5225 | MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); | |
5226 | ||
5227 | /* reg_sbmm_pool | |
5228 | * Association of the port-priority to a pool. | |
5229 | * Access: RW | |
5230 | */ | |
5231 | MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); | |
5232 | ||
5233 | static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, | |
5234 | u32 max_buff, u8 pool) | |
5235 | { | |
5236 | MLXSW_REG_ZERO(sbmm, payload); | |
5237 | mlxsw_reg_sbmm_prio_set(payload, prio); | |
5238 | mlxsw_reg_sbmm_min_buff_set(payload, min_buff); | |
5239 | mlxsw_reg_sbmm_max_buff_set(payload, max_buff); | |
5240 | mlxsw_reg_sbmm_pool_set(payload, pool); | |
5241 | } | |
5242 | ||
26176def JP |
5243 | /* SBSR - Shared Buffer Status Register |
5244 | * ------------------------------------ | |
5245 | * The SBSR register retrieves the shared buffer occupancy according to | |
5246 | * Port-Pool. Note that this register enables reading a large amount of data. | |
5247 | * It is the user's responsibility to limit the amount of data to ensure the | |
5248 | * response can match the maximum transfer unit. In case the response exceeds | |
5249 | * the maximum transport unit, it will be truncated with no special notice. | |
5250 | */ | |
5251 | #define MLXSW_REG_SBSR_ID 0xB005 | |
5252 | #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ | |
5253 | #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ | |
5254 | #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 | |
5255 | #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ | |
5256 | MLXSW_REG_SBSR_REC_LEN * \ | |
5257 | MLXSW_REG_SBSR_REC_MAX_COUNT) | |
5258 | ||
21978dcf | 5259 | MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); |
26176def JP |
5260 | |
5261 | /* reg_sbsr_clr | |
5262 | * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy | |
5263 | * field is cleared (and a new max value is tracked from the time the clear | |
5264 | * was performed). | |
5265 | * Access: OP | |
5266 | */ | |
5267 | MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); | |
5268 | ||
5269 | /* reg_sbsr_ingress_port_mask | |
5270 | * Bit vector for all ingress network ports. | |
5271 | * Indicates which of the ports (for which the relevant bit is set) | |
5272 | * are affected by the set operation. Configuration of any other port | |
5273 | * does not change. | |
5274 | * Access: Index | |
5275 | */ | |
5276 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); | |
5277 | ||
5278 | /* reg_sbsr_pg_buff_mask | |
5279 | * Bit vector for all switch priority groups. | |
5280 | * Indicates which of the priorities (for which the relevant bit is set) | |
5281 | * are affected by the set operation. Configuration of any other priority | |
5282 | * does not change. | |
5283 | * Range is 0..cap_max_pg_buffers - 1 | |
5284 | * Access: Index | |
5285 | */ | |
5286 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); | |
5287 | ||
5288 | /* reg_sbsr_egress_port_mask | |
5289 | * Bit vector for all egress network ports. | |
5290 | * Indicates which of the ports (for which the relevant bit is set) | |
5291 | * are affected by the set operation. Configuration of any other port | |
5292 | * does not change. | |
5293 | * Access: Index | |
5294 | */ | |
5295 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); | |
5296 | ||
5297 | /* reg_sbsr_tclass_mask | |
5298 | * Bit vector for all traffic classes. | |
5299 | * Indicates which of the traffic classes (for which the relevant bit is | |
5300 | * set) are affected by the set operation. Configuration of any other | |
5301 | * traffic class does not change. | |
5302 | * Range is 0..cap_max_tclass - 1 | |
5303 | * Access: Index | |
5304 | */ | |
5305 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); | |
5306 | ||
5307 | static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) | |
5308 | { | |
5309 | MLXSW_REG_ZERO(sbsr, payload); | |
5310 | mlxsw_reg_sbsr_clr_set(payload, clr); | |
5311 | } | |
5312 | ||
5313 | /* reg_sbsr_rec_buff_occupancy | |
5314 | * Current buffer occupancy in cells. | |
5315 | * Access: RO | |
5316 | */ | |
5317 | MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, | |
5318 | 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); | |
5319 | ||
5320 | /* reg_sbsr_rec_max_buff_occupancy | |
5321 | * Maximum value of buffer occupancy in cells monitored. Cleared by | |
5322 | * writing to the clr field. | |
5323 | * Access: RO | |
5324 | */ | |
5325 | MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, | |
5326 | 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); | |
5327 | ||
5328 | static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, | |
5329 | u32 *p_buff_occupancy, | |
5330 | u32 *p_max_buff_occupancy) | |
5331 | { | |
5332 | *p_buff_occupancy = | |
5333 | mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); | |
5334 | *p_max_buff_occupancy = | |
5335 | mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); | |
5336 | } | |
5337 | ||
51ae8cc6 YG |
5338 | /* SBIB - Shared Buffer Internal Buffer Register |
5339 | * --------------------------------------------- | |
5340 | * The SBIB register configures per port buffers for internal use. The internal | |
5341 | * buffers consume memory on the port buffers (note that the port buffers are | |
5342 | * used also by PBMC). | |
5343 | * | |
5344 | * For Spectrum this is used for egress mirroring. | |
5345 | */ | |
5346 | #define MLXSW_REG_SBIB_ID 0xB006 | |
5347 | #define MLXSW_REG_SBIB_LEN 0x10 | |
5348 | ||
21978dcf | 5349 | MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); |
51ae8cc6 YG |
5350 | |
5351 | /* reg_sbib_local_port | |
5352 | * Local port number | |
5353 | * Not supported for CPU port and router port | |
5354 | * Access: Index | |
5355 | */ | |
5356 | MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); | |
5357 | ||
5358 | /* reg_sbib_buff_size | |
5359 | * Units represented in cells | |
5360 | * Allowed range is 0 to (cap_max_headroom_size - 1) | |
5361 | * Default is 0 | |
5362 | * Access: RW | |
5363 | */ | |
5364 | MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); | |
5365 | ||
5366 | static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, | |
5367 | u32 buff_size) | |
5368 | { | |
5369 | MLXSW_REG_ZERO(sbib, payload); | |
5370 | mlxsw_reg_sbib_local_port_set(payload, local_port); | |
5371 | mlxsw_reg_sbib_buff_size_set(payload, buff_size); | |
5372 | } | |
5373 | ||
8e9658d5 JP |
5374 | static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { |
5375 | MLXSW_REG(sgcr), | |
5376 | MLXSW_REG(spad), | |
5377 | MLXSW_REG(smid), | |
5378 | MLXSW_REG(sspr), | |
5379 | MLXSW_REG(sfdat), | |
5380 | MLXSW_REG(sfd), | |
5381 | MLXSW_REG(sfn), | |
5382 | MLXSW_REG(spms), | |
5383 | MLXSW_REG(spvid), | |
5384 | MLXSW_REG(spvm), | |
5385 | MLXSW_REG(spaft), | |
5386 | MLXSW_REG(sfgc), | |
5387 | MLXSW_REG(sftr), | |
5388 | MLXSW_REG(sfdf), | |
5389 | MLXSW_REG(sldr), | |
5390 | MLXSW_REG(slcr), | |
5391 | MLXSW_REG(slcor), | |
5392 | MLXSW_REG(spmlr), | |
5393 | MLXSW_REG(svfa), | |
5394 | MLXSW_REG(svpe), | |
5395 | MLXSW_REG(sfmr), | |
5396 | MLXSW_REG(spvmlr), | |
76a4c7d3 | 5397 | MLXSW_REG(qpcr), |
8e9658d5 JP |
5398 | MLXSW_REG(qtct), |
5399 | MLXSW_REG(qeec), | |
5400 | MLXSW_REG(pmlp), | |
5401 | MLXSW_REG(pmtu), | |
5402 | MLXSW_REG(ptys), | |
5403 | MLXSW_REG(ppad), | |
5404 | MLXSW_REG(paos), | |
5405 | MLXSW_REG(pfcc), | |
5406 | MLXSW_REG(ppcnt), | |
7136793e | 5407 | MLXSW_REG(plib), |
8e9658d5 JP |
5408 | MLXSW_REG(pptb), |
5409 | MLXSW_REG(pbmc), | |
5410 | MLXSW_REG(pspa), | |
5411 | MLXSW_REG(htgt), | |
5412 | MLXSW_REG(hpkt), | |
5413 | MLXSW_REG(rgcr), | |
5414 | MLXSW_REG(ritr), | |
5415 | MLXSW_REG(ratr), | |
5416 | MLXSW_REG(ralta), | |
5417 | MLXSW_REG(ralst), | |
5418 | MLXSW_REG(raltb), | |
5419 | MLXSW_REG(ralue), | |
5420 | MLXSW_REG(rauht), | |
5421 | MLXSW_REG(raleu), | |
5422 | MLXSW_REG(rauhtd), | |
5423 | MLXSW_REG(mfcr), | |
5424 | MLXSW_REG(mfsc), | |
5425 | MLXSW_REG(mfsm), | |
55c63aaa | 5426 | MLXSW_REG(mfsl), |
8e9658d5 JP |
5427 | MLXSW_REG(mtcap), |
5428 | MLXSW_REG(mtmp), | |
5429 | MLXSW_REG(mpat), | |
5430 | MLXSW_REG(mpar), | |
5431 | MLXSW_REG(mlcr), | |
5432 | MLXSW_REG(sbpr), | |
5433 | MLXSW_REG(sbcm), | |
5434 | MLXSW_REG(sbpm), | |
5435 | MLXSW_REG(sbmm), | |
5436 | MLXSW_REG(sbsr), | |
5437 | MLXSW_REG(sbib), | |
5438 | }; | |
5439 | ||
4ec14b76 IS |
5440 | static inline const char *mlxsw_reg_id_str(u16 reg_id) |
5441 | { | |
8e9658d5 JP |
5442 | const struct mlxsw_reg_info *reg_info; |
5443 | int i; | |
5444 | ||
5445 | for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { | |
5446 | reg_info = mlxsw_reg_infos[i]; | |
5447 | if (reg_info->id == reg_id) | |
5448 | return reg_info->name; | |
4ec14b76 | 5449 | } |
8e9658d5 | 5450 | return "*UNKNOWN*"; |
4ec14b76 IS |
5451 | } |
5452 | ||
5453 | /* PUDE - Port Up / Down Event | |
5454 | * --------------------------- | |
5455 | * Reports the operational state change of a port. | |
5456 | */ | |
5457 | #define MLXSW_REG_PUDE_LEN 0x10 | |
5458 | ||
5459 | /* reg_pude_swid | |
5460 | * Switch partition ID with which to associate the port. | |
5461 | * Access: Index | |
5462 | */ | |
5463 | MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); | |
5464 | ||
5465 | /* reg_pude_local_port | |
5466 | * Local port number. | |
5467 | * Access: Index | |
5468 | */ | |
5469 | MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); | |
5470 | ||
5471 | /* reg_pude_admin_status | |
5472 | * Port administrative state (the desired state). | |
5473 | * 1 - Up. | |
5474 | * 2 - Down. | |
5475 | * 3 - Up once. This means that in case of link failure, the port won't go | |
5476 | * into polling mode, but will wait to be re-enabled by software. | |
5477 | * 4 - Disabled by system. Can only be set by hardware. | |
5478 | * Access: RO | |
5479 | */ | |
5480 | MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); | |
5481 | ||
5482 | /* reg_pude_oper_status | |
5483 | * Port operatioanl state. | |
5484 | * 1 - Up. | |
5485 | * 2 - Down. | |
5486 | * 3 - Down by port failure. This means that the device will not let the | |
5487 | * port up again until explicitly specified by software. | |
5488 | * Access: RO | |
5489 | */ | |
5490 | MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); | |
5491 | ||
5492 | #endif |