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1 | /* |
2 | * drivers/net/ethernet/mellanox/mlxsw/reg.h | |
3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> | |
5 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> | |
6 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. Neither the names of the copyright holders nor the names of its | |
17 | * contributors may be used to endorse or promote products derived from | |
18 | * this software without specific prior written permission. | |
19 | * | |
20 | * Alternatively, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") version 2 as published by the Free | |
22 | * Software Foundation. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
34 | * POSSIBILITY OF SUCH DAMAGE. | |
35 | */ | |
36 | ||
37 | #ifndef _MLXSW_REG_H | |
38 | #define _MLXSW_REG_H | |
39 | ||
40 | #include <linux/string.h> | |
41 | #include <linux/bitops.h> | |
42 | #include <linux/if_vlan.h> | |
43 | ||
44 | #include "item.h" | |
45 | #include "port.h" | |
46 | ||
47 | struct mlxsw_reg_info { | |
48 | u16 id; | |
49 | u16 len; /* In u8 */ | |
50 | }; | |
51 | ||
52 | #define MLXSW_REG(type) (&mlxsw_reg_##type) | |
53 | #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len | |
54 | #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) | |
55 | ||
56 | /* SGCR - Switch General Configuration Register | |
57 | * -------------------------------------------- | |
58 | * This register is used for configuration of the switch capabilities. | |
59 | */ | |
60 | #define MLXSW_REG_SGCR_ID 0x2000 | |
61 | #define MLXSW_REG_SGCR_LEN 0x10 | |
62 | ||
63 | static const struct mlxsw_reg_info mlxsw_reg_sgcr = { | |
64 | .id = MLXSW_REG_SGCR_ID, | |
65 | .len = MLXSW_REG_SGCR_LEN, | |
66 | }; | |
67 | ||
68 | /* reg_sgcr_llb | |
69 | * Link Local Broadcast (Default=0) | |
70 | * When set, all Link Local packets (224.0.0.X) will be treated as broadcast | |
71 | * packets and ignore the IGMP snooping entries. | |
72 | * Access: RW | |
73 | */ | |
74 | MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); | |
75 | ||
76 | static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) | |
77 | { | |
78 | MLXSW_REG_ZERO(sgcr, payload); | |
79 | mlxsw_reg_sgcr_llb_set(payload, !!llb); | |
80 | } | |
81 | ||
82 | /* SPAD - Switch Physical Address Register | |
83 | * --------------------------------------- | |
84 | * The SPAD register configures the switch physical MAC address. | |
85 | */ | |
86 | #define MLXSW_REG_SPAD_ID 0x2002 | |
87 | #define MLXSW_REG_SPAD_LEN 0x10 | |
88 | ||
89 | static const struct mlxsw_reg_info mlxsw_reg_spad = { | |
90 | .id = MLXSW_REG_SPAD_ID, | |
91 | .len = MLXSW_REG_SPAD_LEN, | |
92 | }; | |
93 | ||
94 | /* reg_spad_base_mac | |
95 | * Base MAC address for the switch partitions. | |
96 | * Per switch partition MAC address is equal to: | |
97 | * base_mac + swid | |
98 | * Access: RW | |
99 | */ | |
100 | MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); | |
101 | ||
fabe5483 ER |
102 | /* SMID - Switch Multicast ID |
103 | * -------------------------- | |
104 | * The MID record maps from a MID (Multicast ID), which is a unique identifier | |
105 | * of the multicast group within the stacking domain, into a list of local | |
106 | * ports into which the packet is replicated. | |
107 | */ | |
108 | #define MLXSW_REG_SMID_ID 0x2007 | |
109 | #define MLXSW_REG_SMID_LEN 0x240 | |
110 | ||
111 | static const struct mlxsw_reg_info mlxsw_reg_smid = { | |
112 | .id = MLXSW_REG_SMID_ID, | |
113 | .len = MLXSW_REG_SMID_LEN, | |
114 | }; | |
115 | ||
116 | /* reg_smid_swid | |
117 | * Switch partition ID. | |
118 | * Access: Index | |
119 | */ | |
120 | MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); | |
121 | ||
122 | /* reg_smid_mid | |
123 | * Multicast identifier - global identifier that represents the multicast group | |
124 | * across all devices. | |
125 | * Access: Index | |
126 | */ | |
127 | MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); | |
128 | ||
129 | /* reg_smid_port | |
130 | * Local port memebership (1 bit per port). | |
131 | * Access: RW | |
132 | */ | |
133 | MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); | |
134 | ||
135 | /* reg_smid_port_mask | |
136 | * Local port mask (1 bit per port). | |
137 | * Access: W | |
138 | */ | |
139 | MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); | |
140 | ||
141 | static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, | |
142 | u8 port, bool set) | |
143 | { | |
144 | MLXSW_REG_ZERO(smid, payload); | |
145 | mlxsw_reg_smid_swid_set(payload, 0); | |
146 | mlxsw_reg_smid_mid_set(payload, mid); | |
147 | mlxsw_reg_smid_port_set(payload, port, set); | |
148 | mlxsw_reg_smid_port_mask_set(payload, port, 1); | |
149 | } | |
150 | ||
e61011b5 IS |
151 | /* SSPR - Switch System Port Record Register |
152 | * ----------------------------------------- | |
153 | * Configures the system port to local port mapping. | |
154 | */ | |
155 | #define MLXSW_REG_SSPR_ID 0x2008 | |
156 | #define MLXSW_REG_SSPR_LEN 0x8 | |
157 | ||
158 | static const struct mlxsw_reg_info mlxsw_reg_sspr = { | |
159 | .id = MLXSW_REG_SSPR_ID, | |
160 | .len = MLXSW_REG_SSPR_LEN, | |
161 | }; | |
162 | ||
163 | /* reg_sspr_m | |
164 | * Master - if set, then the record describes the master system port. | |
165 | * This is needed in case a local port is mapped into several system ports | |
166 | * (for multipathing). That number will be reported as the source system | |
167 | * port when packets are forwarded to the CPU. Only one master port is allowed | |
168 | * per local port. | |
169 | * | |
170 | * Note: Must be set for Spectrum. | |
171 | * Access: RW | |
172 | */ | |
173 | MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); | |
174 | ||
175 | /* reg_sspr_local_port | |
176 | * Local port number. | |
177 | * | |
178 | * Access: RW | |
179 | */ | |
180 | MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); | |
181 | ||
182 | /* reg_sspr_sub_port | |
183 | * Virtual port within the physical port. | |
184 | * Should be set to 0 when virtual ports are not enabled on the port. | |
185 | * | |
186 | * Access: RW | |
187 | */ | |
188 | MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); | |
189 | ||
190 | /* reg_sspr_system_port | |
191 | * Unique identifier within the stacking domain that represents all the ports | |
192 | * that are available in the system (external ports). | |
193 | * | |
194 | * Currently, only single-ASIC configurations are supported, so we default to | |
195 | * 1:1 mapping between system ports and local ports. | |
196 | * Access: Index | |
197 | */ | |
198 | MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); | |
199 | ||
200 | static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) | |
201 | { | |
202 | MLXSW_REG_ZERO(sspr, payload); | |
203 | mlxsw_reg_sspr_m_set(payload, 1); | |
204 | mlxsw_reg_sspr_local_port_set(payload, local_port); | |
205 | mlxsw_reg_sspr_sub_port_set(payload, 0); | |
206 | mlxsw_reg_sspr_system_port_set(payload, local_port); | |
207 | } | |
208 | ||
e534a56a JP |
209 | /* SFDAT - Switch Filtering Database Aging Time |
210 | * -------------------------------------------- | |
211 | * Controls the Switch aging time. Aging time is able to be set per Switch | |
212 | * Partition. | |
213 | */ | |
214 | #define MLXSW_REG_SFDAT_ID 0x2009 | |
215 | #define MLXSW_REG_SFDAT_LEN 0x8 | |
216 | ||
217 | static const struct mlxsw_reg_info mlxsw_reg_sfdat = { | |
218 | .id = MLXSW_REG_SFDAT_ID, | |
219 | .len = MLXSW_REG_SFDAT_LEN, | |
220 | }; | |
221 | ||
222 | /* reg_sfdat_swid | |
223 | * Switch partition ID. | |
224 | * Access: Index | |
225 | */ | |
226 | MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); | |
227 | ||
228 | /* reg_sfdat_age_time | |
229 | * Aging time in seconds | |
230 | * Min - 10 seconds | |
231 | * Max - 1,000,000 seconds | |
232 | * Default is 300 seconds. | |
233 | * Access: RW | |
234 | */ | |
235 | MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); | |
236 | ||
237 | static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) | |
238 | { | |
239 | MLXSW_REG_ZERO(sfdat, payload); | |
240 | mlxsw_reg_sfdat_swid_set(payload, 0); | |
241 | mlxsw_reg_sfdat_age_time_set(payload, age_time); | |
242 | } | |
243 | ||
236033b3 JP |
244 | /* SFD - Switch Filtering Database |
245 | * ------------------------------- | |
246 | * The following register defines the access to the filtering database. | |
247 | * The register supports querying, adding, removing and modifying the database. | |
248 | * The access is optimized for bulk updates in which case more than one | |
249 | * FDB record is present in the same command. | |
250 | */ | |
251 | #define MLXSW_REG_SFD_ID 0x200A | |
252 | #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ | |
253 | #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ | |
254 | #define MLXSW_REG_SFD_REC_MAX_COUNT 64 | |
255 | #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ | |
256 | MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) | |
257 | ||
258 | static const struct mlxsw_reg_info mlxsw_reg_sfd = { | |
259 | .id = MLXSW_REG_SFD_ID, | |
260 | .len = MLXSW_REG_SFD_LEN, | |
261 | }; | |
262 | ||
263 | /* reg_sfd_swid | |
264 | * Switch partition ID for queries. Reserved on Write. | |
265 | * Access: Index | |
266 | */ | |
267 | MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); | |
268 | ||
269 | enum mlxsw_reg_sfd_op { | |
270 | /* Dump entire FDB a (process according to record_locator) */ | |
271 | MLXSW_REG_SFD_OP_QUERY_DUMP = 0, | |
272 | /* Query records by {MAC, VID/FID} value */ | |
273 | MLXSW_REG_SFD_OP_QUERY_QUERY = 1, | |
274 | /* Query and clear activity. Query records by {MAC, VID/FID} value */ | |
275 | MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, | |
276 | /* Test. Response indicates if each of the records could be | |
277 | * added to the FDB. | |
278 | */ | |
279 | MLXSW_REG_SFD_OP_WRITE_TEST = 0, | |
280 | /* Add/modify. Aged-out records cannot be added. This command removes | |
281 | * the learning notification of the {MAC, VID/FID}. Response includes | |
282 | * the entries that were added to the FDB. | |
283 | */ | |
284 | MLXSW_REG_SFD_OP_WRITE_EDIT = 1, | |
285 | /* Remove record by {MAC, VID/FID}. This command also removes | |
286 | * the learning notification and aged-out notifications | |
287 | * of the {MAC, VID/FID}. The response provides current (pre-removal) | |
288 | * entries as non-aged-out. | |
289 | */ | |
290 | MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, | |
291 | /* Remove learned notification by {MAC, VID/FID}. The response provides | |
292 | * the removed learning notification. | |
293 | */ | |
294 | MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, | |
295 | }; | |
296 | ||
297 | /* reg_sfd_op | |
298 | * Operation. | |
299 | * Access: OP | |
300 | */ | |
301 | MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); | |
302 | ||
303 | /* reg_sfd_record_locator | |
304 | * Used for querying the FDB. Use record_locator=0 to initiate the | |
305 | * query. When a record is returned, a new record_locator is | |
306 | * returned to be used in the subsequent query. | |
307 | * Reserved for database update. | |
308 | * Access: Index | |
309 | */ | |
310 | MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); | |
311 | ||
312 | /* reg_sfd_num_rec | |
313 | * Request: Number of records to read/add/modify/remove | |
314 | * Response: Number of records read/added/replaced/removed | |
315 | * See above description for more details. | |
316 | * Ranges 0..64 | |
317 | * Access: RW | |
318 | */ | |
319 | MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); | |
320 | ||
321 | static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, | |
322 | u32 record_locator) | |
323 | { | |
324 | MLXSW_REG_ZERO(sfd, payload); | |
325 | mlxsw_reg_sfd_op_set(payload, op); | |
326 | mlxsw_reg_sfd_record_locator_set(payload, record_locator); | |
327 | } | |
328 | ||
329 | /* reg_sfd_rec_swid | |
330 | * Switch partition ID. | |
331 | * Access: Index | |
332 | */ | |
333 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, | |
334 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
335 | ||
336 | enum mlxsw_reg_sfd_rec_type { | |
337 | MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, | |
e4bfbae2 | 338 | MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, |
5230b25f | 339 | MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, |
236033b3 JP |
340 | }; |
341 | ||
342 | /* reg_sfd_rec_type | |
343 | * FDB record type. | |
344 | * Access: RW | |
345 | */ | |
346 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, | |
347 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
348 | ||
349 | enum mlxsw_reg_sfd_rec_policy { | |
350 | /* Replacement disabled, aging disabled. */ | |
351 | MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, | |
352 | /* (mlag remote): Replacement enabled, aging disabled, | |
353 | * learning notification enabled on this port. | |
354 | */ | |
355 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, | |
356 | /* (ingress device): Replacement enabled, aging enabled. */ | |
357 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, | |
358 | }; | |
359 | ||
360 | /* reg_sfd_rec_policy | |
361 | * Policy. | |
362 | * Access: RW | |
363 | */ | |
364 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, | |
365 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
366 | ||
367 | /* reg_sfd_rec_a | |
368 | * Activity. Set for new static entries. Set for static entries if a frame SMAC | |
369 | * lookup hits on the entry. | |
370 | * To clear the a bit, use "query and clear activity" op. | |
371 | * Access: RO | |
372 | */ | |
373 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, | |
374 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
375 | ||
376 | /* reg_sfd_rec_mac | |
377 | * MAC address. | |
378 | * Access: Index | |
379 | */ | |
380 | MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, | |
381 | MLXSW_REG_SFD_REC_LEN, 0x02); | |
382 | ||
383 | enum mlxsw_reg_sfd_rec_action { | |
384 | /* forward */ | |
385 | MLXSW_REG_SFD_REC_ACTION_NOP = 0, | |
386 | /* forward and trap, trap_id is FDB_TRAP */ | |
387 | MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, | |
388 | /* trap and do not forward, trap_id is FDB_TRAP */ | |
389 | MLXSW_REG_SFD_REC_ACTION_TRAP = 3, | |
390 | MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, | |
391 | }; | |
392 | ||
393 | /* reg_sfd_rec_action | |
394 | * Action to apply on the packet. | |
395 | * Note: Dynamic entries can only be configured with NOP action. | |
396 | * Access: RW | |
397 | */ | |
398 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, | |
399 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
400 | ||
401 | /* reg_sfd_uc_sub_port | |
4e9ec083 JP |
402 | * VEPA channel on local port. |
403 | * Valid only if local port is a non-stacking port. Must be 0 if multichannel | |
404 | * VEPA is not enabled. | |
236033b3 JP |
405 | * Access: RW |
406 | */ | |
407 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, | |
408 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
409 | ||
410 | /* reg_sfd_uc_fid_vid | |
411 | * Filtering ID or VLAN ID | |
412 | * For SwitchX and SwitchX-2: | |
413 | * - Dynamic entries (policy 2,3) use FID | |
414 | * - Static entries (policy 0) use VID | |
415 | * - When independent learning is configured, VID=FID | |
416 | * For Spectrum: use FID for both Dynamic and Static entries. | |
417 | * VID should not be used. | |
418 | * Access: Index | |
419 | */ | |
420 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
421 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
422 | ||
423 | /* reg_sfd_uc_system_port | |
424 | * Unique port identifier for the final destination of the packet. | |
425 | * Access: RW | |
426 | */ | |
427 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
428 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
429 | ||
e4bfbae2 JP |
430 | static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, |
431 | enum mlxsw_reg_sfd_rec_type rec_type, | |
e4bfbae2 JP |
432 | const char *mac, |
433 | enum mlxsw_reg_sfd_rec_action action) | |
236033b3 JP |
434 | { |
435 | u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); | |
436 | ||
437 | if (rec_index >= num_rec) | |
438 | mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); | |
439 | mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); | |
e4bfbae2 | 440 | mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); |
236033b3 | 441 | mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); |
e4bfbae2 JP |
442 | mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); |
443 | } | |
444 | ||
445 | static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, | |
446 | enum mlxsw_reg_sfd_rec_policy policy, | |
9de6a80e | 447 | const char *mac, u16 fid_vid, |
e4bfbae2 JP |
448 | enum mlxsw_reg_sfd_rec_action action, |
449 | u8 local_port) | |
450 | { | |
451 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
5230b25f ER |
452 | MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); |
453 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
236033b3 | 454 | mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); |
9de6a80e | 455 | mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); |
236033b3 JP |
456 | mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); |
457 | } | |
458 | ||
75c09280 | 459 | static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, |
9de6a80e | 460 | char *mac, u16 *p_fid_vid, |
75c09280 | 461 | u8 *p_local_port) |
236033b3 JP |
462 | { |
463 | mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); | |
9de6a80e | 464 | *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); |
236033b3 JP |
465 | *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); |
466 | } | |
467 | ||
e4bfbae2 JP |
468 | /* reg_sfd_uc_lag_sub_port |
469 | * LAG sub port. | |
470 | * Must be 0 if multichannel VEPA is not enabled. | |
471 | * Access: RW | |
472 | */ | |
473 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, | |
474 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
475 | ||
476 | /* reg_sfd_uc_lag_fid_vid | |
477 | * Filtering ID or VLAN ID | |
478 | * For SwitchX and SwitchX-2: | |
479 | * - Dynamic entries (policy 2,3) use FID | |
480 | * - Static entries (policy 0) use VID | |
481 | * - When independent learning is configured, VID=FID | |
482 | * For Spectrum: use FID for both Dynamic and Static entries. | |
483 | * VID should not be used. | |
484 | * Access: Index | |
485 | */ | |
486 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
487 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
488 | ||
afd7f979 IS |
489 | /* reg_sfd_uc_lag_lag_vid |
490 | * Indicates VID in case of vFIDs. Reserved for FIDs. | |
491 | * Access: RW | |
492 | */ | |
493 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, | |
494 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
495 | ||
e4bfbae2 JP |
496 | /* reg_sfd_uc_lag_lag_id |
497 | * LAG Identifier - pointer into the LAG descriptor table. | |
498 | * Access: RW | |
499 | */ | |
500 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, | |
501 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
502 | ||
503 | static inline void | |
504 | mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, | |
505 | enum mlxsw_reg_sfd_rec_policy policy, | |
9de6a80e | 506 | const char *mac, u16 fid_vid, |
afd7f979 | 507 | enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, |
e4bfbae2 JP |
508 | u16 lag_id) |
509 | { | |
510 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
511 | MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, | |
5230b25f ER |
512 | mac, action); |
513 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
e4bfbae2 | 514 | mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); |
9de6a80e | 515 | mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); |
afd7f979 | 516 | mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); |
e4bfbae2 JP |
517 | mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); |
518 | } | |
519 | ||
520 | static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, | |
521 | char *mac, u16 *p_vid, | |
522 | u16 *p_lag_id) | |
523 | { | |
524 | mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); | |
525 | *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); | |
526 | *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); | |
527 | } | |
528 | ||
5230b25f ER |
529 | /* reg_sfd_mc_pgi |
530 | * | |
531 | * Multicast port group index - index into the port group table. | |
532 | * Value 0x1FFF indicates the pgi should point to the MID entry. | |
533 | * For Spectrum this value must be set to 0x1FFF | |
534 | * Access: RW | |
535 | */ | |
536 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, | |
537 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
538 | ||
539 | /* reg_sfd_mc_fid_vid | |
540 | * | |
541 | * Filtering ID or VLAN ID | |
542 | * Access: Index | |
543 | */ | |
544 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
545 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
546 | ||
547 | /* reg_sfd_mc_mid | |
548 | * | |
549 | * Multicast identifier - global identifier that represents the multicast | |
550 | * group across all devices. | |
551 | * Access: RW | |
552 | */ | |
553 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
554 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
555 | ||
556 | static inline void | |
557 | mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, | |
558 | const char *mac, u16 fid_vid, | |
559 | enum mlxsw_reg_sfd_rec_action action, u16 mid) | |
560 | { | |
561 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
562 | MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); | |
563 | mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); | |
564 | mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); | |
565 | mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); | |
566 | } | |
567 | ||
f5d88f58 JP |
568 | /* SFN - Switch FDB Notification Register |
569 | * ------------------------------------------- | |
570 | * The switch provides notifications on newly learned FDB entries and | |
571 | * aged out entries. The notifications can be polled by software. | |
572 | */ | |
573 | #define MLXSW_REG_SFN_ID 0x200B | |
574 | #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ | |
575 | #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ | |
576 | #define MLXSW_REG_SFN_REC_MAX_COUNT 64 | |
577 | #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ | |
578 | MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) | |
579 | ||
580 | static const struct mlxsw_reg_info mlxsw_reg_sfn = { | |
581 | .id = MLXSW_REG_SFN_ID, | |
582 | .len = MLXSW_REG_SFN_LEN, | |
583 | }; | |
584 | ||
585 | /* reg_sfn_swid | |
586 | * Switch partition ID. | |
587 | * Access: Index | |
588 | */ | |
589 | MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); | |
590 | ||
591 | /* reg_sfn_num_rec | |
592 | * Request: Number of learned notifications and aged-out notification | |
593 | * records requested. | |
594 | * Response: Number of notification records returned (must be smaller | |
595 | * than or equal to the value requested) | |
596 | * Ranges 0..64 | |
597 | * Access: OP | |
598 | */ | |
599 | MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); | |
600 | ||
601 | static inline void mlxsw_reg_sfn_pack(char *payload) | |
602 | { | |
603 | MLXSW_REG_ZERO(sfn, payload); | |
604 | mlxsw_reg_sfn_swid_set(payload, 0); | |
605 | mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); | |
606 | } | |
607 | ||
608 | /* reg_sfn_rec_swid | |
609 | * Switch partition ID. | |
610 | * Access: RO | |
611 | */ | |
612 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, | |
613 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
614 | ||
615 | enum mlxsw_reg_sfn_rec_type { | |
616 | /* MAC addresses learned on a regular port. */ | |
617 | MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, | |
3b71571c JP |
618 | /* MAC addresses learned on a LAG port. */ |
619 | MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, | |
620 | /* Aged-out MAC address on a regular port. */ | |
f5d88f58 | 621 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, |
3b71571c JP |
622 | /* Aged-out MAC address on a LAG port. */ |
623 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, | |
f5d88f58 JP |
624 | }; |
625 | ||
626 | /* reg_sfn_rec_type | |
627 | * Notification record type. | |
628 | * Access: RO | |
629 | */ | |
630 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, | |
631 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
632 | ||
633 | /* reg_sfn_rec_mac | |
634 | * MAC address. | |
635 | * Access: RO | |
636 | */ | |
637 | MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, | |
638 | MLXSW_REG_SFN_REC_LEN, 0x02); | |
639 | ||
8316f087 | 640 | /* reg_sfn_mac_sub_port |
f5d88f58 JP |
641 | * VEPA channel on the local port. |
642 | * 0 if multichannel VEPA is not enabled. | |
643 | * Access: RO | |
644 | */ | |
645 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, | |
646 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
647 | ||
8316f087 | 648 | /* reg_sfn_mac_fid |
f5d88f58 JP |
649 | * Filtering identifier. |
650 | * Access: RO | |
651 | */ | |
652 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
653 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
654 | ||
8316f087 | 655 | /* reg_sfn_mac_system_port |
f5d88f58 JP |
656 | * Unique port identifier for the final destination of the packet. |
657 | * Access: RO | |
658 | */ | |
659 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
660 | MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
661 | ||
662 | static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, | |
663 | char *mac, u16 *p_vid, | |
664 | u8 *p_local_port) | |
665 | { | |
666 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
667 | *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
668 | *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); | |
669 | } | |
670 | ||
3b71571c JP |
671 | /* reg_sfn_mac_lag_lag_id |
672 | * LAG ID (pointer into the LAG descriptor table). | |
673 | * Access: RO | |
674 | */ | |
675 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, | |
676 | MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
677 | ||
678 | static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, | |
679 | char *mac, u16 *p_vid, | |
680 | u16 *p_lag_id) | |
681 | { | |
682 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
683 | *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
684 | *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); | |
685 | } | |
686 | ||
4ec14b76 IS |
687 | /* SPMS - Switch Port MSTP/RSTP State Register |
688 | * ------------------------------------------- | |
689 | * Configures the spanning tree state of a physical port. | |
690 | */ | |
3f0effd1 | 691 | #define MLXSW_REG_SPMS_ID 0x200D |
4ec14b76 IS |
692 | #define MLXSW_REG_SPMS_LEN 0x404 |
693 | ||
694 | static const struct mlxsw_reg_info mlxsw_reg_spms = { | |
695 | .id = MLXSW_REG_SPMS_ID, | |
696 | .len = MLXSW_REG_SPMS_LEN, | |
697 | }; | |
698 | ||
699 | /* reg_spms_local_port | |
700 | * Local port number. | |
701 | * Access: Index | |
702 | */ | |
703 | MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); | |
704 | ||
705 | enum mlxsw_reg_spms_state { | |
706 | MLXSW_REG_SPMS_STATE_NO_CHANGE, | |
707 | MLXSW_REG_SPMS_STATE_DISCARDING, | |
708 | MLXSW_REG_SPMS_STATE_LEARNING, | |
709 | MLXSW_REG_SPMS_STATE_FORWARDING, | |
710 | }; | |
711 | ||
712 | /* reg_spms_state | |
713 | * Spanning tree state of each VLAN ID (VID) of the local port. | |
714 | * 0 - Do not change spanning tree state (used only when writing). | |
715 | * 1 - Discarding. No learning or forwarding to/from this port (default). | |
716 | * 2 - Learning. Port is learning, but not forwarding. | |
717 | * 3 - Forwarding. Port is learning and forwarding. | |
718 | * Access: RW | |
719 | */ | |
720 | MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); | |
721 | ||
ebb7963f | 722 | static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) |
4ec14b76 IS |
723 | { |
724 | MLXSW_REG_ZERO(spms, payload); | |
725 | mlxsw_reg_spms_local_port_set(payload, local_port); | |
ebb7963f JP |
726 | } |
727 | ||
728 | static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, | |
729 | enum mlxsw_reg_spms_state state) | |
730 | { | |
4ec14b76 IS |
731 | mlxsw_reg_spms_state_set(payload, vid, state); |
732 | } | |
733 | ||
b2e345f9 ER |
734 | /* SPVID - Switch Port VID |
735 | * ----------------------- | |
736 | * The switch port VID configures the default VID for a port. | |
737 | */ | |
738 | #define MLXSW_REG_SPVID_ID 0x200E | |
739 | #define MLXSW_REG_SPVID_LEN 0x08 | |
740 | ||
741 | static const struct mlxsw_reg_info mlxsw_reg_spvid = { | |
742 | .id = MLXSW_REG_SPVID_ID, | |
743 | .len = MLXSW_REG_SPVID_LEN, | |
744 | }; | |
745 | ||
746 | /* reg_spvid_local_port | |
747 | * Local port number. | |
748 | * Access: Index | |
749 | */ | |
750 | MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); | |
751 | ||
752 | /* reg_spvid_sub_port | |
753 | * Virtual port within the physical port. | |
754 | * Should be set to 0 when virtual ports are not enabled on the port. | |
755 | * Access: Index | |
756 | */ | |
757 | MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); | |
758 | ||
759 | /* reg_spvid_pvid | |
760 | * Port default VID | |
761 | * Access: RW | |
762 | */ | |
763 | MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); | |
764 | ||
765 | static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) | |
766 | { | |
767 | MLXSW_REG_ZERO(spvid, payload); | |
768 | mlxsw_reg_spvid_local_port_set(payload, local_port); | |
769 | mlxsw_reg_spvid_pvid_set(payload, pvid); | |
770 | } | |
771 | ||
772 | /* SPVM - Switch Port VLAN Membership | |
773 | * ---------------------------------- | |
774 | * The Switch Port VLAN Membership register configures the VLAN membership | |
775 | * of a port in a VLAN denoted by VID. VLAN membership is managed per | |
776 | * virtual port. The register can be used to add and remove VID(s) from a port. | |
777 | */ | |
778 | #define MLXSW_REG_SPVM_ID 0x200F | |
779 | #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ | |
780 | #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ | |
781 | #define MLXSW_REG_SPVM_REC_MAX_COUNT 256 | |
782 | #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ | |
783 | MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) | |
784 | ||
785 | static const struct mlxsw_reg_info mlxsw_reg_spvm = { | |
786 | .id = MLXSW_REG_SPVM_ID, | |
787 | .len = MLXSW_REG_SPVM_LEN, | |
788 | }; | |
789 | ||
790 | /* reg_spvm_pt | |
791 | * Priority tagged. If this bit is set, packets forwarded to the port with | |
792 | * untagged VLAN membership (u bit is set) will be tagged with priority tag | |
793 | * (VID=0) | |
794 | * Access: RW | |
795 | */ | |
796 | MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); | |
797 | ||
798 | /* reg_spvm_pte | |
799 | * Priority Tagged Update Enable. On Write operations, if this bit is cleared, | |
800 | * the pt bit will NOT be updated. To update the pt bit, pte must be set. | |
801 | * Access: WO | |
802 | */ | |
803 | MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); | |
804 | ||
805 | /* reg_spvm_local_port | |
806 | * Local port number. | |
807 | * Access: Index | |
808 | */ | |
809 | MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); | |
810 | ||
811 | /* reg_spvm_sub_port | |
812 | * Virtual port within the physical port. | |
813 | * Should be set to 0 when virtual ports are not enabled on the port. | |
814 | * Access: Index | |
815 | */ | |
816 | MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); | |
817 | ||
818 | /* reg_spvm_num_rec | |
819 | * Number of records to update. Each record contains: i, e, u, vid. | |
820 | * Access: OP | |
821 | */ | |
822 | MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); | |
823 | ||
824 | /* reg_spvm_rec_i | |
825 | * Ingress membership in VLAN ID. | |
826 | * Access: Index | |
827 | */ | |
828 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, | |
829 | MLXSW_REG_SPVM_BASE_LEN, 14, 1, | |
830 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
831 | ||
832 | /* reg_spvm_rec_e | |
833 | * Egress membership in VLAN ID. | |
834 | * Access: Index | |
835 | */ | |
836 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, | |
837 | MLXSW_REG_SPVM_BASE_LEN, 13, 1, | |
838 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
839 | ||
840 | /* reg_spvm_rec_u | |
841 | * Untagged - port is an untagged member - egress transmission uses untagged | |
842 | * frames on VID<n> | |
843 | * Access: Index | |
844 | */ | |
845 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, | |
846 | MLXSW_REG_SPVM_BASE_LEN, 12, 1, | |
847 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
848 | ||
849 | /* reg_spvm_rec_vid | |
850 | * Egress membership in VLAN ID. | |
851 | * Access: Index | |
852 | */ | |
853 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, | |
854 | MLXSW_REG_SPVM_BASE_LEN, 0, 12, | |
855 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
856 | ||
857 | static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, | |
858 | u16 vid_begin, u16 vid_end, | |
859 | bool is_member, bool untagged) | |
860 | { | |
861 | int size = vid_end - vid_begin + 1; | |
862 | int i; | |
863 | ||
864 | MLXSW_REG_ZERO(spvm, payload); | |
865 | mlxsw_reg_spvm_local_port_set(payload, local_port); | |
866 | mlxsw_reg_spvm_num_rec_set(payload, size); | |
867 | ||
868 | for (i = 0; i < size; i++) { | |
869 | mlxsw_reg_spvm_rec_i_set(payload, i, is_member); | |
870 | mlxsw_reg_spvm_rec_e_set(payload, i, is_member); | |
871 | mlxsw_reg_spvm_rec_u_set(payload, i, untagged); | |
872 | mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); | |
873 | } | |
874 | } | |
875 | ||
148f472d IS |
876 | /* SPAFT - Switch Port Acceptable Frame Types |
877 | * ------------------------------------------ | |
878 | * The Switch Port Acceptable Frame Types register configures the frame | |
879 | * admittance of the port. | |
880 | */ | |
881 | #define MLXSW_REG_SPAFT_ID 0x2010 | |
882 | #define MLXSW_REG_SPAFT_LEN 0x08 | |
883 | ||
884 | static const struct mlxsw_reg_info mlxsw_reg_spaft = { | |
885 | .id = MLXSW_REG_SPAFT_ID, | |
886 | .len = MLXSW_REG_SPAFT_LEN, | |
887 | }; | |
888 | ||
889 | /* reg_spaft_local_port | |
890 | * Local port number. | |
891 | * Access: Index | |
892 | * | |
893 | * Note: CPU port is not supported (all tag types are allowed). | |
894 | */ | |
895 | MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); | |
896 | ||
897 | /* reg_spaft_sub_port | |
898 | * Virtual port within the physical port. | |
899 | * Should be set to 0 when virtual ports are not enabled on the port. | |
900 | * Access: RW | |
901 | */ | |
902 | MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); | |
903 | ||
904 | /* reg_spaft_allow_untagged | |
905 | * When set, untagged frames on the ingress are allowed (default). | |
906 | * Access: RW | |
907 | */ | |
908 | MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); | |
909 | ||
910 | /* reg_spaft_allow_prio_tagged | |
911 | * When set, priority tagged frames on the ingress are allowed (default). | |
912 | * Access: RW | |
913 | */ | |
914 | MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); | |
915 | ||
916 | /* reg_spaft_allow_tagged | |
917 | * When set, tagged frames on the ingress are allowed (default). | |
918 | * Access: RW | |
919 | */ | |
920 | MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); | |
921 | ||
922 | static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, | |
923 | bool allow_untagged) | |
924 | { | |
925 | MLXSW_REG_ZERO(spaft, payload); | |
926 | mlxsw_reg_spaft_local_port_set(payload, local_port); | |
927 | mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); | |
928 | mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); | |
929 | mlxsw_reg_spaft_allow_tagged_set(payload, true); | |
930 | } | |
931 | ||
4ec14b76 IS |
932 | /* SFGC - Switch Flooding Group Configuration |
933 | * ------------------------------------------ | |
934 | * The following register controls the association of flooding tables and MIDs | |
935 | * to packet types used for flooding. | |
936 | */ | |
36b78e8a | 937 | #define MLXSW_REG_SFGC_ID 0x2011 |
4ec14b76 IS |
938 | #define MLXSW_REG_SFGC_LEN 0x10 |
939 | ||
940 | static const struct mlxsw_reg_info mlxsw_reg_sfgc = { | |
941 | .id = MLXSW_REG_SFGC_ID, | |
942 | .len = MLXSW_REG_SFGC_LEN, | |
943 | }; | |
944 | ||
945 | enum mlxsw_reg_sfgc_type { | |
fa6ad058 IS |
946 | MLXSW_REG_SFGC_TYPE_BROADCAST, |
947 | MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, | |
948 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, | |
949 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, | |
950 | MLXSW_REG_SFGC_TYPE_RESERVED, | |
951 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, | |
952 | MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, | |
953 | MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, | |
954 | MLXSW_REG_SFGC_TYPE_MAX, | |
4ec14b76 IS |
955 | }; |
956 | ||
957 | /* reg_sfgc_type | |
958 | * The traffic type to reach the flooding table. | |
959 | * Access: Index | |
960 | */ | |
961 | MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); | |
962 | ||
963 | enum mlxsw_reg_sfgc_bridge_type { | |
964 | MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, | |
965 | MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, | |
966 | }; | |
967 | ||
968 | /* reg_sfgc_bridge_type | |
969 | * Access: Index | |
970 | * | |
971 | * Note: SwitchX-2 only supports 802.1Q mode. | |
972 | */ | |
973 | MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); | |
974 | ||
975 | enum mlxsw_flood_table_type { | |
976 | MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, | |
977 | MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, | |
978 | MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, | |
979 | MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3, | |
980 | MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, | |
981 | }; | |
982 | ||
983 | /* reg_sfgc_table_type | |
984 | * See mlxsw_flood_table_type | |
985 | * Access: RW | |
986 | * | |
987 | * Note: FID offset and FID types are not supported in SwitchX-2. | |
988 | */ | |
989 | MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); | |
990 | ||
991 | /* reg_sfgc_flood_table | |
992 | * Flooding table index to associate with the specific type on the specific | |
993 | * switch partition. | |
994 | * Access: RW | |
995 | */ | |
996 | MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); | |
997 | ||
998 | /* reg_sfgc_mid | |
999 | * The multicast ID for the swid. Not supported for Spectrum | |
1000 | * Access: RW | |
1001 | */ | |
1002 | MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); | |
1003 | ||
1004 | /* reg_sfgc_counter_set_type | |
1005 | * Counter Set Type for flow counters. | |
1006 | * Access: RW | |
1007 | */ | |
1008 | MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); | |
1009 | ||
1010 | /* reg_sfgc_counter_index | |
1011 | * Counter Index for flow counters. | |
1012 | * Access: RW | |
1013 | */ | |
1014 | MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); | |
1015 | ||
1016 | static inline void | |
1017 | mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, | |
1018 | enum mlxsw_reg_sfgc_bridge_type bridge_type, | |
1019 | enum mlxsw_flood_table_type table_type, | |
1020 | unsigned int flood_table) | |
1021 | { | |
1022 | MLXSW_REG_ZERO(sfgc, payload); | |
1023 | mlxsw_reg_sfgc_type_set(payload, type); | |
1024 | mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); | |
1025 | mlxsw_reg_sfgc_table_type_set(payload, table_type); | |
1026 | mlxsw_reg_sfgc_flood_table_set(payload, flood_table); | |
1027 | mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); | |
1028 | } | |
1029 | ||
1030 | /* SFTR - Switch Flooding Table Register | |
1031 | * ------------------------------------- | |
1032 | * The switch flooding table is used for flooding packet replication. The table | |
1033 | * defines a bit mask of ports for packet replication. | |
1034 | */ | |
1035 | #define MLXSW_REG_SFTR_ID 0x2012 | |
1036 | #define MLXSW_REG_SFTR_LEN 0x420 | |
1037 | ||
1038 | static const struct mlxsw_reg_info mlxsw_reg_sftr = { | |
1039 | .id = MLXSW_REG_SFTR_ID, | |
1040 | .len = MLXSW_REG_SFTR_LEN, | |
1041 | }; | |
1042 | ||
1043 | /* reg_sftr_swid | |
1044 | * Switch partition ID with which to associate the port. | |
1045 | * Access: Index | |
1046 | */ | |
1047 | MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); | |
1048 | ||
1049 | /* reg_sftr_flood_table | |
1050 | * Flooding table index to associate with the specific type on the specific | |
1051 | * switch partition. | |
1052 | * Access: Index | |
1053 | */ | |
1054 | MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); | |
1055 | ||
1056 | /* reg_sftr_index | |
1057 | * Index. Used as an index into the Flooding Table in case the table is | |
1058 | * configured to use VID / FID or FID Offset. | |
1059 | * Access: Index | |
1060 | */ | |
1061 | MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); | |
1062 | ||
1063 | /* reg_sftr_table_type | |
1064 | * See mlxsw_flood_table_type | |
1065 | * Access: RW | |
1066 | */ | |
1067 | MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); | |
1068 | ||
1069 | /* reg_sftr_range | |
1070 | * Range of entries to update | |
1071 | * Access: Index | |
1072 | */ | |
1073 | MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); | |
1074 | ||
1075 | /* reg_sftr_port | |
1076 | * Local port membership (1 bit per port). | |
1077 | * Access: RW | |
1078 | */ | |
1079 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); | |
1080 | ||
1081 | /* reg_sftr_cpu_port_mask | |
1082 | * CPU port mask (1 bit per port). | |
1083 | * Access: W | |
1084 | */ | |
1085 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); | |
1086 | ||
1087 | static inline void mlxsw_reg_sftr_pack(char *payload, | |
1088 | unsigned int flood_table, | |
1089 | unsigned int index, | |
1090 | enum mlxsw_flood_table_type table_type, | |
bc2055f8 | 1091 | unsigned int range, u8 port, bool set) |
4ec14b76 IS |
1092 | { |
1093 | MLXSW_REG_ZERO(sftr, payload); | |
1094 | mlxsw_reg_sftr_swid_set(payload, 0); | |
1095 | mlxsw_reg_sftr_flood_table_set(payload, flood_table); | |
1096 | mlxsw_reg_sftr_index_set(payload, index); | |
1097 | mlxsw_reg_sftr_table_type_set(payload, table_type); | |
1098 | mlxsw_reg_sftr_range_set(payload, range); | |
bc2055f8 IS |
1099 | mlxsw_reg_sftr_port_set(payload, port, set); |
1100 | mlxsw_reg_sftr_port_mask_set(payload, port, 1); | |
4ec14b76 IS |
1101 | } |
1102 | ||
41933271 IS |
1103 | /* SFDF - Switch Filtering DB Flush |
1104 | * -------------------------------- | |
1105 | * The switch filtering DB flush register is used to flush the FDB. | |
1106 | * Note that FDB notifications are flushed as well. | |
1107 | */ | |
1108 | #define MLXSW_REG_SFDF_ID 0x2013 | |
1109 | #define MLXSW_REG_SFDF_LEN 0x14 | |
1110 | ||
1111 | static const struct mlxsw_reg_info mlxsw_reg_sfdf = { | |
1112 | .id = MLXSW_REG_SFDF_ID, | |
1113 | .len = MLXSW_REG_SFDF_LEN, | |
1114 | }; | |
1115 | ||
1116 | /* reg_sfdf_swid | |
1117 | * Switch partition ID. | |
1118 | * Access: Index | |
1119 | */ | |
1120 | MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); | |
1121 | ||
1122 | enum mlxsw_reg_sfdf_flush_type { | |
1123 | MLXSW_REG_SFDF_FLUSH_PER_SWID, | |
1124 | MLXSW_REG_SFDF_FLUSH_PER_FID, | |
1125 | MLXSW_REG_SFDF_FLUSH_PER_PORT, | |
1126 | MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, | |
1127 | MLXSW_REG_SFDF_FLUSH_PER_LAG, | |
1128 | MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, | |
1129 | }; | |
1130 | ||
1131 | /* reg_sfdf_flush_type | |
1132 | * Flush type. | |
1133 | * 0 - All SWID dynamic entries are flushed. | |
1134 | * 1 - All FID dynamic entries are flushed. | |
1135 | * 2 - All dynamic entries pointing to port are flushed. | |
1136 | * 3 - All FID dynamic entries pointing to port are flushed. | |
1137 | * 4 - All dynamic entries pointing to LAG are flushed. | |
1138 | * 5 - All FID dynamic entries pointing to LAG are flushed. | |
1139 | * Access: RW | |
1140 | */ | |
1141 | MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); | |
1142 | ||
1143 | /* reg_sfdf_flush_static | |
1144 | * Static. | |
1145 | * 0 - Flush only dynamic entries. | |
1146 | * 1 - Flush both dynamic and static entries. | |
1147 | * Access: RW | |
1148 | */ | |
1149 | MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); | |
1150 | ||
1151 | static inline void mlxsw_reg_sfdf_pack(char *payload, | |
1152 | enum mlxsw_reg_sfdf_flush_type type) | |
1153 | { | |
1154 | MLXSW_REG_ZERO(sfdf, payload); | |
1155 | mlxsw_reg_sfdf_flush_type_set(payload, type); | |
1156 | mlxsw_reg_sfdf_flush_static_set(payload, true); | |
1157 | } | |
1158 | ||
1159 | /* reg_sfdf_fid | |
1160 | * FID to flush. | |
1161 | * Access: RW | |
1162 | */ | |
1163 | MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); | |
1164 | ||
1165 | /* reg_sfdf_system_port | |
1166 | * Port to flush. | |
1167 | * Access: RW | |
1168 | */ | |
1169 | MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); | |
1170 | ||
1171 | /* reg_sfdf_port_fid_system_port | |
1172 | * Port to flush, pointed to by FID. | |
1173 | * Access: RW | |
1174 | */ | |
1175 | MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); | |
1176 | ||
1177 | /* reg_sfdf_lag_id | |
1178 | * LAG ID to flush. | |
1179 | * Access: RW | |
1180 | */ | |
1181 | MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); | |
1182 | ||
1183 | /* reg_sfdf_lag_fid_lag_id | |
1184 | * LAG ID to flush, pointed to by FID. | |
1185 | * Access: RW | |
1186 | */ | |
1187 | MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); | |
1188 | ||
d1d40be0 JP |
1189 | /* SLDR - Switch LAG Descriptor Register |
1190 | * ----------------------------------------- | |
1191 | * The switch LAG descriptor register is populated by LAG descriptors. | |
1192 | * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to | |
1193 | * max_lag-1. | |
1194 | */ | |
1195 | #define MLXSW_REG_SLDR_ID 0x2014 | |
1196 | #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ | |
1197 | ||
1198 | static const struct mlxsw_reg_info mlxsw_reg_sldr = { | |
1199 | .id = MLXSW_REG_SLDR_ID, | |
1200 | .len = MLXSW_REG_SLDR_LEN, | |
1201 | }; | |
1202 | ||
1203 | enum mlxsw_reg_sldr_op { | |
1204 | /* Indicates a creation of a new LAG-ID, lag_id must be valid */ | |
1205 | MLXSW_REG_SLDR_OP_LAG_CREATE, | |
1206 | MLXSW_REG_SLDR_OP_LAG_DESTROY, | |
1207 | /* Ports that appear in the list have the Distributor enabled */ | |
1208 | MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, | |
1209 | /* Removes ports from the disributor list */ | |
1210 | MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, | |
1211 | }; | |
1212 | ||
1213 | /* reg_sldr_op | |
1214 | * Operation. | |
1215 | * Access: RW | |
1216 | */ | |
1217 | MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); | |
1218 | ||
1219 | /* reg_sldr_lag_id | |
1220 | * LAG identifier. The lag_id is the index into the LAG descriptor table. | |
1221 | * Access: Index | |
1222 | */ | |
1223 | MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); | |
1224 | ||
1225 | static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) | |
1226 | { | |
1227 | MLXSW_REG_ZERO(sldr, payload); | |
1228 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); | |
1229 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1230 | } | |
1231 | ||
1232 | static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) | |
1233 | { | |
1234 | MLXSW_REG_ZERO(sldr, payload); | |
1235 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); | |
1236 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1237 | } | |
1238 | ||
1239 | /* reg_sldr_num_ports | |
1240 | * The number of member ports of the LAG. | |
1241 | * Reserved for Create / Destroy operations | |
1242 | * For Add / Remove operations - indicates the number of ports in the list. | |
1243 | * Access: RW | |
1244 | */ | |
1245 | MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); | |
1246 | ||
1247 | /* reg_sldr_system_port | |
1248 | * System port. | |
1249 | * Access: RW | |
1250 | */ | |
1251 | MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); | |
1252 | ||
1253 | static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, | |
1254 | u8 local_port) | |
1255 | { | |
1256 | MLXSW_REG_ZERO(sldr, payload); | |
1257 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); | |
1258 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1259 | mlxsw_reg_sldr_num_ports_set(payload, 1); | |
1260 | mlxsw_reg_sldr_system_port_set(payload, 0, local_port); | |
1261 | } | |
1262 | ||
1263 | static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, | |
1264 | u8 local_port) | |
1265 | { | |
1266 | MLXSW_REG_ZERO(sldr, payload); | |
1267 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); | |
1268 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1269 | mlxsw_reg_sldr_num_ports_set(payload, 1); | |
1270 | mlxsw_reg_sldr_system_port_set(payload, 0, local_port); | |
1271 | } | |
1272 | ||
1273 | /* SLCR - Switch LAG Configuration 2 Register | |
1274 | * ------------------------------------------- | |
1275 | * The Switch LAG Configuration register is used for configuring the | |
1276 | * LAG properties of the switch. | |
1277 | */ | |
1278 | #define MLXSW_REG_SLCR_ID 0x2015 | |
1279 | #define MLXSW_REG_SLCR_LEN 0x10 | |
1280 | ||
1281 | static const struct mlxsw_reg_info mlxsw_reg_slcr = { | |
1282 | .id = MLXSW_REG_SLCR_ID, | |
1283 | .len = MLXSW_REG_SLCR_LEN, | |
1284 | }; | |
1285 | ||
1286 | enum mlxsw_reg_slcr_pp { | |
1287 | /* Global Configuration (for all ports) */ | |
1288 | MLXSW_REG_SLCR_PP_GLOBAL, | |
1289 | /* Per port configuration, based on local_port field */ | |
1290 | MLXSW_REG_SLCR_PP_PER_PORT, | |
1291 | }; | |
1292 | ||
1293 | /* reg_slcr_pp | |
1294 | * Per Port Configuration | |
1295 | * Note: Reading at Global mode results in reading port 1 configuration. | |
1296 | * Access: Index | |
1297 | */ | |
1298 | MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); | |
1299 | ||
1300 | /* reg_slcr_local_port | |
1301 | * Local port number | |
1302 | * Supported from CPU port | |
1303 | * Not supported from router port | |
1304 | * Reserved when pp = Global Configuration | |
1305 | * Access: Index | |
1306 | */ | |
1307 | MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); | |
1308 | ||
1309 | enum mlxsw_reg_slcr_type { | |
1310 | MLXSW_REG_SLCR_TYPE_CRC, /* default */ | |
1311 | MLXSW_REG_SLCR_TYPE_XOR, | |
1312 | MLXSW_REG_SLCR_TYPE_RANDOM, | |
1313 | }; | |
1314 | ||
1315 | /* reg_slcr_type | |
1316 | * Hash type | |
1317 | * Access: RW | |
1318 | */ | |
1319 | MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); | |
1320 | ||
1321 | /* Ingress port */ | |
1322 | #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) | |
1323 | /* SMAC - for IPv4 and IPv6 packets */ | |
1324 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) | |
1325 | /* SMAC - for non-IP packets */ | |
1326 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) | |
1327 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ | |
1328 | (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ | |
1329 | MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) | |
1330 | /* DMAC - for IPv4 and IPv6 packets */ | |
1331 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) | |
1332 | /* DMAC - for non-IP packets */ | |
1333 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) | |
1334 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ | |
1335 | (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ | |
1336 | MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) | |
1337 | /* Ethertype - for IPv4 and IPv6 packets */ | |
1338 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) | |
1339 | /* Ethertype - for non-IP packets */ | |
1340 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) | |
1341 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ | |
1342 | (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ | |
1343 | MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) | |
1344 | /* VLAN ID - for IPv4 and IPv6 packets */ | |
1345 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) | |
1346 | /* VLAN ID - for non-IP packets */ | |
1347 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) | |
1348 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ | |
1349 | (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ | |
1350 | MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) | |
1351 | /* Source IP address (can be IPv4 or IPv6) */ | |
1352 | #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) | |
1353 | /* Destination IP address (can be IPv4 or IPv6) */ | |
1354 | #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) | |
1355 | /* TCP/UDP source port */ | |
1356 | #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) | |
1357 | /* TCP/UDP destination port*/ | |
1358 | #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) | |
1359 | /* IPv4 Protocol/IPv6 Next Header */ | |
1360 | #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) | |
1361 | /* IPv6 Flow label */ | |
1362 | #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) | |
1363 | /* SID - FCoE source ID */ | |
1364 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) | |
1365 | /* DID - FCoE destination ID */ | |
1366 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) | |
1367 | /* OXID - FCoE originator exchange ID */ | |
1368 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) | |
1369 | /* Destination QP number - for RoCE packets */ | |
1370 | #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) | |
1371 | ||
1372 | /* reg_slcr_lag_hash | |
1373 | * LAG hashing configuration. This is a bitmask, in which each set | |
1374 | * bit includes the corresponding item in the LAG hash calculation. | |
1375 | * The default lag_hash contains SMAC, DMAC, VLANID and | |
1376 | * Ethertype (for all packet types). | |
1377 | * Access: RW | |
1378 | */ | |
1379 | MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); | |
1380 | ||
1381 | static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) | |
1382 | { | |
1383 | MLXSW_REG_ZERO(slcr, payload); | |
1384 | mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); | |
1385 | mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR); | |
1386 | mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); | |
1387 | } | |
1388 | ||
1389 | /* SLCOR - Switch LAG Collector Register | |
1390 | * ------------------------------------- | |
1391 | * The Switch LAG Collector register controls the Local Port membership | |
1392 | * in a LAG and enablement of the collector. | |
1393 | */ | |
1394 | #define MLXSW_REG_SLCOR_ID 0x2016 | |
1395 | #define MLXSW_REG_SLCOR_LEN 0x10 | |
1396 | ||
1397 | static const struct mlxsw_reg_info mlxsw_reg_slcor = { | |
1398 | .id = MLXSW_REG_SLCOR_ID, | |
1399 | .len = MLXSW_REG_SLCOR_LEN, | |
1400 | }; | |
1401 | ||
1402 | enum mlxsw_reg_slcor_col { | |
1403 | /* Port is added with collector disabled */ | |
1404 | MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, | |
1405 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, | |
1406 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, | |
1407 | MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, | |
1408 | }; | |
1409 | ||
1410 | /* reg_slcor_col | |
1411 | * Collector configuration | |
1412 | * Access: RW | |
1413 | */ | |
1414 | MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); | |
1415 | ||
1416 | /* reg_slcor_local_port | |
1417 | * Local port number | |
1418 | * Not supported for CPU port | |
1419 | * Access: Index | |
1420 | */ | |
1421 | MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); | |
1422 | ||
1423 | /* reg_slcor_lag_id | |
1424 | * LAG Identifier. Index into the LAG descriptor table. | |
1425 | * Access: Index | |
1426 | */ | |
1427 | MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); | |
1428 | ||
1429 | /* reg_slcor_port_index | |
1430 | * Port index in the LAG list. Only valid on Add Port to LAG col. | |
1431 | * Valid range is from 0 to cap_max_lag_members-1 | |
1432 | * Access: RW | |
1433 | */ | |
1434 | MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); | |
1435 | ||
1436 | static inline void mlxsw_reg_slcor_pack(char *payload, | |
1437 | u8 local_port, u16 lag_id, | |
1438 | enum mlxsw_reg_slcor_col col) | |
1439 | { | |
1440 | MLXSW_REG_ZERO(slcor, payload); | |
1441 | mlxsw_reg_slcor_col_set(payload, col); | |
1442 | mlxsw_reg_slcor_local_port_set(payload, local_port); | |
1443 | mlxsw_reg_slcor_lag_id_set(payload, lag_id); | |
1444 | } | |
1445 | ||
1446 | static inline void mlxsw_reg_slcor_port_add_pack(char *payload, | |
1447 | u8 local_port, u16 lag_id, | |
1448 | u8 port_index) | |
1449 | { | |
1450 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1451 | MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); | |
1452 | mlxsw_reg_slcor_port_index_set(payload, port_index); | |
1453 | } | |
1454 | ||
1455 | static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, | |
1456 | u8 local_port, u16 lag_id) | |
1457 | { | |
1458 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1459 | MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); | |
1460 | } | |
1461 | ||
1462 | static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, | |
1463 | u8 local_port, u16 lag_id) | |
1464 | { | |
1465 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1466 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); | |
1467 | } | |
1468 | ||
1469 | static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, | |
1470 | u8 local_port, u16 lag_id) | |
1471 | { | |
1472 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1473 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); | |
1474 | } | |
1475 | ||
4ec14b76 IS |
1476 | /* SPMLR - Switch Port MAC Learning Register |
1477 | * ----------------------------------------- | |
1478 | * Controls the Switch MAC learning policy per port. | |
1479 | */ | |
1480 | #define MLXSW_REG_SPMLR_ID 0x2018 | |
1481 | #define MLXSW_REG_SPMLR_LEN 0x8 | |
1482 | ||
1483 | static const struct mlxsw_reg_info mlxsw_reg_spmlr = { | |
1484 | .id = MLXSW_REG_SPMLR_ID, | |
1485 | .len = MLXSW_REG_SPMLR_LEN, | |
1486 | }; | |
1487 | ||
1488 | /* reg_spmlr_local_port | |
1489 | * Local port number. | |
1490 | * Access: Index | |
1491 | */ | |
1492 | MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); | |
1493 | ||
1494 | /* reg_spmlr_sub_port | |
1495 | * Virtual port within the physical port. | |
1496 | * Should be set to 0 when virtual ports are not enabled on the port. | |
1497 | * Access: Index | |
1498 | */ | |
1499 | MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); | |
1500 | ||
1501 | enum mlxsw_reg_spmlr_learn_mode { | |
1502 | MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, | |
1503 | MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, | |
1504 | MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, | |
1505 | }; | |
1506 | ||
1507 | /* reg_spmlr_learn_mode | |
1508 | * Learning mode on the port. | |
1509 | * 0 - Learning disabled. | |
1510 | * 2 - Learning enabled. | |
1511 | * 3 - Security mode. | |
1512 | * | |
1513 | * In security mode the switch does not learn MACs on the port, but uses the | |
1514 | * SMAC to see if it exists on another ingress port. If so, the packet is | |
1515 | * classified as a bad packet and is discarded unless the software registers | |
1516 | * to receive port security error packets usign HPKT. | |
1517 | */ | |
1518 | MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); | |
1519 | ||
1520 | static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, | |
1521 | enum mlxsw_reg_spmlr_learn_mode mode) | |
1522 | { | |
1523 | MLXSW_REG_ZERO(spmlr, payload); | |
1524 | mlxsw_reg_spmlr_local_port_set(payload, local_port); | |
1525 | mlxsw_reg_spmlr_sub_port_set(payload, 0); | |
1526 | mlxsw_reg_spmlr_learn_mode_set(payload, mode); | |
1527 | } | |
1528 | ||
64790239 IS |
1529 | /* SVFA - Switch VID to FID Allocation Register |
1530 | * -------------------------------------------- | |
1531 | * Controls the VID to FID mapping and {Port, VID} to FID mapping for | |
1532 | * virtualized ports. | |
1533 | */ | |
1534 | #define MLXSW_REG_SVFA_ID 0x201C | |
1535 | #define MLXSW_REG_SVFA_LEN 0x10 | |
1536 | ||
1537 | static const struct mlxsw_reg_info mlxsw_reg_svfa = { | |
1538 | .id = MLXSW_REG_SVFA_ID, | |
1539 | .len = MLXSW_REG_SVFA_LEN, | |
1540 | }; | |
1541 | ||
1542 | /* reg_svfa_swid | |
1543 | * Switch partition ID. | |
1544 | * Access: Index | |
1545 | */ | |
1546 | MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); | |
1547 | ||
1548 | /* reg_svfa_local_port | |
1549 | * Local port number. | |
1550 | * Access: Index | |
1551 | * | |
1552 | * Note: Reserved for 802.1Q FIDs. | |
1553 | */ | |
1554 | MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); | |
1555 | ||
1556 | enum mlxsw_reg_svfa_mt { | |
1557 | MLXSW_REG_SVFA_MT_VID_TO_FID, | |
1558 | MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, | |
1559 | }; | |
1560 | ||
1561 | /* reg_svfa_mapping_table | |
1562 | * Mapping table: | |
1563 | * 0 - VID to FID | |
1564 | * 1 - {Port, VID} to FID | |
1565 | * Access: Index | |
1566 | * | |
1567 | * Note: Reserved for SwitchX-2. | |
1568 | */ | |
1569 | MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); | |
1570 | ||
1571 | /* reg_svfa_v | |
1572 | * Valid. | |
1573 | * Valid if set. | |
1574 | * Access: RW | |
1575 | * | |
1576 | * Note: Reserved for SwitchX-2. | |
1577 | */ | |
1578 | MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); | |
1579 | ||
1580 | /* reg_svfa_fid | |
1581 | * Filtering ID. | |
1582 | * Access: RW | |
1583 | */ | |
1584 | MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); | |
1585 | ||
1586 | /* reg_svfa_vid | |
1587 | * VLAN ID. | |
1588 | * Access: Index | |
1589 | */ | |
1590 | MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); | |
1591 | ||
1592 | /* reg_svfa_counter_set_type | |
1593 | * Counter set type for flow counters. | |
1594 | * Access: RW | |
1595 | * | |
1596 | * Note: Reserved for SwitchX-2. | |
1597 | */ | |
1598 | MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); | |
1599 | ||
1600 | /* reg_svfa_counter_index | |
1601 | * Counter index for flow counters. | |
1602 | * Access: RW | |
1603 | * | |
1604 | * Note: Reserved for SwitchX-2. | |
1605 | */ | |
1606 | MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); | |
1607 | ||
1608 | static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, | |
1609 | enum mlxsw_reg_svfa_mt mt, bool valid, | |
1610 | u16 fid, u16 vid) | |
1611 | { | |
1612 | MLXSW_REG_ZERO(svfa, payload); | |
1613 | local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; | |
1614 | mlxsw_reg_svfa_swid_set(payload, 0); | |
1615 | mlxsw_reg_svfa_local_port_set(payload, local_port); | |
1616 | mlxsw_reg_svfa_mapping_table_set(payload, mt); | |
1617 | mlxsw_reg_svfa_v_set(payload, valid); | |
1618 | mlxsw_reg_svfa_fid_set(payload, fid); | |
1619 | mlxsw_reg_svfa_vid_set(payload, vid); | |
1620 | } | |
1621 | ||
1f65da74 IS |
1622 | /* SVPE - Switch Virtual-Port Enabling Register |
1623 | * -------------------------------------------- | |
1624 | * Enables port virtualization. | |
1625 | */ | |
1626 | #define MLXSW_REG_SVPE_ID 0x201E | |
1627 | #define MLXSW_REG_SVPE_LEN 0x4 | |
1628 | ||
1629 | static const struct mlxsw_reg_info mlxsw_reg_svpe = { | |
1630 | .id = MLXSW_REG_SVPE_ID, | |
1631 | .len = MLXSW_REG_SVPE_LEN, | |
1632 | }; | |
1633 | ||
1634 | /* reg_svpe_local_port | |
1635 | * Local port number | |
1636 | * Access: Index | |
1637 | * | |
1638 | * Note: CPU port is not supported (uses VLAN mode only). | |
1639 | */ | |
1640 | MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); | |
1641 | ||
1642 | /* reg_svpe_vp_en | |
1643 | * Virtual port enable. | |
1644 | * 0 - Disable, VLAN mode (VID to FID). | |
1645 | * 1 - Enable, Virtual port mode ({Port, VID} to FID). | |
1646 | * Access: RW | |
1647 | */ | |
1648 | MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); | |
1649 | ||
1650 | static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, | |
1651 | bool enable) | |
1652 | { | |
1653 | MLXSW_REG_ZERO(svpe, payload); | |
1654 | mlxsw_reg_svpe_local_port_set(payload, local_port); | |
1655 | mlxsw_reg_svpe_vp_en_set(payload, enable); | |
1656 | } | |
1657 | ||
f1fb693a IS |
1658 | /* SFMR - Switch FID Management Register |
1659 | * ------------------------------------- | |
1660 | * Creates and configures FIDs. | |
1661 | */ | |
1662 | #define MLXSW_REG_SFMR_ID 0x201F | |
1663 | #define MLXSW_REG_SFMR_LEN 0x18 | |
1664 | ||
1665 | static const struct mlxsw_reg_info mlxsw_reg_sfmr = { | |
1666 | .id = MLXSW_REG_SFMR_ID, | |
1667 | .len = MLXSW_REG_SFMR_LEN, | |
1668 | }; | |
1669 | ||
1670 | enum mlxsw_reg_sfmr_op { | |
1671 | MLXSW_REG_SFMR_OP_CREATE_FID, | |
1672 | MLXSW_REG_SFMR_OP_DESTROY_FID, | |
1673 | }; | |
1674 | ||
1675 | /* reg_sfmr_op | |
1676 | * Operation. | |
1677 | * 0 - Create or edit FID. | |
1678 | * 1 - Destroy FID. | |
1679 | * Access: WO | |
1680 | */ | |
1681 | MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); | |
1682 | ||
1683 | /* reg_sfmr_fid | |
1684 | * Filtering ID. | |
1685 | * Access: Index | |
1686 | */ | |
1687 | MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); | |
1688 | ||
1689 | /* reg_sfmr_fid_offset | |
1690 | * FID offset. | |
1691 | * Used to point into the flooding table selected by SFGC register if | |
1692 | * the table is of type FID-Offset. Otherwise, this field is reserved. | |
1693 | * Access: RW | |
1694 | */ | |
1695 | MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); | |
1696 | ||
1697 | /* reg_sfmr_vtfp | |
1698 | * Valid Tunnel Flood Pointer. | |
1699 | * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. | |
1700 | * Access: RW | |
1701 | * | |
1702 | * Note: Reserved for 802.1Q FIDs. | |
1703 | */ | |
1704 | MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); | |
1705 | ||
1706 | /* reg_sfmr_nve_tunnel_flood_ptr | |
1707 | * Underlay Flooding and BC Pointer. | |
1708 | * Used as a pointer to the first entry of the group based link lists of | |
1709 | * flooding or BC entries (for NVE tunnels). | |
1710 | * Access: RW | |
1711 | */ | |
1712 | MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); | |
1713 | ||
1714 | /* reg_sfmr_vv | |
1715 | * VNI Valid. | |
1716 | * If not set, then vni is reserved. | |
1717 | * Access: RW | |
1718 | * | |
1719 | * Note: Reserved for 802.1Q FIDs. | |
1720 | */ | |
1721 | MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); | |
1722 | ||
1723 | /* reg_sfmr_vni | |
1724 | * Virtual Network Identifier. | |
1725 | * Access: RW | |
1726 | * | |
1727 | * Note: A given VNI can only be assigned to one FID. | |
1728 | */ | |
1729 | MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); | |
1730 | ||
1731 | static inline void mlxsw_reg_sfmr_pack(char *payload, | |
1732 | enum mlxsw_reg_sfmr_op op, u16 fid, | |
1733 | u16 fid_offset) | |
1734 | { | |
1735 | MLXSW_REG_ZERO(sfmr, payload); | |
1736 | mlxsw_reg_sfmr_op_set(payload, op); | |
1737 | mlxsw_reg_sfmr_fid_set(payload, fid); | |
1738 | mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); | |
1739 | mlxsw_reg_sfmr_vtfp_set(payload, false); | |
1740 | mlxsw_reg_sfmr_vv_set(payload, false); | |
1741 | } | |
1742 | ||
a4feea74 IS |
1743 | /* SPVMLR - Switch Port VLAN MAC Learning Register |
1744 | * ----------------------------------------------- | |
1745 | * Controls the switch MAC learning policy per {Port, VID}. | |
1746 | */ | |
1747 | #define MLXSW_REG_SPVMLR_ID 0x2020 | |
1748 | #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ | |
1749 | #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ | |
1750 | #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256 | |
1751 | #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ | |
1752 | MLXSW_REG_SPVMLR_REC_LEN * \ | |
1753 | MLXSW_REG_SPVMLR_REC_MAX_COUNT) | |
1754 | ||
1755 | static const struct mlxsw_reg_info mlxsw_reg_spvmlr = { | |
1756 | .id = MLXSW_REG_SPVMLR_ID, | |
1757 | .len = MLXSW_REG_SPVMLR_LEN, | |
1758 | }; | |
1759 | ||
1760 | /* reg_spvmlr_local_port | |
1761 | * Local ingress port. | |
1762 | * Access: Index | |
1763 | * | |
1764 | * Note: CPU port is not supported. | |
1765 | */ | |
1766 | MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); | |
1767 | ||
1768 | /* reg_spvmlr_num_rec | |
1769 | * Number of records to update. | |
1770 | * Access: OP | |
1771 | */ | |
1772 | MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); | |
1773 | ||
1774 | /* reg_spvmlr_rec_learn_enable | |
1775 | * 0 - Disable learning for {Port, VID}. | |
1776 | * 1 - Enable learning for {Port, VID}. | |
1777 | * Access: RW | |
1778 | */ | |
1779 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, | |
1780 | 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1781 | ||
1782 | /* reg_spvmlr_rec_vid | |
1783 | * VLAN ID to be added/removed from port or for querying. | |
1784 | * Access: Index | |
1785 | */ | |
1786 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, | |
1787 | MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1788 | ||
1789 | static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, | |
1790 | u16 vid_begin, u16 vid_end, | |
1791 | bool learn_enable) | |
1792 | { | |
1793 | int num_rec = vid_end - vid_begin + 1; | |
1794 | int i; | |
1795 | ||
1796 | WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); | |
1797 | ||
1798 | MLXSW_REG_ZERO(spvmlr, payload); | |
1799 | mlxsw_reg_spvmlr_local_port_set(payload, local_port); | |
1800 | mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); | |
1801 | ||
1802 | for (i = 0; i < num_rec; i++) { | |
1803 | mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); | |
1804 | mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); | |
1805 | } | |
1806 | } | |
1807 | ||
2c63a555 IS |
1808 | /* QTCT - QoS Switch Traffic Class Table |
1809 | * ------------------------------------- | |
1810 | * Configures the mapping between the packet switch priority and the | |
1811 | * traffic class on the transmit port. | |
1812 | */ | |
1813 | #define MLXSW_REG_QTCT_ID 0x400A | |
1814 | #define MLXSW_REG_QTCT_LEN 0x08 | |
1815 | ||
1816 | static const struct mlxsw_reg_info mlxsw_reg_qtct = { | |
1817 | .id = MLXSW_REG_QTCT_ID, | |
1818 | .len = MLXSW_REG_QTCT_LEN, | |
1819 | }; | |
1820 | ||
1821 | /* reg_qtct_local_port | |
1822 | * Local port number. | |
1823 | * Access: Index | |
1824 | * | |
1825 | * Note: CPU port is not supported. | |
1826 | */ | |
1827 | MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); | |
1828 | ||
1829 | /* reg_qtct_sub_port | |
1830 | * Virtual port within the physical port. | |
1831 | * Should be set to 0 when virtual ports are not enabled on the port. | |
1832 | * Access: Index | |
1833 | */ | |
1834 | MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); | |
1835 | ||
1836 | /* reg_qtct_switch_prio | |
1837 | * Switch priority. | |
1838 | * Access: Index | |
1839 | */ | |
1840 | MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); | |
1841 | ||
1842 | /* reg_qtct_tclass | |
1843 | * Traffic class. | |
1844 | * Default values: | |
1845 | * switch_prio 0 : tclass 1 | |
1846 | * switch_prio 1 : tclass 0 | |
1847 | * switch_prio i : tclass i, for i > 1 | |
1848 | * Access: RW | |
1849 | */ | |
1850 | MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); | |
1851 | ||
1852 | static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, | |
1853 | u8 switch_prio, u8 tclass) | |
1854 | { | |
1855 | MLXSW_REG_ZERO(qtct, payload); | |
1856 | mlxsw_reg_qtct_local_port_set(payload, local_port); | |
1857 | mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); | |
1858 | mlxsw_reg_qtct_tclass_set(payload, tclass); | |
1859 | } | |
1860 | ||
b9b7cee4 IS |
1861 | /* QEEC - QoS ETS Element Configuration Register |
1862 | * --------------------------------------------- | |
1863 | * Configures the ETS elements. | |
1864 | */ | |
1865 | #define MLXSW_REG_QEEC_ID 0x400D | |
1866 | #define MLXSW_REG_QEEC_LEN 0x1C | |
1867 | ||
1868 | static const struct mlxsw_reg_info mlxsw_reg_qeec = { | |
1869 | .id = MLXSW_REG_QEEC_ID, | |
1870 | .len = MLXSW_REG_QEEC_LEN, | |
1871 | }; | |
1872 | ||
1873 | /* reg_qeec_local_port | |
1874 | * Local port number. | |
1875 | * Access: Index | |
1876 | * | |
1877 | * Note: CPU port is supported. | |
1878 | */ | |
1879 | MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); | |
1880 | ||
1881 | enum mlxsw_reg_qeec_hr { | |
1882 | MLXSW_REG_QEEC_HIERARCY_PORT, | |
1883 | MLXSW_REG_QEEC_HIERARCY_GROUP, | |
1884 | MLXSW_REG_QEEC_HIERARCY_SUBGROUP, | |
1885 | MLXSW_REG_QEEC_HIERARCY_TC, | |
1886 | }; | |
1887 | ||
1888 | /* reg_qeec_element_hierarchy | |
1889 | * 0 - Port | |
1890 | * 1 - Group | |
1891 | * 2 - Subgroup | |
1892 | * 3 - Traffic Class | |
1893 | * Access: Index | |
1894 | */ | |
1895 | MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); | |
1896 | ||
1897 | /* reg_qeec_element_index | |
1898 | * The index of the element in the hierarchy. | |
1899 | * Access: Index | |
1900 | */ | |
1901 | MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); | |
1902 | ||
1903 | /* reg_qeec_next_element_index | |
1904 | * The index of the next (lower) element in the hierarchy. | |
1905 | * Access: RW | |
1906 | * | |
1907 | * Note: Reserved for element_hierarchy 0. | |
1908 | */ | |
1909 | MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); | |
1910 | ||
1911 | enum { | |
1912 | MLXSW_REG_QEEC_BYTES_MODE, | |
1913 | MLXSW_REG_QEEC_PACKETS_MODE, | |
1914 | }; | |
1915 | ||
1916 | /* reg_qeec_pb | |
1917 | * Packets or bytes mode. | |
1918 | * 0 - Bytes mode | |
1919 | * 1 - Packets mode | |
1920 | * Access: RW | |
1921 | * | |
1922 | * Note: Used for max shaper configuration. For Spectrum, packets mode | |
1923 | * is supported only for traffic classes of CPU port. | |
1924 | */ | |
1925 | MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); | |
1926 | ||
1927 | /* reg_qeec_mase | |
1928 | * Max shaper configuration enable. Enables configuration of the max | |
1929 | * shaper on this ETS element. | |
1930 | * 0 - Disable | |
1931 | * 1 - Enable | |
1932 | * Access: RW | |
1933 | */ | |
1934 | MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); | |
1935 | ||
1936 | /* A large max rate will disable the max shaper. */ | |
1937 | #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ | |
1938 | ||
1939 | /* reg_qeec_max_shaper_rate | |
1940 | * Max shaper information rate. | |
1941 | * For CPU port, can only be configured for port hierarchy. | |
1942 | * When in bytes mode, value is specified in units of 1000bps. | |
1943 | * Access: RW | |
1944 | */ | |
1945 | MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); | |
1946 | ||
1947 | /* reg_qeec_de | |
1948 | * DWRR configuration enable. Enables configuration of the dwrr and | |
1949 | * dwrr_weight. | |
1950 | * 0 - Disable | |
1951 | * 1 - Enable | |
1952 | * Access: RW | |
1953 | */ | |
1954 | MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); | |
1955 | ||
1956 | /* reg_qeec_dwrr | |
1957 | * Transmission selection algorithm to use on the link going down from | |
1958 | * the ETS element. | |
1959 | * 0 - Strict priority | |
1960 | * 1 - DWRR | |
1961 | * Access: RW | |
1962 | */ | |
1963 | MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); | |
1964 | ||
1965 | /* reg_qeec_dwrr_weight | |
1966 | * DWRR weight on the link going down from the ETS element. The | |
1967 | * percentage of bandwidth guaranteed to an ETS element within | |
1968 | * its hierarchy. The sum of all weights across all ETS elements | |
1969 | * within one hierarchy should be equal to 100. Reserved when | |
1970 | * transmission selection algorithm is strict priority. | |
1971 | * Access: RW | |
1972 | */ | |
1973 | MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); | |
1974 | ||
1975 | static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, | |
1976 | enum mlxsw_reg_qeec_hr hr, u8 index, | |
1977 | u8 next_index) | |
1978 | { | |
1979 | MLXSW_REG_ZERO(qeec, payload); | |
1980 | mlxsw_reg_qeec_local_port_set(payload, local_port); | |
1981 | mlxsw_reg_qeec_element_hierarchy_set(payload, hr); | |
1982 | mlxsw_reg_qeec_element_index_set(payload, index); | |
1983 | mlxsw_reg_qeec_next_element_index_set(payload, next_index); | |
1984 | } | |
1985 | ||
4ec14b76 IS |
1986 | /* PMLP - Ports Module to Local Port Register |
1987 | * ------------------------------------------ | |
1988 | * Configures the assignment of modules to local ports. | |
1989 | */ | |
1990 | #define MLXSW_REG_PMLP_ID 0x5002 | |
1991 | #define MLXSW_REG_PMLP_LEN 0x40 | |
1992 | ||
1993 | static const struct mlxsw_reg_info mlxsw_reg_pmlp = { | |
1994 | .id = MLXSW_REG_PMLP_ID, | |
1995 | .len = MLXSW_REG_PMLP_LEN, | |
1996 | }; | |
1997 | ||
1998 | /* reg_pmlp_rxtx | |
1999 | * 0 - Tx value is used for both Tx and Rx. | |
2000 | * 1 - Rx value is taken from a separte field. | |
2001 | * Access: RW | |
2002 | */ | |
2003 | MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); | |
2004 | ||
2005 | /* reg_pmlp_local_port | |
2006 | * Local port number. | |
2007 | * Access: Index | |
2008 | */ | |
2009 | MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); | |
2010 | ||
2011 | /* reg_pmlp_width | |
2012 | * 0 - Unmap local port. | |
2013 | * 1 - Lane 0 is used. | |
2014 | * 2 - Lanes 0 and 1 are used. | |
2015 | * 4 - Lanes 0, 1, 2 and 3 are used. | |
2016 | * Access: RW | |
2017 | */ | |
2018 | MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); | |
2019 | ||
2020 | /* reg_pmlp_module | |
2021 | * Module number. | |
2022 | * Access: RW | |
2023 | */ | |
bbeeda27 | 2024 | MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); |
4ec14b76 IS |
2025 | |
2026 | /* reg_pmlp_tx_lane | |
2027 | * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. | |
2028 | * Access: RW | |
2029 | */ | |
bbeeda27 | 2030 | MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); |
4ec14b76 IS |
2031 | |
2032 | /* reg_pmlp_rx_lane | |
2033 | * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is | |
2034 | * equal to Tx lane. | |
2035 | * Access: RW | |
2036 | */ | |
bbeeda27 | 2037 | MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); |
4ec14b76 IS |
2038 | |
2039 | static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) | |
2040 | { | |
2041 | MLXSW_REG_ZERO(pmlp, payload); | |
2042 | mlxsw_reg_pmlp_local_port_set(payload, local_port); | |
2043 | } | |
2044 | ||
2045 | /* PMTU - Port MTU Register | |
2046 | * ------------------------ | |
2047 | * Configures and reports the port MTU. | |
2048 | */ | |
2049 | #define MLXSW_REG_PMTU_ID 0x5003 | |
2050 | #define MLXSW_REG_PMTU_LEN 0x10 | |
2051 | ||
2052 | static const struct mlxsw_reg_info mlxsw_reg_pmtu = { | |
2053 | .id = MLXSW_REG_PMTU_ID, | |
2054 | .len = MLXSW_REG_PMTU_LEN, | |
2055 | }; | |
2056 | ||
2057 | /* reg_pmtu_local_port | |
2058 | * Local port number. | |
2059 | * Access: Index | |
2060 | */ | |
2061 | MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); | |
2062 | ||
2063 | /* reg_pmtu_max_mtu | |
2064 | * Maximum MTU. | |
2065 | * When port type (e.g. Ethernet) is configured, the relevant MTU is | |
2066 | * reported, otherwise the minimum between the max_mtu of the different | |
2067 | * types is reported. | |
2068 | * Access: RO | |
2069 | */ | |
2070 | MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); | |
2071 | ||
2072 | /* reg_pmtu_admin_mtu | |
2073 | * MTU value to set port to. Must be smaller or equal to max_mtu. | |
2074 | * Note: If port type is Infiniband, then port must be disabled, when its | |
2075 | * MTU is set. | |
2076 | * Access: RW | |
2077 | */ | |
2078 | MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); | |
2079 | ||
2080 | /* reg_pmtu_oper_mtu | |
2081 | * The actual MTU configured on the port. Packets exceeding this size | |
2082 | * will be dropped. | |
2083 | * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband | |
2084 | * oper_mtu might be smaller than admin_mtu. | |
2085 | * Access: RO | |
2086 | */ | |
2087 | MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); | |
2088 | ||
2089 | static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, | |
2090 | u16 new_mtu) | |
2091 | { | |
2092 | MLXSW_REG_ZERO(pmtu, payload); | |
2093 | mlxsw_reg_pmtu_local_port_set(payload, local_port); | |
2094 | mlxsw_reg_pmtu_max_mtu_set(payload, 0); | |
2095 | mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); | |
2096 | mlxsw_reg_pmtu_oper_mtu_set(payload, 0); | |
2097 | } | |
2098 | ||
2099 | /* PTYS - Port Type and Speed Register | |
2100 | * ----------------------------------- | |
2101 | * Configures and reports the port speed type. | |
2102 | * | |
2103 | * Note: When set while the link is up, the changes will not take effect | |
2104 | * until the port transitions from down to up state. | |
2105 | */ | |
2106 | #define MLXSW_REG_PTYS_ID 0x5004 | |
2107 | #define MLXSW_REG_PTYS_LEN 0x40 | |
2108 | ||
2109 | static const struct mlxsw_reg_info mlxsw_reg_ptys = { | |
2110 | .id = MLXSW_REG_PTYS_ID, | |
2111 | .len = MLXSW_REG_PTYS_LEN, | |
2112 | }; | |
2113 | ||
2114 | /* reg_ptys_local_port | |
2115 | * Local port number. | |
2116 | * Access: Index | |
2117 | */ | |
2118 | MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); | |
2119 | ||
2120 | #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) | |
2121 | ||
2122 | /* reg_ptys_proto_mask | |
2123 | * Protocol mask. Indicates which protocol is used. | |
2124 | * 0 - Infiniband. | |
2125 | * 1 - Fibre Channel. | |
2126 | * 2 - Ethernet. | |
2127 | * Access: Index | |
2128 | */ | |
2129 | MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); | |
2130 | ||
2131 | #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) | |
2132 | #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) | |
2133 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) | |
2134 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) | |
2135 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) | |
2136 | #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) | |
2137 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) | |
2138 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) | |
2139 | #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) | |
2140 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) | |
2141 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) | |
2142 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) | |
2143 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) | |
2144 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) | |
2145 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) | |
2146 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) | |
2147 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) | |
2148 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) | |
2149 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) | |
2150 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) | |
2151 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) | |
2152 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) | |
2153 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) | |
2154 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) | |
2155 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) | |
2156 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) | |
2157 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) | |
2158 | ||
2159 | /* reg_ptys_eth_proto_cap | |
2160 | * Ethernet port supported speeds and protocols. | |
2161 | * Access: RO | |
2162 | */ | |
2163 | MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); | |
2164 | ||
2165 | /* reg_ptys_eth_proto_admin | |
2166 | * Speed and protocol to set port to. | |
2167 | * Access: RW | |
2168 | */ | |
2169 | MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); | |
2170 | ||
2171 | /* reg_ptys_eth_proto_oper | |
2172 | * The current speed and protocol configured for the port. | |
2173 | * Access: RO | |
2174 | */ | |
2175 | MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); | |
2176 | ||
2177 | static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port, | |
2178 | u32 proto_admin) | |
2179 | { | |
2180 | MLXSW_REG_ZERO(ptys, payload); | |
2181 | mlxsw_reg_ptys_local_port_set(payload, local_port); | |
2182 | mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); | |
2183 | mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); | |
2184 | } | |
2185 | ||
2186 | static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap, | |
2187 | u32 *p_eth_proto_adm, | |
2188 | u32 *p_eth_proto_oper) | |
2189 | { | |
2190 | if (p_eth_proto_cap) | |
2191 | *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); | |
2192 | if (p_eth_proto_adm) | |
2193 | *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); | |
2194 | if (p_eth_proto_oper) | |
2195 | *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); | |
2196 | } | |
2197 | ||
2198 | /* PPAD - Port Physical Address Register | |
2199 | * ------------------------------------- | |
2200 | * The PPAD register configures the per port physical MAC address. | |
2201 | */ | |
2202 | #define MLXSW_REG_PPAD_ID 0x5005 | |
2203 | #define MLXSW_REG_PPAD_LEN 0x10 | |
2204 | ||
2205 | static const struct mlxsw_reg_info mlxsw_reg_ppad = { | |
2206 | .id = MLXSW_REG_PPAD_ID, | |
2207 | .len = MLXSW_REG_PPAD_LEN, | |
2208 | }; | |
2209 | ||
2210 | /* reg_ppad_single_base_mac | |
2211 | * 0: base_mac, local port should be 0 and mac[7:0] is | |
2212 | * reserved. HW will set incremental | |
2213 | * 1: single_mac - mac of the local_port | |
2214 | * Access: RW | |
2215 | */ | |
2216 | MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); | |
2217 | ||
2218 | /* reg_ppad_local_port | |
2219 | * port number, if single_base_mac = 0 then local_port is reserved | |
2220 | * Access: RW | |
2221 | */ | |
2222 | MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); | |
2223 | ||
2224 | /* reg_ppad_mac | |
2225 | * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. | |
2226 | * If single_base_mac = 1 - the per port MAC address | |
2227 | * Access: RW | |
2228 | */ | |
2229 | MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); | |
2230 | ||
2231 | static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, | |
2232 | u8 local_port) | |
2233 | { | |
2234 | MLXSW_REG_ZERO(ppad, payload); | |
2235 | mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); | |
2236 | mlxsw_reg_ppad_local_port_set(payload, local_port); | |
2237 | } | |
2238 | ||
2239 | /* PAOS - Ports Administrative and Operational Status Register | |
2240 | * ----------------------------------------------------------- | |
2241 | * Configures and retrieves per port administrative and operational status. | |
2242 | */ | |
2243 | #define MLXSW_REG_PAOS_ID 0x5006 | |
2244 | #define MLXSW_REG_PAOS_LEN 0x10 | |
2245 | ||
2246 | static const struct mlxsw_reg_info mlxsw_reg_paos = { | |
2247 | .id = MLXSW_REG_PAOS_ID, | |
2248 | .len = MLXSW_REG_PAOS_LEN, | |
2249 | }; | |
2250 | ||
2251 | /* reg_paos_swid | |
2252 | * Switch partition ID with which to associate the port. | |
2253 | * Note: while external ports uses unique local port numbers (and thus swid is | |
2254 | * redundant), router ports use the same local port number where swid is the | |
2255 | * only indication for the relevant port. | |
2256 | * Access: Index | |
2257 | */ | |
2258 | MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); | |
2259 | ||
2260 | /* reg_paos_local_port | |
2261 | * Local port number. | |
2262 | * Access: Index | |
2263 | */ | |
2264 | MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); | |
2265 | ||
2266 | /* reg_paos_admin_status | |
2267 | * Port administrative state (the desired state of the port): | |
2268 | * 1 - Up. | |
2269 | * 2 - Down. | |
2270 | * 3 - Up once. This means that in case of link failure, the port won't go | |
2271 | * into polling mode, but will wait to be re-enabled by software. | |
2272 | * 4 - Disabled by system. Can only be set by hardware. | |
2273 | * Access: RW | |
2274 | */ | |
2275 | MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); | |
2276 | ||
2277 | /* reg_paos_oper_status | |
2278 | * Port operational state (the current state): | |
2279 | * 1 - Up. | |
2280 | * 2 - Down. | |
2281 | * 3 - Down by port failure. This means that the device will not let the | |
2282 | * port up again until explicitly specified by software. | |
2283 | * Access: RO | |
2284 | */ | |
2285 | MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); | |
2286 | ||
2287 | /* reg_paos_ase | |
2288 | * Admin state update enabled. | |
2289 | * Access: WO | |
2290 | */ | |
2291 | MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); | |
2292 | ||
2293 | /* reg_paos_ee | |
2294 | * Event update enable. If this bit is set, event generation will be | |
2295 | * updated based on the e field. | |
2296 | * Access: WO | |
2297 | */ | |
2298 | MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); | |
2299 | ||
2300 | /* reg_paos_e | |
2301 | * Event generation on operational state change: | |
2302 | * 0 - Do not generate event. | |
2303 | * 1 - Generate Event. | |
2304 | * 2 - Generate Single Event. | |
2305 | * Access: RW | |
2306 | */ | |
2307 | MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); | |
2308 | ||
2309 | static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, | |
2310 | enum mlxsw_port_admin_status status) | |
2311 | { | |
2312 | MLXSW_REG_ZERO(paos, payload); | |
2313 | mlxsw_reg_paos_swid_set(payload, 0); | |
2314 | mlxsw_reg_paos_local_port_set(payload, local_port); | |
2315 | mlxsw_reg_paos_admin_status_set(payload, status); | |
2316 | mlxsw_reg_paos_oper_status_set(payload, 0); | |
2317 | mlxsw_reg_paos_ase_set(payload, 1); | |
2318 | mlxsw_reg_paos_ee_set(payload, 1); | |
2319 | mlxsw_reg_paos_e_set(payload, 1); | |
2320 | } | |
2321 | ||
6f253d83 IS |
2322 | /* PFCC - Ports Flow Control Configuration Register |
2323 | * ------------------------------------------------ | |
2324 | * Configures and retrieves the per port flow control configuration. | |
2325 | */ | |
2326 | #define MLXSW_REG_PFCC_ID 0x5007 | |
2327 | #define MLXSW_REG_PFCC_LEN 0x20 | |
2328 | ||
2329 | static const struct mlxsw_reg_info mlxsw_reg_pfcc = { | |
2330 | .id = MLXSW_REG_PFCC_ID, | |
2331 | .len = MLXSW_REG_PFCC_LEN, | |
2332 | }; | |
2333 | ||
2334 | /* reg_pfcc_local_port | |
2335 | * Local port number. | |
2336 | * Access: Index | |
2337 | */ | |
2338 | MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); | |
2339 | ||
2340 | /* reg_pfcc_pnat | |
2341 | * Port number access type. Determines the way local_port is interpreted: | |
2342 | * 0 - Local port number. | |
2343 | * 1 - IB / label port number. | |
2344 | * Access: Index | |
2345 | */ | |
2346 | MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); | |
2347 | ||
2348 | /* reg_pfcc_shl_cap | |
2349 | * Send to higher layers capabilities: | |
2350 | * 0 - No capability of sending Pause and PFC frames to higher layers. | |
2351 | * 1 - Device has capability of sending Pause and PFC frames to higher | |
2352 | * layers. | |
2353 | * Access: RO | |
2354 | */ | |
2355 | MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); | |
2356 | ||
2357 | /* reg_pfcc_shl_opr | |
2358 | * Send to higher layers operation: | |
2359 | * 0 - Pause and PFC frames are handled by the port (default). | |
2360 | * 1 - Pause and PFC frames are handled by the port and also sent to | |
2361 | * higher layers. Only valid if shl_cap = 1. | |
2362 | * Access: RW | |
2363 | */ | |
2364 | MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); | |
2365 | ||
2366 | /* reg_pfcc_ppan | |
2367 | * Pause policy auto negotiation. | |
2368 | * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. | |
2369 | * 1 - Enabled. When auto-negotiation is performed, set the Pause policy | |
2370 | * based on the auto-negotiation resolution. | |
2371 | * Access: RW | |
2372 | * | |
2373 | * Note: The auto-negotiation advertisement is set according to pptx and | |
2374 | * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. | |
2375 | */ | |
2376 | MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); | |
2377 | ||
2378 | /* reg_pfcc_prio_mask_tx | |
2379 | * Bit per priority indicating if Tx flow control policy should be | |
2380 | * updated based on bit pfctx. | |
2381 | * Access: WO | |
2382 | */ | |
2383 | MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); | |
2384 | ||
2385 | /* reg_pfcc_prio_mask_rx | |
2386 | * Bit per priority indicating if Rx flow control policy should be | |
2387 | * updated based on bit pfcrx. | |
2388 | * Access: WO | |
2389 | */ | |
2390 | MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); | |
2391 | ||
2392 | /* reg_pfcc_pptx | |
2393 | * Admin Pause policy on Tx. | |
2394 | * 0 - Never generate Pause frames (default). | |
2395 | * 1 - Generate Pause frames according to Rx buffer threshold. | |
2396 | * Access: RW | |
2397 | */ | |
2398 | MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); | |
2399 | ||
2400 | /* reg_pfcc_aptx | |
2401 | * Active (operational) Pause policy on Tx. | |
2402 | * 0 - Never generate Pause frames. | |
2403 | * 1 - Generate Pause frames according to Rx buffer threshold. | |
2404 | * Access: RO | |
2405 | */ | |
2406 | MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); | |
2407 | ||
2408 | /* reg_pfcc_pfctx | |
2409 | * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: | |
2410 | * 0 - Never generate priority Pause frames on the specified priority | |
2411 | * (default). | |
2412 | * 1 - Generate priority Pause frames according to Rx buffer threshold on | |
2413 | * the specified priority. | |
2414 | * Access: RW | |
2415 | * | |
2416 | * Note: pfctx and pptx must be mutually exclusive. | |
2417 | */ | |
2418 | MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); | |
2419 | ||
2420 | /* reg_pfcc_pprx | |
2421 | * Admin Pause policy on Rx. | |
2422 | * 0 - Ignore received Pause frames (default). | |
2423 | * 1 - Respect received Pause frames. | |
2424 | * Access: RW | |
2425 | */ | |
2426 | MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); | |
2427 | ||
2428 | /* reg_pfcc_aprx | |
2429 | * Active (operational) Pause policy on Rx. | |
2430 | * 0 - Ignore received Pause frames. | |
2431 | * 1 - Respect received Pause frames. | |
2432 | * Access: RO | |
2433 | */ | |
2434 | MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); | |
2435 | ||
2436 | /* reg_pfcc_pfcrx | |
2437 | * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: | |
2438 | * 0 - Ignore incoming priority Pause frames on the specified priority | |
2439 | * (default). | |
2440 | * 1 - Respect incoming priority Pause frames on the specified priority. | |
2441 | * Access: RW | |
2442 | */ | |
2443 | MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); | |
2444 | ||
d81a6bdb IS |
2445 | #define MLXSW_REG_PFCC_ALL_PRIO 0xFF |
2446 | ||
2447 | static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) | |
2448 | { | |
2449 | mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); | |
2450 | mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); | |
2451 | mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); | |
2452 | mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); | |
2453 | } | |
2454 | ||
6f253d83 IS |
2455 | static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) |
2456 | { | |
2457 | MLXSW_REG_ZERO(pfcc, payload); | |
2458 | mlxsw_reg_pfcc_local_port_set(payload, local_port); | |
2459 | } | |
2460 | ||
4ec14b76 IS |
2461 | /* PPCNT - Ports Performance Counters Register |
2462 | * ------------------------------------------- | |
2463 | * The PPCNT register retrieves per port performance counters. | |
2464 | */ | |
2465 | #define MLXSW_REG_PPCNT_ID 0x5008 | |
2466 | #define MLXSW_REG_PPCNT_LEN 0x100 | |
2467 | ||
2468 | static const struct mlxsw_reg_info mlxsw_reg_ppcnt = { | |
2469 | .id = MLXSW_REG_PPCNT_ID, | |
2470 | .len = MLXSW_REG_PPCNT_LEN, | |
2471 | }; | |
2472 | ||
2473 | /* reg_ppcnt_swid | |
2474 | * For HCA: must be always 0. | |
2475 | * Switch partition ID to associate port with. | |
2476 | * Switch partitions are numbered from 0 to 7 inclusively. | |
2477 | * Switch partition 254 indicates stacking ports. | |
2478 | * Switch partition 255 indicates all switch partitions. | |
2479 | * Only valid on Set() operation with local_port=255. | |
2480 | * Access: Index | |
2481 | */ | |
2482 | MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); | |
2483 | ||
2484 | /* reg_ppcnt_local_port | |
2485 | * Local port number. | |
2486 | * 255 indicates all ports on the device, and is only allowed | |
2487 | * for Set() operation. | |
2488 | * Access: Index | |
2489 | */ | |
2490 | MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); | |
2491 | ||
2492 | /* reg_ppcnt_pnat | |
2493 | * Port number access type: | |
2494 | * 0 - Local port number | |
2495 | * 1 - IB port number | |
2496 | * Access: Index | |
2497 | */ | |
2498 | MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); | |
2499 | ||
34dba0a5 IS |
2500 | enum mlxsw_reg_ppcnt_grp { |
2501 | MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, | |
2502 | MLXSW_REG_PPCNT_PRIO_CNT = 0x10, | |
2503 | }; | |
2504 | ||
4ec14b76 IS |
2505 | /* reg_ppcnt_grp |
2506 | * Performance counter group. | |
2507 | * Group 63 indicates all groups. Only valid on Set() operation with | |
2508 | * clr bit set. | |
2509 | * 0x0: IEEE 802.3 Counters | |
2510 | * 0x1: RFC 2863 Counters | |
2511 | * 0x2: RFC 2819 Counters | |
2512 | * 0x3: RFC 3635 Counters | |
2513 | * 0x5: Ethernet Extended Counters | |
2514 | * 0x8: Link Level Retransmission Counters | |
2515 | * 0x10: Per Priority Counters | |
2516 | * 0x11: Per Traffic Class Counters | |
2517 | * 0x12: Physical Layer Counters | |
2518 | * Access: Index | |
2519 | */ | |
2520 | MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); | |
2521 | ||
2522 | /* reg_ppcnt_clr | |
2523 | * Clear counters. Setting the clr bit will reset the counter value | |
2524 | * for all counters in the counter group. This bit can be set | |
2525 | * for both Set() and Get() operation. | |
2526 | * Access: OP | |
2527 | */ | |
2528 | MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); | |
2529 | ||
2530 | /* reg_ppcnt_prio_tc | |
2531 | * Priority for counter set that support per priority, valid values: 0-7. | |
2532 | * Traffic class for counter set that support per traffic class, | |
2533 | * valid values: 0- cap_max_tclass-1 . | |
2534 | * For HCA: cap_max_tclass is always 8. | |
2535 | * Otherwise must be 0. | |
2536 | * Access: Index | |
2537 | */ | |
2538 | MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); | |
2539 | ||
34dba0a5 IS |
2540 | /* Ethernet IEEE 802.3 Counter Group */ |
2541 | ||
4ec14b76 IS |
2542 | /* reg_ppcnt_a_frames_transmitted_ok |
2543 | * Access: RO | |
2544 | */ | |
2545 | MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, | |
2546 | 0x08 + 0x00, 0, 64); | |
2547 | ||
2548 | /* reg_ppcnt_a_frames_received_ok | |
2549 | * Access: RO | |
2550 | */ | |
2551 | MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, | |
2552 | 0x08 + 0x08, 0, 64); | |
2553 | ||
2554 | /* reg_ppcnt_a_frame_check_sequence_errors | |
2555 | * Access: RO | |
2556 | */ | |
2557 | MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, | |
2558 | 0x08 + 0x10, 0, 64); | |
2559 | ||
2560 | /* reg_ppcnt_a_alignment_errors | |
2561 | * Access: RO | |
2562 | */ | |
2563 | MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, | |
2564 | 0x08 + 0x18, 0, 64); | |
2565 | ||
2566 | /* reg_ppcnt_a_octets_transmitted_ok | |
2567 | * Access: RO | |
2568 | */ | |
2569 | MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, | |
2570 | 0x08 + 0x20, 0, 64); | |
2571 | ||
2572 | /* reg_ppcnt_a_octets_received_ok | |
2573 | * Access: RO | |
2574 | */ | |
2575 | MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, | |
2576 | 0x08 + 0x28, 0, 64); | |
2577 | ||
2578 | /* reg_ppcnt_a_multicast_frames_xmitted_ok | |
2579 | * Access: RO | |
2580 | */ | |
2581 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, | |
2582 | 0x08 + 0x30, 0, 64); | |
2583 | ||
2584 | /* reg_ppcnt_a_broadcast_frames_xmitted_ok | |
2585 | * Access: RO | |
2586 | */ | |
2587 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, | |
2588 | 0x08 + 0x38, 0, 64); | |
2589 | ||
2590 | /* reg_ppcnt_a_multicast_frames_received_ok | |
2591 | * Access: RO | |
2592 | */ | |
2593 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, | |
2594 | 0x08 + 0x40, 0, 64); | |
2595 | ||
2596 | /* reg_ppcnt_a_broadcast_frames_received_ok | |
2597 | * Access: RO | |
2598 | */ | |
2599 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, | |
2600 | 0x08 + 0x48, 0, 64); | |
2601 | ||
2602 | /* reg_ppcnt_a_in_range_length_errors | |
2603 | * Access: RO | |
2604 | */ | |
2605 | MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, | |
2606 | 0x08 + 0x50, 0, 64); | |
2607 | ||
2608 | /* reg_ppcnt_a_out_of_range_length_field | |
2609 | * Access: RO | |
2610 | */ | |
2611 | MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, | |
2612 | 0x08 + 0x58, 0, 64); | |
2613 | ||
2614 | /* reg_ppcnt_a_frame_too_long_errors | |
2615 | * Access: RO | |
2616 | */ | |
2617 | MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, | |
2618 | 0x08 + 0x60, 0, 64); | |
2619 | ||
2620 | /* reg_ppcnt_a_symbol_error_during_carrier | |
2621 | * Access: RO | |
2622 | */ | |
2623 | MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, | |
2624 | 0x08 + 0x68, 0, 64); | |
2625 | ||
2626 | /* reg_ppcnt_a_mac_control_frames_transmitted | |
2627 | * Access: RO | |
2628 | */ | |
2629 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, | |
2630 | 0x08 + 0x70, 0, 64); | |
2631 | ||
2632 | /* reg_ppcnt_a_mac_control_frames_received | |
2633 | * Access: RO | |
2634 | */ | |
2635 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, | |
2636 | 0x08 + 0x78, 0, 64); | |
2637 | ||
2638 | /* reg_ppcnt_a_unsupported_opcodes_received | |
2639 | * Access: RO | |
2640 | */ | |
2641 | MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, | |
2642 | 0x08 + 0x80, 0, 64); | |
2643 | ||
2644 | /* reg_ppcnt_a_pause_mac_ctrl_frames_received | |
2645 | * Access: RO | |
2646 | */ | |
2647 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, | |
2648 | 0x08 + 0x88, 0, 64); | |
2649 | ||
2650 | /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted | |
2651 | * Access: RO | |
2652 | */ | |
2653 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, | |
2654 | 0x08 + 0x90, 0, 64); | |
2655 | ||
34dba0a5 IS |
2656 | /* Ethernet Per Priority Group Counters */ |
2657 | ||
2658 | /* reg_ppcnt_rx_octets | |
2659 | * Access: RO | |
2660 | */ | |
2661 | MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64); | |
2662 | ||
2663 | /* reg_ppcnt_rx_frames | |
2664 | * Access: RO | |
2665 | */ | |
2666 | MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64); | |
2667 | ||
2668 | /* reg_ppcnt_tx_octets | |
2669 | * Access: RO | |
2670 | */ | |
2671 | MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64); | |
2672 | ||
2673 | /* reg_ppcnt_tx_frames | |
2674 | * Access: RO | |
2675 | */ | |
2676 | MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64); | |
2677 | ||
2678 | /* reg_ppcnt_rx_pause | |
2679 | * Access: RO | |
2680 | */ | |
2681 | MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64); | |
2682 | ||
2683 | /* reg_ppcnt_rx_pause_duration | |
2684 | * Access: RO | |
2685 | */ | |
2686 | MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64); | |
2687 | ||
2688 | /* reg_ppcnt_tx_pause | |
2689 | * Access: RO | |
2690 | */ | |
2691 | MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64); | |
2692 | ||
2693 | /* reg_ppcnt_tx_pause_duration | |
2694 | * Access: RO | |
2695 | */ | |
2696 | MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64); | |
2697 | ||
2698 | /* reg_ppcnt_rx_pause_transition | |
2699 | * Access: RO | |
2700 | */ | |
2701 | MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64); | |
2702 | ||
2703 | static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, | |
2704 | enum mlxsw_reg_ppcnt_grp grp, | |
2705 | u8 prio_tc) | |
4ec14b76 IS |
2706 | { |
2707 | MLXSW_REG_ZERO(ppcnt, payload); | |
2708 | mlxsw_reg_ppcnt_swid_set(payload, 0); | |
2709 | mlxsw_reg_ppcnt_local_port_set(payload, local_port); | |
2710 | mlxsw_reg_ppcnt_pnat_set(payload, 0); | |
34dba0a5 | 2711 | mlxsw_reg_ppcnt_grp_set(payload, grp); |
4ec14b76 | 2712 | mlxsw_reg_ppcnt_clr_set(payload, 0); |
34dba0a5 | 2713 | mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); |
4ec14b76 IS |
2714 | } |
2715 | ||
b98ff151 IS |
2716 | /* PPTB - Port Prio To Buffer Register |
2717 | * ----------------------------------- | |
2718 | * Configures the switch priority to buffer table. | |
2719 | */ | |
2720 | #define MLXSW_REG_PPTB_ID 0x500B | |
2721 | #define MLXSW_REG_PPTB_LEN 0x0C | |
2722 | ||
2723 | static const struct mlxsw_reg_info mlxsw_reg_pptb = { | |
2724 | .id = MLXSW_REG_PPTB_ID, | |
2725 | .len = MLXSW_REG_PPTB_LEN, | |
2726 | }; | |
2727 | ||
2728 | enum { | |
2729 | MLXSW_REG_PPTB_MM_UM, | |
2730 | MLXSW_REG_PPTB_MM_UNICAST, | |
2731 | MLXSW_REG_PPTB_MM_MULTICAST, | |
2732 | }; | |
2733 | ||
2734 | /* reg_pptb_mm | |
2735 | * Mapping mode. | |
2736 | * 0 - Map both unicast and multicast packets to the same buffer. | |
2737 | * 1 - Map only unicast packets. | |
2738 | * 2 - Map only multicast packets. | |
2739 | * Access: Index | |
2740 | * | |
2741 | * Note: SwitchX-2 only supports the first option. | |
2742 | */ | |
2743 | MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); | |
2744 | ||
2745 | /* reg_pptb_local_port | |
2746 | * Local port number. | |
2747 | * Access: Index | |
2748 | */ | |
2749 | MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); | |
2750 | ||
2751 | /* reg_pptb_um | |
2752 | * Enables the update of the untagged_buf field. | |
2753 | * Access: RW | |
2754 | */ | |
2755 | MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); | |
2756 | ||
2757 | /* reg_pptb_pm | |
2758 | * Enables the update of the prio_to_buff field. | |
2759 | * Bit <i> is a flag for updating the mapping for switch priority <i>. | |
2760 | * Access: RW | |
2761 | */ | |
2762 | MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); | |
2763 | ||
2764 | /* reg_pptb_prio_to_buff | |
2765 | * Mapping of switch priority <i> to one of the allocated receive port | |
2766 | * buffers. | |
2767 | * Access: RW | |
2768 | */ | |
2769 | MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); | |
2770 | ||
2771 | /* reg_pptb_pm_msb | |
2772 | * Enables the update of the prio_to_buff field. | |
2773 | * Bit <i> is a flag for updating the mapping for switch priority <i+8>. | |
2774 | * Access: RW | |
2775 | */ | |
2776 | MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); | |
2777 | ||
2778 | /* reg_pptb_untagged_buff | |
2779 | * Mapping of untagged frames to one of the allocated receive port buffers. | |
2780 | * Access: RW | |
2781 | * | |
2782 | * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for | |
2783 | * Spectrum, as it maps untagged packets based on the default switch priority. | |
2784 | */ | |
2785 | MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); | |
2786 | ||
2787 | #define MLXSW_REG_PPTB_ALL_PRIO 0xFF | |
2788 | ||
2789 | static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) | |
2790 | { | |
2791 | MLXSW_REG_ZERO(pptb, payload); | |
2792 | mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); | |
2793 | mlxsw_reg_pptb_local_port_set(payload, local_port); | |
2794 | mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); | |
2795 | } | |
2796 | ||
e0594369 JP |
2797 | /* PBMC - Port Buffer Management Control Register |
2798 | * ---------------------------------------------- | |
2799 | * The PBMC register configures and retrieves the port packet buffer | |
2800 | * allocation for different Prios, and the Pause threshold management. | |
2801 | */ | |
2802 | #define MLXSW_REG_PBMC_ID 0x500C | |
7ad7cd61 | 2803 | #define MLXSW_REG_PBMC_LEN 0x6C |
e0594369 JP |
2804 | |
2805 | static const struct mlxsw_reg_info mlxsw_reg_pbmc = { | |
2806 | .id = MLXSW_REG_PBMC_ID, | |
2807 | .len = MLXSW_REG_PBMC_LEN, | |
2808 | }; | |
2809 | ||
2810 | /* reg_pbmc_local_port | |
2811 | * Local port number. | |
2812 | * Access: Index | |
2813 | */ | |
2814 | MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); | |
2815 | ||
2816 | /* reg_pbmc_xoff_timer_value | |
2817 | * When device generates a pause frame, it uses this value as the pause | |
2818 | * timer (time for the peer port to pause in quota-512 bit time). | |
2819 | * Access: RW | |
2820 | */ | |
2821 | MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); | |
2822 | ||
2823 | /* reg_pbmc_xoff_refresh | |
2824 | * The time before a new pause frame should be sent to refresh the pause RW | |
2825 | * state. Using the same units as xoff_timer_value above (in quota-512 bit | |
2826 | * time). | |
2827 | * Access: RW | |
2828 | */ | |
2829 | MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); | |
2830 | ||
d6b7c13b IS |
2831 | #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 |
2832 | ||
e0594369 JP |
2833 | /* reg_pbmc_buf_lossy |
2834 | * The field indicates if the buffer is lossy. | |
2835 | * 0 - Lossless | |
2836 | * 1 - Lossy | |
2837 | * Access: RW | |
2838 | */ | |
2839 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); | |
2840 | ||
2841 | /* reg_pbmc_buf_epsb | |
2842 | * Eligible for Port Shared buffer. | |
2843 | * If epsb is set, packets assigned to buffer are allowed to insert the port | |
2844 | * shared buffer. | |
2845 | * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. | |
2846 | * Access: RW | |
2847 | */ | |
2848 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); | |
2849 | ||
2850 | /* reg_pbmc_buf_size | |
2851 | * The part of the packet buffer array is allocated for the specific buffer. | |
2852 | * Units are represented in cells. | |
2853 | * Access: RW | |
2854 | */ | |
2855 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); | |
2856 | ||
155f9de2 IS |
2857 | /* reg_pbmc_buf_xoff_threshold |
2858 | * Once the amount of data in the buffer goes above this value, device | |
2859 | * starts sending PFC frames for all priorities associated with the | |
2860 | * buffer. Units are represented in cells. Reserved in case of lossy | |
2861 | * buffer. | |
2862 | * Access: RW | |
2863 | * | |
2864 | * Note: In Spectrum, reserved for buffer[9]. | |
2865 | */ | |
2866 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, | |
2867 | 0x08, 0x04, false); | |
2868 | ||
2869 | /* reg_pbmc_buf_xon_threshold | |
2870 | * When the amount of data in the buffer goes below this value, device | |
2871 | * stops sending PFC frames for the priorities associated with the | |
2872 | * buffer. Units are represented in cells. Reserved in case of lossy | |
2873 | * buffer. | |
2874 | * Access: RW | |
2875 | * | |
2876 | * Note: In Spectrum, reserved for buffer[9]. | |
2877 | */ | |
2878 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, | |
2879 | 0x08, 0x04, false); | |
2880 | ||
e0594369 JP |
2881 | static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, |
2882 | u16 xoff_timer_value, u16 xoff_refresh) | |
2883 | { | |
2884 | MLXSW_REG_ZERO(pbmc, payload); | |
2885 | mlxsw_reg_pbmc_local_port_set(payload, local_port); | |
2886 | mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); | |
2887 | mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); | |
2888 | } | |
2889 | ||
2890 | static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, | |
2891 | int buf_index, | |
2892 | u16 size) | |
2893 | { | |
2894 | mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); | |
2895 | mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); | |
2896 | mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); | |
2897 | } | |
2898 | ||
155f9de2 IS |
2899 | static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, |
2900 | int buf_index, u16 size, | |
2901 | u16 threshold) | |
2902 | { | |
2903 | mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); | |
2904 | mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); | |
2905 | mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); | |
2906 | mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); | |
2907 | mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); | |
2908 | } | |
2909 | ||
4ec14b76 IS |
2910 | /* PSPA - Port Switch Partition Allocation |
2911 | * --------------------------------------- | |
2912 | * Controls the association of a port with a switch partition and enables | |
2913 | * configuring ports as stacking ports. | |
2914 | */ | |
3f0effd1 | 2915 | #define MLXSW_REG_PSPA_ID 0x500D |
4ec14b76 IS |
2916 | #define MLXSW_REG_PSPA_LEN 0x8 |
2917 | ||
2918 | static const struct mlxsw_reg_info mlxsw_reg_pspa = { | |
2919 | .id = MLXSW_REG_PSPA_ID, | |
2920 | .len = MLXSW_REG_PSPA_LEN, | |
2921 | }; | |
2922 | ||
2923 | /* reg_pspa_swid | |
2924 | * Switch partition ID. | |
2925 | * Access: RW | |
2926 | */ | |
2927 | MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); | |
2928 | ||
2929 | /* reg_pspa_local_port | |
2930 | * Local port number. | |
2931 | * Access: Index | |
2932 | */ | |
2933 | MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); | |
2934 | ||
2935 | /* reg_pspa_sub_port | |
2936 | * Virtual port within the local port. Set to 0 when virtual ports are | |
2937 | * disabled on the local port. | |
2938 | * Access: Index | |
2939 | */ | |
2940 | MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); | |
2941 | ||
2942 | static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) | |
2943 | { | |
2944 | MLXSW_REG_ZERO(pspa, payload); | |
2945 | mlxsw_reg_pspa_swid_set(payload, swid); | |
2946 | mlxsw_reg_pspa_local_port_set(payload, local_port); | |
2947 | mlxsw_reg_pspa_sub_port_set(payload, 0); | |
2948 | } | |
2949 | ||
2950 | /* HTGT - Host Trap Group Table | |
2951 | * ---------------------------- | |
2952 | * Configures the properties for forwarding to CPU. | |
2953 | */ | |
2954 | #define MLXSW_REG_HTGT_ID 0x7002 | |
2955 | #define MLXSW_REG_HTGT_LEN 0x100 | |
2956 | ||
2957 | static const struct mlxsw_reg_info mlxsw_reg_htgt = { | |
2958 | .id = MLXSW_REG_HTGT_ID, | |
2959 | .len = MLXSW_REG_HTGT_LEN, | |
2960 | }; | |
2961 | ||
2962 | /* reg_htgt_swid | |
2963 | * Switch partition ID. | |
2964 | * Access: Index | |
2965 | */ | |
2966 | MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); | |
2967 | ||
2968 | #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ | |
2969 | ||
2970 | /* reg_htgt_type | |
2971 | * CPU path type. | |
2972 | * Access: RW | |
2973 | */ | |
2974 | MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); | |
2975 | ||
801bd3de IS |
2976 | enum mlxsw_reg_htgt_trap_group { |
2977 | MLXSW_REG_HTGT_TRAP_GROUP_EMAD, | |
2978 | MLXSW_REG_HTGT_TRAP_GROUP_RX, | |
2979 | MLXSW_REG_HTGT_TRAP_GROUP_CTRL, | |
2980 | }; | |
4ec14b76 IS |
2981 | |
2982 | /* reg_htgt_trap_group | |
2983 | * Trap group number. User defined number specifying which trap groups | |
2984 | * should be forwarded to the CPU. The mapping between trap IDs and trap | |
2985 | * groups is configured using HPKT register. | |
2986 | * Access: Index | |
2987 | */ | |
2988 | MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); | |
2989 | ||
2990 | enum { | |
2991 | MLXSW_REG_HTGT_POLICER_DISABLE, | |
2992 | MLXSW_REG_HTGT_POLICER_ENABLE, | |
2993 | }; | |
2994 | ||
2995 | /* reg_htgt_pide | |
2996 | * Enable policer ID specified using 'pid' field. | |
2997 | * Access: RW | |
2998 | */ | |
2999 | MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); | |
3000 | ||
3001 | /* reg_htgt_pid | |
3002 | * Policer ID for the trap group. | |
3003 | * Access: RW | |
3004 | */ | |
3005 | MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); | |
3006 | ||
3007 | #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 | |
3008 | ||
3009 | /* reg_htgt_mirror_action | |
3010 | * Mirror action to use. | |
3011 | * 0 - Trap to CPU. | |
3012 | * 1 - Trap to CPU and mirror to a mirroring agent. | |
3013 | * 2 - Mirror to a mirroring agent and do not trap to CPU. | |
3014 | * Access: RW | |
3015 | * | |
3016 | * Note: Mirroring to a mirroring agent is only supported in Spectrum. | |
3017 | */ | |
3018 | MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); | |
3019 | ||
3020 | /* reg_htgt_mirroring_agent | |
3021 | * Mirroring agent. | |
3022 | * Access: RW | |
3023 | */ | |
3024 | MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); | |
3025 | ||
3026 | /* reg_htgt_priority | |
3027 | * Trap group priority. | |
3028 | * In case a packet matches multiple classification rules, the packet will | |
3029 | * only be trapped once, based on the trap ID associated with the group (via | |
3030 | * register HPKT) with the highest priority. | |
3031 | * Supported values are 0-7, with 7 represnting the highest priority. | |
3032 | * Access: RW | |
3033 | * | |
3034 | * Note: In SwitchX-2 this field is ignored and the priority value is replaced | |
3035 | * by the 'trap_group' field. | |
3036 | */ | |
3037 | MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); | |
3038 | ||
3039 | /* reg_htgt_local_path_cpu_tclass | |
3040 | * CPU ingress traffic class for the trap group. | |
3041 | * Access: RW | |
3042 | */ | |
3043 | MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); | |
3044 | ||
3045 | #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15 | |
3046 | #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14 | |
801bd3de | 3047 | #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13 |
4ec14b76 IS |
3048 | |
3049 | /* reg_htgt_local_path_rdq | |
3050 | * Receive descriptor queue (RDQ) to use for the trap group. | |
3051 | * Access: RW | |
3052 | */ | |
3053 | MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); | |
3054 | ||
801bd3de IS |
3055 | static inline void mlxsw_reg_htgt_pack(char *payload, |
3056 | enum mlxsw_reg_htgt_trap_group group) | |
4ec14b76 IS |
3057 | { |
3058 | u8 swid, rdq; | |
3059 | ||
3060 | MLXSW_REG_ZERO(htgt, payload); | |
801bd3de IS |
3061 | switch (group) { |
3062 | case MLXSW_REG_HTGT_TRAP_GROUP_EMAD: | |
4ec14b76 IS |
3063 | swid = MLXSW_PORT_SWID_ALL_SWIDS; |
3064 | rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD; | |
801bd3de IS |
3065 | break; |
3066 | case MLXSW_REG_HTGT_TRAP_GROUP_RX: | |
4ec14b76 IS |
3067 | swid = 0; |
3068 | rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX; | |
801bd3de IS |
3069 | break; |
3070 | case MLXSW_REG_HTGT_TRAP_GROUP_CTRL: | |
3071 | swid = 0; | |
3072 | rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL; | |
3073 | break; | |
4ec14b76 IS |
3074 | } |
3075 | mlxsw_reg_htgt_swid_set(payload, swid); | |
3076 | mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); | |
801bd3de | 3077 | mlxsw_reg_htgt_trap_group_set(payload, group); |
4ec14b76 IS |
3078 | mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE); |
3079 | mlxsw_reg_htgt_pid_set(payload, 0); | |
3080 | mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); | |
3081 | mlxsw_reg_htgt_mirroring_agent_set(payload, 0); | |
3082 | mlxsw_reg_htgt_priority_set(payload, 0); | |
3083 | mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7); | |
3084 | mlxsw_reg_htgt_local_path_rdq_set(payload, rdq); | |
3085 | } | |
3086 | ||
3087 | /* HPKT - Host Packet Trap | |
3088 | * ----------------------- | |
3089 | * Configures trap IDs inside trap groups. | |
3090 | */ | |
3091 | #define MLXSW_REG_HPKT_ID 0x7003 | |
3092 | #define MLXSW_REG_HPKT_LEN 0x10 | |
3093 | ||
3094 | static const struct mlxsw_reg_info mlxsw_reg_hpkt = { | |
3095 | .id = MLXSW_REG_HPKT_ID, | |
3096 | .len = MLXSW_REG_HPKT_LEN, | |
3097 | }; | |
3098 | ||
3099 | enum { | |
3100 | MLXSW_REG_HPKT_ACK_NOT_REQUIRED, | |
3101 | MLXSW_REG_HPKT_ACK_REQUIRED, | |
3102 | }; | |
3103 | ||
3104 | /* reg_hpkt_ack | |
3105 | * Require acknowledgements from the host for events. | |
3106 | * If set, then the device will wait for the event it sent to be acknowledged | |
3107 | * by the host. This option is only relevant for event trap IDs. | |
3108 | * Access: RW | |
3109 | * | |
3110 | * Note: Currently not supported by firmware. | |
3111 | */ | |
3112 | MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); | |
3113 | ||
3114 | enum mlxsw_reg_hpkt_action { | |
3115 | MLXSW_REG_HPKT_ACTION_FORWARD, | |
3116 | MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, | |
3117 | MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, | |
3118 | MLXSW_REG_HPKT_ACTION_DISCARD, | |
3119 | MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, | |
3120 | MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, | |
3121 | }; | |
3122 | ||
3123 | /* reg_hpkt_action | |
3124 | * Action to perform on packet when trapped. | |
3125 | * 0 - No action. Forward to CPU based on switching rules. | |
3126 | * 1 - Trap to CPU (CPU receives sole copy). | |
3127 | * 2 - Mirror to CPU (CPU receives a replica of the packet). | |
3128 | * 3 - Discard. | |
3129 | * 4 - Soft discard (allow other traps to act on the packet). | |
3130 | * 5 - Trap and soft discard (allow other traps to overwrite this trap). | |
3131 | * Access: RW | |
3132 | * | |
3133 | * Note: Must be set to 0 (forward) for event trap IDs, as they are already | |
3134 | * addressed to the CPU. | |
3135 | */ | |
3136 | MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); | |
3137 | ||
3138 | /* reg_hpkt_trap_group | |
3139 | * Trap group to associate the trap with. | |
3140 | * Access: RW | |
3141 | */ | |
3142 | MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); | |
3143 | ||
3144 | /* reg_hpkt_trap_id | |
3145 | * Trap ID. | |
3146 | * Access: Index | |
3147 | * | |
3148 | * Note: A trap ID can only be associated with a single trap group. The device | |
3149 | * will associate the trap ID with the last trap group configured. | |
3150 | */ | |
3151 | MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); | |
3152 | ||
3153 | enum { | |
3154 | MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, | |
3155 | MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, | |
3156 | MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, | |
3157 | }; | |
3158 | ||
3159 | /* reg_hpkt_ctrl | |
3160 | * Configure dedicated buffer resources for control packets. | |
3161 | * 0 - Keep factory defaults. | |
3162 | * 1 - Do not use control buffer for this trap ID. | |
3163 | * 2 - Use control buffer for this trap ID. | |
3164 | * Access: RW | |
3165 | */ | |
3166 | MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); | |
3167 | ||
f24af330 | 3168 | static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id) |
4ec14b76 | 3169 | { |
801bd3de | 3170 | enum mlxsw_reg_htgt_trap_group trap_group; |
f24af330 | 3171 | |
4ec14b76 IS |
3172 | MLXSW_REG_ZERO(hpkt, payload); |
3173 | mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); | |
3174 | mlxsw_reg_hpkt_action_set(payload, action); | |
f24af330 IS |
3175 | switch (trap_id) { |
3176 | case MLXSW_TRAP_ID_ETHEMAD: | |
3177 | case MLXSW_TRAP_ID_PUDE: | |
3178 | trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD; | |
3179 | break; | |
3180 | default: | |
3181 | trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX; | |
3182 | break; | |
3183 | } | |
4ec14b76 IS |
3184 | mlxsw_reg_hpkt_trap_group_set(payload, trap_group); |
3185 | mlxsw_reg_hpkt_trap_id_set(payload, trap_id); | |
3186 | mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT); | |
3187 | } | |
3188 | ||
5246f2e2 JP |
3189 | /* MFCR - Management Fan Control Register |
3190 | * -------------------------------------- | |
3191 | * This register controls the settings of the Fan Speed PWM mechanism. | |
3192 | */ | |
3193 | #define MLXSW_REG_MFCR_ID 0x9001 | |
3194 | #define MLXSW_REG_MFCR_LEN 0x08 | |
3195 | ||
3196 | static const struct mlxsw_reg_info mlxsw_reg_mfcr = { | |
3197 | .id = MLXSW_REG_MFCR_ID, | |
3198 | .len = MLXSW_REG_MFCR_LEN, | |
3199 | }; | |
3200 | ||
3201 | enum mlxsw_reg_mfcr_pwm_frequency { | |
3202 | MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, | |
3203 | MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, | |
3204 | MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, | |
3205 | MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, | |
3206 | MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, | |
3207 | MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, | |
3208 | MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, | |
3209 | MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, | |
3210 | }; | |
3211 | ||
3212 | /* reg_mfcr_pwm_frequency | |
3213 | * Controls the frequency of the PWM signal. | |
3214 | * Access: RW | |
3215 | */ | |
3216 | MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6); | |
3217 | ||
3218 | #define MLXSW_MFCR_TACHOS_MAX 10 | |
3219 | ||
3220 | /* reg_mfcr_tacho_active | |
3221 | * Indicates which of the tachometer is active (bit per tachometer). | |
3222 | * Access: RO | |
3223 | */ | |
3224 | MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); | |
3225 | ||
3226 | #define MLXSW_MFCR_PWMS_MAX 5 | |
3227 | ||
3228 | /* reg_mfcr_pwm_active | |
3229 | * Indicates which of the PWM control is active (bit per PWM). | |
3230 | * Access: RO | |
3231 | */ | |
3232 | MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); | |
3233 | ||
3234 | static inline void | |
3235 | mlxsw_reg_mfcr_pack(char *payload, | |
3236 | enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) | |
3237 | { | |
3238 | MLXSW_REG_ZERO(mfcr, payload); | |
3239 | mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); | |
3240 | } | |
3241 | ||
3242 | static inline void | |
3243 | mlxsw_reg_mfcr_unpack(char *payload, | |
3244 | enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, | |
3245 | u16 *p_tacho_active, u8 *p_pwm_active) | |
3246 | { | |
3247 | *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); | |
3248 | *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); | |
3249 | *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); | |
3250 | } | |
3251 | ||
3252 | /* MFSC - Management Fan Speed Control Register | |
3253 | * -------------------------------------------- | |
3254 | * This register controls the settings of the Fan Speed PWM mechanism. | |
3255 | */ | |
3256 | #define MLXSW_REG_MFSC_ID 0x9002 | |
3257 | #define MLXSW_REG_MFSC_LEN 0x08 | |
3258 | ||
3259 | static const struct mlxsw_reg_info mlxsw_reg_mfsc = { | |
3260 | .id = MLXSW_REG_MFSC_ID, | |
3261 | .len = MLXSW_REG_MFSC_LEN, | |
3262 | }; | |
3263 | ||
3264 | /* reg_mfsc_pwm | |
3265 | * Fan pwm to control / monitor. | |
3266 | * Access: Index | |
3267 | */ | |
3268 | MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); | |
3269 | ||
3270 | /* reg_mfsc_pwm_duty_cycle | |
3271 | * Controls the duty cycle of the PWM. Value range from 0..255 to | |
3272 | * represent duty cycle of 0%...100%. | |
3273 | * Access: RW | |
3274 | */ | |
3275 | MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); | |
3276 | ||
3277 | static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, | |
3278 | u8 pwm_duty_cycle) | |
3279 | { | |
3280 | MLXSW_REG_ZERO(mfsc, payload); | |
3281 | mlxsw_reg_mfsc_pwm_set(payload, pwm); | |
3282 | mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); | |
3283 | } | |
3284 | ||
3285 | /* MFSM - Management Fan Speed Measurement | |
3286 | * --------------------------------------- | |
3287 | * This register controls the settings of the Tacho measurements and | |
3288 | * enables reading the Tachometer measurements. | |
3289 | */ | |
3290 | #define MLXSW_REG_MFSM_ID 0x9003 | |
3291 | #define MLXSW_REG_MFSM_LEN 0x08 | |
3292 | ||
3293 | static const struct mlxsw_reg_info mlxsw_reg_mfsm = { | |
3294 | .id = MLXSW_REG_MFSM_ID, | |
3295 | .len = MLXSW_REG_MFSM_LEN, | |
3296 | }; | |
3297 | ||
3298 | /* reg_mfsm_tacho | |
3299 | * Fan tachometer index. | |
3300 | * Access: Index | |
3301 | */ | |
3302 | MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); | |
3303 | ||
3304 | /* reg_mfsm_rpm | |
3305 | * Fan speed (round per minute). | |
3306 | * Access: RO | |
3307 | */ | |
3308 | MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); | |
3309 | ||
3310 | static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) | |
3311 | { | |
3312 | MLXSW_REG_ZERO(mfsm, payload); | |
3313 | mlxsw_reg_mfsm_tacho_set(payload, tacho); | |
3314 | } | |
3315 | ||
85926f87 JP |
3316 | /* MTCAP - Management Temperature Capabilities |
3317 | * ------------------------------------------- | |
3318 | * This register exposes the capabilities of the device and | |
3319 | * system temperature sensing. | |
3320 | */ | |
3321 | #define MLXSW_REG_MTCAP_ID 0x9009 | |
3322 | #define MLXSW_REG_MTCAP_LEN 0x08 | |
3323 | ||
3324 | static const struct mlxsw_reg_info mlxsw_reg_mtcap = { | |
3325 | .id = MLXSW_REG_MTCAP_ID, | |
3326 | .len = MLXSW_REG_MTCAP_LEN, | |
3327 | }; | |
3328 | ||
3329 | /* reg_mtcap_sensor_count | |
3330 | * Number of sensors supported by the device. | |
3331 | * This includes the QSFP module sensors (if exists in the QSFP module). | |
3332 | * Access: RO | |
3333 | */ | |
3334 | MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); | |
3335 | ||
3336 | /* MTMP - Management Temperature | |
3337 | * ----------------------------- | |
3338 | * This register controls the settings of the temperature measurements | |
3339 | * and enables reading the temperature measurements. Note that temperature | |
3340 | * is in 0.125 degrees Celsius. | |
3341 | */ | |
3342 | #define MLXSW_REG_MTMP_ID 0x900A | |
3343 | #define MLXSW_REG_MTMP_LEN 0x20 | |
3344 | ||
3345 | static const struct mlxsw_reg_info mlxsw_reg_mtmp = { | |
3346 | .id = MLXSW_REG_MTMP_ID, | |
3347 | .len = MLXSW_REG_MTMP_LEN, | |
3348 | }; | |
3349 | ||
3350 | /* reg_mtmp_sensor_index | |
3351 | * Sensors index to access. | |
3352 | * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially | |
3353 | * (module 0 is mapped to sensor_index 64). | |
3354 | * Access: Index | |
3355 | */ | |
3356 | MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); | |
3357 | ||
3358 | /* Convert to milli degrees Celsius */ | |
3359 | #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) | |
3360 | ||
3361 | /* reg_mtmp_temperature | |
3362 | * Temperature reading from the sensor. Reading is in 0.125 Celsius | |
3363 | * degrees units. | |
3364 | * Access: RO | |
3365 | */ | |
3366 | MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); | |
3367 | ||
3368 | /* reg_mtmp_mte | |
3369 | * Max Temperature Enable - enables measuring the max temperature on a sensor. | |
3370 | * Access: RW | |
3371 | */ | |
3372 | MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); | |
3373 | ||
3374 | /* reg_mtmp_mtr | |
3375 | * Max Temperature Reset - clears the value of the max temperature register. | |
3376 | * Access: WO | |
3377 | */ | |
3378 | MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); | |
3379 | ||
3380 | /* reg_mtmp_max_temperature | |
3381 | * The highest measured temperature from the sensor. | |
3382 | * When the bit mte is cleared, the field max_temperature is reserved. | |
3383 | * Access: RO | |
3384 | */ | |
3385 | MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); | |
3386 | ||
3387 | #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 | |
3388 | ||
3389 | /* reg_mtmp_sensor_name | |
3390 | * Sensor Name | |
3391 | * Access: RO | |
3392 | */ | |
3393 | MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); | |
3394 | ||
3395 | static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, | |
3396 | bool max_temp_enable, | |
3397 | bool max_temp_reset) | |
3398 | { | |
3399 | MLXSW_REG_ZERO(mtmp, payload); | |
3400 | mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); | |
3401 | mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); | |
3402 | mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); | |
3403 | } | |
3404 | ||
3405 | static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, | |
3406 | unsigned int *p_max_temp, | |
3407 | char *sensor_name) | |
3408 | { | |
3409 | u16 temp; | |
3410 | ||
3411 | if (p_temp) { | |
3412 | temp = mlxsw_reg_mtmp_temperature_get(payload); | |
3413 | *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); | |
3414 | } | |
3415 | if (p_max_temp) { | |
acf35a4e | 3416 | temp = mlxsw_reg_mtmp_max_temperature_get(payload); |
85926f87 JP |
3417 | *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); |
3418 | } | |
3419 | if (sensor_name) | |
3420 | mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); | |
3421 | } | |
3422 | ||
3161c159 IS |
3423 | /* MLCR - Management LED Control Register |
3424 | * -------------------------------------- | |
3425 | * Controls the system LEDs. | |
3426 | */ | |
3427 | #define MLXSW_REG_MLCR_ID 0x902B | |
3428 | #define MLXSW_REG_MLCR_LEN 0x0C | |
3429 | ||
3430 | static const struct mlxsw_reg_info mlxsw_reg_mlcr = { | |
3431 | .id = MLXSW_REG_MLCR_ID, | |
3432 | .len = MLXSW_REG_MLCR_LEN, | |
3433 | }; | |
3434 | ||
3435 | /* reg_mlcr_local_port | |
3436 | * Local port number. | |
3437 | * Access: RW | |
3438 | */ | |
3439 | MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); | |
3440 | ||
3441 | #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF | |
3442 | ||
3443 | /* reg_mlcr_beacon_duration | |
3444 | * Duration of the beacon to be active, in seconds. | |
3445 | * 0x0 - Will turn off the beacon. | |
3446 | * 0xFFFF - Will turn on the beacon until explicitly turned off. | |
3447 | * Access: RW | |
3448 | */ | |
3449 | MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); | |
3450 | ||
3451 | /* reg_mlcr_beacon_remain | |
3452 | * Remaining duration of the beacon, in seconds. | |
3453 | * 0xFFFF indicates an infinite amount of time. | |
3454 | * Access: RO | |
3455 | */ | |
3456 | MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); | |
3457 | ||
3458 | static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, | |
3459 | bool active) | |
3460 | { | |
3461 | MLXSW_REG_ZERO(mlcr, payload); | |
3462 | mlxsw_reg_mlcr_local_port_set(payload, local_port); | |
3463 | mlxsw_reg_mlcr_beacon_duration_set(payload, active ? | |
3464 | MLXSW_REG_MLCR_DURATION_MAX : 0); | |
3465 | } | |
3466 | ||
e0594369 JP |
3467 | /* SBPR - Shared Buffer Pools Register |
3468 | * ----------------------------------- | |
3469 | * The SBPR configures and retrieves the shared buffer pools and configuration. | |
3470 | */ | |
3471 | #define MLXSW_REG_SBPR_ID 0xB001 | |
3472 | #define MLXSW_REG_SBPR_LEN 0x14 | |
3473 | ||
3474 | static const struct mlxsw_reg_info mlxsw_reg_sbpr = { | |
3475 | .id = MLXSW_REG_SBPR_ID, | |
3476 | .len = MLXSW_REG_SBPR_LEN, | |
3477 | }; | |
3478 | ||
497e8592 JP |
3479 | /* shared direstion enum for SBPR, SBCM, SBPM */ |
3480 | enum mlxsw_reg_sbxx_dir { | |
3481 | MLXSW_REG_SBXX_DIR_INGRESS, | |
3482 | MLXSW_REG_SBXX_DIR_EGRESS, | |
e0594369 JP |
3483 | }; |
3484 | ||
3485 | /* reg_sbpr_dir | |
3486 | * Direction. | |
3487 | * Access: Index | |
3488 | */ | |
3489 | MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); | |
3490 | ||
3491 | /* reg_sbpr_pool | |
3492 | * Pool index. | |
3493 | * Access: Index | |
3494 | */ | |
3495 | MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); | |
3496 | ||
3497 | /* reg_sbpr_size | |
3498 | * Pool size in buffer cells. | |
3499 | * Access: RW | |
3500 | */ | |
3501 | MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); | |
3502 | ||
3503 | enum mlxsw_reg_sbpr_mode { | |
3504 | MLXSW_REG_SBPR_MODE_STATIC, | |
3505 | MLXSW_REG_SBPR_MODE_DYNAMIC, | |
3506 | }; | |
3507 | ||
3508 | /* reg_sbpr_mode | |
3509 | * Pool quota calculation mode. | |
3510 | * Access: RW | |
3511 | */ | |
3512 | MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); | |
3513 | ||
3514 | static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, | |
497e8592 | 3515 | enum mlxsw_reg_sbxx_dir dir, |
e0594369 JP |
3516 | enum mlxsw_reg_sbpr_mode mode, u32 size) |
3517 | { | |
3518 | MLXSW_REG_ZERO(sbpr, payload); | |
3519 | mlxsw_reg_sbpr_pool_set(payload, pool); | |
3520 | mlxsw_reg_sbpr_dir_set(payload, dir); | |
3521 | mlxsw_reg_sbpr_mode_set(payload, mode); | |
3522 | mlxsw_reg_sbpr_size_set(payload, size); | |
3523 | } | |
3524 | ||
3525 | /* SBCM - Shared Buffer Class Management Register | |
3526 | * ---------------------------------------------- | |
3527 | * The SBCM register configures and retrieves the shared buffer allocation | |
3528 | * and configuration according to Port-PG, including the binding to pool | |
3529 | * and definition of the associated quota. | |
3530 | */ | |
3531 | #define MLXSW_REG_SBCM_ID 0xB002 | |
3532 | #define MLXSW_REG_SBCM_LEN 0x28 | |
3533 | ||
3534 | static const struct mlxsw_reg_info mlxsw_reg_sbcm = { | |
3535 | .id = MLXSW_REG_SBCM_ID, | |
3536 | .len = MLXSW_REG_SBCM_LEN, | |
3537 | }; | |
3538 | ||
3539 | /* reg_sbcm_local_port | |
3540 | * Local port number. | |
3541 | * For Ingress: excludes CPU port and Router port | |
3542 | * For Egress: excludes IP Router | |
3543 | * Access: Index | |
3544 | */ | |
3545 | MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); | |
3546 | ||
3547 | /* reg_sbcm_pg_buff | |
3548 | * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) | |
3549 | * For PG buffer: range is 0..cap_max_pg_buffers - 1 | |
3550 | * For traffic class: range is 0..cap_max_tclass - 1 | |
3551 | * Note that when traffic class is in MC aware mode then the traffic | |
3552 | * classes which are MC aware cannot be configured. | |
3553 | * Access: Index | |
3554 | */ | |
3555 | MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); | |
3556 | ||
e0594369 JP |
3557 | /* reg_sbcm_dir |
3558 | * Direction. | |
3559 | * Access: Index | |
3560 | */ | |
3561 | MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); | |
3562 | ||
3563 | /* reg_sbcm_min_buff | |
3564 | * Minimum buffer size for the limiter, in cells. | |
3565 | * Access: RW | |
3566 | */ | |
3567 | MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); | |
3568 | ||
c30a53c7 JP |
3569 | /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ |
3570 | #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 | |
3571 | #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 | |
3572 | ||
e0594369 JP |
3573 | /* reg_sbcm_max_buff |
3574 | * When the pool associated to the port-pg/tclass is configured to | |
3575 | * static, Maximum buffer size for the limiter configured in cells. | |
3576 | * When the pool associated to the port-pg/tclass is configured to | |
3577 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
3578 | * the following values: | |
3579 | * 0: 0 | |
3580 | * i: (1/128)*2^(i-1), for i=1..14 | |
3581 | * 0xFF: Infinity | |
3582 | * Access: RW | |
3583 | */ | |
3584 | MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); | |
3585 | ||
3586 | /* reg_sbcm_pool | |
3587 | * Association of the port-priority to a pool. | |
3588 | * Access: RW | |
3589 | */ | |
3590 | MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); | |
3591 | ||
3592 | static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, | |
497e8592 | 3593 | enum mlxsw_reg_sbxx_dir dir, |
e0594369 JP |
3594 | u32 min_buff, u32 max_buff, u8 pool) |
3595 | { | |
3596 | MLXSW_REG_ZERO(sbcm, payload); | |
3597 | mlxsw_reg_sbcm_local_port_set(payload, local_port); | |
3598 | mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); | |
3599 | mlxsw_reg_sbcm_dir_set(payload, dir); | |
3600 | mlxsw_reg_sbcm_min_buff_set(payload, min_buff); | |
3601 | mlxsw_reg_sbcm_max_buff_set(payload, max_buff); | |
3602 | mlxsw_reg_sbcm_pool_set(payload, pool); | |
3603 | } | |
3604 | ||
9efc8f65 JP |
3605 | /* SBPM - Shared Buffer Port Management Register |
3606 | * --------------------------------------------- | |
e0594369 JP |
3607 | * The SBPM register configures and retrieves the shared buffer allocation |
3608 | * and configuration according to Port-Pool, including the definition | |
3609 | * of the associated quota. | |
3610 | */ | |
3611 | #define MLXSW_REG_SBPM_ID 0xB003 | |
3612 | #define MLXSW_REG_SBPM_LEN 0x28 | |
3613 | ||
3614 | static const struct mlxsw_reg_info mlxsw_reg_sbpm = { | |
3615 | .id = MLXSW_REG_SBPM_ID, | |
3616 | .len = MLXSW_REG_SBPM_LEN, | |
3617 | }; | |
3618 | ||
3619 | /* reg_sbpm_local_port | |
3620 | * Local port number. | |
3621 | * For Ingress: excludes CPU port and Router port | |
3622 | * For Egress: excludes IP Router | |
3623 | * Access: Index | |
3624 | */ | |
3625 | MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); | |
3626 | ||
3627 | /* reg_sbpm_pool | |
3628 | * The pool associated to quota counting on the local_port. | |
3629 | * Access: Index | |
3630 | */ | |
3631 | MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); | |
3632 | ||
e0594369 JP |
3633 | /* reg_sbpm_dir |
3634 | * Direction. | |
3635 | * Access: Index | |
3636 | */ | |
3637 | MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); | |
3638 | ||
42a7f1d7 JP |
3639 | /* reg_sbpm_buff_occupancy |
3640 | * Current buffer occupancy in cells. | |
3641 | * Access: RO | |
3642 | */ | |
3643 | MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); | |
3644 | ||
3645 | /* reg_sbpm_clr | |
3646 | * Clear Max Buffer Occupancy | |
3647 | * When this bit is set, max_buff_occupancy field is cleared (and a | |
3648 | * new max value is tracked from the time the clear was performed). | |
3649 | * Access: OP | |
3650 | */ | |
3651 | MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); | |
3652 | ||
3653 | /* reg_sbpm_max_buff_occupancy | |
3654 | * Maximum value of buffer occupancy in cells monitored. Cleared by | |
3655 | * writing to the clr field. | |
3656 | * Access: RO | |
3657 | */ | |
3658 | MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); | |
3659 | ||
e0594369 JP |
3660 | /* reg_sbpm_min_buff |
3661 | * Minimum buffer size for the limiter, in cells. | |
3662 | * Access: RW | |
3663 | */ | |
3664 | MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); | |
3665 | ||
3666 | /* reg_sbpm_max_buff | |
3667 | * When the pool associated to the port-pg/tclass is configured to | |
3668 | * static, Maximum buffer size for the limiter configured in cells. | |
3669 | * When the pool associated to the port-pg/tclass is configured to | |
3670 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
3671 | * the following values: | |
3672 | * 0: 0 | |
3673 | * i: (1/128)*2^(i-1), for i=1..14 | |
3674 | * 0xFF: Infinity | |
3675 | * Access: RW | |
3676 | */ | |
3677 | MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); | |
3678 | ||
3679 | static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, | |
42a7f1d7 | 3680 | enum mlxsw_reg_sbxx_dir dir, bool clr, |
e0594369 JP |
3681 | u32 min_buff, u32 max_buff) |
3682 | { | |
3683 | MLXSW_REG_ZERO(sbpm, payload); | |
3684 | mlxsw_reg_sbpm_local_port_set(payload, local_port); | |
3685 | mlxsw_reg_sbpm_pool_set(payload, pool); | |
3686 | mlxsw_reg_sbpm_dir_set(payload, dir); | |
42a7f1d7 | 3687 | mlxsw_reg_sbpm_clr_set(payload, clr); |
e0594369 JP |
3688 | mlxsw_reg_sbpm_min_buff_set(payload, min_buff); |
3689 | mlxsw_reg_sbpm_max_buff_set(payload, max_buff); | |
3690 | } | |
3691 | ||
42a7f1d7 JP |
3692 | static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, |
3693 | u32 *p_max_buff_occupancy) | |
3694 | { | |
3695 | *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); | |
3696 | *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); | |
3697 | } | |
3698 | ||
e0594369 JP |
3699 | /* SBMM - Shared Buffer Multicast Management Register |
3700 | * -------------------------------------------------- | |
3701 | * The SBMM register configures and retrieves the shared buffer allocation | |
3702 | * and configuration for MC packets according to Switch-Priority, including | |
3703 | * the binding to pool and definition of the associated quota. | |
3704 | */ | |
3705 | #define MLXSW_REG_SBMM_ID 0xB004 | |
3706 | #define MLXSW_REG_SBMM_LEN 0x28 | |
3707 | ||
3708 | static const struct mlxsw_reg_info mlxsw_reg_sbmm = { | |
3709 | .id = MLXSW_REG_SBMM_ID, | |
3710 | .len = MLXSW_REG_SBMM_LEN, | |
3711 | }; | |
3712 | ||
3713 | /* reg_sbmm_prio | |
3714 | * Switch Priority. | |
3715 | * Access: Index | |
3716 | */ | |
3717 | MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); | |
3718 | ||
3719 | /* reg_sbmm_min_buff | |
3720 | * Minimum buffer size for the limiter, in cells. | |
3721 | * Access: RW | |
3722 | */ | |
3723 | MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); | |
3724 | ||
3725 | /* reg_sbmm_max_buff | |
3726 | * When the pool associated to the port-pg/tclass is configured to | |
3727 | * static, Maximum buffer size for the limiter configured in cells. | |
3728 | * When the pool associated to the port-pg/tclass is configured to | |
3729 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
3730 | * the following values: | |
3731 | * 0: 0 | |
3732 | * i: (1/128)*2^(i-1), for i=1..14 | |
3733 | * 0xFF: Infinity | |
3734 | * Access: RW | |
3735 | */ | |
3736 | MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); | |
3737 | ||
3738 | /* reg_sbmm_pool | |
3739 | * Association of the port-priority to a pool. | |
3740 | * Access: RW | |
3741 | */ | |
3742 | MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); | |
3743 | ||
3744 | static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, | |
3745 | u32 max_buff, u8 pool) | |
3746 | { | |
3747 | MLXSW_REG_ZERO(sbmm, payload); | |
3748 | mlxsw_reg_sbmm_prio_set(payload, prio); | |
3749 | mlxsw_reg_sbmm_min_buff_set(payload, min_buff); | |
3750 | mlxsw_reg_sbmm_max_buff_set(payload, max_buff); | |
3751 | mlxsw_reg_sbmm_pool_set(payload, pool); | |
3752 | } | |
3753 | ||
26176def JP |
3754 | /* SBSR - Shared Buffer Status Register |
3755 | * ------------------------------------ | |
3756 | * The SBSR register retrieves the shared buffer occupancy according to | |
3757 | * Port-Pool. Note that this register enables reading a large amount of data. | |
3758 | * It is the user's responsibility to limit the amount of data to ensure the | |
3759 | * response can match the maximum transfer unit. In case the response exceeds | |
3760 | * the maximum transport unit, it will be truncated with no special notice. | |
3761 | */ | |
3762 | #define MLXSW_REG_SBSR_ID 0xB005 | |
3763 | #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ | |
3764 | #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ | |
3765 | #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 | |
3766 | #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ | |
3767 | MLXSW_REG_SBSR_REC_LEN * \ | |
3768 | MLXSW_REG_SBSR_REC_MAX_COUNT) | |
3769 | ||
3770 | static const struct mlxsw_reg_info mlxsw_reg_sbsr = { | |
3771 | .id = MLXSW_REG_SBSR_ID, | |
3772 | .len = MLXSW_REG_SBSR_LEN, | |
3773 | }; | |
3774 | ||
3775 | /* reg_sbsr_clr | |
3776 | * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy | |
3777 | * field is cleared (and a new max value is tracked from the time the clear | |
3778 | * was performed). | |
3779 | * Access: OP | |
3780 | */ | |
3781 | MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); | |
3782 | ||
3783 | /* reg_sbsr_ingress_port_mask | |
3784 | * Bit vector for all ingress network ports. | |
3785 | * Indicates which of the ports (for which the relevant bit is set) | |
3786 | * are affected by the set operation. Configuration of any other port | |
3787 | * does not change. | |
3788 | * Access: Index | |
3789 | */ | |
3790 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); | |
3791 | ||
3792 | /* reg_sbsr_pg_buff_mask | |
3793 | * Bit vector for all switch priority groups. | |
3794 | * Indicates which of the priorities (for which the relevant bit is set) | |
3795 | * are affected by the set operation. Configuration of any other priority | |
3796 | * does not change. | |
3797 | * Range is 0..cap_max_pg_buffers - 1 | |
3798 | * Access: Index | |
3799 | */ | |
3800 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); | |
3801 | ||
3802 | /* reg_sbsr_egress_port_mask | |
3803 | * Bit vector for all egress network ports. | |
3804 | * Indicates which of the ports (for which the relevant bit is set) | |
3805 | * are affected by the set operation. Configuration of any other port | |
3806 | * does not change. | |
3807 | * Access: Index | |
3808 | */ | |
3809 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); | |
3810 | ||
3811 | /* reg_sbsr_tclass_mask | |
3812 | * Bit vector for all traffic classes. | |
3813 | * Indicates which of the traffic classes (for which the relevant bit is | |
3814 | * set) are affected by the set operation. Configuration of any other | |
3815 | * traffic class does not change. | |
3816 | * Range is 0..cap_max_tclass - 1 | |
3817 | * Access: Index | |
3818 | */ | |
3819 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); | |
3820 | ||
3821 | static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) | |
3822 | { | |
3823 | MLXSW_REG_ZERO(sbsr, payload); | |
3824 | mlxsw_reg_sbsr_clr_set(payload, clr); | |
3825 | } | |
3826 | ||
3827 | /* reg_sbsr_rec_buff_occupancy | |
3828 | * Current buffer occupancy in cells. | |
3829 | * Access: RO | |
3830 | */ | |
3831 | MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, | |
3832 | 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); | |
3833 | ||
3834 | /* reg_sbsr_rec_max_buff_occupancy | |
3835 | * Maximum value of buffer occupancy in cells monitored. Cleared by | |
3836 | * writing to the clr field. | |
3837 | * Access: RO | |
3838 | */ | |
3839 | MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, | |
3840 | 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); | |
3841 | ||
3842 | static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, | |
3843 | u32 *p_buff_occupancy, | |
3844 | u32 *p_max_buff_occupancy) | |
3845 | { | |
3846 | *p_buff_occupancy = | |
3847 | mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); | |
3848 | *p_max_buff_occupancy = | |
3849 | mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); | |
3850 | } | |
3851 | ||
4ec14b76 IS |
3852 | static inline const char *mlxsw_reg_id_str(u16 reg_id) |
3853 | { | |
3854 | switch (reg_id) { | |
3855 | case MLXSW_REG_SGCR_ID: | |
3856 | return "SGCR"; | |
3857 | case MLXSW_REG_SPAD_ID: | |
3858 | return "SPAD"; | |
fabe5483 ER |
3859 | case MLXSW_REG_SMID_ID: |
3860 | return "SMID"; | |
e61011b5 IS |
3861 | case MLXSW_REG_SSPR_ID: |
3862 | return "SSPR"; | |
e534a56a JP |
3863 | case MLXSW_REG_SFDAT_ID: |
3864 | return "SFDAT"; | |
236033b3 JP |
3865 | case MLXSW_REG_SFD_ID: |
3866 | return "SFD"; | |
f5d88f58 JP |
3867 | case MLXSW_REG_SFN_ID: |
3868 | return "SFN"; | |
4ec14b76 IS |
3869 | case MLXSW_REG_SPMS_ID: |
3870 | return "SPMS"; | |
b2e345f9 ER |
3871 | case MLXSW_REG_SPVID_ID: |
3872 | return "SPVID"; | |
3873 | case MLXSW_REG_SPVM_ID: | |
3874 | return "SPVM"; | |
148f472d IS |
3875 | case MLXSW_REG_SPAFT_ID: |
3876 | return "SPAFT"; | |
4ec14b76 IS |
3877 | case MLXSW_REG_SFGC_ID: |
3878 | return "SFGC"; | |
3879 | case MLXSW_REG_SFTR_ID: | |
3880 | return "SFTR"; | |
41933271 IS |
3881 | case MLXSW_REG_SFDF_ID: |
3882 | return "SFDF"; | |
d1d40be0 JP |
3883 | case MLXSW_REG_SLDR_ID: |
3884 | return "SLDR"; | |
3885 | case MLXSW_REG_SLCR_ID: | |
3886 | return "SLCR"; | |
3887 | case MLXSW_REG_SLCOR_ID: | |
3888 | return "SLCOR"; | |
4ec14b76 IS |
3889 | case MLXSW_REG_SPMLR_ID: |
3890 | return "SPMLR"; | |
64790239 IS |
3891 | case MLXSW_REG_SVFA_ID: |
3892 | return "SVFA"; | |
1f65da74 IS |
3893 | case MLXSW_REG_SVPE_ID: |
3894 | return "SVPE"; | |
f1fb693a IS |
3895 | case MLXSW_REG_SFMR_ID: |
3896 | return "SFMR"; | |
a4feea74 IS |
3897 | case MLXSW_REG_SPVMLR_ID: |
3898 | return "SPVMLR"; | |
2c63a555 IS |
3899 | case MLXSW_REG_QTCT_ID: |
3900 | return "QTCT"; | |
b9b7cee4 IS |
3901 | case MLXSW_REG_QEEC_ID: |
3902 | return "QEEC"; | |
4ec14b76 IS |
3903 | case MLXSW_REG_PMLP_ID: |
3904 | return "PMLP"; | |
3905 | case MLXSW_REG_PMTU_ID: | |
3906 | return "PMTU"; | |
3907 | case MLXSW_REG_PTYS_ID: | |
3908 | return "PTYS"; | |
3909 | case MLXSW_REG_PPAD_ID: | |
3910 | return "PPAD"; | |
3911 | case MLXSW_REG_PAOS_ID: | |
3912 | return "PAOS"; | |
6f253d83 IS |
3913 | case MLXSW_REG_PFCC_ID: |
3914 | return "PFCC"; | |
4ec14b76 IS |
3915 | case MLXSW_REG_PPCNT_ID: |
3916 | return "PPCNT"; | |
b98ff151 IS |
3917 | case MLXSW_REG_PPTB_ID: |
3918 | return "PPTB"; | |
e0594369 JP |
3919 | case MLXSW_REG_PBMC_ID: |
3920 | return "PBMC"; | |
4ec14b76 IS |
3921 | case MLXSW_REG_PSPA_ID: |
3922 | return "PSPA"; | |
3923 | case MLXSW_REG_HTGT_ID: | |
3924 | return "HTGT"; | |
3925 | case MLXSW_REG_HPKT_ID: | |
3926 | return "HPKT"; | |
5246f2e2 JP |
3927 | case MLXSW_REG_MFCR_ID: |
3928 | return "MFCR"; | |
3929 | case MLXSW_REG_MFSC_ID: | |
3930 | return "MFSC"; | |
3931 | case MLXSW_REG_MFSM_ID: | |
3932 | return "MFSM"; | |
85926f87 JP |
3933 | case MLXSW_REG_MTCAP_ID: |
3934 | return "MTCAP"; | |
3935 | case MLXSW_REG_MTMP_ID: | |
3936 | return "MTMP"; | |
3161c159 IS |
3937 | case MLXSW_REG_MLCR_ID: |
3938 | return "MLCR"; | |
e0594369 JP |
3939 | case MLXSW_REG_SBPR_ID: |
3940 | return "SBPR"; | |
3941 | case MLXSW_REG_SBCM_ID: | |
3942 | return "SBCM"; | |
3943 | case MLXSW_REG_SBPM_ID: | |
3944 | return "SBPM"; | |
3945 | case MLXSW_REG_SBMM_ID: | |
3946 | return "SBMM"; | |
26176def JP |
3947 | case MLXSW_REG_SBSR_ID: |
3948 | return "SBSR"; | |
4ec14b76 IS |
3949 | default: |
3950 | return "*UNKNOWN*"; | |
3951 | } | |
3952 | } | |
3953 | ||
3954 | /* PUDE - Port Up / Down Event | |
3955 | * --------------------------- | |
3956 | * Reports the operational state change of a port. | |
3957 | */ | |
3958 | #define MLXSW_REG_PUDE_LEN 0x10 | |
3959 | ||
3960 | /* reg_pude_swid | |
3961 | * Switch partition ID with which to associate the port. | |
3962 | * Access: Index | |
3963 | */ | |
3964 | MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); | |
3965 | ||
3966 | /* reg_pude_local_port | |
3967 | * Local port number. | |
3968 | * Access: Index | |
3969 | */ | |
3970 | MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); | |
3971 | ||
3972 | /* reg_pude_admin_status | |
3973 | * Port administrative state (the desired state). | |
3974 | * 1 - Up. | |
3975 | * 2 - Down. | |
3976 | * 3 - Up once. This means that in case of link failure, the port won't go | |
3977 | * into polling mode, but will wait to be re-enabled by software. | |
3978 | * 4 - Disabled by system. Can only be set by hardware. | |
3979 | * Access: RO | |
3980 | */ | |
3981 | MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); | |
3982 | ||
3983 | /* reg_pude_oper_status | |
3984 | * Port operatioanl state. | |
3985 | * 1 - Up. | |
3986 | * 2 - Down. | |
3987 | * 3 - Down by port failure. This means that the device will not let the | |
3988 | * port up again until explicitly specified by software. | |
3989 | * Access: RO | |
3990 | */ | |
3991 | MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); | |
3992 | ||
3993 | #endif |