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4ec14b76
IS		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
69c407aa 4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
4ec14b76 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6f9fc3ce 6 * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
4457b3df 7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com>
4ec14b76
IS		 8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the names of the copyright holders nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * Alternatively, this software may be distributed under the terms of the
22 * GNU General Public License ("GPL") version 2 as published by the Free
23 * Software Foundation.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef _MLXSW_REG_H
39#define _MLXSW_REG_H
40
41#include <linux/string.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
44
45#include "item.h"
46#include "port.h"
47
48struct mlxsw_reg_info {
49 u16 id;
50 u16 len; /* In u8 */
51};
52
53#define MLXSW_REG(type) (&mlxsw_reg_##type)
54#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
55#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
56
57/* SGCR - Switch General Configuration Register
58 * --------------------------------------------
59 * This register is used for configuration of the switch capabilities.
60 */
61#define MLXSW_REG_SGCR_ID 0x2000
62#define MLXSW_REG_SGCR_LEN 0x10
63
64static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
65 .id = MLXSW_REG_SGCR_ID,
66 .len = MLXSW_REG_SGCR_LEN,
67};
68
69/* reg_sgcr_llb
70 * Link Local Broadcast (Default=0)
71 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
72 * packets and ignore the IGMP snooping entries.
73 * Access: RW
74 */
75MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
76
77static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
78{
79 MLXSW_REG_ZERO(sgcr, payload);
80 mlxsw_reg_sgcr_llb_set(payload, !!llb);
81}
82
83/* SPAD - Switch Physical Address Register
84 * ---------------------------------------
85 * The SPAD register configures the switch physical MAC address.
86 */
87#define MLXSW_REG_SPAD_ID 0x2002
88#define MLXSW_REG_SPAD_LEN 0x10
89
90static const struct mlxsw_reg_info mlxsw_reg_spad = {
91 .id = MLXSW_REG_SPAD_ID,
92 .len = MLXSW_REG_SPAD_LEN,
93};
94
95/* reg_spad_base_mac
96 * Base MAC address for the switch partitions.
97 * Per switch partition MAC address is equal to:
98 * base_mac + swid
99 * Access: RW
100 */
101MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
102
fabe5483
ER		 103/* SMID - Switch Multicast ID
104 * --------------------------
105 * The MID record maps from a MID (Multicast ID), which is a unique identifier
106 * of the multicast group within the stacking domain, into a list of local
107 * ports into which the packet is replicated.
108 */
109#define MLXSW_REG_SMID_ID 0x2007
110#define MLXSW_REG_SMID_LEN 0x240
111
112static const struct mlxsw_reg_info mlxsw_reg_smid = {
113 .id = MLXSW_REG_SMID_ID,
114 .len = MLXSW_REG_SMID_LEN,
115};
116
117/* reg_smid_swid
118 * Switch partition ID.
119 * Access: Index
120 */
121MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
122
123/* reg_smid_mid
124 * Multicast identifier - global identifier that represents the multicast group
125 * across all devices.
126 * Access: Index
127 */
128MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
129
130/* reg_smid_port
131 * Local port memebership (1 bit per port).
132 * Access: RW
133 */
134MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
135
136/* reg_smid_port_mask
137 * Local port mask (1 bit per port).
138 * Access: W
139 */
140MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
141
142static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
143 u8 port, bool set)
144{
145 MLXSW_REG_ZERO(smid, payload);
146 mlxsw_reg_smid_swid_set(payload, 0);
147 mlxsw_reg_smid_mid_set(payload, mid);
148 mlxsw_reg_smid_port_set(payload, port, set);
149 mlxsw_reg_smid_port_mask_set(payload, port, 1);
150}
151
e61011b5
IS		 152/* SSPR - Switch System Port Record Register
153 * -----------------------------------------
154 * Configures the system port to local port mapping.
155 */
156#define MLXSW_REG_SSPR_ID 0x2008
157#define MLXSW_REG_SSPR_LEN 0x8
158
159static const struct mlxsw_reg_info mlxsw_reg_sspr = {
160 .id = MLXSW_REG_SSPR_ID,
161 .len = MLXSW_REG_SSPR_LEN,
162};
163
164/* reg_sspr_m
165 * Master - if set, then the record describes the master system port.
166 * This is needed in case a local port is mapped into several system ports
167 * (for multipathing). That number will be reported as the source system
168 * port when packets are forwarded to the CPU. Only one master port is allowed
169 * per local port.
170 *
171 * Note: Must be set for Spectrum.
172 * Access: RW
173 */
174MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
175
176/* reg_sspr_local_port
177 * Local port number.
178 *
179 * Access: RW
180 */
181MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
182
183/* reg_sspr_sub_port
184 * Virtual port within the physical port.
185 * Should be set to 0 when virtual ports are not enabled on the port.
186 *
187 * Access: RW
188 */
189MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
190
191/* reg_sspr_system_port
192 * Unique identifier within the stacking domain that represents all the ports
193 * that are available in the system (external ports).
194 *
195 * Currently, only single-ASIC configurations are supported, so we default to
196 * 1:1 mapping between system ports and local ports.
197 * Access: Index
198 */
199MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
200
201static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
202{
203 MLXSW_REG_ZERO(sspr, payload);
204 mlxsw_reg_sspr_m_set(payload, 1);
205 mlxsw_reg_sspr_local_port_set(payload, local_port);
206 mlxsw_reg_sspr_sub_port_set(payload, 0);
207 mlxsw_reg_sspr_system_port_set(payload, local_port);
208}
209
e534a56a
JP		 210/* SFDAT - Switch Filtering Database Aging Time
211 * --------------------------------------------
212 * Controls the Switch aging time. Aging time is able to be set per Switch
213 * Partition.
214 */
215#define MLXSW_REG_SFDAT_ID 0x2009
216#define MLXSW_REG_SFDAT_LEN 0x8
217
218static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
219 .id = MLXSW_REG_SFDAT_ID,
220 .len = MLXSW_REG_SFDAT_LEN,
221};
222
223/* reg_sfdat_swid
224 * Switch partition ID.
225 * Access: Index
226 */
227MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
228
229/* reg_sfdat_age_time
230 * Aging time in seconds
231 * Min - 10 seconds
232 * Max - 1,000,000 seconds
233 * Default is 300 seconds.
234 * Access: RW
235 */
236MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
237
238static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
239{
240 MLXSW_REG_ZERO(sfdat, payload);
241 mlxsw_reg_sfdat_swid_set(payload, 0);
242 mlxsw_reg_sfdat_age_time_set(payload, age_time);
243}
244
236033b3
JP		 245/* SFD - Switch Filtering Database
246 * -------------------------------
247 * The following register defines the access to the filtering database.
248 * The register supports querying, adding, removing and modifying the database.
249 * The access is optimized for bulk updates in which case more than one
250 * FDB record is present in the same command.
251 */
252#define MLXSW_REG_SFD_ID 0x200A
253#define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
254#define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
255#define MLXSW_REG_SFD_REC_MAX_COUNT 64
256#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
257 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
258
259static const struct mlxsw_reg_info mlxsw_reg_sfd = {
260 .id = MLXSW_REG_SFD_ID,
261 .len = MLXSW_REG_SFD_LEN,
262};
263
264/* reg_sfd_swid
265 * Switch partition ID for queries. Reserved on Write.
266 * Access: Index
267 */
268MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
269
270enum mlxsw_reg_sfd_op {
271 /* Dump entire FDB a (process according to record_locator) */
272 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
273 /* Query records by {MAC, VID/FID} value */
274 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
275 /* Query and clear activity. Query records by {MAC, VID/FID} value */
276 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
277 /* Test. Response indicates if each of the records could be
278 * added to the FDB.
279 */
280 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
281 /* Add/modify. Aged-out records cannot be added. This command removes
282 * the learning notification of the {MAC, VID/FID}. Response includes
283 * the entries that were added to the FDB.
284 */
285 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
286 /* Remove record by {MAC, VID/FID}. This command also removes
287 * the learning notification and aged-out notifications
288 * of the {MAC, VID/FID}. The response provides current (pre-removal)
289 * entries as non-aged-out.
290 */
291 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
292 /* Remove learned notification by {MAC, VID/FID}. The response provides
293 * the removed learning notification.
294 */
295 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
296};
297
298/* reg_sfd_op
299 * Operation.
300 * Access: OP
301 */
302MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
303
304/* reg_sfd_record_locator
305 * Used for querying the FDB. Use record_locator=0 to initiate the
306 * query. When a record is returned, a new record_locator is
307 * returned to be used in the subsequent query.
308 * Reserved for database update.
309 * Access: Index
310 */
311MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
312
313/* reg_sfd_num_rec
314 * Request: Number of records to read/add/modify/remove
315 * Response: Number of records read/added/replaced/removed
316 * See above description for more details.
317 * Ranges 0..64
318 * Access: RW
319 */
320MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
321
322static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
323 u32 record_locator)
324{
325 MLXSW_REG_ZERO(sfd, payload);
326 mlxsw_reg_sfd_op_set(payload, op);
327 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
328}
329
330/* reg_sfd_rec_swid
331 * Switch partition ID.
332 * Access: Index
333 */
334MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
335 MLXSW_REG_SFD_REC_LEN, 0x00, false);
336
337enum mlxsw_reg_sfd_rec_type {
338 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
e4bfbae2 339 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
5230b25f 340 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
236033b3
JP		 341};
342
343/* reg_sfd_rec_type
344 * FDB record type.
345 * Access: RW
346 */
347MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
348 MLXSW_REG_SFD_REC_LEN, 0x00, false);
349
350enum mlxsw_reg_sfd_rec_policy {
351 /* Replacement disabled, aging disabled. */
352 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
353 /* (mlag remote): Replacement enabled, aging disabled,
354 * learning notification enabled on this port.
355 */
356 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
357 /* (ingress device): Replacement enabled, aging enabled. */
358 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
359};
360
361/* reg_sfd_rec_policy
362 * Policy.
363 * Access: RW
364 */
365MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
366 MLXSW_REG_SFD_REC_LEN, 0x00, false);
367
368/* reg_sfd_rec_a
369 * Activity. Set for new static entries. Set for static entries if a frame SMAC
370 * lookup hits on the entry.
371 * To clear the a bit, use "query and clear activity" op.
372 * Access: RO
373 */
374MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
375 MLXSW_REG_SFD_REC_LEN, 0x00, false);
376
377/* reg_sfd_rec_mac
378 * MAC address.
379 * Access: Index
380 */
381MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
382 MLXSW_REG_SFD_REC_LEN, 0x02);
383
384enum mlxsw_reg_sfd_rec_action {
385 /* forward */
386 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
387 /* forward and trap, trap_id is FDB_TRAP */
388 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
389 /* trap and do not forward, trap_id is FDB_TRAP */
d82d8c06
IS		 390 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
391 /* forward to IP router */
392 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
236033b3
JP		 393 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
394};
395
396/* reg_sfd_rec_action
397 * Action to apply on the packet.
398 * Note: Dynamic entries can only be configured with NOP action.
399 * Access: RW
400 */
401MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
402 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
403
404/* reg_sfd_uc_sub_port
4e9ec083
JP		 405 * VEPA channel on local port.
406 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
407 * VEPA is not enabled.
236033b3
JP		 408 * Access: RW
409 */
410MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
411 MLXSW_REG_SFD_REC_LEN, 0x08, false);
412
413/* reg_sfd_uc_fid_vid
414 * Filtering ID or VLAN ID
415 * For SwitchX and SwitchX-2:
416 * - Dynamic entries (policy 2,3) use FID
417 * - Static entries (policy 0) use VID
418 * - When independent learning is configured, VID=FID
419 * For Spectrum: use FID for both Dynamic and Static entries.
420 * VID should not be used.
421 * Access: Index
422 */
423MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
424 MLXSW_REG_SFD_REC_LEN, 0x08, false);
425
426/* reg_sfd_uc_system_port
427 * Unique port identifier for the final destination of the packet.
428 * Access: RW
429 */
430MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
431 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
432
e4bfbae2
JP		 433static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
434 enum mlxsw_reg_sfd_rec_type rec_type,
e4bfbae2
JP		 435 const char *mac,
436 enum mlxsw_reg_sfd_rec_action action)
236033b3
JP		 437{
438 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
439
440 if (rec_index >= num_rec)
441 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
442 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
e4bfbae2 443 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
236033b3 444 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
e4bfbae2
JP		 445 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
446}
447
448static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
449 enum mlxsw_reg_sfd_rec_policy policy,
9de6a80e 450 const char *mac, u16 fid_vid,
e4bfbae2
JP		 451 enum mlxsw_reg_sfd_rec_action action,
452 u8 local_port)
453{
454 mlxsw_reg_sfd_rec_pack(payload, rec_index,
5230b25f
ER		 455 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
236033b3 457 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
9de6a80e 458 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
236033b3
JP		 459 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
460}
461
75c09280 462static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
9de6a80e 463 char *mac, u16 *p_fid_vid,
75c09280 464 u8 *p_local_port)
236033b3
JP		 465{
466 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
9de6a80e 467 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
236033b3
JP		 468 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
469}
470
e4bfbae2
JP		 471/* reg_sfd_uc_lag_sub_port
472 * LAG sub port.
473 * Must be 0 if multichannel VEPA is not enabled.
474 * Access: RW
475 */
476MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
477 MLXSW_REG_SFD_REC_LEN, 0x08, false);
478
479/* reg_sfd_uc_lag_fid_vid
480 * Filtering ID or VLAN ID
481 * For SwitchX and SwitchX-2:
482 * - Dynamic entries (policy 2,3) use FID
483 * - Static entries (policy 0) use VID
484 * - When independent learning is configured, VID=FID
485 * For Spectrum: use FID for both Dynamic and Static entries.
486 * VID should not be used.
487 * Access: Index
488 */
489MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
490 MLXSW_REG_SFD_REC_LEN, 0x08, false);
491
afd7f979
IS		 492/* reg_sfd_uc_lag_lag_vid
493 * Indicates VID in case of vFIDs. Reserved for FIDs.
494 * Access: RW
495 */
496MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
497 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
498
e4bfbae2
JP		 499/* reg_sfd_uc_lag_lag_id
500 * LAG Identifier - pointer into the LAG descriptor table.
501 * Access: RW
502 */
503MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
504 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
505
506static inline void
507mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
508 enum mlxsw_reg_sfd_rec_policy policy,
9de6a80e 509 const char *mac, u16 fid_vid,
afd7f979 510 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
e4bfbae2
JP		 511 u16 lag_id)
512{
513 mlxsw_reg_sfd_rec_pack(payload, rec_index,
514 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
5230b25f
ER		 515 mac, action);
516 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
e4bfbae2 517 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
9de6a80e 518 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
afd7f979 519 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
e4bfbae2
JP		 520 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
521}
522
523static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
524 char *mac, u16 *p_vid,
525 u16 *p_lag_id)
526{
527 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
528 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
529 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
530}
531
5230b25f
ER		 532/* reg_sfd_mc_pgi
533 *
534 * Multicast port group index - index into the port group table.
535 * Value 0x1FFF indicates the pgi should point to the MID entry.
536 * For Spectrum this value must be set to 0x1FFF
537 * Access: RW
538 */
539MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
540 MLXSW_REG_SFD_REC_LEN, 0x08, false);
541
542/* reg_sfd_mc_fid_vid
543 *
544 * Filtering ID or VLAN ID
545 * Access: Index
546 */
547MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
548 MLXSW_REG_SFD_REC_LEN, 0x08, false);
549
550/* reg_sfd_mc_mid
551 *
552 * Multicast identifier - global identifier that represents the multicast
553 * group across all devices.
554 * Access: RW
555 */
556MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
557 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
558
559static inline void
560mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
561 const char *mac, u16 fid_vid,
562 enum mlxsw_reg_sfd_rec_action action, u16 mid)
563{
564 mlxsw_reg_sfd_rec_pack(payload, rec_index,
565 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
566 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
567 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
568 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
569}
570
f5d88f58
JP		 571/* SFN - Switch FDB Notification Register
572 * -------------------------------------------
573 * The switch provides notifications on newly learned FDB entries and
574 * aged out entries. The notifications can be polled by software.
575 */
576#define MLXSW_REG_SFN_ID 0x200B
577#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
578#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
579#define MLXSW_REG_SFN_REC_MAX_COUNT 64
580#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
581 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
582
583static const struct mlxsw_reg_info mlxsw_reg_sfn = {
584 .id = MLXSW_REG_SFN_ID,
585 .len = MLXSW_REG_SFN_LEN,
586};
587
588/* reg_sfn_swid
589 * Switch partition ID.
590 * Access: Index
591 */
592MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
593
594/* reg_sfn_num_rec
595 * Request: Number of learned notifications and aged-out notification
596 * records requested.
597 * Response: Number of notification records returned (must be smaller
598 * than or equal to the value requested)
599 * Ranges 0..64
600 * Access: OP
601 */
602MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
603
604static inline void mlxsw_reg_sfn_pack(char *payload)
605{
606 MLXSW_REG_ZERO(sfn, payload);
607 mlxsw_reg_sfn_swid_set(payload, 0);
608 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
609}
610
611/* reg_sfn_rec_swid
612 * Switch partition ID.
613 * Access: RO
614 */
615MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
616 MLXSW_REG_SFN_REC_LEN, 0x00, false);
617
618enum mlxsw_reg_sfn_rec_type {
619 /* MAC addresses learned on a regular port. */
620 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
3b71571c
JP		 621 /* MAC addresses learned on a LAG port. */
622 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
623 /* Aged-out MAC address on a regular port. */
f5d88f58 624 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
3b71571c
JP		 625 /* Aged-out MAC address on a LAG port. */
626 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
f5d88f58
JP		 627};
628
629/* reg_sfn_rec_type
630 * Notification record type.
631 * Access: RO
632 */
633MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
634 MLXSW_REG_SFN_REC_LEN, 0x00, false);
635
636/* reg_sfn_rec_mac
637 * MAC address.
638 * Access: RO
639 */
640MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
641 MLXSW_REG_SFN_REC_LEN, 0x02);
642
8316f087 643/* reg_sfn_mac_sub_port
f5d88f58
JP		 644 * VEPA channel on the local port.
645 * 0 if multichannel VEPA is not enabled.
646 * Access: RO
647 */
648MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
649 MLXSW_REG_SFN_REC_LEN, 0x08, false);
650
8316f087 651/* reg_sfn_mac_fid
f5d88f58
JP		 652 * Filtering identifier.
653 * Access: RO
654 */
655MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
656 MLXSW_REG_SFN_REC_LEN, 0x08, false);
657
8316f087 658/* reg_sfn_mac_system_port
f5d88f58
JP		 659 * Unique port identifier for the final destination of the packet.
660 * Access: RO
661 */
662MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
663 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
664
665static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
666 char *mac, u16 *p_vid,
667 u8 *p_local_port)
668{
669 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
670 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
671 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
672}
673
3b71571c
JP		 674/* reg_sfn_mac_lag_lag_id
675 * LAG ID (pointer into the LAG descriptor table).
676 * Access: RO
677 */
678MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
679 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
680
681static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
682 char *mac, u16 *p_vid,
683 u16 *p_lag_id)
684{
685 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
686 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
687 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
688}
689
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IS		 690/* SPMS - Switch Port MSTP/RSTP State Register
691 * -------------------------------------------
692 * Configures the spanning tree state of a physical port.
693 */
3f0effd1 694#define MLXSW_REG_SPMS_ID 0x200D
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IS		 695#define MLXSW_REG_SPMS_LEN 0x404
696
697static const struct mlxsw_reg_info mlxsw_reg_spms = {
698 .id = MLXSW_REG_SPMS_ID,
699 .len = MLXSW_REG_SPMS_LEN,
700};
701
702/* reg_spms_local_port
703 * Local port number.
704 * Access: Index
705 */
706MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
707
708enum mlxsw_reg_spms_state {
709 MLXSW_REG_SPMS_STATE_NO_CHANGE,
710 MLXSW_REG_SPMS_STATE_DISCARDING,
711 MLXSW_REG_SPMS_STATE_LEARNING,
712 MLXSW_REG_SPMS_STATE_FORWARDING,
713};
714
715/* reg_spms_state
716 * Spanning tree state of each VLAN ID (VID) of the local port.
717 * 0 - Do not change spanning tree state (used only when writing).
718 * 1 - Discarding. No learning or forwarding to/from this port (default).
719 * 2 - Learning. Port is learning, but not forwarding.
720 * 3 - Forwarding. Port is learning and forwarding.
721 * Access: RW
722 */
723MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
724
ebb7963f 725static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
4ec14b76
IS		 726{
727 MLXSW_REG_ZERO(spms, payload);
728 mlxsw_reg_spms_local_port_set(payload, local_port);
ebb7963f
JP		 729}
730
731static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
732 enum mlxsw_reg_spms_state state)
733{
4ec14b76
IS		 734 mlxsw_reg_spms_state_set(payload, vid, state);
735}
736
b2e345f9
ER		 737/* SPVID - Switch Port VID
738 * -----------------------
739 * The switch port VID configures the default VID for a port.
740 */
741#define MLXSW_REG_SPVID_ID 0x200E
742#define MLXSW_REG_SPVID_LEN 0x08
743
744static const struct mlxsw_reg_info mlxsw_reg_spvid = {
745 .id = MLXSW_REG_SPVID_ID,
746 .len = MLXSW_REG_SPVID_LEN,
747};
748
749/* reg_spvid_local_port
750 * Local port number.
751 * Access: Index
752 */
753MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
754
755/* reg_spvid_sub_port
756 * Virtual port within the physical port.
757 * Should be set to 0 when virtual ports are not enabled on the port.
758 * Access: Index
759 */
760MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
761
762/* reg_spvid_pvid
763 * Port default VID
764 * Access: RW
765 */
766MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
767
768static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
769{
770 MLXSW_REG_ZERO(spvid, payload);
771 mlxsw_reg_spvid_local_port_set(payload, local_port);
772 mlxsw_reg_spvid_pvid_set(payload, pvid);
773}
774
775/* SPVM - Switch Port VLAN Membership
776 * ----------------------------------
777 * The Switch Port VLAN Membership register configures the VLAN membership
778 * of a port in a VLAN denoted by VID. VLAN membership is managed per
779 * virtual port. The register can be used to add and remove VID(s) from a port.
780 */
781#define MLXSW_REG_SPVM_ID 0x200F
782#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
783#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
784#define MLXSW_REG_SPVM_REC_MAX_COUNT 256
785#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
786 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
787
788static const struct mlxsw_reg_info mlxsw_reg_spvm = {
789 .id = MLXSW_REG_SPVM_ID,
790 .len = MLXSW_REG_SPVM_LEN,
791};
792
793/* reg_spvm_pt
794 * Priority tagged. If this bit is set, packets forwarded to the port with
795 * untagged VLAN membership (u bit is set) will be tagged with priority tag
796 * (VID=0)
797 * Access: RW
798 */
799MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
800
801/* reg_spvm_pte
802 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
803 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
804 * Access: WO
805 */
806MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
807
808/* reg_spvm_local_port
809 * Local port number.
810 * Access: Index
811 */
812MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
813
814/* reg_spvm_sub_port
815 * Virtual port within the physical port.
816 * Should be set to 0 when virtual ports are not enabled on the port.
817 * Access: Index
818 */
819MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
820
821/* reg_spvm_num_rec
822 * Number of records to update. Each record contains: i, e, u, vid.
823 * Access: OP
824 */
825MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
826
827/* reg_spvm_rec_i
828 * Ingress membership in VLAN ID.
829 * Access: Index
830 */
831MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
832 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
833 MLXSW_REG_SPVM_REC_LEN, 0, false);
834
835/* reg_spvm_rec_e
836 * Egress membership in VLAN ID.
837 * Access: Index
838 */
839MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
840 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
841 MLXSW_REG_SPVM_REC_LEN, 0, false);
842
843/* reg_spvm_rec_u
844 * Untagged - port is an untagged member - egress transmission uses untagged
845 * frames on VID<n>
846 * Access: Index
847 */
848MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
849 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
850 MLXSW_REG_SPVM_REC_LEN, 0, false);
851
852/* reg_spvm_rec_vid
853 * Egress membership in VLAN ID.
854 * Access: Index
855 */
856MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
857 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
858 MLXSW_REG_SPVM_REC_LEN, 0, false);
859
860static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
861 u16 vid_begin, u16 vid_end,
862 bool is_member, bool untagged)
863{
864 int size = vid_end - vid_begin + 1;
865 int i;
866
867 MLXSW_REG_ZERO(spvm, payload);
868 mlxsw_reg_spvm_local_port_set(payload, local_port);
869 mlxsw_reg_spvm_num_rec_set(payload, size);
870
871 for (i = 0; i < size; i++) {
872 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
873 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
874 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
875 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
876 }
877}
878
148f472d
IS		 879/* SPAFT - Switch Port Acceptable Frame Types
880 * ------------------------------------------
881 * The Switch Port Acceptable Frame Types register configures the frame
882 * admittance of the port.
883 */
884#define MLXSW_REG_SPAFT_ID 0x2010
885#define MLXSW_REG_SPAFT_LEN 0x08
886
887static const struct mlxsw_reg_info mlxsw_reg_spaft = {
888 .id = MLXSW_REG_SPAFT_ID,
889 .len = MLXSW_REG_SPAFT_LEN,
890};
891
892/* reg_spaft_local_port
893 * Local port number.
894 * Access: Index
895 *
896 * Note: CPU port is not supported (all tag types are allowed).
897 */
898MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
899
900/* reg_spaft_sub_port
901 * Virtual port within the physical port.
902 * Should be set to 0 when virtual ports are not enabled on the port.
903 * Access: RW
904 */
905MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
906
907/* reg_spaft_allow_untagged
908 * When set, untagged frames on the ingress are allowed (default).
909 * Access: RW
910 */
911MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
912
913/* reg_spaft_allow_prio_tagged
914 * When set, priority tagged frames on the ingress are allowed (default).
915 * Access: RW
916 */
917MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
918
919/* reg_spaft_allow_tagged
920 * When set, tagged frames on the ingress are allowed (default).
921 * Access: RW
922 */
923MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
924
925static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
926 bool allow_untagged)
927{
928 MLXSW_REG_ZERO(spaft, payload);
929 mlxsw_reg_spaft_local_port_set(payload, local_port);
930 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
931 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
932 mlxsw_reg_spaft_allow_tagged_set(payload, true);
933}
934
4ec14b76
IS		 935/* SFGC - Switch Flooding Group Configuration
936 * ------------------------------------------
937 * The following register controls the association of flooding tables and MIDs
938 * to packet types used for flooding.
939 */
36b78e8a 940#define MLXSW_REG_SFGC_ID 0x2011
4ec14b76
IS		 941#define MLXSW_REG_SFGC_LEN 0x10
942
943static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
944 .id = MLXSW_REG_SFGC_ID,
945 .len = MLXSW_REG_SFGC_LEN,
946};
947
948enum mlxsw_reg_sfgc_type {
fa6ad058
IS		 949 MLXSW_REG_SFGC_TYPE_BROADCAST,
950 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
951 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
952 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
953 MLXSW_REG_SFGC_TYPE_RESERVED,
954 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
955 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
956 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
957 MLXSW_REG_SFGC_TYPE_MAX,
4ec14b76
IS		 958};
959
960/* reg_sfgc_type
961 * The traffic type to reach the flooding table.
962 * Access: Index
963 */
964MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
965
966enum mlxsw_reg_sfgc_bridge_type {
967 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
968 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
969};
970
971/* reg_sfgc_bridge_type
972 * Access: Index
973 *
974 * Note: SwitchX-2 only supports 802.1Q mode.
975 */
976MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
977
978enum mlxsw_flood_table_type {
979 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
980 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
981 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
982 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
983 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
984};
985
986/* reg_sfgc_table_type
987 * See mlxsw_flood_table_type
988 * Access: RW
989 *
990 * Note: FID offset and FID types are not supported in SwitchX-2.
991 */
992MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
993
994/* reg_sfgc_flood_table
995 * Flooding table index to associate with the specific type on the specific
996 * switch partition.
997 * Access: RW
998 */
999MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1000
1001/* reg_sfgc_mid
1002 * The multicast ID for the swid. Not supported for Spectrum
1003 * Access: RW
1004 */
1005MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1006
1007/* reg_sfgc_counter_set_type
1008 * Counter Set Type for flow counters.
1009 * Access: RW
1010 */
1011MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1012
1013/* reg_sfgc_counter_index
1014 * Counter Index for flow counters.
1015 * Access: RW
1016 */
1017MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1018
1019static inline void
1020mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1021 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1022 enum mlxsw_flood_table_type table_type,
1023 unsigned int flood_table)
1024{
1025 MLXSW_REG_ZERO(sfgc, payload);
1026 mlxsw_reg_sfgc_type_set(payload, type);
1027 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1028 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1029 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1030 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1031}
1032
1033/* SFTR - Switch Flooding Table Register
1034 * -------------------------------------
1035 * The switch flooding table is used for flooding packet replication. The table
1036 * defines a bit mask of ports for packet replication.
1037 */
1038#define MLXSW_REG_SFTR_ID 0x2012
1039#define MLXSW_REG_SFTR_LEN 0x420
1040
1041static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1042 .id = MLXSW_REG_SFTR_ID,
1043 .len = MLXSW_REG_SFTR_LEN,
1044};
1045
1046/* reg_sftr_swid
1047 * Switch partition ID with which to associate the port.
1048 * Access: Index
1049 */
1050MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1051
1052/* reg_sftr_flood_table
1053 * Flooding table index to associate with the specific type on the specific
1054 * switch partition.
1055 * Access: Index
1056 */
1057MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1058
1059/* reg_sftr_index
1060 * Index. Used as an index into the Flooding Table in case the table is
1061 * configured to use VID / FID or FID Offset.
1062 * Access: Index
1063 */
1064MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1065
1066/* reg_sftr_table_type
1067 * See mlxsw_flood_table_type
1068 * Access: RW
1069 */
1070MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1071
1072/* reg_sftr_range
1073 * Range of entries to update
1074 * Access: Index
1075 */
1076MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1077
1078/* reg_sftr_port
1079 * Local port membership (1 bit per port).
1080 * Access: RW
1081 */
1082MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1083
1084/* reg_sftr_cpu_port_mask
1085 * CPU port mask (1 bit per port).
1086 * Access: W
1087 */
1088MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1089
1090static inline void mlxsw_reg_sftr_pack(char *payload,
1091 unsigned int flood_table,
1092 unsigned int index,
1093 enum mlxsw_flood_table_type table_type,
bc2055f8 1094 unsigned int range, u8 port, bool set)
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IS		 1095{
1096 MLXSW_REG_ZERO(sftr, payload);
1097 mlxsw_reg_sftr_swid_set(payload, 0);
1098 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1099 mlxsw_reg_sftr_index_set(payload, index);
1100 mlxsw_reg_sftr_table_type_set(payload, table_type);
1101 mlxsw_reg_sftr_range_set(payload, range);
bc2055f8
IS		 1102 mlxsw_reg_sftr_port_set(payload, port, set);
1103 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
4ec14b76
IS		 1104}
1105
41933271
IS		 1106/* SFDF - Switch Filtering DB Flush
1107 * --------------------------------
1108 * The switch filtering DB flush register is used to flush the FDB.
1109 * Note that FDB notifications are flushed as well.
1110 */
1111#define MLXSW_REG_SFDF_ID 0x2013
1112#define MLXSW_REG_SFDF_LEN 0x14
1113
1114static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1115 .id = MLXSW_REG_SFDF_ID,
1116 .len = MLXSW_REG_SFDF_LEN,
1117};
1118
1119/* reg_sfdf_swid
1120 * Switch partition ID.
1121 * Access: Index
1122 */
1123MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1124
1125enum mlxsw_reg_sfdf_flush_type {
1126 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1127 MLXSW_REG_SFDF_FLUSH_PER_FID,
1128 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1129 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1130 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1131 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1132};
1133
1134/* reg_sfdf_flush_type
1135 * Flush type.
1136 * 0 - All SWID dynamic entries are flushed.
1137 * 1 - All FID dynamic entries are flushed.
1138 * 2 - All dynamic entries pointing to port are flushed.
1139 * 3 - All FID dynamic entries pointing to port are flushed.
1140 * 4 - All dynamic entries pointing to LAG are flushed.
1141 * 5 - All FID dynamic entries pointing to LAG are flushed.
1142 * Access: RW
1143 */
1144MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1145
1146/* reg_sfdf_flush_static
1147 * Static.
1148 * 0 - Flush only dynamic entries.
1149 * 1 - Flush both dynamic and static entries.
1150 * Access: RW
1151 */
1152MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1153
1154static inline void mlxsw_reg_sfdf_pack(char *payload,
1155 enum mlxsw_reg_sfdf_flush_type type)
1156{
1157 MLXSW_REG_ZERO(sfdf, payload);
1158 mlxsw_reg_sfdf_flush_type_set(payload, type);
1159 mlxsw_reg_sfdf_flush_static_set(payload, true);
1160}
1161
1162/* reg_sfdf_fid
1163 * FID to flush.
1164 * Access: RW
1165 */
1166MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1167
1168/* reg_sfdf_system_port
1169 * Port to flush.
1170 * Access: RW
1171 */
1172MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1173
1174/* reg_sfdf_port_fid_system_port
1175 * Port to flush, pointed to by FID.
1176 * Access: RW
1177 */
1178MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1179
1180/* reg_sfdf_lag_id
1181 * LAG ID to flush.
1182 * Access: RW
1183 */
1184MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1185
1186/* reg_sfdf_lag_fid_lag_id
1187 * LAG ID to flush, pointed to by FID.
1188 * Access: RW
1189 */
1190MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1191
d1d40be0
JP		 1192/* SLDR - Switch LAG Descriptor Register
1193 * -----------------------------------------
1194 * The switch LAG descriptor register is populated by LAG descriptors.
1195 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1196 * max_lag-1.
1197 */
1198#define MLXSW_REG_SLDR_ID 0x2014
1199#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1200
1201static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1202 .id = MLXSW_REG_SLDR_ID,
1203 .len = MLXSW_REG_SLDR_LEN,
1204};
1205
1206enum mlxsw_reg_sldr_op {
1207 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1208 MLXSW_REG_SLDR_OP_LAG_CREATE,
1209 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1210 /* Ports that appear in the list have the Distributor enabled */
1211 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1212 /* Removes ports from the disributor list */
1213 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1214};
1215
1216/* reg_sldr_op
1217 * Operation.
1218 * Access: RW
1219 */
1220MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1221
1222/* reg_sldr_lag_id
1223 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1224 * Access: Index
1225 */
1226MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1227
1228static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1229{
1230 MLXSW_REG_ZERO(sldr, payload);
1231 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1232 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1233}
1234
1235static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1236{
1237 MLXSW_REG_ZERO(sldr, payload);
1238 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1239 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1240}
1241
1242/* reg_sldr_num_ports
1243 * The number of member ports of the LAG.
1244 * Reserved for Create / Destroy operations
1245 * For Add / Remove operations - indicates the number of ports in the list.
1246 * Access: RW
1247 */
1248MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1249
1250/* reg_sldr_system_port
1251 * System port.
1252 * Access: RW
1253 */
1254MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1255
1256static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1257 u8 local_port)
1258{
1259 MLXSW_REG_ZERO(sldr, payload);
1260 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1261 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1262 mlxsw_reg_sldr_num_ports_set(payload, 1);
1263 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1264}
1265
1266static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1267 u8 local_port)
1268{
1269 MLXSW_REG_ZERO(sldr, payload);
1270 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1271 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1272 mlxsw_reg_sldr_num_ports_set(payload, 1);
1273 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1274}
1275
1276/* SLCR - Switch LAG Configuration 2 Register
1277 * -------------------------------------------
1278 * The Switch LAG Configuration register is used for configuring the
1279 * LAG properties of the switch.
1280 */
1281#define MLXSW_REG_SLCR_ID 0x2015
1282#define MLXSW_REG_SLCR_LEN 0x10
1283
1284static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1285 .id = MLXSW_REG_SLCR_ID,
1286 .len = MLXSW_REG_SLCR_LEN,
1287};
1288
1289enum mlxsw_reg_slcr_pp {
1290 /* Global Configuration (for all ports) */
1291 MLXSW_REG_SLCR_PP_GLOBAL,
1292 /* Per port configuration, based on local_port field */
1293 MLXSW_REG_SLCR_PP_PER_PORT,
1294};
1295
1296/* reg_slcr_pp
1297 * Per Port Configuration
1298 * Note: Reading at Global mode results in reading port 1 configuration.
1299 * Access: Index
1300 */
1301MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1302
1303/* reg_slcr_local_port
1304 * Local port number
1305 * Supported from CPU port
1306 * Not supported from router port
1307 * Reserved when pp = Global Configuration
1308 * Access: Index
1309 */
1310MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1311
1312enum mlxsw_reg_slcr_type {
1313 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1314 MLXSW_REG_SLCR_TYPE_XOR,
1315 MLXSW_REG_SLCR_TYPE_RANDOM,
1316};
1317
1318/* reg_slcr_type
1319 * Hash type
1320 * Access: RW
1321 */
1322MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1323
1324/* Ingress port */
1325#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1326/* SMAC - for IPv4 and IPv6 packets */
1327#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1328/* SMAC - for non-IP packets */
1329#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1330#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1331 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1332 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1333/* DMAC - for IPv4 and IPv6 packets */
1334#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1335/* DMAC - for non-IP packets */
1336#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1337#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1338 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1339 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1340/* Ethertype - for IPv4 and IPv6 packets */
1341#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1342/* Ethertype - for non-IP packets */
1343#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1344#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1345 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1346 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1347/* VLAN ID - for IPv4 and IPv6 packets */
1348#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1349/* VLAN ID - for non-IP packets */
1350#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1351#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1352 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1353 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1354/* Source IP address (can be IPv4 or IPv6) */
1355#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1356/* Destination IP address (can be IPv4 or IPv6) */
1357#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1358/* TCP/UDP source port */
1359#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1360/* TCP/UDP destination port*/
1361#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1362/* IPv4 Protocol/IPv6 Next Header */
1363#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1364/* IPv6 Flow label */
1365#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1366/* SID - FCoE source ID */
1367#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1368/* DID - FCoE destination ID */
1369#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1370/* OXID - FCoE originator exchange ID */
1371#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1372/* Destination QP number - for RoCE packets */
1373#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1374
1375/* reg_slcr_lag_hash
1376 * LAG hashing configuration. This is a bitmask, in which each set
1377 * bit includes the corresponding item in the LAG hash calculation.
1378 * The default lag_hash contains SMAC, DMAC, VLANID and
1379 * Ethertype (for all packet types).
1380 * Access: RW
1381 */
1382MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1383
1384static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1385{
1386 MLXSW_REG_ZERO(slcr, payload);
1387 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1388 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1389 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1390}
1391
1392/* SLCOR - Switch LAG Collector Register
1393 * -------------------------------------
1394 * The Switch LAG Collector register controls the Local Port membership
1395 * in a LAG and enablement of the collector.
1396 */
1397#define MLXSW_REG_SLCOR_ID 0x2016
1398#define MLXSW_REG_SLCOR_LEN 0x10
1399
1400static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1401 .id = MLXSW_REG_SLCOR_ID,
1402 .len = MLXSW_REG_SLCOR_LEN,
1403};
1404
1405enum mlxsw_reg_slcor_col {
1406 /* Port is added with collector disabled */
1407 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1408 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1409 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1410 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1411};
1412
1413/* reg_slcor_col
1414 * Collector configuration
1415 * Access: RW
1416 */
1417MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1418
1419/* reg_slcor_local_port
1420 * Local port number
1421 * Not supported for CPU port
1422 * Access: Index
1423 */
1424MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1425
1426/* reg_slcor_lag_id
1427 * LAG Identifier. Index into the LAG descriptor table.
1428 * Access: Index
1429 */
1430MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1431
1432/* reg_slcor_port_index
1433 * Port index in the LAG list. Only valid on Add Port to LAG col.
1434 * Valid range is from 0 to cap_max_lag_members-1
1435 * Access: RW
1436 */
1437MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1438
1439static inline void mlxsw_reg_slcor_pack(char *payload,
1440 u8 local_port, u16 lag_id,
1441 enum mlxsw_reg_slcor_col col)
1442{
1443 MLXSW_REG_ZERO(slcor, payload);
1444 mlxsw_reg_slcor_col_set(payload, col);
1445 mlxsw_reg_slcor_local_port_set(payload, local_port);
1446 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1447}
1448
1449static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1450 u8 local_port, u16 lag_id,
1451 u8 port_index)
1452{
1453 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1454 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1455 mlxsw_reg_slcor_port_index_set(payload, port_index);
1456}
1457
1458static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1459 u8 local_port, u16 lag_id)
1460{
1461 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1462 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1463}
1464
1465static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1466 u8 local_port, u16 lag_id)
1467{
1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1470}
1471
1472static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1473 u8 local_port, u16 lag_id)
1474{
1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1477}
1478
4ec14b76
IS		 1479/* SPMLR - Switch Port MAC Learning Register
1480 * -----------------------------------------
1481 * Controls the Switch MAC learning policy per port.
1482 */
1483#define MLXSW_REG_SPMLR_ID 0x2018
1484#define MLXSW_REG_SPMLR_LEN 0x8
1485
1486static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1487 .id = MLXSW_REG_SPMLR_ID,
1488 .len = MLXSW_REG_SPMLR_LEN,
1489};
1490
1491/* reg_spmlr_local_port
1492 * Local port number.
1493 * Access: Index
1494 */
1495MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1496
1497/* reg_spmlr_sub_port
1498 * Virtual port within the physical port.
1499 * Should be set to 0 when virtual ports are not enabled on the port.
1500 * Access: Index
1501 */
1502MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1503
1504enum mlxsw_reg_spmlr_learn_mode {
1505 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1506 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1507 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1508};
1509
1510/* reg_spmlr_learn_mode
1511 * Learning mode on the port.
1512 * 0 - Learning disabled.
1513 * 2 - Learning enabled.
1514 * 3 - Security mode.
1515 *
1516 * In security mode the switch does not learn MACs on the port, but uses the
1517 * SMAC to see if it exists on another ingress port. If so, the packet is
1518 * classified as a bad packet and is discarded unless the software registers
1519 * to receive port security error packets usign HPKT.
1520 */
1521MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1522
1523static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1524 enum mlxsw_reg_spmlr_learn_mode mode)
1525{
1526 MLXSW_REG_ZERO(spmlr, payload);
1527 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1528 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1529 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1530}
1531
64790239
IS		 1532/* SVFA - Switch VID to FID Allocation Register
1533 * --------------------------------------------
1534 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1535 * virtualized ports.
1536 */
1537#define MLXSW_REG_SVFA_ID 0x201C
1538#define MLXSW_REG_SVFA_LEN 0x10
1539
1540static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1541 .id = MLXSW_REG_SVFA_ID,
1542 .len = MLXSW_REG_SVFA_LEN,
1543};
1544
1545/* reg_svfa_swid
1546 * Switch partition ID.
1547 * Access: Index
1548 */
1549MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1550
1551/* reg_svfa_local_port
1552 * Local port number.
1553 * Access: Index
1554 *
1555 * Note: Reserved for 802.1Q FIDs.
1556 */
1557MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1558
1559enum mlxsw_reg_svfa_mt {
1560 MLXSW_REG_SVFA_MT_VID_TO_FID,
1561 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1562};
1563
1564/* reg_svfa_mapping_table
1565 * Mapping table:
1566 * 0 - VID to FID
1567 * 1 - {Port, VID} to FID
1568 * Access: Index
1569 *
1570 * Note: Reserved for SwitchX-2.
1571 */
1572MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1573
1574/* reg_svfa_v
1575 * Valid.
1576 * Valid if set.
1577 * Access: RW
1578 *
1579 * Note: Reserved for SwitchX-2.
1580 */
1581MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1582
1583/* reg_svfa_fid
1584 * Filtering ID.
1585 * Access: RW
1586 */
1587MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1588
1589/* reg_svfa_vid
1590 * VLAN ID.
1591 * Access: Index
1592 */
1593MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1594
1595/* reg_svfa_counter_set_type
1596 * Counter set type for flow counters.
1597 * Access: RW
1598 *
1599 * Note: Reserved for SwitchX-2.
1600 */
1601MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1602
1603/* reg_svfa_counter_index
1604 * Counter index for flow counters.
1605 * Access: RW
1606 *
1607 * Note: Reserved for SwitchX-2.
1608 */
1609MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1610
1611static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1612 enum mlxsw_reg_svfa_mt mt, bool valid,
1613 u16 fid, u16 vid)
1614{
1615 MLXSW_REG_ZERO(svfa, payload);
1616 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1617 mlxsw_reg_svfa_swid_set(payload, 0);
1618 mlxsw_reg_svfa_local_port_set(payload, local_port);
1619 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1620 mlxsw_reg_svfa_v_set(payload, valid);
1621 mlxsw_reg_svfa_fid_set(payload, fid);
1622 mlxsw_reg_svfa_vid_set(payload, vid);
1623}
1624
1f65da74
IS		 1625/* SVPE - Switch Virtual-Port Enabling Register
1626 * --------------------------------------------
1627 * Enables port virtualization.
1628 */
1629#define MLXSW_REG_SVPE_ID 0x201E
1630#define MLXSW_REG_SVPE_LEN 0x4
1631
1632static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1633 .id = MLXSW_REG_SVPE_ID,
1634 .len = MLXSW_REG_SVPE_LEN,
1635};
1636
1637/* reg_svpe_local_port
1638 * Local port number
1639 * Access: Index
1640 *
1641 * Note: CPU port is not supported (uses VLAN mode only).
1642 */
1643MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1644
1645/* reg_svpe_vp_en
1646 * Virtual port enable.
1647 * 0 - Disable, VLAN mode (VID to FID).
1648 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1649 * Access: RW
1650 */
1651MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1652
1653static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1654 bool enable)
1655{
1656 MLXSW_REG_ZERO(svpe, payload);
1657 mlxsw_reg_svpe_local_port_set(payload, local_port);
1658 mlxsw_reg_svpe_vp_en_set(payload, enable);
1659}
1660
f1fb693a
IS		 1661/* SFMR - Switch FID Management Register
1662 * -------------------------------------
1663 * Creates and configures FIDs.
1664 */
1665#define MLXSW_REG_SFMR_ID 0x201F
1666#define MLXSW_REG_SFMR_LEN 0x18
1667
1668static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1669 .id = MLXSW_REG_SFMR_ID,
1670 .len = MLXSW_REG_SFMR_LEN,
1671};
1672
1673enum mlxsw_reg_sfmr_op {
1674 MLXSW_REG_SFMR_OP_CREATE_FID,
1675 MLXSW_REG_SFMR_OP_DESTROY_FID,
1676};
1677
1678/* reg_sfmr_op
1679 * Operation.
1680 * 0 - Create or edit FID.
1681 * 1 - Destroy FID.
1682 * Access: WO
1683 */
1684MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1685
1686/* reg_sfmr_fid
1687 * Filtering ID.
1688 * Access: Index
1689 */
1690MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1691
1692/* reg_sfmr_fid_offset
1693 * FID offset.
1694 * Used to point into the flooding table selected by SFGC register if
1695 * the table is of type FID-Offset. Otherwise, this field is reserved.
1696 * Access: RW
1697 */
1698MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1699
1700/* reg_sfmr_vtfp
1701 * Valid Tunnel Flood Pointer.
1702 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1703 * Access: RW
1704 *
1705 * Note: Reserved for 802.1Q FIDs.
1706 */
1707MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1708
1709/* reg_sfmr_nve_tunnel_flood_ptr
1710 * Underlay Flooding and BC Pointer.
1711 * Used as a pointer to the first entry of the group based link lists of
1712 * flooding or BC entries (for NVE tunnels).
1713 * Access: RW
1714 */
1715MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1716
1717/* reg_sfmr_vv
1718 * VNI Valid.
1719 * If not set, then vni is reserved.
1720 * Access: RW
1721 *
1722 * Note: Reserved for 802.1Q FIDs.
1723 */
1724MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1725
1726/* reg_sfmr_vni
1727 * Virtual Network Identifier.
1728 * Access: RW
1729 *
1730 * Note: A given VNI can only be assigned to one FID.
1731 */
1732MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1733
1734static inline void mlxsw_reg_sfmr_pack(char *payload,
1735 enum mlxsw_reg_sfmr_op op, u16 fid,
1736 u16 fid_offset)
1737{
1738 MLXSW_REG_ZERO(sfmr, payload);
1739 mlxsw_reg_sfmr_op_set(payload, op);
1740 mlxsw_reg_sfmr_fid_set(payload, fid);
1741 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1742 mlxsw_reg_sfmr_vtfp_set(payload, false);
1743 mlxsw_reg_sfmr_vv_set(payload, false);
1744}
1745
a4feea74
IS		 1746/* SPVMLR - Switch Port VLAN MAC Learning Register
1747 * -----------------------------------------------
1748 * Controls the switch MAC learning policy per {Port, VID}.
1749 */
1750#define MLXSW_REG_SPVMLR_ID 0x2020
1751#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1752#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1753#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1754#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1755 MLXSW_REG_SPVMLR_REC_LEN * \
1756 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1757
1758static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1759 .id = MLXSW_REG_SPVMLR_ID,
1760 .len = MLXSW_REG_SPVMLR_LEN,
1761};
1762
1763/* reg_spvmlr_local_port
1764 * Local ingress port.
1765 * Access: Index
1766 *
1767 * Note: CPU port is not supported.
1768 */
1769MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1770
1771/* reg_spvmlr_num_rec
1772 * Number of records to update.
1773 * Access: OP
1774 */
1775MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1776
1777/* reg_spvmlr_rec_learn_enable
1778 * 0 - Disable learning for {Port, VID}.
1779 * 1 - Enable learning for {Port, VID}.
1780 * Access: RW
1781 */
1782MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1783 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1784
1785/* reg_spvmlr_rec_vid
1786 * VLAN ID to be added/removed from port or for querying.
1787 * Access: Index
1788 */
1789MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1790 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1791
1792static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1793 u16 vid_begin, u16 vid_end,
1794 bool learn_enable)
1795{
1796 int num_rec = vid_end - vid_begin + 1;
1797 int i;
1798
1799 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1800
1801 MLXSW_REG_ZERO(spvmlr, payload);
1802 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1803 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1804
1805 for (i = 0; i < num_rec; i++) {
1806 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1807 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1808 }
1809}
1810
2c63a555
IS		 1811/* QTCT - QoS Switch Traffic Class Table
1812 * -------------------------------------
1813 * Configures the mapping between the packet switch priority and the
1814 * traffic class on the transmit port.
1815 */
1816#define MLXSW_REG_QTCT_ID 0x400A
1817#define MLXSW_REG_QTCT_LEN 0x08
1818
1819static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1820 .id = MLXSW_REG_QTCT_ID,
1821 .len = MLXSW_REG_QTCT_LEN,
1822};
1823
1824/* reg_qtct_local_port
1825 * Local port number.
1826 * Access: Index
1827 *
1828 * Note: CPU port is not supported.
1829 */
1830MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1831
1832/* reg_qtct_sub_port
1833 * Virtual port within the physical port.
1834 * Should be set to 0 when virtual ports are not enabled on the port.
1835 * Access: Index
1836 */
1837MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1838
1839/* reg_qtct_switch_prio
1840 * Switch priority.
1841 * Access: Index
1842 */
1843MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1844
1845/* reg_qtct_tclass
1846 * Traffic class.
1847 * Default values:
1848 * switch_prio 0 : tclass 1
1849 * switch_prio 1 : tclass 0
1850 * switch_prio i : tclass i, for i > 1
1851 * Access: RW
1852 */
1853MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1854
1855static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1856 u8 switch_prio, u8 tclass)
1857{
1858 MLXSW_REG_ZERO(qtct, payload);
1859 mlxsw_reg_qtct_local_port_set(payload, local_port);
1860 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1861 mlxsw_reg_qtct_tclass_set(payload, tclass);
1862}
1863
b9b7cee4
IS		 1864/* QEEC - QoS ETS Element Configuration Register
1865 * ---------------------------------------------
1866 * Configures the ETS elements.
1867 */
1868#define MLXSW_REG_QEEC_ID 0x400D
1869#define MLXSW_REG_QEEC_LEN 0x1C
1870
1871static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1872 .id = MLXSW_REG_QEEC_ID,
1873 .len = MLXSW_REG_QEEC_LEN,
1874};
1875
1876/* reg_qeec_local_port
1877 * Local port number.
1878 * Access: Index
1879 *
1880 * Note: CPU port is supported.
1881 */
1882MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1883
1884enum mlxsw_reg_qeec_hr {
1885 MLXSW_REG_QEEC_HIERARCY_PORT,
1886 MLXSW_REG_QEEC_HIERARCY_GROUP,
1887 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1888 MLXSW_REG_QEEC_HIERARCY_TC,
1889};
1890
1891/* reg_qeec_element_hierarchy
1892 * 0 - Port
1893 * 1 - Group
1894 * 2 - Subgroup
1895 * 3 - Traffic Class
1896 * Access: Index
1897 */
1898MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1899
1900/* reg_qeec_element_index
1901 * The index of the element in the hierarchy.
1902 * Access: Index
1903 */
1904MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1905
1906/* reg_qeec_next_element_index
1907 * The index of the next (lower) element in the hierarchy.
1908 * Access: RW
1909 *
1910 * Note: Reserved for element_hierarchy 0.
1911 */
1912MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1913
1914enum {
1915 MLXSW_REG_QEEC_BYTES_MODE,
1916 MLXSW_REG_QEEC_PACKETS_MODE,
1917};
1918
1919/* reg_qeec_pb
1920 * Packets or bytes mode.
1921 * 0 - Bytes mode
1922 * 1 - Packets mode
1923 * Access: RW
1924 *
1925 * Note: Used for max shaper configuration. For Spectrum, packets mode
1926 * is supported only for traffic classes of CPU port.
1927 */
1928MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1929
1930/* reg_qeec_mase
1931 * Max shaper configuration enable. Enables configuration of the max
1932 * shaper on this ETS element.
1933 * 0 - Disable
1934 * 1 - Enable
1935 * Access: RW
1936 */
1937MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1938
1939/* A large max rate will disable the max shaper. */
1940#define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
1941
1942/* reg_qeec_max_shaper_rate
1943 * Max shaper information rate.
1944 * For CPU port, can only be configured for port hierarchy.
1945 * When in bytes mode, value is specified in units of 1000bps.
1946 * Access: RW
1947 */
1948MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1949
1950/* reg_qeec_de
1951 * DWRR configuration enable. Enables configuration of the dwrr and
1952 * dwrr_weight.
1953 * 0 - Disable
1954 * 1 - Enable
1955 * Access: RW
1956 */
1957MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1958
1959/* reg_qeec_dwrr
1960 * Transmission selection algorithm to use on the link going down from
1961 * the ETS element.
1962 * 0 - Strict priority
1963 * 1 - DWRR
1964 * Access: RW
1965 */
1966MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1967
1968/* reg_qeec_dwrr_weight
1969 * DWRR weight on the link going down from the ETS element. The
1970 * percentage of bandwidth guaranteed to an ETS element within
1971 * its hierarchy. The sum of all weights across all ETS elements
1972 * within one hierarchy should be equal to 100. Reserved when
1973 * transmission selection algorithm is strict priority.
1974 * Access: RW
1975 */
1976MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1977
1978static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1979 enum mlxsw_reg_qeec_hr hr, u8 index,
1980 u8 next_index)
1981{
1982 MLXSW_REG_ZERO(qeec, payload);
1983 mlxsw_reg_qeec_local_port_set(payload, local_port);
1984 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1985 mlxsw_reg_qeec_element_index_set(payload, index);
1986 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1987}
1988
4ec14b76
IS		 1989/* PMLP - Ports Module to Local Port Register
1990 * ------------------------------------------
1991 * Configures the assignment of modules to local ports.
1992 */
1993#define MLXSW_REG_PMLP_ID 0x5002
1994#define MLXSW_REG_PMLP_LEN 0x40
1995
1996static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1997 .id = MLXSW_REG_PMLP_ID,
1998 .len = MLXSW_REG_PMLP_LEN,
1999};
2000
2001/* reg_pmlp_rxtx
2002 * 0 - Tx value is used for both Tx and Rx.
2003 * 1 - Rx value is taken from a separte field.
2004 * Access: RW
2005 */
2006MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2007
2008/* reg_pmlp_local_port
2009 * Local port number.
2010 * Access: Index
2011 */
2012MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2013
2014/* reg_pmlp_width
2015 * 0 - Unmap local port.
2016 * 1 - Lane 0 is used.
2017 * 2 - Lanes 0 and 1 are used.
2018 * 4 - Lanes 0, 1, 2 and 3 are used.
2019 * Access: RW
2020 */
2021MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2022
2023/* reg_pmlp_module
2024 * Module number.
2025 * Access: RW
2026 */
bbeeda27 2027MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4ec14b76
IS		 2028
2029/* reg_pmlp_tx_lane
2030 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2031 * Access: RW
2032 */
bbeeda27 2033MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
4ec14b76
IS		 2034
2035/* reg_pmlp_rx_lane
2036 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2037 * equal to Tx lane.
2038 * Access: RW
2039 */
bbeeda27 2040MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
4ec14b76
IS		 2041
2042static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2043{
2044 MLXSW_REG_ZERO(pmlp, payload);
2045 mlxsw_reg_pmlp_local_port_set(payload, local_port);
2046}
2047
2048/* PMTU - Port MTU Register
2049 * ------------------------
2050 * Configures and reports the port MTU.
2051 */
2052#define MLXSW_REG_PMTU_ID 0x5003
2053#define MLXSW_REG_PMTU_LEN 0x10
2054
2055static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2056 .id = MLXSW_REG_PMTU_ID,
2057 .len = MLXSW_REG_PMTU_LEN,
2058};
2059
2060/* reg_pmtu_local_port
2061 * Local port number.
2062 * Access: Index
2063 */
2064MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2065
2066/* reg_pmtu_max_mtu
2067 * Maximum MTU.
2068 * When port type (e.g. Ethernet) is configured, the relevant MTU is
2069 * reported, otherwise the minimum between the max_mtu of the different
2070 * types is reported.
2071 * Access: RO
2072 */
2073MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2074
2075/* reg_pmtu_admin_mtu
2076 * MTU value to set port to. Must be smaller or equal to max_mtu.
2077 * Note: If port type is Infiniband, then port must be disabled, when its
2078 * MTU is set.
2079 * Access: RW
2080 */
2081MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2082
2083/* reg_pmtu_oper_mtu
2084 * The actual MTU configured on the port. Packets exceeding this size
2085 * will be dropped.
2086 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2087 * oper_mtu might be smaller than admin_mtu.
2088 * Access: RO
2089 */
2090MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2091
2092static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2093 u16 new_mtu)
2094{
2095 MLXSW_REG_ZERO(pmtu, payload);
2096 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2097 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2098 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2099 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2100}
2101
2102/* PTYS - Port Type and Speed Register
2103 * -----------------------------------
2104 * Configures and reports the port speed type.
2105 *
2106 * Note: When set while the link is up, the changes will not take effect
2107 * until the port transitions from down to up state.
2108 */
2109#define MLXSW_REG_PTYS_ID 0x5004
2110#define MLXSW_REG_PTYS_LEN 0x40
2111
2112static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2113 .id = MLXSW_REG_PTYS_ID,
2114 .len = MLXSW_REG_PTYS_LEN,
2115};
2116
2117/* reg_ptys_local_port
2118 * Local port number.
2119 * Access: Index
2120 */
2121MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2122
2123#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2124
2125/* reg_ptys_proto_mask
2126 * Protocol mask. Indicates which protocol is used.
2127 * 0 - Infiniband.
2128 * 1 - Fibre Channel.
2129 * 2 - Ethernet.
2130 * Access: Index
2131 */
2132MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2133
2134#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2135#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2136#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2137#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2138#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2139#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2140#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2141#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2142#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2143#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2144#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2145#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2146#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2147#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2148#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2149#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2150#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2151#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2152#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2153#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2154#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2155#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2156#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2157#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2158#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2159#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2160#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2161
2162/* reg_ptys_eth_proto_cap
2163 * Ethernet port supported speeds and protocols.
2164 * Access: RO
2165 */
2166MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2167
2168/* reg_ptys_eth_proto_admin
2169 * Speed and protocol to set port to.
2170 * Access: RW
2171 */
2172MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2173
2174/* reg_ptys_eth_proto_oper
2175 * The current speed and protocol configured for the port.
2176 * Access: RO
2177 */
2178MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2179
2180static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2181 u32 proto_admin)
2182{
2183 MLXSW_REG_ZERO(ptys, payload);
2184 mlxsw_reg_ptys_local_port_set(payload, local_port);
2185 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2186 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2187}
2188
2189static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2190 u32 *p_eth_proto_adm,
2191 u32 *p_eth_proto_oper)
2192{
2193 if (p_eth_proto_cap)
2194 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2195 if (p_eth_proto_adm)
2196 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2197 if (p_eth_proto_oper)
2198 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2199}
2200
2201/* PPAD - Port Physical Address Register
2202 * -------------------------------------
2203 * The PPAD register configures the per port physical MAC address.
2204 */
2205#define MLXSW_REG_PPAD_ID 0x5005
2206#define MLXSW_REG_PPAD_LEN 0x10
2207
2208static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2209 .id = MLXSW_REG_PPAD_ID,
2210 .len = MLXSW_REG_PPAD_LEN,
2211};
2212
2213/* reg_ppad_single_base_mac
2214 * 0: base_mac, local port should be 0 and mac[7:0] is
2215 * reserved. HW will set incremental
2216 * 1: single_mac - mac of the local_port
2217 * Access: RW
2218 */
2219MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2220
2221/* reg_ppad_local_port
2222 * port number, if single_base_mac = 0 then local_port is reserved
2223 * Access: RW
2224 */
2225MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2226
2227/* reg_ppad_mac
2228 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2229 * If single_base_mac = 1 - the per port MAC address
2230 * Access: RW
2231 */
2232MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2233
2234static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2235 u8 local_port)
2236{
2237 MLXSW_REG_ZERO(ppad, payload);
2238 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2239 mlxsw_reg_ppad_local_port_set(payload, local_port);
2240}
2241
2242/* PAOS - Ports Administrative and Operational Status Register
2243 * -----------------------------------------------------------
2244 * Configures and retrieves per port administrative and operational status.
2245 */
2246#define MLXSW_REG_PAOS_ID 0x5006
2247#define MLXSW_REG_PAOS_LEN 0x10
2248
2249static const struct mlxsw_reg_info mlxsw_reg_paos = {
2250 .id = MLXSW_REG_PAOS_ID,
2251 .len = MLXSW_REG_PAOS_LEN,
2252};
2253
2254/* reg_paos_swid
2255 * Switch partition ID with which to associate the port.
2256 * Note: while external ports uses unique local port numbers (and thus swid is
2257 * redundant), router ports use the same local port number where swid is the
2258 * only indication for the relevant port.
2259 * Access: Index
2260 */
2261MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2262
2263/* reg_paos_local_port
2264 * Local port number.
2265 * Access: Index
2266 */
2267MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2268
2269/* reg_paos_admin_status
2270 * Port administrative state (the desired state of the port):
2271 * 1 - Up.
2272 * 2 - Down.
2273 * 3 - Up once. This means that in case of link failure, the port won't go
2274 * into polling mode, but will wait to be re-enabled by software.
2275 * 4 - Disabled by system. Can only be set by hardware.
2276 * Access: RW
2277 */
2278MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2279
2280/* reg_paos_oper_status
2281 * Port operational state (the current state):
2282 * 1 - Up.
2283 * 2 - Down.
2284 * 3 - Down by port failure. This means that the device will not let the
2285 * port up again until explicitly specified by software.
2286 * Access: RO
2287 */
2288MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2289
2290/* reg_paos_ase
2291 * Admin state update enabled.
2292 * Access: WO
2293 */
2294MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2295
2296/* reg_paos_ee
2297 * Event update enable. If this bit is set, event generation will be
2298 * updated based on the e field.
2299 * Access: WO
2300 */
2301MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2302
2303/* reg_paos_e
2304 * Event generation on operational state change:
2305 * 0 - Do not generate event.
2306 * 1 - Generate Event.
2307 * 2 - Generate Single Event.
2308 * Access: RW
2309 */
2310MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2311
2312static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2313 enum mlxsw_port_admin_status status)
2314{
2315 MLXSW_REG_ZERO(paos, payload);
2316 mlxsw_reg_paos_swid_set(payload, 0);
2317 mlxsw_reg_paos_local_port_set(payload, local_port);
2318 mlxsw_reg_paos_admin_status_set(payload, status);
2319 mlxsw_reg_paos_oper_status_set(payload, 0);
2320 mlxsw_reg_paos_ase_set(payload, 1);
2321 mlxsw_reg_paos_ee_set(payload, 1);
2322 mlxsw_reg_paos_e_set(payload, 1);
2323}
2324
6f253d83
IS		 2325/* PFCC - Ports Flow Control Configuration Register
2326 * ------------------------------------------------
2327 * Configures and retrieves the per port flow control configuration.
2328 */
2329#define MLXSW_REG_PFCC_ID 0x5007
2330#define MLXSW_REG_PFCC_LEN 0x20
2331
2332static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2333 .id = MLXSW_REG_PFCC_ID,
2334 .len = MLXSW_REG_PFCC_LEN,
2335};
2336
2337/* reg_pfcc_local_port
2338 * Local port number.
2339 * Access: Index
2340 */
2341MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2342
2343/* reg_pfcc_pnat
2344 * Port number access type. Determines the way local_port is interpreted:
2345 * 0 - Local port number.
2346 * 1 - IB / label port number.
2347 * Access: Index
2348 */
2349MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2350
2351/* reg_pfcc_shl_cap
2352 * Send to higher layers capabilities:
2353 * 0 - No capability of sending Pause and PFC frames to higher layers.
2354 * 1 - Device has capability of sending Pause and PFC frames to higher
2355 * layers.
2356 * Access: RO
2357 */
2358MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2359
2360/* reg_pfcc_shl_opr
2361 * Send to higher layers operation:
2362 * 0 - Pause and PFC frames are handled by the port (default).
2363 * 1 - Pause and PFC frames are handled by the port and also sent to
2364 * higher layers. Only valid if shl_cap = 1.
2365 * Access: RW
2366 */
2367MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2368
2369/* reg_pfcc_ppan
2370 * Pause policy auto negotiation.
2371 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
2372 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
2373 * based on the auto-negotiation resolution.
2374 * Access: RW
2375 *
2376 * Note: The auto-negotiation advertisement is set according to pptx and
2377 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
2378 */
2379MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2380
2381/* reg_pfcc_prio_mask_tx
2382 * Bit per priority indicating if Tx flow control policy should be
2383 * updated based on bit pfctx.
2384 * Access: WO
2385 */
2386MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2387
2388/* reg_pfcc_prio_mask_rx
2389 * Bit per priority indicating if Rx flow control policy should be
2390 * updated based on bit pfcrx.
2391 * Access: WO
2392 */
2393MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2394
2395/* reg_pfcc_pptx
2396 * Admin Pause policy on Tx.
2397 * 0 - Never generate Pause frames (default).
2398 * 1 - Generate Pause frames according to Rx buffer threshold.
2399 * Access: RW
2400 */
2401MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2402
2403/* reg_pfcc_aptx
2404 * Active (operational) Pause policy on Tx.
2405 * 0 - Never generate Pause frames.
2406 * 1 - Generate Pause frames according to Rx buffer threshold.
2407 * Access: RO
2408 */
2409MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2410
2411/* reg_pfcc_pfctx
2412 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
2413 * 0 - Never generate priority Pause frames on the specified priority
2414 * (default).
2415 * 1 - Generate priority Pause frames according to Rx buffer threshold on
2416 * the specified priority.
2417 * Access: RW
2418 *
2419 * Note: pfctx and pptx must be mutually exclusive.
2420 */
2421MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2422
2423/* reg_pfcc_pprx
2424 * Admin Pause policy on Rx.
2425 * 0 - Ignore received Pause frames (default).
2426 * 1 - Respect received Pause frames.
2427 * Access: RW
2428 */
2429MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2430
2431/* reg_pfcc_aprx
2432 * Active (operational) Pause policy on Rx.
2433 * 0 - Ignore received Pause frames.
2434 * 1 - Respect received Pause frames.
2435 * Access: RO
2436 */
2437MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2438
2439/* reg_pfcc_pfcrx
2440 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
2441 * 0 - Ignore incoming priority Pause frames on the specified priority
2442 * (default).
2443 * 1 - Respect incoming priority Pause frames on the specified priority.
2444 * Access: RW
2445 */
2446MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2447
d81a6bdb
IS		 2448#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2449
2450static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2451{
2452 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2453 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2454 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2455 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2456}
2457
6f253d83
IS		 2458static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2459{
2460 MLXSW_REG_ZERO(pfcc, payload);
2461 mlxsw_reg_pfcc_local_port_set(payload, local_port);
2462}
2463
4ec14b76
IS		 2464/* PPCNT - Ports Performance Counters Register
2465 * -------------------------------------------
2466 * The PPCNT register retrieves per port performance counters.
2467 */
2468#define MLXSW_REG_PPCNT_ID 0x5008
2469#define MLXSW_REG_PPCNT_LEN 0x100
2470
2471static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2472 .id = MLXSW_REG_PPCNT_ID,
2473 .len = MLXSW_REG_PPCNT_LEN,
2474};
2475
2476/* reg_ppcnt_swid
2477 * For HCA: must be always 0.
2478 * Switch partition ID to associate port with.
2479 * Switch partitions are numbered from 0 to 7 inclusively.
2480 * Switch partition 254 indicates stacking ports.
2481 * Switch partition 255 indicates all switch partitions.
2482 * Only valid on Set() operation with local_port=255.
2483 * Access: Index
2484 */
2485MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2486
2487/* reg_ppcnt_local_port
2488 * Local port number.
2489 * 255 indicates all ports on the device, and is only allowed
2490 * for Set() operation.
2491 * Access: Index
2492 */
2493MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2494
2495/* reg_ppcnt_pnat
2496 * Port number access type:
2497 * 0 - Local port number
2498 * 1 - IB port number
2499 * Access: Index
2500 */
2501MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2502
34dba0a5
IS		 2503enum mlxsw_reg_ppcnt_grp {
2504 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2505 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
df4750e8 2506 MLXSW_REG_PPCNT_TC_CNT = 0x11,
34dba0a5
IS		 2507};
2508
4ec14b76
IS		 2509/* reg_ppcnt_grp
2510 * Performance counter group.
2511 * Group 63 indicates all groups. Only valid on Set() operation with
2512 * clr bit set.
2513 * 0x0: IEEE 802.3 Counters
2514 * 0x1: RFC 2863 Counters
2515 * 0x2: RFC 2819 Counters
2516 * 0x3: RFC 3635 Counters
2517 * 0x5: Ethernet Extended Counters
2518 * 0x8: Link Level Retransmission Counters
2519 * 0x10: Per Priority Counters
2520 * 0x11: Per Traffic Class Counters
2521 * 0x12: Physical Layer Counters
2522 * Access: Index
2523 */
2524MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2525
2526/* reg_ppcnt_clr
2527 * Clear counters. Setting the clr bit will reset the counter value
2528 * for all counters in the counter group. This bit can be set
2529 * for both Set() and Get() operation.
2530 * Access: OP
2531 */
2532MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2533
2534/* reg_ppcnt_prio_tc
2535 * Priority for counter set that support per priority, valid values: 0-7.
2536 * Traffic class for counter set that support per traffic class,
2537 * valid values: 0- cap_max_tclass-1 .
2538 * For HCA: cap_max_tclass is always 8.
2539 * Otherwise must be 0.
2540 * Access: Index
2541 */
2542MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2543
34dba0a5
IS		 2544/* Ethernet IEEE 802.3 Counter Group */
2545
4ec14b76
IS		 2546/* reg_ppcnt_a_frames_transmitted_ok
2547 * Access: RO
2548 */
2549MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2550 0x08 + 0x00, 0, 64);
2551
2552/* reg_ppcnt_a_frames_received_ok
2553 * Access: RO
2554 */
2555MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2556 0x08 + 0x08, 0, 64);
2557
2558/* reg_ppcnt_a_frame_check_sequence_errors
2559 * Access: RO
2560 */
2561MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2562 0x08 + 0x10, 0, 64);
2563
2564/* reg_ppcnt_a_alignment_errors
2565 * Access: RO
2566 */
2567MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2568 0x08 + 0x18, 0, 64);
2569
2570/* reg_ppcnt_a_octets_transmitted_ok
2571 * Access: RO
2572 */
2573MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2574 0x08 + 0x20, 0, 64);
2575
2576/* reg_ppcnt_a_octets_received_ok
2577 * Access: RO
2578 */
2579MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2580 0x08 + 0x28, 0, 64);
2581
2582/* reg_ppcnt_a_multicast_frames_xmitted_ok
2583 * Access: RO
2584 */
2585MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2586 0x08 + 0x30, 0, 64);
2587
2588/* reg_ppcnt_a_broadcast_frames_xmitted_ok
2589 * Access: RO
2590 */
2591MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2592 0x08 + 0x38, 0, 64);
2593
2594/* reg_ppcnt_a_multicast_frames_received_ok
2595 * Access: RO
2596 */
2597MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2598 0x08 + 0x40, 0, 64);
2599
2600/* reg_ppcnt_a_broadcast_frames_received_ok
2601 * Access: RO
2602 */
2603MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2604 0x08 + 0x48, 0, 64);
2605
2606/* reg_ppcnt_a_in_range_length_errors
2607 * Access: RO
2608 */
2609MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2610 0x08 + 0x50, 0, 64);
2611
2612/* reg_ppcnt_a_out_of_range_length_field
2613 * Access: RO
2614 */
2615MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2616 0x08 + 0x58, 0, 64);
2617
2618/* reg_ppcnt_a_frame_too_long_errors
2619 * Access: RO
2620 */
2621MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2622 0x08 + 0x60, 0, 64);
2623
2624/* reg_ppcnt_a_symbol_error_during_carrier
2625 * Access: RO
2626 */
2627MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2628 0x08 + 0x68, 0, 64);
2629
2630/* reg_ppcnt_a_mac_control_frames_transmitted
2631 * Access: RO
2632 */
2633MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2634 0x08 + 0x70, 0, 64);
2635
2636/* reg_ppcnt_a_mac_control_frames_received
2637 * Access: RO
2638 */
2639MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2640 0x08 + 0x78, 0, 64);
2641
2642/* reg_ppcnt_a_unsupported_opcodes_received
2643 * Access: RO
2644 */
2645MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2646 0x08 + 0x80, 0, 64);
2647
2648/* reg_ppcnt_a_pause_mac_ctrl_frames_received
2649 * Access: RO
2650 */
2651MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2652 0x08 + 0x88, 0, 64);
2653
2654/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2655 * Access: RO
2656 */
2657MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2658 0x08 + 0x90, 0, 64);
2659
34dba0a5
IS		 2660/* Ethernet Per Priority Group Counters */
2661
2662/* reg_ppcnt_rx_octets
2663 * Access: RO
2664 */
2665MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2666
2667/* reg_ppcnt_rx_frames
2668 * Access: RO
2669 */
2670MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2671
2672/* reg_ppcnt_tx_octets
2673 * Access: RO
2674 */
2675MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2676
2677/* reg_ppcnt_tx_frames
2678 * Access: RO
2679 */
2680MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2681
2682/* reg_ppcnt_rx_pause
2683 * Access: RO
2684 */
2685MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2686
2687/* reg_ppcnt_rx_pause_duration
2688 * Access: RO
2689 */
2690MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2691
2692/* reg_ppcnt_tx_pause
2693 * Access: RO
2694 */
2695MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2696
2697/* reg_ppcnt_tx_pause_duration
2698 * Access: RO
2699 */
2700MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2701
2702/* reg_ppcnt_rx_pause_transition
2703 * Access: RO
2704 */
2705MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2706
df4750e8
IS		 2707/* Ethernet Per Traffic Group Counters */
2708
2709/* reg_ppcnt_tc_transmit_queue
2710 * Contains the transmit queue depth in cells of traffic class
2711 * selected by prio_tc and the port selected by local_port.
2712 * The field cannot be cleared.
2713 * Access: RO
2714 */
2715MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64);
2716
2717/* reg_ppcnt_tc_no_buffer_discard_uc
2718 * The number of unicast packets dropped due to lack of shared
2719 * buffer resources.
2720 * Access: RO
2721 */
2722MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64);
2723
34dba0a5
IS		 2724static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2725 enum mlxsw_reg_ppcnt_grp grp,
2726 u8 prio_tc)
4ec14b76
IS		 2727{
2728 MLXSW_REG_ZERO(ppcnt, payload);
2729 mlxsw_reg_ppcnt_swid_set(payload, 0);
2730 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2731 mlxsw_reg_ppcnt_pnat_set(payload, 0);
34dba0a5 2732 mlxsw_reg_ppcnt_grp_set(payload, grp);
4ec14b76 2733 mlxsw_reg_ppcnt_clr_set(payload, 0);
34dba0a5 2734 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
4ec14b76
IS		 2735}
2736
b98ff151
IS		 2737/* PPTB - Port Prio To Buffer Register
2738 * -----------------------------------
2739 * Configures the switch priority to buffer table.
2740 */
2741#define MLXSW_REG_PPTB_ID 0x500B
11719a58 2742#define MLXSW_REG_PPTB_LEN 0x10
b98ff151
IS		 2743
2744static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2745 .id = MLXSW_REG_PPTB_ID,
2746 .len = MLXSW_REG_PPTB_LEN,
2747};
2748
2749enum {
2750 MLXSW_REG_PPTB_MM_UM,
2751 MLXSW_REG_PPTB_MM_UNICAST,
2752 MLXSW_REG_PPTB_MM_MULTICAST,
2753};
2754
2755/* reg_pptb_mm
2756 * Mapping mode.
2757 * 0 - Map both unicast and multicast packets to the same buffer.
2758 * 1 - Map only unicast packets.
2759 * 2 - Map only multicast packets.
2760 * Access: Index
2761 *
2762 * Note: SwitchX-2 only supports the first option.
2763 */
2764MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2765
2766/* reg_pptb_local_port
2767 * Local port number.
2768 * Access: Index
2769 */
2770MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2771
2772/* reg_pptb_um
2773 * Enables the update of the untagged_buf field.
2774 * Access: RW
2775 */
2776MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2777
2778/* reg_pptb_pm
2779 * Enables the update of the prio_to_buff field.
2780 * Bit <i> is a flag for updating the mapping for switch priority <i>.
2781 * Access: RW
2782 */
2783MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2784
2785/* reg_pptb_prio_to_buff
2786 * Mapping of switch priority <i> to one of the allocated receive port
2787 * buffers.
2788 * Access: RW
2789 */
2790MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2791
2792/* reg_pptb_pm_msb
2793 * Enables the update of the prio_to_buff field.
2794 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2795 * Access: RW
2796 */
2797MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2798
2799/* reg_pptb_untagged_buff
2800 * Mapping of untagged frames to one of the allocated receive port buffers.
2801 * Access: RW
2802 *
2803 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2804 * Spectrum, as it maps untagged packets based on the default switch priority.
2805 */
2806MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2807
11719a58
IS		 2808/* reg_pptb_prio_to_buff_msb
2809 * Mapping of switch priority <i+8> to one of the allocated receive port
2810 * buffers.
2811 * Access: RW
2812 */
2813MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
2814
b98ff151
IS		 2815#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2816
2817static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2818{
2819 MLXSW_REG_ZERO(pptb, payload);
2820 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2821 mlxsw_reg_pptb_local_port_set(payload, local_port);
2822 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
11719a58
IS		 2823 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2824}
2825
2826static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
2827 u8 buff)
2828{
2829 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
2830 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
b98ff151
IS		 2831}
2832
e0594369
JP		 2833/* PBMC - Port Buffer Management Control Register
2834 * ----------------------------------------------
2835 * The PBMC register configures and retrieves the port packet buffer
2836 * allocation for different Prios, and the Pause threshold management.
2837 */
2838#define MLXSW_REG_PBMC_ID 0x500C
7ad7cd61 2839#define MLXSW_REG_PBMC_LEN 0x6C
e0594369
JP		 2840
2841static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2842 .id = MLXSW_REG_PBMC_ID,
2843 .len = MLXSW_REG_PBMC_LEN,
2844};
2845
2846/* reg_pbmc_local_port
2847 * Local port number.
2848 * Access: Index
2849 */
2850MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2851
2852/* reg_pbmc_xoff_timer_value
2853 * When device generates a pause frame, it uses this value as the pause
2854 * timer (time for the peer port to pause in quota-512 bit time).
2855 * Access: RW
2856 */
2857MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2858
2859/* reg_pbmc_xoff_refresh
2860 * The time before a new pause frame should be sent to refresh the pause RW
2861 * state. Using the same units as xoff_timer_value above (in quota-512 bit
2862 * time).
2863 * Access: RW
2864 */
2865MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2866
d6b7c13b
IS		 2867#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2868
e0594369
JP		 2869/* reg_pbmc_buf_lossy
2870 * The field indicates if the buffer is lossy.
2871 * 0 - Lossless
2872 * 1 - Lossy
2873 * Access: RW
2874 */
2875MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2876
2877/* reg_pbmc_buf_epsb
2878 * Eligible for Port Shared buffer.
2879 * If epsb is set, packets assigned to buffer are allowed to insert the port
2880 * shared buffer.
2881 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2882 * Access: RW
2883 */
2884MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2885
2886/* reg_pbmc_buf_size
2887 * The part of the packet buffer array is allocated for the specific buffer.
2888 * Units are represented in cells.
2889 * Access: RW
2890 */
2891MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2892
155f9de2
IS		 2893/* reg_pbmc_buf_xoff_threshold
2894 * Once the amount of data in the buffer goes above this value, device
2895 * starts sending PFC frames for all priorities associated with the
2896 * buffer. Units are represented in cells. Reserved in case of lossy
2897 * buffer.
2898 * Access: RW
2899 *
2900 * Note: In Spectrum, reserved for buffer[9].
2901 */
2902MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2903 0x08, 0x04, false);
2904
2905/* reg_pbmc_buf_xon_threshold
2906 * When the amount of data in the buffer goes below this value, device
2907 * stops sending PFC frames for the priorities associated with the
2908 * buffer. Units are represented in cells. Reserved in case of lossy
2909 * buffer.
2910 * Access: RW
2911 *
2912 * Note: In Spectrum, reserved for buffer[9].
2913 */
2914MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2915 0x08, 0x04, false);
2916
e0594369
JP		 2917static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2918 u16 xoff_timer_value, u16 xoff_refresh)
2919{
2920 MLXSW_REG_ZERO(pbmc, payload);
2921 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2922 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2923 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2924}
2925
2926static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2927 int buf_index,
2928 u16 size)
2929{
2930 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2931 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2932 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2933}
2934
155f9de2
IS		 2935static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2936 int buf_index, u16 size,
2937 u16 threshold)
2938{
2939 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2940 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2941 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2942 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2943 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2944}
2945
4ec14b76
IS		 2946/* PSPA - Port Switch Partition Allocation
2947 * ---------------------------------------
2948 * Controls the association of a port with a switch partition and enables
2949 * configuring ports as stacking ports.
2950 */
3f0effd1 2951#define MLXSW_REG_PSPA_ID 0x500D
4ec14b76
IS		 2952#define MLXSW_REG_PSPA_LEN 0x8
2953
2954static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2955 .id = MLXSW_REG_PSPA_ID,
2956 .len = MLXSW_REG_PSPA_LEN,
2957};
2958
2959/* reg_pspa_swid
2960 * Switch partition ID.
2961 * Access: RW
2962 */
2963MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2964
2965/* reg_pspa_local_port
2966 * Local port number.
2967 * Access: Index
2968 */
2969MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2970
2971/* reg_pspa_sub_port
2972 * Virtual port within the local port. Set to 0 when virtual ports are
2973 * disabled on the local port.
2974 * Access: Index
2975 */
2976MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2977
2978static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2979{
2980 MLXSW_REG_ZERO(pspa, payload);
2981 mlxsw_reg_pspa_swid_set(payload, swid);
2982 mlxsw_reg_pspa_local_port_set(payload, local_port);
2983 mlxsw_reg_pspa_sub_port_set(payload, 0);
2984}
2985
2986/* HTGT - Host Trap Group Table
2987 * ----------------------------
2988 * Configures the properties for forwarding to CPU.
2989 */
2990#define MLXSW_REG_HTGT_ID 0x7002
2991#define MLXSW_REG_HTGT_LEN 0x100
2992
2993static const struct mlxsw_reg_info mlxsw_reg_htgt = {
2994 .id = MLXSW_REG_HTGT_ID,
2995 .len = MLXSW_REG_HTGT_LEN,
2996};
2997
2998/* reg_htgt_swid
2999 * Switch partition ID.
3000 * Access: Index
3001 */
3002MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
3003
3004#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
3005
3006/* reg_htgt_type
3007 * CPU path type.
3008 * Access: RW
3009 */
3010MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
3011
801bd3de
IS		 3012enum mlxsw_reg_htgt_trap_group {
3013 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3014 MLXSW_REG_HTGT_TRAP_GROUP_RX,
3015 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
3016};
4ec14b76
IS		 3017
3018/* reg_htgt_trap_group
3019 * Trap group number. User defined number specifying which trap groups
3020 * should be forwarded to the CPU. The mapping between trap IDs and trap
3021 * groups is configured using HPKT register.
3022 * Access: Index
3023 */
3024MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
3025
3026enum {
3027 MLXSW_REG_HTGT_POLICER_DISABLE,
3028 MLXSW_REG_HTGT_POLICER_ENABLE,
3029};
3030
3031/* reg_htgt_pide
3032 * Enable policer ID specified using 'pid' field.
3033 * Access: RW
3034 */
3035MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3036
3037/* reg_htgt_pid
3038 * Policer ID for the trap group.
3039 * Access: RW
3040 */
3041MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3042
3043#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3044
3045/* reg_htgt_mirror_action
3046 * Mirror action to use.
3047 * 0 - Trap to CPU.
3048 * 1 - Trap to CPU and mirror to a mirroring agent.
3049 * 2 - Mirror to a mirroring agent and do not trap to CPU.
3050 * Access: RW
3051 *
3052 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3053 */
3054MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3055
3056/* reg_htgt_mirroring_agent
3057 * Mirroring agent.
3058 * Access: RW
3059 */
3060MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3061
3062/* reg_htgt_priority
3063 * Trap group priority.
3064 * In case a packet matches multiple classification rules, the packet will
3065 * only be trapped once, based on the trap ID associated with the group (via
3066 * register HPKT) with the highest priority.
3067 * Supported values are 0-7, with 7 represnting the highest priority.
3068 * Access: RW
3069 *
3070 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3071 * by the 'trap_group' field.
3072 */
3073MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3074
3075/* reg_htgt_local_path_cpu_tclass
3076 * CPU ingress traffic class for the trap group.
3077 * Access: RW
3078 */
3079MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3080
3081#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
3082#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
801bd3de 3083#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
4ec14b76
IS		 3084
3085/* reg_htgt_local_path_rdq
3086 * Receive descriptor queue (RDQ) to use for the trap group.
3087 * Access: RW
3088 */
3089MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3090
801bd3de
IS		 3091static inline void mlxsw_reg_htgt_pack(char *payload,
3092 enum mlxsw_reg_htgt_trap_group group)
4ec14b76
IS		 3093{
3094 u8 swid, rdq;
3095
3096 MLXSW_REG_ZERO(htgt, payload);
801bd3de
IS		 3097 switch (group) {
3098 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
4ec14b76
IS		 3099 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3100 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
801bd3de
IS		 3101 break;
3102 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
4ec14b76
IS		 3103 swid = 0;
3104 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
801bd3de
IS		 3105 break;
3106 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3107 swid = 0;
3108 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3109 break;
4ec14b76
IS		 3110 }
3111 mlxsw_reg_htgt_swid_set(payload, swid);
3112 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
801bd3de 3113 mlxsw_reg_htgt_trap_group_set(payload, group);
4ec14b76
IS		 3114 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3115 mlxsw_reg_htgt_pid_set(payload, 0);
3116 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3117 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3118 mlxsw_reg_htgt_priority_set(payload, 0);
3119 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3120 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3121}
3122
3123/* HPKT - Host Packet Trap
3124 * -----------------------
3125 * Configures trap IDs inside trap groups.
3126 */
3127#define MLXSW_REG_HPKT_ID 0x7003
3128#define MLXSW_REG_HPKT_LEN 0x10
3129
3130static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3131 .id = MLXSW_REG_HPKT_ID,
3132 .len = MLXSW_REG_HPKT_LEN,
3133};
3134
3135enum {
3136 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3137 MLXSW_REG_HPKT_ACK_REQUIRED,
3138};
3139
3140/* reg_hpkt_ack
3141 * Require acknowledgements from the host for events.
3142 * If set, then the device will wait for the event it sent to be acknowledged
3143 * by the host. This option is only relevant for event trap IDs.
3144 * Access: RW
3145 *
3146 * Note: Currently not supported by firmware.
3147 */
3148MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3149
3150enum mlxsw_reg_hpkt_action {
3151 MLXSW_REG_HPKT_ACTION_FORWARD,
3152 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3153 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3154 MLXSW_REG_HPKT_ACTION_DISCARD,
3155 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3156 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3157};
3158
3159/* reg_hpkt_action
3160 * Action to perform on packet when trapped.
3161 * 0 - No action. Forward to CPU based on switching rules.
3162 * 1 - Trap to CPU (CPU receives sole copy).
3163 * 2 - Mirror to CPU (CPU receives a replica of the packet).
3164 * 3 - Discard.
3165 * 4 - Soft discard (allow other traps to act on the packet).
3166 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3167 * Access: RW
3168 *
3169 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3170 * addressed to the CPU.
3171 */
3172MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3173
3174/* reg_hpkt_trap_group
3175 * Trap group to associate the trap with.
3176 * Access: RW
3177 */
3178MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3179
3180/* reg_hpkt_trap_id
3181 * Trap ID.
3182 * Access: Index
3183 *
3184 * Note: A trap ID can only be associated with a single trap group. The device
3185 * will associate the trap ID with the last trap group configured.
3186 */
3187MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3188
3189enum {
3190 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3191 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3192 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3193};
3194
3195/* reg_hpkt_ctrl
3196 * Configure dedicated buffer resources for control packets.
3197 * 0 - Keep factory defaults.
3198 * 1 - Do not use control buffer for this trap ID.
3199 * 2 - Use control buffer for this trap ID.
3200 * Access: RW
3201 */
3202MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3203
f24af330 3204static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
4ec14b76 3205{
801bd3de 3206 enum mlxsw_reg_htgt_trap_group trap_group;
f24af330 3207
4ec14b76
IS		 3208 MLXSW_REG_ZERO(hpkt, payload);
3209 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3210 mlxsw_reg_hpkt_action_set(payload, action);
f24af330
IS		 3211 switch (trap_id) {
3212 case MLXSW_TRAP_ID_ETHEMAD:
3213 case MLXSW_TRAP_ID_PUDE:
3214 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3215 break;
3216 default:
3217 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3218 break;
3219 }
4ec14b76
IS		 3220 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3221 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3222 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3223}
3224
69c407aa
IS		 3225/* RGCR - Router General Configuration Register
3226 * --------------------------------------------
3227 * The register is used for setting up the router configuration.
3228 */
3229#define MLXSW_REG_RGCR_ID 0x8001
3230#define MLXSW_REG_RGCR_LEN 0x28
3231
3232static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3233 .id = MLXSW_REG_RGCR_ID,
3234 .len = MLXSW_REG_RGCR_LEN,
3235};
3236
3237/* reg_rgcr_ipv4_en
3238 * IPv4 router enable.
3239 * Access: RW
3240 */
3241MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3242
3243/* reg_rgcr_ipv6_en
3244 * IPv6 router enable.
3245 * Access: RW
3246 */
3247MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3248
3249/* reg_rgcr_max_router_interfaces
3250 * Defines the maximum number of active router interfaces for all virtual
3251 * routers.
3252 * Access: RW
3253 */
3254MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3255
3256/* reg_rgcr_usp
3257 * Update switch priority and packet color.
3258 * 0 - Preserve the value of Switch Priority and packet color.
3259 * 1 - Recalculate the value of Switch Priority and packet color.
3260 * Access: RW
3261 *
3262 * Note: Not supported by SwitchX and SwitchX-2.
3263 */
3264MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3265
3266/* reg_rgcr_pcp_rw
3267 * Indicates how to handle the pcp_rewrite_en value:
3268 * 0 - Preserve the value of pcp_rewrite_en.
3269 * 2 - Disable PCP rewrite.
3270 * 3 - Enable PCP rewrite.
3271 * Access: RW
3272 *
3273 * Note: Not supported by SwitchX and SwitchX-2.
3274 */
3275MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3276
3277/* reg_rgcr_activity_dis
3278 * Activity disable:
3279 * 0 - Activity will be set when an entry is hit (default).
3280 * 1 - Activity will not be set when an entry is hit.
3281 *
3282 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3283 * (RALUE).
3284 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3285 * Entry (RAUHT).
3286 * Bits 2:7 are reserved.
3287 * Access: RW
3288 *
3289 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3290 */
3291MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3292
3293static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3294{
3295 MLXSW_REG_ZERO(rgcr, payload);
3296 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3297}
3298
3dc26689
IS		 3299/* RITR - Router Interface Table Register
3300 * --------------------------------------
3301 * The register is used to configure the router interface table.
3302 */
3303#define MLXSW_REG_RITR_ID 0x8002
3304#define MLXSW_REG_RITR_LEN 0x40
3305
3306static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3307 .id = MLXSW_REG_RITR_ID,
3308 .len = MLXSW_REG_RITR_LEN,
3309};
3310
3311/* reg_ritr_enable
3312 * Enables routing on the router interface.
3313 * Access: RW
3314 */
3315MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3316
3317/* reg_ritr_ipv4
3318 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3319 * interface.
3320 * Access: RW
3321 */
3322MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3323
3324/* reg_ritr_ipv6
3325 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3326 * interface.
3327 * Access: RW
3328 */
3329MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3330
3331enum mlxsw_reg_ritr_if_type {
3332 MLXSW_REG_RITR_VLAN_IF,
3333 MLXSW_REG_RITR_FID_IF,
3334 MLXSW_REG_RITR_SP_IF,
3335};
3336
3337/* reg_ritr_type
3338 * Router interface type.
3339 * 0 - VLAN interface.
3340 * 1 - FID interface.
3341 * 2 - Sub-port interface.
3342 * Access: RW
3343 */
3344MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3345
3346enum {
3347 MLXSW_REG_RITR_RIF_CREATE,
3348 MLXSW_REG_RITR_RIF_DEL,
3349};
3350
3351/* reg_ritr_op
3352 * Opcode:
3353 * 0 - Create or edit RIF.
3354 * 1 - Delete RIF.
3355 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
3356 * is not supported. An interface must be deleted and re-created in order
3357 * to update properties.
3358 * Access: WO
3359 */
3360MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3361
3362/* reg_ritr_rif
3363 * Router interface index. A pointer to the Router Interface Table.
3364 * Access: Index
3365 */
3366MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3367
3368/* reg_ritr_ipv4_fe
3369 * IPv4 Forwarding Enable.
3370 * Enables routing of IPv4 traffic on the router interface. When disabled,
3371 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3372 * Not supported in SwitchX-2.
3373 * Access: RW
3374 */
3375MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3376
3377/* reg_ritr_ipv6_fe
3378 * IPv6 Forwarding Enable.
3379 * Enables routing of IPv6 traffic on the router interface. When disabled,
3380 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3381 * Not supported in SwitchX-2.
3382 * Access: RW
3383 */
3384MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3385
a94a614f
IS		 3386/* reg_ritr_lb_en
3387 * Loop-back filter enable for unicast packets.
3388 * If the flag is set then loop-back filter for unicast packets is
3389 * implemented on the RIF. Multicast packets are always subject to
3390 * loop-back filtering.
3391 * Access: RW
3392 */
3393MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
3394
3dc26689
IS		 3395/* reg_ritr_virtual_router
3396 * Virtual router ID associated with the router interface.
3397 * Access: RW
3398 */
3399MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3400
3401/* reg_ritr_mtu
3402 * Router interface MTU.
3403 * Access: RW
3404 */
3405MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3406
3407/* reg_ritr_if_swid
3408 * Switch partition ID.
3409 * Access: RW
3410 */
3411MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3412
3413/* reg_ritr_if_mac
3414 * Router interface MAC address.
3415 * In Spectrum, all MAC addresses must have the same 38 MSBits.
3416 * Access: RW
3417 */
3418MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3419
3420/* VLAN Interface */
3421
3422/* reg_ritr_vlan_if_vid
3423 * VLAN ID.
3424 * Access: RW
3425 */
3426MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3427
3428/* FID Interface */
3429
3430/* reg_ritr_fid_if_fid
3431 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
3432 * the vFID range are supported.
3433 * Access: RW
3434 */
3435MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3436
3437static inline void mlxsw_reg_ritr_fid_set(char *payload,
3438 enum mlxsw_reg_ritr_if_type rif_type,
3439 u16 fid)
3440{
3441 if (rif_type == MLXSW_REG_RITR_FID_IF)
3442 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3443 else
3444 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3445}
3446
3447/* Sub-port Interface */
3448
3449/* reg_ritr_sp_if_lag
3450 * LAG indication. When this bit is set the system_port field holds the
3451 * LAG identifier.
3452 * Access: RW
3453 */
3454MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3455
3456/* reg_ritr_sp_system_port
3457 * Port unique indentifier. When lag bit is set, this field holds the
3458 * lag_id in bits 0:9.
3459 * Access: RW
3460 */
3461MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3462
3463/* reg_ritr_sp_if_vid
3464 * VLAN ID.
3465 * Access: RW
3466 */
3467MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3468
3469static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3470{
3471 MLXSW_REG_ZERO(ritr, payload);
3472 mlxsw_reg_ritr_rif_set(payload, rif);
3473}
3474
3475static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3476 u16 system_port, u16 vid)
3477{
3478 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3479 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3480 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3481}
3482
3483static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3484 enum mlxsw_reg_ritr_if_type type,
3485 u16 rif, u16 mtu, const char *mac)
3486{
3487 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3488
3489 MLXSW_REG_ZERO(ritr, payload);
3490 mlxsw_reg_ritr_enable_set(payload, enable);
3491 mlxsw_reg_ritr_ipv4_set(payload, 1);
3492 mlxsw_reg_ritr_type_set(payload, type);
3493 mlxsw_reg_ritr_op_set(payload, op);
3494 mlxsw_reg_ritr_rif_set(payload, rif);
3495 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
a94a614f 3496 mlxsw_reg_ritr_lb_en_set(payload, 1);
3dc26689
IS		 3497 mlxsw_reg_ritr_mtu_set(payload, mtu);
3498 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3499}
3500
089f9816
YG		 3501/* RATR - Router Adjacency Table Register
3502 * --------------------------------------
3503 * The RATR register is used to configure the Router Adjacency (next-hop)
3504 * Table.
3505 */
3506#define MLXSW_REG_RATR_ID 0x8008
3507#define MLXSW_REG_RATR_LEN 0x2C
3508
3509static const struct mlxsw_reg_info mlxsw_reg_ratr = {
3510 .id = MLXSW_REG_RATR_ID,
3511 .len = MLXSW_REG_RATR_LEN,
3512};
3513
3514enum mlxsw_reg_ratr_op {
3515 /* Read */
3516 MLXSW_REG_RATR_OP_QUERY_READ = 0,
3517 /* Read and clear activity */
3518 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
3519 /* Write Adjacency entry */
3520 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
3521 /* Write Adjacency entry only if the activity is cleared.
3522 * The write may not succeed if the activity is set. There is not
3523 * direct feedback if the write has succeeded or not, however
3524 * the get will reveal the actual entry (SW can compare the get
3525 * response to the set command).
3526 */
3527 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
3528};
3529
3530/* reg_ratr_op
3531 * Note that Write operation may also be used for updating
3532 * counter_set_type and counter_index. In this case all other
3533 * fields must not be updated.
3534 * Access: OP
3535 */
3536MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
3537
3538/* reg_ratr_v
3539 * Valid bit. Indicates if the adjacency entry is valid.
3540 * Note: the device may need some time before reusing an invalidated
3541 * entry. During this time the entry can not be reused. It is
3542 * recommended to use another entry before reusing an invalidated
3543 * entry (e.g. software can put it at the end of the list for
3544 * reusing). Trying to access an invalidated entry not yet cleared
3545 * by the device results with failure indicating "Try Again" status.
3546 * When valid is '0' then egress_router_interface,trap_action,
3547 * adjacency_parameters and counters are reserved
3548 * Access: RW
3549 */
3550MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
3551
3552/* reg_ratr_a
3553 * Activity. Set for new entries. Set if a packet lookup has hit on
3554 * the specific entry. To clear the a bit, use "clear activity".
3555 * Access: RO
3556 */
3557MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
3558
3559/* reg_ratr_adjacency_index_low
3560 * Bits 15:0 of index into the adjacency table.
3561 * For SwitchX and SwitchX-2, the adjacency table is linear and
3562 * used for adjacency entries only.
3563 * For Spectrum, the index is to the KVD linear.
3564 * Access: Index
3565 */
3566MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
3567
3568/* reg_ratr_egress_router_interface
3569 * Range is 0 .. cap_max_router_interfaces - 1
3570 * Access: RW
3571 */
3572MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
3573
3574enum mlxsw_reg_ratr_trap_action {
3575 MLXSW_REG_RATR_TRAP_ACTION_NOP,
3576 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
3577 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
3578 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
3579 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
3580};
3581
3582/* reg_ratr_trap_action
3583 * see mlxsw_reg_ratr_trap_action
3584 * Access: RW
3585 */
3586MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
3587
3588enum mlxsw_reg_ratr_trap_id {
3589 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0,
3590 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1,
3591};
3592
3593/* reg_ratr_adjacency_index_high
3594 * Bits 23:16 of the adjacency_index.
3595 * Access: Index
3596 */
3597MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
3598
3599/* reg_ratr_trap_id
3600 * Trap ID to be reported to CPU.
3601 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
3602 * For trap_action of NOP, MIRROR and DISCARD_ERROR
3603 * Access: RW
3604 */
3605MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
3606
3607/* reg_ratr_eth_destination_mac
3608 * MAC address of the destination next-hop.
3609 * Access: RW
3610 */
3611MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
3612
3613static inline void
3614mlxsw_reg_ratr_pack(char *payload,
3615 enum mlxsw_reg_ratr_op op, bool valid,
3616 u32 adjacency_index, u16 egress_rif)
3617{
3618 MLXSW_REG_ZERO(ratr, payload);
3619 mlxsw_reg_ratr_op_set(payload, op);
3620 mlxsw_reg_ratr_v_set(payload, valid);
3621 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
3622 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
3623 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
3624}
3625
3626static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
3627 const char *dest_mac)
3628{
3629 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
3630}
3631
6f9fc3ce
JP		 3632/* RALTA - Router Algorithmic LPM Tree Allocation Register
3633 * -------------------------------------------------------
3634 * RALTA is used to allocate the LPM trees of the SHSPM method.
3635 */
3636#define MLXSW_REG_RALTA_ID 0x8010
3637#define MLXSW_REG_RALTA_LEN 0x04
3638
3639static const struct mlxsw_reg_info mlxsw_reg_ralta = {
3640 .id = MLXSW_REG_RALTA_ID,
3641 .len = MLXSW_REG_RALTA_LEN,
3642};
3643
3644/* reg_ralta_op
3645 * opcode (valid for Write, must be 0 on Read)
3646 * 0 - allocate a tree
3647 * 1 - deallocate a tree
3648 * Access: OP
3649 */
3650MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
3651
3652enum mlxsw_reg_ralxx_protocol {
3653 MLXSW_REG_RALXX_PROTOCOL_IPV4,
3654 MLXSW_REG_RALXX_PROTOCOL_IPV6,
3655};
3656
3657/* reg_ralta_protocol
3658 * Protocol.
3659 * Deallocation opcode: Reserved.
3660 * Access: RW
3661 */
3662MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
3663
3664/* reg_ralta_tree_id
3665 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
3666 * the tree identifier (managed by software).
3667 * Note that tree_id 0 is allocated for a default-route tree.
3668 * Access: Index
3669 */
3670MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
3671
3672static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
3673 enum mlxsw_reg_ralxx_protocol protocol,
3674 u8 tree_id)
3675{
3676 MLXSW_REG_ZERO(ralta, payload);
3677 mlxsw_reg_ralta_op_set(payload, !alloc);
3678 mlxsw_reg_ralta_protocol_set(payload, protocol);
3679 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
3680}
3681
a9823359
JP		 3682/* RALST - Router Algorithmic LPM Structure Tree Register
3683 * ------------------------------------------------------
3684 * RALST is used to set and query the structure of an LPM tree.
3685 * The structure of the tree must be sorted as a sorted binary tree, while
3686 * each node is a bin that is tagged as the length of the prefixes the lookup
3687 * will refer to. Therefore, bin X refers to a set of entries with prefixes
3688 * of X bits to match with the destination address. The bin 0 indicates
3689 * the default action, when there is no match of any prefix.
3690 */
3691#define MLXSW_REG_RALST_ID 0x8011
3692#define MLXSW_REG_RALST_LEN 0x104
3693
3694static const struct mlxsw_reg_info mlxsw_reg_ralst = {
3695 .id = MLXSW_REG_RALST_ID,
3696 .len = MLXSW_REG_RALST_LEN,
3697};
3698
3699/* reg_ralst_root_bin
3700 * The bin number of the root bin.
3701 * 0<root_bin=<(length of IP address)
3702 * For a default-route tree configure 0xff
3703 * Access: RW
3704 */
3705MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
3706
3707/* reg_ralst_tree_id
3708 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3709 * Access: Index
3710 */
3711MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
3712
3713#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
3714#define MLXSW_REG_RALST_BIN_OFFSET 0x04
3715#define MLXSW_REG_RALST_BIN_COUNT 128
3716
3717/* reg_ralst_left_child_bin
3718 * Holding the children of the bin according to the stored tree's structure.
3719 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3720 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3721 * Access: RW
3722 */
3723MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
3724
3725/* reg_ralst_right_child_bin
3726 * Holding the children of the bin according to the stored tree's structure.
3727 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3728 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3729 * Access: RW
3730 */
3731MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
3732 false);
3733
3734static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
3735{
3736 MLXSW_REG_ZERO(ralst, payload);
3737
3738 /* Initialize all bins to have no left or right child */
3739 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
3740 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
3741
3742 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
3743 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
3744}
3745
3746static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
3747 u8 left_child_bin,
3748 u8 right_child_bin)
3749{
3750 int bin_index = bin_number - 1;
3751
3752 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
3753 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
3754 right_child_bin);
3755}
3756
20ae4053
JP		 3757/* RALTB - Router Algorithmic LPM Tree Binding Register
3758 * ----------------------------------------------------
3759 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
3760 */
3761#define MLXSW_REG_RALTB_ID 0x8012
3762#define MLXSW_REG_RALTB_LEN 0x04
3763
3764static const struct mlxsw_reg_info mlxsw_reg_raltb = {
3765 .id = MLXSW_REG_RALTB_ID,
3766 .len = MLXSW_REG_RALTB_LEN,
3767};
3768
3769/* reg_raltb_virtual_router
3770 * Virtual Router ID
3771 * Range is 0..cap_max_virtual_routers-1
3772 * Access: Index
3773 */
3774MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
3775
3776/* reg_raltb_protocol
3777 * Protocol.
3778 * Access: Index
3779 */
3780MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
3781
3782/* reg_raltb_tree_id
3783 * Tree to be used for the {virtual_router, protocol}
3784 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3785 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
3786 * Access: RW
3787 */
3788MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
3789
3790static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
3791 enum mlxsw_reg_ralxx_protocol protocol,
3792 u8 tree_id)
3793{
3794 MLXSW_REG_ZERO(raltb, payload);
3795 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
3796 mlxsw_reg_raltb_protocol_set(payload, protocol);
3797 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
3798}
3799
d5a1c749
JP		 3800/* RALUE - Router Algorithmic LPM Unicast Entry Register
3801 * -----------------------------------------------------
3802 * RALUE is used to configure and query LPM entries that serve
3803 * the Unicast protocols.
3804 */
3805#define MLXSW_REG_RALUE_ID 0x8013
3806#define MLXSW_REG_RALUE_LEN 0x38
3807
3808static const struct mlxsw_reg_info mlxsw_reg_ralue = {
3809 .id = MLXSW_REG_RALUE_ID,
3810 .len = MLXSW_REG_RALUE_LEN,
3811};
3812
3813/* reg_ralue_protocol
3814 * Protocol.
3815 * Access: Index
3816 */
3817MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
3818
3819enum mlxsw_reg_ralue_op {
3820 /* Read operation. If entry doesn't exist, the operation fails. */
3821 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
3822 /* Clear on read operation. Used to read entry and
3823 * clear Activity bit.
3824 */
3825 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
3826 /* Write operation. Used to write a new entry to the table. All RW
3827 * fields are written for new entry. Activity bit is set
3828 * for new entries.
3829 */
3830 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
3831 /* Update operation. Used to update an existing route entry and
3832 * only update the RW fields that are detailed in the field
3833 * op_u_mask. If entry doesn't exist, the operation fails.
3834 */
3835 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
3836 /* Clear activity. The Activity bit (the field a) is cleared
3837 * for the entry.
3838 */
3839 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
3840 /* Delete operation. Used to delete an existing entry. If entry
3841 * doesn't exist, the operation fails.
3842 */
3843 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
3844};
3845
3846/* reg_ralue_op
3847 * Operation.
3848 * Access: OP
3849 */
3850MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
3851
3852/* reg_ralue_a
3853 * Activity. Set for new entries. Set if a packet lookup has hit on the
3854 * specific entry, only if the entry is a route. To clear the a bit, use
3855 * "clear activity" op.
3856 * Enabled by activity_dis in RGCR
3857 * Access: RO
3858 */
3859MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
3860
3861/* reg_ralue_virtual_router
3862 * Virtual Router ID
3863 * Range is 0..cap_max_virtual_routers-1
3864 * Access: Index
3865 */
3866MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
3867
3868#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
3869#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
3870#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
3871
3872/* reg_ralue_op_u_mask
3873 * opcode update mask.
3874 * On read operation, this field is reserved.
3875 * This field is valid for update opcode, otherwise - reserved.
3876 * This field is a bitmask of the fields that should be updated.
3877 * Access: WO
3878 */
3879MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
3880
3881/* reg_ralue_prefix_len
3882 * Number of bits in the prefix of the LPM route.
3883 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
3884 * two entries in the physical HW table.
3885 * Access: Index
3886 */
3887MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
3888
3889/* reg_ralue_dip*
3890 * The prefix of the route or of the marker that the object of the LPM
3891 * is compared with. The most significant bits of the dip are the prefix.
3892 * The list significant bits must be '0' if the prefix_len is smaller
3893 * than 128 for IPv6 or smaller than 32 for IPv4.
3894 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
3895 * Access: Index
3896 */
3897MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
3898
3899enum mlxsw_reg_ralue_entry_type {
3900 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
3901 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
3902 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
3903};
3904
3905/* reg_ralue_entry_type
3906 * Entry type.
3907 * Note - for Marker entries, the action_type and action fields are reserved.
3908 * Access: RW
3909 */
3910MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
3911
3912/* reg_ralue_bmp_len
3913 * The best match prefix length in the case that there is no match for
3914 * longer prefixes.
3915 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
3916 * Note for any update operation with entry_type modification this
3917 * field must be set.
3918 * Access: RW
3919 */
3920MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
3921
3922enum mlxsw_reg_ralue_action_type {
3923 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
3924 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
3925 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
3926};
3927
3928/* reg_ralue_action_type
3929 * Action Type
3930 * Indicates how the IP address is connected.
3931 * It can be connected to a local subnet through local_erif or can be
3932 * on a remote subnet connected through a next-hop router,
3933 * or transmitted to the CPU.
3934 * Reserved when entry_type = MARKER_ENTRY
3935 * Access: RW
3936 */
3937MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
3938
3939enum mlxsw_reg_ralue_trap_action {
3940 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
3941 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
3942 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
3943 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
3944 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
3945};
3946
3947/* reg_ralue_trap_action
3948 * Trap action.
3949 * For IP2ME action, only NOP and MIRROR are possible.
3950 * Access: RW
3951 */
3952MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
3953
3954/* reg_ralue_trap_id
3955 * Trap ID to be reported to CPU.
3956 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
3957 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
3958 * Access: RW
3959 */
3960MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
3961
3962/* reg_ralue_adjacency_index
3963 * Points to the first entry of the group-based ECMP.
3964 * Only relevant in case of REMOTE action.
3965 * Access: RW
3966 */
3967MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
3968
3969/* reg_ralue_ecmp_size
3970 * Amount of sequential entries starting
3971 * from the adjacency_index (the number of ECMPs).
3972 * The valid range is 1-64, 512, 1024, 2048 and 4096.
3973 * Reserved when trap_action is TRAP or DISCARD_ERROR.
3974 * Only relevant in case of REMOTE action.
3975 * Access: RW
3976 */
3977MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
3978
3979/* reg_ralue_local_erif
3980 * Egress Router Interface.
3981 * Only relevant in case of LOCAL action.
3982 * Access: RW
3983 */
3984MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
3985
3986/* reg_ralue_v
3987 * Valid bit for the tunnel_ptr field.
3988 * If valid = 0 then trap to CPU as IP2ME trap ID.
3989 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
3990 * decapsulation then tunnel decapsulation is done.
3991 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
3992 * decapsulation then trap as IP2ME trap ID.
3993 * Only relevant in case of IP2ME action.
3994 * Access: RW
3995 */
3996MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1);
3997
3998/* reg_ralue_tunnel_ptr
3999 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
4000 * For Spectrum, pointer to KVD Linear.
4001 * Only relevant in case of IP2ME action.
4002 * Access: RW
4003 */
4004MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24);
4005
4006static inline void mlxsw_reg_ralue_pack(char *payload,
4007 enum mlxsw_reg_ralxx_protocol protocol,
4008 enum mlxsw_reg_ralue_op op,
4009 u16 virtual_router, u8 prefix_len)
4010{
4011 MLXSW_REG_ZERO(ralue, payload);
4012 mlxsw_reg_ralue_protocol_set(payload, protocol);
0e7df1a2 4013 mlxsw_reg_ralue_op_set(payload, op);
d5a1c749
JP		 4014 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
4015 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
4016 mlxsw_reg_ralue_entry_type_set(payload,
4017 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
4018 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
4019}
4020
4021static inline void mlxsw_reg_ralue_pack4(char *payload,
4022 enum mlxsw_reg_ralxx_protocol protocol,
4023 enum mlxsw_reg_ralue_op op,
4024 u16 virtual_router, u8 prefix_len,
4025 u32 dip)
4026{
4027 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
4028 mlxsw_reg_ralue_dip4_set(payload, dip);
4029}
4030
4031static inline void
4032mlxsw_reg_ralue_act_remote_pack(char *payload,
4033 enum mlxsw_reg_ralue_trap_action trap_action,
4034 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
4035{
4036 mlxsw_reg_ralue_action_type_set(payload,
4037 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
4038 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4039 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4040 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
4041 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
4042}
4043
4044static inline void
4045mlxsw_reg_ralue_act_local_pack(char *payload,
4046 enum mlxsw_reg_ralue_trap_action trap_action,
4047 u16 trap_id, u16 local_erif)
4048{
4049 mlxsw_reg_ralue_action_type_set(payload,
4050 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
4051 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4052 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4053 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
4054}
4055
4056static inline void
4057mlxsw_reg_ralue_act_ip2me_pack(char *payload)
4058{
4059 mlxsw_reg_ralue_action_type_set(payload,
4060 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
4061}
4062
4457b3df
YG		 4063/* RAUHT - Router Algorithmic LPM Unicast Host Table Register
4064 * ----------------------------------------------------------
4065 * The RAUHT register is used to configure and query the Unicast Host table in
4066 * devices that implement the Algorithmic LPM.
4067 */
4068#define MLXSW_REG_RAUHT_ID 0x8014
4069#define MLXSW_REG_RAUHT_LEN 0x74
4070
4071static const struct mlxsw_reg_info mlxsw_reg_rauht = {
4072 .id = MLXSW_REG_RAUHT_ID,
4073 .len = MLXSW_REG_RAUHT_LEN,
4074};
4075
4076enum mlxsw_reg_rauht_type {
4077 MLXSW_REG_RAUHT_TYPE_IPV4,
4078 MLXSW_REG_RAUHT_TYPE_IPV6,
4079};
4080
4081/* reg_rauht_type
4082 * Access: Index
4083 */
4084MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
4085
4086enum mlxsw_reg_rauht_op {
4087 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
4088 /* Read operation */
4089 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
4090 /* Clear on read operation. Used to read entry and clear
4091 * activity bit.
4092 */
4093 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
4094 /* Add. Used to write a new entry to the table. All R/W fields are
4095 * relevant for new entry. Activity bit is set for new entries.
4096 */
4097 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
4098 /* Update action. Used to update an existing route entry and
4099 * only update the following fields:
4100 * trap_action, trap_id, mac, counter_set_type, counter_index
4101 */
4102 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
4103 /* Clear activity. A bit is cleared for the entry. */
4104 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
4105 /* Delete entry */
4106 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
4107 /* Delete all host entries on a RIF. In this command, dip
4108 * field is reserved.
4109 */
4110};
4111
4112/* reg_rauht_op
4113 * Access: OP
4114 */
4115MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
4116
4117/* reg_rauht_a
4118 * Activity. Set for new entries. Set if a packet lookup has hit on
4119 * the specific entry.
4120 * To clear the a bit, use "clear activity" op.
4121 * Enabled by activity_dis in RGCR
4122 * Access: RO
4123 */
4124MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
4125
4126/* reg_rauht_rif
4127 * Router Interface
4128 * Access: Index
4129 */
4130MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
4131
4132/* reg_rauht_dip*
4133 * Destination address.
4134 * Access: Index
4135 */
4136MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
4137
4138enum mlxsw_reg_rauht_trap_action {
4139 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
4140 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
4141 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
4142 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
4143 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
4144};
4145
4146/* reg_rauht_trap_action
4147 * Access: RW
4148 */
4149MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
4150
4151enum mlxsw_reg_rauht_trap_id {
4152 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
4153 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
4154};
4155
4156/* reg_rauht_trap_id
4157 * Trap ID to be reported to CPU.
4158 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
4159 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
4160 * trap_id is reserved.
4161 * Access: RW
4162 */
4163MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
4164
4165/* reg_rauht_counter_set_type
4166 * Counter set type for flow counters
4167 * Access: RW
4168 */
4169MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
4170
4171/* reg_rauht_counter_index
4172 * Counter index for flow counters
4173 * Access: RW
4174 */
4175MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
4176
4177/* reg_rauht_mac
4178 * MAC address.
4179 * Access: RW
4180 */
4181MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
4182
4183static inline void mlxsw_reg_rauht_pack(char *payload,
4184 enum mlxsw_reg_rauht_op op, u16 rif,
4185 const char *mac)
4186{
4187 MLXSW_REG_ZERO(rauht, payload);
4188 mlxsw_reg_rauht_op_set(payload, op);
4189 mlxsw_reg_rauht_rif_set(payload, rif);
4190 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
4191}
4192
4193static inline void mlxsw_reg_rauht_pack4(char *payload,
4194 enum mlxsw_reg_rauht_op op, u16 rif,
4195 const char *mac, u32 dip)
4196{
4197 mlxsw_reg_rauht_pack(payload, op, rif, mac);
4198 mlxsw_reg_rauht_dip4_set(payload, dip);
4199}
4200
a59f0b31
JP		 4201/* RALEU - Router Algorithmic LPM ECMP Update Register
4202 * ---------------------------------------------------
4203 * The register enables updating the ECMP section in the action for multiple
4204 * LPM Unicast entries in a single operation. The update is executed to
4205 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
4206 */
4207#define MLXSW_REG_RALEU_ID 0x8015
4208#define MLXSW_REG_RALEU_LEN 0x28
4209
4210static const struct mlxsw_reg_info mlxsw_reg_raleu = {
4211 .id = MLXSW_REG_RALEU_ID,
4212 .len = MLXSW_REG_RALEU_LEN,
4213};
4214
4215/* reg_raleu_protocol
4216 * Protocol.
4217 * Access: Index
4218 */
4219MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
4220
4221/* reg_raleu_virtual_router
4222 * Virtual Router ID
4223 * Range is 0..cap_max_virtual_routers-1
4224 * Access: Index
4225 */
4226MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
4227
4228/* reg_raleu_adjacency_index
4229 * Adjacency Index used for matching on the existing entries.
4230 * Access: Index
4231 */
4232MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
4233
4234/* reg_raleu_ecmp_size
4235 * ECMP Size used for matching on the existing entries.
4236 * Access: Index
4237 */
4238MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
4239
4240/* reg_raleu_new_adjacency_index
4241 * New Adjacency Index.
4242 * Access: WO
4243 */
4244MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
4245
4246/* reg_raleu_new_ecmp_size
4247 * New ECMP Size.
4248 * Access: WO
4249 */
4250MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
4251
4252static inline void mlxsw_reg_raleu_pack(char *payload,
4253 enum mlxsw_reg_ralxx_protocol protocol,
4254 u16 virtual_router,
4255 u32 adjacency_index, u16 ecmp_size,
4256 u32 new_adjacency_index,
4257 u16 new_ecmp_size)
4258{
4259 MLXSW_REG_ZERO(raleu, payload);
4260 mlxsw_reg_raleu_protocol_set(payload, protocol);
4261 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
4262 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
4263 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
4264 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
4265 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
4266}
4267
7cf2c205
YG		 4268/* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
4269 * ----------------------------------------------------------------
4270 * The RAUHTD register allows dumping entries from the Router Unicast Host
4271 * Table. For a given session an entry is dumped no more than one time. The
4272 * first RAUHTD access after reset is a new session. A session ends when the
4273 * num_rec response is smaller than num_rec request or for IPv4 when the
4274 * num_entries is smaller than 4. The clear activity affect the current session
4275 * or the last session if a new session has not started.
4276 */
4277#define MLXSW_REG_RAUHTD_ID 0x8018
4278#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
4279#define MLXSW_REG_RAUHTD_REC_LEN 0x20
4280#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
4281#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
4282 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
4283#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
4284
4285static const struct mlxsw_reg_info mlxsw_reg_rauhtd = {
4286 .id = MLXSW_REG_RAUHTD_ID,
4287 .len = MLXSW_REG_RAUHTD_LEN,
4288};
4289
4290#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
4291#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
4292
4293/* reg_rauhtd_filter_fields
4294 * if a bit is '0' then the relevant field is ignored and dump is done
4295 * regardless of the field value
4296 * Bit0 - filter by activity: entry_a
4297 * Bit3 - filter by entry rip: entry_rif
4298 * Access: Index
4299 */
4300MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
4301
4302enum mlxsw_reg_rauhtd_op {
4303 MLXSW_REG_RAUHTD_OP_DUMP,
4304 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
4305};
4306
4307/* reg_rauhtd_op
4308 * Access: OP
4309 */
4310MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
4311
4312/* reg_rauhtd_num_rec
4313 * At request: number of records requested
4314 * At response: number of records dumped
4315 * For IPv4, each record has 4 entries at request and up to 4 entries
4316 * at response
4317 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
4318 * Access: Index
4319 */
4320MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
4321
4322/* reg_rauhtd_entry_a
4323 * Dump only if activity has value of entry_a
4324 * Reserved if filter_fields bit0 is '0'
4325 * Access: Index
4326 */
4327MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
4328
4329enum mlxsw_reg_rauhtd_type {
4330 MLXSW_REG_RAUHTD_TYPE_IPV4,
4331 MLXSW_REG_RAUHTD_TYPE_IPV6,
4332};
4333
4334/* reg_rauhtd_type
4335 * Dump only if record type is:
4336 * 0 - IPv4
4337 * 1 - IPv6
4338 * Access: Index
4339 */
4340MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
4341
4342/* reg_rauhtd_entry_rif
4343 * Dump only if RIF has value of entry_rif
4344 * Reserved if filter_fields bit3 is '0'
4345 * Access: Index
4346 */
4347MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
4348
4349static inline void mlxsw_reg_rauhtd_pack(char *payload,
4350 enum mlxsw_reg_rauhtd_type type)
4351{
4352 MLXSW_REG_ZERO(rauhtd, payload);
4353 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
4354 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
4355 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
4356 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
4357 mlxsw_reg_rauhtd_type_set(payload, type);
4358}
4359
4360/* reg_rauhtd_ipv4_rec_num_entries
4361 * Number of valid entries in this record:
4362 * 0 - 1 valid entry
4363 * 1 - 2 valid entries
4364 * 2 - 3 valid entries
4365 * 3 - 4 valid entries
4366 * Access: RO
4367 */
4368MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
4369 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
4370 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4371
4372/* reg_rauhtd_rec_type
4373 * Record type.
4374 * 0 - IPv4
4375 * 1 - IPv6
4376 * Access: RO
4377 */
4378MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
4379 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4380
4381#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
4382
4383/* reg_rauhtd_ipv4_ent_a
4384 * Activity. Set for new entries. Set if a packet lookup has hit on the
4385 * specific entry.
4386 * Access: RO
4387 */
4388MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
4389 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4390
4391/* reg_rauhtd_ipv4_ent_rif
4392 * Router interface.
4393 * Access: RO
4394 */
4395MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4396 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4397
4398/* reg_rauhtd_ipv4_ent_dip
4399 * Destination IPv4 address.
4400 * Access: RO
4401 */
4402MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4403 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
4404
4405static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
4406 int ent_index, u16 *p_rif,
4407 u32 *p_dip)
4408{
4409 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
4410 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
4411}
4412
5246f2e2
JP		 4413/* MFCR - Management Fan Control Register
4414 * --------------------------------------
4415 * This register controls the settings of the Fan Speed PWM mechanism.
4416 */
4417#define MLXSW_REG_MFCR_ID 0x9001
4418#define MLXSW_REG_MFCR_LEN 0x08
4419
4420static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
4421 .id = MLXSW_REG_MFCR_ID,
4422 .len = MLXSW_REG_MFCR_LEN,
4423};
4424
4425enum mlxsw_reg_mfcr_pwm_frequency {
4426 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
4427 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
4428 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
4429 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
4430 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
4431 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
4432 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
4433 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
4434};
4435
4436/* reg_mfcr_pwm_frequency
4437 * Controls the frequency of the PWM signal.
4438 * Access: RW
4439 */
4440MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
4441
4442#define MLXSW_MFCR_TACHOS_MAX 10
4443
4444/* reg_mfcr_tacho_active
4445 * Indicates which of the tachometer is active (bit per tachometer).
4446 * Access: RO
4447 */
4448MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
4449
4450#define MLXSW_MFCR_PWMS_MAX 5
4451
4452/* reg_mfcr_pwm_active
4453 * Indicates which of the PWM control is active (bit per PWM).
4454 * Access: RO
4455 */
4456MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
4457
4458static inline void
4459mlxsw_reg_mfcr_pack(char *payload,
4460 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
4461{
4462 MLXSW_REG_ZERO(mfcr, payload);
4463 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
4464}
4465
4466static inline void
4467mlxsw_reg_mfcr_unpack(char *payload,
4468 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
4469 u16 *p_tacho_active, u8 *p_pwm_active)
4470{
4471 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
4472 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
4473 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
4474}
4475
4476/* MFSC - Management Fan Speed Control Register
4477 * --------------------------------------------
4478 * This register controls the settings of the Fan Speed PWM mechanism.
4479 */
4480#define MLXSW_REG_MFSC_ID 0x9002
4481#define MLXSW_REG_MFSC_LEN 0x08
4482
4483static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
4484 .id = MLXSW_REG_MFSC_ID,
4485 .len = MLXSW_REG_MFSC_LEN,
4486};
4487
4488/* reg_mfsc_pwm
4489 * Fan pwm to control / monitor.
4490 * Access: Index
4491 */
4492MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
4493
4494/* reg_mfsc_pwm_duty_cycle
4495 * Controls the duty cycle of the PWM. Value range from 0..255 to
4496 * represent duty cycle of 0%...100%.
4497 * Access: RW
4498 */
4499MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
4500
4501static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
4502 u8 pwm_duty_cycle)
4503{
4504 MLXSW_REG_ZERO(mfsc, payload);
4505 mlxsw_reg_mfsc_pwm_set(payload, pwm);
4506 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
4507}
4508
4509/* MFSM - Management Fan Speed Measurement
4510 * ---------------------------------------
4511 * This register controls the settings of the Tacho measurements and
4512 * enables reading the Tachometer measurements.
4513 */
4514#define MLXSW_REG_MFSM_ID 0x9003
4515#define MLXSW_REG_MFSM_LEN 0x08
4516
4517static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
4518 .id = MLXSW_REG_MFSM_ID,
4519 .len = MLXSW_REG_MFSM_LEN,
4520};
4521
4522/* reg_mfsm_tacho
4523 * Fan tachometer index.
4524 * Access: Index
4525 */
4526MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
4527
4528/* reg_mfsm_rpm
4529 * Fan speed (round per minute).
4530 * Access: RO
4531 */
4532MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
4533
4534static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
4535{
4536 MLXSW_REG_ZERO(mfsm, payload);
4537 mlxsw_reg_mfsm_tacho_set(payload, tacho);
4538}
4539
85926f87
JP		 4540/* MTCAP - Management Temperature Capabilities
4541 * -------------------------------------------
4542 * This register exposes the capabilities of the device and
4543 * system temperature sensing.
4544 */
4545#define MLXSW_REG_MTCAP_ID 0x9009
4546#define MLXSW_REG_MTCAP_LEN 0x08
4547
4548static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
4549 .id = MLXSW_REG_MTCAP_ID,
4550 .len = MLXSW_REG_MTCAP_LEN,
4551};
4552
4553/* reg_mtcap_sensor_count
4554 * Number of sensors supported by the device.
4555 * This includes the QSFP module sensors (if exists in the QSFP module).
4556 * Access: RO
4557 */
4558MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
4559
4560/* MTMP - Management Temperature
4561 * -----------------------------
4562 * This register controls the settings of the temperature measurements
4563 * and enables reading the temperature measurements. Note that temperature
4564 * is in 0.125 degrees Celsius.
4565 */
4566#define MLXSW_REG_MTMP_ID 0x900A
4567#define MLXSW_REG_MTMP_LEN 0x20
4568
4569static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
4570 .id = MLXSW_REG_MTMP_ID,
4571 .len = MLXSW_REG_MTMP_LEN,
4572};
4573
4574/* reg_mtmp_sensor_index
4575 * Sensors index to access.
4576 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
4577 * (module 0 is mapped to sensor_index 64).
4578 * Access: Index
4579 */
4580MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
4581
4582/* Convert to milli degrees Celsius */
4583#define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
4584
4585/* reg_mtmp_temperature
4586 * Temperature reading from the sensor. Reading is in 0.125 Celsius
4587 * degrees units.
4588 * Access: RO
4589 */
4590MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
4591
4592/* reg_mtmp_mte
4593 * Max Temperature Enable - enables measuring the max temperature on a sensor.
4594 * Access: RW
4595 */
4596MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
4597
4598/* reg_mtmp_mtr
4599 * Max Temperature Reset - clears the value of the max temperature register.
4600 * Access: WO
4601 */
4602MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
4603
4604/* reg_mtmp_max_temperature
4605 * The highest measured temperature from the sensor.
4606 * When the bit mte is cleared, the field max_temperature is reserved.
4607 * Access: RO
4608 */
4609MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
4610
4611#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
4612
4613/* reg_mtmp_sensor_name
4614 * Sensor Name
4615 * Access: RO
4616 */
4617MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
4618
4619static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
4620 bool max_temp_enable,
4621 bool max_temp_reset)
4622{
4623 MLXSW_REG_ZERO(mtmp, payload);
4624 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
4625 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
4626 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
4627}
4628
4629static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
4630 unsigned int *p_max_temp,
4631 char *sensor_name)
4632{
4633 u16 temp;
4634
4635 if (p_temp) {
4636 temp = mlxsw_reg_mtmp_temperature_get(payload);
4637 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4638 }
4639 if (p_max_temp) {
acf35a4e 4640 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
85926f87
JP		 4641 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4642 }
4643 if (sensor_name)
4644 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
4645}
4646
43a46856
YG		 4647/* MPAT - Monitoring Port Analyzer Table
4648 * -------------------------------------
4649 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
4650 * For an enabled analyzer, all fields except e (enable) cannot be modified.
4651 */
4652#define MLXSW_REG_MPAT_ID 0x901A
4653#define MLXSW_REG_MPAT_LEN 0x78
4654
4655static const struct mlxsw_reg_info mlxsw_reg_mpat = {
4656 .id = MLXSW_REG_MPAT_ID,
4657 .len = MLXSW_REG_MPAT_LEN,
4658};
4659
4660/* reg_mpat_pa_id
4661 * Port Analyzer ID.
4662 * Access: Index
4663 */
4664MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
4665
4666/* reg_mpat_system_port
4667 * A unique port identifier for the final destination of the packet.
4668 * Access: RW
4669 */
4670MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
4671
4672/* reg_mpat_e
4673 * Enable. Indicating the Port Analyzer is enabled.
4674 * Access: RW
4675 */
4676MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
4677
4678/* reg_mpat_qos
4679 * Quality Of Service Mode.
4680 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
4681 * PCP, DEI, DSCP or VL) are configured.
4682 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
4683 * same as in the original packet that has triggered the mirroring. For
4684 * SPAN also the pcp,dei are maintained.
4685 * Access: RW
4686 */
4687MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
4688
23019054
YG		 4689/* reg_mpat_be
4690 * Best effort mode. Indicates mirroring traffic should not cause packet
4691 * drop or back pressure, but will discard the mirrored packets. Mirrored
4692 * packets will be forwarded on a best effort manner.
4693 * 0: Do not discard mirrored packets
4694 * 1: Discard mirrored packets if causing congestion
4695 * Access: RW
4696 */
4697MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
4698
43a46856
YG		 4699static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
4700 u16 system_port, bool e)
4701{
4702 MLXSW_REG_ZERO(mpat, payload);
4703 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
4704 mlxsw_reg_mpat_system_port_set(payload, system_port);
4705 mlxsw_reg_mpat_e_set(payload, e);
4706 mlxsw_reg_mpat_qos_set(payload, 1);
23019054
YG		 4707 mlxsw_reg_mpat_be_set(payload, 1);
4708}
4709
4710/* MPAR - Monitoring Port Analyzer Register
4711 * ----------------------------------------
4712 * MPAR register is used to query and configure the port analyzer port mirroring
4713 * properties.
4714 */
4715#define MLXSW_REG_MPAR_ID 0x901B
4716#define MLXSW_REG_MPAR_LEN 0x08
4717
4718static const struct mlxsw_reg_info mlxsw_reg_mpar = {
4719 .id = MLXSW_REG_MPAR_ID,
4720 .len = MLXSW_REG_MPAR_LEN,
4721};
4722
4723/* reg_mpar_local_port
4724 * The local port to mirror the packets from.
4725 * Access: Index
4726 */
4727MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
4728
4729enum mlxsw_reg_mpar_i_e {
4730 MLXSW_REG_MPAR_TYPE_EGRESS,
4731 MLXSW_REG_MPAR_TYPE_INGRESS,
4732};
4733
4734/* reg_mpar_i_e
4735 * Ingress/Egress
4736 * Access: Index
4737 */
4738MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
4739
4740/* reg_mpar_enable
4741 * Enable mirroring
4742 * By default, port mirroring is disabled for all ports.
4743 * Access: RW
4744 */
4745MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
4746
4747/* reg_mpar_pa_id
4748 * Port Analyzer ID.
4749 * Access: RW
4750 */
4751MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
4752
4753static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
4754 enum mlxsw_reg_mpar_i_e i_e,
4755 bool enable, u8 pa_id)
4756{
4757 MLXSW_REG_ZERO(mpar, payload);
4758 mlxsw_reg_mpar_local_port_set(payload, local_port);
4759 mlxsw_reg_mpar_enable_set(payload, enable);
4760 mlxsw_reg_mpar_i_e_set(payload, i_e);
4761 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
43a46856
YG		 4762}
4763
3161c159
IS		 4764/* MLCR - Management LED Control Register
4765 * --------------------------------------
4766 * Controls the system LEDs.
4767 */
4768#define MLXSW_REG_MLCR_ID 0x902B
4769#define MLXSW_REG_MLCR_LEN 0x0C
4770
4771static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
4772 .id = MLXSW_REG_MLCR_ID,
4773 .len = MLXSW_REG_MLCR_LEN,
4774};
4775
4776/* reg_mlcr_local_port
4777 * Local port number.
4778 * Access: RW
4779 */
4780MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
4781
4782#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
4783
4784/* reg_mlcr_beacon_duration
4785 * Duration of the beacon to be active, in seconds.
4786 * 0x0 - Will turn off the beacon.
4787 * 0xFFFF - Will turn on the beacon until explicitly turned off.
4788 * Access: RW
4789 */
4790MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
4791
4792/* reg_mlcr_beacon_remain
4793 * Remaining duration of the beacon, in seconds.
4794 * 0xFFFF indicates an infinite amount of time.
4795 * Access: RO
4796 */
4797MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
4798
4799static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
4800 bool active)
4801{
4802 MLXSW_REG_ZERO(mlcr, payload);
4803 mlxsw_reg_mlcr_local_port_set(payload, local_port);
4804 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
4805 MLXSW_REG_MLCR_DURATION_MAX : 0);
4806}
4807
e0594369
JP		 4808/* SBPR - Shared Buffer Pools Register
4809 * -----------------------------------
4810 * The SBPR configures and retrieves the shared buffer pools and configuration.
4811 */
4812#define MLXSW_REG_SBPR_ID 0xB001
4813#define MLXSW_REG_SBPR_LEN 0x14
4814
4815static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
4816 .id = MLXSW_REG_SBPR_ID,
4817 .len = MLXSW_REG_SBPR_LEN,
4818};
4819
497e8592
JP		 4820/* shared direstion enum for SBPR, SBCM, SBPM */
4821enum mlxsw_reg_sbxx_dir {
4822 MLXSW_REG_SBXX_DIR_INGRESS,
4823 MLXSW_REG_SBXX_DIR_EGRESS,
e0594369
JP		 4824};
4825
4826/* reg_sbpr_dir
4827 * Direction.
4828 * Access: Index
4829 */
4830MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
4831
4832/* reg_sbpr_pool
4833 * Pool index.
4834 * Access: Index
4835 */
4836MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
4837
4838/* reg_sbpr_size
4839 * Pool size in buffer cells.
4840 * Access: RW
4841 */
4842MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
4843
4844enum mlxsw_reg_sbpr_mode {
4845 MLXSW_REG_SBPR_MODE_STATIC,
4846 MLXSW_REG_SBPR_MODE_DYNAMIC,
4847};
4848
4849/* reg_sbpr_mode
4850 * Pool quota calculation mode.
4851 * Access: RW
4852 */
4853MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
4854
4855static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
497e8592 4856 enum mlxsw_reg_sbxx_dir dir,
e0594369
JP		 4857 enum mlxsw_reg_sbpr_mode mode, u32 size)
4858{
4859 MLXSW_REG_ZERO(sbpr, payload);
4860 mlxsw_reg_sbpr_pool_set(payload, pool);
4861 mlxsw_reg_sbpr_dir_set(payload, dir);
4862 mlxsw_reg_sbpr_mode_set(payload, mode);
4863 mlxsw_reg_sbpr_size_set(payload, size);
4864}
4865
4866/* SBCM - Shared Buffer Class Management Register
4867 * ----------------------------------------------
4868 * The SBCM register configures and retrieves the shared buffer allocation
4869 * and configuration according to Port-PG, including the binding to pool
4870 * and definition of the associated quota.
4871 */
4872#define MLXSW_REG_SBCM_ID 0xB002
4873#define MLXSW_REG_SBCM_LEN 0x28
4874
4875static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
4876 .id = MLXSW_REG_SBCM_ID,
4877 .len = MLXSW_REG_SBCM_LEN,
4878};
4879
4880/* reg_sbcm_local_port
4881 * Local port number.
4882 * For Ingress: excludes CPU port and Router port
4883 * For Egress: excludes IP Router
4884 * Access: Index
4885 */
4886MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
4887
4888/* reg_sbcm_pg_buff
4889 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
4890 * For PG buffer: range is 0..cap_max_pg_buffers - 1
4891 * For traffic class: range is 0..cap_max_tclass - 1
4892 * Note that when traffic class is in MC aware mode then the traffic
4893 * classes which are MC aware cannot be configured.
4894 * Access: Index
4895 */
4896MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
4897
e0594369
JP		 4898/* reg_sbcm_dir
4899 * Direction.
4900 * Access: Index
4901 */
4902MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
4903
4904/* reg_sbcm_min_buff
4905 * Minimum buffer size for the limiter, in cells.
4906 * Access: RW
4907 */
4908MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
4909
c30a53c7
JP		 4910/* shared max_buff limits for dynamic threshold for SBCM, SBPM */
4911#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
4912#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
4913
e0594369
JP		 4914/* reg_sbcm_max_buff
4915 * When the pool associated to the port-pg/tclass is configured to
4916 * static, Maximum buffer size for the limiter configured in cells.
4917 * When the pool associated to the port-pg/tclass is configured to
4918 * dynamic, the max_buff holds the "alpha" parameter, supporting
4919 * the following values:
4920 * 0: 0
4921 * i: (1/128)*2^(i-1), for i=1..14
4922 * 0xFF: Infinity
4923 * Access: RW
4924 */
4925MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
4926
4927/* reg_sbcm_pool
4928 * Association of the port-priority to a pool.
4929 * Access: RW
4930 */
4931MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
4932
4933static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
497e8592 4934 enum mlxsw_reg_sbxx_dir dir,
e0594369
JP		 4935 u32 min_buff, u32 max_buff, u8 pool)
4936{
4937 MLXSW_REG_ZERO(sbcm, payload);
4938 mlxsw_reg_sbcm_local_port_set(payload, local_port);
4939 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
4940 mlxsw_reg_sbcm_dir_set(payload, dir);
4941 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
4942 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
4943 mlxsw_reg_sbcm_pool_set(payload, pool);
4944}
4945
9efc8f65
JP		 4946/* SBPM - Shared Buffer Port Management Register
4947 * ---------------------------------------------
e0594369
JP		 4948 * The SBPM register configures and retrieves the shared buffer allocation
4949 * and configuration according to Port-Pool, including the definition
4950 * of the associated quota.
4951 */
4952#define MLXSW_REG_SBPM_ID 0xB003
4953#define MLXSW_REG_SBPM_LEN 0x28
4954
4955static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
4956 .id = MLXSW_REG_SBPM_ID,
4957 .len = MLXSW_REG_SBPM_LEN,
4958};
4959
4960/* reg_sbpm_local_port
4961 * Local port number.
4962 * For Ingress: excludes CPU port and Router port
4963 * For Egress: excludes IP Router
4964 * Access: Index
4965 */
4966MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
4967
4968/* reg_sbpm_pool
4969 * The pool associated to quota counting on the local_port.
4970 * Access: Index
4971 */
4972MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
4973
e0594369
JP		 4974/* reg_sbpm_dir
4975 * Direction.
4976 * Access: Index
4977 */
4978MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
4979
42a7f1d7
JP		 4980/* reg_sbpm_buff_occupancy
4981 * Current buffer occupancy in cells.
4982 * Access: RO
4983 */
4984MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
4985
4986/* reg_sbpm_clr
4987 * Clear Max Buffer Occupancy
4988 * When this bit is set, max_buff_occupancy field is cleared (and a
4989 * new max value is tracked from the time the clear was performed).
4990 * Access: OP
4991 */
4992MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
4993
4994/* reg_sbpm_max_buff_occupancy
4995 * Maximum value of buffer occupancy in cells monitored. Cleared by
4996 * writing to the clr field.
4997 * Access: RO
4998 */
4999MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
5000
e0594369
JP		 5001/* reg_sbpm_min_buff
5002 * Minimum buffer size for the limiter, in cells.
5003 * Access: RW
5004 */
5005MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
5006
5007/* reg_sbpm_max_buff
5008 * When the pool associated to the port-pg/tclass is configured to
5009 * static, Maximum buffer size for the limiter configured in cells.
5010 * When the pool associated to the port-pg/tclass is configured to
5011 * dynamic, the max_buff holds the "alpha" parameter, supporting
5012 * the following values:
5013 * 0: 0
5014 * i: (1/128)*2^(i-1), for i=1..14
5015 * 0xFF: Infinity
5016 * Access: RW
5017 */
5018MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
5019
5020static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
42a7f1d7 5021 enum mlxsw_reg_sbxx_dir dir, bool clr,
e0594369
JP		 5022 u32 min_buff, u32 max_buff)
5023{
5024 MLXSW_REG_ZERO(sbpm, payload);
5025 mlxsw_reg_sbpm_local_port_set(payload, local_port);
5026 mlxsw_reg_sbpm_pool_set(payload, pool);
5027 mlxsw_reg_sbpm_dir_set(payload, dir);
42a7f1d7 5028 mlxsw_reg_sbpm_clr_set(payload, clr);
e0594369
JP		 5029 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
5030 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
5031}
5032
42a7f1d7
JP		 5033static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
5034 u32 *p_max_buff_occupancy)
5035{
5036 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
5037 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
5038}
5039
e0594369
JP		 5040/* SBMM - Shared Buffer Multicast Management Register
5041 * --------------------------------------------------
5042 * The SBMM register configures and retrieves the shared buffer allocation
5043 * and configuration for MC packets according to Switch-Priority, including
5044 * the binding to pool and definition of the associated quota.
5045 */
5046#define MLXSW_REG_SBMM_ID 0xB004
5047#define MLXSW_REG_SBMM_LEN 0x28
5048
5049static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
5050 .id = MLXSW_REG_SBMM_ID,
5051 .len = MLXSW_REG_SBMM_LEN,
5052};
5053
5054/* reg_sbmm_prio
5055 * Switch Priority.
5056 * Access: Index
5057 */
5058MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
5059
5060/* reg_sbmm_min_buff
5061 * Minimum buffer size for the limiter, in cells.
5062 * Access: RW
5063 */
5064MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
5065
5066/* reg_sbmm_max_buff
5067 * When the pool associated to the port-pg/tclass is configured to
5068 * static, Maximum buffer size for the limiter configured in cells.
5069 * When the pool associated to the port-pg/tclass is configured to
5070 * dynamic, the max_buff holds the "alpha" parameter, supporting
5071 * the following values:
5072 * 0: 0
5073 * i: (1/128)*2^(i-1), for i=1..14
5074 * 0xFF: Infinity
5075 * Access: RW
5076 */
5077MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
5078
5079/* reg_sbmm_pool
5080 * Association of the port-priority to a pool.
5081 * Access: RW
5082 */
5083MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
5084
5085static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
5086 u32 max_buff, u8 pool)
5087{
5088 MLXSW_REG_ZERO(sbmm, payload);
5089 mlxsw_reg_sbmm_prio_set(payload, prio);
5090 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
5091 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
5092 mlxsw_reg_sbmm_pool_set(payload, pool);
5093}
5094
26176def
JP		 5095/* SBSR - Shared Buffer Status Register
5096 * ------------------------------------
5097 * The SBSR register retrieves the shared buffer occupancy according to
5098 * Port-Pool. Note that this register enables reading a large amount of data.
5099 * It is the user's responsibility to limit the amount of data to ensure the
5100 * response can match the maximum transfer unit. In case the response exceeds
5101 * the maximum transport unit, it will be truncated with no special notice.
5102 */
5103#define MLXSW_REG_SBSR_ID 0xB005
5104#define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
5105#define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
5106#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
5107#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
5108 MLXSW_REG_SBSR_REC_LEN * \
5109 MLXSW_REG_SBSR_REC_MAX_COUNT)
5110
5111static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
5112 .id = MLXSW_REG_SBSR_ID,
5113 .len = MLXSW_REG_SBSR_LEN,
5114};
5115
5116/* reg_sbsr_clr
5117 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
5118 * field is cleared (and a new max value is tracked from the time the clear
5119 * was performed).
5120 * Access: OP
5121 */
5122MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
5123
5124/* reg_sbsr_ingress_port_mask
5125 * Bit vector for all ingress network ports.
5126 * Indicates which of the ports (for which the relevant bit is set)
5127 * are affected by the set operation. Configuration of any other port
5128 * does not change.
5129 * Access: Index
5130 */
5131MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
5132
5133/* reg_sbsr_pg_buff_mask
5134 * Bit vector for all switch priority groups.
5135 * Indicates which of the priorities (for which the relevant bit is set)
5136 * are affected by the set operation. Configuration of any other priority
5137 * does not change.
5138 * Range is 0..cap_max_pg_buffers - 1
5139 * Access: Index
5140 */
5141MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
5142
5143/* reg_sbsr_egress_port_mask
5144 * Bit vector for all egress network ports.
5145 * Indicates which of the ports (for which the relevant bit is set)
5146 * are affected by the set operation. Configuration of any other port
5147 * does not change.
5148 * Access: Index
5149 */
5150MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
5151
5152/* reg_sbsr_tclass_mask
5153 * Bit vector for all traffic classes.
5154 * Indicates which of the traffic classes (for which the relevant bit is
5155 * set) are affected by the set operation. Configuration of any other
5156 * traffic class does not change.
5157 * Range is 0..cap_max_tclass - 1
5158 * Access: Index
5159 */
5160MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
5161
5162static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
5163{
5164 MLXSW_REG_ZERO(sbsr, payload);
5165 mlxsw_reg_sbsr_clr_set(payload, clr);
5166}
5167
5168/* reg_sbsr_rec_buff_occupancy
5169 * Current buffer occupancy in cells.
5170 * Access: RO
5171 */
5172MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5173 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
5174
5175/* reg_sbsr_rec_max_buff_occupancy
5176 * Maximum value of buffer occupancy in cells monitored. Cleared by
5177 * writing to the clr field.
5178 * Access: RO
5179 */
5180MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5181 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
5182
5183static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
5184 u32 *p_buff_occupancy,
5185 u32 *p_max_buff_occupancy)
5186{
5187 *p_buff_occupancy =
5188 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
5189 *p_max_buff_occupancy =
5190 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
5191}
5192
51ae8cc6
YG		 5193/* SBIB - Shared Buffer Internal Buffer Register
5194 * ---------------------------------------------
5195 * The SBIB register configures per port buffers for internal use. The internal
5196 * buffers consume memory on the port buffers (note that the port buffers are
5197 * used also by PBMC).
5198 *
5199 * For Spectrum this is used for egress mirroring.
5200 */
5201#define MLXSW_REG_SBIB_ID 0xB006
5202#define MLXSW_REG_SBIB_LEN 0x10
5203
5204static const struct mlxsw_reg_info mlxsw_reg_sbib = {
5205 .id = MLXSW_REG_SBIB_ID,
5206 .len = MLXSW_REG_SBIB_LEN,
5207};
5208
5209/* reg_sbib_local_port
5210 * Local port number
5211 * Not supported for CPU port and router port
5212 * Access: Index
5213 */
5214MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
5215
5216/* reg_sbib_buff_size
5217 * Units represented in cells
5218 * Allowed range is 0 to (cap_max_headroom_size - 1)
5219 * Default is 0
5220 * Access: RW
5221 */
5222MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
5223
5224static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
5225 u32 buff_size)
5226{
5227 MLXSW_REG_ZERO(sbib, payload);
5228 mlxsw_reg_sbib_local_port_set(payload, local_port);
5229 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
5230}
5231
4ec14b76
IS		 5232static inline const char *mlxsw_reg_id_str(u16 reg_id)
5233{
5234 switch (reg_id) {
5235 case MLXSW_REG_SGCR_ID:
5236 return "SGCR";
5237 case MLXSW_REG_SPAD_ID:
5238 return "SPAD";
fabe5483
ER		 5239 case MLXSW_REG_SMID_ID:
5240 return "SMID";
e61011b5
IS		 5241 case MLXSW_REG_SSPR_ID:
5242 return "SSPR";
e534a56a
JP		 5243 case MLXSW_REG_SFDAT_ID:
5244 return "SFDAT";
236033b3
JP		 5245 case MLXSW_REG_SFD_ID:
5246 return "SFD";
f5d88f58
JP		 5247 case MLXSW_REG_SFN_ID:
5248 return "SFN";
4ec14b76
IS		 5249 case MLXSW_REG_SPMS_ID:
5250 return "SPMS";
b2e345f9
ER		 5251 case MLXSW_REG_SPVID_ID:
5252 return "SPVID";
5253 case MLXSW_REG_SPVM_ID:
5254 return "SPVM";
148f472d
IS		 5255 case MLXSW_REG_SPAFT_ID:
5256 return "SPAFT";
4ec14b76
IS		 5257 case MLXSW_REG_SFGC_ID:
5258 return "SFGC";
5259 case MLXSW_REG_SFTR_ID:
5260 return "SFTR";
41933271
IS		 5261 case MLXSW_REG_SFDF_ID:
5262 return "SFDF";
d1d40be0
JP		 5263 case MLXSW_REG_SLDR_ID:
5264 return "SLDR";
5265 case MLXSW_REG_SLCR_ID:
5266 return "SLCR";
5267 case MLXSW_REG_SLCOR_ID:
5268 return "SLCOR";
4ec14b76
IS		 5269 case MLXSW_REG_SPMLR_ID:
5270 return "SPMLR";
64790239
IS		 5271 case MLXSW_REG_SVFA_ID:
5272 return "SVFA";
1f65da74
IS		 5273 case MLXSW_REG_SVPE_ID:
5274 return "SVPE";
f1fb693a
IS		 5275 case MLXSW_REG_SFMR_ID:
5276 return "SFMR";
a4feea74
IS		 5277 case MLXSW_REG_SPVMLR_ID:
5278 return "SPVMLR";
2c63a555
IS		 5279 case MLXSW_REG_QTCT_ID:
5280 return "QTCT";
b9b7cee4
IS		 5281 case MLXSW_REG_QEEC_ID:
5282 return "QEEC";
4ec14b76
IS		 5283 case MLXSW_REG_PMLP_ID:
5284 return "PMLP";
5285 case MLXSW_REG_PMTU_ID:
5286 return "PMTU";
5287 case MLXSW_REG_PTYS_ID:
5288 return "PTYS";
5289 case MLXSW_REG_PPAD_ID:
5290 return "PPAD";
5291 case MLXSW_REG_PAOS_ID:
5292 return "PAOS";
6f253d83
IS		 5293 case MLXSW_REG_PFCC_ID:
5294 return "PFCC";
4ec14b76
IS		 5295 case MLXSW_REG_PPCNT_ID:
5296 return "PPCNT";
b98ff151
IS		 5297 case MLXSW_REG_PPTB_ID:
5298 return "PPTB";
e0594369
JP		 5299 case MLXSW_REG_PBMC_ID:
5300 return "PBMC";
4ec14b76
IS		 5301 case MLXSW_REG_PSPA_ID:
5302 return "PSPA";
5303 case MLXSW_REG_HTGT_ID:
5304 return "HTGT";
5305 case MLXSW_REG_HPKT_ID:
5306 return "HPKT";
69c407aa
IS		 5307 case MLXSW_REG_RGCR_ID:
5308 return "RGCR";
3dc26689
IS		 5309 case MLXSW_REG_RITR_ID:
5310 return "RITR";
089f9816
YG		 5311 case MLXSW_REG_RATR_ID:
5312 return "RATR";
6f9fc3ce
JP		 5313 case MLXSW_REG_RALTA_ID:
5314 return "RALTA";
a9823359
JP		 5315 case MLXSW_REG_RALST_ID:
5316 return "RALST";
20ae4053
JP		 5317 case MLXSW_REG_RALTB_ID:
5318 return "RALTB";
d5a1c749
JP		 5319 case MLXSW_REG_RALUE_ID:
5320 return "RALUE";
4457b3df
YG		 5321 case MLXSW_REG_RAUHT_ID:
5322 return "RAUHT";
a59f0b31
JP		 5323 case MLXSW_REG_RALEU_ID:
5324 return "RALEU";
7cf2c205
YG		 5325 case MLXSW_REG_RAUHTD_ID:
5326 return "RAUHTD";
5246f2e2
JP		 5327 case MLXSW_REG_MFCR_ID:
5328 return "MFCR";
5329 case MLXSW_REG_MFSC_ID:
5330 return "MFSC";
5331 case MLXSW_REG_MFSM_ID:
5332 return "MFSM";
85926f87
JP		 5333 case MLXSW_REG_MTCAP_ID:
5334 return "MTCAP";
43a46856
YG		 5335 case MLXSW_REG_MPAT_ID:
5336 return "MPAT";
23019054
YG		 5337 case MLXSW_REG_MPAR_ID:
5338 return "MPAR";
85926f87
JP		 5339 case MLXSW_REG_MTMP_ID:
5340 return "MTMP";
3161c159
IS		 5341 case MLXSW_REG_MLCR_ID:
5342 return "MLCR";
e0594369
JP		 5343 case MLXSW_REG_SBPR_ID:
5344 return "SBPR";
5345 case MLXSW_REG_SBCM_ID:
5346 return "SBCM";
5347 case MLXSW_REG_SBPM_ID:
5348 return "SBPM";
5349 case MLXSW_REG_SBMM_ID:
5350 return "SBMM";
26176def
JP		 5351 case MLXSW_REG_SBSR_ID:
5352 return "SBSR";
51ae8cc6
YG		 5353 case MLXSW_REG_SBIB_ID:
5354 return "SBIB";
4ec14b76
IS		 5355 default:
5356 return "*UNKNOWN*";
5357 }
5358}
5359
5360/* PUDE - Port Up / Down Event
5361 * ---------------------------
5362 * Reports the operational state change of a port.
5363 */
5364#define MLXSW_REG_PUDE_LEN 0x10
5365
5366/* reg_pude_swid
5367 * Switch partition ID with which to associate the port.
5368 * Access: Index
5369 */
5370MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
5371
5372/* reg_pude_local_port
5373 * Local port number.
5374 * Access: Index
5375 */
5376MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
5377
5378/* reg_pude_admin_status
5379 * Port administrative state (the desired state).
5380 * 1 - Up.
5381 * 2 - Down.
5382 * 3 - Up once. This means that in case of link failure, the port won't go
5383 * into polling mode, but will wait to be re-enabled by software.
5384 * 4 - Disabled by system. Can only be set by hardware.
5385 * Access: RO
5386 */
5387MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
5388
5389/* reg_pude_oper_status
5390 * Port operatioanl state.
5391 * 1 - Up.
5392 * 2 - Down.
5393 * 3 - Down by port failure. This means that the device will not let the
5394 * port up again until explicitly specified by software.
5395 * Access: RO
5396 */
5397MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
5398
5399#endif
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