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9948a064 JP |
1 | /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ |
2 | /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ | |
4ec14b76 IS |
3 | |
4 | #ifndef _MLXSW_REG_H | |
5 | #define _MLXSW_REG_H | |
6 | ||
3390787b | 7 | #include <linux/kernel.h> |
4ec14b76 IS |
8 | #include <linux/string.h> |
9 | #include <linux/bitops.h> | |
10 | #include <linux/if_vlan.h> | |
11 | ||
12 | #include "item.h" | |
13 | #include "port.h" | |
14 | ||
15 | struct mlxsw_reg_info { | |
16 | u16 id; | |
17 | u16 len; /* In u8 */ | |
8e9658d5 | 18 | const char *name; |
4ec14b76 IS |
19 | }; |
20 | ||
21978dcf JP |
21 | #define MLXSW_REG_DEFINE(_name, _id, _len) \ |
22 | static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ | |
23 | .id = _id, \ | |
24 | .len = _len, \ | |
8e9658d5 | 25 | .name = #_name, \ |
21978dcf JP |
26 | } |
27 | ||
4ec14b76 IS |
28 | #define MLXSW_REG(type) (&mlxsw_reg_##type) |
29 | #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len | |
30 | #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) | |
31 | ||
32 | /* SGCR - Switch General Configuration Register | |
33 | * -------------------------------------------- | |
34 | * This register is used for configuration of the switch capabilities. | |
35 | */ | |
36 | #define MLXSW_REG_SGCR_ID 0x2000 | |
37 | #define MLXSW_REG_SGCR_LEN 0x10 | |
38 | ||
21978dcf | 39 | MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); |
4ec14b76 IS |
40 | |
41 | /* reg_sgcr_llb | |
42 | * Link Local Broadcast (Default=0) | |
43 | * When set, all Link Local packets (224.0.0.X) will be treated as broadcast | |
44 | * packets and ignore the IGMP snooping entries. | |
45 | * Access: RW | |
46 | */ | |
47 | MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); | |
48 | ||
49 | static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) | |
50 | { | |
51 | MLXSW_REG_ZERO(sgcr, payload); | |
52 | mlxsw_reg_sgcr_llb_set(payload, !!llb); | |
53 | } | |
54 | ||
55 | /* SPAD - Switch Physical Address Register | |
56 | * --------------------------------------- | |
57 | * The SPAD register configures the switch physical MAC address. | |
58 | */ | |
59 | #define MLXSW_REG_SPAD_ID 0x2002 | |
60 | #define MLXSW_REG_SPAD_LEN 0x10 | |
61 | ||
21978dcf | 62 | MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); |
4ec14b76 IS |
63 | |
64 | /* reg_spad_base_mac | |
65 | * Base MAC address for the switch partitions. | |
66 | * Per switch partition MAC address is equal to: | |
67 | * base_mac + swid | |
68 | * Access: RW | |
69 | */ | |
70 | MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); | |
71 | ||
fabe5483 ER |
72 | /* SMID - Switch Multicast ID |
73 | * -------------------------- | |
74 | * The MID record maps from a MID (Multicast ID), which is a unique identifier | |
75 | * of the multicast group within the stacking domain, into a list of local | |
76 | * ports into which the packet is replicated. | |
77 | */ | |
78 | #define MLXSW_REG_SMID_ID 0x2007 | |
79 | #define MLXSW_REG_SMID_LEN 0x240 | |
80 | ||
21978dcf | 81 | MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); |
fabe5483 ER |
82 | |
83 | /* reg_smid_swid | |
84 | * Switch partition ID. | |
85 | * Access: Index | |
86 | */ | |
87 | MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); | |
88 | ||
89 | /* reg_smid_mid | |
90 | * Multicast identifier - global identifier that represents the multicast group | |
91 | * across all devices. | |
92 | * Access: Index | |
93 | */ | |
94 | MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); | |
95 | ||
96 | /* reg_smid_port | |
97 | * Local port memebership (1 bit per port). | |
98 | * Access: RW | |
99 | */ | |
100 | MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); | |
101 | ||
102 | /* reg_smid_port_mask | |
103 | * Local port mask (1 bit per port). | |
104 | * Access: W | |
105 | */ | |
106 | MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); | |
107 | ||
108 | static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, | |
109 | u8 port, bool set) | |
110 | { | |
111 | MLXSW_REG_ZERO(smid, payload); | |
112 | mlxsw_reg_smid_swid_set(payload, 0); | |
113 | mlxsw_reg_smid_mid_set(payload, mid); | |
114 | mlxsw_reg_smid_port_set(payload, port, set); | |
115 | mlxsw_reg_smid_port_mask_set(payload, port, 1); | |
116 | } | |
117 | ||
e61011b5 IS |
118 | /* SSPR - Switch System Port Record Register |
119 | * ----------------------------------------- | |
120 | * Configures the system port to local port mapping. | |
121 | */ | |
122 | #define MLXSW_REG_SSPR_ID 0x2008 | |
123 | #define MLXSW_REG_SSPR_LEN 0x8 | |
124 | ||
21978dcf | 125 | MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); |
e61011b5 IS |
126 | |
127 | /* reg_sspr_m | |
128 | * Master - if set, then the record describes the master system port. | |
129 | * This is needed in case a local port is mapped into several system ports | |
130 | * (for multipathing). That number will be reported as the source system | |
131 | * port when packets are forwarded to the CPU. Only one master port is allowed | |
132 | * per local port. | |
133 | * | |
134 | * Note: Must be set for Spectrum. | |
135 | * Access: RW | |
136 | */ | |
137 | MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); | |
138 | ||
139 | /* reg_sspr_local_port | |
140 | * Local port number. | |
141 | * | |
142 | * Access: RW | |
143 | */ | |
144 | MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); | |
145 | ||
146 | /* reg_sspr_sub_port | |
147 | * Virtual port within the physical port. | |
148 | * Should be set to 0 when virtual ports are not enabled on the port. | |
149 | * | |
150 | * Access: RW | |
151 | */ | |
152 | MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); | |
153 | ||
154 | /* reg_sspr_system_port | |
155 | * Unique identifier within the stacking domain that represents all the ports | |
156 | * that are available in the system (external ports). | |
157 | * | |
158 | * Currently, only single-ASIC configurations are supported, so we default to | |
159 | * 1:1 mapping between system ports and local ports. | |
160 | * Access: Index | |
161 | */ | |
162 | MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); | |
163 | ||
164 | static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) | |
165 | { | |
166 | MLXSW_REG_ZERO(sspr, payload); | |
167 | mlxsw_reg_sspr_m_set(payload, 1); | |
168 | mlxsw_reg_sspr_local_port_set(payload, local_port); | |
169 | mlxsw_reg_sspr_sub_port_set(payload, 0); | |
170 | mlxsw_reg_sspr_system_port_set(payload, local_port); | |
171 | } | |
172 | ||
e534a56a JP |
173 | /* SFDAT - Switch Filtering Database Aging Time |
174 | * -------------------------------------------- | |
175 | * Controls the Switch aging time. Aging time is able to be set per Switch | |
176 | * Partition. | |
177 | */ | |
178 | #define MLXSW_REG_SFDAT_ID 0x2009 | |
179 | #define MLXSW_REG_SFDAT_LEN 0x8 | |
180 | ||
21978dcf | 181 | MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); |
e534a56a JP |
182 | |
183 | /* reg_sfdat_swid | |
184 | * Switch partition ID. | |
185 | * Access: Index | |
186 | */ | |
187 | MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); | |
188 | ||
189 | /* reg_sfdat_age_time | |
190 | * Aging time in seconds | |
191 | * Min - 10 seconds | |
192 | * Max - 1,000,000 seconds | |
193 | * Default is 300 seconds. | |
194 | * Access: RW | |
195 | */ | |
196 | MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); | |
197 | ||
198 | static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) | |
199 | { | |
200 | MLXSW_REG_ZERO(sfdat, payload); | |
201 | mlxsw_reg_sfdat_swid_set(payload, 0); | |
202 | mlxsw_reg_sfdat_age_time_set(payload, age_time); | |
203 | } | |
204 | ||
236033b3 JP |
205 | /* SFD - Switch Filtering Database |
206 | * ------------------------------- | |
207 | * The following register defines the access to the filtering database. | |
208 | * The register supports querying, adding, removing and modifying the database. | |
209 | * The access is optimized for bulk updates in which case more than one | |
210 | * FDB record is present in the same command. | |
211 | */ | |
212 | #define MLXSW_REG_SFD_ID 0x200A | |
213 | #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ | |
214 | #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ | |
215 | #define MLXSW_REG_SFD_REC_MAX_COUNT 64 | |
216 | #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ | |
217 | MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) | |
218 | ||
21978dcf | 219 | MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); |
236033b3 JP |
220 | |
221 | /* reg_sfd_swid | |
222 | * Switch partition ID for queries. Reserved on Write. | |
223 | * Access: Index | |
224 | */ | |
225 | MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); | |
226 | ||
227 | enum mlxsw_reg_sfd_op { | |
228 | /* Dump entire FDB a (process according to record_locator) */ | |
229 | MLXSW_REG_SFD_OP_QUERY_DUMP = 0, | |
230 | /* Query records by {MAC, VID/FID} value */ | |
231 | MLXSW_REG_SFD_OP_QUERY_QUERY = 1, | |
232 | /* Query and clear activity. Query records by {MAC, VID/FID} value */ | |
233 | MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, | |
234 | /* Test. Response indicates if each of the records could be | |
235 | * added to the FDB. | |
236 | */ | |
237 | MLXSW_REG_SFD_OP_WRITE_TEST = 0, | |
238 | /* Add/modify. Aged-out records cannot be added. This command removes | |
239 | * the learning notification of the {MAC, VID/FID}. Response includes | |
240 | * the entries that were added to the FDB. | |
241 | */ | |
242 | MLXSW_REG_SFD_OP_WRITE_EDIT = 1, | |
243 | /* Remove record by {MAC, VID/FID}. This command also removes | |
244 | * the learning notification and aged-out notifications | |
245 | * of the {MAC, VID/FID}. The response provides current (pre-removal) | |
246 | * entries as non-aged-out. | |
247 | */ | |
248 | MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, | |
249 | /* Remove learned notification by {MAC, VID/FID}. The response provides | |
250 | * the removed learning notification. | |
251 | */ | |
252 | MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, | |
253 | }; | |
254 | ||
255 | /* reg_sfd_op | |
256 | * Operation. | |
257 | * Access: OP | |
258 | */ | |
259 | MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); | |
260 | ||
261 | /* reg_sfd_record_locator | |
262 | * Used for querying the FDB. Use record_locator=0 to initiate the | |
263 | * query. When a record is returned, a new record_locator is | |
264 | * returned to be used in the subsequent query. | |
265 | * Reserved for database update. | |
266 | * Access: Index | |
267 | */ | |
268 | MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); | |
269 | ||
270 | /* reg_sfd_num_rec | |
271 | * Request: Number of records to read/add/modify/remove | |
272 | * Response: Number of records read/added/replaced/removed | |
273 | * See above description for more details. | |
274 | * Ranges 0..64 | |
275 | * Access: RW | |
276 | */ | |
277 | MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); | |
278 | ||
279 | static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, | |
280 | u32 record_locator) | |
281 | { | |
282 | MLXSW_REG_ZERO(sfd, payload); | |
283 | mlxsw_reg_sfd_op_set(payload, op); | |
284 | mlxsw_reg_sfd_record_locator_set(payload, record_locator); | |
285 | } | |
286 | ||
287 | /* reg_sfd_rec_swid | |
288 | * Switch partition ID. | |
289 | * Access: Index | |
290 | */ | |
291 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, | |
292 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
293 | ||
294 | enum mlxsw_reg_sfd_rec_type { | |
295 | MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, | |
e4bfbae2 | 296 | MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, |
5230b25f | 297 | MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, |
0933781f | 298 | MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, |
236033b3 JP |
299 | }; |
300 | ||
301 | /* reg_sfd_rec_type | |
302 | * FDB record type. | |
303 | * Access: RW | |
304 | */ | |
305 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, | |
306 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
307 | ||
308 | enum mlxsw_reg_sfd_rec_policy { | |
309 | /* Replacement disabled, aging disabled. */ | |
310 | MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, | |
311 | /* (mlag remote): Replacement enabled, aging disabled, | |
312 | * learning notification enabled on this port. | |
313 | */ | |
314 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, | |
315 | /* (ingress device): Replacement enabled, aging enabled. */ | |
316 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, | |
317 | }; | |
318 | ||
319 | /* reg_sfd_rec_policy | |
320 | * Policy. | |
321 | * Access: RW | |
322 | */ | |
323 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, | |
324 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
325 | ||
326 | /* reg_sfd_rec_a | |
327 | * Activity. Set for new static entries. Set for static entries if a frame SMAC | |
328 | * lookup hits on the entry. | |
329 | * To clear the a bit, use "query and clear activity" op. | |
330 | * Access: RO | |
331 | */ | |
332 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, | |
333 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
334 | ||
335 | /* reg_sfd_rec_mac | |
336 | * MAC address. | |
337 | * Access: Index | |
338 | */ | |
339 | MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, | |
340 | MLXSW_REG_SFD_REC_LEN, 0x02); | |
341 | ||
342 | enum mlxsw_reg_sfd_rec_action { | |
343 | /* forward */ | |
344 | MLXSW_REG_SFD_REC_ACTION_NOP = 0, | |
345 | /* forward and trap, trap_id is FDB_TRAP */ | |
346 | MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, | |
347 | /* trap and do not forward, trap_id is FDB_TRAP */ | |
d82d8c06 IS |
348 | MLXSW_REG_SFD_REC_ACTION_TRAP = 2, |
349 | /* forward to IP router */ | |
350 | MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, | |
236033b3 JP |
351 | MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, |
352 | }; | |
353 | ||
354 | /* reg_sfd_rec_action | |
355 | * Action to apply on the packet. | |
356 | * Note: Dynamic entries can only be configured with NOP action. | |
357 | * Access: RW | |
358 | */ | |
359 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, | |
360 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
361 | ||
362 | /* reg_sfd_uc_sub_port | |
4e9ec083 JP |
363 | * VEPA channel on local port. |
364 | * Valid only if local port is a non-stacking port. Must be 0 if multichannel | |
365 | * VEPA is not enabled. | |
236033b3 JP |
366 | * Access: RW |
367 | */ | |
368 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, | |
369 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
370 | ||
371 | /* reg_sfd_uc_fid_vid | |
372 | * Filtering ID or VLAN ID | |
373 | * For SwitchX and SwitchX-2: | |
374 | * - Dynamic entries (policy 2,3) use FID | |
375 | * - Static entries (policy 0) use VID | |
376 | * - When independent learning is configured, VID=FID | |
377 | * For Spectrum: use FID for both Dynamic and Static entries. | |
378 | * VID should not be used. | |
379 | * Access: Index | |
380 | */ | |
381 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
382 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
383 | ||
384 | /* reg_sfd_uc_system_port | |
385 | * Unique port identifier for the final destination of the packet. | |
386 | * Access: RW | |
387 | */ | |
388 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
389 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
390 | ||
e4bfbae2 JP |
391 | static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, |
392 | enum mlxsw_reg_sfd_rec_type rec_type, | |
e4bfbae2 JP |
393 | const char *mac, |
394 | enum mlxsw_reg_sfd_rec_action action) | |
236033b3 JP |
395 | { |
396 | u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); | |
397 | ||
398 | if (rec_index >= num_rec) | |
399 | mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); | |
400 | mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); | |
e4bfbae2 | 401 | mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); |
236033b3 | 402 | mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); |
e4bfbae2 JP |
403 | mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); |
404 | } | |
405 | ||
406 | static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, | |
407 | enum mlxsw_reg_sfd_rec_policy policy, | |
9de6a80e | 408 | const char *mac, u16 fid_vid, |
e4bfbae2 JP |
409 | enum mlxsw_reg_sfd_rec_action action, |
410 | u8 local_port) | |
411 | { | |
412 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
5230b25f ER |
413 | MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); |
414 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
236033b3 | 415 | mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); |
9de6a80e | 416 | mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); |
236033b3 JP |
417 | mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); |
418 | } | |
419 | ||
75c09280 | 420 | static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, |
9de6a80e | 421 | char *mac, u16 *p_fid_vid, |
75c09280 | 422 | u8 *p_local_port) |
236033b3 JP |
423 | { |
424 | mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); | |
9de6a80e | 425 | *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); |
236033b3 JP |
426 | *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); |
427 | } | |
428 | ||
e4bfbae2 JP |
429 | /* reg_sfd_uc_lag_sub_port |
430 | * LAG sub port. | |
431 | * Must be 0 if multichannel VEPA is not enabled. | |
432 | * Access: RW | |
433 | */ | |
434 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, | |
435 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
436 | ||
437 | /* reg_sfd_uc_lag_fid_vid | |
438 | * Filtering ID or VLAN ID | |
439 | * For SwitchX and SwitchX-2: | |
440 | * - Dynamic entries (policy 2,3) use FID | |
441 | * - Static entries (policy 0) use VID | |
442 | * - When independent learning is configured, VID=FID | |
443 | * For Spectrum: use FID for both Dynamic and Static entries. | |
444 | * VID should not be used. | |
445 | * Access: Index | |
446 | */ | |
447 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
448 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
449 | ||
afd7f979 IS |
450 | /* reg_sfd_uc_lag_lag_vid |
451 | * Indicates VID in case of vFIDs. Reserved for FIDs. | |
452 | * Access: RW | |
453 | */ | |
454 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, | |
455 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
456 | ||
e4bfbae2 JP |
457 | /* reg_sfd_uc_lag_lag_id |
458 | * LAG Identifier - pointer into the LAG descriptor table. | |
459 | * Access: RW | |
460 | */ | |
461 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, | |
462 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
463 | ||
464 | static inline void | |
465 | mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, | |
466 | enum mlxsw_reg_sfd_rec_policy policy, | |
9de6a80e | 467 | const char *mac, u16 fid_vid, |
afd7f979 | 468 | enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, |
e4bfbae2 JP |
469 | u16 lag_id) |
470 | { | |
471 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
472 | MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, | |
5230b25f ER |
473 | mac, action); |
474 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
e4bfbae2 | 475 | mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); |
9de6a80e | 476 | mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); |
afd7f979 | 477 | mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); |
e4bfbae2 JP |
478 | mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); |
479 | } | |
480 | ||
481 | static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, | |
482 | char *mac, u16 *p_vid, | |
483 | u16 *p_lag_id) | |
484 | { | |
485 | mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); | |
486 | *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); | |
487 | *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); | |
488 | } | |
489 | ||
5230b25f ER |
490 | /* reg_sfd_mc_pgi |
491 | * | |
492 | * Multicast port group index - index into the port group table. | |
493 | * Value 0x1FFF indicates the pgi should point to the MID entry. | |
494 | * For Spectrum this value must be set to 0x1FFF | |
495 | * Access: RW | |
496 | */ | |
497 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, | |
498 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
499 | ||
500 | /* reg_sfd_mc_fid_vid | |
501 | * | |
502 | * Filtering ID or VLAN ID | |
503 | * Access: Index | |
504 | */ | |
505 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
506 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
507 | ||
508 | /* reg_sfd_mc_mid | |
509 | * | |
510 | * Multicast identifier - global identifier that represents the multicast | |
511 | * group across all devices. | |
512 | * Access: RW | |
513 | */ | |
514 | MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
515 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
516 | ||
517 | static inline void | |
518 | mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, | |
519 | const char *mac, u16 fid_vid, | |
520 | enum mlxsw_reg_sfd_rec_action action, u16 mid) | |
521 | { | |
522 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
523 | MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); | |
524 | mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); | |
525 | mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); | |
526 | mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); | |
527 | } | |
528 | ||
0933781f IS |
529 | /* reg_sfd_uc_tunnel_uip_msb |
530 | * When protocol is IPv4, the most significant byte of the underlay IPv4 | |
531 | * destination IP. | |
532 | * When protocol is IPv6, reserved. | |
533 | * Access: RW | |
534 | */ | |
535 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, | |
536 | 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
537 | ||
538 | /* reg_sfd_uc_tunnel_fid | |
539 | * Filtering ID. | |
540 | * Access: Index | |
541 | */ | |
542 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
543 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
544 | ||
545 | enum mlxsw_reg_sfd_uc_tunnel_protocol { | |
546 | MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, | |
547 | MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, | |
548 | }; | |
549 | ||
550 | /* reg_sfd_uc_tunnel_protocol | |
551 | * IP protocol. | |
552 | * Access: RW | |
553 | */ | |
554 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, | |
555 | 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
556 | ||
557 | /* reg_sfd_uc_tunnel_uip_lsb | |
558 | * When protocol is IPv4, the least significant bytes of the underlay | |
559 | * IPv4 destination IP. | |
560 | * When protocol is IPv6, pointer to the underlay IPv6 destination IP | |
561 | * which is configured by RIPS. | |
562 | * Access: RW | |
563 | */ | |
564 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, | |
565 | 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
566 | ||
567 | static inline void | |
568 | mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, | |
569 | enum mlxsw_reg_sfd_rec_policy policy, | |
570 | const char *mac, u16 fid, | |
571 | enum mlxsw_reg_sfd_rec_action action, u32 uip, | |
572 | enum mlxsw_reg_sfd_uc_tunnel_protocol proto) | |
573 | { | |
574 | mlxsw_reg_sfd_rec_pack(payload, rec_index, | |
575 | MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, | |
576 | action); | |
577 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
578 | mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); | |
579 | mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); | |
580 | mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); | |
581 | mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); | |
582 | } | |
583 | ||
f5d88f58 JP |
584 | /* SFN - Switch FDB Notification Register |
585 | * ------------------------------------------- | |
586 | * The switch provides notifications on newly learned FDB entries and | |
587 | * aged out entries. The notifications can be polled by software. | |
588 | */ | |
589 | #define MLXSW_REG_SFN_ID 0x200B | |
590 | #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ | |
591 | #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ | |
592 | #define MLXSW_REG_SFN_REC_MAX_COUNT 64 | |
593 | #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ | |
594 | MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) | |
595 | ||
21978dcf | 596 | MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); |
f5d88f58 JP |
597 | |
598 | /* reg_sfn_swid | |
599 | * Switch partition ID. | |
600 | * Access: Index | |
601 | */ | |
602 | MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); | |
603 | ||
1803e0fb IS |
604 | /* reg_sfn_end |
605 | * Forces the current session to end. | |
606 | * Access: OP | |
607 | */ | |
608 | MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); | |
609 | ||
f5d88f58 JP |
610 | /* reg_sfn_num_rec |
611 | * Request: Number of learned notifications and aged-out notification | |
612 | * records requested. | |
613 | * Response: Number of notification records returned (must be smaller | |
614 | * than or equal to the value requested) | |
615 | * Ranges 0..64 | |
616 | * Access: OP | |
617 | */ | |
618 | MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); | |
619 | ||
620 | static inline void mlxsw_reg_sfn_pack(char *payload) | |
621 | { | |
622 | MLXSW_REG_ZERO(sfn, payload); | |
623 | mlxsw_reg_sfn_swid_set(payload, 0); | |
1803e0fb | 624 | mlxsw_reg_sfn_end_set(payload, 1); |
f5d88f58 JP |
625 | mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); |
626 | } | |
627 | ||
628 | /* reg_sfn_rec_swid | |
629 | * Switch partition ID. | |
630 | * Access: RO | |
631 | */ | |
632 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, | |
633 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
634 | ||
635 | enum mlxsw_reg_sfn_rec_type { | |
636 | /* MAC addresses learned on a regular port. */ | |
637 | MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, | |
3b71571c JP |
638 | /* MAC addresses learned on a LAG port. */ |
639 | MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, | |
640 | /* Aged-out MAC address on a regular port. */ | |
f5d88f58 | 641 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, |
3b71571c JP |
642 | /* Aged-out MAC address on a LAG port. */ |
643 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, | |
933b1ecd IS |
644 | /* Learned unicast tunnel record. */ |
645 | MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, | |
646 | /* Aged-out unicast tunnel record. */ | |
647 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, | |
f5d88f58 JP |
648 | }; |
649 | ||
650 | /* reg_sfn_rec_type | |
651 | * Notification record type. | |
652 | * Access: RO | |
653 | */ | |
654 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, | |
655 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
656 | ||
657 | /* reg_sfn_rec_mac | |
658 | * MAC address. | |
659 | * Access: RO | |
660 | */ | |
661 | MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, | |
662 | MLXSW_REG_SFN_REC_LEN, 0x02); | |
663 | ||
8316f087 | 664 | /* reg_sfn_mac_sub_port |
f5d88f58 JP |
665 | * VEPA channel on the local port. |
666 | * 0 if multichannel VEPA is not enabled. | |
667 | * Access: RO | |
668 | */ | |
669 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, | |
670 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
671 | ||
8316f087 | 672 | /* reg_sfn_mac_fid |
f5d88f58 JP |
673 | * Filtering identifier. |
674 | * Access: RO | |
675 | */ | |
676 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
677 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
678 | ||
8316f087 | 679 | /* reg_sfn_mac_system_port |
f5d88f58 JP |
680 | * Unique port identifier for the final destination of the packet. |
681 | * Access: RO | |
682 | */ | |
683 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
684 | MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
685 | ||
686 | static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, | |
687 | char *mac, u16 *p_vid, | |
688 | u8 *p_local_port) | |
689 | { | |
690 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
691 | *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
692 | *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); | |
693 | } | |
694 | ||
3b71571c JP |
695 | /* reg_sfn_mac_lag_lag_id |
696 | * LAG ID (pointer into the LAG descriptor table). | |
697 | * Access: RO | |
698 | */ | |
699 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, | |
700 | MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
701 | ||
702 | static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, | |
703 | char *mac, u16 *p_vid, | |
704 | u16 *p_lag_id) | |
705 | { | |
706 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
707 | *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
708 | *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); | |
709 | } | |
710 | ||
933b1ecd IS |
711 | /* reg_sfn_uc_tunnel_uip_msb |
712 | * When protocol is IPv4, the most significant byte of the underlay IPv4 | |
713 | * address of the remote VTEP. | |
714 | * When protocol is IPv6, reserved. | |
715 | * Access: RO | |
716 | */ | |
717 | MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, | |
718 | 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
719 | ||
720 | enum mlxsw_reg_sfn_uc_tunnel_protocol { | |
721 | MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, | |
722 | MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, | |
723 | }; | |
724 | ||
725 | /* reg_sfn_uc_tunnel_protocol | |
726 | * IP protocol. | |
727 | * Access: RO | |
728 | */ | |
729 | MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, | |
730 | 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
731 | ||
732 | /* reg_sfn_uc_tunnel_uip_lsb | |
733 | * When protocol is IPv4, the least significant bytes of the underlay | |
734 | * IPv4 address of the remote VTEP. | |
735 | * When protocol is IPv6, ipv6_id to be queried from TNIPSD. | |
736 | * Access: RO | |
737 | */ | |
738 | MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, | |
739 | 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
740 | ||
741 | enum mlxsw_reg_sfn_tunnel_port { | |
742 | MLXSW_REG_SFN_TUNNEL_PORT_NVE, | |
743 | MLXSW_REG_SFN_TUNNEL_PORT_VPLS, | |
744 | MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, | |
745 | MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, | |
746 | }; | |
747 | ||
748 | /* reg_sfn_uc_tunnel_port | |
749 | * Tunnel port. | |
750 | * Reserved on Spectrum. | |
751 | * Access: RO | |
752 | */ | |
753 | MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, | |
754 | MLXSW_REG_SFN_REC_LEN, 0x10, false); | |
755 | ||
756 | static inline void | |
757 | mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, | |
758 | u16 *p_fid, u32 *p_uip, | |
759 | enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) | |
760 | { | |
761 | u32 uip_msb, uip_lsb; | |
762 | ||
763 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
764 | *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
765 | uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); | |
766 | uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); | |
767 | *p_uip = uip_msb << 24 | uip_lsb; | |
768 | *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); | |
769 | } | |
770 | ||
4ec14b76 IS |
771 | /* SPMS - Switch Port MSTP/RSTP State Register |
772 | * ------------------------------------------- | |
773 | * Configures the spanning tree state of a physical port. | |
774 | */ | |
3f0effd1 | 775 | #define MLXSW_REG_SPMS_ID 0x200D |
4ec14b76 IS |
776 | #define MLXSW_REG_SPMS_LEN 0x404 |
777 | ||
21978dcf | 778 | MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); |
4ec14b76 IS |
779 | |
780 | /* reg_spms_local_port | |
781 | * Local port number. | |
782 | * Access: Index | |
783 | */ | |
784 | MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); | |
785 | ||
786 | enum mlxsw_reg_spms_state { | |
787 | MLXSW_REG_SPMS_STATE_NO_CHANGE, | |
788 | MLXSW_REG_SPMS_STATE_DISCARDING, | |
789 | MLXSW_REG_SPMS_STATE_LEARNING, | |
790 | MLXSW_REG_SPMS_STATE_FORWARDING, | |
791 | }; | |
792 | ||
793 | /* reg_spms_state | |
794 | * Spanning tree state of each VLAN ID (VID) of the local port. | |
795 | * 0 - Do not change spanning tree state (used only when writing). | |
796 | * 1 - Discarding. No learning or forwarding to/from this port (default). | |
797 | * 2 - Learning. Port is learning, but not forwarding. | |
798 | * 3 - Forwarding. Port is learning and forwarding. | |
799 | * Access: RW | |
800 | */ | |
801 | MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); | |
802 | ||
ebb7963f | 803 | static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) |
4ec14b76 IS |
804 | { |
805 | MLXSW_REG_ZERO(spms, payload); | |
806 | mlxsw_reg_spms_local_port_set(payload, local_port); | |
ebb7963f JP |
807 | } |
808 | ||
809 | static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, | |
810 | enum mlxsw_reg_spms_state state) | |
811 | { | |
4ec14b76 IS |
812 | mlxsw_reg_spms_state_set(payload, vid, state); |
813 | } | |
814 | ||
b2e345f9 ER |
815 | /* SPVID - Switch Port VID |
816 | * ----------------------- | |
817 | * The switch port VID configures the default VID for a port. | |
818 | */ | |
819 | #define MLXSW_REG_SPVID_ID 0x200E | |
820 | #define MLXSW_REG_SPVID_LEN 0x08 | |
821 | ||
21978dcf | 822 | MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); |
b2e345f9 ER |
823 | |
824 | /* reg_spvid_local_port | |
825 | * Local port number. | |
826 | * Access: Index | |
827 | */ | |
828 | MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); | |
829 | ||
830 | /* reg_spvid_sub_port | |
831 | * Virtual port within the physical port. | |
832 | * Should be set to 0 when virtual ports are not enabled on the port. | |
833 | * Access: Index | |
834 | */ | |
835 | MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); | |
836 | ||
837 | /* reg_spvid_pvid | |
838 | * Port default VID | |
839 | * Access: RW | |
840 | */ | |
841 | MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); | |
842 | ||
843 | static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) | |
844 | { | |
845 | MLXSW_REG_ZERO(spvid, payload); | |
846 | mlxsw_reg_spvid_local_port_set(payload, local_port); | |
847 | mlxsw_reg_spvid_pvid_set(payload, pvid); | |
848 | } | |
849 | ||
850 | /* SPVM - Switch Port VLAN Membership | |
851 | * ---------------------------------- | |
852 | * The Switch Port VLAN Membership register configures the VLAN membership | |
853 | * of a port in a VLAN denoted by VID. VLAN membership is managed per | |
854 | * virtual port. The register can be used to add and remove VID(s) from a port. | |
855 | */ | |
856 | #define MLXSW_REG_SPVM_ID 0x200F | |
857 | #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ | |
858 | #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ | |
f004ec06 | 859 | #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 |
b2e345f9 ER |
860 | #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ |
861 | MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) | |
862 | ||
21978dcf | 863 | MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); |
b2e345f9 ER |
864 | |
865 | /* reg_spvm_pt | |
866 | * Priority tagged. If this bit is set, packets forwarded to the port with | |
867 | * untagged VLAN membership (u bit is set) will be tagged with priority tag | |
868 | * (VID=0) | |
869 | * Access: RW | |
870 | */ | |
871 | MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); | |
872 | ||
873 | /* reg_spvm_pte | |
874 | * Priority Tagged Update Enable. On Write operations, if this bit is cleared, | |
875 | * the pt bit will NOT be updated. To update the pt bit, pte must be set. | |
876 | * Access: WO | |
877 | */ | |
878 | MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); | |
879 | ||
880 | /* reg_spvm_local_port | |
881 | * Local port number. | |
882 | * Access: Index | |
883 | */ | |
884 | MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); | |
885 | ||
886 | /* reg_spvm_sub_port | |
887 | * Virtual port within the physical port. | |
888 | * Should be set to 0 when virtual ports are not enabled on the port. | |
889 | * Access: Index | |
890 | */ | |
891 | MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); | |
892 | ||
893 | /* reg_spvm_num_rec | |
894 | * Number of records to update. Each record contains: i, e, u, vid. | |
895 | * Access: OP | |
896 | */ | |
897 | MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); | |
898 | ||
899 | /* reg_spvm_rec_i | |
900 | * Ingress membership in VLAN ID. | |
901 | * Access: Index | |
902 | */ | |
903 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, | |
904 | MLXSW_REG_SPVM_BASE_LEN, 14, 1, | |
905 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
906 | ||
907 | /* reg_spvm_rec_e | |
908 | * Egress membership in VLAN ID. | |
909 | * Access: Index | |
910 | */ | |
911 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, | |
912 | MLXSW_REG_SPVM_BASE_LEN, 13, 1, | |
913 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
914 | ||
915 | /* reg_spvm_rec_u | |
916 | * Untagged - port is an untagged member - egress transmission uses untagged | |
917 | * frames on VID<n> | |
918 | * Access: Index | |
919 | */ | |
920 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, | |
921 | MLXSW_REG_SPVM_BASE_LEN, 12, 1, | |
922 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
923 | ||
924 | /* reg_spvm_rec_vid | |
925 | * Egress membership in VLAN ID. | |
926 | * Access: Index | |
927 | */ | |
928 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, | |
929 | MLXSW_REG_SPVM_BASE_LEN, 0, 12, | |
930 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
931 | ||
932 | static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, | |
933 | u16 vid_begin, u16 vid_end, | |
934 | bool is_member, bool untagged) | |
935 | { | |
936 | int size = vid_end - vid_begin + 1; | |
937 | int i; | |
938 | ||
939 | MLXSW_REG_ZERO(spvm, payload); | |
940 | mlxsw_reg_spvm_local_port_set(payload, local_port); | |
941 | mlxsw_reg_spvm_num_rec_set(payload, size); | |
942 | ||
943 | for (i = 0; i < size; i++) { | |
944 | mlxsw_reg_spvm_rec_i_set(payload, i, is_member); | |
945 | mlxsw_reg_spvm_rec_e_set(payload, i, is_member); | |
946 | mlxsw_reg_spvm_rec_u_set(payload, i, untagged); | |
947 | mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); | |
948 | } | |
949 | } | |
950 | ||
148f472d IS |
951 | /* SPAFT - Switch Port Acceptable Frame Types |
952 | * ------------------------------------------ | |
953 | * The Switch Port Acceptable Frame Types register configures the frame | |
954 | * admittance of the port. | |
955 | */ | |
956 | #define MLXSW_REG_SPAFT_ID 0x2010 | |
957 | #define MLXSW_REG_SPAFT_LEN 0x08 | |
958 | ||
21978dcf | 959 | MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); |
148f472d IS |
960 | |
961 | /* reg_spaft_local_port | |
962 | * Local port number. | |
963 | * Access: Index | |
964 | * | |
965 | * Note: CPU port is not supported (all tag types are allowed). | |
966 | */ | |
967 | MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); | |
968 | ||
969 | /* reg_spaft_sub_port | |
970 | * Virtual port within the physical port. | |
971 | * Should be set to 0 when virtual ports are not enabled on the port. | |
972 | * Access: RW | |
973 | */ | |
974 | MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); | |
975 | ||
976 | /* reg_spaft_allow_untagged | |
977 | * When set, untagged frames on the ingress are allowed (default). | |
978 | * Access: RW | |
979 | */ | |
980 | MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); | |
981 | ||
982 | /* reg_spaft_allow_prio_tagged | |
983 | * When set, priority tagged frames on the ingress are allowed (default). | |
984 | * Access: RW | |
985 | */ | |
986 | MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); | |
987 | ||
988 | /* reg_spaft_allow_tagged | |
989 | * When set, tagged frames on the ingress are allowed (default). | |
990 | * Access: RW | |
991 | */ | |
992 | MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); | |
993 | ||
994 | static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, | |
995 | bool allow_untagged) | |
996 | { | |
997 | MLXSW_REG_ZERO(spaft, payload); | |
998 | mlxsw_reg_spaft_local_port_set(payload, local_port); | |
999 | mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); | |
4b14cc31 | 1000 | mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); |
148f472d IS |
1001 | mlxsw_reg_spaft_allow_tagged_set(payload, true); |
1002 | } | |
1003 | ||
4ec14b76 IS |
1004 | /* SFGC - Switch Flooding Group Configuration |
1005 | * ------------------------------------------ | |
1006 | * The following register controls the association of flooding tables and MIDs | |
1007 | * to packet types used for flooding. | |
1008 | */ | |
36b78e8a | 1009 | #define MLXSW_REG_SFGC_ID 0x2011 |
4ec14b76 IS |
1010 | #define MLXSW_REG_SFGC_LEN 0x10 |
1011 | ||
21978dcf | 1012 | MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); |
4ec14b76 IS |
1013 | |
1014 | enum mlxsw_reg_sfgc_type { | |
fa6ad058 IS |
1015 | MLXSW_REG_SFGC_TYPE_BROADCAST, |
1016 | MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, | |
1017 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, | |
1018 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, | |
1019 | MLXSW_REG_SFGC_TYPE_RESERVED, | |
1020 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, | |
1021 | MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, | |
1022 | MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, | |
1023 | MLXSW_REG_SFGC_TYPE_MAX, | |
4ec14b76 IS |
1024 | }; |
1025 | ||
1026 | /* reg_sfgc_type | |
1027 | * The traffic type to reach the flooding table. | |
1028 | * Access: Index | |
1029 | */ | |
1030 | MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); | |
1031 | ||
1032 | enum mlxsw_reg_sfgc_bridge_type { | |
1033 | MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, | |
1034 | MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, | |
1035 | }; | |
1036 | ||
1037 | /* reg_sfgc_bridge_type | |
1038 | * Access: Index | |
1039 | * | |
1040 | * Note: SwitchX-2 only supports 802.1Q mode. | |
1041 | */ | |
1042 | MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); | |
1043 | ||
1044 | enum mlxsw_flood_table_type { | |
1045 | MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, | |
1046 | MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, | |
1047 | MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, | |
da0abcf9 | 1048 | MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, |
4ec14b76 IS |
1049 | MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, |
1050 | }; | |
1051 | ||
1052 | /* reg_sfgc_table_type | |
1053 | * See mlxsw_flood_table_type | |
1054 | * Access: RW | |
1055 | * | |
1056 | * Note: FID offset and FID types are not supported in SwitchX-2. | |
1057 | */ | |
1058 | MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); | |
1059 | ||
1060 | /* reg_sfgc_flood_table | |
1061 | * Flooding table index to associate with the specific type on the specific | |
1062 | * switch partition. | |
1063 | * Access: RW | |
1064 | */ | |
1065 | MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); | |
1066 | ||
1067 | /* reg_sfgc_mid | |
1068 | * The multicast ID for the swid. Not supported for Spectrum | |
1069 | * Access: RW | |
1070 | */ | |
1071 | MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); | |
1072 | ||
1073 | /* reg_sfgc_counter_set_type | |
1074 | * Counter Set Type for flow counters. | |
1075 | * Access: RW | |
1076 | */ | |
1077 | MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); | |
1078 | ||
1079 | /* reg_sfgc_counter_index | |
1080 | * Counter Index for flow counters. | |
1081 | * Access: RW | |
1082 | */ | |
1083 | MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); | |
1084 | ||
1085 | static inline void | |
1086 | mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, | |
1087 | enum mlxsw_reg_sfgc_bridge_type bridge_type, | |
1088 | enum mlxsw_flood_table_type table_type, | |
1089 | unsigned int flood_table) | |
1090 | { | |
1091 | MLXSW_REG_ZERO(sfgc, payload); | |
1092 | mlxsw_reg_sfgc_type_set(payload, type); | |
1093 | mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); | |
1094 | mlxsw_reg_sfgc_table_type_set(payload, table_type); | |
1095 | mlxsw_reg_sfgc_flood_table_set(payload, flood_table); | |
1096 | mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); | |
1097 | } | |
1098 | ||
1099 | /* SFTR - Switch Flooding Table Register | |
1100 | * ------------------------------------- | |
1101 | * The switch flooding table is used for flooding packet replication. The table | |
1102 | * defines a bit mask of ports for packet replication. | |
1103 | */ | |
1104 | #define MLXSW_REG_SFTR_ID 0x2012 | |
1105 | #define MLXSW_REG_SFTR_LEN 0x420 | |
1106 | ||
21978dcf | 1107 | MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); |
4ec14b76 IS |
1108 | |
1109 | /* reg_sftr_swid | |
1110 | * Switch partition ID with which to associate the port. | |
1111 | * Access: Index | |
1112 | */ | |
1113 | MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); | |
1114 | ||
1115 | /* reg_sftr_flood_table | |
1116 | * Flooding table index to associate with the specific type on the specific | |
1117 | * switch partition. | |
1118 | * Access: Index | |
1119 | */ | |
1120 | MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); | |
1121 | ||
1122 | /* reg_sftr_index | |
1123 | * Index. Used as an index into the Flooding Table in case the table is | |
1124 | * configured to use VID / FID or FID Offset. | |
1125 | * Access: Index | |
1126 | */ | |
1127 | MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); | |
1128 | ||
1129 | /* reg_sftr_table_type | |
1130 | * See mlxsw_flood_table_type | |
1131 | * Access: RW | |
1132 | */ | |
1133 | MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); | |
1134 | ||
1135 | /* reg_sftr_range | |
1136 | * Range of entries to update | |
1137 | * Access: Index | |
1138 | */ | |
1139 | MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); | |
1140 | ||
1141 | /* reg_sftr_port | |
1142 | * Local port membership (1 bit per port). | |
1143 | * Access: RW | |
1144 | */ | |
1145 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); | |
1146 | ||
1147 | /* reg_sftr_cpu_port_mask | |
1148 | * CPU port mask (1 bit per port). | |
1149 | * Access: W | |
1150 | */ | |
1151 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); | |
1152 | ||
1153 | static inline void mlxsw_reg_sftr_pack(char *payload, | |
1154 | unsigned int flood_table, | |
1155 | unsigned int index, | |
1156 | enum mlxsw_flood_table_type table_type, | |
bc2055f8 | 1157 | unsigned int range, u8 port, bool set) |
4ec14b76 IS |
1158 | { |
1159 | MLXSW_REG_ZERO(sftr, payload); | |
1160 | mlxsw_reg_sftr_swid_set(payload, 0); | |
1161 | mlxsw_reg_sftr_flood_table_set(payload, flood_table); | |
1162 | mlxsw_reg_sftr_index_set(payload, index); | |
1163 | mlxsw_reg_sftr_table_type_set(payload, table_type); | |
1164 | mlxsw_reg_sftr_range_set(payload, range); | |
bc2055f8 IS |
1165 | mlxsw_reg_sftr_port_set(payload, port, set); |
1166 | mlxsw_reg_sftr_port_mask_set(payload, port, 1); | |
4ec14b76 IS |
1167 | } |
1168 | ||
41933271 IS |
1169 | /* SFDF - Switch Filtering DB Flush |
1170 | * -------------------------------- | |
1171 | * The switch filtering DB flush register is used to flush the FDB. | |
1172 | * Note that FDB notifications are flushed as well. | |
1173 | */ | |
1174 | #define MLXSW_REG_SFDF_ID 0x2013 | |
1175 | #define MLXSW_REG_SFDF_LEN 0x14 | |
1176 | ||
21978dcf | 1177 | MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); |
41933271 IS |
1178 | |
1179 | /* reg_sfdf_swid | |
1180 | * Switch partition ID. | |
1181 | * Access: Index | |
1182 | */ | |
1183 | MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); | |
1184 | ||
1185 | enum mlxsw_reg_sfdf_flush_type { | |
1186 | MLXSW_REG_SFDF_FLUSH_PER_SWID, | |
1187 | MLXSW_REG_SFDF_FLUSH_PER_FID, | |
1188 | MLXSW_REG_SFDF_FLUSH_PER_PORT, | |
1189 | MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, | |
1190 | MLXSW_REG_SFDF_FLUSH_PER_LAG, | |
1191 | MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, | |
a682a302 IS |
1192 | MLXSW_REG_SFDF_FLUSH_PER_NVE, |
1193 | MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, | |
41933271 IS |
1194 | }; |
1195 | ||
1196 | /* reg_sfdf_flush_type | |
1197 | * Flush type. | |
1198 | * 0 - All SWID dynamic entries are flushed. | |
1199 | * 1 - All FID dynamic entries are flushed. | |
1200 | * 2 - All dynamic entries pointing to port are flushed. | |
1201 | * 3 - All FID dynamic entries pointing to port are flushed. | |
1202 | * 4 - All dynamic entries pointing to LAG are flushed. | |
1203 | * 5 - All FID dynamic entries pointing to LAG are flushed. | |
a682a302 IS |
1204 | * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are |
1205 | * flushed. | |
1206 | * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are | |
1207 | * flushed, per FID. | |
41933271 IS |
1208 | * Access: RW |
1209 | */ | |
1210 | MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); | |
1211 | ||
1212 | /* reg_sfdf_flush_static | |
1213 | * Static. | |
1214 | * 0 - Flush only dynamic entries. | |
1215 | * 1 - Flush both dynamic and static entries. | |
1216 | * Access: RW | |
1217 | */ | |
1218 | MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); | |
1219 | ||
1220 | static inline void mlxsw_reg_sfdf_pack(char *payload, | |
1221 | enum mlxsw_reg_sfdf_flush_type type) | |
1222 | { | |
1223 | MLXSW_REG_ZERO(sfdf, payload); | |
1224 | mlxsw_reg_sfdf_flush_type_set(payload, type); | |
1225 | mlxsw_reg_sfdf_flush_static_set(payload, true); | |
1226 | } | |
1227 | ||
1228 | /* reg_sfdf_fid | |
1229 | * FID to flush. | |
1230 | * Access: RW | |
1231 | */ | |
1232 | MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); | |
1233 | ||
1234 | /* reg_sfdf_system_port | |
1235 | * Port to flush. | |
1236 | * Access: RW | |
1237 | */ | |
1238 | MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); | |
1239 | ||
1240 | /* reg_sfdf_port_fid_system_port | |
1241 | * Port to flush, pointed to by FID. | |
1242 | * Access: RW | |
1243 | */ | |
1244 | MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); | |
1245 | ||
1246 | /* reg_sfdf_lag_id | |
1247 | * LAG ID to flush. | |
1248 | * Access: RW | |
1249 | */ | |
1250 | MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); | |
1251 | ||
1252 | /* reg_sfdf_lag_fid_lag_id | |
1253 | * LAG ID to flush, pointed to by FID. | |
1254 | * Access: RW | |
1255 | */ | |
1256 | MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); | |
1257 | ||
d1d40be0 JP |
1258 | /* SLDR - Switch LAG Descriptor Register |
1259 | * ----------------------------------------- | |
1260 | * The switch LAG descriptor register is populated by LAG descriptors. | |
1261 | * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to | |
1262 | * max_lag-1. | |
1263 | */ | |
1264 | #define MLXSW_REG_SLDR_ID 0x2014 | |
1265 | #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ | |
1266 | ||
21978dcf | 1267 | MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); |
d1d40be0 JP |
1268 | |
1269 | enum mlxsw_reg_sldr_op { | |
1270 | /* Indicates a creation of a new LAG-ID, lag_id must be valid */ | |
1271 | MLXSW_REG_SLDR_OP_LAG_CREATE, | |
1272 | MLXSW_REG_SLDR_OP_LAG_DESTROY, | |
1273 | /* Ports that appear in the list have the Distributor enabled */ | |
1274 | MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, | |
1275 | /* Removes ports from the disributor list */ | |
1276 | MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, | |
1277 | }; | |
1278 | ||
1279 | /* reg_sldr_op | |
1280 | * Operation. | |
1281 | * Access: RW | |
1282 | */ | |
1283 | MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); | |
1284 | ||
1285 | /* reg_sldr_lag_id | |
1286 | * LAG identifier. The lag_id is the index into the LAG descriptor table. | |
1287 | * Access: Index | |
1288 | */ | |
1289 | MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); | |
1290 | ||
1291 | static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) | |
1292 | { | |
1293 | MLXSW_REG_ZERO(sldr, payload); | |
1294 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); | |
1295 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1296 | } | |
1297 | ||
1298 | static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) | |
1299 | { | |
1300 | MLXSW_REG_ZERO(sldr, payload); | |
1301 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); | |
1302 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1303 | } | |
1304 | ||
1305 | /* reg_sldr_num_ports | |
1306 | * The number of member ports of the LAG. | |
1307 | * Reserved for Create / Destroy operations | |
1308 | * For Add / Remove operations - indicates the number of ports in the list. | |
1309 | * Access: RW | |
1310 | */ | |
1311 | MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); | |
1312 | ||
1313 | /* reg_sldr_system_port | |
1314 | * System port. | |
1315 | * Access: RW | |
1316 | */ | |
1317 | MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); | |
1318 | ||
1319 | static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, | |
1320 | u8 local_port) | |
1321 | { | |
1322 | MLXSW_REG_ZERO(sldr, payload); | |
1323 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); | |
1324 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1325 | mlxsw_reg_sldr_num_ports_set(payload, 1); | |
1326 | mlxsw_reg_sldr_system_port_set(payload, 0, local_port); | |
1327 | } | |
1328 | ||
1329 | static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, | |
1330 | u8 local_port) | |
1331 | { | |
1332 | MLXSW_REG_ZERO(sldr, payload); | |
1333 | mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); | |
1334 | mlxsw_reg_sldr_lag_id_set(payload, lag_id); | |
1335 | mlxsw_reg_sldr_num_ports_set(payload, 1); | |
1336 | mlxsw_reg_sldr_system_port_set(payload, 0, local_port); | |
1337 | } | |
1338 | ||
1339 | /* SLCR - Switch LAG Configuration 2 Register | |
1340 | * ------------------------------------------- | |
1341 | * The Switch LAG Configuration register is used for configuring the | |
1342 | * LAG properties of the switch. | |
1343 | */ | |
1344 | #define MLXSW_REG_SLCR_ID 0x2015 | |
1345 | #define MLXSW_REG_SLCR_LEN 0x10 | |
1346 | ||
21978dcf | 1347 | MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); |
d1d40be0 JP |
1348 | |
1349 | enum mlxsw_reg_slcr_pp { | |
1350 | /* Global Configuration (for all ports) */ | |
1351 | MLXSW_REG_SLCR_PP_GLOBAL, | |
1352 | /* Per port configuration, based on local_port field */ | |
1353 | MLXSW_REG_SLCR_PP_PER_PORT, | |
1354 | }; | |
1355 | ||
1356 | /* reg_slcr_pp | |
1357 | * Per Port Configuration | |
1358 | * Note: Reading at Global mode results in reading port 1 configuration. | |
1359 | * Access: Index | |
1360 | */ | |
1361 | MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); | |
1362 | ||
1363 | /* reg_slcr_local_port | |
1364 | * Local port number | |
1365 | * Supported from CPU port | |
1366 | * Not supported from router port | |
1367 | * Reserved when pp = Global Configuration | |
1368 | * Access: Index | |
1369 | */ | |
1370 | MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); | |
1371 | ||
1372 | enum mlxsw_reg_slcr_type { | |
1373 | MLXSW_REG_SLCR_TYPE_CRC, /* default */ | |
1374 | MLXSW_REG_SLCR_TYPE_XOR, | |
1375 | MLXSW_REG_SLCR_TYPE_RANDOM, | |
1376 | }; | |
1377 | ||
1378 | /* reg_slcr_type | |
1379 | * Hash type | |
1380 | * Access: RW | |
1381 | */ | |
1382 | MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); | |
1383 | ||
1384 | /* Ingress port */ | |
1385 | #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) | |
1386 | /* SMAC - for IPv4 and IPv6 packets */ | |
1387 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) | |
1388 | /* SMAC - for non-IP packets */ | |
1389 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) | |
1390 | #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ | |
1391 | (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ | |
1392 | MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) | |
1393 | /* DMAC - for IPv4 and IPv6 packets */ | |
1394 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) | |
1395 | /* DMAC - for non-IP packets */ | |
1396 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) | |
1397 | #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ | |
1398 | (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ | |
1399 | MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) | |
1400 | /* Ethertype - for IPv4 and IPv6 packets */ | |
1401 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) | |
1402 | /* Ethertype - for non-IP packets */ | |
1403 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) | |
1404 | #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ | |
1405 | (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ | |
1406 | MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) | |
1407 | /* VLAN ID - for IPv4 and IPv6 packets */ | |
1408 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) | |
1409 | /* VLAN ID - for non-IP packets */ | |
1410 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) | |
1411 | #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ | |
1412 | (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ | |
1413 | MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) | |
1414 | /* Source IP address (can be IPv4 or IPv6) */ | |
1415 | #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) | |
1416 | /* Destination IP address (can be IPv4 or IPv6) */ | |
1417 | #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) | |
1418 | /* TCP/UDP source port */ | |
1419 | #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) | |
1420 | /* TCP/UDP destination port*/ | |
1421 | #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) | |
1422 | /* IPv4 Protocol/IPv6 Next Header */ | |
1423 | #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) | |
1424 | /* IPv6 Flow label */ | |
1425 | #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) | |
1426 | /* SID - FCoE source ID */ | |
1427 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) | |
1428 | /* DID - FCoE destination ID */ | |
1429 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) | |
1430 | /* OXID - FCoE originator exchange ID */ | |
1431 | #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) | |
1432 | /* Destination QP number - for RoCE packets */ | |
1433 | #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) | |
1434 | ||
1435 | /* reg_slcr_lag_hash | |
1436 | * LAG hashing configuration. This is a bitmask, in which each set | |
1437 | * bit includes the corresponding item in the LAG hash calculation. | |
1438 | * The default lag_hash contains SMAC, DMAC, VLANID and | |
1439 | * Ethertype (for all packet types). | |
1440 | * Access: RW | |
1441 | */ | |
1442 | MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); | |
1443 | ||
beda7f72 IS |
1444 | /* reg_slcr_seed |
1445 | * LAG seed value. The seed is the same for all ports. | |
1446 | * Access: RW | |
1447 | */ | |
1448 | MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); | |
1449 | ||
1450 | static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) | |
d1d40be0 JP |
1451 | { |
1452 | MLXSW_REG_ZERO(slcr, payload); | |
1453 | mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); | |
18c2d2c1 | 1454 | mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); |
d1d40be0 | 1455 | mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); |
beda7f72 | 1456 | mlxsw_reg_slcr_seed_set(payload, seed); |
d1d40be0 JP |
1457 | } |
1458 | ||
1459 | /* SLCOR - Switch LAG Collector Register | |
1460 | * ------------------------------------- | |
1461 | * The Switch LAG Collector register controls the Local Port membership | |
1462 | * in a LAG and enablement of the collector. | |
1463 | */ | |
1464 | #define MLXSW_REG_SLCOR_ID 0x2016 | |
1465 | #define MLXSW_REG_SLCOR_LEN 0x10 | |
1466 | ||
21978dcf | 1467 | MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); |
d1d40be0 JP |
1468 | |
1469 | enum mlxsw_reg_slcor_col { | |
1470 | /* Port is added with collector disabled */ | |
1471 | MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, | |
1472 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, | |
1473 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, | |
1474 | MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, | |
1475 | }; | |
1476 | ||
1477 | /* reg_slcor_col | |
1478 | * Collector configuration | |
1479 | * Access: RW | |
1480 | */ | |
1481 | MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); | |
1482 | ||
1483 | /* reg_slcor_local_port | |
1484 | * Local port number | |
1485 | * Not supported for CPU port | |
1486 | * Access: Index | |
1487 | */ | |
1488 | MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); | |
1489 | ||
1490 | /* reg_slcor_lag_id | |
1491 | * LAG Identifier. Index into the LAG descriptor table. | |
1492 | * Access: Index | |
1493 | */ | |
1494 | MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); | |
1495 | ||
1496 | /* reg_slcor_port_index | |
1497 | * Port index in the LAG list. Only valid on Add Port to LAG col. | |
1498 | * Valid range is from 0 to cap_max_lag_members-1 | |
1499 | * Access: RW | |
1500 | */ | |
1501 | MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); | |
1502 | ||
1503 | static inline void mlxsw_reg_slcor_pack(char *payload, | |
1504 | u8 local_port, u16 lag_id, | |
1505 | enum mlxsw_reg_slcor_col col) | |
1506 | { | |
1507 | MLXSW_REG_ZERO(slcor, payload); | |
1508 | mlxsw_reg_slcor_col_set(payload, col); | |
1509 | mlxsw_reg_slcor_local_port_set(payload, local_port); | |
1510 | mlxsw_reg_slcor_lag_id_set(payload, lag_id); | |
1511 | } | |
1512 | ||
1513 | static inline void mlxsw_reg_slcor_port_add_pack(char *payload, | |
1514 | u8 local_port, u16 lag_id, | |
1515 | u8 port_index) | |
1516 | { | |
1517 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1518 | MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); | |
1519 | mlxsw_reg_slcor_port_index_set(payload, port_index); | |
1520 | } | |
1521 | ||
1522 | static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, | |
1523 | u8 local_port, u16 lag_id) | |
1524 | { | |
1525 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1526 | MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); | |
1527 | } | |
1528 | ||
1529 | static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, | |
1530 | u8 local_port, u16 lag_id) | |
1531 | { | |
1532 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1533 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); | |
1534 | } | |
1535 | ||
1536 | static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, | |
1537 | u8 local_port, u16 lag_id) | |
1538 | { | |
1539 | mlxsw_reg_slcor_pack(payload, local_port, lag_id, | |
1540 | MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); | |
1541 | } | |
1542 | ||
4ec14b76 IS |
1543 | /* SPMLR - Switch Port MAC Learning Register |
1544 | * ----------------------------------------- | |
1545 | * Controls the Switch MAC learning policy per port. | |
1546 | */ | |
1547 | #define MLXSW_REG_SPMLR_ID 0x2018 | |
1548 | #define MLXSW_REG_SPMLR_LEN 0x8 | |
1549 | ||
21978dcf | 1550 | MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); |
4ec14b76 IS |
1551 | |
1552 | /* reg_spmlr_local_port | |
1553 | * Local port number. | |
1554 | * Access: Index | |
1555 | */ | |
1556 | MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); | |
1557 | ||
1558 | /* reg_spmlr_sub_port | |
1559 | * Virtual port within the physical port. | |
1560 | * Should be set to 0 when virtual ports are not enabled on the port. | |
1561 | * Access: Index | |
1562 | */ | |
1563 | MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); | |
1564 | ||
1565 | enum mlxsw_reg_spmlr_learn_mode { | |
1566 | MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, | |
1567 | MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, | |
1568 | MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, | |
1569 | }; | |
1570 | ||
1571 | /* reg_spmlr_learn_mode | |
1572 | * Learning mode on the port. | |
1573 | * 0 - Learning disabled. | |
1574 | * 2 - Learning enabled. | |
1575 | * 3 - Security mode. | |
1576 | * | |
1577 | * In security mode the switch does not learn MACs on the port, but uses the | |
1578 | * SMAC to see if it exists on another ingress port. If so, the packet is | |
1579 | * classified as a bad packet and is discarded unless the software registers | |
1580 | * to receive port security error packets usign HPKT. | |
1581 | */ | |
1582 | MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); | |
1583 | ||
1584 | static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, | |
1585 | enum mlxsw_reg_spmlr_learn_mode mode) | |
1586 | { | |
1587 | MLXSW_REG_ZERO(spmlr, payload); | |
1588 | mlxsw_reg_spmlr_local_port_set(payload, local_port); | |
1589 | mlxsw_reg_spmlr_sub_port_set(payload, 0); | |
1590 | mlxsw_reg_spmlr_learn_mode_set(payload, mode); | |
1591 | } | |
1592 | ||
64790239 IS |
1593 | /* SVFA - Switch VID to FID Allocation Register |
1594 | * -------------------------------------------- | |
1595 | * Controls the VID to FID mapping and {Port, VID} to FID mapping for | |
1596 | * virtualized ports. | |
1597 | */ | |
1598 | #define MLXSW_REG_SVFA_ID 0x201C | |
1599 | #define MLXSW_REG_SVFA_LEN 0x10 | |
1600 | ||
21978dcf | 1601 | MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); |
64790239 IS |
1602 | |
1603 | /* reg_svfa_swid | |
1604 | * Switch partition ID. | |
1605 | * Access: Index | |
1606 | */ | |
1607 | MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); | |
1608 | ||
1609 | /* reg_svfa_local_port | |
1610 | * Local port number. | |
1611 | * Access: Index | |
1612 | * | |
1613 | * Note: Reserved for 802.1Q FIDs. | |
1614 | */ | |
1615 | MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); | |
1616 | ||
1617 | enum mlxsw_reg_svfa_mt { | |
1618 | MLXSW_REG_SVFA_MT_VID_TO_FID, | |
1619 | MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, | |
1620 | }; | |
1621 | ||
1622 | /* reg_svfa_mapping_table | |
1623 | * Mapping table: | |
1624 | * 0 - VID to FID | |
1625 | * 1 - {Port, VID} to FID | |
1626 | * Access: Index | |
1627 | * | |
1628 | * Note: Reserved for SwitchX-2. | |
1629 | */ | |
1630 | MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); | |
1631 | ||
1632 | /* reg_svfa_v | |
1633 | * Valid. | |
1634 | * Valid if set. | |
1635 | * Access: RW | |
1636 | * | |
1637 | * Note: Reserved for SwitchX-2. | |
1638 | */ | |
1639 | MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); | |
1640 | ||
1641 | /* reg_svfa_fid | |
1642 | * Filtering ID. | |
1643 | * Access: RW | |
1644 | */ | |
1645 | MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); | |
1646 | ||
1647 | /* reg_svfa_vid | |
1648 | * VLAN ID. | |
1649 | * Access: Index | |
1650 | */ | |
1651 | MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); | |
1652 | ||
1653 | /* reg_svfa_counter_set_type | |
1654 | * Counter set type for flow counters. | |
1655 | * Access: RW | |
1656 | * | |
1657 | * Note: Reserved for SwitchX-2. | |
1658 | */ | |
1659 | MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); | |
1660 | ||
1661 | /* reg_svfa_counter_index | |
1662 | * Counter index for flow counters. | |
1663 | * Access: RW | |
1664 | * | |
1665 | * Note: Reserved for SwitchX-2. | |
1666 | */ | |
1667 | MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); | |
1668 | ||
1669 | static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, | |
1670 | enum mlxsw_reg_svfa_mt mt, bool valid, | |
1671 | u16 fid, u16 vid) | |
1672 | { | |
1673 | MLXSW_REG_ZERO(svfa, payload); | |
1674 | local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; | |
1675 | mlxsw_reg_svfa_swid_set(payload, 0); | |
1676 | mlxsw_reg_svfa_local_port_set(payload, local_port); | |
1677 | mlxsw_reg_svfa_mapping_table_set(payload, mt); | |
1678 | mlxsw_reg_svfa_v_set(payload, valid); | |
1679 | mlxsw_reg_svfa_fid_set(payload, fid); | |
1680 | mlxsw_reg_svfa_vid_set(payload, vid); | |
1681 | } | |
1682 | ||
1f65da74 IS |
1683 | /* SVPE - Switch Virtual-Port Enabling Register |
1684 | * -------------------------------------------- | |
1685 | * Enables port virtualization. | |
1686 | */ | |
1687 | #define MLXSW_REG_SVPE_ID 0x201E | |
1688 | #define MLXSW_REG_SVPE_LEN 0x4 | |
1689 | ||
21978dcf | 1690 | MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); |
1f65da74 IS |
1691 | |
1692 | /* reg_svpe_local_port | |
1693 | * Local port number | |
1694 | * Access: Index | |
1695 | * | |
1696 | * Note: CPU port is not supported (uses VLAN mode only). | |
1697 | */ | |
1698 | MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); | |
1699 | ||
1700 | /* reg_svpe_vp_en | |
1701 | * Virtual port enable. | |
1702 | * 0 - Disable, VLAN mode (VID to FID). | |
1703 | * 1 - Enable, Virtual port mode ({Port, VID} to FID). | |
1704 | * Access: RW | |
1705 | */ | |
1706 | MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); | |
1707 | ||
1708 | static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, | |
1709 | bool enable) | |
1710 | { | |
1711 | MLXSW_REG_ZERO(svpe, payload); | |
1712 | mlxsw_reg_svpe_local_port_set(payload, local_port); | |
1713 | mlxsw_reg_svpe_vp_en_set(payload, enable); | |
1714 | } | |
1715 | ||
f1fb693a IS |
1716 | /* SFMR - Switch FID Management Register |
1717 | * ------------------------------------- | |
1718 | * Creates and configures FIDs. | |
1719 | */ | |
1720 | #define MLXSW_REG_SFMR_ID 0x201F | |
1721 | #define MLXSW_REG_SFMR_LEN 0x18 | |
1722 | ||
21978dcf | 1723 | MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); |
f1fb693a IS |
1724 | |
1725 | enum mlxsw_reg_sfmr_op { | |
1726 | MLXSW_REG_SFMR_OP_CREATE_FID, | |
1727 | MLXSW_REG_SFMR_OP_DESTROY_FID, | |
1728 | }; | |
1729 | ||
1730 | /* reg_sfmr_op | |
1731 | * Operation. | |
1732 | * 0 - Create or edit FID. | |
1733 | * 1 - Destroy FID. | |
1734 | * Access: WO | |
1735 | */ | |
1736 | MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); | |
1737 | ||
1738 | /* reg_sfmr_fid | |
1739 | * Filtering ID. | |
1740 | * Access: Index | |
1741 | */ | |
1742 | MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); | |
1743 | ||
1744 | /* reg_sfmr_fid_offset | |
1745 | * FID offset. | |
1746 | * Used to point into the flooding table selected by SFGC register if | |
1747 | * the table is of type FID-Offset. Otherwise, this field is reserved. | |
1748 | * Access: RW | |
1749 | */ | |
1750 | MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); | |
1751 | ||
1752 | /* reg_sfmr_vtfp | |
1753 | * Valid Tunnel Flood Pointer. | |
1754 | * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. | |
1755 | * Access: RW | |
1756 | * | |
1757 | * Note: Reserved for 802.1Q FIDs. | |
1758 | */ | |
1759 | MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); | |
1760 | ||
1761 | /* reg_sfmr_nve_tunnel_flood_ptr | |
1762 | * Underlay Flooding and BC Pointer. | |
1763 | * Used as a pointer to the first entry of the group based link lists of | |
1764 | * flooding or BC entries (for NVE tunnels). | |
1765 | * Access: RW | |
1766 | */ | |
1767 | MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); | |
1768 | ||
1769 | /* reg_sfmr_vv | |
1770 | * VNI Valid. | |
1771 | * If not set, then vni is reserved. | |
1772 | * Access: RW | |
1773 | * | |
1774 | * Note: Reserved for 802.1Q FIDs. | |
1775 | */ | |
1776 | MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); | |
1777 | ||
1778 | /* reg_sfmr_vni | |
1779 | * Virtual Network Identifier. | |
1780 | * Access: RW | |
1781 | * | |
1782 | * Note: A given VNI can only be assigned to one FID. | |
1783 | */ | |
1784 | MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); | |
1785 | ||
1786 | static inline void mlxsw_reg_sfmr_pack(char *payload, | |
1787 | enum mlxsw_reg_sfmr_op op, u16 fid, | |
1788 | u16 fid_offset) | |
1789 | { | |
1790 | MLXSW_REG_ZERO(sfmr, payload); | |
1791 | mlxsw_reg_sfmr_op_set(payload, op); | |
1792 | mlxsw_reg_sfmr_fid_set(payload, fid); | |
1793 | mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); | |
1794 | mlxsw_reg_sfmr_vtfp_set(payload, false); | |
1795 | mlxsw_reg_sfmr_vv_set(payload, false); | |
1796 | } | |
1797 | ||
a4feea74 IS |
1798 | /* SPVMLR - Switch Port VLAN MAC Learning Register |
1799 | * ----------------------------------------------- | |
1800 | * Controls the switch MAC learning policy per {Port, VID}. | |
1801 | */ | |
1802 | #define MLXSW_REG_SPVMLR_ID 0x2020 | |
1803 | #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ | |
1804 | #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ | |
e9093b11 | 1805 | #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 |
a4feea74 IS |
1806 | #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ |
1807 | MLXSW_REG_SPVMLR_REC_LEN * \ | |
1808 | MLXSW_REG_SPVMLR_REC_MAX_COUNT) | |
1809 | ||
21978dcf | 1810 | MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); |
a4feea74 IS |
1811 | |
1812 | /* reg_spvmlr_local_port | |
1813 | * Local ingress port. | |
1814 | * Access: Index | |
1815 | * | |
1816 | * Note: CPU port is not supported. | |
1817 | */ | |
1818 | MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); | |
1819 | ||
1820 | /* reg_spvmlr_num_rec | |
1821 | * Number of records to update. | |
1822 | * Access: OP | |
1823 | */ | |
1824 | MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); | |
1825 | ||
1826 | /* reg_spvmlr_rec_learn_enable | |
1827 | * 0 - Disable learning for {Port, VID}. | |
1828 | * 1 - Enable learning for {Port, VID}. | |
1829 | * Access: RW | |
1830 | */ | |
1831 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, | |
1832 | 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1833 | ||
1834 | /* reg_spvmlr_rec_vid | |
1835 | * VLAN ID to be added/removed from port or for querying. | |
1836 | * Access: Index | |
1837 | */ | |
1838 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, | |
1839 | MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1840 | ||
1841 | static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, | |
1842 | u16 vid_begin, u16 vid_end, | |
1843 | bool learn_enable) | |
1844 | { | |
1845 | int num_rec = vid_end - vid_begin + 1; | |
1846 | int i; | |
1847 | ||
1848 | WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); | |
1849 | ||
1850 | MLXSW_REG_ZERO(spvmlr, payload); | |
1851 | mlxsw_reg_spvmlr_local_port_set(payload, local_port); | |
1852 | mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); | |
1853 | ||
1854 | for (i = 0; i < num_rec; i++) { | |
1855 | mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); | |
1856 | mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); | |
1857 | } | |
1858 | } | |
1859 | ||
ad53fa06 NF |
1860 | /* CWTP - Congetion WRED ECN TClass Profile |
1861 | * ---------------------------------------- | |
1862 | * Configures the profiles for queues of egress port and traffic class | |
1863 | */ | |
1864 | #define MLXSW_REG_CWTP_ID 0x2802 | |
1865 | #define MLXSW_REG_CWTP_BASE_LEN 0x28 | |
1866 | #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 | |
1867 | #define MLXSW_REG_CWTP_LEN 0x40 | |
1868 | ||
1869 | MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); | |
1870 | ||
1871 | /* reg_cwtp_local_port | |
1872 | * Local port number | |
1873 | * Not supported for CPU port | |
1874 | * Access: Index | |
1875 | */ | |
1876 | MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); | |
1877 | ||
1878 | /* reg_cwtp_traffic_class | |
1879 | * Traffic Class to configure | |
1880 | * Access: Index | |
1881 | */ | |
1882 | MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); | |
1883 | ||
1884 | /* reg_cwtp_profile_min | |
1885 | * Minimum Average Queue Size of the profile in cells. | |
1886 | * Access: RW | |
1887 | */ | |
1888 | MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, | |
1889 | 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); | |
1890 | ||
1891 | /* reg_cwtp_profile_percent | |
1892 | * Percentage of WRED and ECN marking for maximum Average Queue size | |
1893 | * Range is 0 to 100, units of integer percentage | |
1894 | * Access: RW | |
1895 | */ | |
1896 | MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, | |
1897 | 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); | |
1898 | ||
1899 | /* reg_cwtp_profile_max | |
1900 | * Maximum Average Queue size of the profile in cells | |
1901 | * Access: RW | |
1902 | */ | |
1903 | MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, | |
1904 | 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); | |
1905 | ||
1906 | #define MLXSW_REG_CWTP_MIN_VALUE 64 | |
1907 | #define MLXSW_REG_CWTP_MAX_PROFILE 2 | |
1908 | #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 | |
1909 | ||
1910 | static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, | |
1911 | u8 traffic_class) | |
1912 | { | |
1913 | int i; | |
1914 | ||
1915 | MLXSW_REG_ZERO(cwtp, payload); | |
1916 | mlxsw_reg_cwtp_local_port_set(payload, local_port); | |
1917 | mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); | |
1918 | ||
1919 | for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { | |
1920 | mlxsw_reg_cwtp_profile_min_set(payload, i, | |
1921 | MLXSW_REG_CWTP_MIN_VALUE); | |
1922 | mlxsw_reg_cwtp_profile_max_set(payload, i, | |
1923 | MLXSW_REG_CWTP_MIN_VALUE); | |
1924 | } | |
1925 | } | |
1926 | ||
1927 | #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) | |
1928 | ||
1929 | static inline void | |
1930 | mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, | |
1931 | u32 probability) | |
1932 | { | |
1933 | u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); | |
1934 | ||
1935 | mlxsw_reg_cwtp_profile_min_set(payload, index, min); | |
1936 | mlxsw_reg_cwtp_profile_max_set(payload, index, max); | |
1937 | mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); | |
1938 | } | |
1939 | ||
1940 | /* CWTPM - Congestion WRED ECN TClass and Pool Mapping | |
1941 | * --------------------------------------------------- | |
1942 | * The CWTPM register maps each egress port and traffic class to profile num. | |
1943 | */ | |
1944 | #define MLXSW_REG_CWTPM_ID 0x2803 | |
1945 | #define MLXSW_REG_CWTPM_LEN 0x44 | |
1946 | ||
1947 | MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); | |
1948 | ||
1949 | /* reg_cwtpm_local_port | |
1950 | * Local port number | |
1951 | * Not supported for CPU port | |
1952 | * Access: Index | |
1953 | */ | |
1954 | MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); | |
1955 | ||
1956 | /* reg_cwtpm_traffic_class | |
1957 | * Traffic Class to configure | |
1958 | * Access: Index | |
1959 | */ | |
1960 | MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); | |
1961 | ||
1962 | /* reg_cwtpm_ew | |
1963 | * Control enablement of WRED for traffic class: | |
1964 | * 0 - Disable | |
1965 | * 1 - Enable | |
1966 | * Access: RW | |
1967 | */ | |
1968 | MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); | |
1969 | ||
1970 | /* reg_cwtpm_ee | |
1971 | * Control enablement of ECN for traffic class: | |
1972 | * 0 - Disable | |
1973 | * 1 - Enable | |
1974 | * Access: RW | |
1975 | */ | |
1976 | MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); | |
1977 | ||
1978 | /* reg_cwtpm_tcp_g | |
1979 | * TCP Green Profile. | |
1980 | * Index of the profile within {port, traffic class} to use. | |
1981 | * 0 for disabling both WRED and ECN for this type of traffic. | |
1982 | * Access: RW | |
1983 | */ | |
1984 | MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); | |
1985 | ||
1986 | /* reg_cwtpm_tcp_y | |
1987 | * TCP Yellow Profile. | |
1988 | * Index of the profile within {port, traffic class} to use. | |
1989 | * 0 for disabling both WRED and ECN for this type of traffic. | |
1990 | * Access: RW | |
1991 | */ | |
1992 | MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); | |
1993 | ||
1994 | /* reg_cwtpm_tcp_r | |
1995 | * TCP Red Profile. | |
1996 | * Index of the profile within {port, traffic class} to use. | |
1997 | * 0 for disabling both WRED and ECN for this type of traffic. | |
1998 | * Access: RW | |
1999 | */ | |
2000 | MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); | |
2001 | ||
2002 | /* reg_cwtpm_ntcp_g | |
2003 | * Non-TCP Green Profile. | |
2004 | * Index of the profile within {port, traffic class} to use. | |
2005 | * 0 for disabling both WRED and ECN for this type of traffic. | |
2006 | * Access: RW | |
2007 | */ | |
2008 | MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); | |
2009 | ||
2010 | /* reg_cwtpm_ntcp_y | |
2011 | * Non-TCP Yellow Profile. | |
2012 | * Index of the profile within {port, traffic class} to use. | |
2013 | * 0 for disabling both WRED and ECN for this type of traffic. | |
2014 | * Access: RW | |
2015 | */ | |
2016 | MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); | |
2017 | ||
2018 | /* reg_cwtpm_ntcp_r | |
2019 | * Non-TCP Red Profile. | |
2020 | * Index of the profile within {port, traffic class} to use. | |
2021 | * 0 for disabling both WRED and ECN for this type of traffic. | |
2022 | * Access: RW | |
2023 | */ | |
2024 | MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); | |
2025 | ||
2026 | #define MLXSW_REG_CWTPM_RESET_PROFILE 0 | |
2027 | ||
2028 | static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, | |
2029 | u8 traffic_class, u8 profile, | |
2030 | bool wred, bool ecn) | |
2031 | { | |
2032 | MLXSW_REG_ZERO(cwtpm, payload); | |
2033 | mlxsw_reg_cwtpm_local_port_set(payload, local_port); | |
2034 | mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); | |
2035 | mlxsw_reg_cwtpm_ew_set(payload, wred); | |
2036 | mlxsw_reg_cwtpm_ee_set(payload, ecn); | |
2037 | mlxsw_reg_cwtpm_tcp_g_set(payload, profile); | |
2038 | mlxsw_reg_cwtpm_tcp_y_set(payload, profile); | |
2039 | mlxsw_reg_cwtpm_tcp_r_set(payload, profile); | |
2040 | mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); | |
2041 | mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); | |
2042 | mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); | |
2043 | } | |
2044 | ||
7050f439 IS |
2045 | /* PGCR - Policy-Engine General Configuration Register |
2046 | * --------------------------------------------------- | |
2047 | * This register configures general Policy-Engine settings. | |
2048 | */ | |
2049 | #define MLXSW_REG_PGCR_ID 0x3001 | |
2050 | #define MLXSW_REG_PGCR_LEN 0x20 | |
2051 | ||
2052 | MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); | |
2053 | ||
2054 | /* reg_pgcr_default_action_pointer_base | |
2055 | * Default action pointer base. Each region has a default action pointer | |
2056 | * which is equal to default_action_pointer_base + region_id. | |
2057 | * Access: RW | |
2058 | */ | |
2059 | MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); | |
2060 | ||
2061 | static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) | |
2062 | { | |
2063 | MLXSW_REG_ZERO(pgcr, payload); | |
2064 | mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); | |
2065 | } | |
2066 | ||
af7170ee JP |
2067 | /* PPBT - Policy-Engine Port Binding Table |
2068 | * --------------------------------------- | |
2069 | * This register is used for configuration of the Port Binding Table. | |
2070 | */ | |
2071 | #define MLXSW_REG_PPBT_ID 0x3002 | |
2072 | #define MLXSW_REG_PPBT_LEN 0x14 | |
2073 | ||
2074 | MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); | |
2075 | ||
2076 | enum mlxsw_reg_pxbt_e { | |
2077 | MLXSW_REG_PXBT_E_IACL, | |
2078 | MLXSW_REG_PXBT_E_EACL, | |
2079 | }; | |
2080 | ||
2081 | /* reg_ppbt_e | |
2082 | * Access: Index | |
2083 | */ | |
2084 | MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); | |
2085 | ||
2086 | enum mlxsw_reg_pxbt_op { | |
2087 | MLXSW_REG_PXBT_OP_BIND, | |
2088 | MLXSW_REG_PXBT_OP_UNBIND, | |
2089 | }; | |
2090 | ||
2091 | /* reg_ppbt_op | |
2092 | * Access: RW | |
2093 | */ | |
2094 | MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); | |
2095 | ||
2096 | /* reg_ppbt_local_port | |
2097 | * Local port. Not including CPU port. | |
2098 | * Access: Index | |
2099 | */ | |
2100 | MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); | |
2101 | ||
2102 | /* reg_ppbt_g | |
2103 | * group - When set, the binding is of an ACL group. When cleared, | |
2104 | * the binding is of an ACL. | |
2105 | * Must be set to 1 for Spectrum. | |
2106 | * Access: RW | |
2107 | */ | |
2108 | MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); | |
2109 | ||
2110 | /* reg_ppbt_acl_info | |
2111 | * ACL/ACL group identifier. If the g bit is set, this field should hold | |
2112 | * the acl_group_id, else it should hold the acl_id. | |
2113 | * Access: RW | |
2114 | */ | |
2115 | MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); | |
2116 | ||
2117 | static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, | |
2118 | enum mlxsw_reg_pxbt_op op, | |
2119 | u8 local_port, u16 acl_info) | |
2120 | { | |
2121 | MLXSW_REG_ZERO(ppbt, payload); | |
2122 | mlxsw_reg_ppbt_e_set(payload, e); | |
2123 | mlxsw_reg_ppbt_op_set(payload, op); | |
2124 | mlxsw_reg_ppbt_local_port_set(payload, local_port); | |
2125 | mlxsw_reg_ppbt_g_set(payload, true); | |
2126 | mlxsw_reg_ppbt_acl_info_set(payload, acl_info); | |
2127 | } | |
2128 | ||
3279da4c JP |
2129 | /* PACL - Policy-Engine ACL Register |
2130 | * --------------------------------- | |
2131 | * This register is used for configuration of the ACL. | |
2132 | */ | |
2133 | #define MLXSW_REG_PACL_ID 0x3004 | |
2134 | #define MLXSW_REG_PACL_LEN 0x70 | |
2135 | ||
2136 | MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); | |
2137 | ||
2138 | /* reg_pacl_v | |
2139 | * Valid. Setting the v bit makes the ACL valid. It should not be cleared | |
2140 | * while the ACL is bounded to either a port, VLAN or ACL rule. | |
2141 | * Access: RW | |
2142 | */ | |
2143 | MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); | |
2144 | ||
2145 | /* reg_pacl_acl_id | |
2146 | * An identifier representing the ACL (managed by software) | |
2147 | * Range 0 .. cap_max_acl_regions - 1 | |
2148 | * Access: Index | |
2149 | */ | |
2150 | MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); | |
2151 | ||
2152 | #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 | |
2153 | ||
2154 | /* reg_pacl_tcam_region_info | |
2155 | * Opaque object that represents a TCAM region. | |
2156 | * Obtained through PTAR register. | |
2157 | * Access: RW | |
2158 | */ | |
2159 | MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, | |
2160 | MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); | |
2161 | ||
2162 | static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, | |
2163 | bool valid, const char *tcam_region_info) | |
2164 | { | |
2165 | MLXSW_REG_ZERO(pacl, payload); | |
2166 | mlxsw_reg_pacl_acl_id_set(payload, acl_id); | |
2167 | mlxsw_reg_pacl_v_set(payload, valid); | |
2168 | mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); | |
2169 | } | |
2170 | ||
10fabef5 JP |
2171 | /* PAGT - Policy-Engine ACL Group Table |
2172 | * ------------------------------------ | |
2173 | * This register is used for configuration of the ACL Group Table. | |
2174 | */ | |
2175 | #define MLXSW_REG_PAGT_ID 0x3005 | |
2176 | #define MLXSW_REG_PAGT_BASE_LEN 0x30 | |
2177 | #define MLXSW_REG_PAGT_ACL_LEN 4 | |
2178 | #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 | |
2179 | #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ | |
2180 | MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) | |
2181 | ||
2182 | MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); | |
2183 | ||
2184 | /* reg_pagt_size | |
2185 | * Number of ACLs in the group. | |
2186 | * Size 0 invalidates a group. | |
2187 | * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) | |
2188 | * Total number of ACLs in all groups must be lower or equal | |
2189 | * to cap_max_acl_tot_groups | |
2190 | * Note: a group which is binded must not be invalidated | |
2191 | * Access: Index | |
2192 | */ | |
2193 | MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); | |
2194 | ||
2195 | /* reg_pagt_acl_group_id | |
2196 | * An identifier (numbered from 0..cap_max_acl_groups-1) representing | |
2197 | * the ACL Group identifier (managed by software). | |
2198 | * Access: Index | |
2199 | */ | |
2200 | MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); | |
2201 | ||
5c661f14 JP |
2202 | /* reg_pagt_multi |
2203 | * Multi-ACL | |
2204 | * 0 - This ACL is the last ACL in the multi-ACL | |
2205 | * 1 - This ACL is part of a multi-ACL | |
2206 | * Access: RW | |
2207 | */ | |
2208 | MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); | |
2209 | ||
10fabef5 JP |
2210 | /* reg_pagt_acl_id |
2211 | * ACL identifier | |
2212 | * Access: RW | |
2213 | */ | |
2214 | MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); | |
2215 | ||
2216 | static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) | |
2217 | { | |
2218 | MLXSW_REG_ZERO(pagt, payload); | |
2219 | mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); | |
2220 | } | |
2221 | ||
2222 | static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, | |
5c661f14 | 2223 | u16 acl_id, bool multi) |
10fabef5 JP |
2224 | { |
2225 | u8 size = mlxsw_reg_pagt_size_get(payload); | |
2226 | ||
2227 | if (index >= size) | |
2228 | mlxsw_reg_pagt_size_set(payload, index + 1); | |
5c661f14 | 2229 | mlxsw_reg_pagt_multi_set(payload, index, multi); |
10fabef5 JP |
2230 | mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); |
2231 | } | |
2232 | ||
d9c2661e JP |
2233 | /* PTAR - Policy-Engine TCAM Allocation Register |
2234 | * --------------------------------------------- | |
2235 | * This register is used for allocation of regions in the TCAM. | |
2236 | * Note: Query method is not supported on this register. | |
2237 | */ | |
2238 | #define MLXSW_REG_PTAR_ID 0x3006 | |
2239 | #define MLXSW_REG_PTAR_BASE_LEN 0x20 | |
2240 | #define MLXSW_REG_PTAR_KEY_ID_LEN 1 | |
2241 | #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 | |
2242 | #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ | |
2243 | MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) | |
2244 | ||
2245 | MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); | |
2246 | ||
2247 | enum mlxsw_reg_ptar_op { | |
2248 | /* allocate a TCAM region */ | |
2249 | MLXSW_REG_PTAR_OP_ALLOC, | |
2250 | /* resize a TCAM region */ | |
2251 | MLXSW_REG_PTAR_OP_RESIZE, | |
2252 | /* deallocate TCAM region */ | |
2253 | MLXSW_REG_PTAR_OP_FREE, | |
2254 | /* test allocation */ | |
2255 | MLXSW_REG_PTAR_OP_TEST, | |
2256 | }; | |
2257 | ||
2258 | /* reg_ptar_op | |
2259 | * Access: OP | |
2260 | */ | |
2261 | MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); | |
2262 | ||
2263 | /* reg_ptar_action_set_type | |
2264 | * Type of action set to be used on this region. | |
45e0620d | 2265 | * For Spectrum and Spectrum-2, this is always type 2 - "flexible" |
d9c2661e JP |
2266 | * Access: WO |
2267 | */ | |
2268 | MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); | |
2269 | ||
45e0620d JP |
2270 | enum mlxsw_reg_ptar_key_type { |
2271 | MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ | |
2272 | MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ | |
2273 | }; | |
2274 | ||
d9c2661e JP |
2275 | /* reg_ptar_key_type |
2276 | * TCAM key type for the region. | |
d9c2661e JP |
2277 | * Access: WO |
2278 | */ | |
2279 | MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); | |
2280 | ||
2281 | /* reg_ptar_region_size | |
2282 | * TCAM region size. When allocating/resizing this is the requested size, | |
2283 | * the response is the actual size. Note that actual size may be | |
2284 | * larger than requested. | |
2285 | * Allowed range 1 .. cap_max_rules-1 | |
2286 | * Reserved during op deallocate. | |
2287 | * Access: WO | |
2288 | */ | |
2289 | MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); | |
2290 | ||
2291 | /* reg_ptar_region_id | |
2292 | * Region identifier | |
2293 | * Range 0 .. cap_max_regions-1 | |
2294 | * Access: Index | |
2295 | */ | |
2296 | MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); | |
2297 | ||
2298 | /* reg_ptar_tcam_region_info | |
2299 | * Opaque object that represents the TCAM region. | |
2300 | * Returned when allocating a region. | |
2301 | * Provided by software for ACL generation and region deallocation and resize. | |
2302 | * Access: RW | |
2303 | */ | |
2304 | MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, | |
2305 | MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); | |
2306 | ||
2307 | /* reg_ptar_flexible_key_id | |
2308 | * Identifier of the Flexible Key. | |
2309 | * Only valid if key_type == "FLEX_KEY" | |
2310 | * The key size will be rounded up to one of the following values: | |
2311 | * 9B, 18B, 36B, 54B. | |
2312 | * This field is reserved for in resize operation. | |
2313 | * Access: WO | |
2314 | */ | |
2315 | MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, | |
2316 | MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); | |
2317 | ||
2318 | static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, | |
45e0620d | 2319 | enum mlxsw_reg_ptar_key_type key_type, |
d9c2661e JP |
2320 | u16 region_size, u16 region_id, |
2321 | const char *tcam_region_info) | |
2322 | { | |
2323 | MLXSW_REG_ZERO(ptar, payload); | |
2324 | mlxsw_reg_ptar_op_set(payload, op); | |
2325 | mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ | |
45e0620d | 2326 | mlxsw_reg_ptar_key_type_set(payload, key_type); |
d9c2661e JP |
2327 | mlxsw_reg_ptar_region_size_set(payload, region_size); |
2328 | mlxsw_reg_ptar_region_id_set(payload, region_id); | |
2329 | mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); | |
2330 | } | |
2331 | ||
2332 | static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, | |
2333 | u16 key_id) | |
2334 | { | |
2335 | mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); | |
2336 | } | |
2337 | ||
2338 | static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) | |
2339 | { | |
2340 | mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); | |
2341 | } | |
2342 | ||
d120649d JP |
2343 | /* PPBS - Policy-Engine Policy Based Switching Register |
2344 | * ---------------------------------------------------- | |
2345 | * This register retrieves and sets Policy Based Switching Table entries. | |
2346 | */ | |
2347 | #define MLXSW_REG_PPBS_ID 0x300C | |
2348 | #define MLXSW_REG_PPBS_LEN 0x14 | |
2349 | ||
2350 | MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); | |
2351 | ||
2352 | /* reg_ppbs_pbs_ptr | |
2353 | * Index into the PBS table. | |
2354 | * For Spectrum, the index points to the KVD Linear. | |
2355 | * Access: Index | |
2356 | */ | |
2357 | MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); | |
2358 | ||
2359 | /* reg_ppbs_system_port | |
2360 | * Unique port identifier for the final destination of the packet. | |
2361 | * Access: RW | |
2362 | */ | |
2363 | MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); | |
2364 | ||
2365 | static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, | |
2366 | u16 system_port) | |
2367 | { | |
2368 | MLXSW_REG_ZERO(ppbs, payload); | |
2369 | mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); | |
2370 | mlxsw_reg_ppbs_system_port_set(payload, system_port); | |
2371 | } | |
2372 | ||
937b682c JP |
2373 | /* PRCR - Policy-Engine Rules Copy Register |
2374 | * ---------------------------------------- | |
2375 | * This register is used for accessing rules within a TCAM region. | |
2376 | */ | |
2377 | #define MLXSW_REG_PRCR_ID 0x300D | |
2378 | #define MLXSW_REG_PRCR_LEN 0x40 | |
2379 | ||
2380 | MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); | |
2381 | ||
2382 | enum mlxsw_reg_prcr_op { | |
2383 | /* Move rules. Moves the rules from "tcam_region_info" starting | |
2384 | * at offset "offset" to "dest_tcam_region_info" | |
2385 | * at offset "dest_offset." | |
2386 | */ | |
2387 | MLXSW_REG_PRCR_OP_MOVE, | |
2388 | /* Copy rules. Copies the rules from "tcam_region_info" starting | |
2389 | * at offset "offset" to "dest_tcam_region_info" | |
2390 | * at offset "dest_offset." | |
2391 | */ | |
2392 | MLXSW_REG_PRCR_OP_COPY, | |
2393 | }; | |
2394 | ||
2395 | /* reg_prcr_op | |
2396 | * Access: OP | |
2397 | */ | |
2398 | MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); | |
2399 | ||
2400 | /* reg_prcr_offset | |
2401 | * Offset within the source region to copy/move from. | |
2402 | * Access: Index | |
2403 | */ | |
2404 | MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); | |
2405 | ||
2406 | /* reg_prcr_size | |
2407 | * The number of rules to copy/move. | |
2408 | * Access: WO | |
2409 | */ | |
2410 | MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); | |
2411 | ||
2412 | /* reg_prcr_tcam_region_info | |
2413 | * Opaque object that represents the source TCAM region. | |
2414 | * Access: Index | |
2415 | */ | |
2416 | MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, | |
2417 | MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); | |
2418 | ||
2419 | /* reg_prcr_dest_offset | |
2420 | * Offset within the source region to copy/move to. | |
2421 | * Access: Index | |
2422 | */ | |
2423 | MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); | |
2424 | ||
2425 | /* reg_prcr_dest_tcam_region_info | |
2426 | * Opaque object that represents the destination TCAM region. | |
2427 | * Access: Index | |
2428 | */ | |
2429 | MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, | |
2430 | MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); | |
2431 | ||
2432 | static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, | |
2433 | const char *src_tcam_region_info, | |
2434 | u16 src_offset, | |
2435 | const char *dest_tcam_region_info, | |
2436 | u16 dest_offset, u16 size) | |
2437 | { | |
2438 | MLXSW_REG_ZERO(prcr, payload); | |
2439 | mlxsw_reg_prcr_op_set(payload, op); | |
2440 | mlxsw_reg_prcr_offset_set(payload, src_offset); | |
2441 | mlxsw_reg_prcr_size_set(payload, size); | |
2442 | mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, | |
2443 | src_tcam_region_info); | |
2444 | mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); | |
2445 | mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, | |
2446 | dest_tcam_region_info); | |
2447 | } | |
2448 | ||
e3426e12 JP |
2449 | /* PEFA - Policy-Engine Extended Flexible Action Register |
2450 | * ------------------------------------------------------ | |
2451 | * This register is used for accessing an extended flexible action entry | |
2452 | * in the central KVD Linear Database. | |
2453 | */ | |
2454 | #define MLXSW_REG_PEFA_ID 0x300F | |
2455 | #define MLXSW_REG_PEFA_LEN 0xB0 | |
2456 | ||
2457 | MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); | |
2458 | ||
2459 | /* reg_pefa_index | |
2460 | * Index in the KVD Linear Centralized Database. | |
2461 | * Access: Index | |
2462 | */ | |
2463 | MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); | |
2464 | ||
2d186ed4 JP |
2465 | /* reg_pefa_a |
2466 | * Index in the KVD Linear Centralized Database. | |
2467 | * Activity | |
2468 | * For a new entry: set if ca=0, clear if ca=1 | |
2469 | * Set if a packet lookup has hit on the specific entry | |
2470 | * Access: RO | |
2471 | */ | |
2472 | MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); | |
2473 | ||
2474 | /* reg_pefa_ca | |
2475 | * Clear activity | |
2476 | * When write: activity is according to this field | |
2477 | * When read: after reading the activity is cleared according to ca | |
2478 | * Access: OP | |
2479 | */ | |
2480 | MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); | |
2481 | ||
58726565 | 2482 | #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 |
e3426e12 JP |
2483 | |
2484 | /* reg_pefa_flex_action_set | |
2485 | * Action-set to perform when rule is matched. | |
2486 | * Must be zero padded if action set is shorter. | |
2487 | * Access: RW | |
2488 | */ | |
58726565 | 2489 | MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); |
e3426e12 | 2490 | |
2d186ed4 | 2491 | static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, |
e3426e12 JP |
2492 | const char *flex_action_set) |
2493 | { | |
2494 | MLXSW_REG_ZERO(pefa, payload); | |
2495 | mlxsw_reg_pefa_index_set(payload, index); | |
2d186ed4 JP |
2496 | mlxsw_reg_pefa_ca_set(payload, ca); |
2497 | if (flex_action_set) | |
2498 | mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, | |
2499 | flex_action_set); | |
2500 | } | |
2501 | ||
2502 | static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) | |
2503 | { | |
2504 | *p_a = mlxsw_reg_pefa_a_get(payload); | |
e3426e12 JP |
2505 | } |
2506 | ||
a75e41d3 ND |
2507 | /* PEMRBT - Policy-Engine Multicast Router Binding Table Register |
2508 | * -------------------------------------------------------------- | |
2509 | * This register is used for binding Multicast router to an ACL group | |
2510 | * that serves the MC router. | |
2511 | * This register is not supported by SwitchX/-2 and Spectrum. | |
2512 | */ | |
2513 | #define MLXSW_REG_PEMRBT_ID 0x3014 | |
2514 | #define MLXSW_REG_PEMRBT_LEN 0x14 | |
2515 | ||
2516 | MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); | |
2517 | ||
2518 | enum mlxsw_reg_pemrbt_protocol { | |
2519 | MLXSW_REG_PEMRBT_PROTO_IPV4, | |
2520 | MLXSW_REG_PEMRBT_PROTO_IPV6, | |
2521 | }; | |
2522 | ||
2523 | /* reg_pemrbt_protocol | |
2524 | * Access: Index | |
2525 | */ | |
2526 | MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); | |
2527 | ||
2528 | /* reg_pemrbt_group_id | |
2529 | * ACL group identifier. | |
2530 | * Range 0..cap_max_acl_groups-1 | |
2531 | * Access: RW | |
2532 | */ | |
2533 | MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); | |
2534 | ||
2535 | static inline void | |
2536 | mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, | |
2537 | u16 group_id) | |
2538 | { | |
2539 | MLXSW_REG_ZERO(pemrbt, payload); | |
2540 | mlxsw_reg_pemrbt_protocol_set(payload, protocol); | |
2541 | mlxsw_reg_pemrbt_group_id_set(payload, group_id); | |
2542 | } | |
2543 | ||
0171cdec JP |
2544 | /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 |
2545 | * ----------------------------------------------------- | |
2546 | * This register is used for accessing rules within a TCAM region. | |
2547 | * It is a new version of PTCE in order to support wider key, | |
2548 | * mask and action within a TCAM region. This register is not supported | |
2549 | * by SwitchX and SwitchX-2. | |
2550 | */ | |
2551 | #define MLXSW_REG_PTCE2_ID 0x3017 | |
2552 | #define MLXSW_REG_PTCE2_LEN 0x1D8 | |
2553 | ||
2554 | MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); | |
2555 | ||
2556 | /* reg_ptce2_v | |
2557 | * Valid. | |
2558 | * Access: RW | |
2559 | */ | |
2560 | MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); | |
2561 | ||
2562 | /* reg_ptce2_a | |
2563 | * Activity. Set if a packet lookup has hit on the specific entry. | |
2564 | * To clear the "a" bit, use "clear activity" op or "clear on read" op. | |
2565 | * Access: RO | |
2566 | */ | |
2567 | MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); | |
2568 | ||
2569 | enum mlxsw_reg_ptce2_op { | |
2570 | /* Read operation. */ | |
2571 | MLXSW_REG_PTCE2_OP_QUERY_READ = 0, | |
2572 | /* clear on read operation. Used to read entry | |
2573 | * and clear Activity bit. | |
2574 | */ | |
2575 | MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, | |
2576 | /* Write operation. Used to write a new entry to the table. | |
2577 | * All R/W fields are relevant for new entry. Activity bit is set | |
2578 | * for new entries - Note write with v = 0 will delete the entry. | |
2579 | */ | |
2580 | MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, | |
2581 | /* Update action. Only action set will be updated. */ | |
2582 | MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, | |
2583 | /* Clear activity. A bit is cleared for the entry. */ | |
2584 | MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, | |
2585 | }; | |
2586 | ||
2587 | /* reg_ptce2_op | |
2588 | * Access: OP | |
2589 | */ | |
2590 | MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); | |
2591 | ||
2592 | /* reg_ptce2_offset | |
2593 | * Access: Index | |
2594 | */ | |
2595 | MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); | |
2596 | ||
42df8358 JP |
2597 | /* reg_ptce2_priority |
2598 | * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. | |
2599 | * Note: priority does not have to be unique per rule. | |
2600 | * Within a region, higher priority should have lower offset (no limitation | |
2601 | * between regions in a multi-region). | |
2602 | * Access: RW | |
2603 | */ | |
2604 | MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); | |
2605 | ||
0171cdec JP |
2606 | /* reg_ptce2_tcam_region_info |
2607 | * Opaque object that represents the TCAM region. | |
2608 | * Access: Index | |
2609 | */ | |
2610 | MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, | |
2611 | MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); | |
2612 | ||
aecefac9 | 2613 | #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 |
0171cdec JP |
2614 | |
2615 | /* reg_ptce2_flex_key_blocks | |
2616 | * ACL Key. | |
2617 | * Access: RW | |
2618 | */ | |
2619 | MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, | |
aecefac9 | 2620 | MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); |
0171cdec JP |
2621 | |
2622 | /* reg_ptce2_mask | |
2623 | * mask- in the same size as key. A bit that is set directs the TCAM | |
2624 | * to compare the corresponding bit in key. A bit that is clear directs | |
2625 | * the TCAM to ignore the corresponding bit in key. | |
2626 | * Access: RW | |
2627 | */ | |
2628 | MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, | |
aecefac9 | 2629 | MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); |
0171cdec | 2630 | |
0171cdec JP |
2631 | /* reg_ptce2_flex_action_set |
2632 | * ACL action set. | |
2633 | * Access: RW | |
2634 | */ | |
2635 | MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, | |
58726565 | 2636 | MLXSW_REG_FLEX_ACTION_SET_LEN); |
0171cdec JP |
2637 | |
2638 | static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, | |
2639 | enum mlxsw_reg_ptce2_op op, | |
2640 | const char *tcam_region_info, | |
42df8358 | 2641 | u16 offset, u32 priority) |
0171cdec JP |
2642 | { |
2643 | MLXSW_REG_ZERO(ptce2, payload); | |
2644 | mlxsw_reg_ptce2_v_set(payload, valid); | |
2645 | mlxsw_reg_ptce2_op_set(payload, op); | |
2646 | mlxsw_reg_ptce2_offset_set(payload, offset); | |
42df8358 | 2647 | mlxsw_reg_ptce2_priority_set(payload, priority); |
0171cdec JP |
2648 | mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); |
2649 | } | |
2650 | ||
8c0d1cdd IS |
2651 | /* PERPT - Policy-Engine ERP Table Register |
2652 | * ---------------------------------------- | |
2653 | * This register adds and removes eRPs from the eRP table. | |
2654 | */ | |
2655 | #define MLXSW_REG_PERPT_ID 0x3021 | |
2656 | #define MLXSW_REG_PERPT_LEN 0x80 | |
2657 | ||
2658 | MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); | |
2659 | ||
2660 | /* reg_perpt_erpt_bank | |
2661 | * eRP table bank. | |
2662 | * Range 0 .. cap_max_erp_table_banks - 1 | |
2663 | * Access: Index | |
2664 | */ | |
2665 | MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); | |
2666 | ||
2667 | /* reg_perpt_erpt_index | |
2668 | * Index to eRP table within the eRP bank. | |
2669 | * Range is 0 .. cap_max_erp_table_bank_size - 1 | |
2670 | * Access: Index | |
2671 | */ | |
2672 | MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); | |
2673 | ||
2674 | enum mlxsw_reg_perpt_key_size { | |
2675 | MLXSW_REG_PERPT_KEY_SIZE_2KB, | |
2676 | MLXSW_REG_PERPT_KEY_SIZE_4KB, | |
2677 | MLXSW_REG_PERPT_KEY_SIZE_8KB, | |
2678 | MLXSW_REG_PERPT_KEY_SIZE_12KB, | |
2679 | }; | |
2680 | ||
2681 | /* reg_perpt_key_size | |
2682 | * Access: OP | |
2683 | */ | |
2684 | MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); | |
2685 | ||
2686 | /* reg_perpt_bf_bypass | |
2687 | * 0 - The eRP is used only if bloom filter state is set for the given | |
2688 | * rule. | |
2689 | * 1 - The eRP is used regardless of bloom filter state. | |
2690 | * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass | |
2691 | * Access: RW | |
2692 | */ | |
2693 | MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); | |
2694 | ||
2695 | /* reg_perpt_erp_id | |
2696 | * eRP ID for use by the rules. | |
2697 | * Access: RW | |
2698 | */ | |
2699 | MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); | |
2700 | ||
2701 | /* reg_perpt_erpt_base_bank | |
2702 | * Base eRP table bank, points to head of erp_vector | |
2703 | * Range is 0 .. cap_max_erp_table_banks - 1 | |
2704 | * Access: OP | |
2705 | */ | |
2706 | MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); | |
2707 | ||
2708 | /* reg_perpt_erpt_base_index | |
2709 | * Base index to eRP table within the eRP bank | |
2710 | * Range is 0 .. cap_max_erp_table_bank_size - 1 | |
2711 | * Access: OP | |
2712 | */ | |
2713 | MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); | |
2714 | ||
2715 | /* reg_perpt_erp_index_in_vector | |
2716 | * eRP index in the vector. | |
2717 | * Access: OP | |
2718 | */ | |
2719 | MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); | |
2720 | ||
2721 | /* reg_perpt_erp_vector | |
2722 | * eRP vector. | |
2723 | * Access: OP | |
2724 | */ | |
2725 | MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); | |
2726 | ||
2727 | /* reg_perpt_mask | |
2728 | * Mask | |
2729 | * 0 - A-TCAM will ignore the bit in key | |
2730 | * 1 - A-TCAM will compare the bit in key | |
2731 | * Access: RW | |
2732 | */ | |
2733 | MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); | |
2734 | ||
2735 | static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, | |
2736 | unsigned long *erp_vector, | |
2737 | unsigned long size) | |
2738 | { | |
2739 | unsigned long bit; | |
2740 | ||
2741 | for_each_set_bit(bit, erp_vector, size) | |
2742 | mlxsw_reg_perpt_erp_vector_set(payload, bit, true); | |
2743 | } | |
2744 | ||
2745 | static inline void | |
2746 | mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, | |
2747 | enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, | |
2748 | u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, | |
2749 | char *mask) | |
2750 | { | |
2751 | MLXSW_REG_ZERO(perpt, payload); | |
2752 | mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); | |
2753 | mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); | |
2754 | mlxsw_reg_perpt_key_size_set(payload, key_size); | |
03ce5bd1 | 2755 | mlxsw_reg_perpt_bf_bypass_set(payload, false); |
8c0d1cdd IS |
2756 | mlxsw_reg_perpt_erp_id_set(payload, erp_id); |
2757 | mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); | |
2758 | mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); | |
2759 | mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); | |
2760 | mlxsw_reg_perpt_mask_memcpy_to(payload, mask); | |
2761 | } | |
2762 | ||
3390787b JP |
2763 | /* PERAR - Policy-Engine Region Association Register |
2764 | * ------------------------------------------------- | |
2765 | * This register associates a hw region for region_id's. Changing on the fly | |
2766 | * is supported by the device. | |
2767 | */ | |
2768 | #define MLXSW_REG_PERAR_ID 0x3026 | |
2769 | #define MLXSW_REG_PERAR_LEN 0x08 | |
2770 | ||
2771 | MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); | |
2772 | ||
2773 | /* reg_perar_region_id | |
2774 | * Region identifier | |
2775 | * Range 0 .. cap_max_regions-1 | |
2776 | * Access: Index | |
2777 | */ | |
2778 | MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); | |
2779 | ||
2780 | static inline unsigned int | |
2781 | mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) | |
2782 | { | |
2783 | return DIV_ROUND_UP(block_num, 4); | |
2784 | } | |
2785 | ||
2786 | /* reg_perar_hw_region | |
2787 | * HW Region | |
2788 | * Range 0 .. cap_max_regions-1 | |
2789 | * Default: hw_region = region_id | |
2790 | * For a 8 key block region, 2 consecutive regions are used | |
2791 | * For a 12 key block region, 3 consecutive regions are used | |
2792 | * Access: RW | |
2793 | */ | |
2794 | MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); | |
2795 | ||
2796 | static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, | |
2797 | u16 hw_region) | |
2798 | { | |
2799 | MLXSW_REG_ZERO(perar, payload); | |
2800 | mlxsw_reg_perar_region_id_set(payload, region_id); | |
2801 | mlxsw_reg_perar_hw_region_set(payload, hw_region); | |
2802 | } | |
2803 | ||
aecefac9 IS |
2804 | /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 |
2805 | * ----------------------------------------------------- | |
2806 | * This register is a new version of PTCE-V2 in order to support the | |
2807 | * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. | |
2808 | */ | |
2809 | #define MLXSW_REG_PTCE3_ID 0x3027 | |
2810 | #define MLXSW_REG_PTCE3_LEN 0xF0 | |
2811 | ||
2812 | MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); | |
2813 | ||
2814 | /* reg_ptce3_v | |
2815 | * Valid. | |
2816 | * Access: RW | |
2817 | */ | |
2818 | MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); | |
2819 | ||
2820 | enum mlxsw_reg_ptce3_op { | |
2821 | /* Write operation. Used to write a new entry to the table. | |
2822 | * All R/W fields are relevant for new entry. Activity bit is set | |
2823 | * for new entries. Write with v = 0 will delete the entry. Must | |
2824 | * not be used if an entry exists. | |
2825 | */ | |
2826 | MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, | |
2827 | /* Update operation */ | |
2828 | MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, | |
2829 | /* Read operation */ | |
2830 | MLXSW_REG_PTCE3_OP_QUERY_READ = 0, | |
2831 | }; | |
2832 | ||
2833 | /* reg_ptce3_op | |
2834 | * Access: OP | |
2835 | */ | |
2836 | MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); | |
2837 | ||
2838 | /* reg_ptce3_priority | |
2839 | * Priority of the rule. Higher values win. | |
2840 | * For Spectrum-2 range is 1..cap_kvd_size - 1 | |
2841 | * Note: Priority does not have to be unique per rule. | |
2842 | * Access: RW | |
2843 | */ | |
2844 | MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); | |
2845 | ||
2846 | /* reg_ptce3_tcam_region_info | |
2847 | * Opaque object that represents the TCAM region. | |
2848 | * Access: Index | |
2849 | */ | |
2850 | MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, | |
2851 | MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); | |
2852 | ||
2853 | /* reg_ptce3_flex2_key_blocks | |
2854 | * ACL key. The key must be masked according to eRP (if exists) or | |
2855 | * according to master mask. | |
2856 | * Access: Index | |
2857 | */ | |
2858 | MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, | |
2859 | MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); | |
2860 | ||
2861 | /* reg_ptce3_erp_id | |
2862 | * eRP ID. | |
2863 | * Access: Index | |
2864 | */ | |
2865 | MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); | |
2866 | ||
2867 | /* reg_ptce3_delta_start | |
2868 | * Start point of delta_value and delta_mask, in bits. Must not exceed | |
2869 | * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. | |
2870 | * Access: Index | |
2871 | */ | |
2872 | MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); | |
2873 | ||
2874 | /* reg_ptce3_delta_mask | |
2875 | * Delta mask. | |
2876 | * 0 - Ignore relevant bit in delta_value | |
2877 | * 1 - Compare relevant bit in delta_value | |
2878 | * Delta mask must not be set for reserved fields in the key blocks. | |
2879 | * Note: No delta when no eRPs. Thus, for regions with | |
2880 | * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. | |
2881 | * Access: Index | |
2882 | */ | |
2883 | MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); | |
2884 | ||
2885 | /* reg_ptce3_delta_value | |
2886 | * Delta value. | |
2887 | * Bits which are masked by delta_mask must be 0. | |
2888 | * Access: Index | |
2889 | */ | |
2890 | MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); | |
2891 | ||
2892 | /* reg_ptce3_prune_vector | |
2893 | * Pruning vector relative to the PERPT.erp_id. | |
2894 | * Used for reducing lookups. | |
2895 | * 0 - NEED: Do a lookup using the eRP. | |
2896 | * 1 - PRUNE: Do not perform a lookup using the eRP. | |
2897 | * Maybe be modified by PEAPBL and PEAPBM. | |
2898 | * Note: In Spectrum-2, a region of 8 key blocks must be set to either | |
2899 | * all 1's or all 0's. | |
2900 | * Access: RW | |
2901 | */ | |
2902 | MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); | |
2903 | ||
2904 | /* reg_ptce3_prune_ctcam | |
2905 | * Pruning on C-TCAM. Used for reducing lookups. | |
2906 | * 0 - NEED: Do a lookup in the C-TCAM. | |
2907 | * 1 - PRUNE: Do not perform a lookup in the C-TCAM. | |
2908 | * Access: RW | |
2909 | */ | |
2910 | MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); | |
2911 | ||
2912 | /* reg_ptce3_large_exists | |
2913 | * Large entry key ID exists. | |
2914 | * Within the region: | |
2915 | * 0 - SINGLE: The large_entry_key_id is not currently in use. | |
2916 | * For rule insert: The MSB of the key (blocks 6..11) will be added. | |
2917 | * For rule delete: The MSB of the key will be removed. | |
2918 | * 1 - NON_SINGLE: The large_entry_key_id is currently in use. | |
2919 | * For rule insert: The MSB of the key (blocks 6..11) will not be added. | |
2920 | * For rule delete: The MSB of the key will not be removed. | |
2921 | * Access: WO | |
2922 | */ | |
2923 | MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); | |
2924 | ||
2925 | /* reg_ptce3_large_entry_key_id | |
2926 | * Large entry key ID. | |
2927 | * A key for 12 key blocks rules. Reserved when region has less than 12 key | |
2928 | * blocks. Must be different for different keys which have the same common | |
2929 | * 6 key blocks (MSB, blocks 6..11) key within a region. | |
2930 | * Range is 0..cap_max_pe_large_key_id - 1 | |
2931 | * Access: RW | |
2932 | */ | |
2933 | MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); | |
2934 | ||
2935 | /* reg_ptce3_action_pointer | |
2936 | * Pointer to action. | |
2937 | * Range is 0..cap_max_kvd_action_sets - 1 | |
2938 | * Access: RW | |
2939 | */ | |
2940 | MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); | |
2941 | ||
2942 | static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, | |
2943 | enum mlxsw_reg_ptce3_op op, | |
2944 | u32 priority, | |
2945 | const char *tcam_region_info, | |
2946 | const char *key, u8 erp_id, | |
c22291f7 JP |
2947 | u16 delta_start, u8 delta_mask, |
2948 | u8 delta_value, bool large_exists, | |
2949 | u32 lkey_id, u32 action_pointer) | |
aecefac9 IS |
2950 | { |
2951 | MLXSW_REG_ZERO(ptce3, payload); | |
2952 | mlxsw_reg_ptce3_v_set(payload, valid); | |
2953 | mlxsw_reg_ptce3_op_set(payload, op); | |
2954 | mlxsw_reg_ptce3_priority_set(payload, priority); | |
2955 | mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); | |
2956 | mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); | |
2957 | mlxsw_reg_ptce3_erp_id_set(payload, erp_id); | |
c22291f7 JP |
2958 | mlxsw_reg_ptce3_delta_start_set(payload, delta_start); |
2959 | mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); | |
2960 | mlxsw_reg_ptce3_delta_value_set(payload, delta_value); | |
aecefac9 IS |
2961 | mlxsw_reg_ptce3_large_exists_set(payload, large_exists); |
2962 | mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); | |
2963 | mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); | |
2964 | } | |
2965 | ||
481662a8 IS |
2966 | /* PERCR - Policy-Engine Region Configuration Register |
2967 | * --------------------------------------------------- | |
2968 | * This register configures the region parameters. The region_id must be | |
2969 | * allocated. | |
2970 | */ | |
2971 | #define MLXSW_REG_PERCR_ID 0x302A | |
2972 | #define MLXSW_REG_PERCR_LEN 0x80 | |
2973 | ||
2974 | MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); | |
2975 | ||
2976 | /* reg_percr_region_id | |
2977 | * Region identifier. | |
2978 | * Range 0..cap_max_regions-1 | |
2979 | * Access: Index | |
2980 | */ | |
2981 | MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); | |
2982 | ||
2983 | /* reg_percr_atcam_ignore_prune | |
2984 | * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. | |
2985 | * Access: RW | |
2986 | */ | |
2987 | MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); | |
2988 | ||
2989 | /* reg_percr_ctcam_ignore_prune | |
2990 | * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. | |
2991 | * Access: RW | |
2992 | */ | |
2993 | MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); | |
2994 | ||
2995 | /* reg_percr_bf_bypass | |
2996 | * Bloom filter bypass. | |
2997 | * 0 - Bloom filter is used (default) | |
2998 | * 1 - Bloom filter is bypassed. The bypass is an OR condition of | |
2999 | * region_id or eRP. See PERPT.bf_bypass | |
3000 | * Access: RW | |
3001 | */ | |
3002 | MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); | |
3003 | ||
3004 | /* reg_percr_master_mask | |
3005 | * Master mask. Logical OR mask of all masks of all rules of a region | |
3006 | * (both A-TCAM and C-TCAM). When there are no eRPs | |
3007 | * (erpt_pointer_valid = 0), then this provides the mask. | |
3008 | * Access: RW | |
3009 | */ | |
3010 | MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); | |
3011 | ||
3012 | static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) | |
3013 | { | |
3014 | MLXSW_REG_ZERO(percr, payload); | |
3015 | mlxsw_reg_percr_region_id_set(payload, region_id); | |
3016 | mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); | |
3017 | mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); | |
03ce5bd1 | 3018 | mlxsw_reg_percr_bf_bypass_set(payload, false); |
481662a8 IS |
3019 | } |
3020 | ||
f1c7d9cc IS |
3021 | /* PERERP - Policy-Engine Region eRP Register |
3022 | * ------------------------------------------ | |
3023 | * This register configures the region eRP. The region_id must be | |
3024 | * allocated. | |
3025 | */ | |
3026 | #define MLXSW_REG_PERERP_ID 0x302B | |
3027 | #define MLXSW_REG_PERERP_LEN 0x1C | |
3028 | ||
3029 | MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); | |
3030 | ||
3031 | /* reg_pererp_region_id | |
3032 | * Region identifier. | |
3033 | * Range 0..cap_max_regions-1 | |
3034 | * Access: Index | |
3035 | */ | |
3036 | MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); | |
3037 | ||
3038 | /* reg_pererp_ctcam_le | |
3039 | * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. | |
3040 | * Access: RW | |
3041 | */ | |
3042 | MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); | |
3043 | ||
3044 | /* reg_pererp_erpt_pointer_valid | |
3045 | * erpt_pointer is valid. | |
3046 | * Access: RW | |
3047 | */ | |
3048 | MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); | |
3049 | ||
3050 | /* reg_pererp_erpt_bank_pointer | |
3051 | * Pointer to eRP table bank. May be modified at any time. | |
3052 | * Range 0..cap_max_erp_table_banks-1 | |
3053 | * Reserved when erpt_pointer_valid = 0 | |
3054 | */ | |
3055 | MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); | |
3056 | ||
3057 | /* reg_pererp_erpt_pointer | |
3058 | * Pointer to eRP table within the eRP bank. Can be changed for an | |
3059 | * existing region. | |
3060 | * Range 0..cap_max_erp_table_size-1 | |
3061 | * Reserved when erpt_pointer_valid = 0 | |
3062 | * Access: RW | |
3063 | */ | |
3064 | MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); | |
3065 | ||
3066 | /* reg_pererp_erpt_vector | |
3067 | * Vector of allowed eRP indexes starting from erpt_pointer within the | |
3068 | * erpt_bank_pointer. Next entries will be in next bank. | |
3069 | * Note that eRP index is used and not eRP ID. | |
3070 | * Reserved when erpt_pointer_valid = 0 | |
3071 | * Access: RW | |
3072 | */ | |
3073 | MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); | |
3074 | ||
3075 | /* reg_pererp_master_rp_id | |
3076 | * Master RP ID. When there are no eRPs, then this provides the eRP ID | |
3077 | * for the lookup. Can be changed for an existing region. | |
3078 | * Reserved when erpt_pointer_valid = 1 | |
3079 | * Access: RW | |
3080 | */ | |
3081 | MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); | |
3082 | ||
91329e27 IS |
3083 | static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, |
3084 | unsigned long *erp_vector, | |
3085 | unsigned long size) | |
3086 | { | |
3087 | unsigned long bit; | |
3088 | ||
3089 | for_each_set_bit(bit, erp_vector, size) | |
3090 | mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); | |
3091 | } | |
3092 | ||
3093 | static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, | |
3094 | bool ctcam_le, bool erpt_pointer_valid, | |
3095 | u8 erpt_bank_pointer, u8 erpt_pointer, | |
3096 | u8 master_rp_id) | |
f1c7d9cc IS |
3097 | { |
3098 | MLXSW_REG_ZERO(pererp, payload); | |
3099 | mlxsw_reg_pererp_region_id_set(payload, region_id); | |
91329e27 IS |
3100 | mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); |
3101 | mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); | |
3102 | mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); | |
3103 | mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); | |
3104 | mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); | |
f1c7d9cc IS |
3105 | } |
3106 | ||
418089a8 ND |
3107 | /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register |
3108 | * ---------------------------------------------------------------- | |
3109 | * This register configures the Bloom filter entries. | |
3110 | */ | |
3111 | #define MLXSW_REG_PEABFE_ID 0x3022 | |
3112 | #define MLXSW_REG_PEABFE_BASE_LEN 0x10 | |
3113 | #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 | |
3114 | #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 | |
3115 | #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ | |
3116 | MLXSW_REG_PEABFE_BF_REC_LEN * \ | |
3117 | MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) | |
3118 | ||
3119 | MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); | |
3120 | ||
3121 | /* reg_peabfe_size | |
3122 | * Number of BF entries to be updated. | |
3123 | * Range 1..256 | |
3124 | * Access: Op | |
3125 | */ | |
3126 | MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); | |
3127 | ||
3128 | /* reg_peabfe_bf_entry_state | |
3129 | * Bloom filter state | |
3130 | * 0 - Clear | |
3131 | * 1 - Set | |
3132 | * Access: RW | |
3133 | */ | |
3134 | MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, | |
3135 | MLXSW_REG_PEABFE_BASE_LEN, 31, 1, | |
3136 | MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); | |
3137 | ||
3138 | /* reg_peabfe_bf_entry_bank | |
3139 | * Bloom filter bank ID | |
3140 | * Range 0..cap_max_erp_table_banks-1 | |
3141 | * Access: Index | |
3142 | */ | |
3143 | MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, | |
3144 | MLXSW_REG_PEABFE_BASE_LEN, 24, 4, | |
3145 | MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); | |
3146 | ||
3147 | /* reg_peabfe_bf_entry_index | |
3148 | * Bloom filter entry index | |
3149 | * Range 0..2^cap_max_bf_log-1 | |
3150 | * Access: Index | |
3151 | */ | |
3152 | MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, | |
3153 | MLXSW_REG_PEABFE_BASE_LEN, 0, 24, | |
3154 | MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); | |
3155 | ||
3156 | static inline void mlxsw_reg_peabfe_pack(char *payload) | |
3157 | { | |
3158 | MLXSW_REG_ZERO(peabfe, payload); | |
3159 | } | |
3160 | ||
3161 | static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, | |
3162 | u8 state, u8 bank, u32 bf_index) | |
3163 | { | |
3164 | u8 num_rec = mlxsw_reg_peabfe_size_get(payload); | |
3165 | ||
3166 | if (rec_index >= num_rec) | |
3167 | mlxsw_reg_peabfe_size_set(payload, rec_index + 1); | |
3168 | mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); | |
3169 | mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); | |
3170 | mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); | |
3171 | } | |
3172 | ||
c33d0cb1 JP |
3173 | /* IEDR - Infrastructure Entry Delete Register |
3174 | * ---------------------------------------------------- | |
3175 | * This register is used for deleting entries from the entry tables. | |
3176 | * It is legitimate to attempt to delete a nonexisting entry (the device will | |
3177 | * respond as a good flow). | |
3178 | */ | |
3179 | #define MLXSW_REG_IEDR_ID 0x3804 | |
3180 | #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ | |
3181 | #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ | |
3182 | #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 | |
3183 | #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ | |
3184 | MLXSW_REG_IEDR_REC_LEN * \ | |
3185 | MLXSW_REG_IEDR_REC_MAX_COUNT) | |
3186 | ||
3187 | MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); | |
3188 | ||
3189 | /* reg_iedr_num_rec | |
3190 | * Number of records. | |
3191 | * Access: OP | |
3192 | */ | |
3193 | MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); | |
3194 | ||
3195 | /* reg_iedr_rec_type | |
3196 | * Resource type. | |
3197 | * Access: OP | |
3198 | */ | |
3199 | MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, | |
3200 | MLXSW_REG_IEDR_REC_LEN, 0x00, false); | |
3201 | ||
3202 | /* reg_iedr_rec_size | |
3203 | * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. | |
3204 | * Access: OP | |
3205 | */ | |
3206 | MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, | |
3207 | MLXSW_REG_IEDR_REC_LEN, 0x00, false); | |
3208 | ||
3209 | /* reg_iedr_rec_index_start | |
3210 | * Resource index start. | |
3211 | * Access: OP | |
3212 | */ | |
3213 | MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, | |
3214 | MLXSW_REG_IEDR_REC_LEN, 0x04, false); | |
3215 | ||
3216 | static inline void mlxsw_reg_iedr_pack(char *payload) | |
3217 | { | |
3218 | MLXSW_REG_ZERO(iedr, payload); | |
3219 | } | |
3220 | ||
3221 | static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, | |
3222 | u8 rec_type, u16 rec_size, | |
3223 | u32 rec_index_start) | |
3224 | { | |
3225 | u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); | |
3226 | ||
3227 | if (rec_index >= num_rec) | |
3228 | mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); | |
3229 | mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); | |
3230 | mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); | |
3231 | mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); | |
3232 | } | |
3233 | ||
746da42a PM |
3234 | /* QPTS - QoS Priority Trust State Register |
3235 | * ---------------------------------------- | |
3236 | * This register controls the port policy to calculate the switch priority and | |
3237 | * packet color based on incoming packet fields. | |
3238 | */ | |
3239 | #define MLXSW_REG_QPTS_ID 0x4002 | |
3240 | #define MLXSW_REG_QPTS_LEN 0x8 | |
3241 | ||
3242 | MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); | |
3243 | ||
3244 | /* reg_qpts_local_port | |
3245 | * Local port number. | |
3246 | * Access: Index | |
3247 | * | |
3248 | * Note: CPU port is supported. | |
3249 | */ | |
3250 | MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); | |
3251 | ||
3252 | enum mlxsw_reg_qpts_trust_state { | |
3253 | MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, | |
3254 | MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ | |
3255 | }; | |
3256 | ||
3257 | /* reg_qpts_trust_state | |
3258 | * Trust state for a given port. | |
3259 | * Access: RW | |
3260 | */ | |
3261 | MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); | |
3262 | ||
3263 | static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, | |
3264 | enum mlxsw_reg_qpts_trust_state ts) | |
3265 | { | |
3266 | MLXSW_REG_ZERO(qpts, payload); | |
3267 | ||
3268 | mlxsw_reg_qpts_local_port_set(payload, local_port); | |
3269 | mlxsw_reg_qpts_trust_state_set(payload, ts); | |
3270 | } | |
3271 | ||
76a4c7d3 NF |
3272 | /* QPCR - QoS Policer Configuration Register |
3273 | * ----------------------------------------- | |
3274 | * The QPCR register is used to create policers - that limit | |
3275 | * the rate of bytes or packets via some trap group. | |
3276 | */ | |
3277 | #define MLXSW_REG_QPCR_ID 0x4004 | |
3278 | #define MLXSW_REG_QPCR_LEN 0x28 | |
3279 | ||
3280 | MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); | |
3281 | ||
3282 | enum mlxsw_reg_qpcr_g { | |
3283 | MLXSW_REG_QPCR_G_GLOBAL = 2, | |
3284 | MLXSW_REG_QPCR_G_STORM_CONTROL = 3, | |
3285 | }; | |
3286 | ||
3287 | /* reg_qpcr_g | |
3288 | * The policer type. | |
3289 | * Access: Index | |
3290 | */ | |
3291 | MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); | |
3292 | ||
3293 | /* reg_qpcr_pid | |
3294 | * Policer ID. | |
3295 | * Access: Index | |
3296 | */ | |
3297 | MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); | |
3298 | ||
3299 | /* reg_qpcr_color_aware | |
3300 | * Is the policer aware of colors. | |
3301 | * Must be 0 (unaware) for cpu port. | |
3302 | * Access: RW for unbounded policer. RO for bounded policer. | |
3303 | */ | |
3304 | MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); | |
3305 | ||
3306 | /* reg_qpcr_bytes | |
3307 | * Is policer limit is for bytes per sec or packets per sec. | |
3308 | * 0 - packets | |
3309 | * 1 - bytes | |
3310 | * Access: RW for unbounded policer. RO for bounded policer. | |
3311 | */ | |
3312 | MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); | |
3313 | ||
3314 | enum mlxsw_reg_qpcr_ir_units { | |
3315 | MLXSW_REG_QPCR_IR_UNITS_M, | |
3316 | MLXSW_REG_QPCR_IR_UNITS_K, | |
3317 | }; | |
3318 | ||
3319 | /* reg_qpcr_ir_units | |
3320 | * Policer's units for cir and eir fields (for bytes limits only) | |
3321 | * 1 - 10^3 | |
3322 | * 0 - 10^6 | |
3323 | * Access: OP | |
3324 | */ | |
3325 | MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); | |
3326 | ||
3327 | enum mlxsw_reg_qpcr_rate_type { | |
3328 | MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, | |
3329 | MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, | |
3330 | }; | |
3331 | ||
3332 | /* reg_qpcr_rate_type | |
3333 | * Policer can have one limit (single rate) or 2 limits with specific operation | |
3334 | * for packets that exceed the lower rate but not the upper one. | |
3335 | * (For cpu port must be single rate) | |
3336 | * Access: RW for unbounded policer. RO for bounded policer. | |
3337 | */ | |
3338 | MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); | |
3339 | ||
3340 | /* reg_qpc_cbs | |
3341 | * Policer's committed burst size. | |
3342 | * The policer is working with time slices of 50 nano sec. By default every | |
3343 | * slice is granted the proportionate share of the committed rate. If we want to | |
3344 | * allow a slice to exceed that share (while still keeping the rate per sec) we | |
3345 | * can allow burst. The burst size is between the default proportionate share | |
3346 | * (and no lower than 8) to 32Gb. (Even though giving a number higher than the | |
3347 | * committed rate will result in exceeding the rate). The burst size must be a | |
3348 | * log of 2 and will be determined by 2^cbs. | |
3349 | * Access: RW | |
3350 | */ | |
3351 | MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); | |
3352 | ||
3353 | /* reg_qpcr_cir | |
3354 | * Policer's committed rate. | |
3355 | * The rate used for sungle rate, the lower rate for double rate. | |
3356 | * For bytes limits, the rate will be this value * the unit from ir_units. | |
3357 | * (Resolution error is up to 1%). | |
3358 | * Access: RW | |
3359 | */ | |
3360 | MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); | |
3361 | ||
3362 | /* reg_qpcr_eir | |
3363 | * Policer's exceed rate. | |
3364 | * The higher rate for double rate, reserved for single rate. | |
3365 | * Lower rate for double rate policer. | |
3366 | * For bytes limits, the rate will be this value * the unit from ir_units. | |
3367 | * (Resolution error is up to 1%). | |
3368 | * Access: RW | |
3369 | */ | |
3370 | MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); | |
3371 | ||
3372 | #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 | |
3373 | ||
3374 | /* reg_qpcr_exceed_action. | |
3375 | * What to do with packets between the 2 limits for double rate. | |
3376 | * Access: RW for unbounded policer. RO for bounded policer. | |
3377 | */ | |
3378 | MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); | |
3379 | ||
3380 | enum mlxsw_reg_qpcr_action { | |
3381 | /* Discard */ | |
3382 | MLXSW_REG_QPCR_ACTION_DISCARD = 1, | |
3383 | /* Forward and set color to red. | |
3384 | * If the packet is intended to cpu port, it will be dropped. | |
3385 | */ | |
3386 | MLXSW_REG_QPCR_ACTION_FORWARD = 2, | |
3387 | }; | |
3388 | ||
3389 | /* reg_qpcr_violate_action | |
3390 | * What to do with packets that cross the cir limit (for single rate) or the eir | |
3391 | * limit (for double rate). | |
3392 | * Access: RW for unbounded policer. RO for bounded policer. | |
3393 | */ | |
3394 | MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); | |
3395 | ||
3396 | static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, | |
3397 | enum mlxsw_reg_qpcr_ir_units ir_units, | |
3398 | bool bytes, u32 cir, u16 cbs) | |
3399 | { | |
3400 | MLXSW_REG_ZERO(qpcr, payload); | |
3401 | mlxsw_reg_qpcr_pid_set(payload, pid); | |
3402 | mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); | |
3403 | mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); | |
3404 | mlxsw_reg_qpcr_violate_action_set(payload, | |
3405 | MLXSW_REG_QPCR_ACTION_DISCARD); | |
3406 | mlxsw_reg_qpcr_cir_set(payload, cir); | |
3407 | mlxsw_reg_qpcr_ir_units_set(payload, ir_units); | |
3408 | mlxsw_reg_qpcr_bytes_set(payload, bytes); | |
3409 | mlxsw_reg_qpcr_cbs_set(payload, cbs); | |
3410 | } | |
3411 | ||
2c63a555 IS |
3412 | /* QTCT - QoS Switch Traffic Class Table |
3413 | * ------------------------------------- | |
3414 | * Configures the mapping between the packet switch priority and the | |
3415 | * traffic class on the transmit port. | |
3416 | */ | |
3417 | #define MLXSW_REG_QTCT_ID 0x400A | |
3418 | #define MLXSW_REG_QTCT_LEN 0x08 | |
3419 | ||
21978dcf | 3420 | MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); |
2c63a555 IS |
3421 | |
3422 | /* reg_qtct_local_port | |
3423 | * Local port number. | |
3424 | * Access: Index | |
3425 | * | |
3426 | * Note: CPU port is not supported. | |
3427 | */ | |
3428 | MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); | |
3429 | ||
3430 | /* reg_qtct_sub_port | |
3431 | * Virtual port within the physical port. | |
3432 | * Should be set to 0 when virtual ports are not enabled on the port. | |
3433 | * Access: Index | |
3434 | */ | |
3435 | MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); | |
3436 | ||
3437 | /* reg_qtct_switch_prio | |
3438 | * Switch priority. | |
3439 | * Access: Index | |
3440 | */ | |
3441 | MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); | |
3442 | ||
3443 | /* reg_qtct_tclass | |
3444 | * Traffic class. | |
3445 | * Default values: | |
3446 | * switch_prio 0 : tclass 1 | |
3447 | * switch_prio 1 : tclass 0 | |
3448 | * switch_prio i : tclass i, for i > 1 | |
3449 | * Access: RW | |
3450 | */ | |
3451 | MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); | |
3452 | ||
3453 | static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, | |
3454 | u8 switch_prio, u8 tclass) | |
3455 | { | |
3456 | MLXSW_REG_ZERO(qtct, payload); | |
3457 | mlxsw_reg_qtct_local_port_set(payload, local_port); | |
3458 | mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); | |
3459 | mlxsw_reg_qtct_tclass_set(payload, tclass); | |
3460 | } | |
3461 | ||
b9b7cee4 IS |
3462 | /* QEEC - QoS ETS Element Configuration Register |
3463 | * --------------------------------------------- | |
3464 | * Configures the ETS elements. | |
3465 | */ | |
3466 | #define MLXSW_REG_QEEC_ID 0x400D | |
8b931821 | 3467 | #define MLXSW_REG_QEEC_LEN 0x20 |
b9b7cee4 | 3468 | |
21978dcf | 3469 | MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); |
b9b7cee4 IS |
3470 | |
3471 | /* reg_qeec_local_port | |
3472 | * Local port number. | |
3473 | * Access: Index | |
3474 | * | |
3475 | * Note: CPU port is supported. | |
3476 | */ | |
3477 | MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); | |
3478 | ||
3479 | enum mlxsw_reg_qeec_hr { | |
3480 | MLXSW_REG_QEEC_HIERARCY_PORT, | |
3481 | MLXSW_REG_QEEC_HIERARCY_GROUP, | |
3482 | MLXSW_REG_QEEC_HIERARCY_SUBGROUP, | |
3483 | MLXSW_REG_QEEC_HIERARCY_TC, | |
3484 | }; | |
3485 | ||
3486 | /* reg_qeec_element_hierarchy | |
3487 | * 0 - Port | |
3488 | * 1 - Group | |
3489 | * 2 - Subgroup | |
3490 | * 3 - Traffic Class | |
3491 | * Access: Index | |
3492 | */ | |
3493 | MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); | |
3494 | ||
3495 | /* reg_qeec_element_index | |
3496 | * The index of the element in the hierarchy. | |
3497 | * Access: Index | |
3498 | */ | |
3499 | MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); | |
3500 | ||
3501 | /* reg_qeec_next_element_index | |
3502 | * The index of the next (lower) element in the hierarchy. | |
3503 | * Access: RW | |
3504 | * | |
3505 | * Note: Reserved for element_hierarchy 0. | |
3506 | */ | |
3507 | MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); | |
3508 | ||
8b931821 PM |
3509 | /* reg_qeec_mise |
3510 | * Min shaper configuration enable. Enables configuration of the min | |
3511 | * shaper on this ETS element | |
3512 | * 0 - Disable | |
3513 | * 1 - Enable | |
3514 | * Access: RW | |
3515 | */ | |
3516 | MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); | |
3517 | ||
12f0e2e9 ST |
3518 | /* reg_qeec_ptps |
3519 | * PTP shaper | |
3520 | * 0: regular shaper mode | |
3521 | * 1: PTP oriented shaper | |
3522 | * Allowed only for hierarchy 0 | |
3523 | * Not supported for CPU port | |
3524 | * Note that ptps mode may affect the shaper rates of all hierarchies | |
3525 | * Supported only on Spectrum-1 | |
3526 | * Access: RW | |
3527 | */ | |
3528 | MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); | |
3529 | ||
b9b7cee4 IS |
3530 | enum { |
3531 | MLXSW_REG_QEEC_BYTES_MODE, | |
3532 | MLXSW_REG_QEEC_PACKETS_MODE, | |
3533 | }; | |
3534 | ||
3535 | /* reg_qeec_pb | |
3536 | * Packets or bytes mode. | |
3537 | * 0 - Bytes mode | |
3538 | * 1 - Packets mode | |
3539 | * Access: RW | |
3540 | * | |
3541 | * Note: Used for max shaper configuration. For Spectrum, packets mode | |
3542 | * is supported only for traffic classes of CPU port. | |
3543 | */ | |
3544 | MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); | |
3545 | ||
8b931821 PM |
3546 | /* The smallest permitted min shaper rate. */ |
3547 | #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ | |
3548 | ||
3549 | /* reg_qeec_min_shaper_rate | |
3550 | * Min shaper information rate. | |
3551 | * For CPU port, can only be configured for port hierarchy. | |
3552 | * When in bytes mode, value is specified in units of 1000bps. | |
3553 | * Access: RW | |
3554 | */ | |
3555 | MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); | |
3556 | ||
b9b7cee4 IS |
3557 | /* reg_qeec_mase |
3558 | * Max shaper configuration enable. Enables configuration of the max | |
3559 | * shaper on this ETS element. | |
3560 | * 0 - Disable | |
3561 | * 1 - Enable | |
3562 | * Access: RW | |
3563 | */ | |
3564 | MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); | |
3565 | ||
3566 | /* A large max rate will disable the max shaper. */ | |
3567 | #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ | |
3568 | ||
3569 | /* reg_qeec_max_shaper_rate | |
3570 | * Max shaper information rate. | |
3571 | * For CPU port, can only be configured for port hierarchy. | |
3572 | * When in bytes mode, value is specified in units of 1000bps. | |
3573 | * Access: RW | |
3574 | */ | |
3575 | MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); | |
3576 | ||
3577 | /* reg_qeec_de | |
3578 | * DWRR configuration enable. Enables configuration of the dwrr and | |
3579 | * dwrr_weight. | |
3580 | * 0 - Disable | |
3581 | * 1 - Enable | |
3582 | * Access: RW | |
3583 | */ | |
3584 | MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); | |
3585 | ||
3586 | /* reg_qeec_dwrr | |
3587 | * Transmission selection algorithm to use on the link going down from | |
3588 | * the ETS element. | |
3589 | * 0 - Strict priority | |
3590 | * 1 - DWRR | |
3591 | * Access: RW | |
3592 | */ | |
3593 | MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); | |
3594 | ||
3595 | /* reg_qeec_dwrr_weight | |
3596 | * DWRR weight on the link going down from the ETS element. The | |
3597 | * percentage of bandwidth guaranteed to an ETS element within | |
3598 | * its hierarchy. The sum of all weights across all ETS elements | |
3599 | * within one hierarchy should be equal to 100. Reserved when | |
3600 | * transmission selection algorithm is strict priority. | |
3601 | * Access: RW | |
3602 | */ | |
3603 | MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); | |
3604 | ||
3605 | static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, | |
3606 | enum mlxsw_reg_qeec_hr hr, u8 index, | |
3607 | u8 next_index) | |
3608 | { | |
3609 | MLXSW_REG_ZERO(qeec, payload); | |
3610 | mlxsw_reg_qeec_local_port_set(payload, local_port); | |
3611 | mlxsw_reg_qeec_element_hierarchy_set(payload, hr); | |
3612 | mlxsw_reg_qeec_element_index_set(payload, index); | |
3613 | mlxsw_reg_qeec_next_element_index_set(payload, next_index); | |
3614 | } | |
3615 | ||
12f0e2e9 ST |
3616 | static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, |
3617 | bool ptps) | |
3618 | { | |
3619 | MLXSW_REG_ZERO(qeec, payload); | |
3620 | mlxsw_reg_qeec_local_port_set(payload, local_port); | |
3621 | mlxsw_reg_qeec_element_hierarchy_set(payload, | |
3622 | MLXSW_REG_QEEC_HIERARCY_PORT); | |
3623 | mlxsw_reg_qeec_ptps_set(payload, ptps); | |
3624 | } | |
3625 | ||
e67131d9 PM |
3626 | /* QRWE - QoS ReWrite Enable |
3627 | * ------------------------- | |
3628 | * This register configures the rewrite enable per receive port. | |
3629 | */ | |
3630 | #define MLXSW_REG_QRWE_ID 0x400F | |
3631 | #define MLXSW_REG_QRWE_LEN 0x08 | |
3632 | ||
3633 | MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); | |
3634 | ||
3635 | /* reg_qrwe_local_port | |
3636 | * Local port number. | |
3637 | * Access: Index | |
3638 | * | |
3639 | * Note: CPU port is supported. No support for router port. | |
3640 | */ | |
3641 | MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); | |
3642 | ||
3643 | /* reg_qrwe_dscp | |
3644 | * Whether to enable DSCP rewrite (default is 0, don't rewrite). | |
3645 | * Access: RW | |
3646 | */ | |
3647 | MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); | |
3648 | ||
3649 | /* reg_qrwe_pcp | |
3650 | * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). | |
3651 | * Access: RW | |
3652 | */ | |
3653 | MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); | |
3654 | ||
3655 | static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, | |
3656 | bool rewrite_pcp, bool rewrite_dscp) | |
3657 | { | |
3658 | MLXSW_REG_ZERO(qrwe, payload); | |
3659 | mlxsw_reg_qrwe_local_port_set(payload, local_port); | |
3660 | mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); | |
3661 | mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); | |
3662 | } | |
3663 | ||
55fb71f4 PM |
3664 | /* QPDSM - QoS Priority to DSCP Mapping |
3665 | * ------------------------------------ | |
3666 | * QoS Priority to DSCP Mapping Register | |
3667 | */ | |
3668 | #define MLXSW_REG_QPDSM_ID 0x4011 | |
3669 | #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ | |
3670 | #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ | |
3671 | #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 | |
3672 | #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ | |
3673 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ | |
3674 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) | |
3675 | ||
3676 | MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); | |
3677 | ||
3678 | /* reg_qpdsm_local_port | |
3679 | * Local Port. Supported for data packets from CPU port. | |
3680 | * Access: Index | |
3681 | */ | |
3682 | MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); | |
3683 | ||
3684 | /* reg_qpdsm_prio_entry_color0_e | |
3685 | * Enable update of the entry for color 0 and a given port. | |
3686 | * Access: WO | |
3687 | */ | |
3688 | MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, | |
3689 | MLXSW_REG_QPDSM_BASE_LEN, 31, 1, | |
3690 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); | |
3691 | ||
3692 | /* reg_qpdsm_prio_entry_color0_dscp | |
3693 | * DSCP field in the outer label of the packet for color 0 and a given port. | |
3694 | * Reserved when e=0. | |
3695 | * Access: RW | |
3696 | */ | |
3697 | MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, | |
3698 | MLXSW_REG_QPDSM_BASE_LEN, 24, 6, | |
3699 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); | |
3700 | ||
3701 | /* reg_qpdsm_prio_entry_color1_e | |
3702 | * Enable update of the entry for color 1 and a given port. | |
3703 | * Access: WO | |
3704 | */ | |
3705 | MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, | |
3706 | MLXSW_REG_QPDSM_BASE_LEN, 23, 1, | |
3707 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); | |
3708 | ||
3709 | /* reg_qpdsm_prio_entry_color1_dscp | |
3710 | * DSCP field in the outer label of the packet for color 1 and a given port. | |
3711 | * Reserved when e=0. | |
3712 | * Access: RW | |
3713 | */ | |
3714 | MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, | |
3715 | MLXSW_REG_QPDSM_BASE_LEN, 16, 6, | |
3716 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); | |
3717 | ||
3718 | /* reg_qpdsm_prio_entry_color2_e | |
3719 | * Enable update of the entry for color 2 and a given port. | |
3720 | * Access: WO | |
3721 | */ | |
3722 | MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, | |
3723 | MLXSW_REG_QPDSM_BASE_LEN, 15, 1, | |
3724 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); | |
3725 | ||
3726 | /* reg_qpdsm_prio_entry_color2_dscp | |
3727 | * DSCP field in the outer label of the packet for color 2 and a given port. | |
3728 | * Reserved when e=0. | |
3729 | * Access: RW | |
3730 | */ | |
3731 | MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, | |
3732 | MLXSW_REG_QPDSM_BASE_LEN, 8, 6, | |
3733 | MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); | |
3734 | ||
3735 | static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) | |
3736 | { | |
3737 | MLXSW_REG_ZERO(qpdsm, payload); | |
3738 | mlxsw_reg_qpdsm_local_port_set(payload, local_port); | |
3739 | } | |
3740 | ||
3741 | static inline void | |
3742 | mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) | |
3743 | { | |
3744 | mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); | |
3745 | mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); | |
3746 | mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); | |
3747 | mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); | |
3748 | mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); | |
3749 | mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); | |
3750 | } | |
3751 | ||
02837d72 PM |
3752 | /* QPDPM - QoS Port DSCP to Priority Mapping Register |
3753 | * -------------------------------------------------- | |
3754 | * This register controls the mapping from DSCP field to | |
3755 | * Switch Priority for IP packets. | |
3756 | */ | |
3757 | #define MLXSW_REG_QPDPM_ID 0x4013 | |
3758 | #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ | |
3759 | #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ | |
3760 | #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 | |
3761 | #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ | |
3762 | MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ | |
3763 | MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) | |
3764 | ||
3765 | MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); | |
3766 | ||
3767 | /* reg_qpdpm_local_port | |
3768 | * Local Port. Supported for data packets from CPU port. | |
3769 | * Access: Index | |
3770 | */ | |
3771 | MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); | |
3772 | ||
3773 | /* reg_qpdpm_dscp_e | |
3774 | * Enable update of the specific entry. When cleared, the switch_prio and color | |
3775 | * fields are ignored and the previous switch_prio and color values are | |
3776 | * preserved. | |
3777 | * Access: WO | |
3778 | */ | |
3779 | MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, | |
3780 | MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); | |
3781 | ||
3782 | /* reg_qpdpm_dscp_prio | |
3783 | * The new Switch Priority value for the relevant DSCP value. | |
3784 | * Access: RW | |
3785 | */ | |
3786 | MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, | |
3787 | MLXSW_REG_QPDPM_BASE_LEN, 0, 4, | |
3788 | MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); | |
3789 | ||
3790 | static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) | |
3791 | { | |
3792 | MLXSW_REG_ZERO(qpdpm, payload); | |
3793 | mlxsw_reg_qpdpm_local_port_set(payload, local_port); | |
3794 | } | |
3795 | ||
3796 | static inline void | |
3797 | mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) | |
3798 | { | |
3799 | mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); | |
3800 | mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); | |
3801 | } | |
3802 | ||
671ae8af PM |
3803 | /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register |
3804 | * ------------------------------------------------------------------ | |
3805 | * This register configures if the Switch Priority to Traffic Class mapping is | |
3806 | * based on Multicast packet indication. If so, then multicast packets will get | |
3807 | * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by | |
3808 | * QTCT. | |
3809 | * By default, Switch Priority to Traffic Class mapping is not based on | |
3810 | * Multicast packet indication. | |
3811 | */ | |
3812 | #define MLXSW_REG_QTCTM_ID 0x401A | |
3813 | #define MLXSW_REG_QTCTM_LEN 0x08 | |
3814 | ||
3815 | MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); | |
3816 | ||
3817 | /* reg_qtctm_local_port | |
3818 | * Local port number. | |
3819 | * No support for CPU port. | |
3820 | * Access: Index | |
3821 | */ | |
3822 | MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); | |
3823 | ||
3824 | /* reg_qtctm_mc | |
3825 | * Multicast Mode | |
3826 | * Whether Switch Priority to Traffic Class mapping is based on Multicast packet | |
3827 | * indication (default is 0, not based on Multicast packet indication). | |
3828 | */ | |
3829 | MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); | |
3830 | ||
3831 | static inline void | |
3832 | mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) | |
3833 | { | |
3834 | MLXSW_REG_ZERO(qtctm, payload); | |
3835 | mlxsw_reg_qtctm_local_port_set(payload, local_port); | |
3836 | mlxsw_reg_qtctm_mc_set(payload, mc); | |
3837 | } | |
3838 | ||
71147506 ST |
3839 | /* QPSC - QoS PTP Shaper Configuration Register |
3840 | * -------------------------------------------- | |
3841 | * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. | |
3842 | * Supported only on Spectrum-1. | |
3843 | */ | |
3844 | #define MLXSW_REG_QPSC_ID 0x401B | |
3845 | #define MLXSW_REG_QPSC_LEN 0x28 | |
3846 | ||
3847 | MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); | |
3848 | ||
3849 | enum mlxsw_reg_qpsc_port_speed { | |
3850 | MLXSW_REG_QPSC_PORT_SPEED_100M, | |
3851 | MLXSW_REG_QPSC_PORT_SPEED_1G, | |
3852 | MLXSW_REG_QPSC_PORT_SPEED_10G, | |
3853 | MLXSW_REG_QPSC_PORT_SPEED_25G, | |
3854 | }; | |
3855 | ||
3856 | /* reg_qpsc_port_speed | |
3857 | * Port speed. | |
3858 | * Access: Index | |
3859 | */ | |
3860 | MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); | |
3861 | ||
3862 | /* reg_qpsc_shaper_time_exp | |
3863 | * The base-time-interval for updating the shapers tokens (for all hierarchies). | |
3864 | * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec | |
3865 | * shaper_rate = 64bit * shaper_inc / shaper_update_rate | |
3866 | * Access: RW | |
3867 | */ | |
3868 | MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); | |
3869 | ||
3870 | /* reg_qpsc_shaper_time_mantissa | |
3871 | * The base-time-interval for updating the shapers tokens (for all hierarchies). | |
3872 | * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec | |
3873 | * shaper_rate = 64bit * shaper_inc / shaper_update_rate | |
3874 | * Access: RW | |
3875 | */ | |
3876 | MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); | |
3877 | ||
3878 | /* reg_qpsc_shaper_inc | |
3879 | * Number of tokens added to shaper on each update. | |
3880 | * Units of 8B. | |
3881 | * Access: RW | |
3882 | */ | |
3883 | MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); | |
3884 | ||
3885 | /* reg_qpsc_shaper_bs | |
3886 | * Max shaper Burst size. | |
3887 | * Burst size is 2 ^ max_shaper_bs * 512 [bits] | |
3888 | * Range is: 5..25 (from 2KB..2GB) | |
3889 | * Access: RW | |
3890 | */ | |
3891 | MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); | |
3892 | ||
3893 | /* reg_qpsc_ptsc_we | |
3894 | * Write enable to port_to_shaper_credits. | |
3895 | * Access: WO | |
3896 | */ | |
3897 | MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); | |
3898 | ||
3899 | /* reg_qpsc_port_to_shaper_credits | |
3900 | * For split ports: range 1..57 | |
3901 | * For non-split ports: range 1..112 | |
3902 | * Written only when ptsc_we is set. | |
3903 | * Access: RW | |
3904 | */ | |
3905 | MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); | |
3906 | ||
3907 | /* reg_qpsc_ing_timestamp_inc | |
3908 | * Ingress timestamp increment. | |
3909 | * 2's complement. | |
3910 | * The timestamp of MTPPTR at ingress will be incremented by this value. Global | |
3911 | * value for all ports. | |
3912 | * Same units as used by MTPPTR. | |
3913 | * Access: RW | |
3914 | */ | |
3915 | MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); | |
3916 | ||
3917 | /* reg_qpsc_egr_timestamp_inc | |
3918 | * Egress timestamp increment. | |
3919 | * 2's complement. | |
3920 | * The timestamp of MTPPTR at egress will be incremented by this value. Global | |
3921 | * value for all ports. | |
3922 | * Same units as used by MTPPTR. | |
3923 | * Access: RW | |
3924 | */ | |
3925 | MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); | |
3926 | ||
3927 | static inline void | |
3928 | mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, | |
3929 | u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, | |
3930 | u8 shaper_bs, u8 port_to_shaper_credits, | |
3931 | int ing_timestamp_inc, int egr_timestamp_inc) | |
3932 | { | |
3933 | MLXSW_REG_ZERO(qpsc, payload); | |
3934 | mlxsw_reg_qpsc_port_speed_set(payload, port_speed); | |
3935 | mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); | |
3936 | mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); | |
3937 | mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); | |
3938 | mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); | |
3939 | mlxsw_reg_qpsc_ptsc_we_set(payload, true); | |
3940 | mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); | |
3941 | mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); | |
3942 | mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); | |
3943 | } | |
3944 | ||
4ec14b76 IS |
3945 | /* PMLP - Ports Module to Local Port Register |
3946 | * ------------------------------------------ | |
3947 | * Configures the assignment of modules to local ports. | |
3948 | */ | |
3949 | #define MLXSW_REG_PMLP_ID 0x5002 | |
3950 | #define MLXSW_REG_PMLP_LEN 0x40 | |
3951 | ||
21978dcf | 3952 | MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); |
4ec14b76 IS |
3953 | |
3954 | /* reg_pmlp_rxtx | |
3955 | * 0 - Tx value is used for both Tx and Rx. | |
3956 | * 1 - Rx value is taken from a separte field. | |
3957 | * Access: RW | |
3958 | */ | |
3959 | MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); | |
3960 | ||
3961 | /* reg_pmlp_local_port | |
3962 | * Local port number. | |
3963 | * Access: Index | |
3964 | */ | |
3965 | MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); | |
3966 | ||
3967 | /* reg_pmlp_width | |
3968 | * 0 - Unmap local port. | |
3969 | * 1 - Lane 0 is used. | |
3970 | * 2 - Lanes 0 and 1 are used. | |
3971 | * 4 - Lanes 0, 1, 2 and 3 are used. | |
94e76837 | 3972 | * 8 - Lanes 0-7 are used. |
4ec14b76 IS |
3973 | * Access: RW |
3974 | */ | |
3975 | MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); | |
3976 | ||
3977 | /* reg_pmlp_module | |
3978 | * Module number. | |
3979 | * Access: RW | |
3980 | */ | |
bbeeda27 | 3981 | MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); |
4ec14b76 IS |
3982 | |
3983 | /* reg_pmlp_tx_lane | |
3984 | * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. | |
3985 | * Access: RW | |
3986 | */ | |
94e76837 | 3987 | MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); |
4ec14b76 IS |
3988 | |
3989 | /* reg_pmlp_rx_lane | |
3990 | * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is | |
3991 | * equal to Tx lane. | |
3992 | * Access: RW | |
3993 | */ | |
94e76837 | 3994 | MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); |
4ec14b76 IS |
3995 | |
3996 | static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) | |
3997 | { | |
3998 | MLXSW_REG_ZERO(pmlp, payload); | |
3999 | mlxsw_reg_pmlp_local_port_set(payload, local_port); | |
4000 | } | |
4001 | ||
4002 | /* PMTU - Port MTU Register | |
4003 | * ------------------------ | |
4004 | * Configures and reports the port MTU. | |
4005 | */ | |
4006 | #define MLXSW_REG_PMTU_ID 0x5003 | |
4007 | #define MLXSW_REG_PMTU_LEN 0x10 | |
4008 | ||
21978dcf | 4009 | MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); |
4ec14b76 IS |
4010 | |
4011 | /* reg_pmtu_local_port | |
4012 | * Local port number. | |
4013 | * Access: Index | |
4014 | */ | |
4015 | MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); | |
4016 | ||
4017 | /* reg_pmtu_max_mtu | |
4018 | * Maximum MTU. | |
4019 | * When port type (e.g. Ethernet) is configured, the relevant MTU is | |
4020 | * reported, otherwise the minimum between the max_mtu of the different | |
4021 | * types is reported. | |
4022 | * Access: RO | |
4023 | */ | |
4024 | MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); | |
4025 | ||
4026 | /* reg_pmtu_admin_mtu | |
4027 | * MTU value to set port to. Must be smaller or equal to max_mtu. | |
4028 | * Note: If port type is Infiniband, then port must be disabled, when its | |
4029 | * MTU is set. | |
4030 | * Access: RW | |
4031 | */ | |
4032 | MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); | |
4033 | ||
4034 | /* reg_pmtu_oper_mtu | |
4035 | * The actual MTU configured on the port. Packets exceeding this size | |
4036 | * will be dropped. | |
4037 | * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband | |
4038 | * oper_mtu might be smaller than admin_mtu. | |
4039 | * Access: RO | |
4040 | */ | |
4041 | MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); | |
4042 | ||
4043 | static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, | |
4044 | u16 new_mtu) | |
4045 | { | |
4046 | MLXSW_REG_ZERO(pmtu, payload); | |
4047 | mlxsw_reg_pmtu_local_port_set(payload, local_port); | |
4048 | mlxsw_reg_pmtu_max_mtu_set(payload, 0); | |
4049 | mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); | |
4050 | mlxsw_reg_pmtu_oper_mtu_set(payload, 0); | |
4051 | } | |
4052 | ||
4053 | /* PTYS - Port Type and Speed Register | |
4054 | * ----------------------------------- | |
4055 | * Configures and reports the port speed type. | |
4056 | * | |
4057 | * Note: When set while the link is up, the changes will not take effect | |
4058 | * until the port transitions from down to up state. | |
4059 | */ | |
4060 | #define MLXSW_REG_PTYS_ID 0x5004 | |
4061 | #define MLXSW_REG_PTYS_LEN 0x40 | |
4062 | ||
21978dcf | 4063 | MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); |
4ec14b76 | 4064 | |
8e1ed739 TB |
4065 | /* an_disable_admin |
4066 | * Auto negotiation disable administrative configuration | |
4067 | * 0 - Device doesn't support AN disable. | |
4068 | * 1 - Device supports AN disable. | |
4069 | * Access: RW | |
4070 | */ | |
4071 | MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); | |
4072 | ||
4ec14b76 IS |
4073 | /* reg_ptys_local_port |
4074 | * Local port number. | |
4075 | * Access: Index | |
4076 | */ | |
4077 | MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); | |
4078 | ||
79417702 | 4079 | #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) |
4ec14b76 IS |
4080 | #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) |
4081 | ||
4082 | /* reg_ptys_proto_mask | |
4083 | * Protocol mask. Indicates which protocol is used. | |
4084 | * 0 - Infiniband. | |
4085 | * 1 - Fibre Channel. | |
4086 | * 2 - Ethernet. | |
4087 | * Access: Index | |
4088 | */ | |
4089 | MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); | |
4090 | ||
4149b97f IS |
4091 | enum { |
4092 | MLXSW_REG_PTYS_AN_STATUS_NA, | |
4093 | MLXSW_REG_PTYS_AN_STATUS_OK, | |
4094 | MLXSW_REG_PTYS_AN_STATUS_FAIL, | |
4095 | }; | |
4096 | ||
4097 | /* reg_ptys_an_status | |
4098 | * Autonegotiation status. | |
4099 | * Access: RO | |
4100 | */ | |
4101 | MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); | |
4102 | ||
9ce84397 ST |
4103 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) |
4104 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) | |
4105 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) | |
4106 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) | |
4107 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) | |
4108 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) | |
4109 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) | |
4110 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) | |
4111 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) | |
4112 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) | |
4113 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) | |
4114 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) | |
5bd29b9b | 4115 | #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) |
9ce84397 ST |
4116 | |
4117 | /* reg_ptys_ext_eth_proto_cap | |
4118 | * Extended Ethernet port supported speeds and protocols. | |
4119 | * Access: RO | |
4120 | */ | |
4121 | MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); | |
4122 | ||
4ec14b76 IS |
4123 | #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) |
4124 | #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) | |
4125 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) | |
4126 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) | |
4127 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) | |
4128 | #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) | |
4129 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) | |
4130 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) | |
4ec14b76 IS |
4131 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) |
4132 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) | |
4133 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) | |
4134 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) | |
4135 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) | |
b9d66a36 | 4136 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) |
4ec14b76 IS |
4137 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) |
4138 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) | |
4139 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) | |
4140 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) | |
4141 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) | |
4142 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) | |
4143 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) | |
4144 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) | |
4145 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) | |
4146 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) | |
4147 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) | |
4148 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) | |
4149 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) | |
4150 | ||
4151 | /* reg_ptys_eth_proto_cap | |
4152 | * Ethernet port supported speeds and protocols. | |
4153 | * Access: RO | |
4154 | */ | |
4155 | MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); | |
4156 | ||
79417702 ER |
4157 | /* reg_ptys_ib_link_width_cap |
4158 | * IB port supported widths. | |
4159 | * Access: RO | |
4160 | */ | |
4161 | MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); | |
4162 | ||
4163 | #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) | |
4164 | #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) | |
4165 | #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) | |
4166 | #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) | |
4167 | #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) | |
4168 | #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) | |
4169 | ||
4170 | /* reg_ptys_ib_proto_cap | |
4171 | * IB port supported speeds and protocols. | |
4172 | * Access: RO | |
4173 | */ | |
4174 | MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); | |
4175 | ||
9ce84397 ST |
4176 | /* reg_ptys_ext_eth_proto_admin |
4177 | * Extended speed and protocol to set port to. | |
4178 | * Access: RW | |
4179 | */ | |
4180 | MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); | |
4181 | ||
4ec14b76 IS |
4182 | /* reg_ptys_eth_proto_admin |
4183 | * Speed and protocol to set port to. | |
4184 | * Access: RW | |
4185 | */ | |
4186 | MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); | |
4187 | ||
79417702 ER |
4188 | /* reg_ptys_ib_link_width_admin |
4189 | * IB width to set port to. | |
4190 | * Access: RW | |
4191 | */ | |
4192 | MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); | |
4193 | ||
4194 | /* reg_ptys_ib_proto_admin | |
4195 | * IB speeds and protocols to set port to. | |
4196 | * Access: RW | |
4197 | */ | |
4198 | MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); | |
4199 | ||
9ce84397 ST |
4200 | /* reg_ptys_ext_eth_proto_oper |
4201 | * The extended current speed and protocol configured for the port. | |
4202 | * Access: RO | |
4203 | */ | |
4204 | MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); | |
4205 | ||
4ec14b76 IS |
4206 | /* reg_ptys_eth_proto_oper |
4207 | * The current speed and protocol configured for the port. | |
4208 | * Access: RO | |
4209 | */ | |
4210 | MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); | |
4211 | ||
79417702 ER |
4212 | /* reg_ptys_ib_link_width_oper |
4213 | * The current IB width to set port to. | |
4214 | * Access: RO | |
4215 | */ | |
4216 | MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); | |
4217 | ||
4218 | /* reg_ptys_ib_proto_oper | |
4219 | * The current IB speed and protocol. | |
4220 | * Access: RO | |
4221 | */ | |
4222 | MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); | |
4223 | ||
1e2f66ec ST |
4224 | enum mlxsw_reg_ptys_connector_type { |
4225 | MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, | |
4226 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, | |
4227 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, | |
4228 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, | |
4229 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, | |
4230 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, | |
4231 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, | |
4232 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, | |
4233 | MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, | |
4234 | }; | |
4235 | ||
4236 | /* reg_ptys_connector_type | |
4237 | * Connector type indication. | |
4238 | * Access: RO | |
4239 | */ | |
4240 | MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); | |
4241 | ||
401c8b4e | 4242 | static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, |
8e1ed739 | 4243 | u32 proto_admin, bool autoneg) |
4ec14b76 IS |
4244 | { |
4245 | MLXSW_REG_ZERO(ptys, payload); | |
4246 | mlxsw_reg_ptys_local_port_set(payload, local_port); | |
4247 | mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); | |
4248 | mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); | |
8e1ed739 | 4249 | mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); |
4ec14b76 IS |
4250 | } |
4251 | ||
9ce84397 ST |
4252 | static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, |
4253 | u32 proto_admin, bool autoneg) | |
4254 | { | |
4255 | MLXSW_REG_ZERO(ptys, payload); | |
4256 | mlxsw_reg_ptys_local_port_set(payload, local_port); | |
4257 | mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); | |
4258 | mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); | |
4259 | mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); | |
4260 | } | |
4261 | ||
401c8b4e ER |
4262 | static inline void mlxsw_reg_ptys_eth_unpack(char *payload, |
4263 | u32 *p_eth_proto_cap, | |
e6f66f50 | 4264 | u32 *p_eth_proto_admin, |
401c8b4e | 4265 | u32 *p_eth_proto_oper) |
4ec14b76 IS |
4266 | { |
4267 | if (p_eth_proto_cap) | |
1dc3c0a2 ST |
4268 | *p_eth_proto_cap = |
4269 | mlxsw_reg_ptys_eth_proto_cap_get(payload); | |
e6f66f50 | 4270 | if (p_eth_proto_admin) |
1dc3c0a2 ST |
4271 | *p_eth_proto_admin = |
4272 | mlxsw_reg_ptys_eth_proto_admin_get(payload); | |
4ec14b76 | 4273 | if (p_eth_proto_oper) |
1dc3c0a2 ST |
4274 | *p_eth_proto_oper = |
4275 | mlxsw_reg_ptys_eth_proto_oper_get(payload); | |
4ec14b76 IS |
4276 | } |
4277 | ||
9ce84397 ST |
4278 | static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, |
4279 | u32 *p_eth_proto_cap, | |
4280 | u32 *p_eth_proto_admin, | |
4281 | u32 *p_eth_proto_oper) | |
4282 | { | |
4283 | if (p_eth_proto_cap) | |
4284 | *p_eth_proto_cap = | |
4285 | mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); | |
4286 | if (p_eth_proto_admin) | |
4287 | *p_eth_proto_admin = | |
4288 | mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); | |
4289 | if (p_eth_proto_oper) | |
4290 | *p_eth_proto_oper = | |
4291 | mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); | |
4292 | } | |
4293 | ||
79417702 ER |
4294 | static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, |
4295 | u16 proto_admin, u16 link_width) | |
4296 | { | |
4297 | MLXSW_REG_ZERO(ptys, payload); | |
4298 | mlxsw_reg_ptys_local_port_set(payload, local_port); | |
4299 | mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); | |
4300 | mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); | |
4301 | mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); | |
4302 | } | |
4303 | ||
4304 | static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, | |
4305 | u16 *p_ib_link_width_cap, | |
4306 | u16 *p_ib_proto_oper, | |
4307 | u16 *p_ib_link_width_oper) | |
4308 | { | |
4309 | if (p_ib_proto_cap) | |
4310 | *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); | |
4311 | if (p_ib_link_width_cap) | |
4312 | *p_ib_link_width_cap = | |
4313 | mlxsw_reg_ptys_ib_link_width_cap_get(payload); | |
4314 | if (p_ib_proto_oper) | |
4315 | *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); | |
4316 | if (p_ib_link_width_oper) | |
4317 | *p_ib_link_width_oper = | |
4318 | mlxsw_reg_ptys_ib_link_width_oper_get(payload); | |
4319 | } | |
4320 | ||
4ec14b76 IS |
4321 | /* PPAD - Port Physical Address Register |
4322 | * ------------------------------------- | |
4323 | * The PPAD register configures the per port physical MAC address. | |
4324 | */ | |
4325 | #define MLXSW_REG_PPAD_ID 0x5005 | |
4326 | #define MLXSW_REG_PPAD_LEN 0x10 | |
4327 | ||
21978dcf | 4328 | MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); |
4ec14b76 IS |
4329 | |
4330 | /* reg_ppad_single_base_mac | |
4331 | * 0: base_mac, local port should be 0 and mac[7:0] is | |
4332 | * reserved. HW will set incremental | |
4333 | * 1: single_mac - mac of the local_port | |
4334 | * Access: RW | |
4335 | */ | |
4336 | MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); | |
4337 | ||
4338 | /* reg_ppad_local_port | |
4339 | * port number, if single_base_mac = 0 then local_port is reserved | |
4340 | * Access: RW | |
4341 | */ | |
4342 | MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); | |
4343 | ||
4344 | /* reg_ppad_mac | |
4345 | * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. | |
4346 | * If single_base_mac = 1 - the per port MAC address | |
4347 | * Access: RW | |
4348 | */ | |
4349 | MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); | |
4350 | ||
4351 | static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, | |
4352 | u8 local_port) | |
4353 | { | |
4354 | MLXSW_REG_ZERO(ppad, payload); | |
4355 | mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); | |
4356 | mlxsw_reg_ppad_local_port_set(payload, local_port); | |
4357 | } | |
4358 | ||
4359 | /* PAOS - Ports Administrative and Operational Status Register | |
4360 | * ----------------------------------------------------------- | |
4361 | * Configures and retrieves per port administrative and operational status. | |
4362 | */ | |
4363 | #define MLXSW_REG_PAOS_ID 0x5006 | |
4364 | #define MLXSW_REG_PAOS_LEN 0x10 | |
4365 | ||
21978dcf | 4366 | MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); |
4ec14b76 IS |
4367 | |
4368 | /* reg_paos_swid | |
4369 | * Switch partition ID with which to associate the port. | |
4370 | * Note: while external ports uses unique local port numbers (and thus swid is | |
4371 | * redundant), router ports use the same local port number where swid is the | |
4372 | * only indication for the relevant port. | |
4373 | * Access: Index | |
4374 | */ | |
4375 | MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); | |
4376 | ||
4377 | /* reg_paos_local_port | |
4378 | * Local port number. | |
4379 | * Access: Index | |
4380 | */ | |
4381 | MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); | |
4382 | ||
4383 | /* reg_paos_admin_status | |
4384 | * Port administrative state (the desired state of the port): | |
4385 | * 1 - Up. | |
4386 | * 2 - Down. | |
4387 | * 3 - Up once. This means that in case of link failure, the port won't go | |
4388 | * into polling mode, but will wait to be re-enabled by software. | |
4389 | * 4 - Disabled by system. Can only be set by hardware. | |
4390 | * Access: RW | |
4391 | */ | |
4392 | MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); | |
4393 | ||
4394 | /* reg_paos_oper_status | |
4395 | * Port operational state (the current state): | |
4396 | * 1 - Up. | |
4397 | * 2 - Down. | |
4398 | * 3 - Down by port failure. This means that the device will not let the | |
4399 | * port up again until explicitly specified by software. | |
4400 | * Access: RO | |
4401 | */ | |
4402 | MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); | |
4403 | ||
4404 | /* reg_paos_ase | |
4405 | * Admin state update enabled. | |
4406 | * Access: WO | |
4407 | */ | |
4408 | MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); | |
4409 | ||
4410 | /* reg_paos_ee | |
4411 | * Event update enable. If this bit is set, event generation will be | |
4412 | * updated based on the e field. | |
4413 | * Access: WO | |
4414 | */ | |
4415 | MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); | |
4416 | ||
4417 | /* reg_paos_e | |
4418 | * Event generation on operational state change: | |
4419 | * 0 - Do not generate event. | |
4420 | * 1 - Generate Event. | |
4421 | * 2 - Generate Single Event. | |
4422 | * Access: RW | |
4423 | */ | |
4424 | MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); | |
4425 | ||
4426 | static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, | |
4427 | enum mlxsw_port_admin_status status) | |
4428 | { | |
4429 | MLXSW_REG_ZERO(paos, payload); | |
4430 | mlxsw_reg_paos_swid_set(payload, 0); | |
4431 | mlxsw_reg_paos_local_port_set(payload, local_port); | |
4432 | mlxsw_reg_paos_admin_status_set(payload, status); | |
4433 | mlxsw_reg_paos_oper_status_set(payload, 0); | |
4434 | mlxsw_reg_paos_ase_set(payload, 1); | |
4435 | mlxsw_reg_paos_ee_set(payload, 1); | |
4436 | mlxsw_reg_paos_e_set(payload, 1); | |
4437 | } | |
4438 | ||
6f253d83 IS |
4439 | /* PFCC - Ports Flow Control Configuration Register |
4440 | * ------------------------------------------------ | |
4441 | * Configures and retrieves the per port flow control configuration. | |
4442 | */ | |
4443 | #define MLXSW_REG_PFCC_ID 0x5007 | |
4444 | #define MLXSW_REG_PFCC_LEN 0x20 | |
4445 | ||
21978dcf | 4446 | MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); |
6f253d83 IS |
4447 | |
4448 | /* reg_pfcc_local_port | |
4449 | * Local port number. | |
4450 | * Access: Index | |
4451 | */ | |
4452 | MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); | |
4453 | ||
4454 | /* reg_pfcc_pnat | |
4455 | * Port number access type. Determines the way local_port is interpreted: | |
4456 | * 0 - Local port number. | |
4457 | * 1 - IB / label port number. | |
4458 | * Access: Index | |
4459 | */ | |
4460 | MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); | |
4461 | ||
4462 | /* reg_pfcc_shl_cap | |
4463 | * Send to higher layers capabilities: | |
4464 | * 0 - No capability of sending Pause and PFC frames to higher layers. | |
4465 | * 1 - Device has capability of sending Pause and PFC frames to higher | |
4466 | * layers. | |
4467 | * Access: RO | |
4468 | */ | |
4469 | MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); | |
4470 | ||
4471 | /* reg_pfcc_shl_opr | |
4472 | * Send to higher layers operation: | |
4473 | * 0 - Pause and PFC frames are handled by the port (default). | |
4474 | * 1 - Pause and PFC frames are handled by the port and also sent to | |
4475 | * higher layers. Only valid if shl_cap = 1. | |
4476 | * Access: RW | |
4477 | */ | |
4478 | MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); | |
4479 | ||
4480 | /* reg_pfcc_ppan | |
4481 | * Pause policy auto negotiation. | |
4482 | * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. | |
4483 | * 1 - Enabled. When auto-negotiation is performed, set the Pause policy | |
4484 | * based on the auto-negotiation resolution. | |
4485 | * Access: RW | |
4486 | * | |
4487 | * Note: The auto-negotiation advertisement is set according to pptx and | |
4488 | * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. | |
4489 | */ | |
4490 | MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); | |
4491 | ||
4492 | /* reg_pfcc_prio_mask_tx | |
4493 | * Bit per priority indicating if Tx flow control policy should be | |
4494 | * updated based on bit pfctx. | |
4495 | * Access: WO | |
4496 | */ | |
4497 | MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); | |
4498 | ||
4499 | /* reg_pfcc_prio_mask_rx | |
4500 | * Bit per priority indicating if Rx flow control policy should be | |
4501 | * updated based on bit pfcrx. | |
4502 | * Access: WO | |
4503 | */ | |
4504 | MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); | |
4505 | ||
4506 | /* reg_pfcc_pptx | |
4507 | * Admin Pause policy on Tx. | |
4508 | * 0 - Never generate Pause frames (default). | |
4509 | * 1 - Generate Pause frames according to Rx buffer threshold. | |
4510 | * Access: RW | |
4511 | */ | |
4512 | MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); | |
4513 | ||
4514 | /* reg_pfcc_aptx | |
4515 | * Active (operational) Pause policy on Tx. | |
4516 | * 0 - Never generate Pause frames. | |
4517 | * 1 - Generate Pause frames according to Rx buffer threshold. | |
4518 | * Access: RO | |
4519 | */ | |
4520 | MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); | |
4521 | ||
4522 | /* reg_pfcc_pfctx | |
4523 | * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: | |
4524 | * 0 - Never generate priority Pause frames on the specified priority | |
4525 | * (default). | |
4526 | * 1 - Generate priority Pause frames according to Rx buffer threshold on | |
4527 | * the specified priority. | |
4528 | * Access: RW | |
4529 | * | |
4530 | * Note: pfctx and pptx must be mutually exclusive. | |
4531 | */ | |
4532 | MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); | |
4533 | ||
4534 | /* reg_pfcc_pprx | |
4535 | * Admin Pause policy on Rx. | |
4536 | * 0 - Ignore received Pause frames (default). | |
4537 | * 1 - Respect received Pause frames. | |
4538 | * Access: RW | |
4539 | */ | |
4540 | MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); | |
4541 | ||
4542 | /* reg_pfcc_aprx | |
4543 | * Active (operational) Pause policy on Rx. | |
4544 | * 0 - Ignore received Pause frames. | |
4545 | * 1 - Respect received Pause frames. | |
4546 | * Access: RO | |
4547 | */ | |
4548 | MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); | |
4549 | ||
4550 | /* reg_pfcc_pfcrx | |
4551 | * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: | |
4552 | * 0 - Ignore incoming priority Pause frames on the specified priority | |
4553 | * (default). | |
4554 | * 1 - Respect incoming priority Pause frames on the specified priority. | |
4555 | * Access: RW | |
4556 | */ | |
4557 | MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); | |
4558 | ||
d81a6bdb IS |
4559 | #define MLXSW_REG_PFCC_ALL_PRIO 0xFF |
4560 | ||
4561 | static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) | |
4562 | { | |
4563 | mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); | |
4564 | mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); | |
4565 | mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); | |
4566 | mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); | |
4567 | } | |
4568 | ||
6f253d83 IS |
4569 | static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) |
4570 | { | |
4571 | MLXSW_REG_ZERO(pfcc, payload); | |
4572 | mlxsw_reg_pfcc_local_port_set(payload, local_port); | |
4573 | } | |
4574 | ||
4ec14b76 IS |
4575 | /* PPCNT - Ports Performance Counters Register |
4576 | * ------------------------------------------- | |
4577 | * The PPCNT register retrieves per port performance counters. | |
4578 | */ | |
4579 | #define MLXSW_REG_PPCNT_ID 0x5008 | |
4580 | #define MLXSW_REG_PPCNT_LEN 0x100 | |
3e8c1fd3 | 4581 | #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 |
4ec14b76 | 4582 | |
21978dcf | 4583 | MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); |
4ec14b76 IS |
4584 | |
4585 | /* reg_ppcnt_swid | |
4586 | * For HCA: must be always 0. | |
4587 | * Switch partition ID to associate port with. | |
4588 | * Switch partitions are numbered from 0 to 7 inclusively. | |
4589 | * Switch partition 254 indicates stacking ports. | |
4590 | * Switch partition 255 indicates all switch partitions. | |
4591 | * Only valid on Set() operation with local_port=255. | |
4592 | * Access: Index | |
4593 | */ | |
4594 | MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); | |
4595 | ||
4596 | /* reg_ppcnt_local_port | |
4597 | * Local port number. | |
4598 | * 255 indicates all ports on the device, and is only allowed | |
4599 | * for Set() operation. | |
4600 | * Access: Index | |
4601 | */ | |
4602 | MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); | |
4603 | ||
4604 | /* reg_ppcnt_pnat | |
4605 | * Port number access type: | |
4606 | * 0 - Local port number | |
4607 | * 1 - IB port number | |
4608 | * Access: Index | |
4609 | */ | |
4610 | MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); | |
4611 | ||
34dba0a5 IS |
4612 | enum mlxsw_reg_ppcnt_grp { |
4613 | MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, | |
bae4e109 | 4614 | MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, |
1222d15a | 4615 | MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, |
bae4e109 | 4616 | MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, |
0afc1221 | 4617 | MLXSW_REG_PPCNT_EXT_CNT = 0x5, |
bae4e109 | 4618 | MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, |
34dba0a5 | 4619 | MLXSW_REG_PPCNT_PRIO_CNT = 0x10, |
df4750e8 | 4620 | MLXSW_REG_PPCNT_TC_CNT = 0x11, |
0afc1221 | 4621 | MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, |
34dba0a5 IS |
4622 | }; |
4623 | ||
4ec14b76 IS |
4624 | /* reg_ppcnt_grp |
4625 | * Performance counter group. | |
4626 | * Group 63 indicates all groups. Only valid on Set() operation with | |
4627 | * clr bit set. | |
4628 | * 0x0: IEEE 802.3 Counters | |
4629 | * 0x1: RFC 2863 Counters | |
4630 | * 0x2: RFC 2819 Counters | |
4631 | * 0x3: RFC 3635 Counters | |
4632 | * 0x5: Ethernet Extended Counters | |
bae4e109 | 4633 | * 0x6: Ethernet Discard Counters |
4ec14b76 IS |
4634 | * 0x8: Link Level Retransmission Counters |
4635 | * 0x10: Per Priority Counters | |
4636 | * 0x11: Per Traffic Class Counters | |
4637 | * 0x12: Physical Layer Counters | |
0afc1221 | 4638 | * 0x13: Per Traffic Class Congestion Counters |
4ec14b76 IS |
4639 | * Access: Index |
4640 | */ | |
4641 | MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); | |
4642 | ||
4643 | /* reg_ppcnt_clr | |
4644 | * Clear counters. Setting the clr bit will reset the counter value | |
4645 | * for all counters in the counter group. This bit can be set | |
4646 | * for both Set() and Get() operation. | |
4647 | * Access: OP | |
4648 | */ | |
4649 | MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); | |
4650 | ||
4651 | /* reg_ppcnt_prio_tc | |
4652 | * Priority for counter set that support per priority, valid values: 0-7. | |
4653 | * Traffic class for counter set that support per traffic class, | |
4654 | * valid values: 0- cap_max_tclass-1 . | |
4655 | * For HCA: cap_max_tclass is always 8. | |
4656 | * Otherwise must be 0. | |
4657 | * Access: Index | |
4658 | */ | |
4659 | MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); | |
4660 | ||
34dba0a5 IS |
4661 | /* Ethernet IEEE 802.3 Counter Group */ |
4662 | ||
4ec14b76 IS |
4663 | /* reg_ppcnt_a_frames_transmitted_ok |
4664 | * Access: RO | |
4665 | */ | |
4666 | MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, | |
3e8c1fd3 | 4667 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); |
4ec14b76 IS |
4668 | |
4669 | /* reg_ppcnt_a_frames_received_ok | |
4670 | * Access: RO | |
4671 | */ | |
4672 | MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, | |
3e8c1fd3 | 4673 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); |
4ec14b76 IS |
4674 | |
4675 | /* reg_ppcnt_a_frame_check_sequence_errors | |
4676 | * Access: RO | |
4677 | */ | |
4678 | MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, | |
3e8c1fd3 | 4679 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); |
4ec14b76 IS |
4680 | |
4681 | /* reg_ppcnt_a_alignment_errors | |
4682 | * Access: RO | |
4683 | */ | |
4684 | MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, | |
3e8c1fd3 | 4685 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); |
4ec14b76 IS |
4686 | |
4687 | /* reg_ppcnt_a_octets_transmitted_ok | |
4688 | * Access: RO | |
4689 | */ | |
4690 | MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, | |
3e8c1fd3 | 4691 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); |
4ec14b76 IS |
4692 | |
4693 | /* reg_ppcnt_a_octets_received_ok | |
4694 | * Access: RO | |
4695 | */ | |
4696 | MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, | |
3e8c1fd3 | 4697 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); |
4ec14b76 IS |
4698 | |
4699 | /* reg_ppcnt_a_multicast_frames_xmitted_ok | |
4700 | * Access: RO | |
4701 | */ | |
4702 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, | |
3e8c1fd3 | 4703 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); |
4ec14b76 IS |
4704 | |
4705 | /* reg_ppcnt_a_broadcast_frames_xmitted_ok | |
4706 | * Access: RO | |
4707 | */ | |
4708 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, | |
3e8c1fd3 | 4709 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); |
4ec14b76 IS |
4710 | |
4711 | /* reg_ppcnt_a_multicast_frames_received_ok | |
4712 | * Access: RO | |
4713 | */ | |
4714 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, | |
3e8c1fd3 | 4715 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); |
4ec14b76 IS |
4716 | |
4717 | /* reg_ppcnt_a_broadcast_frames_received_ok | |
4718 | * Access: RO | |
4719 | */ | |
4720 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, | |
3e8c1fd3 | 4721 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); |
4ec14b76 IS |
4722 | |
4723 | /* reg_ppcnt_a_in_range_length_errors | |
4724 | * Access: RO | |
4725 | */ | |
4726 | MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, | |
3e8c1fd3 | 4727 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); |
4ec14b76 IS |
4728 | |
4729 | /* reg_ppcnt_a_out_of_range_length_field | |
4730 | * Access: RO | |
4731 | */ | |
4732 | MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, | |
3e8c1fd3 | 4733 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); |
4ec14b76 IS |
4734 | |
4735 | /* reg_ppcnt_a_frame_too_long_errors | |
4736 | * Access: RO | |
4737 | */ | |
4738 | MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, | |
3e8c1fd3 | 4739 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); |
4ec14b76 IS |
4740 | |
4741 | /* reg_ppcnt_a_symbol_error_during_carrier | |
4742 | * Access: RO | |
4743 | */ | |
4744 | MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, | |
3e8c1fd3 | 4745 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); |
4ec14b76 IS |
4746 | |
4747 | /* reg_ppcnt_a_mac_control_frames_transmitted | |
4748 | * Access: RO | |
4749 | */ | |
4750 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, | |
3e8c1fd3 | 4751 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); |
4ec14b76 IS |
4752 | |
4753 | /* reg_ppcnt_a_mac_control_frames_received | |
4754 | * Access: RO | |
4755 | */ | |
4756 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, | |
3e8c1fd3 | 4757 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); |
4ec14b76 IS |
4758 | |
4759 | /* reg_ppcnt_a_unsupported_opcodes_received | |
4760 | * Access: RO | |
4761 | */ | |
4762 | MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, | |
3e8c1fd3 | 4763 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); |
4ec14b76 IS |
4764 | |
4765 | /* reg_ppcnt_a_pause_mac_ctrl_frames_received | |
4766 | * Access: RO | |
4767 | */ | |
4768 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, | |
3e8c1fd3 | 4769 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); |
4ec14b76 IS |
4770 | |
4771 | /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted | |
4772 | * Access: RO | |
4773 | */ | |
4774 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, | |
3e8c1fd3 | 4775 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); |
4ec14b76 | 4776 | |
bae4e109 ST |
4777 | /* Ethernet RFC 2863 Counter Group */ |
4778 | ||
4779 | /* reg_ppcnt_if_in_discards | |
4780 | * Access: RO | |
4781 | */ | |
4782 | MLXSW_ITEM64(reg, ppcnt, if_in_discards, | |
4783 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); | |
4784 | ||
4785 | /* reg_ppcnt_if_out_discards | |
4786 | * Access: RO | |
4787 | */ | |
4788 | MLXSW_ITEM64(reg, ppcnt, if_out_discards, | |
4789 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); | |
4790 | ||
4791 | /* reg_ppcnt_if_out_errors | |
4792 | * Access: RO | |
4793 | */ | |
4794 | MLXSW_ITEM64(reg, ppcnt, if_out_errors, | |
4795 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); | |
4796 | ||
1222d15a JP |
4797 | /* Ethernet RFC 2819 Counter Group */ |
4798 | ||
bae4e109 ST |
4799 | /* reg_ppcnt_ether_stats_undersize_pkts |
4800 | * Access: RO | |
4801 | */ | |
4802 | MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, | |
4803 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); | |
4804 | ||
4805 | /* reg_ppcnt_ether_stats_oversize_pkts | |
4806 | * Access: RO | |
4807 | */ | |
4808 | MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, | |
4809 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); | |
4810 | ||
4811 | /* reg_ppcnt_ether_stats_fragments | |
4812 | * Access: RO | |
4813 | */ | |
4814 | MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, | |
4815 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); | |
4816 | ||
1222d15a JP |
4817 | /* reg_ppcnt_ether_stats_pkts64octets |
4818 | * Access: RO | |
4819 | */ | |
4820 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, | |
4821 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); | |
4822 | ||
4823 | /* reg_ppcnt_ether_stats_pkts65to127octets | |
4824 | * Access: RO | |
4825 | */ | |
4826 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, | |
4827 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); | |
4828 | ||
4829 | /* reg_ppcnt_ether_stats_pkts128to255octets | |
4830 | * Access: RO | |
4831 | */ | |
4832 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, | |
4833 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); | |
4834 | ||
4835 | /* reg_ppcnt_ether_stats_pkts256to511octets | |
4836 | * Access: RO | |
4837 | */ | |
4838 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, | |
4839 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); | |
4840 | ||
4841 | /* reg_ppcnt_ether_stats_pkts512to1023octets | |
4842 | * Access: RO | |
4843 | */ | |
4844 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, | |
4845 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); | |
4846 | ||
4847 | /* reg_ppcnt_ether_stats_pkts1024to1518octets | |
4848 | * Access: RO | |
4849 | */ | |
4850 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, | |
4851 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); | |
4852 | ||
4853 | /* reg_ppcnt_ether_stats_pkts1519to2047octets | |
4854 | * Access: RO | |
4855 | */ | |
4856 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, | |
4857 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); | |
4858 | ||
4859 | /* reg_ppcnt_ether_stats_pkts2048to4095octets | |
4860 | * Access: RO | |
4861 | */ | |
4862 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, | |
4863 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); | |
4864 | ||
4865 | /* reg_ppcnt_ether_stats_pkts4096to8191octets | |
4866 | * Access: RO | |
4867 | */ | |
4868 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, | |
4869 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); | |
4870 | ||
4871 | /* reg_ppcnt_ether_stats_pkts8192to10239octets | |
4872 | * Access: RO | |
4873 | */ | |
4874 | MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, | |
4875 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); | |
4876 | ||
bae4e109 ST |
4877 | /* Ethernet RFC 3635 Counter Group */ |
4878 | ||
4879 | /* reg_ppcnt_dot3stats_fcs_errors | |
4880 | * Access: RO | |
4881 | */ | |
4882 | MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, | |
4883 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); | |
4884 | ||
4885 | /* reg_ppcnt_dot3stats_symbol_errors | |
4886 | * Access: RO | |
4887 | */ | |
4888 | MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, | |
4889 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); | |
4890 | ||
4891 | /* reg_ppcnt_dot3control_in_unknown_opcodes | |
4892 | * Access: RO | |
4893 | */ | |
4894 | MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, | |
4895 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); | |
4896 | ||
4897 | /* reg_ppcnt_dot3in_pause_frames | |
4898 | * Access: RO | |
4899 | */ | |
4900 | MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, | |
4901 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); | |
4902 | ||
0afc1221 YM |
4903 | /* Ethernet Extended Counter Group Counters */ |
4904 | ||
4905 | /* reg_ppcnt_ecn_marked | |
4906 | * Access: RO | |
4907 | */ | |
4908 | MLXSW_ITEM64(reg, ppcnt, ecn_marked, | |
4909 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); | |
4910 | ||
bae4e109 ST |
4911 | /* Ethernet Discard Counter Group Counters */ |
4912 | ||
4913 | /* reg_ppcnt_ingress_general | |
4914 | * Access: RO | |
4915 | */ | |
4916 | MLXSW_ITEM64(reg, ppcnt, ingress_general, | |
4917 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); | |
4918 | ||
4919 | /* reg_ppcnt_ingress_policy_engine | |
4920 | * Access: RO | |
4921 | */ | |
4922 | MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, | |
4923 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); | |
4924 | ||
4925 | /* reg_ppcnt_ingress_vlan_membership | |
4926 | * Access: RO | |
4927 | */ | |
4928 | MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, | |
4929 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); | |
4930 | ||
4931 | /* reg_ppcnt_ingress_tag_frame_type | |
4932 | * Access: RO | |
4933 | */ | |
4934 | MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, | |
4935 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); | |
4936 | ||
4937 | /* reg_ppcnt_egress_vlan_membership | |
4938 | * Access: RO | |
4939 | */ | |
4940 | MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, | |
4941 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); | |
4942 | ||
4943 | /* reg_ppcnt_loopback_filter | |
4944 | * Access: RO | |
4945 | */ | |
4946 | MLXSW_ITEM64(reg, ppcnt, loopback_filter, | |
4947 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); | |
4948 | ||
4949 | /* reg_ppcnt_egress_general | |
4950 | * Access: RO | |
4951 | */ | |
4952 | MLXSW_ITEM64(reg, ppcnt, egress_general, | |
4953 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); | |
4954 | ||
4955 | /* reg_ppcnt_egress_hoq | |
4956 | * Access: RO | |
4957 | */ | |
4958 | MLXSW_ITEM64(reg, ppcnt, egress_hoq, | |
4959 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); | |
4960 | ||
4961 | /* reg_ppcnt_egress_policy_engine | |
4962 | * Access: RO | |
4963 | */ | |
4964 | MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, | |
4965 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); | |
4966 | ||
4967 | /* reg_ppcnt_ingress_tx_link_down | |
4968 | * Access: RO | |
4969 | */ | |
4970 | MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, | |
4971 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); | |
4972 | ||
4973 | /* reg_ppcnt_egress_stp_filter | |
4974 | * Access: RO | |
4975 | */ | |
4976 | MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, | |
4977 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); | |
4978 | ||
4979 | /* reg_ppcnt_egress_sll | |
4980 | * Access: RO | |
4981 | */ | |
4982 | MLXSW_ITEM64(reg, ppcnt, egress_sll, | |
4983 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); | |
4984 | ||
34dba0a5 IS |
4985 | /* Ethernet Per Priority Group Counters */ |
4986 | ||
4987 | /* reg_ppcnt_rx_octets | |
4988 | * Access: RO | |
4989 | */ | |
3e8c1fd3 NF |
4990 | MLXSW_ITEM64(reg, ppcnt, rx_octets, |
4991 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); | |
34dba0a5 IS |
4992 | |
4993 | /* reg_ppcnt_rx_frames | |
4994 | * Access: RO | |
4995 | */ | |
3e8c1fd3 NF |
4996 | MLXSW_ITEM64(reg, ppcnt, rx_frames, |
4997 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); | |
34dba0a5 IS |
4998 | |
4999 | /* reg_ppcnt_tx_octets | |
5000 | * Access: RO | |
5001 | */ | |
3e8c1fd3 NF |
5002 | MLXSW_ITEM64(reg, ppcnt, tx_octets, |
5003 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); | |
34dba0a5 IS |
5004 | |
5005 | /* reg_ppcnt_tx_frames | |
5006 | * Access: RO | |
5007 | */ | |
3e8c1fd3 NF |
5008 | MLXSW_ITEM64(reg, ppcnt, tx_frames, |
5009 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); | |
34dba0a5 IS |
5010 | |
5011 | /* reg_ppcnt_rx_pause | |
5012 | * Access: RO | |
5013 | */ | |
3e8c1fd3 NF |
5014 | MLXSW_ITEM64(reg, ppcnt, rx_pause, |
5015 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); | |
34dba0a5 IS |
5016 | |
5017 | /* reg_ppcnt_rx_pause_duration | |
5018 | * Access: RO | |
5019 | */ | |
3e8c1fd3 NF |
5020 | MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, |
5021 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); | |
34dba0a5 IS |
5022 | |
5023 | /* reg_ppcnt_tx_pause | |
5024 | * Access: RO | |
5025 | */ | |
3e8c1fd3 NF |
5026 | MLXSW_ITEM64(reg, ppcnt, tx_pause, |
5027 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); | |
34dba0a5 IS |
5028 | |
5029 | /* reg_ppcnt_tx_pause_duration | |
5030 | * Access: RO | |
5031 | */ | |
3e8c1fd3 NF |
5032 | MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, |
5033 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); | |
34dba0a5 IS |
5034 | |
5035 | /* reg_ppcnt_rx_pause_transition | |
5036 | * Access: RO | |
5037 | */ | |
3e8c1fd3 NF |
5038 | MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, |
5039 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); | |
34dba0a5 | 5040 | |
df4750e8 IS |
5041 | /* Ethernet Per Traffic Group Counters */ |
5042 | ||
5043 | /* reg_ppcnt_tc_transmit_queue | |
5044 | * Contains the transmit queue depth in cells of traffic class | |
5045 | * selected by prio_tc and the port selected by local_port. | |
5046 | * The field cannot be cleared. | |
5047 | * Access: RO | |
5048 | */ | |
3e8c1fd3 NF |
5049 | MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, |
5050 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); | |
df4750e8 IS |
5051 | |
5052 | /* reg_ppcnt_tc_no_buffer_discard_uc | |
5053 | * The number of unicast packets dropped due to lack of shared | |
5054 | * buffer resources. | |
5055 | * Access: RO | |
5056 | */ | |
3e8c1fd3 NF |
5057 | MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, |
5058 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); | |
df4750e8 | 5059 | |
0afc1221 YM |
5060 | /* Ethernet Per Traffic Class Congestion Group Counters */ |
5061 | ||
5062 | /* reg_ppcnt_wred_discard | |
5063 | * Access: RO | |
5064 | */ | |
5065 | MLXSW_ITEM64(reg, ppcnt, wred_discard, | |
5066 | MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); | |
5067 | ||
34dba0a5 IS |
5068 | static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, |
5069 | enum mlxsw_reg_ppcnt_grp grp, | |
5070 | u8 prio_tc) | |
4ec14b76 IS |
5071 | { |
5072 | MLXSW_REG_ZERO(ppcnt, payload); | |
5073 | mlxsw_reg_ppcnt_swid_set(payload, 0); | |
5074 | mlxsw_reg_ppcnt_local_port_set(payload, local_port); | |
5075 | mlxsw_reg_ppcnt_pnat_set(payload, 0); | |
34dba0a5 | 5076 | mlxsw_reg_ppcnt_grp_set(payload, grp); |
4ec14b76 | 5077 | mlxsw_reg_ppcnt_clr_set(payload, 0); |
34dba0a5 | 5078 | mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); |
4ec14b76 IS |
5079 | } |
5080 | ||
7136793e ER |
5081 | /* PLIB - Port Local to InfiniBand Port |
5082 | * ------------------------------------ | |
5083 | * The PLIB register performs mapping from Local Port into InfiniBand Port. | |
5084 | */ | |
5085 | #define MLXSW_REG_PLIB_ID 0x500A | |
5086 | #define MLXSW_REG_PLIB_LEN 0x10 | |
5087 | ||
5088 | MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); | |
5089 | ||
5090 | /* reg_plib_local_port | |
5091 | * Local port number. | |
5092 | * Access: Index | |
5093 | */ | |
5094 | MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); | |
5095 | ||
5096 | /* reg_plib_ib_port | |
5097 | * InfiniBand port remapping for local_port. | |
5098 | * Access: RW | |
5099 | */ | |
5100 | MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); | |
5101 | ||
b98ff151 IS |
5102 | /* PPTB - Port Prio To Buffer Register |
5103 | * ----------------------------------- | |
5104 | * Configures the switch priority to buffer table. | |
5105 | */ | |
5106 | #define MLXSW_REG_PPTB_ID 0x500B | |
11719a58 | 5107 | #define MLXSW_REG_PPTB_LEN 0x10 |
b98ff151 | 5108 | |
21978dcf | 5109 | MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); |
b98ff151 IS |
5110 | |
5111 | enum { | |
5112 | MLXSW_REG_PPTB_MM_UM, | |
5113 | MLXSW_REG_PPTB_MM_UNICAST, | |
5114 | MLXSW_REG_PPTB_MM_MULTICAST, | |
5115 | }; | |
5116 | ||
5117 | /* reg_pptb_mm | |
5118 | * Mapping mode. | |
5119 | * 0 - Map both unicast and multicast packets to the same buffer. | |
5120 | * 1 - Map only unicast packets. | |
5121 | * 2 - Map only multicast packets. | |
5122 | * Access: Index | |
5123 | * | |
5124 | * Note: SwitchX-2 only supports the first option. | |
5125 | */ | |
5126 | MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); | |
5127 | ||
5128 | /* reg_pptb_local_port | |
5129 | * Local port number. | |
5130 | * Access: Index | |
5131 | */ | |
5132 | MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); | |
5133 | ||
5134 | /* reg_pptb_um | |
5135 | * Enables the update of the untagged_buf field. | |
5136 | * Access: RW | |
5137 | */ | |
5138 | MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); | |
5139 | ||
5140 | /* reg_pptb_pm | |
5141 | * Enables the update of the prio_to_buff field. | |
5142 | * Bit <i> is a flag for updating the mapping for switch priority <i>. | |
5143 | * Access: RW | |
5144 | */ | |
5145 | MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); | |
5146 | ||
5147 | /* reg_pptb_prio_to_buff | |
5148 | * Mapping of switch priority <i> to one of the allocated receive port | |
5149 | * buffers. | |
5150 | * Access: RW | |
5151 | */ | |
5152 | MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); | |
5153 | ||
5154 | /* reg_pptb_pm_msb | |
5155 | * Enables the update of the prio_to_buff field. | |
5156 | * Bit <i> is a flag for updating the mapping for switch priority <i+8>. | |
5157 | * Access: RW | |
5158 | */ | |
5159 | MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); | |
5160 | ||
5161 | /* reg_pptb_untagged_buff | |
5162 | * Mapping of untagged frames to one of the allocated receive port buffers. | |
5163 | * Access: RW | |
5164 | * | |
5165 | * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for | |
5166 | * Spectrum, as it maps untagged packets based on the default switch priority. | |
5167 | */ | |
5168 | MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); | |
5169 | ||
11719a58 IS |
5170 | /* reg_pptb_prio_to_buff_msb |
5171 | * Mapping of switch priority <i+8> to one of the allocated receive port | |
5172 | * buffers. | |
5173 | * Access: RW | |
5174 | */ | |
5175 | MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); | |
5176 | ||
b98ff151 IS |
5177 | #define MLXSW_REG_PPTB_ALL_PRIO 0xFF |
5178 | ||
5179 | static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) | |
5180 | { | |
5181 | MLXSW_REG_ZERO(pptb, payload); | |
5182 | mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); | |
5183 | mlxsw_reg_pptb_local_port_set(payload, local_port); | |
5184 | mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); | |
11719a58 IS |
5185 | mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); |
5186 | } | |
5187 | ||
5188 | static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, | |
5189 | u8 buff) | |
5190 | { | |
5191 | mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); | |
5192 | mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); | |
b98ff151 IS |
5193 | } |
5194 | ||
e0594369 JP |
5195 | /* PBMC - Port Buffer Management Control Register |
5196 | * ---------------------------------------------- | |
5197 | * The PBMC register configures and retrieves the port packet buffer | |
5198 | * allocation for different Prios, and the Pause threshold management. | |
5199 | */ | |
5200 | #define MLXSW_REG_PBMC_ID 0x500C | |
7ad7cd61 | 5201 | #define MLXSW_REG_PBMC_LEN 0x6C |
e0594369 | 5202 | |
21978dcf | 5203 | MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); |
e0594369 JP |
5204 | |
5205 | /* reg_pbmc_local_port | |
5206 | * Local port number. | |
5207 | * Access: Index | |
5208 | */ | |
5209 | MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); | |
5210 | ||
5211 | /* reg_pbmc_xoff_timer_value | |
5212 | * When device generates a pause frame, it uses this value as the pause | |
5213 | * timer (time for the peer port to pause in quota-512 bit time). | |
5214 | * Access: RW | |
5215 | */ | |
5216 | MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); | |
5217 | ||
5218 | /* reg_pbmc_xoff_refresh | |
5219 | * The time before a new pause frame should be sent to refresh the pause RW | |
5220 | * state. Using the same units as xoff_timer_value above (in quota-512 bit | |
5221 | * time). | |
5222 | * Access: RW | |
5223 | */ | |
5224 | MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); | |
5225 | ||
d6b7c13b IS |
5226 | #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 |
5227 | ||
e0594369 JP |
5228 | /* reg_pbmc_buf_lossy |
5229 | * The field indicates if the buffer is lossy. | |
5230 | * 0 - Lossless | |
5231 | * 1 - Lossy | |
5232 | * Access: RW | |
5233 | */ | |
5234 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); | |
5235 | ||
5236 | /* reg_pbmc_buf_epsb | |
5237 | * Eligible for Port Shared buffer. | |
5238 | * If epsb is set, packets assigned to buffer are allowed to insert the port | |
5239 | * shared buffer. | |
5240 | * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. | |
5241 | * Access: RW | |
5242 | */ | |
5243 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); | |
5244 | ||
5245 | /* reg_pbmc_buf_size | |
5246 | * The part of the packet buffer array is allocated for the specific buffer. | |
5247 | * Units are represented in cells. | |
5248 | * Access: RW | |
5249 | */ | |
5250 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); | |
5251 | ||
155f9de2 IS |
5252 | /* reg_pbmc_buf_xoff_threshold |
5253 | * Once the amount of data in the buffer goes above this value, device | |
5254 | * starts sending PFC frames for all priorities associated with the | |
5255 | * buffer. Units are represented in cells. Reserved in case of lossy | |
5256 | * buffer. | |
5257 | * Access: RW | |
5258 | * | |
5259 | * Note: In Spectrum, reserved for buffer[9]. | |
5260 | */ | |
5261 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, | |
5262 | 0x08, 0x04, false); | |
5263 | ||
5264 | /* reg_pbmc_buf_xon_threshold | |
5265 | * When the amount of data in the buffer goes below this value, device | |
5266 | * stops sending PFC frames for the priorities associated with the | |
5267 | * buffer. Units are represented in cells. Reserved in case of lossy | |
5268 | * buffer. | |
5269 | * Access: RW | |
5270 | * | |
5271 | * Note: In Spectrum, reserved for buffer[9]. | |
5272 | */ | |
5273 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, | |
5274 | 0x08, 0x04, false); | |
5275 | ||
e0594369 JP |
5276 | static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, |
5277 | u16 xoff_timer_value, u16 xoff_refresh) | |
5278 | { | |
5279 | MLXSW_REG_ZERO(pbmc, payload); | |
5280 | mlxsw_reg_pbmc_local_port_set(payload, local_port); | |
5281 | mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); | |
5282 | mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); | |
5283 | } | |
5284 | ||
5285 | static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, | |
5286 | int buf_index, | |
5287 | u16 size) | |
5288 | { | |
5289 | mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); | |
5290 | mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); | |
5291 | mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); | |
5292 | } | |
5293 | ||
155f9de2 IS |
5294 | static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, |
5295 | int buf_index, u16 size, | |
5296 | u16 threshold) | |
5297 | { | |
5298 | mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); | |
5299 | mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); | |
5300 | mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); | |
5301 | mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); | |
5302 | mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); | |
5303 | } | |
5304 | ||
4ec14b76 IS |
5305 | /* PSPA - Port Switch Partition Allocation |
5306 | * --------------------------------------- | |
5307 | * Controls the association of a port with a switch partition and enables | |
5308 | * configuring ports as stacking ports. | |
5309 | */ | |
3f0effd1 | 5310 | #define MLXSW_REG_PSPA_ID 0x500D |
4ec14b76 IS |
5311 | #define MLXSW_REG_PSPA_LEN 0x8 |
5312 | ||
21978dcf | 5313 | MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); |
4ec14b76 IS |
5314 | |
5315 | /* reg_pspa_swid | |
5316 | * Switch partition ID. | |
5317 | * Access: RW | |
5318 | */ | |
5319 | MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); | |
5320 | ||
5321 | /* reg_pspa_local_port | |
5322 | * Local port number. | |
5323 | * Access: Index | |
5324 | */ | |
5325 | MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); | |
5326 | ||
5327 | /* reg_pspa_sub_port | |
5328 | * Virtual port within the local port. Set to 0 when virtual ports are | |
5329 | * disabled on the local port. | |
5330 | * Access: Index | |
5331 | */ | |
5332 | MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); | |
5333 | ||
5334 | static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) | |
5335 | { | |
5336 | MLXSW_REG_ZERO(pspa, payload); | |
5337 | mlxsw_reg_pspa_swid_set(payload, swid); | |
5338 | mlxsw_reg_pspa_local_port_set(payload, local_port); | |
5339 | mlxsw_reg_pspa_sub_port_set(payload, 0); | |
5340 | } | |
5341 | ||
a0c25387 JP |
5342 | /* PPLR - Port Physical Loopback Register |
5343 | * -------------------------------------- | |
5344 | * This register allows configuration of the port's loopback mode. | |
5345 | */ | |
5346 | #define MLXSW_REG_PPLR_ID 0x5018 | |
5347 | #define MLXSW_REG_PPLR_LEN 0x8 | |
5348 | ||
5349 | MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); | |
5350 | ||
5351 | /* reg_pplr_local_port | |
5352 | * Local port number. | |
5353 | * Access: Index | |
5354 | */ | |
5355 | MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); | |
5356 | ||
5357 | /* Phy local loopback. When set the port's egress traffic is looped back | |
5358 | * to the receiver and the port transmitter is disabled. | |
5359 | */ | |
5360 | #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) | |
5361 | ||
5362 | /* reg_pplr_lb_en | |
5363 | * Loopback enable. | |
5364 | * Access: RW | |
5365 | */ | |
5366 | MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); | |
5367 | ||
5368 | static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, | |
5369 | bool phy_local) | |
5370 | { | |
5371 | MLXSW_REG_ZERO(pplr, payload); | |
5372 | mlxsw_reg_pplr_local_port_set(payload, local_port); | |
5373 | mlxsw_reg_pplr_lb_en_set(payload, | |
5374 | phy_local ? | |
5375 | MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); | |
5376 | } | |
5377 | ||
a513b1a5 JP |
5378 | /* PMTM - Port Module Type Mapping Register |
5379 | * ---------------------------------------- | |
5380 | * The PMTM allows query or configuration of module types. | |
5381 | */ | |
5382 | #define MLXSW_REG_PMTM_ID 0x5067 | |
5383 | #define MLXSW_REG_PMTM_LEN 0x10 | |
5384 | ||
5385 | MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); | |
5386 | ||
5387 | /* reg_pmtm_module | |
5388 | * Module number. | |
5389 | * Access: Index | |
5390 | */ | |
5391 | MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); | |
5392 | ||
5393 | enum mlxsw_reg_pmtm_module_type { | |
5394 | /* Backplane with 4 lanes */ | |
5395 | MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, | |
5396 | /* QSFP */ | |
5397 | MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP, | |
5398 | /* SFP */ | |
5399 | MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP, | |
5400 | /* Backplane with single lane */ | |
5401 | MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, | |
5402 | /* Backplane with two lane */ | |
5403 | MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, | |
5404 | /* Chip2Chip */ | |
5405 | MLXSW_REG_PMTM_MODULE_TYPE_C2C = 10, | |
5406 | }; | |
5407 | ||
5408 | /* reg_pmtm_module_type | |
5409 | * Module type. | |
5410 | * Access: RW | |
5411 | */ | |
5412 | MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); | |
5413 | ||
5414 | static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) | |
5415 | { | |
5416 | MLXSW_REG_ZERO(pmtm, payload); | |
5417 | mlxsw_reg_pmtm_module_set(payload, module); | |
5418 | } | |
5419 | ||
5420 | static inline void | |
5421 | mlxsw_reg_pmtm_unpack(char *payload, | |
5422 | enum mlxsw_reg_pmtm_module_type *module_type) | |
5423 | { | |
5424 | *module_type = mlxsw_reg_pmtm_module_type_get(payload); | |
5425 | } | |
5426 | ||
4ec14b76 IS |
5427 | /* HTGT - Host Trap Group Table |
5428 | * ---------------------------- | |
5429 | * Configures the properties for forwarding to CPU. | |
5430 | */ | |
5431 | #define MLXSW_REG_HTGT_ID 0x7002 | |
e158e5ef | 5432 | #define MLXSW_REG_HTGT_LEN 0x20 |
4ec14b76 | 5433 | |
21978dcf | 5434 | MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); |
4ec14b76 IS |
5435 | |
5436 | /* reg_htgt_swid | |
5437 | * Switch partition ID. | |
5438 | * Access: Index | |
5439 | */ | |
5440 | MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); | |
5441 | ||
5442 | #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ | |
5443 | ||
5444 | /* reg_htgt_type | |
5445 | * CPU path type. | |
5446 | * Access: RW | |
5447 | */ | |
5448 | MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); | |
5449 | ||
801bd3de IS |
5450 | enum mlxsw_reg_htgt_trap_group { |
5451 | MLXSW_REG_HTGT_TRAP_GROUP_EMAD, | |
117b0dad NF |
5452 | MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, |
5453 | MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, | |
5454 | MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, | |
5455 | MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, | |
5456 | MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, | |
5457 | MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, | |
8d54814e | 5458 | MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, |
117b0dad | 5459 | MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, |
b48cfc80 YG |
5460 | MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, |
5461 | MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, | |
117b0dad | 5462 | MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, |
8d54814e | 5463 | MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, |
117b0dad NF |
5464 | MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, |
5465 | MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, | |
5466 | MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, | |
5467 | MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, | |
b48cfc80 | 5468 | MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, |
117b0dad | 5469 | MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, |
588823f9 | 5470 | MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, |
8d54814e | 5471 | MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, |
2f4f4494 | 5472 | MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, |
aed4b572 PM |
5473 | MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, |
5474 | MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, | |
9e6290c7 IS |
5475 | |
5476 | __MLXSW_REG_HTGT_TRAP_GROUP_MAX, | |
5477 | MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 | |
5478 | }; | |
5479 | ||
5480 | enum mlxsw_reg_htgt_discard_trap_group { | |
5481 | MLXSW_REG_HTGT_DISCARD_TRAP_GROUP_BASE = MLXSW_REG_HTGT_TRAP_GROUP_MAX, | |
5482 | MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, | |
dbc684f1 | 5483 | MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, |
801bd3de | 5484 | }; |
4ec14b76 IS |
5485 | |
5486 | /* reg_htgt_trap_group | |
5487 | * Trap group number. User defined number specifying which trap groups | |
5488 | * should be forwarded to the CPU. The mapping between trap IDs and trap | |
5489 | * groups is configured using HPKT register. | |
5490 | * Access: Index | |
5491 | */ | |
5492 | MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); | |
5493 | ||
5494 | enum { | |
5495 | MLXSW_REG_HTGT_POLICER_DISABLE, | |
5496 | MLXSW_REG_HTGT_POLICER_ENABLE, | |
5497 | }; | |
5498 | ||
5499 | /* reg_htgt_pide | |
5500 | * Enable policer ID specified using 'pid' field. | |
5501 | * Access: RW | |
5502 | */ | |
5503 | MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); | |
5504 | ||
579c82e4 NF |
5505 | #define MLXSW_REG_HTGT_INVALID_POLICER 0xff |
5506 | ||
4ec14b76 IS |
5507 | /* reg_htgt_pid |
5508 | * Policer ID for the trap group. | |
5509 | * Access: RW | |
5510 | */ | |
5511 | MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); | |
5512 | ||
5513 | #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 | |
5514 | ||
5515 | /* reg_htgt_mirror_action | |
5516 | * Mirror action to use. | |
5517 | * 0 - Trap to CPU. | |
5518 | * 1 - Trap to CPU and mirror to a mirroring agent. | |
5519 | * 2 - Mirror to a mirroring agent and do not trap to CPU. | |
5520 | * Access: RW | |
5521 | * | |
5522 | * Note: Mirroring to a mirroring agent is only supported in Spectrum. | |
5523 | */ | |
5524 | MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); | |
5525 | ||
5526 | /* reg_htgt_mirroring_agent | |
5527 | * Mirroring agent. | |
5528 | * Access: RW | |
5529 | */ | |
5530 | MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); | |
5531 | ||
579c82e4 NF |
5532 | #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 |
5533 | ||
4ec14b76 IS |
5534 | /* reg_htgt_priority |
5535 | * Trap group priority. | |
5536 | * In case a packet matches multiple classification rules, the packet will | |
5537 | * only be trapped once, based on the trap ID associated with the group (via | |
5538 | * register HPKT) with the highest priority. | |
5539 | * Supported values are 0-7, with 7 represnting the highest priority. | |
5540 | * Access: RW | |
5541 | * | |
5542 | * Note: In SwitchX-2 this field is ignored and the priority value is replaced | |
5543 | * by the 'trap_group' field. | |
5544 | */ | |
5545 | MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); | |
5546 | ||
579c82e4 NF |
5547 | #define MLXSW_REG_HTGT_DEFAULT_TC 7 |
5548 | ||
4ec14b76 IS |
5549 | /* reg_htgt_local_path_cpu_tclass |
5550 | * CPU ingress traffic class for the trap group. | |
5551 | * Access: RW | |
5552 | */ | |
5553 | MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); | |
5554 | ||
579c82e4 NF |
5555 | enum mlxsw_reg_htgt_local_path_rdq { |
5556 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, | |
5557 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, | |
5558 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, | |
5559 | MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, | |
5560 | }; | |
4ec14b76 IS |
5561 | /* reg_htgt_local_path_rdq |
5562 | * Receive descriptor queue (RDQ) to use for the trap group. | |
5563 | * Access: RW | |
5564 | */ | |
5565 | MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); | |
5566 | ||
579c82e4 NF |
5567 | static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, |
5568 | u8 priority, u8 tc) | |
4ec14b76 | 5569 | { |
4ec14b76 | 5570 | MLXSW_REG_ZERO(htgt, payload); |
579c82e4 NF |
5571 | |
5572 | if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { | |
5573 | mlxsw_reg_htgt_pide_set(payload, | |
5574 | MLXSW_REG_HTGT_POLICER_DISABLE); | |
5575 | } else { | |
5576 | mlxsw_reg_htgt_pide_set(payload, | |
5577 | MLXSW_REG_HTGT_POLICER_ENABLE); | |
5578 | mlxsw_reg_htgt_pid_set(payload, policer_id); | |
4ec14b76 | 5579 | } |
579c82e4 | 5580 | |
4ec14b76 | 5581 | mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); |
801bd3de | 5582 | mlxsw_reg_htgt_trap_group_set(payload, group); |
4ec14b76 IS |
5583 | mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); |
5584 | mlxsw_reg_htgt_mirroring_agent_set(payload, 0); | |
579c82e4 NF |
5585 | mlxsw_reg_htgt_priority_set(payload, priority); |
5586 | mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); | |
5587 | mlxsw_reg_htgt_local_path_rdq_set(payload, group); | |
4ec14b76 IS |
5588 | } |
5589 | ||
5590 | /* HPKT - Host Packet Trap | |
5591 | * ----------------------- | |
5592 | * Configures trap IDs inside trap groups. | |
5593 | */ | |
5594 | #define MLXSW_REG_HPKT_ID 0x7003 | |
5595 | #define MLXSW_REG_HPKT_LEN 0x10 | |
5596 | ||
21978dcf | 5597 | MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); |
4ec14b76 IS |
5598 | |
5599 | enum { | |
5600 | MLXSW_REG_HPKT_ACK_NOT_REQUIRED, | |
5601 | MLXSW_REG_HPKT_ACK_REQUIRED, | |
5602 | }; | |
5603 | ||
5604 | /* reg_hpkt_ack | |
5605 | * Require acknowledgements from the host for events. | |
5606 | * If set, then the device will wait for the event it sent to be acknowledged | |
5607 | * by the host. This option is only relevant for event trap IDs. | |
5608 | * Access: RW | |
5609 | * | |
5610 | * Note: Currently not supported by firmware. | |
5611 | */ | |
5612 | MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); | |
5613 | ||
5614 | enum mlxsw_reg_hpkt_action { | |
5615 | MLXSW_REG_HPKT_ACTION_FORWARD, | |
5616 | MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, | |
5617 | MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, | |
5618 | MLXSW_REG_HPKT_ACTION_DISCARD, | |
5619 | MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, | |
5620 | MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, | |
6a44bae3 IS |
5621 | MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, |
5622 | MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, | |
4ec14b76 IS |
5623 | }; |
5624 | ||
5625 | /* reg_hpkt_action | |
5626 | * Action to perform on packet when trapped. | |
5627 | * 0 - No action. Forward to CPU based on switching rules. | |
5628 | * 1 - Trap to CPU (CPU receives sole copy). | |
5629 | * 2 - Mirror to CPU (CPU receives a replica of the packet). | |
5630 | * 3 - Discard. | |
5631 | * 4 - Soft discard (allow other traps to act on the packet). | |
5632 | * 5 - Trap and soft discard (allow other traps to overwrite this trap). | |
6a44bae3 IS |
5633 | * 6 - Trap to CPU (CPU receives sole copy) and count it as error. |
5634 | * 15 - Restore the firmware's default action. | |
4ec14b76 IS |
5635 | * Access: RW |
5636 | * | |
5637 | * Note: Must be set to 0 (forward) for event trap IDs, as they are already | |
5638 | * addressed to the CPU. | |
5639 | */ | |
5640 | MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); | |
5641 | ||
5642 | /* reg_hpkt_trap_group | |
5643 | * Trap group to associate the trap with. | |
5644 | * Access: RW | |
5645 | */ | |
5646 | MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); | |
5647 | ||
5648 | /* reg_hpkt_trap_id | |
5649 | * Trap ID. | |
5650 | * Access: Index | |
5651 | * | |
5652 | * Note: A trap ID can only be associated with a single trap group. The device | |
5653 | * will associate the trap ID with the last trap group configured. | |
5654 | */ | |
5655 | MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); | |
5656 | ||
5657 | enum { | |
5658 | MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, | |
5659 | MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, | |
5660 | MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, | |
5661 | }; | |
5662 | ||
5663 | /* reg_hpkt_ctrl | |
5664 | * Configure dedicated buffer resources for control packets. | |
d570b7ee | 5665 | * Ignored by SwitchX-2. |
4ec14b76 IS |
5666 | * 0 - Keep factory defaults. |
5667 | * 1 - Do not use control buffer for this trap ID. | |
5668 | * 2 - Use control buffer for this trap ID. | |
5669 | * Access: RW | |
5670 | */ | |
5671 | MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); | |
5672 | ||
d570b7ee NF |
5673 | static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, |
5674 | enum mlxsw_reg_htgt_trap_group trap_group, | |
5675 | bool is_ctrl) | |
4ec14b76 IS |
5676 | { |
5677 | MLXSW_REG_ZERO(hpkt, payload); | |
5678 | mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); | |
5679 | mlxsw_reg_hpkt_action_set(payload, action); | |
5680 | mlxsw_reg_hpkt_trap_group_set(payload, trap_group); | |
5681 | mlxsw_reg_hpkt_trap_id_set(payload, trap_id); | |
d570b7ee NF |
5682 | mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? |
5683 | MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : | |
5684 | MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); | |
4ec14b76 IS |
5685 | } |
5686 | ||
69c407aa IS |
5687 | /* RGCR - Router General Configuration Register |
5688 | * -------------------------------------------- | |
5689 | * The register is used for setting up the router configuration. | |
5690 | */ | |
5691 | #define MLXSW_REG_RGCR_ID 0x8001 | |
5692 | #define MLXSW_REG_RGCR_LEN 0x28 | |
5693 | ||
21978dcf | 5694 | MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); |
69c407aa IS |
5695 | |
5696 | /* reg_rgcr_ipv4_en | |
5697 | * IPv4 router enable. | |
5698 | * Access: RW | |
5699 | */ | |
5700 | MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); | |
5701 | ||
5702 | /* reg_rgcr_ipv6_en | |
5703 | * IPv6 router enable. | |
5704 | * Access: RW | |
5705 | */ | |
5706 | MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); | |
5707 | ||
5708 | /* reg_rgcr_max_router_interfaces | |
5709 | * Defines the maximum number of active router interfaces for all virtual | |
5710 | * routers. | |
5711 | * Access: RW | |
5712 | */ | |
5713 | MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); | |
5714 | ||
5715 | /* reg_rgcr_usp | |
5716 | * Update switch priority and packet color. | |
5717 | * 0 - Preserve the value of Switch Priority and packet color. | |
5718 | * 1 - Recalculate the value of Switch Priority and packet color. | |
5719 | * Access: RW | |
5720 | * | |
5721 | * Note: Not supported by SwitchX and SwitchX-2. | |
5722 | */ | |
5723 | MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); | |
5724 | ||
5725 | /* reg_rgcr_pcp_rw | |
5726 | * Indicates how to handle the pcp_rewrite_en value: | |
5727 | * 0 - Preserve the value of pcp_rewrite_en. | |
5728 | * 2 - Disable PCP rewrite. | |
5729 | * 3 - Enable PCP rewrite. | |
5730 | * Access: RW | |
5731 | * | |
5732 | * Note: Not supported by SwitchX and SwitchX-2. | |
5733 | */ | |
5734 | MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); | |
5735 | ||
5736 | /* reg_rgcr_activity_dis | |
5737 | * Activity disable: | |
5738 | * 0 - Activity will be set when an entry is hit (default). | |
5739 | * 1 - Activity will not be set when an entry is hit. | |
5740 | * | |
5741 | * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry | |
5742 | * (RALUE). | |
5743 | * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host | |
5744 | * Entry (RAUHT). | |
5745 | * Bits 2:7 are reserved. | |
5746 | * Access: RW | |
5747 | * | |
5748 | * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. | |
5749 | */ | |
5750 | MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); | |
5751 | ||
e29237e7 AS |
5752 | static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, |
5753 | bool ipv6_en) | |
69c407aa IS |
5754 | { |
5755 | MLXSW_REG_ZERO(rgcr, payload); | |
5756 | mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); | |
e29237e7 | 5757 | mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); |
69c407aa IS |
5758 | } |
5759 | ||
3dc26689 IS |
5760 | /* RITR - Router Interface Table Register |
5761 | * -------------------------------------- | |
5762 | * The register is used to configure the router interface table. | |
5763 | */ | |
5764 | #define MLXSW_REG_RITR_ID 0x8002 | |
5765 | #define MLXSW_REG_RITR_LEN 0x40 | |
5766 | ||
21978dcf | 5767 | MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); |
3dc26689 IS |
5768 | |
5769 | /* reg_ritr_enable | |
5770 | * Enables routing on the router interface. | |
5771 | * Access: RW | |
5772 | */ | |
5773 | MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); | |
5774 | ||
5775 | /* reg_ritr_ipv4 | |
5776 | * IPv4 routing enable. Enables routing of IPv4 traffic on the router | |
5777 | * interface. | |
5778 | * Access: RW | |
5779 | */ | |
5780 | MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); | |
5781 | ||
5782 | /* reg_ritr_ipv6 | |
5783 | * IPv6 routing enable. Enables routing of IPv6 traffic on the router | |
5784 | * interface. | |
5785 | * Access: RW | |
5786 | */ | |
5787 | MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); | |
5788 | ||
4af5964e YG |
5789 | /* reg_ritr_ipv4_mc |
5790 | * IPv4 multicast routing enable. | |
5791 | * Access: RW | |
5792 | */ | |
5793 | MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); | |
5794 | ||
9a3d183a YM |
5795 | /* reg_ritr_ipv6_mc |
5796 | * IPv6 multicast routing enable. | |
5797 | * Access: RW | |
5798 | */ | |
5799 | MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); | |
5800 | ||
3dc26689 | 5801 | enum mlxsw_reg_ritr_if_type { |
78676ad4 | 5802 | /* VLAN interface. */ |
3dc26689 | 5803 | MLXSW_REG_RITR_VLAN_IF, |
78676ad4 | 5804 | /* FID interface. */ |
3dc26689 | 5805 | MLXSW_REG_RITR_FID_IF, |
78676ad4 | 5806 | /* Sub-port interface. */ |
3dc26689 | 5807 | MLXSW_REG_RITR_SP_IF, |
99ae8e3e PM |
5808 | /* Loopback Interface. */ |
5809 | MLXSW_REG_RITR_LOOPBACK_IF, | |
3dc26689 IS |
5810 | }; |
5811 | ||
5812 | /* reg_ritr_type | |
78676ad4 | 5813 | * Router interface type as per enum mlxsw_reg_ritr_if_type. |
3dc26689 IS |
5814 | * Access: RW |
5815 | */ | |
5816 | MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); | |
5817 | ||
5818 | enum { | |
5819 | MLXSW_REG_RITR_RIF_CREATE, | |
5820 | MLXSW_REG_RITR_RIF_DEL, | |
5821 | }; | |
5822 | ||
5823 | /* reg_ritr_op | |
5824 | * Opcode: | |
5825 | * 0 - Create or edit RIF. | |
5826 | * 1 - Delete RIF. | |
5827 | * Reserved for SwitchX-2. For Spectrum, editing of interface properties | |
5828 | * is not supported. An interface must be deleted and re-created in order | |
5829 | * to update properties. | |
5830 | * Access: WO | |
5831 | */ | |
5832 | MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); | |
5833 | ||
5834 | /* reg_ritr_rif | |
5835 | * Router interface index. A pointer to the Router Interface Table. | |
5836 | * Access: Index | |
5837 | */ | |
5838 | MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); | |
5839 | ||
5840 | /* reg_ritr_ipv4_fe | |
5841 | * IPv4 Forwarding Enable. | |
5842 | * Enables routing of IPv4 traffic on the router interface. When disabled, | |
5843 | * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. | |
5844 | * Not supported in SwitchX-2. | |
5845 | * Access: RW | |
5846 | */ | |
5847 | MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); | |
5848 | ||
5849 | /* reg_ritr_ipv6_fe | |
5850 | * IPv6 Forwarding Enable. | |
5851 | * Enables routing of IPv6 traffic on the router interface. When disabled, | |
5852 | * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. | |
5853 | * Not supported in SwitchX-2. | |
5854 | * Access: RW | |
5855 | */ | |
5856 | MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); | |
5857 | ||
4af5964e YG |
5858 | /* reg_ritr_ipv4_mc_fe |
5859 | * IPv4 Multicast Forwarding Enable. | |
5860 | * When disabled, forwarding is blocked but local traffic (traps and IP to me) | |
5861 | * will be enabled. | |
5862 | * Access: RW | |
5863 | */ | |
5864 | MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); | |
5865 | ||
9a3d183a YM |
5866 | /* reg_ritr_ipv6_mc_fe |
5867 | * IPv6 Multicast Forwarding Enable. | |
5868 | * When disabled, forwarding is blocked but local traffic (traps and IP to me) | |
5869 | * will be enabled. | |
5870 | * Access: RW | |
5871 | */ | |
5872 | MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); | |
5873 | ||
a94a614f IS |
5874 | /* reg_ritr_lb_en |
5875 | * Loop-back filter enable for unicast packets. | |
5876 | * If the flag is set then loop-back filter for unicast packets is | |
5877 | * implemented on the RIF. Multicast packets are always subject to | |
5878 | * loop-back filtering. | |
5879 | * Access: RW | |
5880 | */ | |
5881 | MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); | |
5882 | ||
3dc26689 IS |
5883 | /* reg_ritr_virtual_router |
5884 | * Virtual router ID associated with the router interface. | |
5885 | * Access: RW | |
5886 | */ | |
5887 | MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); | |
5888 | ||
5889 | /* reg_ritr_mtu | |
5890 | * Router interface MTU. | |
5891 | * Access: RW | |
5892 | */ | |
5893 | MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); | |
5894 | ||
5895 | /* reg_ritr_if_swid | |
5896 | * Switch partition ID. | |
5897 | * Access: RW | |
5898 | */ | |
5899 | MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); | |
5900 | ||
5901 | /* reg_ritr_if_mac | |
5902 | * Router interface MAC address. | |
5903 | * In Spectrum, all MAC addresses must have the same 38 MSBits. | |
5904 | * Access: RW | |
5905 | */ | |
5906 | MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); | |
5907 | ||
c3a49540 IS |
5908 | /* reg_ritr_if_vrrp_id_ipv6 |
5909 | * VRRP ID for IPv6 | |
5910 | * Note: Reserved for RIF types other than VLAN, FID and Sub-port. | |
5911 | * Access: RW | |
5912 | */ | |
5913 | MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); | |
5914 | ||
5915 | /* reg_ritr_if_vrrp_id_ipv4 | |
5916 | * VRRP ID for IPv4 | |
5917 | * Note: Reserved for RIF types other than VLAN, FID and Sub-port. | |
5918 | * Access: RW | |
5919 | */ | |
5920 | MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); | |
5921 | ||
3dc26689 IS |
5922 | /* VLAN Interface */ |
5923 | ||
5924 | /* reg_ritr_vlan_if_vid | |
5925 | * VLAN ID. | |
5926 | * Access: RW | |
5927 | */ | |
5928 | MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); | |
5929 | ||
5930 | /* FID Interface */ | |
5931 | ||
5932 | /* reg_ritr_fid_if_fid | |
5933 | * Filtering ID. Used to connect a bridge to the router. Only FIDs from | |
5934 | * the vFID range are supported. | |
5935 | * Access: RW | |
5936 | */ | |
5937 | MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); | |
5938 | ||
5939 | static inline void mlxsw_reg_ritr_fid_set(char *payload, | |
5940 | enum mlxsw_reg_ritr_if_type rif_type, | |
5941 | u16 fid) | |
5942 | { | |
5943 | if (rif_type == MLXSW_REG_RITR_FID_IF) | |
5944 | mlxsw_reg_ritr_fid_if_fid_set(payload, fid); | |
5945 | else | |
5946 | mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); | |
5947 | } | |
5948 | ||
5949 | /* Sub-port Interface */ | |
5950 | ||
5951 | /* reg_ritr_sp_if_lag | |
5952 | * LAG indication. When this bit is set the system_port field holds the | |
5953 | * LAG identifier. | |
5954 | * Access: RW | |
5955 | */ | |
5956 | MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); | |
5957 | ||
5958 | /* reg_ritr_sp_system_port | |
5959 | * Port unique indentifier. When lag bit is set, this field holds the | |
5960 | * lag_id in bits 0:9. | |
5961 | * Access: RW | |
5962 | */ | |
5963 | MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); | |
5964 | ||
5965 | /* reg_ritr_sp_if_vid | |
5966 | * VLAN ID. | |
5967 | * Access: RW | |
5968 | */ | |
5969 | MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); | |
5970 | ||
99ae8e3e PM |
5971 | /* Loopback Interface */ |
5972 | ||
5973 | enum mlxsw_reg_ritr_loopback_protocol { | |
5974 | /* IPinIP IPv4 underlay Unicast */ | |
5975 | MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, | |
5976 | /* IPinIP IPv6 underlay Unicast */ | |
5977 | MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, | |
afba3e10 ND |
5978 | /* IPinIP generic - used for Spectrum-2 underlay RIF */ |
5979 | MLXSW_REG_RITR_LOOPBACK_GENERIC, | |
99ae8e3e PM |
5980 | }; |
5981 | ||
5982 | /* reg_ritr_loopback_protocol | |
5983 | * Access: RW | |
5984 | */ | |
5985 | MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); | |
5986 | ||
5987 | enum mlxsw_reg_ritr_loopback_ipip_type { | |
5988 | /* Tunnel is IPinIP. */ | |
5989 | MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, | |
5990 | /* Tunnel is GRE, no key. */ | |
5991 | MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, | |
5992 | /* Tunnel is GRE, with a key. */ | |
5993 | MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, | |
5994 | }; | |
5995 | ||
5996 | /* reg_ritr_loopback_ipip_type | |
5997 | * Encapsulation type. | |
5998 | * Access: RW | |
5999 | */ | |
6000 | MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); | |
6001 | ||
6002 | enum mlxsw_reg_ritr_loopback_ipip_options { | |
6003 | /* The key is defined by gre_key. */ | |
6004 | MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, | |
6005 | }; | |
6006 | ||
6007 | /* reg_ritr_loopback_ipip_options | |
6008 | * Access: RW | |
6009 | */ | |
6010 | MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); | |
6011 | ||
6012 | /* reg_ritr_loopback_ipip_uvr | |
6013 | * Underlay Virtual Router ID. | |
6014 | * Range is 0..cap_max_virtual_routers-1. | |
6015 | * Reserved for Spectrum-2. | |
6016 | * Access: RW | |
6017 | */ | |
6018 | MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); | |
6019 | ||
afba3e10 ND |
6020 | /* reg_ritr_loopback_ipip_underlay_rif |
6021 | * Underlay ingress router interface. | |
6022 | * Reserved for Spectrum. | |
6023 | * Access: RW | |
6024 | */ | |
6025 | MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); | |
6026 | ||
99ae8e3e PM |
6027 | /* reg_ritr_loopback_ipip_usip* |
6028 | * Encapsulation Underlay source IP. | |
6029 | * Access: RW | |
6030 | */ | |
6031 | MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); | |
6032 | MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); | |
6033 | ||
6034 | /* reg_ritr_loopback_ipip_gre_key | |
6035 | * GRE Key. | |
6036 | * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. | |
6037 | * Access: RW | |
6038 | */ | |
6039 | MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); | |
6040 | ||
0f630fcb AS |
6041 | /* Shared between ingress/egress */ |
6042 | enum mlxsw_reg_ritr_counter_set_type { | |
6043 | /* No Count. */ | |
6044 | MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, | |
6045 | /* Basic. Used for router interfaces, counting the following: | |
6046 | * - Error and Discard counters. | |
6047 | * - Unicast, Multicast and Broadcast counters. Sharing the | |
6048 | * same set of counters for the different type of traffic | |
6049 | * (IPv4, IPv6 and mpls). | |
6050 | */ | |
6051 | MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, | |
6052 | }; | |
6053 | ||
6054 | /* reg_ritr_ingress_counter_index | |
6055 | * Counter Index for flow counter. | |
6056 | * Access: RW | |
6057 | */ | |
6058 | MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); | |
6059 | ||
6060 | /* reg_ritr_ingress_counter_set_type | |
6061 | * Igress Counter Set Type for router interface counter. | |
6062 | * Access: RW | |
6063 | */ | |
6064 | MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); | |
6065 | ||
6066 | /* reg_ritr_egress_counter_index | |
6067 | * Counter Index for flow counter. | |
6068 | * Access: RW | |
6069 | */ | |
6070 | MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); | |
6071 | ||
6072 | /* reg_ritr_egress_counter_set_type | |
6073 | * Egress Counter Set Type for router interface counter. | |
6074 | * Access: RW | |
6075 | */ | |
6076 | MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); | |
6077 | ||
6078 | static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, | |
6079 | bool enable, bool egress) | |
6080 | { | |
6081 | enum mlxsw_reg_ritr_counter_set_type set_type; | |
6082 | ||
6083 | if (enable) | |
6084 | set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; | |
6085 | else | |
6086 | set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; | |
6087 | mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); | |
6088 | ||
6089 | if (egress) | |
6090 | mlxsw_reg_ritr_egress_counter_index_set(payload, index); | |
6091 | else | |
6092 | mlxsw_reg_ritr_ingress_counter_index_set(payload, index); | |
6093 | } | |
6094 | ||
3dc26689 IS |
6095 | static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) |
6096 | { | |
6097 | MLXSW_REG_ZERO(ritr, payload); | |
6098 | mlxsw_reg_ritr_rif_set(payload, rif); | |
6099 | } | |
6100 | ||
6101 | static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, | |
6102 | u16 system_port, u16 vid) | |
6103 | { | |
6104 | mlxsw_reg_ritr_sp_if_lag_set(payload, lag); | |
6105 | mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); | |
6106 | mlxsw_reg_ritr_sp_if_vid_set(payload, vid); | |
6107 | } | |
6108 | ||
6109 | static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, | |
6110 | enum mlxsw_reg_ritr_if_type type, | |
9571e828 | 6111 | u16 rif, u16 vr_id, u16 mtu) |
3dc26689 IS |
6112 | { |
6113 | bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; | |
6114 | ||
6115 | MLXSW_REG_ZERO(ritr, payload); | |
6116 | mlxsw_reg_ritr_enable_set(payload, enable); | |
6117 | mlxsw_reg_ritr_ipv4_set(payload, 1); | |
e717e011 | 6118 | mlxsw_reg_ritr_ipv6_set(payload, 1); |
4af5964e | 6119 | mlxsw_reg_ritr_ipv4_mc_set(payload, 1); |
9a3d183a | 6120 | mlxsw_reg_ritr_ipv6_mc_set(payload, 1); |
3dc26689 IS |
6121 | mlxsw_reg_ritr_type_set(payload, type); |
6122 | mlxsw_reg_ritr_op_set(payload, op); | |
6123 | mlxsw_reg_ritr_rif_set(payload, rif); | |
6124 | mlxsw_reg_ritr_ipv4_fe_set(payload, 1); | |
e717e011 | 6125 | mlxsw_reg_ritr_ipv6_fe_set(payload, 1); |
4af5964e | 6126 | mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); |
9a3d183a | 6127 | mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); |
a94a614f | 6128 | mlxsw_reg_ritr_lb_en_set(payload, 1); |
6913229e | 6129 | mlxsw_reg_ritr_virtual_router_set(payload, vr_id); |
3dc26689 | 6130 | mlxsw_reg_ritr_mtu_set(payload, mtu); |
9571e828 PM |
6131 | } |
6132 | ||
6133 | static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) | |
6134 | { | |
3dc26689 IS |
6135 | mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); |
6136 | } | |
6137 | ||
99ae8e3e PM |
6138 | static inline void |
6139 | mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, | |
6140 | enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, | |
6141 | enum mlxsw_reg_ritr_loopback_ipip_options options, | |
afba3e10 | 6142 | u16 uvr_id, u16 underlay_rif, u32 gre_key) |
99ae8e3e PM |
6143 | { |
6144 | mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); | |
6145 | mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); | |
6146 | mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); | |
afba3e10 | 6147 | mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); |
99ae8e3e PM |
6148 | mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); |
6149 | } | |
6150 | ||
6151 | static inline void | |
6152 | mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, | |
6153 | enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, | |
6154 | enum mlxsw_reg_ritr_loopback_ipip_options options, | |
afba3e10 | 6155 | u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) |
99ae8e3e PM |
6156 | { |
6157 | mlxsw_reg_ritr_loopback_protocol_set(payload, | |
6158 | MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); | |
6159 | mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, | |
afba3e10 | 6160 | uvr_id, underlay_rif, gre_key); |
99ae8e3e PM |
6161 | mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); |
6162 | } | |
6163 | ||
46a7054e YG |
6164 | /* RTAR - Router TCAM Allocation Register |
6165 | * -------------------------------------- | |
6166 | * This register is used for allocation of regions in the TCAM table. | |
6167 | */ | |
6168 | #define MLXSW_REG_RTAR_ID 0x8004 | |
6169 | #define MLXSW_REG_RTAR_LEN 0x20 | |
6170 | ||
6171 | MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); | |
6172 | ||
6173 | enum mlxsw_reg_rtar_op { | |
6174 | MLXSW_REG_RTAR_OP_ALLOCATE, | |
6175 | MLXSW_REG_RTAR_OP_RESIZE, | |
6176 | MLXSW_REG_RTAR_OP_DEALLOCATE, | |
6177 | }; | |
6178 | ||
6179 | /* reg_rtar_op | |
6180 | * Access: WO | |
6181 | */ | |
6182 | MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); | |
6183 | ||
6184 | enum mlxsw_reg_rtar_key_type { | |
6185 | MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, | |
6186 | MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 | |
6187 | }; | |
6188 | ||
6189 | /* reg_rtar_key_type | |
6190 | * TCAM key type for the region. | |
6191 | * Access: WO | |
6192 | */ | |
6193 | MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); | |
6194 | ||
6195 | /* reg_rtar_region_size | |
6196 | * TCAM region size. When allocating/resizing this is the requested | |
6197 | * size, the response is the actual size. | |
6198 | * Note: Actual size may be larger than requested. | |
6199 | * Reserved for op = Deallocate | |
6200 | * Access: WO | |
6201 | */ | |
6202 | MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); | |
6203 | ||
6204 | static inline void mlxsw_reg_rtar_pack(char *payload, | |
6205 | enum mlxsw_reg_rtar_op op, | |
6206 | enum mlxsw_reg_rtar_key_type key_type, | |
6207 | u16 region_size) | |
6208 | { | |
6209 | MLXSW_REG_ZERO(rtar, payload); | |
6210 | mlxsw_reg_rtar_op_set(payload, op); | |
6211 | mlxsw_reg_rtar_key_type_set(payload, key_type); | |
6212 | mlxsw_reg_rtar_region_size_set(payload, region_size); | |
6213 | } | |
6214 | ||
089f9816 YG |
6215 | /* RATR - Router Adjacency Table Register |
6216 | * -------------------------------------- | |
6217 | * The RATR register is used to configure the Router Adjacency (next-hop) | |
6218 | * Table. | |
6219 | */ | |
6220 | #define MLXSW_REG_RATR_ID 0x8008 | |
6221 | #define MLXSW_REG_RATR_LEN 0x2C | |
6222 | ||
21978dcf | 6223 | MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); |
089f9816 YG |
6224 | |
6225 | enum mlxsw_reg_ratr_op { | |
6226 | /* Read */ | |
6227 | MLXSW_REG_RATR_OP_QUERY_READ = 0, | |
6228 | /* Read and clear activity */ | |
6229 | MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, | |
6230 | /* Write Adjacency entry */ | |
6231 | MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, | |
6232 | /* Write Adjacency entry only if the activity is cleared. | |
6233 | * The write may not succeed if the activity is set. There is not | |
6234 | * direct feedback if the write has succeeded or not, however | |
6235 | * the get will reveal the actual entry (SW can compare the get | |
6236 | * response to the set command). | |
6237 | */ | |
6238 | MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, | |
6239 | }; | |
6240 | ||
6241 | /* reg_ratr_op | |
6242 | * Note that Write operation may also be used for updating | |
6243 | * counter_set_type and counter_index. In this case all other | |
6244 | * fields must not be updated. | |
6245 | * Access: OP | |
6246 | */ | |
6247 | MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); | |
6248 | ||
6249 | /* reg_ratr_v | |
6250 | * Valid bit. Indicates if the adjacency entry is valid. | |
6251 | * Note: the device may need some time before reusing an invalidated | |
6252 | * entry. During this time the entry can not be reused. It is | |
6253 | * recommended to use another entry before reusing an invalidated | |
6254 | * entry (e.g. software can put it at the end of the list for | |
6255 | * reusing). Trying to access an invalidated entry not yet cleared | |
6256 | * by the device results with failure indicating "Try Again" status. | |
6257 | * When valid is '0' then egress_router_interface,trap_action, | |
6258 | * adjacency_parameters and counters are reserved | |
6259 | * Access: RW | |
6260 | */ | |
6261 | MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); | |
6262 | ||
6263 | /* reg_ratr_a | |
6264 | * Activity. Set for new entries. Set if a packet lookup has hit on | |
6265 | * the specific entry. To clear the a bit, use "clear activity". | |
6266 | * Access: RO | |
6267 | */ | |
6268 | MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); | |
6269 | ||
7c819de4 PM |
6270 | enum mlxsw_reg_ratr_type { |
6271 | /* Ethernet */ | |
6272 | MLXSW_REG_RATR_TYPE_ETHERNET, | |
6273 | /* IPoIB Unicast without GRH. | |
6274 | * Reserved for Spectrum. | |
6275 | */ | |
6276 | MLXSW_REG_RATR_TYPE_IPOIB_UC, | |
6277 | /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast | |
6278 | * adjacency). | |
6279 | * Reserved for Spectrum. | |
6280 | */ | |
6281 | MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, | |
6282 | /* IPoIB Multicast. | |
6283 | * Reserved for Spectrum. | |
6284 | */ | |
6285 | MLXSW_REG_RATR_TYPE_IPOIB_MC, | |
6286 | /* MPLS. | |
6287 | * Reserved for SwitchX/-2. | |
6288 | */ | |
6289 | MLXSW_REG_RATR_TYPE_MPLS, | |
6290 | /* IPinIP Encap. | |
6291 | * Reserved for SwitchX/-2. | |
6292 | */ | |
6293 | MLXSW_REG_RATR_TYPE_IPIP, | |
6294 | }; | |
6295 | ||
6296 | /* reg_ratr_type | |
6297 | * Adjacency entry type. | |
6298 | * Access: RW | |
6299 | */ | |
6300 | MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); | |
6301 | ||
089f9816 YG |
6302 | /* reg_ratr_adjacency_index_low |
6303 | * Bits 15:0 of index into the adjacency table. | |
6304 | * For SwitchX and SwitchX-2, the adjacency table is linear and | |
6305 | * used for adjacency entries only. | |
6306 | * For Spectrum, the index is to the KVD linear. | |
6307 | * Access: Index | |
6308 | */ | |
6309 | MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); | |
6310 | ||
6311 | /* reg_ratr_egress_router_interface | |
6312 | * Range is 0 .. cap_max_router_interfaces - 1 | |
6313 | * Access: RW | |
6314 | */ | |
6315 | MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); | |
6316 | ||
6317 | enum mlxsw_reg_ratr_trap_action { | |
6318 | MLXSW_REG_RATR_TRAP_ACTION_NOP, | |
6319 | MLXSW_REG_RATR_TRAP_ACTION_TRAP, | |
6320 | MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, | |
6321 | MLXSW_REG_RATR_TRAP_ACTION_MIRROR, | |
6322 | MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, | |
6323 | }; | |
6324 | ||
6325 | /* reg_ratr_trap_action | |
6326 | * see mlxsw_reg_ratr_trap_action | |
6327 | * Access: RW | |
6328 | */ | |
6329 | MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); | |
6330 | ||
089f9816 YG |
6331 | /* reg_ratr_adjacency_index_high |
6332 | * Bits 23:16 of the adjacency_index. | |
6333 | * Access: Index | |
6334 | */ | |
6335 | MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); | |
6336 | ||
6c4153b1 PM |
6337 | enum mlxsw_reg_ratr_trap_id { |
6338 | MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, | |
6339 | MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, | |
6340 | }; | |
6341 | ||
089f9816 YG |
6342 | /* reg_ratr_trap_id |
6343 | * Trap ID to be reported to CPU. | |
6344 | * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. | |
6345 | * For trap_action of NOP, MIRROR and DISCARD_ERROR | |
6346 | * Access: RW | |
6347 | */ | |
6348 | MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); | |
6349 | ||
6350 | /* reg_ratr_eth_destination_mac | |
6351 | * MAC address of the destination next-hop. | |
6352 | * Access: RW | |
6353 | */ | |
6354 | MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); | |
6355 | ||
7c819de4 PM |
6356 | enum mlxsw_reg_ratr_ipip_type { |
6357 | /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ | |
6358 | MLXSW_REG_RATR_IPIP_TYPE_IPV4, | |
6359 | /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ | |
6360 | MLXSW_REG_RATR_IPIP_TYPE_IPV6, | |
6361 | }; | |
6362 | ||
6363 | /* reg_ratr_ipip_type | |
6364 | * Underlay destination ip type. | |
6365 | * Note: the type field must match the protocol of the router interface. | |
6366 | * Access: RW | |
6367 | */ | |
6368 | MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); | |
6369 | ||
6370 | /* reg_ratr_ipip_ipv4_udip | |
6371 | * Underlay ipv4 dip. | |
6372 | * Reserved when ipip_type is IPv6. | |
6373 | * Access: RW | |
6374 | */ | |
6375 | MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); | |
6376 | ||
6377 | /* reg_ratr_ipip_ipv6_ptr | |
6378 | * Pointer to IPv6 underlay destination ip address. | |
6379 | * For Spectrum: Pointer to KVD linear space. | |
6380 | * Access: RW | |
6381 | */ | |
6382 | MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); | |
6383 | ||
f4de25fb AS |
6384 | enum mlxsw_reg_flow_counter_set_type { |
6385 | /* No count */ | |
6386 | MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, | |
6387 | /* Count packets and bytes */ | |
6388 | MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, | |
6389 | /* Count only packets */ | |
6390 | MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, | |
6391 | }; | |
6392 | ||
6393 | /* reg_ratr_counter_set_type | |
6394 | * Counter set type for flow counters | |
6395 | * Access: RW | |
6396 | */ | |
6397 | MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); | |
6398 | ||
6399 | /* reg_ratr_counter_index | |
6400 | * Counter index for flow counters | |
6401 | * Access: RW | |
6402 | */ | |
6403 | MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); | |
6404 | ||
089f9816 YG |
6405 | static inline void |
6406 | mlxsw_reg_ratr_pack(char *payload, | |
6407 | enum mlxsw_reg_ratr_op op, bool valid, | |
89e41982 | 6408 | enum mlxsw_reg_ratr_type type, |
089f9816 YG |
6409 | u32 adjacency_index, u16 egress_rif) |
6410 | { | |
6411 | MLXSW_REG_ZERO(ratr, payload); | |
6412 | mlxsw_reg_ratr_op_set(payload, op); | |
6413 | mlxsw_reg_ratr_v_set(payload, valid); | |
89e41982 | 6414 | mlxsw_reg_ratr_type_set(payload, type); |
089f9816 YG |
6415 | mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); |
6416 | mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); | |
6417 | mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); | |
6418 | } | |
6419 | ||
6420 | static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, | |
6421 | const char *dest_mac) | |
6422 | { | |
6423 | mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); | |
6424 | } | |
6425 | ||
7c819de4 PM |
6426 | static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) |
6427 | { | |
6428 | mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); | |
6429 | mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); | |
6430 | } | |
6431 | ||
f4de25fb AS |
6432 | static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, |
6433 | bool counter_enable) | |
6434 | { | |
6435 | enum mlxsw_reg_flow_counter_set_type set_type; | |
6436 | ||
6437 | if (counter_enable) | |
6438 | set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; | |
6439 | else | |
6440 | set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; | |
6441 | ||
6442 | mlxsw_reg_ratr_counter_index_set(payload, counter_index); | |
6443 | mlxsw_reg_ratr_counter_set_type_set(payload, set_type); | |
6444 | } | |
6445 | ||
ddb362ce YM |
6446 | /* RDPM - Router DSCP to Priority Mapping |
6447 | * -------------------------------------- | |
6448 | * Controls the mapping from DSCP field to switch priority on routed packets | |
6449 | */ | |
6450 | #define MLXSW_REG_RDPM_ID 0x8009 | |
6451 | #define MLXSW_REG_RDPM_BASE_LEN 0x00 | |
6452 | #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 | |
6453 | #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 | |
6454 | #define MLXSW_REG_RDPM_LEN 0x40 | |
6455 | #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ | |
6456 | MLXSW_REG_RDPM_LEN - \ | |
6457 | MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) | |
6458 | ||
6459 | MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); | |
6460 | ||
6461 | /* reg_dscp_entry_e | |
6462 | * Enable update of the specific entry | |
6463 | * Access: Index | |
6464 | */ | |
6465 | MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, | |
6466 | -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); | |
6467 | ||
6468 | /* reg_dscp_entry_prio | |
6469 | * Switch Priority | |
6470 | * Access: RW | |
6471 | */ | |
6472 | MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, | |
6473 | -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); | |
6474 | ||
6475 | static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, | |
6476 | u8 prio) | |
6477 | { | |
6478 | mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); | |
6479 | mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); | |
6480 | } | |
6481 | ||
ba73e97a AS |
6482 | /* RICNT - Router Interface Counter Register |
6483 | * ----------------------------------------- | |
6484 | * The RICNT register retrieves per port performance counters | |
6485 | */ | |
6486 | #define MLXSW_REG_RICNT_ID 0x800B | |
6487 | #define MLXSW_REG_RICNT_LEN 0x100 | |
6488 | ||
6489 | MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); | |
6490 | ||
6491 | /* reg_ricnt_counter_index | |
6492 | * Counter index | |
6493 | * Access: RW | |
6494 | */ | |
6495 | MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); | |
6496 | ||
6497 | enum mlxsw_reg_ricnt_counter_set_type { | |
6498 | /* No Count. */ | |
6499 | MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, | |
6500 | /* Basic. Used for router interfaces, counting the following: | |
6501 | * - Error and Discard counters. | |
6502 | * - Unicast, Multicast and Broadcast counters. Sharing the | |
6503 | * same set of counters for the different type of traffic | |
6504 | * (IPv4, IPv6 and mpls). | |
6505 | */ | |
6506 | MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, | |
6507 | }; | |
6508 | ||
6509 | /* reg_ricnt_counter_set_type | |
6510 | * Counter Set Type for router interface counter | |
6511 | * Access: RW | |
6512 | */ | |
6513 | MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); | |
6514 | ||
6515 | enum mlxsw_reg_ricnt_opcode { | |
6516 | /* Nop. Supported only for read access*/ | |
6517 | MLXSW_REG_RICNT_OPCODE_NOP = 0x00, | |
6518 | /* Clear. Setting the clr bit will reset the counter value for | |
6519 | * all counters of the specified Router Interface. | |
6520 | */ | |
6521 | MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, | |
6522 | }; | |
6523 | ||
6524 | /* reg_ricnt_opcode | |
6525 | * Opcode | |
6526 | * Access: RW | |
6527 | */ | |
6528 | MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); | |
6529 | ||
6530 | /* reg_ricnt_good_unicast_packets | |
6531 | * good unicast packets. | |
6532 | * Access: RW | |
6533 | */ | |
6534 | MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); | |
6535 | ||
6536 | /* reg_ricnt_good_multicast_packets | |
6537 | * good multicast packets. | |
6538 | * Access: RW | |
6539 | */ | |
6540 | MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); | |
6541 | ||
6542 | /* reg_ricnt_good_broadcast_packets | |
6543 | * good broadcast packets | |
6544 | * Access: RW | |
6545 | */ | |
6546 | MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); | |
6547 | ||
6548 | /* reg_ricnt_good_unicast_bytes | |
6549 | * A count of L3 data and padding octets not including L2 headers | |
6550 | * for good unicast frames. | |
6551 | * Access: RW | |
6552 | */ | |
6553 | MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); | |
6554 | ||
6555 | /* reg_ricnt_good_multicast_bytes | |
6556 | * A count of L3 data and padding octets not including L2 headers | |
6557 | * for good multicast frames. | |
6558 | * Access: RW | |
6559 | */ | |
6560 | MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); | |
6561 | ||
6562 | /* reg_ritr_good_broadcast_bytes | |
6563 | * A count of L3 data and padding octets not including L2 headers | |
6564 | * for good broadcast frames. | |
6565 | * Access: RW | |
6566 | */ | |
6567 | MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); | |
6568 | ||
6569 | /* reg_ricnt_error_packets | |
6570 | * A count of errored frames that do not pass the router checks. | |
6571 | * Access: RW | |
6572 | */ | |
6573 | MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); | |
6574 | ||
6575 | /* reg_ricnt_discrad_packets | |
6576 | * A count of non-errored frames that do not pass the router checks. | |
6577 | * Access: RW | |
6578 | */ | |
6579 | MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); | |
6580 | ||
6581 | /* reg_ricnt_error_bytes | |
6582 | * A count of L3 data and padding octets not including L2 headers | |
6583 | * for errored frames. | |
6584 | * Access: RW | |
6585 | */ | |
6586 | MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); | |
6587 | ||
6588 | /* reg_ricnt_discard_bytes | |
6589 | * A count of L3 data and padding octets not including L2 headers | |
6590 | * for non-errored frames that do not pass the router checks. | |
6591 | * Access: RW | |
6592 | */ | |
6593 | MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); | |
6594 | ||
6595 | static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, | |
6596 | enum mlxsw_reg_ricnt_opcode op) | |
6597 | { | |
6598 | MLXSW_REG_ZERO(ricnt, payload); | |
6599 | mlxsw_reg_ricnt_op_set(payload, op); | |
6600 | mlxsw_reg_ricnt_counter_index_set(payload, index); | |
6601 | mlxsw_reg_ricnt_counter_set_type_set(payload, | |
6602 | MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); | |
6603 | } | |
6604 | ||
4fc92846 YG |
6605 | /* RRCR - Router Rules Copy Register Layout |
6606 | * ---------------------------------------- | |
6607 | * This register is used for moving and copying route entry rules. | |
6608 | */ | |
6609 | #define MLXSW_REG_RRCR_ID 0x800F | |
6610 | #define MLXSW_REG_RRCR_LEN 0x24 | |
6611 | ||
6612 | MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); | |
6613 | ||
6614 | enum mlxsw_reg_rrcr_op { | |
6615 | /* Move rules */ | |
6616 | MLXSW_REG_RRCR_OP_MOVE, | |
6617 | /* Copy rules */ | |
6618 | MLXSW_REG_RRCR_OP_COPY, | |
6619 | }; | |
6620 | ||
6621 | /* reg_rrcr_op | |
6622 | * Access: WO | |
6623 | */ | |
6624 | MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); | |
6625 | ||
6626 | /* reg_rrcr_offset | |
6627 | * Offset within the region from which to copy/move. | |
6628 | * Access: Index | |
6629 | */ | |
6630 | MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); | |
6631 | ||
6632 | /* reg_rrcr_size | |
6633 | * The number of rules to copy/move. | |
6634 | * Access: WO | |
6635 | */ | |
6636 | MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); | |
6637 | ||
6638 | /* reg_rrcr_table_id | |
6639 | * Identifier of the table on which to perform the operation. Encoding is the | |
6640 | * same as in RTAR.key_type | |
6641 | * Access: Index | |
6642 | */ | |
6643 | MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); | |
6644 | ||
6645 | /* reg_rrcr_dest_offset | |
6646 | * Offset within the region to which to copy/move | |
6647 | * Access: Index | |
6648 | */ | |
6649 | MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); | |
6650 | ||
6651 | static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, | |
6652 | u16 offset, u16 size, | |
6653 | enum mlxsw_reg_rtar_key_type table_id, | |
6654 | u16 dest_offset) | |
6655 | { | |
6656 | MLXSW_REG_ZERO(rrcr, payload); | |
6657 | mlxsw_reg_rrcr_op_set(payload, op); | |
6658 | mlxsw_reg_rrcr_offset_set(payload, offset); | |
6659 | mlxsw_reg_rrcr_size_set(payload, size); | |
6660 | mlxsw_reg_rrcr_table_id_set(payload, table_id); | |
6661 | mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); | |
6662 | } | |
6663 | ||
6f9fc3ce JP |
6664 | /* RALTA - Router Algorithmic LPM Tree Allocation Register |
6665 | * ------------------------------------------------------- | |
6666 | * RALTA is used to allocate the LPM trees of the SHSPM method. | |
6667 | */ | |
6668 | #define MLXSW_REG_RALTA_ID 0x8010 | |
6669 | #define MLXSW_REG_RALTA_LEN 0x04 | |
6670 | ||
21978dcf | 6671 | MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); |
6f9fc3ce JP |
6672 | |
6673 | /* reg_ralta_op | |
6674 | * opcode (valid for Write, must be 0 on Read) | |
6675 | * 0 - allocate a tree | |
6676 | * 1 - deallocate a tree | |
6677 | * Access: OP | |
6678 | */ | |
6679 | MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); | |
6680 | ||
6681 | enum mlxsw_reg_ralxx_protocol { | |
6682 | MLXSW_REG_RALXX_PROTOCOL_IPV4, | |
6683 | MLXSW_REG_RALXX_PROTOCOL_IPV6, | |
6684 | }; | |
6685 | ||
6686 | /* reg_ralta_protocol | |
6687 | * Protocol. | |
6688 | * Deallocation opcode: Reserved. | |
6689 | * Access: RW | |
6690 | */ | |
6691 | MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); | |
6692 | ||
6693 | /* reg_ralta_tree_id | |
6694 | * An identifier (numbered from 1..cap_shspm_max_trees-1) representing | |
6695 | * the tree identifier (managed by software). | |
6696 | * Note that tree_id 0 is allocated for a default-route tree. | |
6697 | * Access: Index | |
6698 | */ | |
6699 | MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); | |
6700 | ||
6701 | static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, | |
6702 | enum mlxsw_reg_ralxx_protocol protocol, | |
6703 | u8 tree_id) | |
6704 | { | |
6705 | MLXSW_REG_ZERO(ralta, payload); | |
6706 | mlxsw_reg_ralta_op_set(payload, !alloc); | |
6707 | mlxsw_reg_ralta_protocol_set(payload, protocol); | |
6708 | mlxsw_reg_ralta_tree_id_set(payload, tree_id); | |
6709 | } | |
6710 | ||
a9823359 JP |
6711 | /* RALST - Router Algorithmic LPM Structure Tree Register |
6712 | * ------------------------------------------------------ | |
6713 | * RALST is used to set and query the structure of an LPM tree. | |
6714 | * The structure of the tree must be sorted as a sorted binary tree, while | |
6715 | * each node is a bin that is tagged as the length of the prefixes the lookup | |
6716 | * will refer to. Therefore, bin X refers to a set of entries with prefixes | |
6717 | * of X bits to match with the destination address. The bin 0 indicates | |
6718 | * the default action, when there is no match of any prefix. | |
6719 | */ | |
6720 | #define MLXSW_REG_RALST_ID 0x8011 | |
6721 | #define MLXSW_REG_RALST_LEN 0x104 | |
6722 | ||
21978dcf | 6723 | MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); |
a9823359 JP |
6724 | |
6725 | /* reg_ralst_root_bin | |
6726 | * The bin number of the root bin. | |
6727 | * 0<root_bin=<(length of IP address) | |
6728 | * For a default-route tree configure 0xff | |
6729 | * Access: RW | |
6730 | */ | |
6731 | MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); | |
6732 | ||
6733 | /* reg_ralst_tree_id | |
6734 | * Tree identifier numbered from 1..(cap_shspm_max_trees-1). | |
6735 | * Access: Index | |
6736 | */ | |
6737 | MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); | |
6738 | ||
6739 | #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff | |
6740 | #define MLXSW_REG_RALST_BIN_OFFSET 0x04 | |
6741 | #define MLXSW_REG_RALST_BIN_COUNT 128 | |
6742 | ||
6743 | /* reg_ralst_left_child_bin | |
6744 | * Holding the children of the bin according to the stored tree's structure. | |
6745 | * For trees composed of less than 4 blocks, the bins in excess are reserved. | |
6746 | * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff | |
6747 | * Access: RW | |
6748 | */ | |
6749 | MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); | |
6750 | ||
6751 | /* reg_ralst_right_child_bin | |
6752 | * Holding the children of the bin according to the stored tree's structure. | |
6753 | * For trees composed of less than 4 blocks, the bins in excess are reserved. | |
6754 | * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff | |
6755 | * Access: RW | |
6756 | */ | |
6757 | MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, | |
6758 | false); | |
6759 | ||
6760 | static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) | |
6761 | { | |
6762 | MLXSW_REG_ZERO(ralst, payload); | |
6763 | ||
6764 | /* Initialize all bins to have no left or right child */ | |
6765 | memset(payload + MLXSW_REG_RALST_BIN_OFFSET, | |
6766 | MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); | |
6767 | ||
6768 | mlxsw_reg_ralst_root_bin_set(payload, root_bin); | |
6769 | mlxsw_reg_ralst_tree_id_set(payload, tree_id); | |
6770 | } | |
6771 | ||
6772 | static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, | |
6773 | u8 left_child_bin, | |
6774 | u8 right_child_bin) | |
6775 | { | |
6776 | int bin_index = bin_number - 1; | |
6777 | ||
6778 | mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); | |
6779 | mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, | |
6780 | right_child_bin); | |
6781 | } | |
6782 | ||
20ae4053 JP |
6783 | /* RALTB - Router Algorithmic LPM Tree Binding Register |
6784 | * ---------------------------------------------------- | |
6785 | * RALTB is used to bind virtual router and protocol to an allocated LPM tree. | |
6786 | */ | |
6787 | #define MLXSW_REG_RALTB_ID 0x8012 | |
6788 | #define MLXSW_REG_RALTB_LEN 0x04 | |
6789 | ||
21978dcf | 6790 | MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); |
20ae4053 JP |
6791 | |
6792 | /* reg_raltb_virtual_router | |
6793 | * Virtual Router ID | |
6794 | * Range is 0..cap_max_virtual_routers-1 | |
6795 | * Access: Index | |
6796 | */ | |
6797 | MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); | |
6798 | ||
6799 | /* reg_raltb_protocol | |
6800 | * Protocol. | |
6801 | * Access: Index | |
6802 | */ | |
6803 | MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); | |
6804 | ||
6805 | /* reg_raltb_tree_id | |
6806 | * Tree to be used for the {virtual_router, protocol} | |
6807 | * Tree identifier numbered from 1..(cap_shspm_max_trees-1). | |
6808 | * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. | |
6809 | * Access: RW | |
6810 | */ | |
6811 | MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); | |
6812 | ||
6813 | static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, | |
6814 | enum mlxsw_reg_ralxx_protocol protocol, | |
6815 | u8 tree_id) | |
6816 | { | |
6817 | MLXSW_REG_ZERO(raltb, payload); | |
6818 | mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); | |
6819 | mlxsw_reg_raltb_protocol_set(payload, protocol); | |
6820 | mlxsw_reg_raltb_tree_id_set(payload, tree_id); | |
6821 | } | |
6822 | ||
d5a1c749 JP |
6823 | /* RALUE - Router Algorithmic LPM Unicast Entry Register |
6824 | * ----------------------------------------------------- | |
6825 | * RALUE is used to configure and query LPM entries that serve | |
6826 | * the Unicast protocols. | |
6827 | */ | |
6828 | #define MLXSW_REG_RALUE_ID 0x8013 | |
6829 | #define MLXSW_REG_RALUE_LEN 0x38 | |
6830 | ||
21978dcf | 6831 | MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); |
d5a1c749 JP |
6832 | |
6833 | /* reg_ralue_protocol | |
6834 | * Protocol. | |
6835 | * Access: Index | |
6836 | */ | |
6837 | MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); | |
6838 | ||
6839 | enum mlxsw_reg_ralue_op { | |
6840 | /* Read operation. If entry doesn't exist, the operation fails. */ | |
6841 | MLXSW_REG_RALUE_OP_QUERY_READ = 0, | |
6842 | /* Clear on read operation. Used to read entry and | |
6843 | * clear Activity bit. | |
6844 | */ | |
6845 | MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, | |
6846 | /* Write operation. Used to write a new entry to the table. All RW | |
6847 | * fields are written for new entry. Activity bit is set | |
6848 | * for new entries. | |
6849 | */ | |
6850 | MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, | |
6851 | /* Update operation. Used to update an existing route entry and | |
6852 | * only update the RW fields that are detailed in the field | |
6853 | * op_u_mask. If entry doesn't exist, the operation fails. | |
6854 | */ | |
6855 | MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, | |
6856 | /* Clear activity. The Activity bit (the field a) is cleared | |
6857 | * for the entry. | |
6858 | */ | |
6859 | MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, | |
6860 | /* Delete operation. Used to delete an existing entry. If entry | |
6861 | * doesn't exist, the operation fails. | |
6862 | */ | |
6863 | MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, | |
6864 | }; | |
6865 | ||
6866 | /* reg_ralue_op | |
6867 | * Operation. | |
6868 | * Access: OP | |
6869 | */ | |
6870 | MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); | |
6871 | ||
6872 | /* reg_ralue_a | |
6873 | * Activity. Set for new entries. Set if a packet lookup has hit on the | |
6874 | * specific entry, only if the entry is a route. To clear the a bit, use | |
6875 | * "clear activity" op. | |
6876 | * Enabled by activity_dis in RGCR | |
6877 | * Access: RO | |
6878 | */ | |
6879 | MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); | |
6880 | ||
6881 | /* reg_ralue_virtual_router | |
6882 | * Virtual Router ID | |
6883 | * Range is 0..cap_max_virtual_routers-1 | |
6884 | * Access: Index | |
6885 | */ | |
6886 | MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); | |
6887 | ||
6888 | #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) | |
6889 | #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) | |
6890 | #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) | |
6891 | ||
6892 | /* reg_ralue_op_u_mask | |
6893 | * opcode update mask. | |
6894 | * On read operation, this field is reserved. | |
6895 | * This field is valid for update opcode, otherwise - reserved. | |
6896 | * This field is a bitmask of the fields that should be updated. | |
6897 | * Access: WO | |
6898 | */ | |
6899 | MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); | |
6900 | ||
6901 | /* reg_ralue_prefix_len | |
6902 | * Number of bits in the prefix of the LPM route. | |
6903 | * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes | |
6904 | * two entries in the physical HW table. | |
6905 | * Access: Index | |
6906 | */ | |
6907 | MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); | |
6908 | ||
6909 | /* reg_ralue_dip* | |
6910 | * The prefix of the route or of the marker that the object of the LPM | |
6911 | * is compared with. The most significant bits of the dip are the prefix. | |
806a1c1a | 6912 | * The least significant bits must be '0' if the prefix_len is smaller |
d5a1c749 JP |
6913 | * than 128 for IPv6 or smaller than 32 for IPv4. |
6914 | * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. | |
6915 | * Access: Index | |
6916 | */ | |
6917 | MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); | |
62547f40 | 6918 | MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); |
d5a1c749 JP |
6919 | |
6920 | enum mlxsw_reg_ralue_entry_type { | |
6921 | MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, | |
6922 | MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, | |
6923 | MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, | |
6924 | }; | |
6925 | ||
6926 | /* reg_ralue_entry_type | |
6927 | * Entry type. | |
6928 | * Note - for Marker entries, the action_type and action fields are reserved. | |
6929 | * Access: RW | |
6930 | */ | |
6931 | MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); | |
6932 | ||
6933 | /* reg_ralue_bmp_len | |
6934 | * The best match prefix length in the case that there is no match for | |
6935 | * longer prefixes. | |
6936 | * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len | |
6937 | * Note for any update operation with entry_type modification this | |
6938 | * field must be set. | |
6939 | * Access: RW | |
6940 | */ | |
6941 | MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); | |
6942 | ||
6943 | enum mlxsw_reg_ralue_action_type { | |
6944 | MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, | |
6945 | MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, | |
6946 | MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, | |
6947 | }; | |
6948 | ||
6949 | /* reg_ralue_action_type | |
6950 | * Action Type | |
6951 | * Indicates how the IP address is connected. | |
6952 | * It can be connected to a local subnet through local_erif or can be | |
6953 | * on a remote subnet connected through a next-hop router, | |
6954 | * or transmitted to the CPU. | |
6955 | * Reserved when entry_type = MARKER_ENTRY | |
6956 | * Access: RW | |
6957 | */ | |
6958 | MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); | |
6959 | ||
6960 | enum mlxsw_reg_ralue_trap_action { | |
6961 | MLXSW_REG_RALUE_TRAP_ACTION_NOP, | |
6962 | MLXSW_REG_RALUE_TRAP_ACTION_TRAP, | |
6963 | MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, | |
6964 | MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, | |
6965 | MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, | |
6966 | }; | |
6967 | ||
6968 | /* reg_ralue_trap_action | |
6969 | * Trap action. | |
6970 | * For IP2ME action, only NOP and MIRROR are possible. | |
6971 | * Access: RW | |
6972 | */ | |
6973 | MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); | |
6974 | ||
6975 | /* reg_ralue_trap_id | |
6976 | * Trap ID to be reported to CPU. | |
6977 | * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. | |
6978 | * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. | |
6979 | * Access: RW | |
6980 | */ | |
6981 | MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); | |
6982 | ||
6983 | /* reg_ralue_adjacency_index | |
6984 | * Points to the first entry of the group-based ECMP. | |
6985 | * Only relevant in case of REMOTE action. | |
6986 | * Access: RW | |
6987 | */ | |
6988 | MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); | |
6989 | ||
6990 | /* reg_ralue_ecmp_size | |
6991 | * Amount of sequential entries starting | |
6992 | * from the adjacency_index (the number of ECMPs). | |
6993 | * The valid range is 1-64, 512, 1024, 2048 and 4096. | |
6994 | * Reserved when trap_action is TRAP or DISCARD_ERROR. | |
6995 | * Only relevant in case of REMOTE action. | |
6996 | * Access: RW | |
6997 | */ | |
6998 | MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); | |
6999 | ||
7000 | /* reg_ralue_local_erif | |
7001 | * Egress Router Interface. | |
7002 | * Only relevant in case of LOCAL action. | |
7003 | * Access: RW | |
7004 | */ | |
7005 | MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); | |
7006 | ||
83930cd7 | 7007 | /* reg_ralue_ip2me_v |
d5a1c749 JP |
7008 | * Valid bit for the tunnel_ptr field. |
7009 | * If valid = 0 then trap to CPU as IP2ME trap ID. | |
7010 | * If valid = 1 and the packet format allows NVE or IPinIP tunnel | |
7011 | * decapsulation then tunnel decapsulation is done. | |
7012 | * If valid = 1 and packet format does not allow NVE or IPinIP tunnel | |
7013 | * decapsulation then trap as IP2ME trap ID. | |
7014 | * Only relevant in case of IP2ME action. | |
7015 | * Access: RW | |
7016 | */ | |
83930cd7 | 7017 | MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); |
d5a1c749 | 7018 | |
83930cd7 | 7019 | /* reg_ralue_ip2me_tunnel_ptr |
d5a1c749 JP |
7020 | * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. |
7021 | * For Spectrum, pointer to KVD Linear. | |
7022 | * Only relevant in case of IP2ME action. | |
7023 | * Access: RW | |
7024 | */ | |
83930cd7 | 7025 | MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); |
d5a1c749 JP |
7026 | |
7027 | static inline void mlxsw_reg_ralue_pack(char *payload, | |
7028 | enum mlxsw_reg_ralxx_protocol protocol, | |
7029 | enum mlxsw_reg_ralue_op op, | |
7030 | u16 virtual_router, u8 prefix_len) | |
7031 | { | |
7032 | MLXSW_REG_ZERO(ralue, payload); | |
7033 | mlxsw_reg_ralue_protocol_set(payload, protocol); | |
0e7df1a2 | 7034 | mlxsw_reg_ralue_op_set(payload, op); |
d5a1c749 JP |
7035 | mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); |
7036 | mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); | |
7037 | mlxsw_reg_ralue_entry_type_set(payload, | |
7038 | MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); | |
7039 | mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); | |
7040 | } | |
7041 | ||
7042 | static inline void mlxsw_reg_ralue_pack4(char *payload, | |
7043 | enum mlxsw_reg_ralxx_protocol protocol, | |
7044 | enum mlxsw_reg_ralue_op op, | |
7045 | u16 virtual_router, u8 prefix_len, | |
7046 | u32 dip) | |
7047 | { | |
7048 | mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); | |
7049 | mlxsw_reg_ralue_dip4_set(payload, dip); | |
7050 | } | |
7051 | ||
62547f40 IS |
7052 | static inline void mlxsw_reg_ralue_pack6(char *payload, |
7053 | enum mlxsw_reg_ralxx_protocol protocol, | |
7054 | enum mlxsw_reg_ralue_op op, | |
7055 | u16 virtual_router, u8 prefix_len, | |
7056 | const void *dip) | |
7057 | { | |
7058 | mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); | |
7059 | mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); | |
7060 | } | |
7061 | ||
d5a1c749 JP |
7062 | static inline void |
7063 | mlxsw_reg_ralue_act_remote_pack(char *payload, | |
7064 | enum mlxsw_reg_ralue_trap_action trap_action, | |
7065 | u16 trap_id, u32 adjacency_index, u16 ecmp_size) | |
7066 | { | |
7067 | mlxsw_reg_ralue_action_type_set(payload, | |
7068 | MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); | |
7069 | mlxsw_reg_ralue_trap_action_set(payload, trap_action); | |
7070 | mlxsw_reg_ralue_trap_id_set(payload, trap_id); | |
7071 | mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); | |
7072 | mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); | |
7073 | } | |
7074 | ||
7075 | static inline void | |
7076 | mlxsw_reg_ralue_act_local_pack(char *payload, | |
7077 | enum mlxsw_reg_ralue_trap_action trap_action, | |
7078 | u16 trap_id, u16 local_erif) | |
7079 | { | |
7080 | mlxsw_reg_ralue_action_type_set(payload, | |
7081 | MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); | |
7082 | mlxsw_reg_ralue_trap_action_set(payload, trap_action); | |
7083 | mlxsw_reg_ralue_trap_id_set(payload, trap_id); | |
7084 | mlxsw_reg_ralue_local_erif_set(payload, local_erif); | |
7085 | } | |
7086 | ||
7087 | static inline void | |
7088 | mlxsw_reg_ralue_act_ip2me_pack(char *payload) | |
7089 | { | |
7090 | mlxsw_reg_ralue_action_type_set(payload, | |
7091 | MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); | |
7092 | } | |
7093 | ||
a43da820 PM |
7094 | static inline void |
7095 | mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) | |
7096 | { | |
7097 | mlxsw_reg_ralue_action_type_set(payload, | |
7098 | MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); | |
7099 | mlxsw_reg_ralue_ip2me_v_set(payload, 1); | |
7100 | mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); | |
7101 | } | |
7102 | ||
4457b3df YG |
7103 | /* RAUHT - Router Algorithmic LPM Unicast Host Table Register |
7104 | * ---------------------------------------------------------- | |
7105 | * The RAUHT register is used to configure and query the Unicast Host table in | |
7106 | * devices that implement the Algorithmic LPM. | |
7107 | */ | |
7108 | #define MLXSW_REG_RAUHT_ID 0x8014 | |
7109 | #define MLXSW_REG_RAUHT_LEN 0x74 | |
7110 | ||
21978dcf | 7111 | MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); |
4457b3df YG |
7112 | |
7113 | enum mlxsw_reg_rauht_type { | |
7114 | MLXSW_REG_RAUHT_TYPE_IPV4, | |
7115 | MLXSW_REG_RAUHT_TYPE_IPV6, | |
7116 | }; | |
7117 | ||
7118 | /* reg_rauht_type | |
7119 | * Access: Index | |
7120 | */ | |
7121 | MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); | |
7122 | ||
7123 | enum mlxsw_reg_rauht_op { | |
7124 | MLXSW_REG_RAUHT_OP_QUERY_READ = 0, | |
7125 | /* Read operation */ | |
7126 | MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, | |
7127 | /* Clear on read operation. Used to read entry and clear | |
7128 | * activity bit. | |
7129 | */ | |
7130 | MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, | |
7131 | /* Add. Used to write a new entry to the table. All R/W fields are | |
7132 | * relevant for new entry. Activity bit is set for new entries. | |
7133 | */ | |
7134 | MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, | |
7135 | /* Update action. Used to update an existing route entry and | |
7136 | * only update the following fields: | |
7137 | * trap_action, trap_id, mac, counter_set_type, counter_index | |
7138 | */ | |
7139 | MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, | |
7140 | /* Clear activity. A bit is cleared for the entry. */ | |
7141 | MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, | |
7142 | /* Delete entry */ | |
7143 | MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, | |
7144 | /* Delete all host entries on a RIF. In this command, dip | |
7145 | * field is reserved. | |
7146 | */ | |
7147 | }; | |
7148 | ||
7149 | /* reg_rauht_op | |
7150 | * Access: OP | |
7151 | */ | |
7152 | MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); | |
7153 | ||
7154 | /* reg_rauht_a | |
7155 | * Activity. Set for new entries. Set if a packet lookup has hit on | |
7156 | * the specific entry. | |
7157 | * To clear the a bit, use "clear activity" op. | |
7158 | * Enabled by activity_dis in RGCR | |
7159 | * Access: RO | |
7160 | */ | |
7161 | MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); | |
7162 | ||
7163 | /* reg_rauht_rif | |
7164 | * Router Interface | |
7165 | * Access: Index | |
7166 | */ | |
7167 | MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); | |
7168 | ||
7169 | /* reg_rauht_dip* | |
7170 | * Destination address. | |
7171 | * Access: Index | |
7172 | */ | |
7173 | MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); | |
6929e507 | 7174 | MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); |
4457b3df YG |
7175 | |
7176 | enum mlxsw_reg_rauht_trap_action { | |
7177 | MLXSW_REG_RAUHT_TRAP_ACTION_NOP, | |
7178 | MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, | |
7179 | MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, | |
7180 | MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, | |
7181 | MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, | |
7182 | }; | |
7183 | ||
7184 | /* reg_rauht_trap_action | |
7185 | * Access: RW | |
7186 | */ | |
7187 | MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); | |
7188 | ||
7189 | enum mlxsw_reg_rauht_trap_id { | |
7190 | MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, | |
7191 | MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, | |
7192 | }; | |
7193 | ||
7194 | /* reg_rauht_trap_id | |
7195 | * Trap ID to be reported to CPU. | |
7196 | * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. | |
7197 | * For trap_action of NOP, MIRROR and DISCARD_ERROR, | |
7198 | * trap_id is reserved. | |
7199 | * Access: RW | |
7200 | */ | |
7201 | MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); | |
7202 | ||
7203 | /* reg_rauht_counter_set_type | |
7204 | * Counter set type for flow counters | |
7205 | * Access: RW | |
7206 | */ | |
7207 | MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); | |
7208 | ||
7209 | /* reg_rauht_counter_index | |
7210 | * Counter index for flow counters | |
7211 | * Access: RW | |
7212 | */ | |
7213 | MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); | |
7214 | ||
7215 | /* reg_rauht_mac | |
7216 | * MAC address. | |
7217 | * Access: RW | |
7218 | */ | |
7219 | MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); | |
7220 | ||
7221 | static inline void mlxsw_reg_rauht_pack(char *payload, | |
7222 | enum mlxsw_reg_rauht_op op, u16 rif, | |
7223 | const char *mac) | |
7224 | { | |
7225 | MLXSW_REG_ZERO(rauht, payload); | |
7226 | mlxsw_reg_rauht_op_set(payload, op); | |
7227 | mlxsw_reg_rauht_rif_set(payload, rif); | |
7228 | mlxsw_reg_rauht_mac_memcpy_to(payload, mac); | |
7229 | } | |
7230 | ||
7231 | static inline void mlxsw_reg_rauht_pack4(char *payload, | |
7232 | enum mlxsw_reg_rauht_op op, u16 rif, | |
7233 | const char *mac, u32 dip) | |
7234 | { | |
7235 | mlxsw_reg_rauht_pack(payload, op, rif, mac); | |
7236 | mlxsw_reg_rauht_dip4_set(payload, dip); | |
7237 | } | |
7238 | ||
6929e507 AS |
7239 | static inline void mlxsw_reg_rauht_pack6(char *payload, |
7240 | enum mlxsw_reg_rauht_op op, u16 rif, | |
7241 | const char *mac, const char *dip) | |
7242 | { | |
7243 | mlxsw_reg_rauht_pack(payload, op, rif, mac); | |
7244 | mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); | |
7245 | mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); | |
7246 | } | |
7247 | ||
7cfcbc75 AS |
7248 | static inline void mlxsw_reg_rauht_pack_counter(char *payload, |
7249 | u64 counter_index) | |
7250 | { | |
7251 | mlxsw_reg_rauht_counter_index_set(payload, counter_index); | |
7252 | mlxsw_reg_rauht_counter_set_type_set(payload, | |
7253 | MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); | |
7254 | } | |
7255 | ||
a59f0b31 JP |
7256 | /* RALEU - Router Algorithmic LPM ECMP Update Register |
7257 | * --------------------------------------------------- | |
7258 | * The register enables updating the ECMP section in the action for multiple | |
7259 | * LPM Unicast entries in a single operation. The update is executed to | |
7260 | * all entries of a {virtual router, protocol} tuple using the same ECMP group. | |
7261 | */ | |
7262 | #define MLXSW_REG_RALEU_ID 0x8015 | |
7263 | #define MLXSW_REG_RALEU_LEN 0x28 | |
7264 | ||
21978dcf | 7265 | MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); |
a59f0b31 JP |
7266 | |
7267 | /* reg_raleu_protocol | |
7268 | * Protocol. | |
7269 | * Access: Index | |
7270 | */ | |
7271 | MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); | |
7272 | ||
7273 | /* reg_raleu_virtual_router | |
7274 | * Virtual Router ID | |
7275 | * Range is 0..cap_max_virtual_routers-1 | |
7276 | * Access: Index | |
7277 | */ | |
7278 | MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); | |
7279 | ||
7280 | /* reg_raleu_adjacency_index | |
7281 | * Adjacency Index used for matching on the existing entries. | |
7282 | * Access: Index | |
7283 | */ | |
7284 | MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); | |
7285 | ||
7286 | /* reg_raleu_ecmp_size | |
7287 | * ECMP Size used for matching on the existing entries. | |
7288 | * Access: Index | |
7289 | */ | |
7290 | MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); | |
7291 | ||
7292 | /* reg_raleu_new_adjacency_index | |
7293 | * New Adjacency Index. | |
7294 | * Access: WO | |
7295 | */ | |
7296 | MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); | |
7297 | ||
7298 | /* reg_raleu_new_ecmp_size | |
7299 | * New ECMP Size. | |
7300 | * Access: WO | |
7301 | */ | |
7302 | MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); | |
7303 | ||
7304 | static inline void mlxsw_reg_raleu_pack(char *payload, | |
7305 | enum mlxsw_reg_ralxx_protocol protocol, | |
7306 | u16 virtual_router, | |
7307 | u32 adjacency_index, u16 ecmp_size, | |
7308 | u32 new_adjacency_index, | |
7309 | u16 new_ecmp_size) | |
7310 | { | |
7311 | MLXSW_REG_ZERO(raleu, payload); | |
7312 | mlxsw_reg_raleu_protocol_set(payload, protocol); | |
7313 | mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); | |
7314 | mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); | |
7315 | mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); | |
7316 | mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); | |
7317 | mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); | |
7318 | } | |
7319 | ||
7cf2c205 YG |
7320 | /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register |
7321 | * ---------------------------------------------------------------- | |
7322 | * The RAUHTD register allows dumping entries from the Router Unicast Host | |
7323 | * Table. For a given session an entry is dumped no more than one time. The | |
7324 | * first RAUHTD access after reset is a new session. A session ends when the | |
7325 | * num_rec response is smaller than num_rec request or for IPv4 when the | |
7326 | * num_entries is smaller than 4. The clear activity affect the current session | |
7327 | * or the last session if a new session has not started. | |
7328 | */ | |
7329 | #define MLXSW_REG_RAUHTD_ID 0x8018 | |
7330 | #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 | |
7331 | #define MLXSW_REG_RAUHTD_REC_LEN 0x20 | |
7332 | #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 | |
7333 | #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ | |
7334 | MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) | |
7335 | #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 | |
7336 | ||
21978dcf | 7337 | MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); |
7cf2c205 YG |
7338 | |
7339 | #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) | |
7340 | #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) | |
7341 | ||
7342 | /* reg_rauhtd_filter_fields | |
7343 | * if a bit is '0' then the relevant field is ignored and dump is done | |
7344 | * regardless of the field value | |
7345 | * Bit0 - filter by activity: entry_a | |
7346 | * Bit3 - filter by entry rip: entry_rif | |
7347 | * Access: Index | |
7348 | */ | |
7349 | MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); | |
7350 | ||
7351 | enum mlxsw_reg_rauhtd_op { | |
7352 | MLXSW_REG_RAUHTD_OP_DUMP, | |
7353 | MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, | |
7354 | }; | |
7355 | ||
7356 | /* reg_rauhtd_op | |
7357 | * Access: OP | |
7358 | */ | |
7359 | MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); | |
7360 | ||
7361 | /* reg_rauhtd_num_rec | |
7362 | * At request: number of records requested | |
7363 | * At response: number of records dumped | |
7364 | * For IPv4, each record has 4 entries at request and up to 4 entries | |
7365 | * at response | |
7366 | * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM | |
7367 | * Access: Index | |
7368 | */ | |
7369 | MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); | |
7370 | ||
7371 | /* reg_rauhtd_entry_a | |
7372 | * Dump only if activity has value of entry_a | |
7373 | * Reserved if filter_fields bit0 is '0' | |
7374 | * Access: Index | |
7375 | */ | |
7376 | MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); | |
7377 | ||
7378 | enum mlxsw_reg_rauhtd_type { | |
7379 | MLXSW_REG_RAUHTD_TYPE_IPV4, | |
7380 | MLXSW_REG_RAUHTD_TYPE_IPV6, | |
7381 | }; | |
7382 | ||
7383 | /* reg_rauhtd_type | |
7384 | * Dump only if record type is: | |
7385 | * 0 - IPv4 | |
7386 | * 1 - IPv6 | |
7387 | * Access: Index | |
7388 | */ | |
7389 | MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); | |
7390 | ||
7391 | /* reg_rauhtd_entry_rif | |
7392 | * Dump only if RIF has value of entry_rif | |
7393 | * Reserved if filter_fields bit3 is '0' | |
7394 | * Access: Index | |
7395 | */ | |
7396 | MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); | |
7397 | ||
7398 | static inline void mlxsw_reg_rauhtd_pack(char *payload, | |
7399 | enum mlxsw_reg_rauhtd_type type) | |
7400 | { | |
7401 | MLXSW_REG_ZERO(rauhtd, payload); | |
7402 | mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); | |
7403 | mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); | |
7404 | mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); | |
7405 | mlxsw_reg_rauhtd_entry_a_set(payload, 1); | |
7406 | mlxsw_reg_rauhtd_type_set(payload, type); | |
7407 | } | |
7408 | ||
7409 | /* reg_rauhtd_ipv4_rec_num_entries | |
7410 | * Number of valid entries in this record: | |
7411 | * 0 - 1 valid entry | |
7412 | * 1 - 2 valid entries | |
7413 | * 2 - 3 valid entries | |
7414 | * 3 - 4 valid entries | |
7415 | * Access: RO | |
7416 | */ | |
7417 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, | |
7418 | MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, | |
7419 | MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); | |
7420 | ||
7421 | /* reg_rauhtd_rec_type | |
7422 | * Record type. | |
7423 | * 0 - IPv4 | |
7424 | * 1 - IPv6 | |
7425 | * Access: RO | |
7426 | */ | |
7427 | MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, | |
7428 | MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); | |
7429 | ||
7430 | #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 | |
7431 | ||
7432 | /* reg_rauhtd_ipv4_ent_a | |
7433 | * Activity. Set for new entries. Set if a packet lookup has hit on the | |
7434 | * specific entry. | |
7435 | * Access: RO | |
7436 | */ | |
7437 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, | |
7438 | MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); | |
7439 | ||
7440 | /* reg_rauhtd_ipv4_ent_rif | |
7441 | * Router interface. | |
7442 | * Access: RO | |
7443 | */ | |
7444 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, | |
7445 | 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); | |
7446 | ||
7447 | /* reg_rauhtd_ipv4_ent_dip | |
7448 | * Destination IPv4 address. | |
7449 | * Access: RO | |
7450 | */ | |
7451 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, | |
7452 | 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); | |
7453 | ||
72e8ebe1 AS |
7454 | #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 |
7455 | ||
7456 | /* reg_rauhtd_ipv6_ent_a | |
7457 | * Activity. Set for new entries. Set if a packet lookup has hit on the | |
7458 | * specific entry. | |
7459 | * Access: RO | |
7460 | */ | |
7461 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, | |
7462 | MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); | |
7463 | ||
7464 | /* reg_rauhtd_ipv6_ent_rif | |
7465 | * Router interface. | |
7466 | * Access: RO | |
7467 | */ | |
7468 | MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, | |
7469 | 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); | |
7470 | ||
7471 | /* reg_rauhtd_ipv6_ent_dip | |
7472 | * Destination IPv6 address. | |
7473 | * Access: RO | |
7474 | */ | |
7475 | MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, | |
7476 | 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); | |
7477 | ||
7cf2c205 YG |
7478 | static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, |
7479 | int ent_index, u16 *p_rif, | |
7480 | u32 *p_dip) | |
7481 | { | |
7482 | *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); | |
7483 | *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); | |
7484 | } | |
7485 | ||
72e8ebe1 AS |
7486 | static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, |
7487 | int rec_index, u16 *p_rif, | |
7488 | char *p_dip) | |
7489 | { | |
7490 | *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); | |
7491 | mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); | |
7492 | } | |
7493 | ||
1e659ebf PM |
7494 | /* RTDP - Routing Tunnel Decap Properties Register |
7495 | * ----------------------------------------------- | |
7496 | * The RTDP register is used for configuring the tunnel decap properties of NVE | |
7497 | * and IPinIP. | |
7498 | */ | |
7499 | #define MLXSW_REG_RTDP_ID 0x8020 | |
7500 | #define MLXSW_REG_RTDP_LEN 0x44 | |
7501 | ||
7502 | MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); | |
7503 | ||
7504 | enum mlxsw_reg_rtdp_type { | |
7505 | MLXSW_REG_RTDP_TYPE_NVE, | |
7506 | MLXSW_REG_RTDP_TYPE_IPIP, | |
7507 | }; | |
7508 | ||
7509 | /* reg_rtdp_type | |
7510 | * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. | |
7511 | * Access: RW | |
7512 | */ | |
7513 | MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); | |
7514 | ||
7515 | /* reg_rtdp_tunnel_index | |
7516 | * Index to the Decap entry. | |
7517 | * For Spectrum, Index to KVD Linear. | |
7518 | * Access: Index | |
7519 | */ | |
7520 | MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); | |
7521 | ||
c9417498 IS |
7522 | /* reg_rtdp_egress_router_interface |
7523 | * Underlay egress router interface. | |
7524 | * Valid range is from 0 to cap_max_router_interfaces - 1 | |
7525 | * Access: RW | |
7526 | */ | |
7527 | MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); | |
7528 | ||
1e659ebf PM |
7529 | /* IPinIP */ |
7530 | ||
7531 | /* reg_rtdp_ipip_irif | |
7532 | * Ingress Router Interface for the overlay router | |
7533 | * Access: RW | |
7534 | */ | |
7535 | MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); | |
7536 | ||
7537 | enum mlxsw_reg_rtdp_ipip_sip_check { | |
7538 | /* No sip checks. */ | |
7539 | MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, | |
7540 | /* Filter packet if underlay is not IPv4 or if underlay SIP does not | |
7541 | * equal ipv4_usip. | |
7542 | */ | |
7543 | MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, | |
7544 | /* Filter packet if underlay is not IPv6 or if underlay SIP does not | |
7545 | * equal ipv6_usip. | |
7546 | */ | |
7547 | MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, | |
7548 | }; | |
7549 | ||
7550 | /* reg_rtdp_ipip_sip_check | |
7551 | * SIP check to perform. If decapsulation failed due to these configurations | |
7552 | * then trap_id is IPIP_DECAP_ERROR. | |
7553 | * Access: RW | |
7554 | */ | |
7555 | MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); | |
7556 | ||
7557 | /* If set, allow decapsulation of IPinIP (without GRE). */ | |
7558 | #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) | |
7559 | /* If set, allow decapsulation of IPinGREinIP without a key. */ | |
7560 | #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) | |
7561 | /* If set, allow decapsulation of IPinGREinIP with a key. */ | |
7562 | #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) | |
7563 | ||
7564 | /* reg_rtdp_ipip_type_check | |
7565 | * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to | |
7566 | * these configurations then trap_id is IPIP_DECAP_ERROR. | |
7567 | * Access: RW | |
7568 | */ | |
7569 | MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); | |
7570 | ||
7571 | /* reg_rtdp_ipip_gre_key_check | |
7572 | * Whether GRE key should be checked. When check is enabled: | |
7573 | * - A packet received as IPinIP (without GRE) will always pass. | |
7574 | * - A packet received as IPinGREinIP without a key will not pass the check. | |
7575 | * - A packet received as IPinGREinIP with a key will pass the check only if the | |
7576 | * key in the packet is equal to expected_gre_key. | |
7577 | * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. | |
7578 | * Access: RW | |
7579 | */ | |
7580 | MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); | |
7581 | ||
7582 | /* reg_rtdp_ipip_ipv4_usip | |
7583 | * Underlay IPv4 address for ipv4 source address check. | |
7584 | * Reserved when sip_check is not '1'. | |
7585 | * Access: RW | |
7586 | */ | |
7587 | MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); | |
7588 | ||
7589 | /* reg_rtdp_ipip_ipv6_usip_ptr | |
7590 | * This field is valid when sip_check is "sipv6 check explicitly". This is a | |
7591 | * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index | |
7592 | * is to the KVD linear. | |
7593 | * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. | |
7594 | * Access: RW | |
7595 | */ | |
7596 | MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); | |
7597 | ||
7598 | /* reg_rtdp_ipip_expected_gre_key | |
7599 | * GRE key for checking. | |
7600 | * Reserved when gre_key_check is '0'. | |
7601 | * Access: RW | |
7602 | */ | |
7603 | MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); | |
7604 | ||
7605 | static inline void mlxsw_reg_rtdp_pack(char *payload, | |
7606 | enum mlxsw_reg_rtdp_type type, | |
7607 | u32 tunnel_index) | |
7608 | { | |
7609 | MLXSW_REG_ZERO(rtdp, payload); | |
7610 | mlxsw_reg_rtdp_type_set(payload, type); | |
7611 | mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); | |
7612 | } | |
7613 | ||
7614 | static inline void | |
7615 | mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, | |
7616 | enum mlxsw_reg_rtdp_ipip_sip_check sip_check, | |
7617 | unsigned int type_check, bool gre_key_check, | |
7618 | u32 ipv4_usip, u32 expected_gre_key) | |
7619 | { | |
7620 | mlxsw_reg_rtdp_ipip_irif_set(payload, irif); | |
7621 | mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); | |
7622 | mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); | |
7623 | mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); | |
7624 | mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); | |
7625 | mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); | |
7626 | } | |
7627 | ||
5080c7e9 YG |
7628 | /* RIGR-V2 - Router Interface Group Register Version 2 |
7629 | * --------------------------------------------------- | |
7630 | * The RIGR_V2 register is used to add, remove and query egress interface list | |
7631 | * of a multicast forwarding entry. | |
7632 | */ | |
7633 | #define MLXSW_REG_RIGR2_ID 0x8023 | |
7634 | #define MLXSW_REG_RIGR2_LEN 0xB0 | |
7635 | ||
7636 | #define MLXSW_REG_RIGR2_MAX_ERIFS 32 | |
7637 | ||
7638 | MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); | |
7639 | ||
7640 | /* reg_rigr2_rigr_index | |
7641 | * KVD Linear index. | |
7642 | * Access: Index | |
7643 | */ | |
7644 | MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); | |
7645 | ||
7646 | /* reg_rigr2_vnext | |
7647 | * Next RIGR Index is valid. | |
7648 | * Access: RW | |
7649 | */ | |
7650 | MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); | |
7651 | ||
7652 | /* reg_rigr2_next_rigr_index | |
7653 | * Next RIGR Index. The index is to the KVD linear. | |
7654 | * Reserved when vnxet = '0'. | |
7655 | * Access: RW | |
7656 | */ | |
7657 | MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); | |
7658 | ||
7659 | /* reg_rigr2_vrmid | |
7660 | * RMID Index is valid. | |
7661 | * Access: RW | |
7662 | */ | |
7663 | MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); | |
7664 | ||
7665 | /* reg_rigr2_rmid_index | |
7666 | * RMID Index. | |
7667 | * Range 0 .. max_mid - 1 | |
7668 | * Reserved when vrmid = '0'. | |
7669 | * The index is to the Port Group Table (PGT) | |
7670 | * Access: RW | |
7671 | */ | |
7672 | MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); | |
7673 | ||
7674 | /* reg_rigr2_erif_entry_v | |
7675 | * Egress Router Interface is valid. | |
7676 | * Note that low-entries must be set if high-entries are set. For | |
7677 | * example: if erif_entry[2].v is set then erif_entry[1].v and | |
7678 | * erif_entry[0].v must be set. | |
7679 | * Index can be from 0 to cap_mc_erif_list_entries-1 | |
7680 | * Access: RW | |
7681 | */ | |
7682 | MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); | |
7683 | ||
7684 | /* reg_rigr2_erif_entry_erif | |
7685 | * Egress Router Interface. | |
7686 | * Valid range is from 0 to cap_max_router_interfaces - 1 | |
7687 | * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 | |
7688 | * Access: RW | |
7689 | */ | |
7690 | MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); | |
7691 | ||
7692 | static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, | |
7693 | bool vnext, u32 next_rigr_index) | |
7694 | { | |
7695 | MLXSW_REG_ZERO(rigr2, payload); | |
7696 | mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); | |
7697 | mlxsw_reg_rigr2_vnext_set(payload, vnext); | |
7698 | mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); | |
7699 | mlxsw_reg_rigr2_vrmid_set(payload, 0); | |
7700 | mlxsw_reg_rigr2_rmid_index_set(payload, 0); | |
7701 | } | |
7702 | ||
7703 | static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, | |
7704 | bool v, u16 erif) | |
7705 | { | |
7706 | mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); | |
7707 | mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); | |
7708 | } | |
7709 | ||
e471859b IS |
7710 | /* RECR-V2 - Router ECMP Configuration Version 2 Register |
7711 | * ------------------------------------------------------ | |
7712 | */ | |
7713 | #define MLXSW_REG_RECR2_ID 0x8025 | |
7714 | #define MLXSW_REG_RECR2_LEN 0x38 | |
7715 | ||
7716 | MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); | |
7717 | ||
7718 | /* reg_recr2_pp | |
7719 | * Per-port configuration | |
7720 | * Access: Index | |
7721 | */ | |
7722 | MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); | |
7723 | ||
7724 | /* reg_recr2_sh | |
7725 | * Symmetric hash | |
7726 | * Access: RW | |
7727 | */ | |
7728 | MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); | |
7729 | ||
7730 | /* reg_recr2_seed | |
7731 | * Seed | |
7732 | * Access: RW | |
7733 | */ | |
7734 | MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); | |
7735 | ||
7736 | enum { | |
7737 | /* Enable IPv4 fields if packet is not TCP and not UDP */ | |
7738 | MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, | |
7739 | /* Enable IPv4 fields if packet is TCP or UDP */ | |
7740 | MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, | |
7741 | /* Enable IPv6 fields if packet is not TCP and not UDP */ | |
7742 | MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, | |
7743 | /* Enable IPv6 fields if packet is TCP or UDP */ | |
7744 | MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, | |
7745 | /* Enable TCP/UDP header fields if packet is IPv4 */ | |
7746 | MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, | |
7747 | /* Enable TCP/UDP header fields if packet is IPv6 */ | |
7748 | MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, | |
7749 | }; | |
7750 | ||
7751 | /* reg_recr2_outer_header_enables | |
7752 | * Bit mask where each bit enables a specific layer to be included in | |
7753 | * the hash calculation. | |
7754 | * Access: RW | |
7755 | */ | |
7756 | MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); | |
7757 | ||
7758 | enum { | |
7759 | /* IPv4 Source IP */ | |
7760 | MLXSW_REG_RECR2_IPV4_SIP0 = 9, | |
7761 | MLXSW_REG_RECR2_IPV4_SIP3 = 12, | |
7762 | /* IPv4 Destination IP */ | |
7763 | MLXSW_REG_RECR2_IPV4_DIP0 = 13, | |
7764 | MLXSW_REG_RECR2_IPV4_DIP3 = 16, | |
7765 | /* IP Protocol */ | |
7766 | MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, | |
7767 | /* IPv6 Source IP */ | |
7768 | MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, | |
7769 | MLXSW_REG_RECR2_IPV6_SIP8 = 29, | |
7770 | MLXSW_REG_RECR2_IPV6_SIP15 = 36, | |
7771 | /* IPv6 Destination IP */ | |
7772 | MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, | |
7773 | MLXSW_REG_RECR2_IPV6_DIP8 = 45, | |
7774 | MLXSW_REG_RECR2_IPV6_DIP15 = 52, | |
7775 | /* IPv6 Next Header */ | |
7776 | MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, | |
7777 | /* IPv6 Flow Label */ | |
7778 | MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, | |
7779 | /* TCP/UDP Source Port */ | |
7780 | MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, | |
7781 | /* TCP/UDP Destination Port */ | |
7782 | MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, | |
7783 | }; | |
7784 | ||
7785 | /* reg_recr2_outer_header_fields_enable | |
7786 | * Packet fields to enable for ECMP hash subject to outer_header_enable. | |
7787 | * Access: RW | |
7788 | */ | |
7789 | MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); | |
7790 | ||
7791 | static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) | |
7792 | { | |
7793 | int i; | |
7794 | ||
7795 | for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) | |
7796 | mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, | |
7797 | true); | |
7798 | } | |
7799 | ||
7800 | static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) | |
7801 | { | |
7802 | int i; | |
7803 | ||
7804 | for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) | |
7805 | mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, | |
7806 | true); | |
7807 | } | |
7808 | ||
7809 | static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) | |
7810 | { | |
7811 | int i = MLXSW_REG_RECR2_IPV6_SIP0_7; | |
7812 | ||
7813 | mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); | |
7814 | ||
7815 | i = MLXSW_REG_RECR2_IPV6_SIP8; | |
7816 | for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) | |
7817 | mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, | |
7818 | true); | |
7819 | } | |
7820 | ||
7821 | static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) | |
7822 | { | |
7823 | int i = MLXSW_REG_RECR2_IPV6_DIP0_7; | |
7824 | ||
7825 | mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); | |
7826 | ||
7827 | i = MLXSW_REG_RECR2_IPV6_DIP8; | |
7828 | for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) | |
7829 | mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, | |
7830 | true); | |
7831 | } | |
7832 | ||
7833 | static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) | |
7834 | { | |
7835 | MLXSW_REG_ZERO(recr2, payload); | |
7836 | mlxsw_reg_recr2_pp_set(payload, false); | |
7837 | mlxsw_reg_recr2_sh_set(payload, true); | |
7838 | mlxsw_reg_recr2_seed_set(payload, seed); | |
7839 | } | |
7840 | ||
2e654e33 YG |
7841 | /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register |
7842 | * -------------------------------------------------------------- | |
7843 | * The RMFT_V2 register is used to configure and query the multicast table. | |
7844 | */ | |
7845 | #define MLXSW_REG_RMFT2_ID 0x8027 | |
7846 | #define MLXSW_REG_RMFT2_LEN 0x174 | |
7847 | ||
7848 | MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); | |
7849 | ||
7850 | /* reg_rmft2_v | |
7851 | * Valid | |
7852 | * Access: RW | |
7853 | */ | |
7854 | MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); | |
7855 | ||
7856 | enum mlxsw_reg_rmft2_type { | |
7857 | MLXSW_REG_RMFT2_TYPE_IPV4, | |
7858 | MLXSW_REG_RMFT2_TYPE_IPV6 | |
7859 | }; | |
7860 | ||
7861 | /* reg_rmft2_type | |
7862 | * Access: Index | |
7863 | */ | |
7864 | MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); | |
7865 | ||
7866 | enum mlxsw_sp_reg_rmft2_op { | |
7867 | /* For Write: | |
7868 | * Write operation. Used to write a new entry to the table. All RW | |
7869 | * fields are relevant for new entry. Activity bit is set for new | |
7870 | * entries - Note write with v (Valid) 0 will delete the entry. | |
7871 | * For Query: | |
7872 | * Read operation | |
7873 | */ | |
7874 | MLXSW_REG_RMFT2_OP_READ_WRITE, | |
7875 | }; | |
7876 | ||
7877 | /* reg_rmft2_op | |
7878 | * Operation. | |
7879 | * Access: OP | |
7880 | */ | |
7881 | MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); | |
7882 | ||
7883 | /* reg_rmft2_a | |
7884 | * Activity. Set for new entries. Set if a packet lookup has hit on the specific | |
7885 | * entry. | |
7886 | * Access: RO | |
7887 | */ | |
7888 | MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); | |
7889 | ||
7890 | /* reg_rmft2_offset | |
7891 | * Offset within the multicast forwarding table to write to. | |
7892 | * Access: Index | |
7893 | */ | |
7894 | MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); | |
7895 | ||
7896 | /* reg_rmft2_virtual_router | |
7897 | * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 | |
7898 | * Access: RW | |
7899 | */ | |
7900 | MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); | |
7901 | ||
7902 | enum mlxsw_reg_rmft2_irif_mask { | |
7903 | MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, | |
7904 | MLXSW_REG_RMFT2_IRIF_MASK_COMPARE | |
7905 | }; | |
7906 | ||
7907 | /* reg_rmft2_irif_mask | |
7908 | * Ingress RIF mask. | |
7909 | * Access: RW | |
7910 | */ | |
7911 | MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); | |
7912 | ||
7913 | /* reg_rmft2_irif | |
7914 | * Ingress RIF index. | |
7915 | * Access: RW | |
7916 | */ | |
7917 | MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); | |
7918 | ||
a82b1b8f YM |
7919 | /* reg_rmft2_dip{4,6} |
7920 | * Destination IPv4/6 address | |
2e654e33 YG |
7921 | * Access: RW |
7922 | */ | |
a82b1b8f | 7923 | MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); |
2e654e33 YG |
7924 | MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); |
7925 | ||
a82b1b8f | 7926 | /* reg_rmft2_dip{4,6}_mask |
2e654e33 YG |
7927 | * A bit that is set directs the TCAM to compare the corresponding bit in key. A |
7928 | * bit that is clear directs the TCAM to ignore the corresponding bit in key. | |
7929 | * Access: RW | |
7930 | */ | |
a82b1b8f | 7931 | MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); |
2e654e33 YG |
7932 | MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); |
7933 | ||
a82b1b8f YM |
7934 | /* reg_rmft2_sip{4,6} |
7935 | * Source IPv4/6 address | |
2e654e33 YG |
7936 | * Access: RW |
7937 | */ | |
a82b1b8f | 7938 | MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); |
2e654e33 YG |
7939 | MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); |
7940 | ||
a82b1b8f | 7941 | /* reg_rmft2_sip{4,6}_mask |
2e654e33 YG |
7942 | * A bit that is set directs the TCAM to compare the corresponding bit in key. A |
7943 | * bit that is clear directs the TCAM to ignore the corresponding bit in key. | |
7944 | * Access: RW | |
7945 | */ | |
a82b1b8f | 7946 | MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); |
2e654e33 YG |
7947 | MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); |
7948 | ||
7949 | /* reg_rmft2_flexible_action_set | |
7950 | * ACL action set. The only supported action types in this field and in any | |
7951 | * action-set pointed from here are as follows: | |
7952 | * 00h: ACTION_NULL | |
7953 | * 01h: ACTION_MAC_TTL, only TTL configuration is supported. | |
7954 | * 03h: ACTION_TRAP | |
7955 | * 06h: ACTION_QOS | |
7956 | * 08h: ACTION_POLICING_MONITORING | |
7957 | * 10h: ACTION_ROUTER_MC | |
7958 | * Access: RW | |
7959 | */ | |
7960 | MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, | |
7961 | MLXSW_REG_FLEX_ACTION_SET_LEN); | |
7962 | ||
7963 | static inline void | |
a82b1b8f YM |
7964 | mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, |
7965 | u16 virtual_router, | |
7966 | enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, | |
7967 | const char *flex_action_set) | |
2e654e33 YG |
7968 | { |
7969 | MLXSW_REG_ZERO(rmft2, payload); | |
7970 | mlxsw_reg_rmft2_v_set(payload, v); | |
2e654e33 YG |
7971 | mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); |
7972 | mlxsw_reg_rmft2_offset_set(payload, offset); | |
7973 | mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); | |
7974 | mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); | |
7975 | mlxsw_reg_rmft2_irif_set(payload, irif); | |
a82b1b8f YM |
7976 | if (flex_action_set) |
7977 | mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, | |
7978 | flex_action_set); | |
7979 | } | |
7980 | ||
7981 | static inline void | |
7982 | mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, | |
7983 | enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, | |
7984 | u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, | |
7985 | const char *flexible_action_set) | |
7986 | { | |
7987 | mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, | |
7988 | irif_mask, irif, flexible_action_set); | |
7989 | mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); | |
2e654e33 YG |
7990 | mlxsw_reg_rmft2_dip4_set(payload, dip4); |
7991 | mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); | |
7992 | mlxsw_reg_rmft2_sip4_set(payload, sip4); | |
7993 | mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); | |
a82b1b8f YM |
7994 | } |
7995 | ||
7996 | static inline void | |
7997 | mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, | |
7998 | enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, | |
7999 | struct in6_addr dip6, struct in6_addr dip6_mask, | |
8000 | struct in6_addr sip6, struct in6_addr sip6_mask, | |
8001 | const char *flexible_action_set) | |
8002 | { | |
8003 | mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, | |
8004 | irif_mask, irif, flexible_action_set); | |
8005 | mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); | |
8006 | mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); | |
8007 | mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); | |
8008 | mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); | |
8009 | mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); | |
2e654e33 YG |
8010 | } |
8011 | ||
5246f2e2 JP |
8012 | /* MFCR - Management Fan Control Register |
8013 | * -------------------------------------- | |
8014 | * This register controls the settings of the Fan Speed PWM mechanism. | |
8015 | */ | |
8016 | #define MLXSW_REG_MFCR_ID 0x9001 | |
8017 | #define MLXSW_REG_MFCR_LEN 0x08 | |
8018 | ||
21978dcf | 8019 | MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); |
5246f2e2 JP |
8020 | |
8021 | enum mlxsw_reg_mfcr_pwm_frequency { | |
8022 | MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, | |
8023 | MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, | |
8024 | MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, | |
8025 | MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, | |
8026 | MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, | |
8027 | MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, | |
8028 | MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, | |
8029 | MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, | |
8030 | }; | |
8031 | ||
8032 | /* reg_mfcr_pwm_frequency | |
8033 | * Controls the frequency of the PWM signal. | |
8034 | * Access: RW | |
8035 | */ | |
f7ad3d4b | 8036 | MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); |
5246f2e2 JP |
8037 | |
8038 | #define MLXSW_MFCR_TACHOS_MAX 10 | |
8039 | ||
8040 | /* reg_mfcr_tacho_active | |
8041 | * Indicates which of the tachometer is active (bit per tachometer). | |
8042 | * Access: RO | |
8043 | */ | |
8044 | MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); | |
8045 | ||
8046 | #define MLXSW_MFCR_PWMS_MAX 5 | |
8047 | ||
8048 | /* reg_mfcr_pwm_active | |
8049 | * Indicates which of the PWM control is active (bit per PWM). | |
8050 | * Access: RO | |
8051 | */ | |
8052 | MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); | |
8053 | ||
8054 | static inline void | |
8055 | mlxsw_reg_mfcr_pack(char *payload, | |
8056 | enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) | |
8057 | { | |
8058 | MLXSW_REG_ZERO(mfcr, payload); | |
8059 | mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); | |
8060 | } | |
8061 | ||
8062 | static inline void | |
8063 | mlxsw_reg_mfcr_unpack(char *payload, | |
8064 | enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, | |
8065 | u16 *p_tacho_active, u8 *p_pwm_active) | |
8066 | { | |
8067 | *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); | |
8068 | *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); | |
8069 | *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); | |
8070 | } | |
8071 | ||
8072 | /* MFSC - Management Fan Speed Control Register | |
8073 | * -------------------------------------------- | |
8074 | * This register controls the settings of the Fan Speed PWM mechanism. | |
8075 | */ | |
8076 | #define MLXSW_REG_MFSC_ID 0x9002 | |
8077 | #define MLXSW_REG_MFSC_LEN 0x08 | |
8078 | ||
21978dcf | 8079 | MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); |
5246f2e2 JP |
8080 | |
8081 | /* reg_mfsc_pwm | |
8082 | * Fan pwm to control / monitor. | |
8083 | * Access: Index | |
8084 | */ | |
8085 | MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); | |
8086 | ||
8087 | /* reg_mfsc_pwm_duty_cycle | |
8088 | * Controls the duty cycle of the PWM. Value range from 0..255 to | |
8089 | * represent duty cycle of 0%...100%. | |
8090 | * Access: RW | |
8091 | */ | |
8092 | MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); | |
8093 | ||
8094 | static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, | |
8095 | u8 pwm_duty_cycle) | |
8096 | { | |
8097 | MLXSW_REG_ZERO(mfsc, payload); | |
8098 | mlxsw_reg_mfsc_pwm_set(payload, pwm); | |
8099 | mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); | |
8100 | } | |
8101 | ||
8102 | /* MFSM - Management Fan Speed Measurement | |
8103 | * --------------------------------------- | |
8104 | * This register controls the settings of the Tacho measurements and | |
8105 | * enables reading the Tachometer measurements. | |
8106 | */ | |
8107 | #define MLXSW_REG_MFSM_ID 0x9003 | |
8108 | #define MLXSW_REG_MFSM_LEN 0x08 | |
8109 | ||
21978dcf | 8110 | MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); |
5246f2e2 JP |
8111 | |
8112 | /* reg_mfsm_tacho | |
8113 | * Fan tachometer index. | |
8114 | * Access: Index | |
8115 | */ | |
8116 | MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); | |
8117 | ||
8118 | /* reg_mfsm_rpm | |
8119 | * Fan speed (round per minute). | |
8120 | * Access: RO | |
8121 | */ | |
8122 | MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); | |
8123 | ||
8124 | static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) | |
8125 | { | |
8126 | MLXSW_REG_ZERO(mfsm, payload); | |
8127 | mlxsw_reg_mfsm_tacho_set(payload, tacho); | |
8128 | } | |
8129 | ||
55c63aaa JP |
8130 | /* MFSL - Management Fan Speed Limit Register |
8131 | * ------------------------------------------ | |
8132 | * The Fan Speed Limit register is used to configure the fan speed | |
8133 | * event / interrupt notification mechanism. Fan speed threshold are | |
8134 | * defined for both under-speed and over-speed. | |
8135 | */ | |
8136 | #define MLXSW_REG_MFSL_ID 0x9004 | |
8137 | #define MLXSW_REG_MFSL_LEN 0x0C | |
8138 | ||
8139 | MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); | |
8140 | ||
8141 | /* reg_mfsl_tacho | |
8142 | * Fan tachometer index. | |
8143 | * Access: Index | |
8144 | */ | |
8145 | MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); | |
8146 | ||
8147 | /* reg_mfsl_tach_min | |
8148 | * Tachometer minimum value (minimum RPM). | |
8149 | * Access: RW | |
8150 | */ | |
8151 | MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); | |
8152 | ||
8153 | /* reg_mfsl_tach_max | |
8154 | * Tachometer maximum value (maximum RPM). | |
8155 | * Access: RW | |
8156 | */ | |
8157 | MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); | |
8158 | ||
8159 | static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, | |
8160 | u16 tach_min, u16 tach_max) | |
8161 | { | |
8162 | MLXSW_REG_ZERO(mfsl, payload); | |
8163 | mlxsw_reg_mfsl_tacho_set(payload, tacho); | |
8164 | mlxsw_reg_mfsl_tach_min_set(payload, tach_min); | |
8165 | mlxsw_reg_mfsl_tach_max_set(payload, tach_max); | |
8166 | } | |
8167 | ||
8168 | static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, | |
8169 | u16 *p_tach_min, u16 *p_tach_max) | |
8170 | { | |
8171 | if (p_tach_min) | |
8172 | *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); | |
8173 | ||
8174 | if (p_tach_max) | |
8175 | *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); | |
8176 | } | |
8177 | ||
3760c2b9 VP |
8178 | /* FORE - Fan Out of Range Event Register |
8179 | * -------------------------------------- | |
8180 | * This register reports the status of the controlled fans compared to the | |
8181 | * range defined by the MFSL register. | |
8182 | */ | |
8183 | #define MLXSW_REG_FORE_ID 0x9007 | |
8184 | #define MLXSW_REG_FORE_LEN 0x0C | |
8185 | ||
8186 | MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); | |
8187 | ||
8188 | /* fan_under_limit | |
8189 | * Fan speed is below the low limit defined in MFSL register. Each bit relates | |
8190 | * to a single tachometer and indicates the specific tachometer reading is | |
8191 | * below the threshold. | |
8192 | * Access: RO | |
8193 | */ | |
8194 | MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); | |
8195 | ||
8196 | static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, | |
8197 | bool *fault) | |
8198 | { | |
8199 | u16 limit; | |
8200 | ||
8201 | if (fault) { | |
8202 | limit = mlxsw_reg_fore_fan_under_limit_get(payload); | |
8203 | *fault = limit & BIT(tacho); | |
8204 | } | |
8205 | } | |
8206 | ||
85926f87 JP |
8207 | /* MTCAP - Management Temperature Capabilities |
8208 | * ------------------------------------------- | |
8209 | * This register exposes the capabilities of the device and | |
8210 | * system temperature sensing. | |
8211 | */ | |
8212 | #define MLXSW_REG_MTCAP_ID 0x9009 | |
8213 | #define MLXSW_REG_MTCAP_LEN 0x08 | |
8214 | ||
21978dcf | 8215 | MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); |
85926f87 JP |
8216 | |
8217 | /* reg_mtcap_sensor_count | |
8218 | * Number of sensors supported by the device. | |
8219 | * This includes the QSFP module sensors (if exists in the QSFP module). | |
8220 | * Access: RO | |
8221 | */ | |
8222 | MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); | |
8223 | ||
8224 | /* MTMP - Management Temperature | |
8225 | * ----------------------------- | |
8226 | * This register controls the settings of the temperature measurements | |
8227 | * and enables reading the temperature measurements. Note that temperature | |
8228 | * is in 0.125 degrees Celsius. | |
8229 | */ | |
8230 | #define MLXSW_REG_MTMP_ID 0x900A | |
8231 | #define MLXSW_REG_MTMP_LEN 0x20 | |
8232 | ||
21978dcf | 8233 | MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); |
85926f87 | 8234 | |
984aec75 | 8235 | #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 |
ae574678 | 8236 | #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 |
85926f87 JP |
8237 | /* reg_mtmp_sensor_index |
8238 | * Sensors index to access. | |
8239 | * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially | |
8240 | * (module 0 is mapped to sensor_index 64). | |
8241 | * Access: Index | |
8242 | */ | |
984aec75 | 8243 | MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); |
85926f87 JP |
8244 | |
8245 | /* Convert to milli degrees Celsius */ | |
f485cc36 VP |
8246 | #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ |
8247 | ((v_) >= 0) ? ((v_) * 125) : \ | |
8248 | ((s16)((GENMASK(15, 0) + (v_) + 1) \ | |
8249 | * 125)); }) | |
85926f87 JP |
8250 | |
8251 | /* reg_mtmp_temperature | |
8252 | * Temperature reading from the sensor. Reading is in 0.125 Celsius | |
8253 | * degrees units. | |
8254 | * Access: RO | |
8255 | */ | |
8256 | MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); | |
8257 | ||
8258 | /* reg_mtmp_mte | |
8259 | * Max Temperature Enable - enables measuring the max temperature on a sensor. | |
8260 | * Access: RW | |
8261 | */ | |
8262 | MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); | |
8263 | ||
8264 | /* reg_mtmp_mtr | |
8265 | * Max Temperature Reset - clears the value of the max temperature register. | |
8266 | * Access: WO | |
8267 | */ | |
8268 | MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); | |
8269 | ||
8270 | /* reg_mtmp_max_temperature | |
8271 | * The highest measured temperature from the sensor. | |
8272 | * When the bit mte is cleared, the field max_temperature is reserved. | |
8273 | * Access: RO | |
8274 | */ | |
8275 | MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); | |
8276 | ||
62b0e924 IS |
8277 | /* reg_mtmp_tee |
8278 | * Temperature Event Enable. | |
8279 | * 0 - Do not generate event | |
8280 | * 1 - Generate event | |
8281 | * 2 - Generate single event | |
8282 | * Access: RW | |
8283 | */ | |
8284 | MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); | |
8285 | ||
8286 | #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ | |
8287 | ||
8288 | /* reg_mtmp_temperature_threshold_hi | |
8289 | * High threshold for Temperature Warning Event. In 0.125 Celsius. | |
8290 | * Access: RW | |
8291 | */ | |
8292 | MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); | |
8293 | ||
8294 | /* reg_mtmp_temperature_threshold_lo | |
8295 | * Low threshold for Temperature Warning Event. In 0.125 Celsius. | |
8296 | * Access: RW | |
8297 | */ | |
8298 | MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); | |
8299 | ||
85926f87 JP |
8300 | #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 |
8301 | ||
8302 | /* reg_mtmp_sensor_name | |
8303 | * Sensor Name | |
8304 | * Access: RO | |
8305 | */ | |
8306 | MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); | |
8307 | ||
ae574678 | 8308 | static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, |
85926f87 JP |
8309 | bool max_temp_enable, |
8310 | bool max_temp_reset) | |
8311 | { | |
8312 | MLXSW_REG_ZERO(mtmp, payload); | |
8313 | mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); | |
8314 | mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); | |
8315 | mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); | |
62b0e924 IS |
8316 | mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, |
8317 | MLXSW_REG_MTMP_THRESH_HI); | |
85926f87 JP |
8318 | } |
8319 | ||
f485cc36 VP |
8320 | static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, |
8321 | int *p_max_temp, char *sensor_name) | |
85926f87 | 8322 | { |
f485cc36 | 8323 | s16 temp; |
85926f87 JP |
8324 | |
8325 | if (p_temp) { | |
8326 | temp = mlxsw_reg_mtmp_temperature_get(payload); | |
8327 | *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); | |
8328 | } | |
8329 | if (p_max_temp) { | |
acf35a4e | 8330 | temp = mlxsw_reg_mtmp_max_temperature_get(payload); |
85926f87 JP |
8331 | *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); |
8332 | } | |
8333 | if (sensor_name) | |
8334 | mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); | |
8335 | } | |
8336 | ||
5f28ef71 VP |
8337 | /* MTBR - Management Temperature Bulk Register |
8338 | * ------------------------------------------- | |
8339 | * This register is used for bulk temperature reading. | |
8340 | */ | |
8341 | #define MLXSW_REG_MTBR_ID 0x900F | |
8342 | #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ | |
8343 | #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ | |
8344 | #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ | |
8345 | #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ | |
8346 | MLXSW_REG_MTBR_REC_LEN * \ | |
8347 | MLXSW_REG_MTBR_REC_MAX_COUNT) | |
8348 | ||
8349 | MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); | |
8350 | ||
8351 | /* reg_mtbr_base_sensor_index | |
8352 | * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, | |
8353 | * 64-127 are mapped to the SFP+/QSFP modules sequentially). | |
8354 | * Access: Index | |
8355 | */ | |
984aec75 | 8356 | MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); |
5f28ef71 VP |
8357 | |
8358 | /* reg_mtbr_num_rec | |
8359 | * Request: Number of records to read | |
8360 | * Response: Number of records read | |
8361 | * See above description for more details. | |
8362 | * Range 1..255 | |
8363 | * Access: RW | |
8364 | */ | |
8365 | MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); | |
8366 | ||
8367 | /* reg_mtbr_rec_max_temp | |
8368 | * The highest measured temperature from the sensor. | |
8369 | * When the bit mte is cleared, the field max_temperature is reserved. | |
8370 | * Access: RO | |
8371 | */ | |
8372 | MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, | |
8373 | 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); | |
8374 | ||
8375 | /* reg_mtbr_rec_temp | |
8376 | * Temperature reading from the sensor. Reading is in 0..125 Celsius | |
8377 | * degrees units. | |
8378 | * Access: RO | |
8379 | */ | |
8380 | MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, | |
8381 | MLXSW_REG_MTBR_REC_LEN, 0x00, false); | |
8382 | ||
984aec75 | 8383 | static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, |
5f28ef71 VP |
8384 | u8 num_rec) |
8385 | { | |
8386 | MLXSW_REG_ZERO(mtbr, payload); | |
8387 | mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); | |
8388 | mlxsw_reg_mtbr_num_rec_set(payload, num_rec); | |
8389 | } | |
8390 | ||
8391 | /* Error codes from temperatute reading */ | |
8392 | enum mlxsw_reg_mtbr_temp_status { | |
8393 | MLXSW_REG_MTBR_NO_CONN = 0x8000, | |
8394 | MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, | |
8395 | MLXSW_REG_MTBR_INDEX_NA = 0x8002, | |
8396 | MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, | |
8397 | }; | |
8398 | ||
8399 | /* Base index for reading modules temperature */ | |
8400 | #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 | |
8401 | ||
8402 | static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, | |
8403 | u16 *p_temp, u16 *p_max_temp) | |
8404 | { | |
8405 | if (p_temp) | |
8406 | *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); | |
8407 | if (p_max_temp) | |
8408 | *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); | |
8409 | } | |
8410 | ||
7ca36994 AS |
8411 | /* MCIA - Management Cable Info Access |
8412 | * ----------------------------------- | |
8413 | * MCIA register is used to access the SFP+ and QSFP connector's EPROM. | |
8414 | */ | |
8415 | ||
8416 | #define MLXSW_REG_MCIA_ID 0x9014 | |
8417 | #define MLXSW_REG_MCIA_LEN 0x40 | |
8418 | ||
8419 | MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); | |
8420 | ||
8421 | /* reg_mcia_l | |
8422 | * Lock bit. Setting this bit will lock the access to the specific | |
8423 | * cable. Used for updating a full page in a cable EPROM. Any access | |
8424 | * other then subsequence writes will fail while the port is locked. | |
8425 | * Access: RW | |
8426 | */ | |
8427 | MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); | |
8428 | ||
8429 | /* reg_mcia_module | |
8430 | * Module number. | |
8431 | * Access: Index | |
8432 | */ | |
8433 | MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); | |
8434 | ||
8435 | /* reg_mcia_status | |
8436 | * Module status. | |
8437 | * Access: RO | |
8438 | */ | |
8439 | MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); | |
8440 | ||
8441 | /* reg_mcia_i2c_device_address | |
8442 | * I2C device address. | |
8443 | * Access: RW | |
8444 | */ | |
8445 | MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); | |
8446 | ||
8447 | /* reg_mcia_page_number | |
8448 | * Page number. | |
8449 | * Access: RW | |
8450 | */ | |
8451 | MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); | |
8452 | ||
8453 | /* reg_mcia_device_address | |
8454 | * Device address. | |
8455 | * Access: RW | |
8456 | */ | |
8457 | MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); | |
8458 | ||
8459 | /* reg_mcia_size | |
8460 | * Number of bytes to read/write (up to 48 bytes). | |
8461 | * Access: RW | |
8462 | */ | |
8463 | MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); | |
8464 | ||
d517ee7c | 8465 | #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 |
f366cd2a | 8466 | #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 |
d517ee7c VP |
8467 | #define MLXSW_REG_MCIA_EEPROM_SIZE 48 |
8468 | #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 | |
8469 | #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 | |
8470 | #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 | |
8471 | #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 | |
8472 | #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 | |
8473 | #define MLXSW_REG_MCIA_PAGE0_LO 0 | |
8474 | #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 | |
8475 | ||
8476 | enum mlxsw_reg_mcia_eeprom_module_info_rev_id { | |
8477 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, | |
8478 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, | |
8479 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, | |
8480 | }; | |
8481 | ||
8482 | enum mlxsw_reg_mcia_eeprom_module_info_id { | |
8483 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, | |
8484 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, | |
8485 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, | |
8486 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, | |
8487 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, | |
8488 | }; | |
8489 | ||
8490 | enum mlxsw_reg_mcia_eeprom_module_info { | |
8491 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, | |
8492 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, | |
8493 | MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, | |
8494 | }; | |
7ca36994 AS |
8495 | |
8496 | /* reg_mcia_eeprom | |
8497 | * Bytes to read/write. | |
8498 | * Access: RW | |
8499 | */ | |
d517ee7c | 8500 | MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); |
7ca36994 | 8501 | |
f366cd2a VP |
8502 | /* This is used to access the optional upper pages (1-3) in the QSFP+ |
8503 | * memory map. Page 1 is available on offset 256 through 383, page 2 - | |
8504 | * on offset 384 through 511, page 3 - on offset 512 through 639. | |
8505 | */ | |
8506 | #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ | |
8507 | MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ | |
8508 | MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) | |
8509 | ||
7ca36994 AS |
8510 | static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, |
8511 | u8 page_number, u16 device_addr, | |
8512 | u8 size, u8 i2c_device_addr) | |
8513 | { | |
8514 | MLXSW_REG_ZERO(mcia, payload); | |
8515 | mlxsw_reg_mcia_module_set(payload, module); | |
8516 | mlxsw_reg_mcia_l_set(payload, lock); | |
8517 | mlxsw_reg_mcia_page_number_set(payload, page_number); | |
8518 | mlxsw_reg_mcia_device_address_set(payload, device_addr); | |
8519 | mlxsw_reg_mcia_size_set(payload, size); | |
8520 | mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); | |
8521 | } | |
8522 | ||
43a46856 YG |
8523 | /* MPAT - Monitoring Port Analyzer Table |
8524 | * ------------------------------------- | |
8525 | * MPAT Register is used to query and configure the Switch PortAnalyzer Table. | |
8526 | * For an enabled analyzer, all fields except e (enable) cannot be modified. | |
8527 | */ | |
8528 | #define MLXSW_REG_MPAT_ID 0x901A | |
8529 | #define MLXSW_REG_MPAT_LEN 0x78 | |
8530 | ||
21978dcf | 8531 | MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); |
43a46856 YG |
8532 | |
8533 | /* reg_mpat_pa_id | |
8534 | * Port Analyzer ID. | |
8535 | * Access: Index | |
8536 | */ | |
8537 | MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); | |
8538 | ||
8539 | /* reg_mpat_system_port | |
8540 | * A unique port identifier for the final destination of the packet. | |
8541 | * Access: RW | |
8542 | */ | |
8543 | MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); | |
8544 | ||
8545 | /* reg_mpat_e | |
8546 | * Enable. Indicating the Port Analyzer is enabled. | |
8547 | * Access: RW | |
8548 | */ | |
8549 | MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); | |
8550 | ||
8551 | /* reg_mpat_qos | |
8552 | * Quality Of Service Mode. | |
8553 | * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation | |
8554 | * PCP, DEI, DSCP or VL) are configured. | |
8555 | * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the | |
8556 | * same as in the original packet that has triggered the mirroring. For | |
8557 | * SPAN also the pcp,dei are maintained. | |
8558 | * Access: RW | |
8559 | */ | |
8560 | MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); | |
8561 | ||
23019054 YG |
8562 | /* reg_mpat_be |
8563 | * Best effort mode. Indicates mirroring traffic should not cause packet | |
8564 | * drop or back pressure, but will discard the mirrored packets. Mirrored | |
8565 | * packets will be forwarded on a best effort manner. | |
8566 | * 0: Do not discard mirrored packets | |
8567 | * 1: Discard mirrored packets if causing congestion | |
8568 | * Access: RW | |
8569 | */ | |
8570 | MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); | |
8571 | ||
0d6cd3fc PM |
8572 | enum mlxsw_reg_mpat_span_type { |
8573 | /* Local SPAN Ethernet. | |
8574 | * The original packet is not encapsulated. | |
8575 | */ | |
8576 | MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, | |
8577 | ||
41947662 PM |
8578 | /* Remote SPAN Ethernet VLAN. |
8579 | * The packet is forwarded to the monitoring port on the monitoring | |
8580 | * VLAN. | |
8581 | */ | |
8582 | MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, | |
8583 | ||
0d6cd3fc PM |
8584 | /* Encapsulated Remote SPAN Ethernet L3 GRE. |
8585 | * The packet is encapsulated with GRE header. | |
8586 | */ | |
8587 | MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, | |
8588 | }; | |
8589 | ||
8590 | /* reg_mpat_span_type | |
8591 | * SPAN type. | |
8592 | * Access: RW | |
8593 | */ | |
8594 | MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); | |
8595 | ||
8596 | /* Remote SPAN - Ethernet VLAN | |
8597 | * - - - - - - - - - - - - - - | |
8598 | */ | |
8599 | ||
8600 | /* reg_mpat_eth_rspan_vid | |
8601 | * Encapsulation header VLAN ID. | |
8602 | * Access: RW | |
8603 | */ | |
8604 | MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); | |
8605 | ||
8606 | /* Encapsulated Remote SPAN - Ethernet L2 | |
8607 | * - - - - - - - - - - - - - - - - - - - | |
8608 | */ | |
8609 | ||
8610 | enum mlxsw_reg_mpat_eth_rspan_version { | |
8611 | MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, | |
8612 | }; | |
8613 | ||
8614 | /* reg_mpat_eth_rspan_version | |
8615 | * RSPAN mirror header version. | |
8616 | * Access: RW | |
8617 | */ | |
8618 | MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); | |
8619 | ||
8620 | /* reg_mpat_eth_rspan_mac | |
8621 | * Destination MAC address. | |
8622 | * Access: RW | |
8623 | */ | |
8624 | MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); | |
8625 | ||
8626 | /* reg_mpat_eth_rspan_tp | |
8627 | * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. | |
8628 | * Access: RW | |
8629 | */ | |
8630 | MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); | |
8631 | ||
8632 | /* Encapsulated Remote SPAN - Ethernet L3 | |
8633 | * - - - - - - - - - - - - - - - - - - - | |
8634 | */ | |
8635 | ||
8636 | enum mlxsw_reg_mpat_eth_rspan_protocol { | |
8637 | MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, | |
8638 | MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, | |
8639 | }; | |
8640 | ||
8641 | /* reg_mpat_eth_rspan_protocol | |
8642 | * SPAN encapsulation protocol. | |
8643 | * Access: RW | |
8644 | */ | |
8645 | MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); | |
8646 | ||
8647 | /* reg_mpat_eth_rspan_ttl | |
8648 | * Encapsulation header Time-to-Live/HopLimit. | |
8649 | * Access: RW | |
8650 | */ | |
8651 | MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); | |
8652 | ||
8653 | /* reg_mpat_eth_rspan_smac | |
8654 | * Source MAC address | |
8655 | * Access: RW | |
8656 | */ | |
8657 | MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); | |
8658 | ||
8659 | /* reg_mpat_eth_rspan_dip* | |
8660 | * Destination IP address. The IP version is configured by protocol. | |
8661 | * Access: RW | |
8662 | */ | |
8663 | MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); | |
8664 | MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); | |
8665 | ||
8666 | /* reg_mpat_eth_rspan_sip* | |
8667 | * Source IP address. The IP version is configured by protocol. | |
8668 | * Access: RW | |
8669 | */ | |
8670 | MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); | |
8671 | MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); | |
8672 | ||
43a46856 | 8673 | static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, |
1da93eb4 PM |
8674 | u16 system_port, bool e, |
8675 | enum mlxsw_reg_mpat_span_type span_type) | |
43a46856 YG |
8676 | { |
8677 | MLXSW_REG_ZERO(mpat, payload); | |
8678 | mlxsw_reg_mpat_pa_id_set(payload, pa_id); | |
8679 | mlxsw_reg_mpat_system_port_set(payload, system_port); | |
8680 | mlxsw_reg_mpat_e_set(payload, e); | |
8681 | mlxsw_reg_mpat_qos_set(payload, 1); | |
23019054 | 8682 | mlxsw_reg_mpat_be_set(payload, 1); |
1da93eb4 | 8683 | mlxsw_reg_mpat_span_type_set(payload, span_type); |
23019054 YG |
8684 | } |
8685 | ||
0d6cd3fc PM |
8686 | static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) |
8687 | { | |
8688 | mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); | |
8689 | } | |
8690 | ||
8691 | static inline void | |
8692 | mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, | |
8693 | enum mlxsw_reg_mpat_eth_rspan_version version, | |
8694 | const char *mac, | |
8695 | bool tp) | |
8696 | { | |
8697 | mlxsw_reg_mpat_eth_rspan_version_set(payload, version); | |
8698 | mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); | |
8699 | mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); | |
8700 | } | |
8701 | ||
8702 | static inline void | |
8703 | mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, | |
8704 | const char *smac, | |
8705 | u32 sip, u32 dip) | |
8706 | { | |
8707 | mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); | |
8708 | mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); | |
8709 | mlxsw_reg_mpat_eth_rspan_protocol_set(payload, | |
8710 | MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); | |
8711 | mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); | |
8712 | mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); | |
8713 | } | |
8714 | ||
8715 | static inline void | |
8716 | mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, | |
8717 | const char *smac, | |
8718 | struct in6_addr sip, struct in6_addr dip) | |
8719 | { | |
8720 | mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); | |
8721 | mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); | |
8722 | mlxsw_reg_mpat_eth_rspan_protocol_set(payload, | |
8723 | MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); | |
8724 | mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); | |
8725 | mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); | |
8726 | } | |
8727 | ||
23019054 YG |
8728 | /* MPAR - Monitoring Port Analyzer Register |
8729 | * ---------------------------------------- | |
8730 | * MPAR register is used to query and configure the port analyzer port mirroring | |
8731 | * properties. | |
8732 | */ | |
8733 | #define MLXSW_REG_MPAR_ID 0x901B | |
5075066a | 8734 | #define MLXSW_REG_MPAR_LEN 0x0C |
23019054 | 8735 | |
21978dcf | 8736 | MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); |
23019054 YG |
8737 | |
8738 | /* reg_mpar_local_port | |
8739 | * The local port to mirror the packets from. | |
8740 | * Access: Index | |
8741 | */ | |
8742 | MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); | |
8743 | ||
8744 | enum mlxsw_reg_mpar_i_e { | |
8745 | MLXSW_REG_MPAR_TYPE_EGRESS, | |
8746 | MLXSW_REG_MPAR_TYPE_INGRESS, | |
8747 | }; | |
8748 | ||
8749 | /* reg_mpar_i_e | |
8750 | * Ingress/Egress | |
8751 | * Access: Index | |
8752 | */ | |
8753 | MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); | |
8754 | ||
8755 | /* reg_mpar_enable | |
8756 | * Enable mirroring | |
8757 | * By default, port mirroring is disabled for all ports. | |
8758 | * Access: RW | |
8759 | */ | |
8760 | MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); | |
8761 | ||
8762 | /* reg_mpar_pa_id | |
8763 | * Port Analyzer ID. | |
8764 | * Access: RW | |
8765 | */ | |
8766 | MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); | |
8767 | ||
8768 | static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, | |
8769 | enum mlxsw_reg_mpar_i_e i_e, | |
8770 | bool enable, u8 pa_id) | |
8771 | { | |
8772 | MLXSW_REG_ZERO(mpar, payload); | |
8773 | mlxsw_reg_mpar_local_port_set(payload, local_port); | |
8774 | mlxsw_reg_mpar_enable_set(payload, enable); | |
8775 | mlxsw_reg_mpar_i_e_set(payload, i_e); | |
8776 | mlxsw_reg_mpar_pa_id_set(payload, pa_id); | |
43a46856 YG |
8777 | } |
8778 | ||
8d77d4bf ST |
8779 | /* MGIR - Management General Information Register |
8780 | * ---------------------------------------------- | |
8781 | * MGIR register allows software to query the hardware and firmware general | |
8782 | * information. | |
8783 | */ | |
8784 | #define MLXSW_REG_MGIR_ID 0x9020 | |
8785 | #define MLXSW_REG_MGIR_LEN 0x9C | |
8786 | ||
8787 | MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); | |
8788 | ||
8789 | /* reg_mgir_hw_info_device_hw_revision | |
8790 | * Access: RO | |
8791 | */ | |
8792 | MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); | |
8793 | ||
8794 | #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 | |
8795 | ||
8796 | /* reg_mgir_fw_info_psid | |
8797 | * PSID (ASCII string). | |
8798 | * Access: RO | |
8799 | */ | |
8800 | MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); | |
8801 | ||
8802 | /* reg_mgir_fw_info_extended_major | |
8803 | * Access: RO | |
8804 | */ | |
8805 | MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); | |
8806 | ||
8807 | /* reg_mgir_fw_info_extended_minor | |
8808 | * Access: RO | |
8809 | */ | |
8810 | MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); | |
8811 | ||
8812 | /* reg_mgir_fw_info_extended_sub_minor | |
8813 | * Access: RO | |
8814 | */ | |
8815 | MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); | |
8816 | ||
8817 | static inline void mlxsw_reg_mgir_pack(char *payload) | |
8818 | { | |
8819 | MLXSW_REG_ZERO(mgir, payload); | |
8820 | } | |
8821 | ||
8822 | static inline void | |
8823 | mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, | |
8824 | u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) | |
8825 | { | |
8826 | *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); | |
8827 | mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); | |
8828 | *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); | |
8829 | *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); | |
8830 | *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); | |
8831 | } | |
8832 | ||
12b003b2 JP |
8833 | /* MRSR - Management Reset and Shutdown Register |
8834 | * --------------------------------------------- | |
8835 | * MRSR register is used to reset or shutdown the switch or | |
8836 | * the entire system (when applicable). | |
8837 | */ | |
8838 | #define MLXSW_REG_MRSR_ID 0x9023 | |
8839 | #define MLXSW_REG_MRSR_LEN 0x08 | |
8840 | ||
8841 | MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); | |
8842 | ||
8843 | /* reg_mrsr_command | |
8844 | * Reset/shutdown command | |
8845 | * 0 - do nothing | |
8846 | * 1 - software reset | |
8847 | * Access: WO | |
8848 | */ | |
8849 | MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); | |
8850 | ||
8851 | static inline void mlxsw_reg_mrsr_pack(char *payload) | |
8852 | { | |
8853 | MLXSW_REG_ZERO(mrsr, payload); | |
8854 | mlxsw_reg_mrsr_command_set(payload, 1); | |
8855 | } | |
8856 | ||
3161c159 IS |
8857 | /* MLCR - Management LED Control Register |
8858 | * -------------------------------------- | |
8859 | * Controls the system LEDs. | |
8860 | */ | |
8861 | #define MLXSW_REG_MLCR_ID 0x902B | |
8862 | #define MLXSW_REG_MLCR_LEN 0x0C | |
8863 | ||
21978dcf | 8864 | MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); |
3161c159 IS |
8865 | |
8866 | /* reg_mlcr_local_port | |
8867 | * Local port number. | |
8868 | * Access: RW | |
8869 | */ | |
8870 | MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); | |
8871 | ||
8872 | #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF | |
8873 | ||
8874 | /* reg_mlcr_beacon_duration | |
8875 | * Duration of the beacon to be active, in seconds. | |
8876 | * 0x0 - Will turn off the beacon. | |
8877 | * 0xFFFF - Will turn on the beacon until explicitly turned off. | |
8878 | * Access: RW | |
8879 | */ | |
8880 | MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); | |
8881 | ||
8882 | /* reg_mlcr_beacon_remain | |
8883 | * Remaining duration of the beacon, in seconds. | |
8884 | * 0xFFFF indicates an infinite amount of time. | |
8885 | * Access: RO | |
8886 | */ | |
8887 | MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); | |
8888 | ||
8889 | static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, | |
8890 | bool active) | |
8891 | { | |
8892 | MLXSW_REG_ZERO(mlcr, payload); | |
8893 | mlxsw_reg_mlcr_local_port_set(payload, local_port); | |
8894 | mlxsw_reg_mlcr_beacon_duration_set(payload, active ? | |
8895 | MLXSW_REG_MLCR_DURATION_MAX : 0); | |
8896 | } | |
8897 | ||
1078645a ST |
8898 | /* MTPPS - Management Pulse Per Second Register |
8899 | * -------------------------------------------- | |
8900 | * This register provides the device PPS capabilities, configure the PPS in and | |
8901 | * out modules and holds the PPS in time stamp. | |
8902 | */ | |
8903 | #define MLXSW_REG_MTPPS_ID 0x9053 | |
8904 | #define MLXSW_REG_MTPPS_LEN 0x3C | |
8905 | ||
8906 | MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); | |
8907 | ||
8908 | /* reg_mtpps_enable | |
8909 | * Enables the PPS functionality the specific pin. | |
8910 | * A boolean variable. | |
8911 | * Access: RW | |
8912 | */ | |
8913 | MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); | |
8914 | ||
8915 | enum mlxsw_reg_mtpps_pin_mode { | |
8916 | MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, | |
8917 | }; | |
8918 | ||
8919 | /* reg_mtpps_pin_mode | |
8920 | * Pin mode to be used. The mode must comply with the supported modes of the | |
8921 | * requested pin. | |
8922 | * Access: RW | |
8923 | */ | |
8924 | MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); | |
8925 | ||
8926 | #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 | |
8927 | ||
8928 | /* reg_mtpps_pin | |
8929 | * Pin to be configured or queried out of the supported pins. | |
8930 | * Access: Index | |
8931 | */ | |
8932 | MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); | |
8933 | ||
8934 | /* reg_mtpps_time_stamp | |
8935 | * When pin_mode = pps_in, the latched device time when it was triggered from | |
8936 | * the external GPIO pin. | |
8937 | * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target | |
8938 | * time to generate next output signal. | |
8939 | * Time is in units of device clock. | |
8940 | * Access: RW | |
8941 | */ | |
8942 | MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); | |
8943 | ||
8944 | static inline void | |
8945 | mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) | |
8946 | { | |
8947 | MLXSW_REG_ZERO(mtpps, payload); | |
8948 | mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); | |
8949 | mlxsw_reg_mtpps_pin_mode_set(payload, | |
8950 | MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); | |
8951 | mlxsw_reg_mtpps_enable_set(payload, true); | |
8952 | mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); | |
8953 | } | |
8954 | ||
55a8b001 ST |
8955 | /* MTUTC - Management UTC Register |
8956 | * ------------------------------- | |
8957 | * Configures the HW UTC counter. | |
8958 | */ | |
8959 | #define MLXSW_REG_MTUTC_ID 0x9055 | |
8960 | #define MLXSW_REG_MTUTC_LEN 0x1C | |
8961 | ||
8962 | MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); | |
8963 | ||
8964 | enum mlxsw_reg_mtutc_operation { | |
8965 | MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, | |
8966 | MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, | |
8967 | }; | |
8968 | ||
8969 | /* reg_mtutc_operation | |
8970 | * Operation. | |
8971 | * Access: OP | |
8972 | */ | |
8973 | MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); | |
8974 | ||
8975 | /* reg_mtutc_freq_adjustment | |
8976 | * Frequency adjustment: Every PPS the HW frequency will be | |
8977 | * adjusted by this value. Units of HW clock, where HW counts | |
8978 | * 10^9 HW clocks for 1 HW second. | |
8979 | * Access: RW | |
8980 | */ | |
8981 | MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); | |
8982 | ||
8983 | /* reg_mtutc_utc_sec | |
8984 | * UTC seconds. | |
8985 | * Access: WO | |
8986 | */ | |
8987 | MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); | |
8988 | ||
8989 | static inline void | |
8990 | mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, | |
8991 | u32 freq_adj, u32 utc_sec) | |
8992 | { | |
8993 | MLXSW_REG_ZERO(mtutc, payload); | |
8994 | mlxsw_reg_mtutc_operation_set(payload, oper); | |
8995 | mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); | |
8996 | mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); | |
8997 | } | |
8998 | ||
4f2402d4 YG |
8999 | /* MCQI - Management Component Query Information |
9000 | * --------------------------------------------- | |
9001 | * This register allows querying information about firmware components. | |
9002 | */ | |
9003 | #define MLXSW_REG_MCQI_ID 0x9061 | |
9004 | #define MLXSW_REG_MCQI_BASE_LEN 0x18 | |
9005 | #define MLXSW_REG_MCQI_CAP_LEN 0x14 | |
9006 | #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) | |
9007 | ||
9008 | MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); | |
9009 | ||
9010 | /* reg_mcqi_component_index | |
9011 | * Index of the accessed component. | |
9012 | * Access: Index | |
9013 | */ | |
9014 | MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); | |
9015 | ||
9016 | enum mlxfw_reg_mcqi_info_type { | |
9017 | MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, | |
9018 | }; | |
9019 | ||
9020 | /* reg_mcqi_info_type | |
9021 | * Component properties set. | |
9022 | * Access: RW | |
9023 | */ | |
9024 | MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); | |
9025 | ||
9026 | /* reg_mcqi_offset | |
9027 | * The requested/returned data offset from the section start, given in bytes. | |
9028 | * Must be DWORD aligned. | |
9029 | * Access: RW | |
9030 | */ | |
9031 | MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); | |
9032 | ||
9033 | /* reg_mcqi_data_size | |
9034 | * The requested/returned data size, given in bytes. If data_size is not DWORD | |
9035 | * aligned, the last bytes are zero padded. | |
9036 | * Access: RW | |
9037 | */ | |
9038 | MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); | |
9039 | ||
9040 | /* reg_mcqi_cap_max_component_size | |
9041 | * Maximum size for this component, given in bytes. | |
9042 | * Access: RO | |
9043 | */ | |
9044 | MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); | |
9045 | ||
9046 | /* reg_mcqi_cap_log_mcda_word_size | |
9047 | * Log 2 of the access word size in bytes. Read and write access must be aligned | |
9048 | * to the word size. Write access must be done for an integer number of words. | |
9049 | * Access: RO | |
9050 | */ | |
9051 | MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); | |
9052 | ||
9053 | /* reg_mcqi_cap_mcda_max_write_size | |
9054 | * Maximal write size for MCDA register | |
9055 | * Access: RO | |
9056 | */ | |
9057 | MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); | |
9058 | ||
9059 | static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) | |
9060 | { | |
9061 | MLXSW_REG_ZERO(mcqi, payload); | |
9062 | mlxsw_reg_mcqi_component_index_set(payload, component_index); | |
9063 | mlxsw_reg_mcqi_info_type_set(payload, | |
9064 | MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); | |
9065 | mlxsw_reg_mcqi_offset_set(payload, 0); | |
9066 | mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); | |
9067 | } | |
9068 | ||
9069 | static inline void mlxsw_reg_mcqi_unpack(char *payload, | |
9070 | u32 *p_cap_max_component_size, | |
9071 | u8 *p_cap_log_mcda_word_size, | |
9072 | u16 *p_cap_mcda_max_write_size) | |
9073 | { | |
9074 | *p_cap_max_component_size = | |
9075 | mlxsw_reg_mcqi_cap_max_component_size_get(payload); | |
9076 | *p_cap_log_mcda_word_size = | |
9077 | mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); | |
9078 | *p_cap_mcda_max_write_size = | |
9079 | mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); | |
9080 | } | |
9081 | ||
191839de YG |
9082 | /* MCC - Management Component Control |
9083 | * ---------------------------------- | |
9084 | * Controls the firmware component and updates the FSM. | |
9085 | */ | |
9086 | #define MLXSW_REG_MCC_ID 0x9062 | |
9087 | #define MLXSW_REG_MCC_LEN 0x1C | |
9088 | ||
9089 | MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); | |
9090 | ||
9091 | enum mlxsw_reg_mcc_instruction { | |
9092 | MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, | |
9093 | MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, | |
9094 | MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, | |
9095 | MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, | |
9096 | MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, | |
9097 | MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, | |
9098 | }; | |
9099 | ||
9100 | /* reg_mcc_instruction | |
9101 | * Command to be executed by the FSM. | |
9102 | * Applicable for write operation only. | |
9103 | * Access: RW | |
9104 | */ | |
9105 | MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); | |
9106 | ||
9107 | /* reg_mcc_component_index | |
9108 | * Index of the accessed component. Applicable only for commands that | |
9109 | * refer to components. Otherwise, this field is reserved. | |
9110 | * Access: Index | |
9111 | */ | |
9112 | MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); | |
9113 | ||
9114 | /* reg_mcc_update_handle | |
9115 | * Token representing the current flow executed by the FSM. | |
9116 | * Access: WO | |
9117 | */ | |
9118 | MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); | |
9119 | ||
9120 | /* reg_mcc_error_code | |
9121 | * Indicates the successful completion of the instruction, or the reason it | |
9122 | * failed | |
9123 | * Access: RO | |
9124 | */ | |
9125 | MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); | |
9126 | ||
9127 | /* reg_mcc_control_state | |
9128 | * Current FSM state | |
9129 | * Access: RO | |
9130 | */ | |
9131 | MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); | |
9132 | ||
9133 | /* reg_mcc_component_size | |
9134 | * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying | |
9135 | * the size may shorten the update time. Value 0x0 means that size is | |
9136 | * unspecified. | |
9137 | * Access: WO | |
9138 | */ | |
9139 | MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); | |
9140 | ||
9141 | static inline void mlxsw_reg_mcc_pack(char *payload, | |
9142 | enum mlxsw_reg_mcc_instruction instr, | |
9143 | u16 component_index, u32 update_handle, | |
9144 | u32 component_size) | |
9145 | { | |
9146 | MLXSW_REG_ZERO(mcc, payload); | |
9147 | mlxsw_reg_mcc_instruction_set(payload, instr); | |
9148 | mlxsw_reg_mcc_component_index_set(payload, component_index); | |
9149 | mlxsw_reg_mcc_update_handle_set(payload, update_handle); | |
9150 | mlxsw_reg_mcc_component_size_set(payload, component_size); | |
9151 | } | |
9152 | ||
9153 | static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, | |
9154 | u8 *p_error_code, u8 *p_control_state) | |
9155 | { | |
9156 | if (p_update_handle) | |
9157 | *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); | |
9158 | if (p_error_code) | |
9159 | *p_error_code = mlxsw_reg_mcc_error_code_get(payload); | |
9160 | if (p_control_state) | |
9161 | *p_control_state = mlxsw_reg_mcc_control_state_get(payload); | |
9162 | } | |
9163 | ||
4625d59d YG |
9164 | /* MCDA - Management Component Data Access |
9165 | * --------------------------------------- | |
9166 | * This register allows reading and writing a firmware component. | |
9167 | */ | |
9168 | #define MLXSW_REG_MCDA_ID 0x9063 | |
9169 | #define MLXSW_REG_MCDA_BASE_LEN 0x10 | |
9170 | #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 | |
9171 | #define MLXSW_REG_MCDA_LEN \ | |
9172 | (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) | |
9173 | ||
9174 | MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); | |
9175 | ||
9176 | /* reg_mcda_update_handle | |
9177 | * Token representing the current flow executed by the FSM. | |
9178 | * Access: RW | |
9179 | */ | |
9180 | MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); | |
9181 | ||
9182 | /* reg_mcda_offset | |
9183 | * Offset of accessed address relative to component start. Accesses must be in | |
9184 | * accordance to log_mcda_word_size in MCQI reg. | |
9185 | * Access: RW | |
9186 | */ | |
9187 | MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); | |
9188 | ||
9189 | /* reg_mcda_size | |
9190 | * Size of the data accessed, given in bytes. | |
9191 | * Access: RW | |
9192 | */ | |
9193 | MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); | |
9194 | ||
9195 | /* reg_mcda_data | |
9196 | * Data block accessed. | |
9197 | * Access: RW | |
9198 | */ | |
9199 | MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); | |
9200 | ||
9201 | static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, | |
9202 | u32 offset, u16 size, u8 *data) | |
9203 | { | |
9204 | int i; | |
9205 | ||
9206 | MLXSW_REG_ZERO(mcda, payload); | |
9207 | mlxsw_reg_mcda_update_handle_set(payload, update_handle); | |
9208 | mlxsw_reg_mcda_offset_set(payload, offset); | |
9209 | mlxsw_reg_mcda_size_set(payload, size); | |
9210 | ||
9211 | for (i = 0; i < size / 4; i++) | |
9212 | mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); | |
9213 | } | |
9214 | ||
0677d682 YG |
9215 | /* MPSC - Monitoring Packet Sampling Configuration Register |
9216 | * -------------------------------------------------------- | |
9217 | * MPSC Register is used to configure the Packet Sampling mechanism. | |
9218 | */ | |
9219 | #define MLXSW_REG_MPSC_ID 0x9080 | |
9220 | #define MLXSW_REG_MPSC_LEN 0x1C | |
9221 | ||
9222 | MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); | |
9223 | ||
9224 | /* reg_mpsc_local_port | |
9225 | * Local port number | |
9226 | * Not supported for CPU port | |
9227 | * Access: Index | |
9228 | */ | |
9229 | MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); | |
9230 | ||
9231 | /* reg_mpsc_e | |
9232 | * Enable sampling on port local_port | |
9233 | * Access: RW | |
9234 | */ | |
9235 | MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); | |
9236 | ||
9237 | #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL | |
9238 | ||
9239 | /* reg_mpsc_rate | |
9240 | * Sampling rate = 1 out of rate packets (with randomization around | |
9241 | * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX | |
9242 | * Access: RW | |
9243 | */ | |
9244 | MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); | |
9245 | ||
9246 | static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, | |
9247 | u32 rate) | |
9248 | { | |
9249 | MLXSW_REG_ZERO(mpsc, payload); | |
9250 | mlxsw_reg_mpsc_local_port_set(payload, local_port); | |
9251 | mlxsw_reg_mpsc_e_set(payload, e); | |
9252 | mlxsw_reg_mpsc_rate_set(payload, rate); | |
9253 | } | |
9254 | ||
5766532a AS |
9255 | /* MGPC - Monitoring General Purpose Counter Set Register |
9256 | * The MGPC register retrieves and sets the General Purpose Counter Set. | |
9257 | */ | |
9258 | #define MLXSW_REG_MGPC_ID 0x9081 | |
9259 | #define MLXSW_REG_MGPC_LEN 0x18 | |
9260 | ||
9261 | MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); | |
9262 | ||
5766532a AS |
9263 | /* reg_mgpc_counter_set_type |
9264 | * Counter set type. | |
9265 | * Access: OP | |
9266 | */ | |
9267 | MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); | |
9268 | ||
9269 | /* reg_mgpc_counter_index | |
9270 | * Counter index. | |
9271 | * Access: Index | |
9272 | */ | |
9273 | MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); | |
9274 | ||
9275 | enum mlxsw_reg_mgpc_opcode { | |
9276 | /* Nop */ | |
9277 | MLXSW_REG_MGPC_OPCODE_NOP = 0x00, | |
9278 | /* Clear counters */ | |
9279 | MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, | |
9280 | }; | |
9281 | ||
9282 | /* reg_mgpc_opcode | |
9283 | * Opcode. | |
9284 | * Access: OP | |
9285 | */ | |
9286 | MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); | |
9287 | ||
9288 | /* reg_mgpc_byte_counter | |
9289 | * Byte counter value. | |
9290 | * Access: RW | |
9291 | */ | |
9292 | MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); | |
9293 | ||
9294 | /* reg_mgpc_packet_counter | |
9295 | * Packet counter value. | |
9296 | * Access: RW | |
9297 | */ | |
9298 | MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); | |
9299 | ||
9300 | static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, | |
9301 | enum mlxsw_reg_mgpc_opcode opcode, | |
6bba7e20 | 9302 | enum mlxsw_reg_flow_counter_set_type set_type) |
5766532a AS |
9303 | { |
9304 | MLXSW_REG_ZERO(mgpc, payload); | |
9305 | mlxsw_reg_mgpc_counter_index_set(payload, counter_index); | |
9306 | mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); | |
9307 | mlxsw_reg_mgpc_opcode_set(payload, opcode); | |
9308 | } | |
9309 | ||
27f68c08 IS |
9310 | /* MPRS - Monitoring Parsing State Register |
9311 | * ---------------------------------------- | |
9312 | * The MPRS register is used for setting up the parsing for hash, | |
9313 | * policy-engine and routing. | |
9314 | */ | |
9315 | #define MLXSW_REG_MPRS_ID 0x9083 | |
9316 | #define MLXSW_REG_MPRS_LEN 0x14 | |
9317 | ||
9318 | MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); | |
9319 | ||
9320 | /* reg_mprs_parsing_depth | |
9321 | * Minimum parsing depth. | |
9322 | * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL | |
9323 | * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. | |
9324 | * Access: RW | |
9325 | */ | |
9326 | MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); | |
9327 | ||
9328 | /* reg_mprs_parsing_en | |
9329 | * Parsing enable. | |
9330 | * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and | |
9331 | * NVGRE. Default is enabled. Reserved when SwitchX-2. | |
9332 | * Access: RW | |
9333 | */ | |
9334 | MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); | |
9335 | ||
9336 | /* reg_mprs_vxlan_udp_dport | |
9337 | * VxLAN UDP destination port. | |
9338 | * Used for identifying VxLAN packets and for dport field in | |
9339 | * encapsulation. Default is 4789. | |
9340 | * Access: RW | |
9341 | */ | |
9342 | MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); | |
9343 | ||
9344 | static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, | |
9345 | u16 vxlan_udp_dport) | |
9346 | { | |
9347 | MLXSW_REG_ZERO(mprs, payload); | |
9348 | mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); | |
9349 | mlxsw_reg_mprs_parsing_en_set(payload, true); | |
9350 | mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); | |
9351 | } | |
9352 | ||
41ce78b9 PM |
9353 | /* MOGCR - Monitoring Global Configuration Register |
9354 | * ------------------------------------------------ | |
9355 | */ | |
9356 | #define MLXSW_REG_MOGCR_ID 0x9086 | |
9357 | #define MLXSW_REG_MOGCR_LEN 0x20 | |
9358 | ||
9359 | MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); | |
9360 | ||
9361 | /* reg_mogcr_ptp_iftc | |
9362 | * PTP Ingress FIFO Trap Clear | |
9363 | * The PTP_ING_FIFO trap provides MTPPTR with clr according | |
9364 | * to this value. Default 0. | |
9365 | * Reserved when IB switches and when SwitchX/-2, Spectrum-2 | |
9366 | * Access: RW | |
9367 | */ | |
9368 | MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); | |
9369 | ||
9370 | /* reg_mogcr_ptp_eftc | |
9371 | * PTP Egress FIFO Trap Clear | |
9372 | * The PTP_EGR_FIFO trap provides MTPPTR with clr according | |
9373 | * to this value. Default 0. | |
9374 | * Reserved when IB switches and when SwitchX/-2, Spectrum-2 | |
9375 | * Access: RW | |
9376 | */ | |
9377 | MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); | |
9378 | ||
da28e878 PM |
9379 | /* MTPPPC - Time Precision Packet Port Configuration |
9380 | * ------------------------------------------------- | |
9381 | * This register serves for configuration of which PTP messages should be | |
9382 | * timestamped. This is a global configuration, despite the register name. | |
9383 | * | |
9384 | * Reserved when Spectrum-2. | |
9385 | */ | |
9386 | #define MLXSW_REG_MTPPPC_ID 0x9090 | |
9387 | #define MLXSW_REG_MTPPPC_LEN 0x28 | |
9388 | ||
9389 | MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); | |
9390 | ||
9391 | /* reg_mtpppc_ing_timestamp_message_type | |
9392 | * Bitwise vector of PTP message types to timestamp at ingress. | |
9393 | * MessageType field as defined by IEEE 1588 | |
9394 | * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) | |
9395 | * Default all 0 | |
9396 | * Access: RW | |
9397 | */ | |
9398 | MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); | |
9399 | ||
9400 | /* reg_mtpppc_egr_timestamp_message_type | |
9401 | * Bitwise vector of PTP message types to timestamp at egress. | |
9402 | * MessageType field as defined by IEEE 1588 | |
9403 | * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) | |
9404 | * Default all 0 | |
9405 | * Access: RW | |
9406 | */ | |
9407 | MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); | |
9408 | ||
9409 | static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) | |
9410 | { | |
9411 | MLXSW_REG_ZERO(mtpppc, payload); | |
9412 | mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); | |
9413 | mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); | |
9414 | } | |
9415 | ||
98b9028e PM |
9416 | /* MTPPTR - Time Precision Packet Timestamping Reading |
9417 | * --------------------------------------------------- | |
9418 | * The MTPPTR is used for reading the per port PTP timestamp FIFO. | |
9419 | * There is a trap for packets which are latched to the timestamp FIFO, thus the | |
9420 | * SW knows which FIFO to read. Note that packets enter the FIFO before been | |
9421 | * trapped. The sequence number is used to synchronize the timestamp FIFO | |
9422 | * entries and the trapped packets. | |
9423 | * Reserved when Spectrum-2. | |
9424 | */ | |
9425 | ||
9426 | #define MLXSW_REG_MTPPTR_ID 0x9091 | |
9427 | #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ | |
9428 | #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ | |
9429 | #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 | |
9430 | #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ | |
9431 | MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) | |
9432 | ||
9433 | MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); | |
9434 | ||
9435 | /* reg_mtpptr_local_port | |
9436 | * Not supported for CPU port. | |
9437 | * Access: Index | |
9438 | */ | |
9439 | MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); | |
9440 | ||
9441 | enum mlxsw_reg_mtpptr_dir { | |
9442 | MLXSW_REG_MTPPTR_DIR_INGRESS, | |
9443 | MLXSW_REG_MTPPTR_DIR_EGRESS, | |
9444 | }; | |
9445 | ||
9446 | /* reg_mtpptr_dir | |
9447 | * Direction. | |
9448 | * Access: Index | |
9449 | */ | |
9450 | MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); | |
9451 | ||
9452 | /* reg_mtpptr_clr | |
9453 | * Clear the records. | |
9454 | * Access: OP | |
9455 | */ | |
9456 | MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); | |
9457 | ||
9458 | /* reg_mtpptr_num_rec | |
9459 | * Number of valid records in the response | |
9460 | * Range 0.. cap_ptp_timestamp_fifo | |
9461 | * Access: RO | |
9462 | */ | |
9463 | MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); | |
9464 | ||
9465 | /* reg_mtpptr_rec_message_type | |
9466 | * MessageType field as defined by IEEE 1588 Each bit corresponds to a value | |
9467 | * (e.g. Bit0: Sync, Bit1: Delay_Req) | |
9468 | * Access: RO | |
9469 | */ | |
9470 | MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, | |
9471 | MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, | |
9472 | MLXSW_REG_MTPPTR_REC_LEN, 0, false); | |
9473 | ||
9474 | /* reg_mtpptr_rec_domain_number | |
9475 | * DomainNumber field as defined by IEEE 1588 | |
9476 | * Access: RO | |
9477 | */ | |
9478 | MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, | |
9479 | MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, | |
9480 | MLXSW_REG_MTPPTR_REC_LEN, 0, false); | |
9481 | ||
9482 | /* reg_mtpptr_rec_sequence_id | |
9483 | * SequenceId field as defined by IEEE 1588 | |
9484 | * Access: RO | |
9485 | */ | |
9486 | MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, | |
9487 | MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, | |
9488 | MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); | |
9489 | ||
9490 | /* reg_mtpptr_rec_timestamp_high | |
9491 | * Timestamp of when the PTP packet has passed through the port Units of PLL | |
9492 | * clock time. | |
9493 | * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. | |
9494 | * Access: RO | |
9495 | */ | |
9496 | MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, | |
9497 | MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, | |
9498 | MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); | |
9499 | ||
9500 | /* reg_mtpptr_rec_timestamp_low | |
9501 | * See rec_timestamp_high. | |
9502 | * Access: RO | |
9503 | */ | |
9504 | MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, | |
9505 | MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, | |
9506 | MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); | |
9507 | ||
9508 | static inline void mlxsw_reg_mtpptr_unpack(const char *payload, | |
9509 | unsigned int rec, | |
9510 | u8 *p_message_type, | |
9511 | u8 *p_domain_number, | |
9512 | u16 *p_sequence_id, | |
9513 | u64 *p_timestamp) | |
9514 | { | |
9515 | u32 timestamp_high, timestamp_low; | |
9516 | ||
9517 | *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); | |
9518 | *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); | |
9519 | *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); | |
9520 | timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); | |
9521 | timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); | |
9522 | *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; | |
9523 | } | |
9524 | ||
4dfecb65 PM |
9525 | /* MTPTPT - Monitoring Precision Time Protocol Trap Register |
9526 | * --------------------------------------------------------- | |
9527 | * This register is used for configuring under which trap to deliver PTP | |
9528 | * packets depending on type of the packet. | |
9529 | */ | |
9530 | #define MLXSW_REG_MTPTPT_ID 0x9092 | |
9531 | #define MLXSW_REG_MTPTPT_LEN 0x08 | |
9532 | ||
9533 | MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); | |
9534 | ||
9535 | enum mlxsw_reg_mtptpt_trap_id { | |
9536 | MLXSW_REG_MTPTPT_TRAP_ID_PTP0, | |
9537 | MLXSW_REG_MTPTPT_TRAP_ID_PTP1, | |
9538 | }; | |
9539 | ||
9540 | /* reg_mtptpt_trap_id | |
9541 | * Trap id. | |
9542 | * Access: Index | |
9543 | */ | |
9544 | MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); | |
9545 | ||
9546 | /* reg_mtptpt_message_type | |
9547 | * Bitwise vector of PTP message types to trap. This is a necessary but | |
9548 | * non-sufficient condition since need to enable also per port. See MTPPPC. | |
9549 | * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. | |
9550 | * Bit0: Sync, Bit1: Delay_Req) | |
9551 | */ | |
9552 | MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); | |
9553 | ||
9554 | static inline void mlxsw_reg_mtptptp_pack(char *payload, | |
9555 | enum mlxsw_reg_mtptpt_trap_id trap_id, | |
9556 | u16 message_type) | |
9557 | { | |
9558 | MLXSW_REG_ZERO(mtptpt, payload); | |
9559 | mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); | |
9560 | mlxsw_reg_mtptpt_message_type_set(payload, message_type); | |
9561 | } | |
9562 | ||
7e9561ed VP |
9563 | /* MGPIR - Management General Peripheral Information Register |
9564 | * ---------------------------------------------------------- | |
9565 | * MGPIR register allows software to query the hardware and | |
9566 | * firmware general information of peripheral entities. | |
9567 | */ | |
9568 | #define MLXSW_REG_MGPIR_ID 0x9100 | |
9569 | #define MLXSW_REG_MGPIR_LEN 0xA0 | |
9570 | ||
9571 | MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); | |
9572 | ||
9573 | enum mlxsw_reg_mgpir_device_type { | |
9574 | MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, | |
9575 | MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, | |
9576 | }; | |
9577 | ||
9578 | /* device_type | |
9579 | * Access: RO | |
9580 | */ | |
9581 | MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); | |
9582 | ||
9583 | /* devices_per_flash | |
9584 | * Number of devices of device_type per flash (can be shared by few devices). | |
9585 | * Access: RO | |
9586 | */ | |
9587 | MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); | |
9588 | ||
9589 | /* num_of_devices | |
9590 | * Number of devices of device_type. | |
9591 | * Access: RO | |
9592 | */ | |
9593 | MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); | |
9594 | ||
5cfa030a VP |
9595 | /* num_of_modules |
9596 | * Number of modules. | |
9597 | * Access: RO | |
9598 | */ | |
9599 | MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); | |
9600 | ||
7e9561ed VP |
9601 | static inline void mlxsw_reg_mgpir_pack(char *payload) |
9602 | { | |
9603 | MLXSW_REG_ZERO(mgpir, payload); | |
9604 | } | |
9605 | ||
9606 | static inline void | |
9607 | mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, | |
9608 | enum mlxsw_reg_mgpir_device_type *device_type, | |
5cfa030a | 9609 | u8 *devices_per_flash, u8 *num_of_modules) |
7e9561ed VP |
9610 | { |
9611 | if (num_of_devices) | |
9612 | *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); | |
9613 | if (device_type) | |
9614 | *device_type = mlxsw_reg_mgpir_device_type_get(payload); | |
9615 | if (devices_per_flash) | |
9616 | *devices_per_flash = | |
9617 | mlxsw_reg_mgpir_devices_per_flash_get(payload); | |
5cfa030a VP |
9618 | if (num_of_modules) |
9619 | *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); | |
7e9561ed VP |
9620 | } |
9621 | ||
710dd1a0 IS |
9622 | /* TNGCR - Tunneling NVE General Configuration Register |
9623 | * ---------------------------------------------------- | |
9624 | * The TNGCR register is used for setting up the NVE Tunneling configuration. | |
9625 | */ | |
9626 | #define MLXSW_REG_TNGCR_ID 0xA001 | |
9627 | #define MLXSW_REG_TNGCR_LEN 0x44 | |
9628 | ||
9629 | MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); | |
9630 | ||
9631 | enum mlxsw_reg_tngcr_type { | |
9632 | MLXSW_REG_TNGCR_TYPE_VXLAN, | |
9633 | MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, | |
9634 | MLXSW_REG_TNGCR_TYPE_GENEVE, | |
9635 | MLXSW_REG_TNGCR_TYPE_NVGRE, | |
9636 | }; | |
9637 | ||
9638 | /* reg_tngcr_type | |
9639 | * Tunnel type for encapsulation and decapsulation. The types are mutually | |
9640 | * exclusive. | |
9641 | * Note: For Spectrum the NVE parsing must be enabled in MPRS. | |
9642 | * Access: RW | |
9643 | */ | |
9644 | MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); | |
9645 | ||
9646 | /* reg_tngcr_nve_valid | |
9647 | * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. | |
9648 | * Access: RW | |
9649 | */ | |
9650 | MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); | |
9651 | ||
9652 | /* reg_tngcr_nve_ttl_uc | |
9653 | * The TTL for NVE tunnel encapsulation underlay unicast packets. | |
9654 | * Access: RW | |
9655 | */ | |
9656 | MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); | |
9657 | ||
9658 | /* reg_tngcr_nve_ttl_mc | |
9659 | * The TTL for NVE tunnel encapsulation underlay multicast packets. | |
9660 | * Access: RW | |
9661 | */ | |
9662 | MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); | |
9663 | ||
9664 | enum { | |
9665 | /* Do not copy flow label. Calculate flow label using nve_flh. */ | |
9666 | MLXSW_REG_TNGCR_FL_NO_COPY, | |
9667 | /* Copy flow label from inner packet if packet is IPv6 and | |
9668 | * encapsulation is by IPv6. Otherwise, calculate flow label using | |
9669 | * nve_flh. | |
9670 | */ | |
9671 | MLXSW_REG_TNGCR_FL_COPY, | |
9672 | }; | |
9673 | ||
9674 | /* reg_tngcr_nve_flc | |
9675 | * For NVE tunnel encapsulation: Flow label copy from inner packet. | |
9676 | * Access: RW | |
9677 | */ | |
9678 | MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); | |
9679 | ||
9680 | enum { | |
9681 | /* Flow label is static. In Spectrum this means '0'. Spectrum-2 | |
9682 | * uses {nve_fl_prefix, nve_fl_suffix}. | |
9683 | */ | |
9684 | MLXSW_REG_TNGCR_FL_NO_HASH, | |
9685 | /* 8 LSBs of the flow label are calculated from ECMP hash of the | |
9686 | * inner packet. 12 MSBs are configured by nve_fl_prefix. | |
9687 | */ | |
9688 | MLXSW_REG_TNGCR_FL_HASH, | |
9689 | }; | |
9690 | ||
9691 | /* reg_tngcr_nve_flh | |
9692 | * NVE flow label hash. | |
9693 | * Access: RW | |
9694 | */ | |
9695 | MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); | |
9696 | ||
9697 | /* reg_tngcr_nve_fl_prefix | |
9698 | * NVE flow label prefix. Constant 12 MSBs of the flow label. | |
9699 | * Access: RW | |
9700 | */ | |
9701 | MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); | |
9702 | ||
9703 | /* reg_tngcr_nve_fl_suffix | |
9704 | * NVE flow label suffix. Constant 8 LSBs of the flow label. | |
9705 | * Reserved when nve_flh=1 and for Spectrum. | |
9706 | * Access: RW | |
9707 | */ | |
9708 | MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); | |
9709 | ||
9710 | enum { | |
9711 | /* Source UDP port is fixed (default '0') */ | |
9712 | MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, | |
9713 | /* Source UDP port is calculated based on hash */ | |
9714 | MLXSW_REG_TNGCR_UDP_SPORT_HASH, | |
9715 | }; | |
9716 | ||
9717 | /* reg_tngcr_nve_udp_sport_type | |
9718 | * NVE UDP source port type. | |
9719 | * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). | |
9720 | * When the source UDP port is calculated based on hash, then the 8 LSBs | |
9721 | * are calculated from hash the 8 MSBs are configured by | |
9722 | * nve_udp_sport_prefix. | |
9723 | * Access: RW | |
9724 | */ | |
9725 | MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); | |
9726 | ||
9727 | /* reg_tngcr_nve_udp_sport_prefix | |
9728 | * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. | |
9729 | * Reserved when NVE type is NVGRE. | |
9730 | * Access: RW | |
9731 | */ | |
9732 | MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); | |
9733 | ||
9734 | /* reg_tngcr_nve_group_size_mc | |
9735 | * The amount of sequential linked lists of MC entries. The first linked | |
9736 | * list is configured by SFD.underlay_mc_ptr. | |
9737 | * Valid values: 1, 2, 4, 8, 16, 32, 64 | |
9738 | * The linked list are configured by TNUMT. | |
9739 | * The hash is set by LAG hash. | |
9740 | * Access: RW | |
9741 | */ | |
9742 | MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); | |
9743 | ||
9744 | /* reg_tngcr_nve_group_size_flood | |
9745 | * The amount of sequential linked lists of flooding entries. The first | |
9746 | * linked list is configured by SFMR.nve_tunnel_flood_ptr | |
9747 | * Valid values: 1, 2, 4, 8, 16, 32, 64 | |
9748 | * The linked list are configured by TNUMT. | |
9749 | * The hash is set by LAG hash. | |
9750 | * Access: RW | |
9751 | */ | |
9752 | MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); | |
9753 | ||
9754 | /* reg_tngcr_learn_enable | |
9755 | * During decapsulation, whether to learn from NVE port. | |
9756 | * Reserved when Spectrum-2. See TNPC. | |
9757 | * Access: RW | |
9758 | */ | |
9759 | MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); | |
9760 | ||
9761 | /* reg_tngcr_underlay_virtual_router | |
9762 | * Underlay virtual router. | |
9763 | * Reserved when Spectrum-2. | |
9764 | * Access: RW | |
9765 | */ | |
9766 | MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); | |
9767 | ||
9768 | /* reg_tngcr_underlay_rif | |
9769 | * Underlay ingress router interface. RIF type should be loopback generic. | |
9770 | * Reserved when Spectrum. | |
9771 | * Access: RW | |
9772 | */ | |
9773 | MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); | |
9774 | ||
9775 | /* reg_tngcr_usipv4 | |
9776 | * Underlay source IPv4 address of the NVE. | |
9777 | * Access: RW | |
9778 | */ | |
9779 | MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); | |
9780 | ||
9781 | /* reg_tngcr_usipv6 | |
9782 | * Underlay source IPv6 address of the NVE. For Spectrum, must not be | |
9783 | * modified under traffic of NVE tunneling encapsulation. | |
9784 | * Access: RW | |
9785 | */ | |
9786 | MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); | |
9787 | ||
9788 | static inline void mlxsw_reg_tngcr_pack(char *payload, | |
9789 | enum mlxsw_reg_tngcr_type type, | |
9790 | bool valid, u8 ttl) | |
9791 | { | |
9792 | MLXSW_REG_ZERO(tngcr, payload); | |
9793 | mlxsw_reg_tngcr_type_set(payload, type); | |
9794 | mlxsw_reg_tngcr_nve_valid_set(payload, valid); | |
9795 | mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); | |
9796 | mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); | |
9797 | mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); | |
9798 | mlxsw_reg_tngcr_nve_flh_set(payload, 0); | |
9799 | mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, | |
9800 | MLXSW_REG_TNGCR_UDP_SPORT_HASH); | |
9801 | mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); | |
9802 | mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); | |
9803 | mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); | |
9804 | } | |
9805 | ||
c723d19f IS |
9806 | /* TNUMT - Tunneling NVE Underlay Multicast Table Register |
9807 | * ------------------------------------------------------- | |
9808 | * The TNUMT register is for building the underlay MC table. It is used | |
9809 | * for MC, flooding and BC traffic into the NVE tunnel. | |
9810 | */ | |
9811 | #define MLXSW_REG_TNUMT_ID 0xA003 | |
9812 | #define MLXSW_REG_TNUMT_LEN 0x20 | |
9813 | ||
9814 | MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); | |
9815 | ||
9816 | enum mlxsw_reg_tnumt_record_type { | |
9817 | MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, | |
9818 | MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, | |
9819 | MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, | |
9820 | }; | |
9821 | ||
9822 | /* reg_tnumt_record_type | |
9823 | * Record type. | |
9824 | * Access: RW | |
9825 | */ | |
9826 | MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); | |
9827 | ||
9828 | enum mlxsw_reg_tnumt_tunnel_port { | |
9829 | MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, | |
9830 | MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, | |
9831 | MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, | |
9832 | MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, | |
9833 | }; | |
9834 | ||
9835 | /* reg_tnumt_tunnel_port | |
9836 | * Tunnel port. | |
9837 | * Access: RW | |
9838 | */ | |
9839 | MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); | |
9840 | ||
9841 | /* reg_tnumt_underlay_mc_ptr | |
9842 | * Index to the underlay multicast table. | |
9843 | * For Spectrum the index is to the KVD linear. | |
9844 | * Access: Index | |
9845 | */ | |
9846 | MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); | |
9847 | ||
9848 | /* reg_tnumt_vnext | |
9849 | * The next_underlay_mc_ptr is valid. | |
9850 | * Access: RW | |
9851 | */ | |
9852 | MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); | |
9853 | ||
9854 | /* reg_tnumt_next_underlay_mc_ptr | |
9855 | * The next index to the underlay multicast table. | |
9856 | * Access: RW | |
9857 | */ | |
9858 | MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); | |
9859 | ||
9860 | /* reg_tnumt_record_size | |
9861 | * Number of IP addresses in the record. | |
9862 | * Range is 1..cap_max_nve_mc_entries_ipv{4,6} | |
9863 | * Access: RW | |
9864 | */ | |
9865 | MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); | |
9866 | ||
9867 | /* reg_tnumt_udip | |
9868 | * The underlay IPv4 addresses. udip[i] is reserved if i >= size | |
9869 | * Access: RW | |
9870 | */ | |
9871 | MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); | |
9872 | ||
9873 | /* reg_tnumt_udip_ptr | |
9874 | * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if | |
9875 | * i >= size. The IPv6 addresses are configured by RIPS. | |
9876 | * Access: RW | |
9877 | */ | |
9878 | MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); | |
9879 | ||
9880 | static inline void mlxsw_reg_tnumt_pack(char *payload, | |
9881 | enum mlxsw_reg_tnumt_record_type type, | |
9882 | enum mlxsw_reg_tnumt_tunnel_port tport, | |
9883 | u32 underlay_mc_ptr, bool vnext, | |
9884 | u32 next_underlay_mc_ptr, | |
9885 | u8 record_size) | |
9886 | { | |
9887 | MLXSW_REG_ZERO(tnumt, payload); | |
9888 | mlxsw_reg_tnumt_record_type_set(payload, type); | |
9889 | mlxsw_reg_tnumt_tunnel_port_set(payload, tport); | |
9890 | mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); | |
9891 | mlxsw_reg_tnumt_vnext_set(payload, vnext); | |
9892 | mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); | |
9893 | mlxsw_reg_tnumt_record_size_set(payload, record_size); | |
9894 | } | |
9895 | ||
fd6db27c IS |
9896 | /* TNQCR - Tunneling NVE QoS Configuration Register |
9897 | * ------------------------------------------------ | |
9898 | * The TNQCR register configures how QoS is set in encapsulation into the | |
9899 | * underlay network. | |
9900 | */ | |
9901 | #define MLXSW_REG_TNQCR_ID 0xA010 | |
9902 | #define MLXSW_REG_TNQCR_LEN 0x0C | |
9903 | ||
9904 | MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); | |
9905 | ||
9906 | /* reg_tnqcr_enc_set_dscp | |
9907 | * For encapsulation: How to set DSCP field: | |
9908 | * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay | |
9909 | * (outer) IP header. If there is no IP header, use TNQDR.dscp | |
9910 | * 1 - Set the DSCP field as TNQDR.dscp | |
9911 | * Access: RW | |
9912 | */ | |
9913 | MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); | |
9914 | ||
9915 | static inline void mlxsw_reg_tnqcr_pack(char *payload) | |
9916 | { | |
9917 | MLXSW_REG_ZERO(tnqcr, payload); | |
9918 | mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); | |
9919 | } | |
9920 | ||
8efcf6bb IS |
9921 | /* TNQDR - Tunneling NVE QoS Default Register |
9922 | * ------------------------------------------ | |
9923 | * The TNQDR register configures the default QoS settings for NVE | |
9924 | * encapsulation. | |
9925 | */ | |
9926 | #define MLXSW_REG_TNQDR_ID 0xA011 | |
9927 | #define MLXSW_REG_TNQDR_LEN 0x08 | |
9928 | ||
9929 | MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); | |
9930 | ||
9931 | /* reg_tnqdr_local_port | |
9932 | * Local port number (receive port). CPU port is supported. | |
9933 | * Access: Index | |
9934 | */ | |
9935 | MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); | |
9936 | ||
9937 | /* reg_tnqdr_dscp | |
9938 | * For encapsulation, the default DSCP. | |
9939 | * Access: RW | |
9940 | */ | |
9941 | MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); | |
9942 | ||
9943 | static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) | |
9944 | { | |
9945 | MLXSW_REG_ZERO(tnqdr, payload); | |
9946 | mlxsw_reg_tnqdr_local_port_set(payload, local_port); | |
9947 | mlxsw_reg_tnqdr_dscp_set(payload, 0); | |
9948 | } | |
9949 | ||
4a8d1860 IS |
9950 | /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register |
9951 | * -------------------------------------------------------- | |
9952 | * The TNEEM register maps ECN of the IP header at the ingress to the | |
9953 | * encapsulation to the ECN of the underlay network. | |
9954 | */ | |
9955 | #define MLXSW_REG_TNEEM_ID 0xA012 | |
9956 | #define MLXSW_REG_TNEEM_LEN 0x0C | |
9957 | ||
9958 | MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); | |
9959 | ||
9960 | /* reg_tneem_overlay_ecn | |
9961 | * ECN of the IP header in the overlay network. | |
9962 | * Access: Index | |
9963 | */ | |
9964 | MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); | |
9965 | ||
9966 | /* reg_tneem_underlay_ecn | |
9967 | * ECN of the IP header in the underlay network. | |
9968 | * Access: RW | |
9969 | */ | |
9970 | MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); | |
9971 | ||
9972 | static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, | |
9973 | u8 underlay_ecn) | |
9974 | { | |
9975 | MLXSW_REG_ZERO(tneem, payload); | |
9976 | mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); | |
9977 | mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); | |
9978 | } | |
9979 | ||
a77d5f0b IS |
9980 | /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register |
9981 | * -------------------------------------------------------- | |
9982 | * The TNDEM register configures the actions that are done in the | |
9983 | * decapsulation. | |
9984 | */ | |
9985 | #define MLXSW_REG_TNDEM_ID 0xA013 | |
9986 | #define MLXSW_REG_TNDEM_LEN 0x0C | |
9987 | ||
9988 | MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); | |
9989 | ||
9990 | /* reg_tndem_underlay_ecn | |
9991 | * ECN field of the IP header in the underlay network. | |
9992 | * Access: Index | |
9993 | */ | |
9994 | MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); | |
9995 | ||
9996 | /* reg_tndem_overlay_ecn | |
9997 | * ECN field of the IP header in the overlay network. | |
9998 | * Access: Index | |
9999 | */ | |
10000 | MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); | |
10001 | ||
10002 | /* reg_tndem_eip_ecn | |
10003 | * Egress IP ECN. ECN field of the IP header of the packet which goes out | |
10004 | * from the decapsulation. | |
10005 | * Access: RW | |
10006 | */ | |
10007 | MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); | |
10008 | ||
10009 | /* reg_tndem_trap_en | |
10010 | * Trap enable: | |
10011 | * 0 - No trap due to decap ECN | |
10012 | * 1 - Trap enable with trap_id | |
10013 | * Access: RW | |
10014 | */ | |
10015 | MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); | |
10016 | ||
10017 | /* reg_tndem_trap_id | |
10018 | * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. | |
10019 | * Reserved when trap_en is '0'. | |
10020 | * Access: RW | |
10021 | */ | |
10022 | MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); | |
10023 | ||
10024 | static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, | |
10025 | u8 overlay_ecn, u8 ecn, bool trap_en, | |
10026 | u16 trap_id) | |
10027 | { | |
10028 | MLXSW_REG_ZERO(tndem, payload); | |
10029 | mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); | |
10030 | mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); | |
10031 | mlxsw_reg_tndem_eip_ecn_set(payload, ecn); | |
10032 | mlxsw_reg_tndem_trap_en_set(payload, trap_en); | |
10033 | mlxsw_reg_tndem_trap_id_set(payload, trap_id); | |
10034 | } | |
10035 | ||
50e6eb2a IS |
10036 | /* TNPC - Tunnel Port Configuration Register |
10037 | * ----------------------------------------- | |
10038 | * The TNPC register is used for tunnel port configuration. | |
10039 | * Reserved when Spectrum. | |
10040 | */ | |
10041 | #define MLXSW_REG_TNPC_ID 0xA020 | |
10042 | #define MLXSW_REG_TNPC_LEN 0x18 | |
10043 | ||
10044 | MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); | |
10045 | ||
10046 | enum mlxsw_reg_tnpc_tunnel_port { | |
10047 | MLXSW_REG_TNPC_TUNNEL_PORT_NVE, | |
10048 | MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, | |
10049 | MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, | |
10050 | MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, | |
10051 | }; | |
10052 | ||
10053 | /* reg_tnpc_tunnel_port | |
10054 | * Tunnel port. | |
10055 | * Access: Index | |
10056 | */ | |
10057 | MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); | |
10058 | ||
10059 | /* reg_tnpc_learn_enable_v6 | |
10060 | * During IPv6 underlay decapsulation, whether to learn from tunnel port. | |
10061 | * Access: RW | |
10062 | */ | |
10063 | MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); | |
10064 | ||
10065 | /* reg_tnpc_learn_enable_v4 | |
10066 | * During IPv4 underlay decapsulation, whether to learn from tunnel port. | |
10067 | * Access: RW | |
10068 | */ | |
10069 | MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); | |
10070 | ||
10071 | static inline void mlxsw_reg_tnpc_pack(char *payload, | |
10072 | enum mlxsw_reg_tnpc_tunnel_port tport, | |
10073 | bool learn_enable) | |
10074 | { | |
10075 | MLXSW_REG_ZERO(tnpc, payload); | |
10076 | mlxsw_reg_tnpc_tunnel_port_set(payload, tport); | |
10077 | mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); | |
10078 | mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); | |
10079 | } | |
10080 | ||
14aefd90 PM |
10081 | /* TIGCR - Tunneling IPinIP General Configuration Register |
10082 | * ------------------------------------------------------- | |
10083 | * The TIGCR register is used for setting up the IPinIP Tunnel configuration. | |
10084 | */ | |
10085 | #define MLXSW_REG_TIGCR_ID 0xA801 | |
10086 | #define MLXSW_REG_TIGCR_LEN 0x10 | |
10087 | ||
10088 | MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); | |
10089 | ||
10090 | /* reg_tigcr_ipip_ttlc | |
10091 | * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet | |
10092 | * header. | |
10093 | * Access: RW | |
10094 | */ | |
10095 | MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); | |
10096 | ||
10097 | /* reg_tigcr_ipip_ttl_uc | |
10098 | * The TTL for IPinIP Tunnel encapsulation of unicast packets if | |
10099 | * reg_tigcr_ipip_ttlc is unset. | |
10100 | * Access: RW | |
10101 | */ | |
10102 | MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); | |
10103 | ||
10104 | static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) | |
10105 | { | |
10106 | MLXSW_REG_ZERO(tigcr, payload); | |
10107 | mlxsw_reg_tigcr_ttlc_set(payload, ttlc); | |
10108 | mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); | |
10109 | } | |
10110 | ||
e0594369 JP |
10111 | /* SBPR - Shared Buffer Pools Register |
10112 | * ----------------------------------- | |
10113 | * The SBPR configures and retrieves the shared buffer pools and configuration. | |
10114 | */ | |
10115 | #define MLXSW_REG_SBPR_ID 0xB001 | |
10116 | #define MLXSW_REG_SBPR_LEN 0x14 | |
10117 | ||
21978dcf | 10118 | MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); |
e0594369 | 10119 | |
497e8592 JP |
10120 | /* shared direstion enum for SBPR, SBCM, SBPM */ |
10121 | enum mlxsw_reg_sbxx_dir { | |
10122 | MLXSW_REG_SBXX_DIR_INGRESS, | |
10123 | MLXSW_REG_SBXX_DIR_EGRESS, | |
e0594369 JP |
10124 | }; |
10125 | ||
10126 | /* reg_sbpr_dir | |
10127 | * Direction. | |
10128 | * Access: Index | |
10129 | */ | |
10130 | MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); | |
10131 | ||
10132 | /* reg_sbpr_pool | |
10133 | * Pool index. | |
10134 | * Access: Index | |
10135 | */ | |
10136 | MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); | |
10137 | ||
f0024f0d PM |
10138 | /* reg_sbpr_infi_size |
10139 | * Size is infinite. | |
10140 | * Access: RW | |
10141 | */ | |
10142 | MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); | |
10143 | ||
e0594369 JP |
10144 | /* reg_sbpr_size |
10145 | * Pool size in buffer cells. | |
f0024f0d | 10146 | * Reserved when infi_size = 1. |
e0594369 JP |
10147 | * Access: RW |
10148 | */ | |
10149 | MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); | |
10150 | ||
10151 | enum mlxsw_reg_sbpr_mode { | |
10152 | MLXSW_REG_SBPR_MODE_STATIC, | |
10153 | MLXSW_REG_SBPR_MODE_DYNAMIC, | |
10154 | }; | |
10155 | ||
10156 | /* reg_sbpr_mode | |
10157 | * Pool quota calculation mode. | |
10158 | * Access: RW | |
10159 | */ | |
10160 | MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); | |
10161 | ||
10162 | static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, | |
497e8592 | 10163 | enum mlxsw_reg_sbxx_dir dir, |
f0024f0d PM |
10164 | enum mlxsw_reg_sbpr_mode mode, u32 size, |
10165 | bool infi_size) | |
e0594369 JP |
10166 | { |
10167 | MLXSW_REG_ZERO(sbpr, payload); | |
10168 | mlxsw_reg_sbpr_pool_set(payload, pool); | |
10169 | mlxsw_reg_sbpr_dir_set(payload, dir); | |
10170 | mlxsw_reg_sbpr_mode_set(payload, mode); | |
10171 | mlxsw_reg_sbpr_size_set(payload, size); | |
f0024f0d | 10172 | mlxsw_reg_sbpr_infi_size_set(payload, infi_size); |
e0594369 JP |
10173 | } |
10174 | ||
10175 | /* SBCM - Shared Buffer Class Management Register | |
10176 | * ---------------------------------------------- | |
10177 | * The SBCM register configures and retrieves the shared buffer allocation | |
10178 | * and configuration according to Port-PG, including the binding to pool | |
10179 | * and definition of the associated quota. | |
10180 | */ | |
10181 | #define MLXSW_REG_SBCM_ID 0xB002 | |
10182 | #define MLXSW_REG_SBCM_LEN 0x28 | |
10183 | ||
21978dcf | 10184 | MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); |
e0594369 JP |
10185 | |
10186 | /* reg_sbcm_local_port | |
10187 | * Local port number. | |
10188 | * For Ingress: excludes CPU port and Router port | |
10189 | * For Egress: excludes IP Router | |
10190 | * Access: Index | |
10191 | */ | |
10192 | MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); | |
10193 | ||
10194 | /* reg_sbcm_pg_buff | |
10195 | * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) | |
10196 | * For PG buffer: range is 0..cap_max_pg_buffers - 1 | |
10197 | * For traffic class: range is 0..cap_max_tclass - 1 | |
10198 | * Note that when traffic class is in MC aware mode then the traffic | |
10199 | * classes which are MC aware cannot be configured. | |
10200 | * Access: Index | |
10201 | */ | |
10202 | MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); | |
10203 | ||
e0594369 JP |
10204 | /* reg_sbcm_dir |
10205 | * Direction. | |
10206 | * Access: Index | |
10207 | */ | |
10208 | MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); | |
10209 | ||
10210 | /* reg_sbcm_min_buff | |
10211 | * Minimum buffer size for the limiter, in cells. | |
10212 | * Access: RW | |
10213 | */ | |
10214 | MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); | |
10215 | ||
c30a53c7 JP |
10216 | /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ |
10217 | #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 | |
10218 | #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 | |
10219 | ||
d144e3a2 PM |
10220 | /* reg_sbcm_infi_max |
10221 | * Max buffer is infinite. | |
10222 | * Access: RW | |
10223 | */ | |
10224 | MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); | |
10225 | ||
e0594369 JP |
10226 | /* reg_sbcm_max_buff |
10227 | * When the pool associated to the port-pg/tclass is configured to | |
10228 | * static, Maximum buffer size for the limiter configured in cells. | |
10229 | * When the pool associated to the port-pg/tclass is configured to | |
10230 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
10231 | * the following values: | |
10232 | * 0: 0 | |
10233 | * i: (1/128)*2^(i-1), for i=1..14 | |
10234 | * 0xFF: Infinity | |
d144e3a2 | 10235 | * Reserved when infi_max = 1. |
e0594369 JP |
10236 | * Access: RW |
10237 | */ | |
10238 | MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); | |
10239 | ||
10240 | /* reg_sbcm_pool | |
10241 | * Association of the port-priority to a pool. | |
10242 | * Access: RW | |
10243 | */ | |
10244 | MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); | |
10245 | ||
10246 | static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, | |
497e8592 | 10247 | enum mlxsw_reg_sbxx_dir dir, |
d144e3a2 PM |
10248 | u32 min_buff, u32 max_buff, |
10249 | bool infi_max, u8 pool) | |
e0594369 JP |
10250 | { |
10251 | MLXSW_REG_ZERO(sbcm, payload); | |
10252 | mlxsw_reg_sbcm_local_port_set(payload, local_port); | |
10253 | mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); | |
10254 | mlxsw_reg_sbcm_dir_set(payload, dir); | |
10255 | mlxsw_reg_sbcm_min_buff_set(payload, min_buff); | |
10256 | mlxsw_reg_sbcm_max_buff_set(payload, max_buff); | |
d144e3a2 | 10257 | mlxsw_reg_sbcm_infi_max_set(payload, infi_max); |
e0594369 JP |
10258 | mlxsw_reg_sbcm_pool_set(payload, pool); |
10259 | } | |
10260 | ||
9efc8f65 JP |
10261 | /* SBPM - Shared Buffer Port Management Register |
10262 | * --------------------------------------------- | |
e0594369 JP |
10263 | * The SBPM register configures and retrieves the shared buffer allocation |
10264 | * and configuration according to Port-Pool, including the definition | |
10265 | * of the associated quota. | |
10266 | */ | |
10267 | #define MLXSW_REG_SBPM_ID 0xB003 | |
10268 | #define MLXSW_REG_SBPM_LEN 0x28 | |
10269 | ||
21978dcf | 10270 | MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); |
e0594369 JP |
10271 | |
10272 | /* reg_sbpm_local_port | |
10273 | * Local port number. | |
10274 | * For Ingress: excludes CPU port and Router port | |
10275 | * For Egress: excludes IP Router | |
10276 | * Access: Index | |
10277 | */ | |
10278 | MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); | |
10279 | ||
10280 | /* reg_sbpm_pool | |
10281 | * The pool associated to quota counting on the local_port. | |
10282 | * Access: Index | |
10283 | */ | |
10284 | MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); | |
10285 | ||
e0594369 JP |
10286 | /* reg_sbpm_dir |
10287 | * Direction. | |
10288 | * Access: Index | |
10289 | */ | |
10290 | MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); | |
10291 | ||
42a7f1d7 JP |
10292 | /* reg_sbpm_buff_occupancy |
10293 | * Current buffer occupancy in cells. | |
10294 | * Access: RO | |
10295 | */ | |
10296 | MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); | |
10297 | ||
10298 | /* reg_sbpm_clr | |
10299 | * Clear Max Buffer Occupancy | |
10300 | * When this bit is set, max_buff_occupancy field is cleared (and a | |
10301 | * new max value is tracked from the time the clear was performed). | |
10302 | * Access: OP | |
10303 | */ | |
10304 | MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); | |
10305 | ||
10306 | /* reg_sbpm_max_buff_occupancy | |
10307 | * Maximum value of buffer occupancy in cells monitored. Cleared by | |
10308 | * writing to the clr field. | |
10309 | * Access: RO | |
10310 | */ | |
10311 | MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); | |
10312 | ||
e0594369 JP |
10313 | /* reg_sbpm_min_buff |
10314 | * Minimum buffer size for the limiter, in cells. | |
10315 | * Access: RW | |
10316 | */ | |
10317 | MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); | |
10318 | ||
10319 | /* reg_sbpm_max_buff | |
10320 | * When the pool associated to the port-pg/tclass is configured to | |
10321 | * static, Maximum buffer size for the limiter configured in cells. | |
10322 | * When the pool associated to the port-pg/tclass is configured to | |
10323 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
10324 | * the following values: | |
10325 | * 0: 0 | |
10326 | * i: (1/128)*2^(i-1), for i=1..14 | |
10327 | * 0xFF: Infinity | |
10328 | * Access: RW | |
10329 | */ | |
10330 | MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); | |
10331 | ||
10332 | static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, | |
42a7f1d7 | 10333 | enum mlxsw_reg_sbxx_dir dir, bool clr, |
e0594369 JP |
10334 | u32 min_buff, u32 max_buff) |
10335 | { | |
10336 | MLXSW_REG_ZERO(sbpm, payload); | |
10337 | mlxsw_reg_sbpm_local_port_set(payload, local_port); | |
10338 | mlxsw_reg_sbpm_pool_set(payload, pool); | |
10339 | mlxsw_reg_sbpm_dir_set(payload, dir); | |
42a7f1d7 | 10340 | mlxsw_reg_sbpm_clr_set(payload, clr); |
e0594369 JP |
10341 | mlxsw_reg_sbpm_min_buff_set(payload, min_buff); |
10342 | mlxsw_reg_sbpm_max_buff_set(payload, max_buff); | |
10343 | } | |
10344 | ||
42a7f1d7 JP |
10345 | static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, |
10346 | u32 *p_max_buff_occupancy) | |
10347 | { | |
10348 | *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); | |
10349 | *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); | |
10350 | } | |
10351 | ||
e0594369 JP |
10352 | /* SBMM - Shared Buffer Multicast Management Register |
10353 | * -------------------------------------------------- | |
10354 | * The SBMM register configures and retrieves the shared buffer allocation | |
10355 | * and configuration for MC packets according to Switch-Priority, including | |
10356 | * the binding to pool and definition of the associated quota. | |
10357 | */ | |
10358 | #define MLXSW_REG_SBMM_ID 0xB004 | |
10359 | #define MLXSW_REG_SBMM_LEN 0x28 | |
10360 | ||
21978dcf | 10361 | MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); |
e0594369 JP |
10362 | |
10363 | /* reg_sbmm_prio | |
10364 | * Switch Priority. | |
10365 | * Access: Index | |
10366 | */ | |
10367 | MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); | |
10368 | ||
10369 | /* reg_sbmm_min_buff | |
10370 | * Minimum buffer size for the limiter, in cells. | |
10371 | * Access: RW | |
10372 | */ | |
10373 | MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); | |
10374 | ||
10375 | /* reg_sbmm_max_buff | |
10376 | * When the pool associated to the port-pg/tclass is configured to | |
10377 | * static, Maximum buffer size for the limiter configured in cells. | |
10378 | * When the pool associated to the port-pg/tclass is configured to | |
10379 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
10380 | * the following values: | |
10381 | * 0: 0 | |
10382 | * i: (1/128)*2^(i-1), for i=1..14 | |
10383 | * 0xFF: Infinity | |
10384 | * Access: RW | |
10385 | */ | |
10386 | MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); | |
10387 | ||
10388 | /* reg_sbmm_pool | |
10389 | * Association of the port-priority to a pool. | |
10390 | * Access: RW | |
10391 | */ | |
10392 | MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); | |
10393 | ||
10394 | static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, | |
10395 | u32 max_buff, u8 pool) | |
10396 | { | |
10397 | MLXSW_REG_ZERO(sbmm, payload); | |
10398 | mlxsw_reg_sbmm_prio_set(payload, prio); | |
10399 | mlxsw_reg_sbmm_min_buff_set(payload, min_buff); | |
10400 | mlxsw_reg_sbmm_max_buff_set(payload, max_buff); | |
10401 | mlxsw_reg_sbmm_pool_set(payload, pool); | |
10402 | } | |
10403 | ||
26176def JP |
10404 | /* SBSR - Shared Buffer Status Register |
10405 | * ------------------------------------ | |
10406 | * The SBSR register retrieves the shared buffer occupancy according to | |
10407 | * Port-Pool. Note that this register enables reading a large amount of data. | |
10408 | * It is the user's responsibility to limit the amount of data to ensure the | |
10409 | * response can match the maximum transfer unit. In case the response exceeds | |
10410 | * the maximum transport unit, it will be truncated with no special notice. | |
10411 | */ | |
10412 | #define MLXSW_REG_SBSR_ID 0xB005 | |
10413 | #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ | |
10414 | #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ | |
10415 | #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 | |
10416 | #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ | |
10417 | MLXSW_REG_SBSR_REC_LEN * \ | |
10418 | MLXSW_REG_SBSR_REC_MAX_COUNT) | |
10419 | ||
21978dcf | 10420 | MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); |
26176def JP |
10421 | |
10422 | /* reg_sbsr_clr | |
10423 | * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy | |
10424 | * field is cleared (and a new max value is tracked from the time the clear | |
10425 | * was performed). | |
10426 | * Access: OP | |
10427 | */ | |
10428 | MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); | |
10429 | ||
10430 | /* reg_sbsr_ingress_port_mask | |
10431 | * Bit vector for all ingress network ports. | |
10432 | * Indicates which of the ports (for which the relevant bit is set) | |
10433 | * are affected by the set operation. Configuration of any other port | |
10434 | * does not change. | |
10435 | * Access: Index | |
10436 | */ | |
10437 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); | |
10438 | ||
10439 | /* reg_sbsr_pg_buff_mask | |
10440 | * Bit vector for all switch priority groups. | |
10441 | * Indicates which of the priorities (for which the relevant bit is set) | |
10442 | * are affected by the set operation. Configuration of any other priority | |
10443 | * does not change. | |
10444 | * Range is 0..cap_max_pg_buffers - 1 | |
10445 | * Access: Index | |
10446 | */ | |
10447 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); | |
10448 | ||
10449 | /* reg_sbsr_egress_port_mask | |
10450 | * Bit vector for all egress network ports. | |
10451 | * Indicates which of the ports (for which the relevant bit is set) | |
10452 | * are affected by the set operation. Configuration of any other port | |
10453 | * does not change. | |
10454 | * Access: Index | |
10455 | */ | |
10456 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); | |
10457 | ||
10458 | /* reg_sbsr_tclass_mask | |
10459 | * Bit vector for all traffic classes. | |
10460 | * Indicates which of the traffic classes (for which the relevant bit is | |
10461 | * set) are affected by the set operation. Configuration of any other | |
10462 | * traffic class does not change. | |
10463 | * Range is 0..cap_max_tclass - 1 | |
10464 | * Access: Index | |
10465 | */ | |
10466 | MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); | |
10467 | ||
10468 | static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) | |
10469 | { | |
10470 | MLXSW_REG_ZERO(sbsr, payload); | |
10471 | mlxsw_reg_sbsr_clr_set(payload, clr); | |
10472 | } | |
10473 | ||
10474 | /* reg_sbsr_rec_buff_occupancy | |
10475 | * Current buffer occupancy in cells. | |
10476 | * Access: RO | |
10477 | */ | |
10478 | MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, | |
10479 | 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); | |
10480 | ||
10481 | /* reg_sbsr_rec_max_buff_occupancy | |
10482 | * Maximum value of buffer occupancy in cells monitored. Cleared by | |
10483 | * writing to the clr field. | |
10484 | * Access: RO | |
10485 | */ | |
10486 | MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, | |
10487 | 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); | |
10488 | ||
10489 | static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, | |
10490 | u32 *p_buff_occupancy, | |
10491 | u32 *p_max_buff_occupancy) | |
10492 | { | |
10493 | *p_buff_occupancy = | |
10494 | mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); | |
10495 | *p_max_buff_occupancy = | |
10496 | mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); | |
10497 | } | |
10498 | ||
51ae8cc6 YG |
10499 | /* SBIB - Shared Buffer Internal Buffer Register |
10500 | * --------------------------------------------- | |
10501 | * The SBIB register configures per port buffers for internal use. The internal | |
10502 | * buffers consume memory on the port buffers (note that the port buffers are | |
10503 | * used also by PBMC). | |
10504 | * | |
10505 | * For Spectrum this is used for egress mirroring. | |
10506 | */ | |
10507 | #define MLXSW_REG_SBIB_ID 0xB006 | |
10508 | #define MLXSW_REG_SBIB_LEN 0x10 | |
10509 | ||
21978dcf | 10510 | MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); |
51ae8cc6 YG |
10511 | |
10512 | /* reg_sbib_local_port | |
10513 | * Local port number | |
10514 | * Not supported for CPU port and router port | |
10515 | * Access: Index | |
10516 | */ | |
10517 | MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); | |
10518 | ||
10519 | /* reg_sbib_buff_size | |
10520 | * Units represented in cells | |
10521 | * Allowed range is 0 to (cap_max_headroom_size - 1) | |
10522 | * Default is 0 | |
10523 | * Access: RW | |
10524 | */ | |
10525 | MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); | |
10526 | ||
10527 | static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, | |
10528 | u32 buff_size) | |
10529 | { | |
10530 | MLXSW_REG_ZERO(sbib, payload); | |
10531 | mlxsw_reg_sbib_local_port_set(payload, local_port); | |
10532 | mlxsw_reg_sbib_buff_size_set(payload, buff_size); | |
10533 | } | |
10534 | ||
8e9658d5 JP |
10535 | static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { |
10536 | MLXSW_REG(sgcr), | |
10537 | MLXSW_REG(spad), | |
10538 | MLXSW_REG(smid), | |
10539 | MLXSW_REG(sspr), | |
10540 | MLXSW_REG(sfdat), | |
10541 | MLXSW_REG(sfd), | |
10542 | MLXSW_REG(sfn), | |
10543 | MLXSW_REG(spms), | |
10544 | MLXSW_REG(spvid), | |
10545 | MLXSW_REG(spvm), | |
10546 | MLXSW_REG(spaft), | |
10547 | MLXSW_REG(sfgc), | |
10548 | MLXSW_REG(sftr), | |
10549 | MLXSW_REG(sfdf), | |
10550 | MLXSW_REG(sldr), | |
10551 | MLXSW_REG(slcr), | |
10552 | MLXSW_REG(slcor), | |
10553 | MLXSW_REG(spmlr), | |
10554 | MLXSW_REG(svfa), | |
10555 | MLXSW_REG(svpe), | |
10556 | MLXSW_REG(sfmr), | |
10557 | MLXSW_REG(spvmlr), | |
ad53fa06 NF |
10558 | MLXSW_REG(cwtp), |
10559 | MLXSW_REG(cwtpm), | |
7050f439 | 10560 | MLXSW_REG(pgcr), |
af7170ee | 10561 | MLXSW_REG(ppbt), |
3279da4c | 10562 | MLXSW_REG(pacl), |
10fabef5 | 10563 | MLXSW_REG(pagt), |
d9c2661e | 10564 | MLXSW_REG(ptar), |
d120649d | 10565 | MLXSW_REG(ppbs), |
937b682c | 10566 | MLXSW_REG(prcr), |
e3426e12 | 10567 | MLXSW_REG(pefa), |
a75e41d3 | 10568 | MLXSW_REG(pemrbt), |
0171cdec | 10569 | MLXSW_REG(ptce2), |
8c0d1cdd | 10570 | MLXSW_REG(perpt), |
418089a8 | 10571 | MLXSW_REG(peabfe), |
3390787b | 10572 | MLXSW_REG(perar), |
aecefac9 | 10573 | MLXSW_REG(ptce3), |
481662a8 | 10574 | MLXSW_REG(percr), |
f1c7d9cc | 10575 | MLXSW_REG(pererp), |
c33d0cb1 | 10576 | MLXSW_REG(iedr), |
746da42a | 10577 | MLXSW_REG(qpts), |
76a4c7d3 | 10578 | MLXSW_REG(qpcr), |
8e9658d5 JP |
10579 | MLXSW_REG(qtct), |
10580 | MLXSW_REG(qeec), | |
e67131d9 | 10581 | MLXSW_REG(qrwe), |
55fb71f4 | 10582 | MLXSW_REG(qpdsm), |
02837d72 | 10583 | MLXSW_REG(qpdpm), |
671ae8af | 10584 | MLXSW_REG(qtctm), |
71147506 | 10585 | MLXSW_REG(qpsc), |
8e9658d5 JP |
10586 | MLXSW_REG(pmlp), |
10587 | MLXSW_REG(pmtu), | |
10588 | MLXSW_REG(ptys), | |
10589 | MLXSW_REG(ppad), | |
10590 | MLXSW_REG(paos), | |
10591 | MLXSW_REG(pfcc), | |
10592 | MLXSW_REG(ppcnt), | |
7136793e | 10593 | MLXSW_REG(plib), |
8e9658d5 JP |
10594 | MLXSW_REG(pptb), |
10595 | MLXSW_REG(pbmc), | |
10596 | MLXSW_REG(pspa), | |
a0c25387 | 10597 | MLXSW_REG(pplr), |
a513b1a5 | 10598 | MLXSW_REG(pmtm), |
8e9658d5 JP |
10599 | MLXSW_REG(htgt), |
10600 | MLXSW_REG(hpkt), | |
10601 | MLXSW_REG(rgcr), | |
10602 | MLXSW_REG(ritr), | |
46a7054e | 10603 | MLXSW_REG(rtar), |
8e9658d5 | 10604 | MLXSW_REG(ratr), |
1e659ebf | 10605 | MLXSW_REG(rtdp), |
ddb362ce | 10606 | MLXSW_REG(rdpm), |
ba73e97a | 10607 | MLXSW_REG(ricnt), |
4fc92846 | 10608 | MLXSW_REG(rrcr), |
8e9658d5 JP |
10609 | MLXSW_REG(ralta), |
10610 | MLXSW_REG(ralst), | |
10611 | MLXSW_REG(raltb), | |
10612 | MLXSW_REG(ralue), | |
10613 | MLXSW_REG(rauht), | |
10614 | MLXSW_REG(raleu), | |
10615 | MLXSW_REG(rauhtd), | |
5080c7e9 | 10616 | MLXSW_REG(rigr2), |
e471859b | 10617 | MLXSW_REG(recr2), |
2e654e33 | 10618 | MLXSW_REG(rmft2), |
8e9658d5 JP |
10619 | MLXSW_REG(mfcr), |
10620 | MLXSW_REG(mfsc), | |
10621 | MLXSW_REG(mfsm), | |
55c63aaa | 10622 | MLXSW_REG(mfsl), |
3760c2b9 | 10623 | MLXSW_REG(fore), |
8e9658d5 JP |
10624 | MLXSW_REG(mtcap), |
10625 | MLXSW_REG(mtmp), | |
5f28ef71 | 10626 | MLXSW_REG(mtbr), |
7ca36994 | 10627 | MLXSW_REG(mcia), |
8e9658d5 JP |
10628 | MLXSW_REG(mpat), |
10629 | MLXSW_REG(mpar), | |
8d77d4bf | 10630 | MLXSW_REG(mgir), |
12b003b2 | 10631 | MLXSW_REG(mrsr), |
8e9658d5 | 10632 | MLXSW_REG(mlcr), |
1078645a | 10633 | MLXSW_REG(mtpps), |
55a8b001 | 10634 | MLXSW_REG(mtutc), |
0677d682 | 10635 | MLXSW_REG(mpsc), |
4f2402d4 | 10636 | MLXSW_REG(mcqi), |
191839de | 10637 | MLXSW_REG(mcc), |
4625d59d | 10638 | MLXSW_REG(mcda), |
5766532a | 10639 | MLXSW_REG(mgpc), |
27f68c08 | 10640 | MLXSW_REG(mprs), |
41ce78b9 | 10641 | MLXSW_REG(mogcr), |
da28e878 | 10642 | MLXSW_REG(mtpppc), |
98b9028e | 10643 | MLXSW_REG(mtpptr), |
4dfecb65 | 10644 | MLXSW_REG(mtptpt), |
7e9561ed | 10645 | MLXSW_REG(mgpir), |
710dd1a0 | 10646 | MLXSW_REG(tngcr), |
c723d19f | 10647 | MLXSW_REG(tnumt), |
fd6db27c | 10648 | MLXSW_REG(tnqcr), |
8efcf6bb | 10649 | MLXSW_REG(tnqdr), |
4a8d1860 | 10650 | MLXSW_REG(tneem), |
a77d5f0b | 10651 | MLXSW_REG(tndem), |
50e6eb2a | 10652 | MLXSW_REG(tnpc), |
14aefd90 | 10653 | MLXSW_REG(tigcr), |
8e9658d5 JP |
10654 | MLXSW_REG(sbpr), |
10655 | MLXSW_REG(sbcm), | |
10656 | MLXSW_REG(sbpm), | |
10657 | MLXSW_REG(sbmm), | |
10658 | MLXSW_REG(sbsr), | |
10659 | MLXSW_REG(sbib), | |
10660 | }; | |
10661 | ||
4ec14b76 IS |
10662 | static inline const char *mlxsw_reg_id_str(u16 reg_id) |
10663 | { | |
8e9658d5 JP |
10664 | const struct mlxsw_reg_info *reg_info; |
10665 | int i; | |
10666 | ||
10667 | for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { | |
10668 | reg_info = mlxsw_reg_infos[i]; | |
10669 | if (reg_info->id == reg_id) | |
10670 | return reg_info->name; | |
4ec14b76 | 10671 | } |
8e9658d5 | 10672 | return "*UNKNOWN*"; |
4ec14b76 IS |
10673 | } |
10674 | ||
10675 | /* PUDE - Port Up / Down Event | |
10676 | * --------------------------- | |
10677 | * Reports the operational state change of a port. | |
10678 | */ | |
10679 | #define MLXSW_REG_PUDE_LEN 0x10 | |
10680 | ||
10681 | /* reg_pude_swid | |
10682 | * Switch partition ID with which to associate the port. | |
10683 | * Access: Index | |
10684 | */ | |
10685 | MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); | |
10686 | ||
10687 | /* reg_pude_local_port | |
10688 | * Local port number. | |
10689 | * Access: Index | |
10690 | */ | |
10691 | MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); | |
10692 | ||
10693 | /* reg_pude_admin_status | |
10694 | * Port administrative state (the desired state). | |
10695 | * 1 - Up. | |
10696 | * 2 - Down. | |
10697 | * 3 - Up once. This means that in case of link failure, the port won't go | |
10698 | * into polling mode, but will wait to be re-enabled by software. | |
10699 | * 4 - Disabled by system. Can only be set by hardware. | |
10700 | * Access: RO | |
10701 | */ | |
10702 | MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); | |
10703 | ||
10704 | /* reg_pude_oper_status | |
10705 | * Port operatioanl state. | |
10706 | * 1 - Up. | |
10707 | * 2 - Down. | |
10708 | * 3 - Down by port failure. This means that the device will not let the | |
10709 | * port up again until explicitly specified by software. | |
10710 | * Access: RO | |
10711 | */ | |
10712 | MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); | |
10713 | ||
10714 | #endif |