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mlxsw: reg: Add ext and tc-cong counter groups
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
CommitLineData
56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
22a67766
JP		 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
56ade8fe
JP		 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
c1f2c6d0 56#include <linux/netlink.h>
56ade8fe 57#include <net/switchdev.h>
763b4b70
YG		 58#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
e7322638 60#include <net/netevent.h>
98d0f7b9 61#include <net/tc_act/tc_sample.h>
5ea1237f 62#include <net/addrconf.h>
56ade8fe
JP		 63
64#include "spectrum.h"
1d20d23c 65#include "pci.h"
56ade8fe
JP		 66#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
ff7b0d27 71#include "spectrum_cnt.h"
230ead01 72#include "spectrum_dpipe.h"
d3b939b8 73#include "spectrum_acl_flex_actions.h"
e5e5c88a 74#include "../mlxfw/mlxfw.h"
56ade8fe 75
6b742199
YG		 76#define MLXSW_FWREV_MAJOR 13
77#define MLXSW_FWREV_MINOR 1420
78#define MLXSW_FWREV_SUBMINOR 122
79
80static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
81 .major = MLXSW_FWREV_MAJOR,
82 .minor = MLXSW_FWREV_MINOR,
83 .subminor = MLXSW_FWREV_SUBMINOR
84};
85
86#define MLXSW_SP_FW_FILENAME \
a4e1ce24 87 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
6b742199
YG		 88 "." __stringify(MLXSW_FWREV_MINOR) \
89 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
90
56ade8fe
JP		 91static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
92static const char mlxsw_sp_driver_version[] = "1.0";
93
94/* tx_hdr_version
95 * Tx header version.
96 * Must be set to 1.
97 */
98MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
99
100/* tx_hdr_ctl
101 * Packet control type.
102 * 0 - Ethernet control (e.g. EMADs, LACP)
103 * 1 - Ethernet data
104 */
105MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
106
107/* tx_hdr_proto
108 * Packet protocol type. Must be set to 1 (Ethernet).
109 */
110MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
111
112/* tx_hdr_rx_is_router
113 * Packet is sent from the router. Valid for data packets only.
114 */
115MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
116
117/* tx_hdr_fid_valid
118 * Indicates if the 'fid' field is valid and should be used for
119 * forwarding lookup. Valid for data packets only.
120 */
121MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
122
123/* tx_hdr_swid
124 * Switch partition ID. Must be set to 0.
125 */
126MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
127
128/* tx_hdr_control_tclass
129 * Indicates if the packet should use the control TClass and not one
130 * of the data TClasses.
131 */
132MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
133
134/* tx_hdr_etclass
135 * Egress TClass to be used on the egress device on the egress port.
136 */
137MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
138
139/* tx_hdr_port_mid
140 * Destination local port for unicast packets.
141 * Destination multicast ID for multicast packets.
142 *
143 * Control packets are directed to a specific egress port, while data
144 * packets are transmitted through the CPU port (0) into the switch partition,
145 * where forwarding rules are applied.
146 */
147MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
148
149/* tx_hdr_fid
150 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
151 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
152 * Valid for data packets only.
153 */
154MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
155
156/* tx_hdr_type
157 * 0 - Data packets
158 * 6 - Control packets
159 */
160MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161
e5e5c88a
YG		 162struct mlxsw_sp_mlxfw_dev {
163 struct mlxfw_dev mlxfw_dev;
164 struct mlxsw_sp *mlxsw_sp;
165};
166
167static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
168 u16 component_index, u32 *p_max_size,
169 u8 *p_align_bits, u16 *p_max_write_size)
170{
171 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
172 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
174 char mcqi_pl[MLXSW_REG_MCQI_LEN];
175 int err;
176
177 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
178 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
179 if (err)
180 return err;
181 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
182 p_max_write_size);
183
184 *p_align_bits = max_t(u8, *p_align_bits, 2);
185 *p_max_write_size = min_t(u16, *p_max_write_size,
186 MLXSW_REG_MCDA_MAX_DATA_LEN);
187 return 0;
188}
189
190static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
191{
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
196 u8 control_state;
197 int err;
198
199 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
200 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
201 if (err)
202 return err;
203
204 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
205 if (control_state != MLXFW_FSM_STATE_IDLE)
206 return -EBUSY;
207
208 mlxsw_reg_mcc_pack(mcc_pl,
209 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
210 0, *fwhandle, 0);
211 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
212}
213
214static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
215 u32 fwhandle, u16 component_index,
216 u32 component_size)
217{
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
222
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
224 component_index, fwhandle, component_size);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226}
227
228static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
229 u32 fwhandle, u8 *data, u16 size,
230 u32 offset)
231{
232 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
233 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
234 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
235 char mcda_pl[MLXSW_REG_MCDA_LEN];
236
237 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
238 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
239}
240
241static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
242 u32 fwhandle, u16 component_index)
243{
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
248
249 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
250 component_index, fwhandle, 0);
251 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
252}
253
254static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
255{
256 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
257 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
258 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
259 char mcc_pl[MLXSW_REG_MCC_LEN];
260
261 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
262 fwhandle, 0);
263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
264}
265
266static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
267 enum mlxfw_fsm_state *fsm_state,
268 enum mlxfw_fsm_state_err *fsm_state_err)
269{
270 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
271 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
272 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
273 char mcc_pl[MLXSW_REG_MCC_LEN];
274 u8 control_state;
275 u8 error_code;
276 int err;
277
278 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
279 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
280 if (err)
281 return err;
282
283 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
284 *fsm_state = control_state;
285 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
286 MLXFW_FSM_STATE_ERR_MAX);
287 return 0;
288}
289
290static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
291{
292 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
293 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
294 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
295 char mcc_pl[MLXSW_REG_MCC_LEN];
296
297 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
298 fwhandle, 0);
299 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
300}
301
302static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
303{
304 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
305 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
307 char mcc_pl[MLXSW_REG_MCC_LEN];
308
309 mlxsw_reg_mcc_pack(mcc_pl,
310 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
311 fwhandle, 0);
312 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
313}
314
315static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
316 .component_query = mlxsw_sp_component_query,
317 .fsm_lock = mlxsw_sp_fsm_lock,
318 .fsm_component_update = mlxsw_sp_fsm_component_update,
319 .fsm_block_download = mlxsw_sp_fsm_block_download,
320 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
321 .fsm_activate = mlxsw_sp_fsm_activate,
322 .fsm_query_state = mlxsw_sp_fsm_query_state,
323 .fsm_cancel = mlxsw_sp_fsm_cancel,
324 .fsm_release = mlxsw_sp_fsm_release
325};
326
ce6ef68f
YG		 327static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
328 const struct firmware *firmware)
329{
330 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
331 .mlxfw_dev = {
332 .ops = &mlxsw_sp_mlxfw_dev_ops,
333 .psid = mlxsw_sp->bus_info->psid,
334 .psid_size = strlen(mlxsw_sp->bus_info->psid),
335 },
336 .mlxsw_sp = mlxsw_sp
337 };
338
339 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
340}
341
6b742199
YG		 342static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
343 const struct mlxsw_fw_rev *b)
344{
345 if (a->major != b->major)
346 return a->major > b->major;
347 if (a->minor != b->minor)
348 return a->minor > b->minor;
349 return a->subminor >= b->subminor;
350}
351
352static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
353{
354 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
6b742199
YG		 355 const struct firmware *firmware;
356 int err;
357
358 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
359 return 0;
360
361 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
362 rev->major, rev->minor, rev->subminor);
363 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
364 MLXSW_SP_FW_FILENAME);
365
366 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
367 mlxsw_sp->bus_info->dev);
368 if (err) {
369 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
370 MLXSW_SP_FW_FILENAME);
371 return err;
372 }
373
ce6ef68f 374 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
6b742199
YG		 375 release_firmware(firmware);
376 return err;
377}
378
1abcbcc2
AS		 379int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
380 unsigned int counter_index, u64 *packets,
381 u64 *bytes)
382{
383 char mgpc_pl[MLXSW_REG_MGPC_LEN];
384 int err;
385
386 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
6bba7e20 387 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 388 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
389 if (err)
390 return err;
7cfcbc75
AS		 391 if (packets)
392 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
393 if (bytes)
394 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
1abcbcc2
AS		 395 return 0;
396}
397
398static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
399 unsigned int counter_index)
400{
401 char mgpc_pl[MLXSW_REG_MGPC_LEN];
402
403 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
6bba7e20 404 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 405 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
406}
407
408int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
409 unsigned int *p_counter_index)
410{
411 int err;
412
413 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
414 p_counter_index);
415 if (err)
416 return err;
417 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
418 if (err)
419 goto err_counter_clear;
420 return 0;
421
422err_counter_clear:
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 *p_counter_index);
425 return err;
426}
427
428void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
429 unsigned int counter_index)
430{
431 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
432 counter_index);
433}
434
56ade8fe
JP		 435static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
436 const struct mlxsw_tx_info *tx_info)
437{
438 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
439
440 memset(txhdr, 0, MLXSW_TXHDR_LEN);
441
442 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
443 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
444 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
445 mlxsw_tx_hdr_swid_set(txhdr, 0);
446 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
447 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
448 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
449}
450
fe9ccc78
IS		 451int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
452 u8 state)
453{
454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
455 enum mlxsw_reg_spms_state spms_state;
456 char *spms_pl;
457 int err;
458
459 switch (state) {
460 case BR_STATE_FORWARDING:
461 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
462 break;
463 case BR_STATE_LEARNING:
464 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
465 break;
466 case BR_STATE_LISTENING: /* fall-through */
467 case BR_STATE_DISABLED: /* fall-through */
468 case BR_STATE_BLOCKING:
469 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
470 break;
471 default:
472 BUG();
473 }
474
475 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
476 if (!spms_pl)
477 return -ENOMEM;
478 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
479 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
480
481 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
482 kfree(spms_pl);
483 return err;
484}
485
56ade8fe
JP		 486static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
487{
5b090740 488 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
56ade8fe
JP		 489 int err;
490
491 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
492 if (err)
493 return err;
494 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
495 return 0;
496}
497
763b4b70
YG		 498static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
499{
763b4b70
YG		 500 int i;
501
c1a38311 502 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 503 return -EIO;
504
c1a38311
JP		 505 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
506 MAX_SPAN);
763b4b70
YG		 507 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
508 sizeof(struct mlxsw_sp_span_entry),
509 GFP_KERNEL);
510 if (!mlxsw_sp->span.entries)
511 return -ENOMEM;
512
513 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
514 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
515
516 return 0;
517}
518
519static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
520{
521 int i;
522
523 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
524 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
525
526 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
527 }
528 kfree(mlxsw_sp->span.entries);
529}
530
531static struct mlxsw_sp_span_entry *
532mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
533{
534 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
535 struct mlxsw_sp_span_entry *span_entry;
536 char mpat_pl[MLXSW_REG_MPAT_LEN];
537 u8 local_port = port->local_port;
538 int index;
539 int i;
540 int err;
541
542 /* find a free entry to use */
543 index = -1;
544 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
545 if (!mlxsw_sp->span.entries[i].used) {
546 index = i;
547 span_entry = &mlxsw_sp->span.entries[i];
548 break;
549 }
550 }
551 if (index < 0)
552 return NULL;
553
554 /* create a new port analayzer entry for local_port */
555 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
556 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
557 if (err)
558 return NULL;
559
560 span_entry->used = true;
561 span_entry->id = index;
2d644d4c 562 span_entry->ref_count = 1;
763b4b70
YG		 563 span_entry->local_port = local_port;
564 return span_entry;
565}
566
567static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
568 struct mlxsw_sp_span_entry *span_entry)
569{
570 u8 local_port = span_entry->local_port;
571 char mpat_pl[MLXSW_REG_MPAT_LEN];
572 int pa_id = span_entry->id;
573
574 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
575 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
576 span_entry->used = false;
577}
578
1a9234e6 579static struct mlxsw_sp_span_entry *
6399ebcc 580mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
763b4b70 581{
763b4b70
YG		 582 int i;
583
584 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
585 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
586
6399ebcc 587 if (curr->used && curr->local_port == local_port)
763b4b70
YG		 588 return curr;
589 }
590 return NULL;
591}
592
1a9234e6
IS		 593static struct mlxsw_sp_span_entry
594*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 595{
596 struct mlxsw_sp_span_entry *span_entry;
597
6399ebcc
YM		 598 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
599 port->local_port);
763b4b70 600 if (span_entry) {
2d644d4c 601 /* Already exists, just take a reference */
763b4b70
YG		 602 span_entry->ref_count++;
603 return span_entry;
604 }
605
606 return mlxsw_sp_span_entry_create(port);
607}
608
609static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
610 struct mlxsw_sp_span_entry *span_entry)
611{
2d644d4c 612 WARN_ON(!span_entry->ref_count);
763b4b70
YG		 613 if (--span_entry->ref_count == 0)
614 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
615 return 0;
616}
617
618static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
619{
620 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
621 struct mlxsw_sp_span_inspected_port *p;
622 int i;
623
624 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
625 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
626
627 list_for_each_entry(p, &curr->bound_ports_list, list)
628 if (p->local_port == port->local_port &&
629 p->type == MLXSW_SP_SPAN_EGRESS)
630 return true;
631 }
632
633 return false;
634}
635
18281f2d
IS		 636static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
637 int mtu)
763b4b70 638{
18281f2d 639 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
763b4b70
YG		 640}
641
642static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
643{
644 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
645 char sbib_pl[MLXSW_REG_SBIB_LEN];
646 int err;
647
648 /* If port is egress mirrored, the shared buffer size should be
649 * updated according to the mtu value
650 */
651 if (mlxsw_sp_span_is_egress_mirror(port)) {
18281f2d
IS		 652 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
653
654 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 655 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
656 if (err) {
657 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
658 return err;
659 }
660 }
661
662 return 0;
663}
664
665static struct mlxsw_sp_span_inspected_port *
666mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry)
668{
669 struct mlxsw_sp_span_inspected_port *p;
670
671 list_for_each_entry(p, &span_entry->bound_ports_list, list)
672 if (port->local_port == p->local_port)
673 return p;
674 return NULL;
675}
676
677static int
678mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
679 struct mlxsw_sp_span_entry *span_entry,
680 enum mlxsw_sp_span_type type)
681{
682 struct mlxsw_sp_span_inspected_port *inspected_port;
683 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
684 char mpar_pl[MLXSW_REG_MPAR_LEN];
685 char sbib_pl[MLXSW_REG_SBIB_LEN];
686 int pa_id = span_entry->id;
687 int err;
688
689 /* if it is an egress SPAN, bind a shared buffer to it */
690 if (type == MLXSW_SP_SPAN_EGRESS) {
18281f2d
IS		 691 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
692 port->dev->mtu);
693
694 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 695 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
696 if (err) {
697 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
698 return err;
699 }
700 }
701
702 /* bind the port to the SPAN entry */
1a9234e6
IS		 703 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
704 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
763b4b70
YG		 705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
706 if (err)
707 goto err_mpar_reg_write;
708
709 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
710 if (!inspected_port) {
711 err = -ENOMEM;
712 goto err_inspected_port_alloc;
713 }
714 inspected_port->local_port = port->local_port;
715 inspected_port->type = type;
716 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
717
718 return 0;
719
720err_mpar_reg_write:
721err_inspected_port_alloc:
722 if (type == MLXSW_SP_SPAN_EGRESS) {
723 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
724 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
725 }
726 return err;
727}
728
729static void
730mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
731 struct mlxsw_sp_span_entry *span_entry,
732 enum mlxsw_sp_span_type type)
733{
734 struct mlxsw_sp_span_inspected_port *inspected_port;
735 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
736 char mpar_pl[MLXSW_REG_MPAR_LEN];
737 char sbib_pl[MLXSW_REG_SBIB_LEN];
738 int pa_id = span_entry->id;
739
740 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
741 if (!inspected_port)
742 return;
743
744 /* remove the inspected port */
1a9234e6
IS		 745 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
746 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
763b4b70
YG		 747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
748
749 /* remove the SBIB buffer if it was egress SPAN */
750 if (type == MLXSW_SP_SPAN_EGRESS) {
751 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
752 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
753 }
754
755 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
756
757 list_del(&inspected_port->list);
758 kfree(inspected_port);
759}
760
761static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
762 struct mlxsw_sp_port *to,
763 enum mlxsw_sp_span_type type)
764{
765 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
766 struct mlxsw_sp_span_entry *span_entry;
767 int err;
768
769 span_entry = mlxsw_sp_span_entry_get(to);
770 if (!span_entry)
771 return -ENOENT;
772
773 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
774 span_entry->id);
775
776 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
777 if (err)
778 goto err_port_bind;
779
780 return 0;
781
782err_port_bind:
783 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
784 return err;
785}
786
787static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
6399ebcc 788 u8 destination_port,
763b4b70
YG		 789 enum mlxsw_sp_span_type type)
790{
791 struct mlxsw_sp_span_entry *span_entry;
792
6399ebcc
YM		 793 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
794 destination_port);
763b4b70
YG		 795 if (!span_entry) {
796 netdev_err(from->dev, "no span entry found\n");
797 return;
798 }
799
800 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
801 span_entry->id);
802 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
803}
804
98d0f7b9
YG		 805static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
806 bool enable, u32 rate)
807{
808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
809 char mpsc_pl[MLXSW_REG_MPSC_LEN];
810
811 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
812 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
813}
814
56ade8fe
JP		 815static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
816 bool is_up)
817{
818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
819 char paos_pl[MLXSW_REG_PAOS_LEN];
820
821 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
822 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
823 MLXSW_PORT_ADMIN_STATUS_DOWN);
824 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
825}
826
56ade8fe
JP		 827static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
828 unsigned char *addr)
829{
830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
831 char ppad_pl[MLXSW_REG_PPAD_LEN];
832
833 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
834 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
835 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
836}
837
838static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
839{
840 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
841 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
842
843 ether_addr_copy(addr, mlxsw_sp->base_mac);
844 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
845 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
846}
847
56ade8fe
JP		 848static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
849{
850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
851 char pmtu_pl[MLXSW_REG_PMTU_LEN];
852 int max_mtu;
853 int err;
854
855 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
856 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
857 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
858 if (err)
859 return err;
860 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
861
862 if (mtu > max_mtu)
863 return -EINVAL;
864
865 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
867}
868
be94535f
IS		 869static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
870{
871 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5b153859 872 char pspa_pl[MLXSW_REG_PSPA_LEN];
be94535f 873
5b153859
IS		 874 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
875 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
be94535f
IS		 876}
877
a1107487 878int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
56ade8fe
JP		 879{
880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
881 char svpe_pl[MLXSW_REG_SVPE_LEN];
882
883 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
884 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
885}
886
7cbc4277
IS		 887int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
888 bool learn_enable)
56ade8fe
JP		 889{
890 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
891 char *spvmlr_pl;
892 int err;
893
894 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
895 if (!spvmlr_pl)
896 return -ENOMEM;
7cbc4277
IS		 897 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
898 learn_enable);
56ade8fe
JP		 899 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
900 kfree(spvmlr_pl);
901 return err;
902}
903
b02eae9b
IS		 904static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
905 u16 vid)
906{
907 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
908 char spvid_pl[MLXSW_REG_SPVID_LEN];
909
910 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
912}
913
914static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
915 bool allow)
916{
917 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
918 char spaft_pl[MLXSW_REG_SPAFT_LEN];
919
920 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
922}
923
924int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
925{
926 int err;
927
928 if (!vid) {
929 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
930 if (err)
931 return err;
932 } else {
933 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
934 if (err)
935 return err;
936 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
937 if (err)
938 goto err_port_allow_untagged_set;
939 }
940
941 mlxsw_sp_port->pvid = vid;
942 return 0;
943
944err_port_allow_untagged_set:
945 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
946 return err;
947}
948
56ade8fe
JP		 949static int
950mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
951{
952 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
953 char sspr_pl[MLXSW_REG_SSPR_LEN];
954
955 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
956 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
957}
958
d664b41e
IS		 959static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
960 u8 local_port, u8 *p_module,
961 u8 *p_width, u8 *p_lane)
56ade8fe 962{
56ade8fe
JP		 963 char pmlp_pl[MLXSW_REG_PMLP_LEN];
964 int err;
965
558c2d5e 966 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 967 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
968 if (err)
969 return err;
558c2d5e
IS		 970 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
971 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 972 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 973 return 0;
974}
975
2e915e0b 976static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
18f1e70c
IS		 977 u8 module, u8 width, u8 lane)
978{
2e915e0b 979 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
18f1e70c
IS		 980 char pmlp_pl[MLXSW_REG_PMLP_LEN];
981 int i;
982
2e915e0b 983 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
18f1e70c
IS		 984 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
985 for (i = 0; i < width; i++) {
986 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
987 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
988 }
989
990 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
991}
992
2e915e0b 993static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
3e9b27b8 994{
2e915e0b 995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3e9b27b8
IS		 996 char pmlp_pl[MLXSW_REG_PMLP_LEN];
997
2e915e0b 998 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
3e9b27b8
IS		 999 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1001}
1002
56ade8fe
JP		 1003static int mlxsw_sp_port_open(struct net_device *dev)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 int err;
1007
1008 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1009 if (err)
1010 return err;
1011 netif_start_queue(dev);
1012 return 0;
1013}
1014
1015static int mlxsw_sp_port_stop(struct net_device *dev)
1016{
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018
1019 netif_stop_queue(dev);
1020 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1021}
1022
1023static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1024 struct net_device *dev)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1028 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1029 const struct mlxsw_tx_info tx_info = {
1030 .local_port = mlxsw_sp_port->local_port,
1031 .is_emad = false,
1032 };
1033 u64 len;
1034 int err;
1035
307c2431 1036 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 1037 return NETDEV_TX_BUSY;
1038
1039 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1040 struct sk_buff *skb_orig = skb;
1041
1042 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1043 if (!skb) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 dev_kfree_skb_any(skb_orig);
1046 return NETDEV_TX_OK;
1047 }
36bf38d1 1048 dev_consume_skb_any(skb_orig);
56ade8fe
JP		 1049 }
1050
1051 if (eth_skb_pad(skb)) {
1052 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1053 return NETDEV_TX_OK;
1054 }
1055
1056 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 1057 /* TX header is consumed by HW on the way so we shouldn't count its
1058 * bytes as being sent.
1059 */
1060 len = skb->len - MLXSW_TXHDR_LEN;
1061
56ade8fe
JP		 1062 /* Due to a race we might fail here because of a full queue. In that
1063 * unlikely case we simply drop the packet.
1064 */
307c2431 1065 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 1066
1067 if (!err) {
1068 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1069 u64_stats_update_begin(&pcpu_stats->syncp);
1070 pcpu_stats->tx_packets++;
1071 pcpu_stats->tx_bytes += len;
1072 u64_stats_update_end(&pcpu_stats->syncp);
1073 } else {
1074 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1075 dev_kfree_skb_any(skb);
1076 }
1077 return NETDEV_TX_OK;
1078}
1079
c5b9b518
JP		 1080static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1081{
1082}
1083
56ade8fe
JP		 1084static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1085{
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087 struct sockaddr *addr = p;
1088 int err;
1089
1090 if (!is_valid_ether_addr(addr->sa_data))
1091 return -EADDRNOTAVAIL;
1092
1093 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1094 if (err)
1095 return err;
1096 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1097 return 0;
1098}
1099
18281f2d
IS		 1100static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1101 int mtu)
ff6551ec 1102{
18281f2d 1103 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
f417f04d 1104}
8e8dfe9f 1105
f417f04d 1106#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
18281f2d
IS		 1107
1108static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1109 u16 delay)
f417f04d 1110{
18281f2d
IS		 1111 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1112 BITS_PER_BYTE));
1113 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1114 mtu);
f417f04d
IS		 1115}
1116
18281f2d 1117/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
f417f04d
IS		 1118 * Assumes 100m cable and maximum MTU.
1119 */
18281f2d
IS		 1120#define MLXSW_SP_PAUSE_DELAY 58752
1121
1122static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1123 u16 delay, bool pfc, bool pause)
f417f04d
IS		 1124{
1125 if (pfc)
18281f2d 1126 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
f417f04d 1127 else if (pause)
18281f2d 1128 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
f417f04d
IS		 1129 else
1130 return 0;
1131}
9f7ec052 1132
f417f04d
IS		 1133static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1134 bool lossy)
1135{
1136 if (lossy)
1137 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
d81a6bdb 1138 else
f417f04d
IS		 1139 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1140 thres);
8e8dfe9f
IS		 1141}
1142
1143int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 1144 u8 *prio_tc, bool pause_en,
1145 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 1146{
1147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 1148 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1149 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 1150 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 1151 int i, j, err;
ff6551ec
IS		 1152
1153 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1154 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1155 if (err)
1156 return err;
8e8dfe9f
IS		 1157
1158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1159 bool configure = false;
d81a6bdb 1160 bool pfc = false;
f417f04d
IS		 1161 bool lossy;
1162 u16 thres;
8e8dfe9f
IS		 1163
1164 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1165 if (prio_tc[j] == i) {
d81a6bdb 1166 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 1167 configure = true;
1168 break;
1169 }
1170 }
1171
1172 if (!configure)
1173 continue;
f417f04d
IS		 1174
1175 lossy = !(pfc || pause_en);
18281f2d
IS		 1176 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1177 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1178 pause_en);
f417f04d 1179 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
8e8dfe9f
IS		 1180 }
1181
ff6551ec
IS		 1182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1183}
1184
8e8dfe9f 1185static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 1186 int mtu, bool pause_en)
8e8dfe9f
IS		 1187{
1188 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1189 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 1190 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 1191 u8 *prio_tc;
1192
1193 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 1194 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 1195
9f7ec052 1196 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 1197 pause_en, my_pfc);
8e8dfe9f
IS		 1198}
1199
56ade8fe
JP		 1200static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 1203 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 1204 int err;
1205
9f7ec052 1206 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 1207 if (err)
1208 return err;
763b4b70
YG		 1209 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1210 if (err)
1211 goto err_span_port_mtu_update;
ff6551ec
IS		 1212 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1213 if (err)
1214 goto err_port_mtu_set;
56ade8fe
JP		 1215 dev->mtu = mtu;
1216 return 0;
ff6551ec
IS		 1217
1218err_port_mtu_set:
763b4b70
YG		 1219 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1220err_span_port_mtu_update:
9f7ec052 1221 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 1222 return err;
56ade8fe
JP		 1223}
1224
4bdcc6ca 1225static int
fc1bbb0f
NF		 1226mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1227 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 1228{
1229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1230 struct mlxsw_sp_port_pcpu_stats *p;
1231 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1232 u32 tx_dropped = 0;
1233 unsigned int start;
1234 int i;
1235
1236 for_each_possible_cpu(i) {
1237 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1238 do {
1239 start = u64_stats_fetch_begin_irq(&p->syncp);
1240 rx_packets = p->rx_packets;
1241 rx_bytes = p->rx_bytes;
1242 tx_packets = p->tx_packets;
1243 tx_bytes = p->tx_bytes;
1244 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1245
1246 stats->rx_packets += rx_packets;
1247 stats->rx_bytes += rx_bytes;
1248 stats->tx_packets += tx_packets;
1249 stats->tx_bytes += tx_bytes;
1250 /* tx_dropped is u32, updated without syncp protection. */
1251 tx_dropped += p->tx_dropped;
1252 }
1253 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 1254 return 0;
1255}
1256
3df5b3c6 1257static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
fc1bbb0f
NF		 1258{
1259 switch (attr_id) {
1260 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
4bdcc6ca
OG		 1267static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1268 void *sp)
fc1bbb0f
NF		 1269{
1270 switch (attr_id) {
1271 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1272 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1273 }
1274
1275 return -EINVAL;
1276}
1277
1278static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1279 int prio, char *ppcnt_pl)
1280{
1281 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1283
1284 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1285 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1286}
1287
1288static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1289 struct rtnl_link_stats64 *stats)
1290{
1291 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1292 int err;
1293
1294 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1295 0, ppcnt_pl);
1296 if (err)
1297 goto out;
1298
1299 stats->tx_packets =
1300 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1301 stats->rx_packets =
1302 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1303 stats->tx_bytes =
1304 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_bytes =
1306 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1307 stats->multicast =
1308 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1309
1310 stats->rx_crc_errors =
1311 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1312 stats->rx_frame_errors =
1313 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1314
1315 stats->rx_length_errors = (
1316 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1318 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1319
1320 stats->rx_errors = (stats->rx_crc_errors +
1321 stats->rx_frame_errors + stats->rx_length_errors);
1322
1323out:
1324 return err;
1325}
1326
1327static void update_stats_cache(struct work_struct *work)
1328{
1329 struct mlxsw_sp_port *mlxsw_sp_port =
1330 container_of(work, struct mlxsw_sp_port,
9deef43d 1331 periodic_hw_stats.update_dw.work);
fc1bbb0f
NF		 1332
1333 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1334 goto out;
1335
1336 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
9deef43d 1337 &mlxsw_sp_port->periodic_hw_stats.stats);
fc1bbb0f
NF		 1338
1339out:
9deef43d 1340 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 1341 MLXSW_HW_STATS_UPDATE_TIME);
1342}
1343
1344/* Return the stats from a cache that is updated periodically,
1345 * as this function might get called in an atomic context.
1346 */
bc1f4470 1347static void
fc1bbb0f
NF		 1348mlxsw_sp_port_get_stats64(struct net_device *dev,
1349 struct rtnl_link_stats64 *stats)
1350{
1351 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1352
9deef43d 1353 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
56ade8fe
JP		 1354}
1355
93cd0813
JP		 1356static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1357 u16 vid_begin, u16 vid_end,
1358 bool is_member, bool untagged)
56ade8fe
JP		 1359{
1360 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1361 char *spvm_pl;
1362 int err;
1363
1364 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1365 if (!spvm_pl)
1366 return -ENOMEM;
1367
1368 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1369 vid_end, is_member, untagged);
1370 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1371 kfree(spvm_pl);
1372 return err;
1373}
1374
93cd0813
JP		 1375int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1376 u16 vid_end, bool is_member, bool untagged)
1377{
1378 u16 vid, vid_e;
1379 int err;
1380
1381 for (vid = vid_begin; vid <= vid_end;
1382 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1383 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1384 vid_end);
1385
1386 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1387 is_member, untagged);
1388 if (err)
1389 return err;
1390 }
1391
1392 return 0;
1393}
1394
c57529e1 1395static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
7f71eb46 1396{
c57529e1 1397 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
7f71eb46 1398
c57529e1
IS		 1399 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1400 &mlxsw_sp_port->vlans_list, list)
1401 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
7f71eb46
IS		 1402}
1403
31a08a52
IS		 1404static struct mlxsw_sp_port_vlan *
1405mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1406{
1407 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
c57529e1
IS		 1408 bool untagged = vid == 1;
1409 int err;
1410
1411 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1412 if (err)
1413 return ERR_PTR(err);
31a08a52
IS		 1414
1415 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
c57529e1
IS		 1416 if (!mlxsw_sp_port_vlan) {
1417 err = -ENOMEM;
1418 goto err_port_vlan_alloc;
1419 }
31a08a52
IS		 1420
1421 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1422 mlxsw_sp_port_vlan->vid = vid;
1423 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1424
1425 return mlxsw_sp_port_vlan;
c57529e1
IS		 1426
1427err_port_vlan_alloc:
1428 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1429 return ERR_PTR(err);
31a08a52
IS		 1430}
1431
1432static void
1433mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1434{
c57529e1
IS		 1435 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1436 u16 vid = mlxsw_sp_port_vlan->vid;
7cbecf24 1437
31a08a52
IS		 1438 list_del(&mlxsw_sp_port_vlan->list);
1439 kfree(mlxsw_sp_port_vlan);
c57529e1
IS		 1440 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1441}
1442
1443struct mlxsw_sp_port_vlan *
1444mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1445{
1446 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1447
1448 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1449 if (mlxsw_sp_port_vlan)
1450 return mlxsw_sp_port_vlan;
1451
1452 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1453}
1454
1455void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1456{
a1107487
IS		 1457 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1458
c57529e1
IS		 1459 if (mlxsw_sp_port_vlan->bridge_port)
1460 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
a1107487
IS		 1461 else if (fid)
1462 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
c57529e1
IS		 1463
1464 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
31a08a52
IS		 1465}
1466
05978481
IS		 1467static int mlxsw_sp_port_add_vid(struct net_device *dev,
1468 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1469{
1470 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
56ade8fe
JP		 1471
1472 /* VLAN 0 is added to HW filter when device goes up, but it is
1473 * reserved in our case, so simply return.
1474 */
1475 if (!vid)
1476 return 0;
1477
c57529e1 1478 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
56ade8fe
JP		 1479}
1480
32d863fb
IS		 1481static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1482 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1483{
1484 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
31a08a52 1485 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 1486
1487 /* VLAN 0 is removed from HW filter when device goes down, but
1488 * it is reserved in our case, so simply return.
1489 */
1490 if (!vid)
1491 return 0;
1492
31a08a52 1493 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
c57529e1 1494 if (!mlxsw_sp_port_vlan)
56ade8fe 1495 return 0;
c57529e1 1496 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
31a08a52 1497
56ade8fe
JP		 1498 return 0;
1499}
1500
2bf9a586
IS		 1501static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1502 size_t len)
1503{
1504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1505 u8 module = mlxsw_sp_port->mapping.module;
1506 u8 width = mlxsw_sp_port->mapping.width;
1507 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1508 int err;
1509
2bf9a586
IS		 1510 if (!mlxsw_sp_port->split)
1511 err = snprintf(name, len, "p%d", module + 1);
1512 else
1513 err = snprintf(name, len, "p%ds%d", module + 1,
1514 lane / width);
1515
1516 if (err >= len)
1517 return -EINVAL;
1518
1519 return 0;
1520}
1521
763b4b70 1522static struct mlxsw_sp_port_mall_tc_entry *
65acb5d0
YG		 1523mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1524 unsigned long cookie) {
763b4b70
YG		 1525 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1526
1527 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1528 if (mall_tc_entry->cookie == cookie)
1529 return mall_tc_entry;
1530
1531 return NULL;
1532}
1533
1534static int
1535mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
65acb5d0 1536 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
763b4b70
YG		 1537 const struct tc_action *a,
1538 bool ingress)
1539{
763b4b70
YG		 1540 struct net *net = dev_net(mlxsw_sp_port->dev);
1541 enum mlxsw_sp_span_type span_type;
1542 struct mlxsw_sp_port *to_port;
1543 struct net_device *to_dev;
1544 int ifindex;
763b4b70
YG		 1545
1546 ifindex = tcf_mirred_ifindex(a);
1547 to_dev = __dev_get_by_index(net, ifindex);
1548 if (!to_dev) {
1549 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1550 return -EINVAL;
1551 }
1552
1553 if (!mlxsw_sp_port_dev_check(to_dev)) {
1554 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
e915ac68 1555 return -EOPNOTSUPP;
763b4b70
YG		 1556 }
1557 to_port = netdev_priv(to_dev);
1558
65acb5d0
YG		 1559 mirror->to_local_port = to_port->local_port;
1560 mirror->ingress = ingress;
763b4b70 1561 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
65acb5d0
YG		 1562 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1563}
763b4b70 1564
65acb5d0
YG		 1565static void
1566mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1567 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1568{
65acb5d0 1569 enum mlxsw_sp_span_type span_type;
65acb5d0 1570
65acb5d0
YG		 1571 span_type = mirror->ingress ?
1572 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
6399ebcc
YM		 1573 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1574 span_type);
763b4b70
YG		 1575}
1576
98d0f7b9
YG		 1577static int
1578mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1579 struct tc_cls_matchall_offload *cls,
1580 const struct tc_action *a,
1581 bool ingress)
1582{
1583 int err;
1584
1585 if (!mlxsw_sp_port->sample)
1586 return -EOPNOTSUPP;
1587 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1588 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1589 return -EEXIST;
1590 }
1591 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1592 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1593 return -EOPNOTSUPP;
1594 }
1595
1596 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1597 tcf_sample_psample_group(a));
1598 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1599 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1600 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1601
1602 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1603 if (err)
1604 goto err_port_sample_set;
1605 return 0;
1606
1607err_port_sample_set:
1608 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1609 return err;
1610}
1611
1612static void
1613mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1614{
1615 if (!mlxsw_sp_port->sample)
1616 return;
1617
1618 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1619 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1620}
1621
763b4b70 1622static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1623 struct tc_cls_matchall_offload *f,
763b4b70
YG		 1624 bool ingress)
1625{
65acb5d0 1626 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
5fd9fc4e 1627 __be16 protocol = f->common.protocol;
763b4b70 1628 const struct tc_action *a;
22dc13c8 1629 LIST_HEAD(actions);
763b4b70
YG		 1630 int err;
1631
9cbf14ed 1632 if (!tcf_exts_has_one_action(f->exts)) {
763b4b70 1633 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
e915ac68 1634 return -EOPNOTSUPP;
763b4b70
YG		 1635 }
1636
65acb5d0
YG		 1637 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1638 if (!mall_tc_entry)
1639 return -ENOMEM;
9cbf14ed 1640 mall_tc_entry->cookie = f->cookie;
65acb5d0 1641
9cbf14ed 1642 tcf_exts_to_list(f->exts, &actions);
65acb5d0 1643 a = list_first_entry(&actions, struct tc_action, list);
86cb13e4 1644
65acb5d0
YG		 1645 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1646 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1647
1648 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1649 mirror = &mall_tc_entry->mirror;
1650 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1651 mirror, a, ingress);
98d0f7b9
YG		 1652 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1653 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
9cbf14ed 1654 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
98d0f7b9 1655 a, ingress);
65acb5d0
YG		 1656 } else {
1657 err = -EOPNOTSUPP;
763b4b70
YG		 1658 }
1659
65acb5d0
YG		 1660 if (err)
1661 goto err_add_action;
1662
1663 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
763b4b70 1664 return 0;
65acb5d0
YG		 1665
1666err_add_action:
1667 kfree(mall_tc_entry);
1668 return err;
763b4b70
YG		 1669}
1670
1671static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1672 struct tc_cls_matchall_offload *f)
763b4b70 1673{
763b4b70 1674 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
763b4b70 1675
65acb5d0 1676 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
9cbf14ed 1677 f->cookie);
763b4b70
YG		 1678 if (!mall_tc_entry) {
1679 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1680 return;
1681 }
65acb5d0 1682 list_del(&mall_tc_entry->list);
763b4b70
YG		 1683
1684 switch (mall_tc_entry->type) {
1685 case MLXSW_SP_PORT_MALL_MIRROR:
65acb5d0
YG		 1686 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1687 &mall_tc_entry->mirror);
763b4b70 1688 break;
98d0f7b9
YG		 1689 case MLXSW_SP_PORT_MALL_SAMPLE:
1690 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1691 break;
763b4b70
YG		 1692 default:
1693 WARN_ON(1);
1694 }
1695
763b4b70
YG		 1696 kfree(mall_tc_entry);
1697}
1698
fd33f1df 1699static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
eb49cfaa
JP		 1700 struct tc_cls_matchall_offload *f,
1701 bool ingress)
fd33f1df 1702{
5fd9fc4e 1703 if (f->common.chain_index)
fd33f1df
JP		 1704 return -EOPNOTSUPP;
1705
1706 switch (f->command) {
1707 case TC_CLSMATCHALL_REPLACE:
5fd9fc4e 1708 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
fd33f1df
JP		 1709 ingress);
1710 case TC_CLSMATCHALL_DESTROY:
1711 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1712 return 0;
1713 default:
1714 return -EOPNOTSUPP;
1715 }
1716}
1717
1718static int
1719mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
eb49cfaa
JP		 1720 struct tc_cls_flower_offload *f,
1721 bool ingress)
763b4b70 1722{
fd33f1df
JP		 1723 switch (f->command) {
1724 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 1725 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
fd33f1df
JP		 1726 case TC_CLSFLOWER_DESTROY:
1727 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
1728 return 0;
1729 case TC_CLSFLOWER_STATS:
1730 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
1731 default:
1732 return -EOPNOTSUPP;
1733 }
1734}
1735
eb49cfaa
JP		 1736static int mlxsw_sp_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1737 void *cb_priv, bool ingress)
1738{
1739 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1740
44ae12a7
JP		 1741 if (!tc_can_offload(mlxsw_sp_port->dev))
1742 return -EOPNOTSUPP;
1743
eb49cfaa
JP		 1744 switch (type) {
1745 case TC_SETUP_CLSMATCHALL:
1746 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1747 ingress);
1748 case TC_SETUP_CLSFLOWER:
1749 return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port, type_data,
1750 ingress);
1751 default:
1752 return -EOPNOTSUPP;
1753 }
1754}
1755
1756static int mlxsw_sp_setup_tc_block_cb_ig(enum tc_setup_type type,
1757 void *type_data, void *cb_priv)
1758{
1759 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, true);
1760}
1761
1762static int mlxsw_sp_setup_tc_block_cb_eg(enum tc_setup_type type,
1763 void *type_data, void *cb_priv)
1764{
1765 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, false);
1766}
1767
1768static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1769 struct tc_block_offload *f)
1770{
1771 tc_setup_cb_t *cb;
1772
1773 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
1774 cb = mlxsw_sp_setup_tc_block_cb_ig;
1775 else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS)
1776 cb = mlxsw_sp_setup_tc_block_cb_eg;
1777 else
1778 return -EOPNOTSUPP;
1779
1780 switch (f->command) {
1781 case TC_BLOCK_BIND:
1782 return tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1783 mlxsw_sp_port);
1784 case TC_BLOCK_UNBIND:
1785 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1786 return 0;
1787 default:
1788 return -EOPNOTSUPP;
1789 }
1790}
1791
fd33f1df 1792static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1793 void *type_data)
fd33f1df
JP		 1794{
1795 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1796
2572ac53 1797 switch (type) {
eb49cfaa
JP		 1798 case TC_SETUP_BLOCK:
1799 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
96f17e07
NF		 1800 case TC_SETUP_QDISC_RED:
1801 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
2572ac53
JP		 1802 default:
1803 return -EOPNOTSUPP;
763b4b70 1804 }
763b4b70
YG		 1805}
1806
56ade8fe
JP		 1807static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1808 .ndo_open = mlxsw_sp_port_open,
1809 .ndo_stop = mlxsw_sp_port_stop,
1810 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 1811 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 1812 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 1813 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1814 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1815 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 1816 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1817 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 1818 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1819 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
2bf9a586 1820 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 1821};
1822
1823static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1824 struct ethtool_drvinfo *drvinfo)
1825{
1826 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1827 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1828
1829 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1830 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1831 sizeof(drvinfo->version));
1832 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1833 "%d.%d.%d",
1834 mlxsw_sp->bus_info->fw_rev.major,
1835 mlxsw_sp->bus_info->fw_rev.minor,
1836 mlxsw_sp->bus_info->fw_rev.subminor);
1837 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1838 sizeof(drvinfo->bus_info));
1839}
1840
9f7ec052
IS		 1841static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1842 struct ethtool_pauseparam *pause)
1843{
1844 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1845
1846 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1847 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1848}
1849
1850static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1851 struct ethtool_pauseparam *pause)
1852{
1853 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1854
1855 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1856 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1857 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1858
1859 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1860 pfcc_pl);
1861}
1862
1863static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1864 struct ethtool_pauseparam *pause)
1865{
1866 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1867 bool pause_en = pause->tx_pause || pause->rx_pause;
1868 int err;
1869
d81a6bdb
IS		 1870 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1871 netdev_err(dev, "PFC already enabled on port\n");
1872 return -EINVAL;
1873 }
1874
9f7ec052
IS		 1875 if (pause->autoneg) {
1876 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1877 return -EINVAL;
1878 }
1879
1880 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1881 if (err) {
1882 netdev_err(dev, "Failed to configure port's headroom\n");
1883 return err;
1884 }
1885
1886 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1887 if (err) {
1888 netdev_err(dev, "Failed to set PAUSE parameters\n");
1889 goto err_port_pause_configure;
1890 }
1891
1892 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1893 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1894
1895 return 0;
1896
1897err_port_pause_configure:
1898 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1899 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1900 return err;
1901}
1902
56ade8fe
JP		 1903struct mlxsw_sp_port_hw_stats {
1904 char str[ETH_GSTRING_LEN];
412791df 1905 u64 (*getter)(const char *payload);
18281f2d 1906 bool cells_bytes;
56ade8fe
JP		 1907};
1908
7ed674bc 1909static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 1910 {
1911 .str = "a_frames_transmitted_ok",
1912 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1913 },
1914 {
1915 .str = "a_frames_received_ok",
1916 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1917 },
1918 {
1919 .str = "a_frame_check_sequence_errors",
1920 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1921 },
1922 {
1923 .str = "a_alignment_errors",
1924 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1925 },
1926 {
1927 .str = "a_octets_transmitted_ok",
1928 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1929 },
1930 {
1931 .str = "a_octets_received_ok",
1932 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1933 },
1934 {
1935 .str = "a_multicast_frames_xmitted_ok",
1936 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1937 },
1938 {
1939 .str = "a_broadcast_frames_xmitted_ok",
1940 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1941 },
1942 {
1943 .str = "a_multicast_frames_received_ok",
1944 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1945 },
1946 {
1947 .str = "a_broadcast_frames_received_ok",
1948 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1949 },
1950 {
1951 .str = "a_in_range_length_errors",
1952 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1953 },
1954 {
1955 .str = "a_out_of_range_length_field",
1956 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1957 },
1958 {
1959 .str = "a_frame_too_long_errors",
1960 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1961 },
1962 {
1963 .str = "a_symbol_error_during_carrier",
1964 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1965 },
1966 {
1967 .str = "a_mac_control_frames_transmitted",
1968 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1969 },
1970 {
1971 .str = "a_mac_control_frames_received",
1972 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1973 },
1974 {
1975 .str = "a_unsupported_opcodes_received",
1976 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1977 },
1978 {
1979 .str = "a_pause_mac_ctrl_frames_received",
1980 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1981 },
1982 {
1983 .str = "a_pause_mac_ctrl_frames_xmitted",
1984 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1985 },
1986};
1987
1988#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1989
7ed674bc
IS		 1990static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1991 {
1992 .str = "rx_octets_prio",
1993 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1994 },
1995 {
1996 .str = "rx_frames_prio",
1997 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1998 },
1999 {
2000 .str = "tx_octets_prio",
2001 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2002 },
2003 {
2004 .str = "tx_frames_prio",
2005 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2006 },
2007 {
2008 .str = "rx_pause_prio",
2009 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2010 },
2011 {
2012 .str = "rx_pause_duration_prio",
2013 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2014 },
2015 {
2016 .str = "tx_pause_prio",
2017 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2018 },
2019 {
2020 .str = "tx_pause_duration_prio",
2021 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2022 },
2023};
2024
2025#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2026
df4750e8
IS		 2027static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2028 {
2029 .str = "tc_transmit_queue_tc",
18281f2d
IS		 2030 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2031 .cells_bytes = true,
df4750e8
IS		 2032 },
2033 {
2034 .str = "tc_no_buffer_discard_uc_tc",
2035 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2036 },
2037};
2038
2039#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2040
7ed674bc 2041#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 2042 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2043 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 2044 IEEE_8021QAZ_MAX_TCS)
2045
2046static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2047{
2048 int i;
2049
2050 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2051 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2052 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2053 *p += ETH_GSTRING_LEN;
2054 }
2055}
2056
df4750e8
IS		 2057static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2058{
2059 int i;
2060
2061 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2062 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2063 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2064 *p += ETH_GSTRING_LEN;
2065 }
2066}
2067
56ade8fe
JP		 2068static void mlxsw_sp_port_get_strings(struct net_device *dev,
2069 u32 stringset, u8 *data)
2070{
2071 u8 *p = data;
2072 int i;
2073
2074 switch (stringset) {
2075 case ETH_SS_STATS:
2076 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2077 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2078 ETH_GSTRING_LEN);
2079 p += ETH_GSTRING_LEN;
2080 }
7ed674bc
IS		 2081
2082 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2083 mlxsw_sp_port_get_prio_strings(&p, i);
2084
df4750e8
IS		 2085 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2086 mlxsw_sp_port_get_tc_strings(&p, i);
2087
56ade8fe
JP		 2088 break;
2089 }
2090}
2091
3a66ee38
IS		 2092static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2093 enum ethtool_phys_id_state state)
2094{
2095 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2096 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2097 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2098 bool active;
2099
2100 switch (state) {
2101 case ETHTOOL_ID_ACTIVE:
2102 active = true;
2103 break;
2104 case ETHTOOL_ID_INACTIVE:
2105 active = false;
2106 break;
2107 default:
2108 return -EOPNOTSUPP;
2109 }
2110
2111 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2112 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2113}
2114
7ed674bc
IS		 2115static int
2116mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2117 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2118{
2119 switch (grp) {
2120 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2121 *p_hw_stats = mlxsw_sp_port_hw_stats;
2122 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2123 break;
2124 case MLXSW_REG_PPCNT_PRIO_CNT:
2125 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2126 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2127 break;
df4750e8
IS		 2128 case MLXSW_REG_PPCNT_TC_CNT:
2129 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2130 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2131 break;
7ed674bc
IS		 2132 default:
2133 WARN_ON(1);
e915ac68 2134 return -EOPNOTSUPP;
7ed674bc
IS		 2135 }
2136 return 0;
2137}
2138
2139static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2140 enum mlxsw_reg_ppcnt_grp grp, int prio,
2141 u64 *data, int data_index)
56ade8fe 2142{
18281f2d
IS		 2143 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2144 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
7ed674bc 2145 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 2146 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 2147 int i, len;
56ade8fe
JP		 2148 int err;
2149
7ed674bc
IS		 2150 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2151 if (err)
2152 return;
fc1bbb0f 2153 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
18281f2d 2154 for (i = 0; i < len; i++) {
faac0ff0 2155 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
18281f2d
IS		 2156 if (!hw_stats[i].cells_bytes)
2157 continue;
2158 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2159 data[data_index + i]);
2160 }
7ed674bc
IS		 2161}
2162
2163static void mlxsw_sp_port_get_stats(struct net_device *dev,
2164 struct ethtool_stats *stats, u64 *data)
2165{
2166 int i, data_index = 0;
2167
2168 /* IEEE 802.3 Counters */
2169 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2170 data, data_index);
2171 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2172
2173 /* Per-Priority Counters */
2174 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2175 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2176 data, data_index);
2177 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2178 }
df4750e8
IS		 2179
2180 /* Per-TC Counters */
2181 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2182 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2183 data, data_index);
2184 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2185 }
56ade8fe
JP		 2186}
2187
2188static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2189{
2190 switch (sset) {
2191 case ETH_SS_STATS:
7ed674bc 2192 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 2193 default:
2194 return -EOPNOTSUPP;
2195 }
2196}
2197
2198struct mlxsw_sp_port_link_mode {
b9d66a36 2199 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 2200 u32 mask;
56ade8fe
JP		 2201 u32 speed;
2202};
2203
2204static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2205 {
2206 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 2207 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2208 .speed = SPEED_100,
56ade8fe
JP		 2209 },
2210 {
2211 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2212 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 2213 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2214 .speed = SPEED_1000,
56ade8fe
JP		 2215 },
2216 {
2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 2218 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2219 .speed = SPEED_10000,
56ade8fe
JP		 2220 },
2221 {
2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2223 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 2224 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2225 .speed = SPEED_10000,
56ade8fe
JP		 2226 },
2227 {
2228 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2229 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2230 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2231 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 2232 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2233 .speed = SPEED_10000,
56ade8fe
JP		 2234 },
2235 {
2236 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 2237 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2238 .speed = SPEED_20000,
56ade8fe
JP		 2239 },
2240 {
2241 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 2242 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2243 .speed = SPEED_40000,
56ade8fe
JP		 2244 },
2245 {
2246 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 2247 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2248 .speed = SPEED_40000,
56ade8fe
JP		 2249 },
2250 {
2251 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 2252 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2253 .speed = SPEED_40000,
56ade8fe
JP		 2254 },
2255 {
2256 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 2257 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2258 .speed = SPEED_40000,
2259 },
2260 {
2261 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2262 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2263 .speed = SPEED_25000,
2264 },
2265 {
2266 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2267 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2268 .speed = SPEED_25000,
2269 },
2270 {
2271 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2272 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2273 .speed = SPEED_25000,
56ade8fe
JP		 2274 },
2275 {
b9d66a36
IS		 2276 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2277 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2278 .speed = SPEED_25000,
56ade8fe
JP		 2279 },
2280 {
b9d66a36
IS		 2281 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2282 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2283 .speed = SPEED_50000,
2284 },
2285 {
2286 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2287 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2288 .speed = SPEED_50000,
2289 },
2290 {
2291 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2292 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2293 .speed = SPEED_50000,
56ade8fe
JP		 2294 },
2295 {
2296 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 2297 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2298 .speed = SPEED_56000,
56ade8fe
JP		 2299 },
2300 {
b9d66a36
IS		 2301 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2302 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2303 .speed = SPEED_56000,
2304 },
2305 {
2306 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2307 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2308 .speed = SPEED_56000,
2309 },
2310 {
2311 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2312 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2313 .speed = SPEED_56000,
2314 },
2315 {
2316 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2317 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2318 .speed = SPEED_100000,
2319 },
2320 {
2321 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2322 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2323 .speed = SPEED_100000,
2324 },
2325 {
2326 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2327 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2328 .speed = SPEED_100000,
2329 },
2330 {
2331 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2332 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2333 .speed = SPEED_100000,
56ade8fe
JP		 2334 },
2335};
2336
2337#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2338
b9d66a36
IS		 2339static void
2340mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2341 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2342{
2343 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2344 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2345 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2346 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2347 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2348 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 2349 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 2350
2351 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2352 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2353 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2354 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2355 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 2356 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 2357}
2358
b9d66a36 2359static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 2360{
56ade8fe
JP		 2361 int i;
2362
2363 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2364 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 2365 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2366 mode);
56ade8fe 2367 }
56ade8fe
JP		 2368}
2369
2370static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 2371 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2372{
2373 u32 speed = SPEED_UNKNOWN;
2374 u8 duplex = DUPLEX_UNKNOWN;
2375 int i;
2376
2377 if (!carrier_ok)
2378 goto out;
2379
2380 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2381 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2382 speed = mlxsw_sp_port_link_mode[i].speed;
2383 duplex = DUPLEX_FULL;
2384 break;
2385 }
2386 }
2387out:
b9d66a36
IS		 2388 cmd->base.speed = speed;
2389 cmd->base.duplex = duplex;
56ade8fe
JP		 2390}
2391
2392static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2393{
2394 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2395 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2396 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2397 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2398 return PORT_FIBRE;
2399
2400 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2401 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2402 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2403 return PORT_DA;
2404
2405 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2406 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2407 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2408 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2409 return PORT_NONE;
2410
2411 return PORT_OTHER;
2412}
2413
b9d66a36
IS		 2414static u32
2415mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2416{
2417 u32 ptys_proto = 0;
2418 int i;
2419
2420 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 2421 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2422 cmd->link_modes.advertising))
56ade8fe
JP		 2423 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2424 }
2425 return ptys_proto;
2426}
2427
2428static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2429{
2430 u32 ptys_proto = 0;
2431 int i;
2432
2433 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2434 if (speed == mlxsw_sp_port_link_mode[i].speed)
2435 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2436 }
2437 return ptys_proto;
2438}
2439
18f1e70c
IS		 2440static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2441{
2442 u32 ptys_proto = 0;
2443 int i;
2444
2445 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2446 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2447 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2448 }
2449 return ptys_proto;
2450}
2451
b9d66a36
IS		 2452static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2453 struct ethtool_link_ksettings *cmd)
2454{
2455 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2456 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2457 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2458
2459 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2460 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2461}
2462
2463static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2464 struct ethtool_link_ksettings *cmd)
56ade8fe 2465{
b9d66a36
IS		 2466 if (!autoneg)
2467 return;
2468
2469 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2470 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2471}
2472
2473static void
2474mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2475 struct ethtool_link_ksettings *cmd)
2476{
2477 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2478 return;
2479
2480 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2481 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2482}
2483
2484static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2485 struct ethtool_link_ksettings *cmd)
2486{
2487 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 2488 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2489 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2490 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2491 u8 autoneg_status;
0c83f88c 2492 bool autoneg;
56ade8fe
JP		 2493 int err;
2494
b9d66a36 2495 autoneg = mlxsw_sp_port->link.autoneg;
401c8b4e 2496 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
b9d66a36
IS		 2497 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2498 if (err)
2499 return err;
401c8b4e
ER		 2500 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2501 &eth_proto_oper);
b9d66a36
IS		 2502
2503 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2504
b9d66a36
IS		 2505 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2506
2507 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2508 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2509 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2510
2511 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2512 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2513 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2514 cmd);
2515
2516 return 0;
2517}
2518
2519static int
2520mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2521 const struct ethtool_link_ksettings *cmd)
2522{
2523 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2524 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2525 char ptys_pl[MLXSW_REG_PTYS_LEN];
2526 u32 eth_proto_cap, eth_proto_new;
2527 bool autoneg;
2528 int err;
56ade8fe 2529
401c8b4e 2530 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
56ade8fe 2531 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2532 if (err)
56ade8fe 2533 return err;
401c8b4e 2534 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
b9d66a36
IS		 2535
2536 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2537 eth_proto_new = autoneg ?
2538 mlxsw_sp_to_ptys_advert_link(cmd) :
2539 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2540
2541 eth_proto_new = eth_proto_new & eth_proto_cap;
2542 if (!eth_proto_new) {
b9d66a36 2543 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2544 return -EINVAL;
2545 }
56ade8fe 2546
401c8b4e
ER		 2547 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2548 eth_proto_new);
56ade8fe 2549 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2550 if (err)
56ade8fe 2551 return err;
56ade8fe 2552
6277d46b 2553 if (!netif_running(dev))
56ade8fe
JP		 2554 return 0;
2555
0c83f88c
IS		 2556 mlxsw_sp_port->link.autoneg = autoneg;
2557
b9d66a36
IS		 2558 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2559 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2560
2561 return 0;
2562}
2563
ce6ef68f
YG		 2564static int mlxsw_sp_flash_device(struct net_device *dev,
2565 struct ethtool_flash *flash)
2566{
2567 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2568 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2569 const struct firmware *firmware;
2570 int err;
2571
2572 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2573 return -EOPNOTSUPP;
2574
2575 dev_hold(dev);
2576 rtnl_unlock();
2577
2578 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2579 if (err)
2580 goto out;
2581 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2582 release_firmware(firmware);
2583out:
2584 rtnl_lock();
2585 dev_put(dev);
2586 return err;
2587}
2588
4400081b
AS		 2589#define MLXSW_SP_I2C_ADDR_LOW 0x50
2590#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2591#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2ea10903
AS		 2592
2593static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2594 u16 offset, u16 size, void *data,
2595 unsigned int *p_read_size)
2596{
2597 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2598 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2599 char mcia_pl[MLXSW_REG_MCIA_LEN];
4400081b 2600 u16 i2c_addr;
2ea10903
AS		 2601 int status;
2602 int err;
2603
2604 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
4400081b
AS		 2605
2606 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2607 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2608 /* Cross pages read, read until offset 256 in low page */
2609 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2610
2611 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2612 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2613 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2614 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2615 }
2616
2ea10903 2617 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
4400081b 2618 0, 0, offset, size, i2c_addr);
2ea10903
AS		 2619
2620 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2621 if (err)
2622 return err;
2623
2624 status = mlxsw_reg_mcia_status_get(mcia_pl);
2625 if (status)
2626 return -EIO;
2627
2628 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2629 memcpy(data, eeprom_tmp, size);
2630 *p_read_size = size;
2631
2632 return 0;
2633}
2634
2635enum mlxsw_sp_eeprom_module_info_rev_id {
2636 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2637 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2638 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2639};
2640
2641enum mlxsw_sp_eeprom_module_info_id {
2642 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2643 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2644 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2645 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2646};
2647
2648enum mlxsw_sp_eeprom_module_info {
2649 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2650 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2651 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2652};
2653
2654static int mlxsw_sp_get_module_info(struct net_device *netdev,
2655 struct ethtool_modinfo *modinfo)
2656{
2657 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2658 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2659 u8 module_rev_id, module_id;
2660 unsigned int read_size;
2661 int err;
2662
2663 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2664 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2665 module_info, &read_size);
2666 if (err)
2667 return err;
2668
2669 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2670 return -EIO;
2671
2672 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2673 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2674
2675 switch (module_id) {
2676 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2677 modinfo->type = ETH_MODULE_SFF_8436;
2678 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2679 break;
2680 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2681 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2682 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2683 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2684 modinfo->type = ETH_MODULE_SFF_8636;
2685 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2686 } else {
2687 modinfo->type = ETH_MODULE_SFF_8436;
2688 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2689 }
2690 break;
2691 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2692 modinfo->type = ETH_MODULE_SFF_8472;
2693 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2694 break;
2695 default:
2696 return -EINVAL;
2697 }
2698
2699 return 0;
2700}
2701
2702static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2703 struct ethtool_eeprom *ee,
2704 u8 *data)
2705{
2706 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2707 int offset = ee->offset;
2708 unsigned int read_size;
2709 int i = 0;
2710 int err;
2711
2712 if (!ee->len)
2713 return -EINVAL;
2714
2715 memset(data, 0, ee->len);
2716
2717 while (i < ee->len) {
2718 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2719 ee->len - i, data + i,
2720 &read_size);
2721 if (err) {
2722 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2723 return err;
2724 }
2725
2726 i += read_size;
2727 offset += read_size;
2728 }
2729
2730 return 0;
2731}
2732
56ade8fe
JP		 2733static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2734 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2735 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2736 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2737 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2738 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2739 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2740 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2741 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2742 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2743 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
ce6ef68f 2744 .flash_device = mlxsw_sp_flash_device,
2ea10903
AS		 2745 .get_module_info = mlxsw_sp_get_module_info,
2746 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
56ade8fe
JP		 2747};
2748
18f1e70c
IS		 2749static int
2750mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2751{
2752 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2753 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2754 char ptys_pl[MLXSW_REG_PTYS_LEN];
2755 u32 eth_proto_admin;
2756
2757 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
401c8b4e
ER		 2758 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2759 eth_proto_admin);
18f1e70c
IS		 2760 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2761}
2762
8e8dfe9f
IS		 2763int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2764 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2765 bool dwrr, u8 dwrr_weight)
90183b98
IS		 2766{
2767 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2768 char qeec_pl[MLXSW_REG_QEEC_LEN];
2769
2770 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2771 next_index);
2772 mlxsw_reg_qeec_de_set(qeec_pl, true);
2773 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2774 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2775 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2776}
2777
cc7cf517
IS		 2778int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2779 enum mlxsw_reg_qeec_hr hr, u8 index,
2780 u8 next_index, u32 maxrate)
90183b98
IS		 2781{
2782 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2783 char qeec_pl[MLXSW_REG_QEEC_LEN];
2784
2785 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2786 next_index);
2787 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2788 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2789 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2790}
2791
8e8dfe9f
IS		 2792int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2793 u8 switch_prio, u8 tclass)
90183b98
IS		 2794{
2795 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2796 char qtct_pl[MLXSW_REG_QTCT_LEN];
2797
2798 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2799 tclass);
2800 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2801}
2802
2803static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2804{
2805 int err, i;
2806
2807 /* Setup the elements hierarcy, so that each TC is linked to
2808 * one subgroup, which are all member in the same group.
2809 */
2810 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2811 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2812 0);
2813 if (err)
2814 return err;
2815 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2816 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2817 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2818 0, false, 0);
2819 if (err)
2820 return err;
2821 }
2822 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2823 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2824 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2825 false, 0);
2826 if (err)
2827 return err;
2828 }
2829
2830 /* Make sure the max shaper is disabled in all hierarcies that
2831 * support it.
2832 */
2833 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2834 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2835 MLXSW_REG_QEEC_MAS_DIS);
2836 if (err)
2837 return err;
2838 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2839 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2840 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2841 i, 0,
2842 MLXSW_REG_QEEC_MAS_DIS);
2843 if (err)
2844 return err;
2845 }
2846 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2847 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2848 MLXSW_REG_QEEC_HIERARCY_TC,
2849 i, i,
2850 MLXSW_REG_QEEC_MAS_DIS);
2851 if (err)
2852 return err;
2853 }
2854
2855 /* Map all priorities to traffic class 0. */
2856 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2857 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2858 if (err)
2859 return err;
2860 }
2861
2862 return 0;
2863}
2864
5b153859
IS		 2865static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2866 bool split, u8 module, u8 width, u8 lane)
56ade8fe 2867{
c57529e1 2868 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 2869 struct mlxsw_sp_port *mlxsw_sp_port;
2870 struct net_device *dev;
56ade8fe
JP		 2871 int err;
2872
5b153859
IS		 2873 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2874 if (err) {
2875 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2876 local_port);
2877 return err;
2878 }
2879
56ade8fe 2880 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
5b153859
IS		 2881 if (!dev) {
2882 err = -ENOMEM;
2883 goto err_alloc_etherdev;
2884 }
f20a91f1 2885 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 2886 mlxsw_sp_port = netdev_priv(dev);
2887 mlxsw_sp_port->dev = dev;
2888 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2889 mlxsw_sp_port->local_port = local_port;
c57529e1 2890 mlxsw_sp_port->pvid = 1;
18f1e70c 2891 mlxsw_sp_port->split = split;
d664b41e
IS		 2892 mlxsw_sp_port->mapping.module = module;
2893 mlxsw_sp_port->mapping.width = width;
2894 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 2895 mlxsw_sp_port->link.autoneg = 1;
31a08a52 2896 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
763b4b70 2897 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 2898
2899 mlxsw_sp_port->pcpu_stats =
2900 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2901 if (!mlxsw_sp_port->pcpu_stats) {
2902 err = -ENOMEM;
2903 goto err_alloc_stats;
2904 }
2905
98d0f7b9
YG		 2906 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2907 GFP_KERNEL);
2908 if (!mlxsw_sp_port->sample) {
2909 err = -ENOMEM;
2910 goto err_alloc_sample;
2911 }
2912
9deef43d 2913 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 2914 &update_stats_cache);
2915
56ade8fe
JP		 2916 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2917 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2918
2e915e0b 2919 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
5b153859
IS		 2920 if (err) {
2921 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2922 mlxsw_sp_port->local_port);
2923 goto err_port_module_map;
2924 }
2925
3247ff2b
IS		 2926 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2927 if (err) {
2928 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2929 mlxsw_sp_port->local_port);
2930 goto err_port_swid_set;
2931 }
2932
56ade8fe
JP		 2933 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2934 if (err) {
2935 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2936 mlxsw_sp_port->local_port);
2937 goto err_dev_addr_init;
2938 }
2939
2940 netif_carrier_off(dev);
2941
2942 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 2943 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2944 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 2945
d894be57
JW		 2946 dev->min_mtu = 0;
2947 dev->max_mtu = ETH_MAX_MTU;
2948
56ade8fe
JP		 2949 /* Each packet needs to have a Tx header (metadata) on top all other
2950 * headers.
2951 */
feb7d387 2952 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 2953
56ade8fe
JP		 2954 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2955 if (err) {
2956 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2957 mlxsw_sp_port->local_port);
2958 goto err_port_system_port_mapping_set;
2959 }
2960
18f1e70c
IS		 2961 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2962 if (err) {
2963 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2964 mlxsw_sp_port->local_port);
2965 goto err_port_speed_by_width_set;
2966 }
2967
56ade8fe
JP		 2968 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2969 if (err) {
2970 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2971 mlxsw_sp_port->local_port);
2972 goto err_port_mtu_set;
2973 }
2974
2975 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2976 if (err)
2977 goto err_port_admin_status_set;
2978
2979 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2980 if (err) {
2981 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2982 mlxsw_sp_port->local_port);
2983 goto err_port_buffers_init;
2984 }
2985
90183b98
IS		 2986 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2987 if (err) {
2988 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2989 mlxsw_sp_port->local_port);
2990 goto err_port_ets_init;
2991 }
2992
f00817df
IS		 2993 /* ETS and buffers must be initialized before DCB. */
2994 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2995 if (err) {
2996 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2997 mlxsw_sp_port->local_port);
2998 goto err_port_dcb_init;
2999 }
3000
a1107487 3001 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
45a4a16c 3002 if (err) {
a1107487 3003 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
45a4a16c 3004 mlxsw_sp_port->local_port);
a1107487 3005 goto err_port_fids_init;
45a4a16c
IS		 3006 }
3007
c57529e1
IS		 3008 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3009 if (IS_ERR(mlxsw_sp_port_vlan)) {
3010 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
05978481 3011 mlxsw_sp_port->local_port);
c57529e1 3012 goto err_port_vlan_get;
05978481
IS		 3013 }
3014
56ade8fe 3015 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 3016 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 3017 err = register_netdev(dev);
3018 if (err) {
3019 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3020 mlxsw_sp_port->local_port);
3021 goto err_register_netdev;
3022 }
3023
d808c7e4
ER		 3024 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3025 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3026 module);
9deef43d 3027 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
56ade8fe
JP		 3028 return 0;
3029
56ade8fe 3030err_register_netdev:
2f25844c 3031 mlxsw_sp->ports[local_port] = NULL;
0583272d 3032 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1
IS		 3033 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3034err_port_vlan_get:
a1107487
IS		 3035 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3036err_port_fids_init:
4de34eb5 3037 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 3038err_port_dcb_init:
90183b98 3039err_port_ets_init:
56ade8fe
JP		 3040err_port_buffers_init:
3041err_port_admin_status_set:
3042err_port_mtu_set:
18f1e70c 3043err_port_speed_by_width_set:
56ade8fe 3044err_port_system_port_mapping_set:
56ade8fe 3045err_dev_addr_init:
3247ff2b
IS		 3046 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3047err_port_swid_set:
2e915e0b 3048 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
5b153859 3049err_port_module_map:
98d0f7b9
YG		 3050 kfree(mlxsw_sp_port->sample);
3051err_alloc_sample:
56ade8fe
JP		 3052 free_percpu(mlxsw_sp_port->pcpu_stats);
3053err_alloc_stats:
3054 free_netdev(dev);
5b153859 3055err_alloc_etherdev:
67963a33
JP		 3056 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3057 return err;
3058}
3059
5b153859 3060static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
56ade8fe
JP		 3061{
3062 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3063
9deef43d 3064 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
67963a33 3065 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
56ade8fe 3066 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 3067 mlxsw_sp->ports[local_port] = NULL;
0583272d 3068 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1 3069 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
a1107487 3070 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
f00817df 3071 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8 3072 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2e915e0b 3073 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
98d0f7b9 3074 kfree(mlxsw_sp_port->sample);
136f1445 3075 free_percpu(mlxsw_sp_port->pcpu_stats);
31a08a52 3076 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
56ade8fe 3077 free_netdev(mlxsw_sp_port->dev);
67963a33
JP		 3078 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3079}
3080
f83e2102
JP		 3081static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3082{
3083 return mlxsw_sp->ports[local_port] != NULL;
3084}
3085
56ade8fe
JP		 3086static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3087{
3088 int i;
3089
5ec2ee7d 3090 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
f83e2102
JP		 3091 if (mlxsw_sp_port_created(mlxsw_sp, i))
3092 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d 3093 kfree(mlxsw_sp->port_to_module);
56ade8fe
JP		 3094 kfree(mlxsw_sp->ports);
3095}
3096
3097static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3098{
5ec2ee7d 3099 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
d664b41e 3100 u8 module, width, lane;
56ade8fe
JP		 3101 size_t alloc_size;
3102 int i;
3103 int err;
3104
5ec2ee7d 3105 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
56ade8fe
JP		 3106 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3107 if (!mlxsw_sp->ports)
3108 return -ENOMEM;
3109
5ec2ee7d
IS		 3110 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
3111 if (!mlxsw_sp->port_to_module) {
3112 err = -ENOMEM;
3113 goto err_port_to_module_alloc;
3114 }
3115
3116 for (i = 1; i < max_ports; i++) {
558c2d5e 3117 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 3118 &width, &lane);
558c2d5e
IS		 3119 if (err)
3120 goto err_port_module_info_get;
3121 if (!width)
3122 continue;
3123 mlxsw_sp->port_to_module[i] = module;
67963a33
JP		 3124 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3125 module, width, lane);
56ade8fe
JP		 3126 if (err)
3127 goto err_port_create;
3128 }
3129 return 0;
3130
3131err_port_create:
558c2d5e 3132err_port_module_info_get:
56ade8fe 3133 for (i--; i >= 1; i--)
f83e2102
JP		 3134 if (mlxsw_sp_port_created(mlxsw_sp, i))
3135 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d
IS		 3136 kfree(mlxsw_sp->port_to_module);
3137err_port_to_module_alloc:
56ade8fe
JP		 3138 kfree(mlxsw_sp->ports);
3139 return err;
3140}
3141
18f1e70c
IS		 3142static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3143{
3144 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3145
3146 return local_port - offset;
3147}
3148
be94535f
IS		 3149static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3150 u8 module, unsigned int count)
3151{
3152 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3153 int err, i;
3154
be94535f
IS		 3155 for (i = 0; i < count; i++) {
3156 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 3157 module, width, i * width);
be94535f
IS		 3158 if (err)
3159 goto err_port_create;
3160 }
3161
3162 return 0;
3163
3164err_port_create:
3165 for (i--; i >= 0; i--)
f83e2102
JP		 3166 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3167 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
be94535f
IS		 3168 return err;
3169}
3170
3171static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3172 u8 base_port, unsigned int count)
3173{
3174 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3175 int i;
3176
3177 /* Split by four means we need to re-create two ports, otherwise
3178 * only one.
3179 */
3180 count = count / 2;
3181
be94535f
IS		 3182 for (i = 0; i < count; i++) {
3183 local_port = base_port + i * 2;
3184 module = mlxsw_sp->port_to_module[local_port];
3185
3186 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 3187 width, 0);
be94535f
IS		 3188 }
3189}
3190
b2f10571
JP		 3191static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3192 unsigned int count)
18f1e70c 3193{
b2f10571 3194 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3195 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 3196 u8 module, cur_width, base_port;
3197 int i;
3198 int err;
3199
3200 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3201 if (!mlxsw_sp_port) {
3202 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3203 local_port);
3204 return -EINVAL;
3205 }
3206
d664b41e
IS		 3207 module = mlxsw_sp_port->mapping.module;
3208 cur_width = mlxsw_sp_port->mapping.width;
3209
18f1e70c
IS		 3210 if (count != 2 && count != 4) {
3211 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3212 return -EINVAL;
3213 }
3214
18f1e70c
IS		 3215 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3216 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3217 return -EINVAL;
3218 }
3219
3220 /* Make sure we have enough slave (even) ports for the split. */
3221 if (count == 2) {
3222 base_port = local_port;
3223 if (mlxsw_sp->ports[base_port + 1]) {
3224 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3225 return -EINVAL;
3226 }
3227 } else {
3228 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3229 if (mlxsw_sp->ports[base_port + 1] ||
3230 mlxsw_sp->ports[base_port + 3]) {
3231 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3232 return -EINVAL;
3233 }
3234 }
3235
3236 for (i = 0; i < count; i++)
f83e2102
JP		 3237 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3238 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3239
be94535f
IS		 3240 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3241 if (err) {
3242 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3243 goto err_port_split_create;
18f1e70c
IS		 3244 }
3245
3246 return 0;
3247
be94535f
IS		 3248err_port_split_create:
3249 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3250 return err;
3251}
3252
b2f10571 3253static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 3254{
b2f10571 3255 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3256 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 3257 u8 cur_width, base_port;
18f1e70c
IS		 3258 unsigned int count;
3259 int i;
18f1e70c
IS		 3260
3261 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3262 if (!mlxsw_sp_port) {
3263 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3264 local_port);
3265 return -EINVAL;
3266 }
3267
3268 if (!mlxsw_sp_port->split) {
3269 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3270 return -EINVAL;
3271 }
3272
d664b41e 3273 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 3274 count = cur_width == 1 ? 4 : 2;
3275
3276 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3277
3278 /* Determine which ports to remove. */
3279 if (count == 2 && local_port >= base_port + 2)
3280 base_port = base_port + 2;
3281
3282 for (i = 0; i < count; i++)
f83e2102
JP		 3283 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3284 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3285
be94535f 3286 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3287
3288 return 0;
3289}
3290
56ade8fe
JP		 3291static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3292 char *pude_pl, void *priv)
3293{
3294 struct mlxsw_sp *mlxsw_sp = priv;
3295 struct mlxsw_sp_port *mlxsw_sp_port;
3296 enum mlxsw_reg_pude_oper_status status;
3297 u8 local_port;
3298
3299 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3300 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 3301 if (!mlxsw_sp_port)
56ade8fe 3302 return;
56ade8fe
JP		 3303
3304 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3305 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3306 netdev_info(mlxsw_sp_port->dev, "link up\n");
3307 netif_carrier_on(mlxsw_sp_port->dev);
3308 } else {
3309 netdev_info(mlxsw_sp_port->dev, "link down\n");
3310 netif_carrier_off(mlxsw_sp_port->dev);
3311 }
3312}
3313
14eeda99
NF		 3314static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3315 u8 local_port, void *priv)
56ade8fe
JP		 3316{
3317 struct mlxsw_sp *mlxsw_sp = priv;
3318 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3319 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3320
3321 if (unlikely(!mlxsw_sp_port)) {
3322 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3323 local_port);
3324 return;
3325 }
3326
3327 skb->dev = mlxsw_sp_port->dev;
3328
3329 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3330 u64_stats_update_begin(&pcpu_stats->syncp);
3331 pcpu_stats->rx_packets++;
3332 pcpu_stats->rx_bytes += skb->len;
3333 u64_stats_update_end(&pcpu_stats->syncp);
3334
3335 skb->protocol = eth_type_trans(skb, skb->dev);
3336 netif_receive_skb(skb);
3337}
3338
1c6c6d22
IS		 3339static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3340 void *priv)
3341{
3342 skb->offload_fwd_mark = 1;
14eeda99 3343 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
1c6c6d22
IS		 3344}
3345
a0040c8c
YG		 3346static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3347 u8 local_port, void *priv)
3348{
3349 skb->offload_mr_fwd_mark = 1;
3350 skb->offload_fwd_mark = 1;
3351 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3352}
3353
98d0f7b9
YG		 3354static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3355 void *priv)
3356{
3357 struct mlxsw_sp *mlxsw_sp = priv;
3358 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3359 struct psample_group *psample_group;
3360 u32 size;
3361
3362 if (unlikely(!mlxsw_sp_port)) {
3363 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3364 local_port);
3365 goto out;
3366 }
3367 if (unlikely(!mlxsw_sp_port->sample)) {
3368 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3369 local_port);
3370 goto out;
3371 }
3372
3373 size = mlxsw_sp_port->sample->truncate ?
3374 mlxsw_sp_port->sample->trunc_size : skb->len;
3375
3376 rcu_read_lock();
3377 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3378 if (!psample_group)
3379 goto out_unlock;
3380 psample_sample_packet(psample_group, skb, size,
3381 mlxsw_sp_port->dev->ifindex, 0,
3382 mlxsw_sp_port->sample->rate);
3383out_unlock:
3384 rcu_read_unlock();
3385out:
3386 consume_skb(skb);
3387}
3388
117b0dad 3389#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
0fb78a4e 3390 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
117b0dad 3391 _is_ctrl, SP_##_trap_group, DISCARD)
14eeda99 3392
117b0dad 3393#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
14eeda99 3394 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
117b0dad
NF		 3395 _is_ctrl, SP_##_trap_group, DISCARD)
3396
a0040c8c
YG		 3397#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3398 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3399 _is_ctrl, SP_##_trap_group, DISCARD)
3400
117b0dad
NF		 3401#define MLXSW_SP_EVENTL(_func, _trap_id) \
3402 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
93393b33 3403
4544913e
NF		 3404static const struct mlxsw_listener mlxsw_sp_listener[] = {
3405 /* Events */
117b0dad 3406 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
ee4a60d8 3407 /* L2 traps */
117b0dad
NF		 3408 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3409 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3410 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3411 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3412 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3413 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3414 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3415 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3416 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3417 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3418 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
9d41accc 3419 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
588823f9
AS		 3420 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3421 false),
3422 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3423 false),
3424 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3425 false),
3426 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3427 false),
93393b33 3428 /* L3 traps */
0fcc4847
IS		 3429 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3430 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3431 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
0fcc4847 3432 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
8d54814e
AS		 3433 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3434 false),
3435 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3436 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3437 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3438 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3439 false),
3440 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3441 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3442 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
0fcc4847 3443 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
8d54814e
AS		 3444 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3445 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3446 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3447 false),
3448 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3449 false),
3450 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3451 false),
3452 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3453 false),
3454 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3455 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3456 false),
3457 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3458 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
7607dd35 3459 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
8d54814e 3460 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
86484de2 3461 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
98d0f7b9
YG		 3462 /* PKT Sample trap */
3463 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
0db7b386
JP		 3464 false, SP_IP2ME, DISCARD),
3465 /* ACL trap */
3466 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
b48cfc80
YG		 3467 /* Multicast Router Traps */
3468 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3469 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3470 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
a0040c8c 3471 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
56ade8fe
JP		 3472};
3473
9148e7cf
NF		 3474static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3475{
3476 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3477 enum mlxsw_reg_qpcr_ir_units ir_units;
3478 int max_cpu_policers;
3479 bool is_bytes;
3480 u8 burst_size;
3481 u32 rate;
3482 int i, err;
3483
3484 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3485 return -EIO;
3486
3487 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3488
3489 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3490 for (i = 0; i < max_cpu_policers; i++) {
3491 is_bytes = false;
3492 switch (i) {
3493 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3494 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3495 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80
YG		 3497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3498 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
9148e7cf
NF		 3499 rate = 128;
3500 burst_size = 7;
3501 break;
3502 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
588823f9 3503 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
9148e7cf
NF		 3504 rate = 16 * 1024;
3505 burst_size = 10;
3506 break;
8d54814e 3507 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
9148e7cf
NF		 3508 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3509 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
8d54814e 3510 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
9148e7cf
NF		 3511 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3512 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
8d54814e 3513 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3514 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
9148e7cf
NF		 3515 rate = 1024;
3516 burst_size = 7;
3517 break;
3518 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3519 is_bytes = true;
3520 rate = 4 * 1024;
3521 burst_size = 4;
3522 break;
3523 default:
3524 continue;
3525 }
3526
3527 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3528 burst_size);
3529 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3530 if (err)
3531 return err;
3532 }
3533
3534 return 0;
3535}
3536
579c82e4 3537static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
56ade8fe
JP		 3538{
3539 char htgt_pl[MLXSW_REG_HTGT_LEN];
117b0dad 3540 enum mlxsw_reg_htgt_trap_group i;
9148e7cf 3541 int max_cpu_policers;
579c82e4
NF		 3542 int max_trap_groups;
3543 u8 priority, tc;
9148e7cf 3544 u16 policer_id;
117b0dad 3545 int err;
579c82e4
NF		 3546
3547 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3548 return -EIO;
3549
3550 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
9148e7cf 3551 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
579c82e4
NF		 3552
3553 for (i = 0; i < max_trap_groups; i++) {
9148e7cf 3554 policer_id = i;
579c82e4 3555 switch (i) {
117b0dad
NF		 3556 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3557 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3558 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3559 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80 3560 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
117b0dad
NF		 3561 priority = 5;
3562 tc = 5;
3563 break;
8d54814e 3564 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
117b0dad
NF		 3565 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3566 priority = 4;
3567 tc = 4;
3568 break;
3569 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3570 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
588823f9 3571 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
117b0dad
NF		 3572 priority = 3;
3573 tc = 3;
3574 break;
3575 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
8d54814e 3576 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3577 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
117b0dad
NF		 3578 priority = 2;
3579 tc = 2;
3580 break;
8d54814e 3581 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
117b0dad
NF		 3582 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3583 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
b48cfc80 3584 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
117b0dad
NF		 3585 priority = 1;
3586 tc = 1;
3587 break;
3588 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
579c82e4
NF		 3589 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3590 tc = MLXSW_REG_HTGT_DEFAULT_TC;
9148e7cf 3591 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
579c82e4
NF		 3592 break;
3593 default:
3594 continue;
3595 }
117b0dad 3596
9148e7cf
NF		 3597 if (max_cpu_policers <= policer_id &&
3598 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3599 return -EIO;
3600
3601 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
579c82e4
NF		 3602 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3603 if (err)
3604 return err;
3605 }
3606
3607 return 0;
3608}
3609
3610static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3611{
56ade8fe
JP		 3612 int i;
3613 int err;
3614
9148e7cf
NF		 3615 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3616 if (err)
3617 return err;
3618
579c82e4 3619 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
56ade8fe
JP		 3620 if (err)
3621 return err;
3622
4544913e 3623 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3624 err = mlxsw_core_trap_register(mlxsw_sp->core,
4544913e 3625 &mlxsw_sp_listener[i],
14eeda99 3626 mlxsw_sp);
56ade8fe 3627 if (err)
4544913e 3628 goto err_listener_register;
56ade8fe 3629
56ade8fe
JP		 3630 }
3631 return 0;
3632
4544913e 3633err_listener_register:
56ade8fe 3634 for (i--; i >= 0; i--) {
14eeda99 3635 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3636 &mlxsw_sp_listener[i],
14eeda99 3637 mlxsw_sp);
56ade8fe
JP		 3638 }
3639 return err;
3640}
3641
3642static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3643{
56ade8fe
JP		 3644 int i;
3645
4544913e 3646 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3647 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3648 &mlxsw_sp_listener[i],
14eeda99 3649 mlxsw_sp);
56ade8fe
JP		 3650 }
3651}
3652
0d65fc13
JP		 3653static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3654{
3655 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 3656 int err;
0d65fc13
JP		 3657
3658 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3659 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3660 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3661 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3662 MLXSW_REG_SLCR_LAG_HASH_SIP |
3663 MLXSW_REG_SLCR_LAG_HASH_DIP |
3664 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3665 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3666 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 3667 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3668 if (err)
3669 return err;
3670
c1a38311
JP		 3671 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3672 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 3673 return -EIO;
3674
c1a38311 3675 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 3676 sizeof(struct mlxsw_sp_upper),
3677 GFP_KERNEL);
3678 if (!mlxsw_sp->lags)
3679 return -ENOMEM;
3680
3681 return 0;
3682}
3683
3684static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3685{
3686 kfree(mlxsw_sp->lags);
0d65fc13
JP		 3687}
3688
9d87fcea
NF		 3689static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3690{
3691 char htgt_pl[MLXSW_REG_HTGT_LEN];
3692
579c82e4
NF		 3693 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3694 MLXSW_REG_HTGT_INVALID_POLICER,
3695 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3696 MLXSW_REG_HTGT_DEFAULT_TC);
9d87fcea
NF		 3697 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3698}
3699
c30f5d01
PM		 3700static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3701 unsigned long event, void *ptr);
3702
b2f10571 3703static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 3704 const struct mlxsw_bus_info *mlxsw_bus_info)
3705{
b2f10571 3706 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 3707 int err;
3708
3709 mlxsw_sp->core = mlxsw_core;
3710 mlxsw_sp->bus_info = mlxsw_bus_info;
3711
6b742199
YG		 3712 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3713 if (err) {
3714 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3715 return err;
3716 }
3717
56ade8fe
JP		 3718 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3719 if (err) {
3720 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3721 return err;
3722 }
3723
a875a2ee
IS		 3724 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3725 if (err) {
3726 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3727 return err;
3728 }
3729
a1107487 3730 err = mlxsw_sp_fids_init(mlxsw_sp);
56ade8fe 3731 if (err) {
a1107487 3732 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
a875a2ee 3733 goto err_fids_init;
56ade8fe
JP		 3734 }
3735
a1107487 3736 err = mlxsw_sp_traps_init(mlxsw_sp);
56ade8fe 3737 if (err) {
a1107487
IS		 3738 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3739 goto err_traps_init;
56ade8fe
JP		 3740 }
3741
3742 err = mlxsw_sp_buffers_init(mlxsw_sp);
3743 if (err) {
3744 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3745 goto err_buffers_init;
3746 }
3747
0d65fc13
JP		 3748 err = mlxsw_sp_lag_init(mlxsw_sp);
3749 if (err) {
3750 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3751 goto err_lag_init;
3752 }
3753
56ade8fe
JP		 3754 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3755 if (err) {
3756 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3757 goto err_switchdev_init;
3758 }
3759
e2b2d35a
YG		 3760 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3761 if (err) {
3762 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3763 goto err_counter_pool_init;
3764 }
3765
d3b939b8
YG		 3766 err = mlxsw_sp_afa_init(mlxsw_sp);
3767 if (err) {
3768 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3769 goto err_afa_init;
3770 }
3771
464dce18
IS		 3772 err = mlxsw_sp_router_init(mlxsw_sp);
3773 if (err) {
3774 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3775 goto err_router_init;
3776 }
3777
c30f5d01
PM		 3778 /* Initialize netdevice notifier after router is initialized, so that
3779 * the event handler can use router structures.
3780 */
3781 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3782 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3783 if (err) {
3784 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3785 goto err_netdev_notifier;
3786 }
3787
763b4b70
YG		 3788 err = mlxsw_sp_span_init(mlxsw_sp);
3789 if (err) {
3790 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3791 goto err_span_init;
3792 }
3793
22a67766
JP		 3794 err = mlxsw_sp_acl_init(mlxsw_sp);
3795 if (err) {
3796 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3797 goto err_acl_init;
3798 }
3799
230ead01
AS		 3800 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3801 if (err) {
3802 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3803 goto err_dpipe_init;
3804 }
3805
bbf2a475
IS		 3806 err = mlxsw_sp_ports_create(mlxsw_sp);
3807 if (err) {
3808 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3809 goto err_ports_create;
3810 }
3811
56ade8fe
JP		 3812 return 0;
3813
bbf2a475 3814err_ports_create:
230ead01
AS		 3815 mlxsw_sp_dpipe_fini(mlxsw_sp);
3816err_dpipe_init:
22a67766
JP		 3817 mlxsw_sp_acl_fini(mlxsw_sp);
3818err_acl_init:
763b4b70
YG		 3819 mlxsw_sp_span_fini(mlxsw_sp);
3820err_span_init:
c30f5d01
PM		 3821 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3822err_netdev_notifier:
464dce18
IS		 3823 mlxsw_sp_router_fini(mlxsw_sp);
3824err_router_init:
d3b939b8
YG		 3825 mlxsw_sp_afa_fini(mlxsw_sp);
3826err_afa_init:
e2b2d35a
YG		 3827 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3828err_counter_pool_init:
bbf2a475 3829 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 3830err_switchdev_init:
ce0bd2b0 3831 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 3832err_lag_init:
0f433fa0 3833 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3834err_buffers_init:
56ade8fe 3835 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487
IS		 3836err_traps_init:
3837 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee
IS		 3838err_fids_init:
3839 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 3840 return err;
3841}
3842
b2f10571 3843static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 3844{
b2f10571 3845 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 3846
bbf2a475 3847 mlxsw_sp_ports_remove(mlxsw_sp);
230ead01 3848 mlxsw_sp_dpipe_fini(mlxsw_sp);
22a67766 3849 mlxsw_sp_acl_fini(mlxsw_sp);
763b4b70 3850 mlxsw_sp_span_fini(mlxsw_sp);
c30f5d01 3851 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
464dce18 3852 mlxsw_sp_router_fini(mlxsw_sp);
d3b939b8 3853 mlxsw_sp_afa_fini(mlxsw_sp);
e2b2d35a 3854 mlxsw_sp_counter_pool_fini(mlxsw_sp);
56ade8fe 3855 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 3856 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 3857 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3858 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487 3859 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee 3860 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 3861}
3862
159fe88e 3863static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
56ade8fe
JP		 3864 .used_max_vepa_channels = 1,
3865 .max_vepa_channels = 0,
56ade8fe 3866 .used_max_mid = 1,
53ae6283 3867 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 3868 .used_max_pgt = 1,
3869 .max_pgt = 0,
56ade8fe
JP		 3870 .used_flood_tables = 1,
3871 .used_flood_mode = 1,
3872 .flood_mode = 3,
71c365bd 3873 .max_fid_offset_flood_tables = 3,
56ade8fe 3874 .fid_offset_flood_table_size = VLAN_N_VID - 1,
71c365bd 3875 .max_fid_flood_tables = 3,
a1107487 3876 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
56ade8fe
JP		 3877 .used_max_ib_mc = 1,
3878 .max_ib_mc = 0,
3879 .used_max_pkey = 1,
3880 .max_pkey = 0,
403547d3
NF		 3881 .used_kvd_split_data = 1,
3882 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
f11fbaf8
IS		 3883 .kvd_hash_single_parts = 59,
3884 .kvd_hash_double_parts = 41,
c6022427 3885 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 3886 .swid_config = {
3887 {
3888 .used_type = 1,
3889 .type = MLXSW_PORT_SWID_TYPE_ETH,
3890 }
3891 },
57d316ba 3892 .resource_query_enable = 1,
56ade8fe
JP		 3893};
3894
3895static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 3896 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 3897 .priv_size = sizeof(struct mlxsw_sp),
3898 .init = mlxsw_sp_init,
3899 .fini = mlxsw_sp_fini,
9d87fcea 3900 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
2d0ed39f
JP		 3901 .port_split = mlxsw_sp_port_split,
3902 .port_unsplit = mlxsw_sp_port_unsplit,
3903 .sb_pool_get = mlxsw_sp_sb_pool_get,
3904 .sb_pool_set = mlxsw_sp_sb_pool_set,
3905 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3906 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3907 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3908 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3909 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3910 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3911 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3912 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3913 .txhdr_construct = mlxsw_sp_txhdr_construct,
3914 .txhdr_len = MLXSW_TXHDR_LEN,
3915 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 3916};
3917
22a67766 3918bool mlxsw_sp_port_dev_check(const struct net_device *dev)
7ce856aa
JP		 3919{
3920 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3921}
3922
1182e536 3923static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
dd82364c 3924{
1182e536 3925 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
dd82364c
DA		 3926 int ret = 0;
3927
3928 if (mlxsw_sp_port_dev_check(lower_dev)) {
1182e536 3929 *p_mlxsw_sp_port = netdev_priv(lower_dev);
dd82364c
DA		 3930 ret = 1;
3931 }
3932
3933 return ret;
3934}
3935
c57529e1 3936struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
7ce856aa 3937{
1182e536 3938 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 3939
3940 if (mlxsw_sp_port_dev_check(dev))
3941 return netdev_priv(dev);
3942
1182e536
JP		 3943 mlxsw_sp_port = NULL;
3944 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
dd82364c 3945
1182e536 3946 return mlxsw_sp_port;
7ce856aa
JP		 3947}
3948
4724ba56 3949struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
7ce856aa
JP		 3950{
3951 struct mlxsw_sp_port *mlxsw_sp_port;
3952
3953 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3954 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3955}
3956
af061378 3957struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
7ce856aa 3958{
1182e536 3959 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 3960
3961 if (mlxsw_sp_port_dev_check(dev))
3962 return netdev_priv(dev);
3963
1182e536
JP		 3964 mlxsw_sp_port = NULL;
3965 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3966 &mlxsw_sp_port);
dd82364c 3967
1182e536 3968 return mlxsw_sp_port;
7ce856aa
JP		 3969}
3970
3971struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3972{
3973 struct mlxsw_sp_port *mlxsw_sp_port;
3974
3975 rcu_read_lock();
3976 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3977 if (mlxsw_sp_port)
3978 dev_hold(mlxsw_sp_port->dev);
3979 rcu_read_unlock();
3980 return mlxsw_sp_port;
3981}
3982
3983void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3984{
3985 dev_put(mlxsw_sp_port->dev);
3986}
3987
0d65fc13
JP		 3988static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3989{
3990 char sldr_pl[MLXSW_REG_SLDR_LEN];
3991
3992 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3993 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3994}
3995
3996static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3997{
3998 char sldr_pl[MLXSW_REG_SLDR_LEN];
3999
4000 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4001 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4002}
4003
4004static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4005 u16 lag_id, u8 port_index)
4006{
4007 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4008 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4009
4010 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4011 lag_id, port_index);
4012 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4013}
4014
4015static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4016 u16 lag_id)
4017{
4018 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4019 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4020
4021 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4022 lag_id);
4023 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4024}
4025
4026static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4027 u16 lag_id)
4028{
4029 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4030 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4031
4032 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4033 lag_id);
4034 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4035}
4036
4037static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4038 u16 lag_id)
4039{
4040 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4041 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4042
4043 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4044 lag_id);
4045 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4046}
4047
4048static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4049 struct net_device *lag_dev,
4050 u16 *p_lag_id)
4051{
4052 struct mlxsw_sp_upper *lag;
4053 int free_lag_id = -1;
c1a38311 4054 u64 max_lag;
0d65fc13
JP		 4055 int i;
4056
c1a38311
JP		 4057 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4058 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 4059 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4060 if (lag->ref_count) {
4061 if (lag->dev == lag_dev) {
4062 *p_lag_id = i;
4063 return 0;
4064 }
4065 } else if (free_lag_id < 0) {
4066 free_lag_id = i;
4067 }
4068 }
4069 if (free_lag_id < 0)
4070 return -EBUSY;
4071 *p_lag_id = free_lag_id;
4072 return 0;
4073}
4074
4075static bool
4076mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4077 struct net_device *lag_dev,
e58376e1
DA		 4078 struct netdev_lag_upper_info *lag_upper_info,
4079 struct netlink_ext_ack *extack)
0d65fc13
JP		 4080{
4081 u16 lag_id;
4082
e58376e1
DA		 4083 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4084 NL_SET_ERR_MSG(extack,
4085 "spectrum: Exceeded number of supported LAG devices");
0d65fc13 4086 return false;
e58376e1
DA		 4087 }
4088 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4089 NL_SET_ERR_MSG(extack,
4090 "spectrum: LAG device using unsupported Tx type");
0d65fc13 4091 return false;
e58376e1 4092 }
0d65fc13
JP		 4093 return true;
4094}
4095
4096static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4097 u16 lag_id, u8 *p_port_index)
4098{
c1a38311 4099 u64 max_lag_members;
0d65fc13
JP		 4100 int i;
4101
c1a38311
JP		 4102 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4103 MAX_LAG_MEMBERS);
4104 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 4105 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4106 *p_port_index = i;
4107 return 0;
4108 }
4109 }
4110 return -EBUSY;
4111}
4112
4113static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4114 struct net_device *lag_dev)
4115{
4116 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
c57529e1 4117 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
0d65fc13
JP		 4118 struct mlxsw_sp_upper *lag;
4119 u16 lag_id;
4120 u8 port_index;
4121 int err;
4122
4123 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4124 if (err)
4125 return err;
4126 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4127 if (!lag->ref_count) {
4128 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4129 if (err)
4130 return err;
4131 lag->dev = lag_dev;
4132 }
4133
4134 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4135 if (err)
4136 return err;
4137 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4138 if (err)
4139 goto err_col_port_add;
4140 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4141 if (err)
4142 goto err_col_port_enable;
4143
4144 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4145 mlxsw_sp_port->local_port);
4146 mlxsw_sp_port->lag_id = lag_id;
4147 mlxsw_sp_port->lagged = 1;
4148 lag->ref_count++;
86bf95b3 4149
c57529e1
IS		 4150 /* Port is no longer usable as a router interface */
4151 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4152 if (mlxsw_sp_port_vlan->fid)
a1107487 4153 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
86bf95b3 4154
0d65fc13
JP		 4155 return 0;
4156
51554db2
IS		 4157err_col_port_enable:
4158 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4159err_col_port_add:
4160 if (!lag->ref_count)
4161 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4162 return err;
4163}
4164
82e6db03
IS		 4165static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4166 struct net_device *lag_dev)
0d65fc13
JP		 4167{
4168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4169 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4170 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4171
4172 if (!mlxsw_sp_port->lagged)
82e6db03 4173 return;
0d65fc13
JP		 4174 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4175 WARN_ON(lag->ref_count == 0);
4176
82e6db03
IS		 4177 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4178 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4179
c57529e1
IS		 4180 /* Any VLANs configured on the port are no longer valid */
4181 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4dc236c3 4182
fe3f6d14 4183 if (lag->ref_count == 1)
82e6db03 4184 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4185
4186 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4187 mlxsw_sp_port->local_port);
4188 mlxsw_sp_port->lagged = 0;
4189 lag->ref_count--;
86bf95b3 4190
c57529e1
IS		 4191 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4192 /* Make sure untagged frames are allowed to ingress */
4193 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
0d65fc13
JP		 4194}
4195
74581206
JP		 4196static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4197 u16 lag_id)
4198{
4199 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4200 char sldr_pl[MLXSW_REG_SLDR_LEN];
4201
4202 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4203 mlxsw_sp_port->local_port);
4204 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4205}
4206
4207static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4208 u16 lag_id)
4209{
4210 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4211 char sldr_pl[MLXSW_REG_SLDR_LEN];
4212
4213 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4214 mlxsw_sp_port->local_port);
4215 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4216}
4217
4218static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4219 bool lag_tx_enabled)
4220{
4221 if (lag_tx_enabled)
4222 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4223 mlxsw_sp_port->lag_id);
4224 else
4225 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4226 mlxsw_sp_port->lag_id);
4227}
4228
4229static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4230 struct netdev_lag_lower_state_info *info)
4231{
4232 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4233}
4234
2b94e58d
JP		 4235static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4236 bool enable)
4237{
4238 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4239 enum mlxsw_reg_spms_state spms_state;
4240 char *spms_pl;
4241 u16 vid;
4242 int err;
4243
4244 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4245 MLXSW_REG_SPMS_STATE_DISCARDING;
4246
4247 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4248 if (!spms_pl)
4249 return -ENOMEM;
4250 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4251
4252 for (vid = 0; vid < VLAN_N_VID; vid++)
4253 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4254
4255 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4256 kfree(spms_pl);
4257 return err;
4258}
4259
4260static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4261{
4262 int err;
4263
4aafc368 4264 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
2b94e58d
JP		 4265 if (err)
4266 return err;
4aafc368
IS		 4267 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4268 if (err)
4269 goto err_port_stp_set;
2b94e58d
JP		 4270 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4271 true, false);
4272 if (err)
4273 goto err_port_vlan_set;
4274 return 0;
4275
4276err_port_vlan_set:
4277 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368
IS		 4278err_port_stp_set:
4279 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4280 return err;
4281}
4282
4283static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4284{
4285 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4286 false, false);
4287 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368 4288 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4289}
4290
f0cebd81
IS		 4291static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4292 struct net_device *dev,
74581206 4293 unsigned long event, void *ptr)
56ade8fe 4294{
56ade8fe
JP		 4295 struct netdev_notifier_changeupper_info *info;
4296 struct mlxsw_sp_port *mlxsw_sp_port;
e58376e1 4297 struct netlink_ext_ack *extack;
56ade8fe
JP		 4298 struct net_device *upper_dev;
4299 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4300 int err = 0;
56ade8fe 4301
56ade8fe
JP		 4302 mlxsw_sp_port = netdev_priv(dev);
4303 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4304 info = ptr;
e58376e1 4305 extack = netdev_notifier_info_to_extack(&info->info);
56ade8fe
JP		 4306
4307 switch (event) {
4308 case NETDEV_PRECHANGEUPPER:
4309 upper_dev = info->upper_dev;
59fe9b3f
IS		 4310 if (!is_vlan_dev(upper_dev) &&
4311 !netif_is_lag_master(upper_dev) &&
7179eb5a 4312 !netif_is_bridge_master(upper_dev) &&
e58376e1
DA		 4313 !netif_is_ovs_master(upper_dev)) {
4314 NL_SET_ERR_MSG(extack,
4315 "spectrum: Unknown upper device type");
59fe9b3f 4316 return -EINVAL;
e58376e1 4317 }
6ec43904 4318 if (!info->linking)
0d65fc13 4319 break;
e58376e1
DA		 4320 if (netdev_has_any_upper_dev(upper_dev)) {
4321 NL_SET_ERR_MSG(extack,
4322 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4323 return -EINVAL;
e58376e1 4324 }
0d65fc13
JP		 4325 if (netif_is_lag_master(upper_dev) &&
4326 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
e58376e1 4327 info->upper_info, extack))
80bedf1a 4328 return -EINVAL;
e58376e1
DA		 4329 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4330 NL_SET_ERR_MSG(extack,
4331 "spectrum: Master device is a LAG master and this device has a VLAN");
6ec43904 4332 return -EINVAL;
e58376e1 4333 }
6ec43904 4334 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
e58376e1
DA		 4335 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4336 NL_SET_ERR_MSG(extack,
4337 "spectrum: Can not put a VLAN on a LAG port");
6ec43904 4338 return -EINVAL;
e58376e1
DA		 4339 }
4340 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4341 NL_SET_ERR_MSG(extack,
4342 "spectrum: Master device is an OVS master and this device has a VLAN");
2b94e58d 4343 return -EINVAL;
e58376e1
DA		 4344 }
4345 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4346 NL_SET_ERR_MSG(extack,
4347 "spectrum: Can not put a VLAN on an OVS port");
2b94e58d 4348 return -EINVAL;
e58376e1 4349 }
56ade8fe
JP		 4350 break;
4351 case NETDEV_CHANGEUPPER:
4352 upper_dev = info->upper_dev;
c57529e1 4353 if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4354 if (info->linking)
4355 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
f0cebd81 4356 lower_dev,
9b63ef88
IS		 4357 upper_dev,
4358 extack);
7117a570 4359 else
f0cebd81
IS		 4360 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4361 lower_dev,
4362 upper_dev);
0d65fc13 4363 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4364 if (info->linking)
0d65fc13
JP		 4365 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4366 upper_dev);
80bedf1a 4367 else
82e6db03
IS		 4368 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4369 upper_dev);
2b94e58d
JP		 4370 } else if (netif_is_ovs_master(upper_dev)) {
4371 if (info->linking)
4372 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4373 else
4374 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
56ade8fe
JP		 4375 }
4376 break;
4377 }
4378
80bedf1a 4379 return err;
56ade8fe
JP		 4380}
4381
74581206
JP		 4382static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4383 unsigned long event, void *ptr)
4384{
4385 struct netdev_notifier_changelowerstate_info *info;
4386 struct mlxsw_sp_port *mlxsw_sp_port;
4387 int err;
4388
4389 mlxsw_sp_port = netdev_priv(dev);
4390 info = ptr;
4391
4392 switch (event) {
4393 case NETDEV_CHANGELOWERSTATE:
4394 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4395 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4396 info->lower_state_info);
4397 if (err)
4398 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4399 }
4400 break;
4401 }
4402
80bedf1a 4403 return 0;
74581206
JP		 4404}
4405
f0cebd81
IS		 4406static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4407 struct net_device *port_dev,
74581206
JP		 4408 unsigned long event, void *ptr)
4409{
4410 switch (event) {
4411 case NETDEV_PRECHANGEUPPER:
4412 case NETDEV_CHANGEUPPER:
f0cebd81
IS		 4413 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4414 event, ptr);
74581206 4415 case NETDEV_CHANGELOWERSTATE:
f0cebd81
IS		 4416 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4417 ptr);
74581206
JP		 4418 }
4419
80bedf1a 4420 return 0;
74581206
JP		 4421}
4422
0d65fc13
JP		 4423static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4424 unsigned long event, void *ptr)
4425{
4426 struct net_device *dev;
4427 struct list_head *iter;
4428 int ret;
4429
4430 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4431 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4432 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4433 ptr);
80bedf1a 4434 if (ret)
0d65fc13
JP		 4435 return ret;
4436 }
4437 }
4438
80bedf1a 4439 return 0;
0d65fc13
JP		 4440}
4441
f0cebd81
IS		 4442static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4443 struct net_device *dev,
4444 unsigned long event, void *ptr,
4445 u16 vid)
26f0e7fb
IS		 4446{
4447 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4448 struct netdev_notifier_changeupper_info *info = ptr;
c1f2c6d0 4449 struct netlink_ext_ack *extack;
26f0e7fb 4450 struct net_device *upper_dev;
80bedf1a 4451 int err = 0;
26f0e7fb 4452
c1f2c6d0
IS		 4453 extack = netdev_notifier_info_to_extack(&info->info);
4454
26f0e7fb
IS		 4455 switch (event) {
4456 case NETDEV_PRECHANGEUPPER:
4457 upper_dev = info->upper_dev;
c1f2c6d0
IS		 4458 if (!netif_is_bridge_master(upper_dev)) {
4459 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
80bedf1a 4460 return -EINVAL;
c1f2c6d0 4461 }
25cc72a3
IS		 4462 if (!info->linking)
4463 break;
c1f2c6d0
IS		 4464 if (netdev_has_any_upper_dev(upper_dev)) {
4465 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4466 return -EINVAL;
c1f2c6d0 4467 }
26f0e7fb
IS		 4468 break;
4469 case NETDEV_CHANGEUPPER:
4470 upper_dev = info->upper_dev;
1f88061e
IS		 4471 if (netif_is_bridge_master(upper_dev)) {
4472 if (info->linking)
c57529e1
IS		 4473 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4474 vlan_dev,
9b63ef88
IS		 4475 upper_dev,
4476 extack);
1f88061e 4477 else
c57529e1
IS		 4478 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4479 vlan_dev,
4480 upper_dev);
26f0e7fb 4481 } else {
1f88061e
IS		 4482 err = -EINVAL;
4483 WARN_ON(1);
26f0e7fb 4484 }
1f88061e 4485 break;
26f0e7fb
IS		 4486 }
4487
80bedf1a 4488 return err;
26f0e7fb
IS		 4489}
4490
f0cebd81
IS		 4491static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4492 struct net_device *lag_dev,
4493 unsigned long event,
4494 void *ptr, u16 vid)
272c4470
IS		 4495{
4496 struct net_device *dev;
4497 struct list_head *iter;
4498 int ret;
4499
4500 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4501 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4502 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4503 event, ptr,
4504 vid);
80bedf1a 4505 if (ret)
272c4470
IS		 4506 return ret;
4507 }
4508 }
4509
80bedf1a 4510 return 0;
272c4470
IS		 4511}
4512
26f0e7fb
IS		 4513static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4514 unsigned long event, void *ptr)
4515{
4516 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4517 u16 vid = vlan_dev_vlan_id(vlan_dev);
4518
272c4470 4519 if (mlxsw_sp_port_dev_check(real_dev))
f0cebd81
IS		 4520 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4521 event, ptr, vid);
272c4470 4522 else if (netif_is_lag_master(real_dev))
f0cebd81
IS		 4523 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4524 real_dev, event,
4525 ptr, vid);
26f0e7fb 4526
80bedf1a 4527 return 0;
26f0e7fb
IS		 4528}
4529
b1e45526
IS		 4530static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4531{
4532 struct netdev_notifier_changeupper_info *info = ptr;
4533
4534 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4535 return false;
4536 return netif_is_l3_master(info->upper_dev);
4537}
4538
0063587d 4539static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
0d65fc13
JP		 4540 unsigned long event, void *ptr)
4541{
4542 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
0063587d 4543 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4544 int err = 0;
0d65fc13 4545
0063587d 4546 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
796ec776
PM		 4547 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4548 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4549 event, ptr);
61481f2f
PM		 4550 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4551 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4552 event, ptr);
0063587d 4553 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
6e095fd4 4554 err = mlxsw_sp_netdevice_router_port_event(dev);
b1e45526
IS		 4555 else if (mlxsw_sp_is_vrf_event(event, ptr))
4556 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6e095fd4 4557 else if (mlxsw_sp_port_dev_check(dev))
f0cebd81 4558 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
80bedf1a
IS		 4559 else if (netif_is_lag_master(dev))
4560 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4561 else if (is_vlan_dev(dev))
4562 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 4563
80bedf1a 4564 return notifier_from_errno(err);
0d65fc13
JP		 4565}
4566
89d5dd2e
DA		 4567static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4568 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4569};
4570
99724c18
IS		 4571static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4572 .notifier_call = mlxsw_sp_inetaddr_event,
89d5dd2e
DA		 4573};
4574
4575static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4576 .notifier_call = mlxsw_sp_inet6addr_valid_event,
99724c18
IS		 4577};
4578
5ea1237f
AS		 4579static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4580 .notifier_call = mlxsw_sp_inet6addr_event,
4581};
4582
1d20d23c
JP		 4583static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4584 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4585 {0, },
4586};
4587
4588static struct pci_driver mlxsw_sp_pci_driver = {
4589 .name = mlxsw_sp_driver_name,
4590 .id_table = mlxsw_sp_pci_id_table,
4591};
4592
56ade8fe
JP		 4593static int __init mlxsw_sp_module_init(void)
4594{
4595 int err;
4596
89d5dd2e 4597 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
99724c18 4598 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4599 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5ea1237f 4600 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
e7322638 4601
56ade8fe
JP		 4602 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4603 if (err)
4604 goto err_core_driver_register;
1d20d23c
JP		 4605
4606 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4607 if (err)
4608 goto err_pci_driver_register;
4609
56ade8fe
JP		 4610 return 0;
4611
1d20d23c
JP		 4612err_pci_driver_register:
4613 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 4614err_core_driver_register:
5ea1237f 4615 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 4616 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
de7d6295 4617 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4618 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 4619 return err;
4620}
4621
4622static void __exit mlxsw_sp_module_exit(void)
4623{
1d20d23c 4624 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 4625 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
5ea1237f 4626 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 4627 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
99724c18 4628 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4629 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 4630}
4631
4632module_init(mlxsw_sp_module_init);
4633module_exit(mlxsw_sp_module_exit);
4634
4635MODULE_LICENSE("Dual BSD/GPL");
4636MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4637MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 4638MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
6b742199 4639MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);
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