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mlxsw: reg: Add lossless settings for PBMC register
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
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56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
7f71eb46 51#include <linux/list.h>
90183b98 52#include <linux/dcbnl.h>
c4745500 53#include <net/devlink.h>
56ade8fe
JP		 54#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
56ade8fe
JP		 192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
251static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
252{
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
256 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
260static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
261 bool enable)
262{
263 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
264 char svpe_pl[MLXSW_REG_SVPE_LEN];
265
266 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
267 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
268}
269
270int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
271 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
272 u16 vid)
273{
274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
275 char svfa_pl[MLXSW_REG_SVFA_LEN];
276
277 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
278 fid, vid);
279 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
280}
281
282static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
283 u16 vid, bool learn_enable)
284{
285 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
286 char *spvmlr_pl;
287 int err;
288
289 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
290 if (!spvmlr_pl)
291 return -ENOMEM;
292 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
293 learn_enable);
294 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
295 kfree(spvmlr_pl);
296 return err;
297}
298
299static int
300mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
301{
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
303 char sspr_pl[MLXSW_REG_SSPR_LEN];
304
305 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
306 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
307}
308
2bf9a586
IS		 309static int __mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
310 u8 local_port, u8 *p_module,
311 u8 *p_width, u8 *p_lane)
56ade8fe 312{
56ade8fe
JP		 313 char pmlp_pl[MLXSW_REG_PMLP_LEN];
314 int err;
315
558c2d5e 316 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 317 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
318 if (err)
319 return err;
558c2d5e
IS		 320 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
321 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 322 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 323 return 0;
324}
325
2bf9a586
IS		 326static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
327 u8 local_port, u8 *p_module,
328 u8 *p_width)
329{
330 u8 lane;
331
332 return __mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, p_module,
333 p_width, &lane);
334}
335
18f1e70c
IS		 336static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
337 u8 module, u8 width, u8 lane)
338{
339 char pmlp_pl[MLXSW_REG_PMLP_LEN];
340 int i;
341
342 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
343 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
344 for (i = 0; i < width; i++) {
345 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
346 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
347 }
348
349 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
350}
351
3e9b27b8
IS		 352static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
353{
354 char pmlp_pl[MLXSW_REG_PMLP_LEN];
355
356 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
357 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
358 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
359}
360
56ade8fe
JP		 361static int mlxsw_sp_port_open(struct net_device *dev)
362{
363 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
364 int err;
365
366 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
367 if (err)
368 return err;
369 netif_start_queue(dev);
370 return 0;
371}
372
373static int mlxsw_sp_port_stop(struct net_device *dev)
374{
375 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
376
377 netif_stop_queue(dev);
378 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
379}
380
381static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
382 struct net_device *dev)
383{
384 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
385 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
386 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
387 const struct mlxsw_tx_info tx_info = {
388 .local_port = mlxsw_sp_port->local_port,
389 .is_emad = false,
390 };
391 u64 len;
392 int err;
393
394 if (mlxsw_core_skb_transmit_busy(mlxsw_sp, &tx_info))
395 return NETDEV_TX_BUSY;
396
397 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
398 struct sk_buff *skb_orig = skb;
399
400 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
401 if (!skb) {
402 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
403 dev_kfree_skb_any(skb_orig);
404 return NETDEV_TX_OK;
405 }
406 }
407
408 if (eth_skb_pad(skb)) {
409 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
410 return NETDEV_TX_OK;
411 }
412
413 mlxsw_sp_txhdr_construct(skb, &tx_info);
414 len = skb->len;
415 /* Due to a race we might fail here because of a full queue. In that
416 * unlikely case we simply drop the packet.
417 */
418 err = mlxsw_core_skb_transmit(mlxsw_sp, skb, &tx_info);
419
420 if (!err) {
421 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
422 u64_stats_update_begin(&pcpu_stats->syncp);
423 pcpu_stats->tx_packets++;
424 pcpu_stats->tx_bytes += len;
425 u64_stats_update_end(&pcpu_stats->syncp);
426 } else {
427 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
428 dev_kfree_skb_any(skb);
429 }
430 return NETDEV_TX_OK;
431}
432
c5b9b518
JP		 433static void mlxsw_sp_set_rx_mode(struct net_device *dev)
434{
435}
436
56ade8fe
JP		 437static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
438{
439 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
440 struct sockaddr *addr = p;
441 int err;
442
443 if (!is_valid_ether_addr(addr->sa_data))
444 return -EADDRNOTAVAIL;
445
446 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
447 if (err)
448 return err;
449 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
450 return 0;
451}
452
8e8dfe9f 453static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu)
ff6551ec 454{
ff6551ec 455 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
8e8dfe9f
IS		 456
457 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
458}
459
460int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
461 u8 *prio_tc)
462{
463 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
ff6551ec 464 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 465 int i, j, err;
ff6551ec
IS		 466
467 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
468 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
469 if (err)
470 return err;
8e8dfe9f
IS		 471
472 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
473 bool configure = false;
474
475 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
476 if (prio_tc[j] == i) {
477 configure = true;
478 break;
479 }
480 }
481
482 if (!configure)
483 continue;
484 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu);
485 }
486
ff6551ec
IS		 487 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
488}
489
8e8dfe9f
IS		 490static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
491 int mtu)
492{
493 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
494 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
495 u8 *prio_tc;
496
497 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
498
499 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc);
500}
501
56ade8fe
JP		 502static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
503{
504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
505 int err;
506
ff6551ec 507 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu);
56ade8fe
JP		 508 if (err)
509 return err;
ff6551ec
IS		 510 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
511 if (err)
512 goto err_port_mtu_set;
56ade8fe
JP		 513 dev->mtu = mtu;
514 return 0;
ff6551ec
IS		 515
516err_port_mtu_set:
517 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu);
518 return err;
56ade8fe
JP		 519}
520
521static struct rtnl_link_stats64 *
522mlxsw_sp_port_get_stats64(struct net_device *dev,
523 struct rtnl_link_stats64 *stats)
524{
525 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
526 struct mlxsw_sp_port_pcpu_stats *p;
527 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
528 u32 tx_dropped = 0;
529 unsigned int start;
530 int i;
531
532 for_each_possible_cpu(i) {
533 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
534 do {
535 start = u64_stats_fetch_begin_irq(&p->syncp);
536 rx_packets = p->rx_packets;
537 rx_bytes = p->rx_bytes;
538 tx_packets = p->tx_packets;
539 tx_bytes = p->tx_bytes;
540 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
541
542 stats->rx_packets += rx_packets;
543 stats->rx_bytes += rx_bytes;
544 stats->tx_packets += tx_packets;
545 stats->tx_bytes += tx_bytes;
546 /* tx_dropped is u32, updated without syncp protection. */
547 tx_dropped += p->tx_dropped;
548 }
549 stats->tx_dropped = tx_dropped;
550 return stats;
551}
552
553int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
554 u16 vid_end, bool is_member, bool untagged)
555{
556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
557 char *spvm_pl;
558 int err;
559
560 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
561 if (!spvm_pl)
562 return -ENOMEM;
563
564 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
565 vid_end, is_member, untagged);
566 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
567 kfree(spvm_pl);
568 return err;
569}
570
571static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
572{
573 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
574 u16 vid, last_visited_vid;
575 int err;
576
577 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
578 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
579 vid);
580 if (err) {
581 last_visited_vid = vid;
582 goto err_port_vid_to_fid_set;
583 }
584 }
585
586 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
587 if (err) {
588 last_visited_vid = VLAN_N_VID;
589 goto err_port_vid_to_fid_set;
590 }
591
592 return 0;
593
594err_port_vid_to_fid_set:
595 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
596 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
597 vid);
598 return err;
599}
600
601static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
602{
603 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
604 u16 vid;
605 int err;
606
607 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
608 if (err)
609 return err;
610
611 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
612 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
613 vid, vid);
614 if (err)
615 return err;
616 }
617
618 return 0;
619}
620
7f71eb46
IS		 621static struct mlxsw_sp_vfid *
622mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
623{
624 struct mlxsw_sp_vfid *vfid;
625
626 list_for_each_entry(vfid, &mlxsw_sp->port_vfids.list, list) {
627 if (vfid->vid == vid)
628 return vfid;
629 }
630
631 return NULL;
632}
633
634static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
635{
636 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
637 MLXSW_SP_VFID_PORT_MAX);
638}
639
640static int __mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp, u16 vfid)
641{
642 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
643 char sfmr_pl[MLXSW_REG_SFMR_LEN];
644
645 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID, fid, 0);
646 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
647}
648
649static void __mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp, u16 vfid)
650{
651 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
652 char sfmr_pl[MLXSW_REG_SFMR_LEN];
653
654 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_DESTROY_FID, fid, 0);
655 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
656}
657
658static struct mlxsw_sp_vfid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
659 u16 vid)
660{
661 struct device *dev = mlxsw_sp->bus_info->dev;
662 struct mlxsw_sp_vfid *vfid;
663 u16 n_vfid;
664 int err;
665
666 n_vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
667 if (n_vfid == MLXSW_SP_VFID_PORT_MAX) {
668 dev_err(dev, "No available vFIDs\n");
669 return ERR_PTR(-ERANGE);
670 }
671
672 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
673 if (err) {
674 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
675 return ERR_PTR(err);
676 }
677
678 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
679 if (!vfid)
680 goto err_allocate_vfid;
681
682 vfid->vfid = n_vfid;
683 vfid->vid = vid;
684
685 list_add(&vfid->list, &mlxsw_sp->port_vfids.list);
686 set_bit(n_vfid, mlxsw_sp->port_vfids.mapped);
687
688 return vfid;
689
690err_allocate_vfid:
691 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
692 return ERR_PTR(-ENOMEM);
693}
694
695static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
696 struct mlxsw_sp_vfid *vfid)
697{
698 clear_bit(vfid->vfid, mlxsw_sp->port_vfids.mapped);
699 list_del(&vfid->list);
700
701 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
702
703 kfree(vfid);
704}
705
706static struct mlxsw_sp_port *
707mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port,
708 struct mlxsw_sp_vfid *vfid)
709{
710 struct mlxsw_sp_port *mlxsw_sp_vport;
711
712 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
713 if (!mlxsw_sp_vport)
714 return NULL;
715
716 /* dev will be set correctly after the VLAN device is linked
717 * with the real device. In case of bridge SELF invocation, dev
718 * will remain as is.
719 */
720 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
721 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
722 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
723 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
272c4470
IS		 724 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
725 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
7f71eb46
IS		 726 mlxsw_sp_vport->vport.vfid = vfid;
727 mlxsw_sp_vport->vport.vid = vfid->vid;
728
729 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
730
731 return mlxsw_sp_vport;
732}
733
734static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
735{
736 list_del(&mlxsw_sp_vport->vport.list);
737 kfree(mlxsw_sp_vport);
738}
739
56ade8fe
JP		 740int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
741 u16 vid)
742{
743 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
744 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
7f71eb46
IS		 745 struct mlxsw_sp_port *mlxsw_sp_vport;
746 struct mlxsw_sp_vfid *vfid;
56ade8fe
JP		 747 int err;
748
749 /* VLAN 0 is added to HW filter when device goes up, but it is
750 * reserved in our case, so simply return.
751 */
752 if (!vid)
753 return 0;
754
7f71eb46 755 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
56ade8fe
JP		 756 netdev_warn(dev, "VID=%d already configured\n", vid);
757 return 0;
758 }
759
7f71eb46
IS		 760 vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
761 if (!vfid) {
762 vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
763 if (IS_ERR(vfid)) {
764 netdev_err(dev, "Failed to create vFID for VID=%d\n",
765 vid);
766 return PTR_ERR(vfid);
56ade8fe 767 }
7f71eb46 768 }
56ade8fe 769
7f71eb46
IS		 770 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vfid);
771 if (!mlxsw_sp_vport) {
772 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
773 err = -ENOMEM;
774 goto err_port_vport_create;
775 }
776
777 if (!vfid->nr_vports) {
778 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid,
19ae6124 779 true, false);
56ade8fe 780 if (err) {
7f71eb46
IS		 781 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
782 vfid->vfid);
783 goto err_vport_flood_set;
56ade8fe
JP		 784 }
785 }
786
56ade8fe
JP		 787 /* When adding the first VLAN interface on a bridged port we need to
788 * transition all the active 802.1Q bridge VLANs to use explicit
789 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
790 */
7f71eb46 791 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 792 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
793 if (err) {
794 netdev_err(dev, "Failed to set to Virtual mode\n");
7f71eb46 795 goto err_port_vp_mode_trans;
56ade8fe
JP		 796 }
797 }
798
7f71eb46 799 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
56ade8fe 800 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
7f71eb46
IS		 801 true,
802 mlxsw_sp_vfid_to_fid(vfid->vfid),
803 vid);
56ade8fe
JP		 804 if (err) {
805 netdev_err(dev, "Failed to map {Port, VID=%d} to vFID=%d\n",
7f71eb46 806 vid, vfid->vfid);
56ade8fe
JP		 807 goto err_port_vid_to_fid_set;
808 }
809
7f71eb46 810 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
56ade8fe
JP		 811 if (err) {
812 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
813 goto err_port_vid_learning_set;
814 }
815
7f71eb46 816 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
56ade8fe
JP		 817 if (err) {
818 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
819 vid);
820 goto err_port_add_vid;
821 }
822
7f71eb46 823 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 824 MLXSW_REG_SPMS_STATE_FORWARDING);
825 if (err) {
826 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
827 goto err_port_stp_state_set;
828 }
829
7f71eb46 830 vfid->nr_vports++;
56ade8fe
JP		 831
832 return 0;
833
56ade8fe 834err_port_stp_state_set:
7f71eb46 835 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe 836err_port_add_vid:
7f71eb46 837 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe 838err_port_vid_learning_set:
7f71eb46 839 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
56ade8fe 840 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
7f71eb46 841 mlxsw_sp_vfid_to_fid(vfid->vfid), vid);
56ade8fe 842err_port_vid_to_fid_set:
7f71eb46
IS		 843 if (list_is_singular(&mlxsw_sp_port->vports_list))
844 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
845err_port_vp_mode_trans:
846 if (!vfid->nr_vports)
19ae6124
IS		 847 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
848 false);
7f71eb46
IS		 849err_vport_flood_set:
850 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
851err_port_vport_create:
852 if (!vfid->nr_vports)
853 mlxsw_sp_vfid_destroy(mlxsw_sp, vfid);
56ade8fe
JP		 854 return err;
855}
856
857int mlxsw_sp_port_kill_vid(struct net_device *dev,
858 __be16 __always_unused proto, u16 vid)
859{
860 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46
IS		 861 struct mlxsw_sp_port *mlxsw_sp_vport;
862 struct mlxsw_sp_vfid *vfid;
56ade8fe
JP		 863 int err;
864
865 /* VLAN 0 is removed from HW filter when device goes down, but
866 * it is reserved in our case, so simply return.
867 */
868 if (!vid)
869 return 0;
870
7f71eb46
IS		 871 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
872 if (!mlxsw_sp_vport) {
56ade8fe
JP		 873 netdev_warn(dev, "VID=%d does not exist\n", vid);
874 return 0;
875 }
876
7f71eb46
IS		 877 vfid = mlxsw_sp_vport->vport.vfid;
878
879 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 880 MLXSW_REG_SPMS_STATE_DISCARDING);
881 if (err) {
882 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
883 return err;
884 }
885
7f71eb46 886 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe
JP		 887 if (err) {
888 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
889 vid);
890 return err;
891 }
892
7f71eb46 893 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe
JP		 894 if (err) {
895 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
896 return err;
897 }
898
7f71eb46 899 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
56ade8fe 900 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
7f71eb46
IS		 901 false,
902 mlxsw_sp_vfid_to_fid(vfid->vfid),
56ade8fe
JP		 903 vid);
904 if (err) {
905 netdev_err(dev, "Failed to invalidate {Port, VID=%d} to vFID=%d mapping\n",
7f71eb46 906 vid, vfid->vfid);
56ade8fe
JP		 907 return err;
908 }
909
910 /* When removing the last VLAN interface on a bridged port we need to
911 * transition all active 802.1Q bridge VLANs to use VID to FID
912 * mappings and set port's mode to VLAN mode.
913 */
7f71eb46 914 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 915 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
916 if (err) {
917 netdev_err(dev, "Failed to set to VLAN mode\n");
918 return err;
919 }
920 }
921
7f71eb46
IS		 922 vfid->nr_vports--;
923 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
924
925 /* Destroy the vFID if no vPorts are assigned to it anymore. */
926 if (!vfid->nr_vports)
927 mlxsw_sp_vfid_destroy(mlxsw_sp_port->mlxsw_sp, vfid);
56ade8fe
JP		 928
929 return 0;
930}
931
2bf9a586
IS		 932static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
933 size_t len)
934{
935 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
936 u8 module, width, lane;
937 int err;
938
939 err = __mlxsw_sp_port_module_info_get(mlxsw_sp_port->mlxsw_sp,
940 mlxsw_sp_port->local_port,
941 &module, &width, &lane);
942 if (err) {
943 netdev_err(dev, "Failed to retrieve module information\n");
944 return err;
945 }
946
947 if (!mlxsw_sp_port->split)
948 err = snprintf(name, len, "p%d", module + 1);
949 else
950 err = snprintf(name, len, "p%ds%d", module + 1,
951 lane / width);
952
953 if (err >= len)
954 return -EINVAL;
955
956 return 0;
957}
958
56ade8fe
JP		 959static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
960 .ndo_open = mlxsw_sp_port_open,
961 .ndo_stop = mlxsw_sp_port_stop,
962 .ndo_start_xmit = mlxsw_sp_port_xmit,
c5b9b518 963 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 964 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
965 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
966 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
967 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
968 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
969 .ndo_fdb_add = switchdev_port_fdb_add,
970 .ndo_fdb_del = switchdev_port_fdb_del,
971 .ndo_fdb_dump = switchdev_port_fdb_dump,
972 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
973 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
974 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
2bf9a586 975 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 976};
977
978static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
979 struct ethtool_drvinfo *drvinfo)
980{
981 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
982 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
983
984 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
985 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
986 sizeof(drvinfo->version));
987 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
988 "%d.%d.%d",
989 mlxsw_sp->bus_info->fw_rev.major,
990 mlxsw_sp->bus_info->fw_rev.minor,
991 mlxsw_sp->bus_info->fw_rev.subminor);
992 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
993 sizeof(drvinfo->bus_info));
994}
995
996struct mlxsw_sp_port_hw_stats {
997 char str[ETH_GSTRING_LEN];
998 u64 (*getter)(char *payload);
999};
1000
1001static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1002 {
1003 .str = "a_frames_transmitted_ok",
1004 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1005 },
1006 {
1007 .str = "a_frames_received_ok",
1008 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1009 },
1010 {
1011 .str = "a_frame_check_sequence_errors",
1012 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1013 },
1014 {
1015 .str = "a_alignment_errors",
1016 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1017 },
1018 {
1019 .str = "a_octets_transmitted_ok",
1020 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1021 },
1022 {
1023 .str = "a_octets_received_ok",
1024 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1025 },
1026 {
1027 .str = "a_multicast_frames_xmitted_ok",
1028 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1029 },
1030 {
1031 .str = "a_broadcast_frames_xmitted_ok",
1032 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1033 },
1034 {
1035 .str = "a_multicast_frames_received_ok",
1036 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1037 },
1038 {
1039 .str = "a_broadcast_frames_received_ok",
1040 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1041 },
1042 {
1043 .str = "a_in_range_length_errors",
1044 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1045 },
1046 {
1047 .str = "a_out_of_range_length_field",
1048 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1049 },
1050 {
1051 .str = "a_frame_too_long_errors",
1052 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1053 },
1054 {
1055 .str = "a_symbol_error_during_carrier",
1056 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1057 },
1058 {
1059 .str = "a_mac_control_frames_transmitted",
1060 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1061 },
1062 {
1063 .str = "a_mac_control_frames_received",
1064 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1065 },
1066 {
1067 .str = "a_unsupported_opcodes_received",
1068 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1069 },
1070 {
1071 .str = "a_pause_mac_ctrl_frames_received",
1072 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1073 },
1074 {
1075 .str = "a_pause_mac_ctrl_frames_xmitted",
1076 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1077 },
1078};
1079
1080#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1081
1082static void mlxsw_sp_port_get_strings(struct net_device *dev,
1083 u32 stringset, u8 *data)
1084{
1085 u8 *p = data;
1086 int i;
1087
1088 switch (stringset) {
1089 case ETH_SS_STATS:
1090 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1091 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1092 ETH_GSTRING_LEN);
1093 p += ETH_GSTRING_LEN;
1094 }
1095 break;
1096 }
1097}
1098
3a66ee38
IS		 1099static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1100 enum ethtool_phys_id_state state)
1101{
1102 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1104 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1105 bool active;
1106
1107 switch (state) {
1108 case ETHTOOL_ID_ACTIVE:
1109 active = true;
1110 break;
1111 case ETHTOOL_ID_INACTIVE:
1112 active = false;
1113 break;
1114 default:
1115 return -EOPNOTSUPP;
1116 }
1117
1118 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1119 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1120}
1121
56ade8fe
JP		 1122static void mlxsw_sp_port_get_stats(struct net_device *dev,
1123 struct ethtool_stats *stats, u64 *data)
1124{
1125 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1126 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1127 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1128 int i;
1129 int err;
1130
1131 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port);
1132 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1133 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1134 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1135}
1136
1137static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1138{
1139 switch (sset) {
1140 case ETH_SS_STATS:
1141 return MLXSW_SP_PORT_HW_STATS_LEN;
1142 default:
1143 return -EOPNOTSUPP;
1144 }
1145}
1146
1147struct mlxsw_sp_port_link_mode {
1148 u32 mask;
1149 u32 supported;
1150 u32 advertised;
1151 u32 speed;
1152};
1153
1154static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1155 {
1156 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1157 .supported = SUPPORTED_100baseT_Full,
1158 .advertised = ADVERTISED_100baseT_Full,
1159 .speed = 100,
1160 },
1161 {
1162 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1163 .speed = 100,
1164 },
1165 {
1166 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1167 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1168 .supported = SUPPORTED_1000baseKX_Full,
1169 .advertised = ADVERTISED_1000baseKX_Full,
1170 .speed = 1000,
1171 },
1172 {
1173 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1174 .supported = SUPPORTED_10000baseT_Full,
1175 .advertised = ADVERTISED_10000baseT_Full,
1176 .speed = 10000,
1177 },
1178 {
1179 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1180 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1181 .supported = SUPPORTED_10000baseKX4_Full,
1182 .advertised = ADVERTISED_10000baseKX4_Full,
1183 .speed = 10000,
1184 },
1185 {
1186 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1187 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1188 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1189 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1190 .supported = SUPPORTED_10000baseKR_Full,
1191 .advertised = ADVERTISED_10000baseKR_Full,
1192 .speed = 10000,
1193 },
1194 {
1195 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1196 .supported = SUPPORTED_20000baseKR2_Full,
1197 .advertised = ADVERTISED_20000baseKR2_Full,
1198 .speed = 20000,
1199 },
1200 {
1201 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1202 .supported = SUPPORTED_40000baseCR4_Full,
1203 .advertised = ADVERTISED_40000baseCR4_Full,
1204 .speed = 40000,
1205 },
1206 {
1207 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1208 .supported = SUPPORTED_40000baseKR4_Full,
1209 .advertised = ADVERTISED_40000baseKR4_Full,
1210 .speed = 40000,
1211 },
1212 {
1213 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1214 .supported = SUPPORTED_40000baseSR4_Full,
1215 .advertised = ADVERTISED_40000baseSR4_Full,
1216 .speed = 40000,
1217 },
1218 {
1219 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1220 .supported = SUPPORTED_40000baseLR4_Full,
1221 .advertised = ADVERTISED_40000baseLR4_Full,
1222 .speed = 40000,
1223 },
1224 {
1225 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1226 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1227 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1228 .speed = 25000,
1229 },
1230 {
1231 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1232 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1233 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1234 .speed = 50000,
1235 },
1236 {
1237 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1238 .supported = SUPPORTED_56000baseKR4_Full,
1239 .advertised = ADVERTISED_56000baseKR4_Full,
1240 .speed = 56000,
1241 },
1242 {
1243 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1244 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1245 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1246 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1247 .speed = 100000,
1248 },
1249};
1250
1251#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1252
1253static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1254{
1255 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1256 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1257 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1258 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1259 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1260 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1261 return SUPPORTED_FIBRE;
1262
1263 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1264 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1265 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1266 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1267 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1268 return SUPPORTED_Backplane;
1269 return 0;
1270}
1271
1272static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1273{
1274 u32 modes = 0;
1275 int i;
1276
1277 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1278 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1279 modes |= mlxsw_sp_port_link_mode[i].supported;
1280 }
1281 return modes;
1282}
1283
1284static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1285{
1286 u32 modes = 0;
1287 int i;
1288
1289 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1290 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1291 modes |= mlxsw_sp_port_link_mode[i].advertised;
1292 }
1293 return modes;
1294}
1295
1296static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1297 struct ethtool_cmd *cmd)
1298{
1299 u32 speed = SPEED_UNKNOWN;
1300 u8 duplex = DUPLEX_UNKNOWN;
1301 int i;
1302
1303 if (!carrier_ok)
1304 goto out;
1305
1306 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1307 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1308 speed = mlxsw_sp_port_link_mode[i].speed;
1309 duplex = DUPLEX_FULL;
1310 break;
1311 }
1312 }
1313out:
1314 ethtool_cmd_speed_set(cmd, speed);
1315 cmd->duplex = duplex;
1316}
1317
1318static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1319{
1320 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1321 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1322 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1323 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1324 return PORT_FIBRE;
1325
1326 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1327 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1328 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1329 return PORT_DA;
1330
1331 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1332 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1333 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1334 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1335 return PORT_NONE;
1336
1337 return PORT_OTHER;
1338}
1339
1340static int mlxsw_sp_port_get_settings(struct net_device *dev,
1341 struct ethtool_cmd *cmd)
1342{
1343 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1344 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1345 char ptys_pl[MLXSW_REG_PTYS_LEN];
1346 u32 eth_proto_cap;
1347 u32 eth_proto_admin;
1348 u32 eth_proto_oper;
1349 int err;
1350
1351 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1352 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1353 if (err) {
1354 netdev_err(dev, "Failed to get proto");
1355 return err;
1356 }
1357 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1358 &eth_proto_admin, &eth_proto_oper);
1359
1360 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1361 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1362 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1363 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1364 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1365 eth_proto_oper, cmd);
1366
1367 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1368 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1369 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1370
1371 cmd->transceiver = XCVR_INTERNAL;
1372 return 0;
1373}
1374
1375static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1376{
1377 u32 ptys_proto = 0;
1378 int i;
1379
1380 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1381 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1382 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1383 }
1384 return ptys_proto;
1385}
1386
1387static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1388{
1389 u32 ptys_proto = 0;
1390 int i;
1391
1392 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1393 if (speed == mlxsw_sp_port_link_mode[i].speed)
1394 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1395 }
1396 return ptys_proto;
1397}
1398
18f1e70c
IS		 1399static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1400{
1401 u32 ptys_proto = 0;
1402 int i;
1403
1404 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1405 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1406 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1407 }
1408 return ptys_proto;
1409}
1410
56ade8fe
JP		 1411static int mlxsw_sp_port_set_settings(struct net_device *dev,
1412 struct ethtool_cmd *cmd)
1413{
1414 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1415 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1416 char ptys_pl[MLXSW_REG_PTYS_LEN];
1417 u32 speed;
1418 u32 eth_proto_new;
1419 u32 eth_proto_cap;
1420 u32 eth_proto_admin;
1421 bool is_up;
1422 int err;
1423
1424 speed = ethtool_cmd_speed(cmd);
1425
1426 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1427 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1428 mlxsw_sp_to_ptys_speed(speed);
1429
1430 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1431 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1432 if (err) {
1433 netdev_err(dev, "Failed to get proto");
1434 return err;
1435 }
1436 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1437
1438 eth_proto_new = eth_proto_new & eth_proto_cap;
1439 if (!eth_proto_new) {
1440 netdev_err(dev, "Not supported proto admin requested");
1441 return -EINVAL;
1442 }
1443 if (eth_proto_new == eth_proto_admin)
1444 return 0;
1445
1446 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1447 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1448 if (err) {
1449 netdev_err(dev, "Failed to set proto admin");
1450 return err;
1451 }
1452
1453 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1454 if (err) {
1455 netdev_err(dev, "Failed to get oper status");
1456 return err;
1457 }
1458 if (!is_up)
1459 return 0;
1460
1461 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1462 if (err) {
1463 netdev_err(dev, "Failed to set admin status");
1464 return err;
1465 }
1466
1467 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1468 if (err) {
1469 netdev_err(dev, "Failed to set admin status");
1470 return err;
1471 }
1472
1473 return 0;
1474}
1475
1476static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1477 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1478 .get_link = ethtool_op_get_link,
1479 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 1480 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 1481 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1482 .get_sset_count = mlxsw_sp_port_get_sset_count,
1483 .get_settings = mlxsw_sp_port_get_settings,
1484 .set_settings = mlxsw_sp_port_set_settings,
1485};
1486
18f1e70c
IS		 1487static int
1488mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1489{
1490 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1491 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1492 char ptys_pl[MLXSW_REG_PTYS_LEN];
1493 u32 eth_proto_admin;
1494
1495 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1496 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1497 eth_proto_admin);
1498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1499}
1500
8e8dfe9f
IS		 1501int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1502 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1503 bool dwrr, u8 dwrr_weight)
90183b98
IS		 1504{
1505 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1506 char qeec_pl[MLXSW_REG_QEEC_LEN];
1507
1508 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1509 next_index);
1510 mlxsw_reg_qeec_de_set(qeec_pl, true);
1511 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1512 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1513 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1514}
1515
cc7cf517
IS		 1516int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1517 enum mlxsw_reg_qeec_hr hr, u8 index,
1518 u8 next_index, u32 maxrate)
90183b98
IS		 1519{
1520 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1521 char qeec_pl[MLXSW_REG_QEEC_LEN];
1522
1523 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1524 next_index);
1525 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1526 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1527 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1528}
1529
8e8dfe9f
IS		 1530int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1531 u8 switch_prio, u8 tclass)
90183b98
IS		 1532{
1533 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1534 char qtct_pl[MLXSW_REG_QTCT_LEN];
1535
1536 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1537 tclass);
1538 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1539}
1540
1541static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1542{
1543 int err, i;
1544
1545 /* Setup the elements hierarcy, so that each TC is linked to
1546 * one subgroup, which are all member in the same group.
1547 */
1548 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1549 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1550 0);
1551 if (err)
1552 return err;
1553 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1554 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1555 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1556 0, false, 0);
1557 if (err)
1558 return err;
1559 }
1560 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1561 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1562 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1563 false, 0);
1564 if (err)
1565 return err;
1566 }
1567
1568 /* Make sure the max shaper is disabled in all hierarcies that
1569 * support it.
1570 */
1571 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1572 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1573 MLXSW_REG_QEEC_MAS_DIS);
1574 if (err)
1575 return err;
1576 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1577 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1578 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1579 i, 0,
1580 MLXSW_REG_QEEC_MAS_DIS);
1581 if (err)
1582 return err;
1583 }
1584 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1585 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1586 MLXSW_REG_QEEC_HIERARCY_TC,
1587 i, i,
1588 MLXSW_REG_QEEC_MAS_DIS);
1589 if (err)
1590 return err;
1591 }
1592
1593 /* Map all priorities to traffic class 0. */
1594 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1595 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1596 if (err)
1597 return err;
1598 }
1599
1600 return 0;
1601}
1602
18f1e70c
IS		 1603static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1604 bool split, u8 module, u8 width)
56ade8fe 1605{
c4745500 1606 struct devlink *devlink = priv_to_devlink(mlxsw_sp->core);
56ade8fe 1607 struct mlxsw_sp_port *mlxsw_sp_port;
c4745500 1608 struct devlink_port *devlink_port;
56ade8fe 1609 struct net_device *dev;
bd40e9d6 1610 size_t bytes;
56ade8fe
JP		 1611 int err;
1612
1613 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1614 if (!dev)
1615 return -ENOMEM;
1616 mlxsw_sp_port = netdev_priv(dev);
1617 mlxsw_sp_port->dev = dev;
1618 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1619 mlxsw_sp_port->local_port = local_port;
18f1e70c 1620 mlxsw_sp_port->split = split;
bd40e9d6
IS		 1621 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1622 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1623 if (!mlxsw_sp_port->active_vlans) {
1624 err = -ENOMEM;
1625 goto err_port_active_vlans_alloc;
1626 }
fc1273af
ER		 1627 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1628 if (!mlxsw_sp_port->untagged_vlans) {
1629 err = -ENOMEM;
1630 goto err_port_untagged_vlans_alloc;
1631 }
7f71eb46 1632 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
56ade8fe
JP		 1633
1634 mlxsw_sp_port->pcpu_stats =
1635 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1636 if (!mlxsw_sp_port->pcpu_stats) {
1637 err = -ENOMEM;
1638 goto err_alloc_stats;
1639 }
1640
1641 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1642 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1643
1644 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1645 if (err) {
1646 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1647 mlxsw_sp_port->local_port);
1648 goto err_dev_addr_init;
1649 }
1650
1651 netif_carrier_off(dev);
1652
1653 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1654 NETIF_F_HW_VLAN_CTAG_FILTER;
1655
1656 /* Each packet needs to have a Tx header (metadata) on top all other
1657 * headers.
1658 */
1659 dev->hard_header_len += MLXSW_TXHDR_LEN;
1660
c4745500 1661 devlink_port = &mlxsw_sp_port->devlink_port;
18f1e70c
IS		 1662 if (mlxsw_sp_port->split)
1663 devlink_port_split_set(devlink_port, module);
c4745500
JP		 1664 err = devlink_port_register(devlink, devlink_port, local_port);
1665 if (err) {
1666 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register devlink port\n",
1667 mlxsw_sp_port->local_port);
1668 goto err_devlink_port_register;
1669 }
1670
56ade8fe
JP		 1671 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1672 if (err) {
1673 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1674 mlxsw_sp_port->local_port);
1675 goto err_port_system_port_mapping_set;
1676 }
1677
1678 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1679 if (err) {
1680 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1681 mlxsw_sp_port->local_port);
1682 goto err_port_swid_set;
1683 }
1684
18f1e70c
IS		 1685 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1686 if (err) {
1687 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1688 mlxsw_sp_port->local_port);
1689 goto err_port_speed_by_width_set;
1690 }
1691
56ade8fe
JP		 1692 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1693 if (err) {
1694 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1695 mlxsw_sp_port->local_port);
1696 goto err_port_mtu_set;
1697 }
1698
1699 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1700 if (err)
1701 goto err_port_admin_status_set;
1702
1703 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1704 if (err) {
1705 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1706 mlxsw_sp_port->local_port);
1707 goto err_port_buffers_init;
1708 }
1709
90183b98
IS		 1710 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1711 if (err) {
1712 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1713 mlxsw_sp_port->local_port);
1714 goto err_port_ets_init;
1715 }
1716
f00817df
IS		 1717 /* ETS and buffers must be initialized before DCB. */
1718 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1719 if (err) {
1720 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1721 mlxsw_sp_port->local_port);
1722 goto err_port_dcb_init;
1723 }
1724
56ade8fe
JP		 1725 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1726 err = register_netdev(dev);
1727 if (err) {
1728 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1729 mlxsw_sp_port->local_port);
1730 goto err_register_netdev;
1731 }
1732
c4745500
JP		 1733 devlink_port_type_eth_set(devlink_port, dev);
1734
56ade8fe
JP		 1735 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1736 if (err)
1737 goto err_port_vlan_init;
1738
1739 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1740 return 0;
1741
1742err_port_vlan_init:
1743 unregister_netdev(dev);
1744err_register_netdev:
f00817df 1745err_port_dcb_init:
90183b98 1746err_port_ets_init:
56ade8fe
JP		 1747err_port_buffers_init:
1748err_port_admin_status_set:
1749err_port_mtu_set:
18f1e70c 1750err_port_speed_by_width_set:
56ade8fe
JP		 1751err_port_swid_set:
1752err_port_system_port_mapping_set:
c4745500
JP		 1753 devlink_port_unregister(&mlxsw_sp_port->devlink_port);
1754err_devlink_port_register:
56ade8fe
JP		 1755err_dev_addr_init:
1756 free_percpu(mlxsw_sp_port->pcpu_stats);
1757err_alloc_stats:
fc1273af
ER		 1758 kfree(mlxsw_sp_port->untagged_vlans);
1759err_port_untagged_vlans_alloc:
bd40e9d6
IS		 1760 kfree(mlxsw_sp_port->active_vlans);
1761err_port_active_vlans_alloc:
56ade8fe
JP		 1762 free_netdev(dev);
1763 return err;
1764}
1765
18f1e70c
IS		 1766static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1767 bool split, u8 module, u8 width, u8 lane)
1768{
1769 int err;
1770
1771 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1772 lane);
1773 if (err)
1774 return err;
1775
1776 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split, module,
1777 width);
1778 if (err)
1779 goto err_port_create;
1780
1781 return 0;
1782
1783err_port_create:
1784 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port);
1785 return err;
1786}
1787
7f71eb46 1788static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
56ade8fe 1789{
7f71eb46
IS		 1790 struct net_device *dev = mlxsw_sp_port->dev;
1791 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
56ade8fe 1792
7f71eb46
IS		 1793 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1794 &mlxsw_sp_port->vports_list, vport.list) {
1795 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1796
1797 /* vPorts created for VLAN devices should already be gone
1798 * by now, since we unregistered the port netdev.
1799 */
1800 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1801 mlxsw_sp_port_kill_vid(dev, 0, vid);
1802 }
56ade8fe
JP		 1803}
1804
1805static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1806{
1807 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
c4745500 1808 struct devlink_port *devlink_port;
56ade8fe
JP		 1809
1810 if (!mlxsw_sp_port)
1811 return;
a133318c 1812 mlxsw_sp->ports[local_port] = NULL;
c4745500
JP		 1813 devlink_port = &mlxsw_sp_port->devlink_port;
1814 devlink_port_type_clear(devlink_port);
56ade8fe 1815 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
f00817df 1816 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
c4745500 1817 devlink_port_unregister(devlink_port);
7f71eb46 1818 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
56ade8fe 1819 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3e9b27b8
IS		 1820 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1821 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
56ade8fe 1822 free_percpu(mlxsw_sp_port->pcpu_stats);
fc1273af 1823 kfree(mlxsw_sp_port->untagged_vlans);
bd40e9d6 1824 kfree(mlxsw_sp_port->active_vlans);
56ade8fe
JP		 1825 free_netdev(mlxsw_sp_port->dev);
1826}
1827
1828static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1829{
1830 int i;
1831
1832 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1833 mlxsw_sp_port_remove(mlxsw_sp, i);
1834 kfree(mlxsw_sp->ports);
1835}
1836
1837static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1838{
1839 size_t alloc_size;
558c2d5e 1840 u8 module, width;
56ade8fe
JP		 1841 int i;
1842 int err;
1843
1844 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1845 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1846 if (!mlxsw_sp->ports)
1847 return -ENOMEM;
1848
1849 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
558c2d5e
IS		 1850 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
1851 &width);
1852 if (err)
1853 goto err_port_module_info_get;
1854 if (!width)
1855 continue;
1856 mlxsw_sp->port_to_module[i] = module;
18f1e70c 1857 err = __mlxsw_sp_port_create(mlxsw_sp, i, false, module, width);
56ade8fe
JP		 1858 if (err)
1859 goto err_port_create;
1860 }
1861 return 0;
1862
1863err_port_create:
558c2d5e 1864err_port_module_info_get:
56ade8fe
JP		 1865 for (i--; i >= 1; i--)
1866 mlxsw_sp_port_remove(mlxsw_sp, i);
1867 kfree(mlxsw_sp->ports);
1868 return err;
1869}
1870
18f1e70c
IS		 1871static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1872{
1873 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1874
1875 return local_port - offset;
1876}
1877
1878static int mlxsw_sp_port_split(void *priv, u8 local_port, unsigned int count)
1879{
1880 struct mlxsw_sp *mlxsw_sp = priv;
1881 struct mlxsw_sp_port *mlxsw_sp_port;
1882 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1883 u8 module, cur_width, base_port;
1884 int i;
1885 int err;
1886
1887 mlxsw_sp_port = mlxsw_sp->ports[local_port];
1888 if (!mlxsw_sp_port) {
1889 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
1890 local_port);
1891 return -EINVAL;
1892 }
1893
1894 if (count != 2 && count != 4) {
1895 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
1896 return -EINVAL;
1897 }
1898
1899 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
1900 &cur_width);
1901 if (err) {
1902 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
1903 return err;
1904 }
1905
1906 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
1907 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
1908 return -EINVAL;
1909 }
1910
1911 /* Make sure we have enough slave (even) ports for the split. */
1912 if (count == 2) {
1913 base_port = local_port;
1914 if (mlxsw_sp->ports[base_port + 1]) {
1915 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1916 return -EINVAL;
1917 }
1918 } else {
1919 base_port = mlxsw_sp_cluster_base_port_get(local_port);
1920 if (mlxsw_sp->ports[base_port + 1] ||
1921 mlxsw_sp->ports[base_port + 3]) {
1922 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1923 return -EINVAL;
1924 }
1925 }
1926
1927 for (i = 0; i < count; i++)
1928 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1929
1930 for (i = 0; i < count; i++) {
1931 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
1932 module, width, i * width);
1933 if (err) {
1934 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split port\n");
1935 goto err_port_create;
1936 }
1937 }
1938
1939 return 0;
1940
1941err_port_create:
1942 for (i--; i >= 0; i--)
1943 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1944 for (i = 0; i < count / 2; i++) {
1945 module = mlxsw_sp->port_to_module[base_port + i * 2];
1946 mlxsw_sp_port_create(mlxsw_sp, base_port + i * 2, false,
1947 module, MLXSW_PORT_MODULE_MAX_WIDTH, 0);
1948 }
1949 return err;
1950}
1951
1952static int mlxsw_sp_port_unsplit(void *priv, u8 local_port)
1953{
1954 struct mlxsw_sp *mlxsw_sp = priv;
1955 struct mlxsw_sp_port *mlxsw_sp_port;
1956 u8 module, cur_width, base_port;
1957 unsigned int count;
1958 int i;
1959 int err;
1960
1961 mlxsw_sp_port = mlxsw_sp->ports[local_port];
1962 if (!mlxsw_sp_port) {
1963 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
1964 local_port);
1965 return -EINVAL;
1966 }
1967
1968 if (!mlxsw_sp_port->split) {
1969 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
1970 return -EINVAL;
1971 }
1972
1973 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
1974 &cur_width);
1975 if (err) {
1976 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
1977 return err;
1978 }
1979 count = cur_width == 1 ? 4 : 2;
1980
1981 base_port = mlxsw_sp_cluster_base_port_get(local_port);
1982
1983 /* Determine which ports to remove. */
1984 if (count == 2 && local_port >= base_port + 2)
1985 base_port = base_port + 2;
1986
1987 for (i = 0; i < count; i++)
1988 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1989
1990 for (i = 0; i < count / 2; i++) {
1991 module = mlxsw_sp->port_to_module[base_port + i * 2];
1992 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * 2, false,
1993 module, MLXSW_PORT_MODULE_MAX_WIDTH,
1994 0);
1995 if (err)
1996 dev_err(mlxsw_sp->bus_info->dev, "Failed to reinstantiate port\n");
1997 }
1998
1999 return 0;
2000}
2001
56ade8fe
JP		 2002static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2003 char *pude_pl, void *priv)
2004{
2005 struct mlxsw_sp *mlxsw_sp = priv;
2006 struct mlxsw_sp_port *mlxsw_sp_port;
2007 enum mlxsw_reg_pude_oper_status status;
2008 u8 local_port;
2009
2010 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2011 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2012 if (!mlxsw_sp_port) {
2013 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2014 local_port);
2015 return;
2016 }
2017
2018 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2019 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2020 netdev_info(mlxsw_sp_port->dev, "link up\n");
2021 netif_carrier_on(mlxsw_sp_port->dev);
2022 } else {
2023 netdev_info(mlxsw_sp_port->dev, "link down\n");
2024 netif_carrier_off(mlxsw_sp_port->dev);
2025 }
2026}
2027
2028static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2029 .func = mlxsw_sp_pude_event_func,
2030 .trap_id = MLXSW_TRAP_ID_PUDE,
2031};
2032
2033static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2034 enum mlxsw_event_trap_id trap_id)
2035{
2036 struct mlxsw_event_listener *el;
2037 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2038 int err;
2039
2040 switch (trap_id) {
2041 case MLXSW_TRAP_ID_PUDE:
2042 el = &mlxsw_sp_pude_event;
2043 break;
2044 }
2045 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2046 if (err)
2047 return err;
2048
2049 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2050 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2051 if (err)
2052 goto err_event_trap_set;
2053
2054 return 0;
2055
2056err_event_trap_set:
2057 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2058 return err;
2059}
2060
2061static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2062 enum mlxsw_event_trap_id trap_id)
2063{
2064 struct mlxsw_event_listener *el;
2065
2066 switch (trap_id) {
2067 case MLXSW_TRAP_ID_PUDE:
2068 el = &mlxsw_sp_pude_event;
2069 break;
2070 }
2071 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2072}
2073
2074static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2075 void *priv)
2076{
2077 struct mlxsw_sp *mlxsw_sp = priv;
2078 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2079 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2080
2081 if (unlikely(!mlxsw_sp_port)) {
2082 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2083 local_port);
2084 return;
2085 }
2086
2087 skb->dev = mlxsw_sp_port->dev;
2088
2089 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2090 u64_stats_update_begin(&pcpu_stats->syncp);
2091 pcpu_stats->rx_packets++;
2092 pcpu_stats->rx_bytes += skb->len;
2093 u64_stats_update_end(&pcpu_stats->syncp);
2094
2095 skb->protocol = eth_type_trans(skb, skb->dev);
2096 netif_receive_skb(skb);
2097}
2098
2099static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2100 {
2101 .func = mlxsw_sp_rx_listener_func,
2102 .local_port = MLXSW_PORT_DONT_CARE,
2103 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2104 },
2105 /* Traps for specific L2 packet types, not trapped as FDB MC */
2106 {
2107 .func = mlxsw_sp_rx_listener_func,
2108 .local_port = MLXSW_PORT_DONT_CARE,
2109 .trap_id = MLXSW_TRAP_ID_STP,
2110 },
2111 {
2112 .func = mlxsw_sp_rx_listener_func,
2113 .local_port = MLXSW_PORT_DONT_CARE,
2114 .trap_id = MLXSW_TRAP_ID_LACP,
2115 },
2116 {
2117 .func = mlxsw_sp_rx_listener_func,
2118 .local_port = MLXSW_PORT_DONT_CARE,
2119 .trap_id = MLXSW_TRAP_ID_EAPOL,
2120 },
2121 {
2122 .func = mlxsw_sp_rx_listener_func,
2123 .local_port = MLXSW_PORT_DONT_CARE,
2124 .trap_id = MLXSW_TRAP_ID_LLDP,
2125 },
2126 {
2127 .func = mlxsw_sp_rx_listener_func,
2128 .local_port = MLXSW_PORT_DONT_CARE,
2129 .trap_id = MLXSW_TRAP_ID_MMRP,
2130 },
2131 {
2132 .func = mlxsw_sp_rx_listener_func,
2133 .local_port = MLXSW_PORT_DONT_CARE,
2134 .trap_id = MLXSW_TRAP_ID_MVRP,
2135 },
2136 {
2137 .func = mlxsw_sp_rx_listener_func,
2138 .local_port = MLXSW_PORT_DONT_CARE,
2139 .trap_id = MLXSW_TRAP_ID_RPVST,
2140 },
2141 {
2142 .func = mlxsw_sp_rx_listener_func,
2143 .local_port = MLXSW_PORT_DONT_CARE,
2144 .trap_id = MLXSW_TRAP_ID_DHCP,
2145 },
2146 {
2147 .func = mlxsw_sp_rx_listener_func,
2148 .local_port = MLXSW_PORT_DONT_CARE,
2149 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2150 },
2151 {
2152 .func = mlxsw_sp_rx_listener_func,
2153 .local_port = MLXSW_PORT_DONT_CARE,
2154 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2155 },
2156 {
2157 .func = mlxsw_sp_rx_listener_func,
2158 .local_port = MLXSW_PORT_DONT_CARE,
2159 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2160 },
2161 {
2162 .func = mlxsw_sp_rx_listener_func,
2163 .local_port = MLXSW_PORT_DONT_CARE,
2164 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2165 },
2166 {
2167 .func = mlxsw_sp_rx_listener_func,
2168 .local_port = MLXSW_PORT_DONT_CARE,
2169 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2170 },
2171};
2172
2173static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2174{
2175 char htgt_pl[MLXSW_REG_HTGT_LEN];
2176 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2177 int i;
2178 int err;
2179
2180 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2181 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2182 if (err)
2183 return err;
2184
2185 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2186 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2187 if (err)
2188 return err;
2189
2190 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2191 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2192 &mlxsw_sp_rx_listener[i],
2193 mlxsw_sp);
2194 if (err)
2195 goto err_rx_listener_register;
2196
2197 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2198 mlxsw_sp_rx_listener[i].trap_id);
2199 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2200 if (err)
2201 goto err_rx_trap_set;
2202 }
2203 return 0;
2204
2205err_rx_trap_set:
2206 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2207 &mlxsw_sp_rx_listener[i],
2208 mlxsw_sp);
2209err_rx_listener_register:
2210 for (i--; i >= 0; i--) {
2211 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2212 mlxsw_sp_rx_listener[i].trap_id);
2213 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2214
2215 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2216 &mlxsw_sp_rx_listener[i],
2217 mlxsw_sp);
2218 }
2219 return err;
2220}
2221
2222static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2223{
2224 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2225 int i;
2226
2227 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2228 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2229 mlxsw_sp_rx_listener[i].trap_id);
2230 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2231
2232 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2233 &mlxsw_sp_rx_listener[i],
2234 mlxsw_sp);
2235 }
2236}
2237
2238static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2239 enum mlxsw_reg_sfgc_type type,
2240 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2241{
2242 enum mlxsw_flood_table_type table_type;
2243 enum mlxsw_sp_flood_table flood_table;
2244 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2245
19ae6124 2246 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
56ade8fe 2247 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
19ae6124 2248 else
56ade8fe 2249 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
19ae6124
IS		 2250
2251 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2252 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2253 else
2254 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
56ade8fe
JP		 2255
2256 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2257 flood_table);
2258 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2259}
2260
2261static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2262{
2263 int type, err;
2264
56ade8fe
JP		 2265 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2266 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2267 continue;
2268
2269 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2270 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2271 if (err)
2272 return err;
56ade8fe
JP		 2273
2274 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2275 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2276 if (err)
2277 return err;
2278 }
2279
2280 return 0;
2281}
2282
0d65fc13
JP		 2283static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2284{
2285 char slcr_pl[MLXSW_REG_SLCR_LEN];
2286
2287 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2288 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2289 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2290 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2291 MLXSW_REG_SLCR_LAG_HASH_SIP |
2292 MLXSW_REG_SLCR_LAG_HASH_DIP |
2293 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2294 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2295 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2296 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2297}
2298
56ade8fe
JP		 2299static int mlxsw_sp_init(void *priv, struct mlxsw_core *mlxsw_core,
2300 const struct mlxsw_bus_info *mlxsw_bus_info)
2301{
2302 struct mlxsw_sp *mlxsw_sp = priv;
2303 int err;
2304
2305 mlxsw_sp->core = mlxsw_core;
2306 mlxsw_sp->bus_info = mlxsw_bus_info;
7f71eb46 2307 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
26f0e7fb 2308 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
3a49b4fd 2309 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
56ade8fe
JP		 2310
2311 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2312 if (err) {
2313 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2314 return err;
2315 }
2316
2317 err = mlxsw_sp_ports_create(mlxsw_sp);
2318 if (err) {
2319 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
7f71eb46 2320 return err;
56ade8fe
JP		 2321 }
2322
2323 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2324 if (err) {
2325 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2326 goto err_event_register;
2327 }
2328
2329 err = mlxsw_sp_traps_init(mlxsw_sp);
2330 if (err) {
2331 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2332 goto err_rx_listener_register;
2333 }
2334
2335 err = mlxsw_sp_flood_init(mlxsw_sp);
2336 if (err) {
2337 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2338 goto err_flood_init;
2339 }
2340
2341 err = mlxsw_sp_buffers_init(mlxsw_sp);
2342 if (err) {
2343 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2344 goto err_buffers_init;
2345 }
2346
0d65fc13
JP		 2347 err = mlxsw_sp_lag_init(mlxsw_sp);
2348 if (err) {
2349 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2350 goto err_lag_init;
2351 }
2352
56ade8fe
JP		 2353 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2354 if (err) {
2355 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2356 goto err_switchdev_init;
2357 }
2358
2359 return 0;
2360
2361err_switchdev_init:
0d65fc13 2362err_lag_init:
56ade8fe
JP		 2363err_buffers_init:
2364err_flood_init:
2365 mlxsw_sp_traps_fini(mlxsw_sp);
2366err_rx_listener_register:
2367 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2368err_event_register:
2369 mlxsw_sp_ports_remove(mlxsw_sp);
56ade8fe
JP		 2370 return err;
2371}
2372
2373static void mlxsw_sp_fini(void *priv)
2374{
2375 struct mlxsw_sp *mlxsw_sp = priv;
2376
2377 mlxsw_sp_switchdev_fini(mlxsw_sp);
2378 mlxsw_sp_traps_fini(mlxsw_sp);
2379 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2380 mlxsw_sp_ports_remove(mlxsw_sp);
56ade8fe
JP		 2381}
2382
2383static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2384 .used_max_vepa_channels = 1,
2385 .max_vepa_channels = 0,
2386 .used_max_lag = 1,
0d65fc13 2387 .max_lag = MLXSW_SP_LAG_MAX,
56ade8fe 2388 .used_max_port_per_lag = 1,
0d65fc13 2389 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
56ade8fe 2390 .used_max_mid = 1,
53ae6283 2391 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 2392 .used_max_pgt = 1,
2393 .max_pgt = 0,
2394 .used_max_system_port = 1,
2395 .max_system_port = 64,
2396 .used_max_vlan_groups = 1,
2397 .max_vlan_groups = 127,
2398 .used_max_regions = 1,
2399 .max_regions = 400,
2400 .used_flood_tables = 1,
2401 .used_flood_mode = 1,
2402 .flood_mode = 3,
2403 .max_fid_offset_flood_tables = 2,
2404 .fid_offset_flood_table_size = VLAN_N_VID - 1,
19ae6124
IS		 2405 .max_fid_flood_tables = 2,
2406 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
56ade8fe
JP		 2407 .used_max_ib_mc = 1,
2408 .max_ib_mc = 0,
2409 .used_max_pkey = 1,
2410 .max_pkey = 0,
2411 .swid_config = {
2412 {
2413 .used_type = 1,
2414 .type = MLXSW_PORT_SWID_TYPE_ETH,
2415 }
2416 },
2417};
2418
2419static struct mlxsw_driver mlxsw_sp_driver = {
2420 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2421 .owner = THIS_MODULE,
2422 .priv_size = sizeof(struct mlxsw_sp),
2423 .init = mlxsw_sp_init,
2424 .fini = mlxsw_sp_fini,
18f1e70c
IS		 2425 .port_split = mlxsw_sp_port_split,
2426 .port_unsplit = mlxsw_sp_port_unsplit,
56ade8fe
JP		 2427 .txhdr_construct = mlxsw_sp_txhdr_construct,
2428 .txhdr_len = MLXSW_TXHDR_LEN,
2429 .profile = &mlxsw_sp_config_profile,
2430};
2431
039c49a6
IS		 2432static int
2433mlxsw_sp_port_fdb_flush_by_port(const struct mlxsw_sp_port *mlxsw_sp_port)
2434{
2435 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2436 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2437
2438 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT);
2439 mlxsw_reg_sfdf_system_port_set(sfdf_pl, mlxsw_sp_port->local_port);
2440
2441 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2442}
2443
2444static int
2445mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2446 u16 fid)
2447{
2448 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2449 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2450
2451 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2452 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2453 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2454 mlxsw_sp_port->local_port);
2455
2456 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2457}
2458
2459static int
2460mlxsw_sp_port_fdb_flush_by_lag_id(const struct mlxsw_sp_port *mlxsw_sp_port)
2461{
2462 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2463 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2464
2465 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG);
2466 mlxsw_reg_sfdf_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2467
2468 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2469}
2470
2471static int
2472mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2473 u16 fid)
2474{
2475 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2476 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2477
2478 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2479 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2480 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2481
2482 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2483}
2484
2485static int
2486__mlxsw_sp_port_fdb_flush(const struct mlxsw_sp_port *mlxsw_sp_port)
2487{
2488 int err, last_err = 0;
2489 u16 vid;
2490
2491 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2492 err = mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, vid);
2493 if (err)
2494 last_err = err;
2495 }
2496
2497 return last_err;
2498}
2499
2500static int
2501__mlxsw_sp_port_fdb_flush_lagged(const struct mlxsw_sp_port *mlxsw_sp_port)
2502{
2503 int err, last_err = 0;
2504 u16 vid;
2505
2506 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2507 err = mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port, vid);
2508 if (err)
2509 last_err = err;
2510 }
2511
2512 return last_err;
2513}
2514
2515static int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port)
2516{
2517 if (!list_empty(&mlxsw_sp_port->vports_list))
2518 if (mlxsw_sp_port->lagged)
2519 return __mlxsw_sp_port_fdb_flush_lagged(mlxsw_sp_port);
2520 else
2521 return __mlxsw_sp_port_fdb_flush(mlxsw_sp_port);
2522 else
2523 if (mlxsw_sp_port->lagged)
2524 return mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port);
2525 else
2526 return mlxsw_sp_port_fdb_flush_by_port(mlxsw_sp_port);
2527}
2528
2529static int mlxsw_sp_vport_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_vport)
2530{
2531 u16 vfid = mlxsw_sp_vport_vfid_get(mlxsw_sp_vport);
2532 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
2533
2534 if (mlxsw_sp_vport->lagged)
2535 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_vport,
2536 fid);
2537 else
2538 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_vport, fid);
2539}
2540
56ade8fe
JP		 2541static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2542{
2543 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2544}
2545
2546static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port)
2547{
2548 struct net_device *dev = mlxsw_sp_port->dev;
2549 int err;
2550
2551 /* When port is not bridged untagged packets are tagged with
2552 * PVID=VID=1, thereby creating an implicit VLAN interface in
2553 * the device. Remove it and let bridge code take care of its
2554 * own VLANs.
2555 */
2556 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
6c72a3d0
IS		 2557 if (err)
2558 return err;
56ade8fe 2559
6c72a3d0
IS		 2560 mlxsw_sp_port->learning = 1;
2561 mlxsw_sp_port->learning_sync = 1;
2562 mlxsw_sp_port->uc_flood = 1;
2563 mlxsw_sp_port->bridged = 1;
2564
2565 return 0;
56ade8fe
JP		 2566}
2567
039c49a6
IS		 2568static int mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2569 bool flush_fdb)
56ade8fe
JP		 2570{
2571 struct net_device *dev = mlxsw_sp_port->dev;
5a8f4525 2572
039c49a6
IS		 2573 if (flush_fdb && mlxsw_sp_port_fdb_flush(mlxsw_sp_port))
2574 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
2575
28a01d2d
IS		 2576 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2577
6c72a3d0
IS		 2578 mlxsw_sp_port->learning = 0;
2579 mlxsw_sp_port->learning_sync = 0;
2580 mlxsw_sp_port->uc_flood = 0;
5a8f4525 2581 mlxsw_sp_port->bridged = 0;
56ade8fe
JP		 2582
2583 /* Add implicit VLAN interface in the device, so that untagged
2584 * packets will be classified to the default vFID.
2585 */
5a8f4525 2586 return mlxsw_sp_port_add_vid(dev, 0, 1);
56ade8fe
JP		 2587}
2588
2589static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2590 struct net_device *br_dev)
2591{
2592 return !mlxsw_sp->master_bridge.dev ||
2593 mlxsw_sp->master_bridge.dev == br_dev;
2594}
2595
2596static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2597 struct net_device *br_dev)
2598{
2599 mlxsw_sp->master_bridge.dev = br_dev;
2600 mlxsw_sp->master_bridge.ref_count++;
2601}
2602
2603static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp,
2604 struct net_device *br_dev)
2605{
2606 if (--mlxsw_sp->master_bridge.ref_count == 0)
2607 mlxsw_sp->master_bridge.dev = NULL;
2608}
2609
0d65fc13
JP		 2610static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2611{
2612 char sldr_pl[MLXSW_REG_SLDR_LEN];
2613
2614 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2615 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2616}
2617
2618static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2619{
2620 char sldr_pl[MLXSW_REG_SLDR_LEN];
2621
2622 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2623 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2624}
2625
2626static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2627 u16 lag_id, u8 port_index)
2628{
2629 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2630 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2631
2632 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2633 lag_id, port_index);
2634 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2635}
2636
2637static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2638 u16 lag_id)
2639{
2640 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2641 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2642
2643 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2644 lag_id);
2645 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2646}
2647
2648static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2649 u16 lag_id)
2650{
2651 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2652 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2653
2654 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2655 lag_id);
2656 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2657}
2658
2659static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2660 u16 lag_id)
2661{
2662 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2663 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2664
2665 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2666 lag_id);
2667 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2668}
2669
2670static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2671 struct net_device *lag_dev,
2672 u16 *p_lag_id)
2673{
2674 struct mlxsw_sp_upper *lag;
2675 int free_lag_id = -1;
2676 int i;
2677
2678 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2679 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2680 if (lag->ref_count) {
2681 if (lag->dev == lag_dev) {
2682 *p_lag_id = i;
2683 return 0;
2684 }
2685 } else if (free_lag_id < 0) {
2686 free_lag_id = i;
2687 }
2688 }
2689 if (free_lag_id < 0)
2690 return -EBUSY;
2691 *p_lag_id = free_lag_id;
2692 return 0;
2693}
2694
2695static bool
2696mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2697 struct net_device *lag_dev,
2698 struct netdev_lag_upper_info *lag_upper_info)
2699{
2700 u16 lag_id;
2701
2702 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2703 return false;
2704 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2705 return false;
2706 return true;
2707}
2708
2709static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2710 u16 lag_id, u8 *p_port_index)
2711{
2712 int i;
2713
2714 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2715 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2716 *p_port_index = i;
2717 return 0;
2718 }
2719 }
2720 return -EBUSY;
2721}
2722
2723static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2724 struct net_device *lag_dev)
2725{
2726 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2727 struct mlxsw_sp_upper *lag;
2728 u16 lag_id;
2729 u8 port_index;
2730 int err;
2731
2732 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2733 if (err)
2734 return err;
2735 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2736 if (!lag->ref_count) {
2737 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2738 if (err)
2739 return err;
2740 lag->dev = lag_dev;
2741 }
2742
2743 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2744 if (err)
2745 return err;
2746 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2747 if (err)
2748 goto err_col_port_add;
2749 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2750 if (err)
2751 goto err_col_port_enable;
2752
2753 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2754 mlxsw_sp_port->local_port);
2755 mlxsw_sp_port->lag_id = lag_id;
2756 mlxsw_sp_port->lagged = 1;
2757 lag->ref_count++;
2758 return 0;
2759
2760err_col_port_add:
2761 if (!lag->ref_count)
2762 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2763err_col_port_enable:
2764 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
2765 return err;
2766}
2767
4dc236c3 2768static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
039c49a6
IS		 2769 struct net_device *br_dev,
2770 bool flush_fdb);
4dc236c3 2771
0d65fc13
JP		 2772static int mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2773 struct net_device *lag_dev)
2774{
2775 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4dc236c3 2776 struct mlxsw_sp_port *mlxsw_sp_vport;
0d65fc13
JP		 2777 struct mlxsw_sp_upper *lag;
2778 u16 lag_id = mlxsw_sp_port->lag_id;
2779 int err;
2780
2781 if (!mlxsw_sp_port->lagged)
2782 return 0;
2783 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2784 WARN_ON(lag->ref_count == 0);
2785
2786 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2787 if (err)
2788 return err;
82a06429 2789 err = mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 2790 if (err)
2791 return err;
2792
4dc236c3
IS		 2793 /* In case we leave a LAG device that has bridges built on top,
2794 * then their teardown sequence is never issued and we need to
2795 * invoke the necessary cleanup routines ourselves.
2796 */
2797 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
2798 vport.list) {
2799 struct net_device *br_dev;
2800
2801 if (!mlxsw_sp_vport->bridged)
2802 continue;
2803
2804 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
039c49a6 2805 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, false);
4dc236c3
IS		 2806 }
2807
2808 if (mlxsw_sp_port->bridged) {
2809 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
039c49a6 2810 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, false);
912b1c89 2811 mlxsw_sp_master_bridge_dec(mlxsw_sp, NULL);
4dc236c3
IS		 2812 }
2813
0d65fc13 2814 if (lag->ref_count == 1) {
039c49a6
IS		 2815 if (mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port))
2816 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
0d65fc13
JP		 2817 err = mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2818 if (err)
2819 return err;
2820 }
2821
2822 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2823 mlxsw_sp_port->local_port);
2824 mlxsw_sp_port->lagged = 0;
2825 lag->ref_count--;
2826 return 0;
2827}
2828
74581206
JP		 2829static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2830 u16 lag_id)
2831{
2832 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2833 char sldr_pl[MLXSW_REG_SLDR_LEN];
2834
2835 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2836 mlxsw_sp_port->local_port);
2837 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2838}
2839
2840static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2841 u16 lag_id)
2842{
2843 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2844 char sldr_pl[MLXSW_REG_SLDR_LEN];
2845
2846 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2847 mlxsw_sp_port->local_port);
2848 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2849}
2850
2851static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2852 bool lag_tx_enabled)
2853{
2854 if (lag_tx_enabled)
2855 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2856 mlxsw_sp_port->lag_id);
2857 else
2858 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2859 mlxsw_sp_port->lag_id);
2860}
2861
2862static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2863 struct netdev_lag_lower_state_info *info)
2864{
2865 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2866}
2867
9589a7b5
IS		 2868static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2869 struct net_device *vlan_dev)
2870{
2871 struct mlxsw_sp_port *mlxsw_sp_vport;
2872 u16 vid = vlan_dev_vlan_id(vlan_dev);
2873
2874 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2875 if (!mlxsw_sp_vport) {
2876 WARN_ON(!mlxsw_sp_vport);
2877 return -EINVAL;
2878 }
2879
2880 mlxsw_sp_vport->dev = vlan_dev;
2881
2882 return 0;
2883}
2884
2885static int mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2886 struct net_device *vlan_dev)
2887{
2888 struct mlxsw_sp_port *mlxsw_sp_vport;
2889 u16 vid = vlan_dev_vlan_id(vlan_dev);
2890
2891 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2892 if (!mlxsw_sp_vport) {
2893 WARN_ON(!mlxsw_sp_vport);
2894 return -EINVAL;
2895 }
2896
26f0e7fb
IS		 2897 /* When removing a VLAN device while still bridged we should first
2898 * remove it from the bridge, as we receive the bridge's notification
2899 * when the vPort is already gone.
2900 */
2901 if (mlxsw_sp_vport->bridged) {
2902 struct net_device *br_dev;
2903
2904 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
039c49a6 2905 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, true);
26f0e7fb
IS		 2906 }
2907
9589a7b5
IS		 2908 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
2909
2910 return 0;
2911}
2912
74581206
JP		 2913static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
2914 unsigned long event, void *ptr)
56ade8fe 2915{
56ade8fe
JP		 2916 struct netdev_notifier_changeupper_info *info;
2917 struct mlxsw_sp_port *mlxsw_sp_port;
2918 struct net_device *upper_dev;
2919 struct mlxsw_sp *mlxsw_sp;
2920 int err;
2921
56ade8fe
JP		 2922 mlxsw_sp_port = netdev_priv(dev);
2923 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2924 info = ptr;
2925
2926 switch (event) {
2927 case NETDEV_PRECHANGEUPPER:
2928 upper_dev = info->upper_dev;
0d65fc13
JP		 2929 if (!info->master || !info->linking)
2930 break;
56ade8fe 2931 /* HW limitation forbids to put ports to multiple bridges. */
0d65fc13 2932 if (netif_is_bridge_master(upper_dev) &&
56ade8fe
JP		 2933 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
2934 return NOTIFY_BAD;
0d65fc13
JP		 2935 if (netif_is_lag_master(upper_dev) &&
2936 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
2937 info->upper_info))
2938 return NOTIFY_BAD;
56ade8fe
JP		 2939 break;
2940 case NETDEV_CHANGEUPPER:
2941 upper_dev = info->upper_dev;
9589a7b5
IS		 2942 if (is_vlan_dev(upper_dev)) {
2943 if (info->linking) {
2944 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
2945 upper_dev);
2946 if (err) {
2947 netdev_err(dev, "Failed to link VLAN device\n");
2948 return NOTIFY_BAD;
2949 }
2950 } else {
2951 err = mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
2952 upper_dev);
2953 if (err) {
2954 netdev_err(dev, "Failed to unlink VLAN device\n");
2955 return NOTIFY_BAD;
2956 }
2957 }
2958 } else if (netif_is_bridge_master(upper_dev)) {
56ade8fe
JP		 2959 if (info->linking) {
2960 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port);
78124078 2961 if (err) {
56ade8fe 2962 netdev_err(dev, "Failed to join bridge\n");
78124078
IS		 2963 return NOTIFY_BAD;
2964 }
56ade8fe 2965 mlxsw_sp_master_bridge_inc(mlxsw_sp, upper_dev);
56ade8fe 2966 } else {
039c49a6
IS		 2967 err = mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
2968 true);
56ade8fe 2969 mlxsw_sp_master_bridge_dec(mlxsw_sp, upper_dev);
78124078
IS		 2970 if (err) {
2971 netdev_err(dev, "Failed to leave bridge\n");
2972 return NOTIFY_BAD;
2973 }
56ade8fe 2974 }
0d65fc13
JP		 2975 } else if (netif_is_lag_master(upper_dev)) {
2976 if (info->linking) {
2977 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
2978 upper_dev);
2979 if (err) {
2980 netdev_err(dev, "Failed to join link aggregation\n");
2981 return NOTIFY_BAD;
2982 }
2983 } else {
2984 err = mlxsw_sp_port_lag_leave(mlxsw_sp_port,
2985 upper_dev);
2986 if (err) {
2987 netdev_err(dev, "Failed to leave link aggregation\n");
2988 return NOTIFY_BAD;
2989 }
2990 }
56ade8fe
JP		 2991 }
2992 break;
2993 }
2994
2995 return NOTIFY_DONE;
2996}
2997
74581206
JP		 2998static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
2999 unsigned long event, void *ptr)
3000{
3001 struct netdev_notifier_changelowerstate_info *info;
3002 struct mlxsw_sp_port *mlxsw_sp_port;
3003 int err;
3004
3005 mlxsw_sp_port = netdev_priv(dev);
3006 info = ptr;
3007
3008 switch (event) {
3009 case NETDEV_CHANGELOWERSTATE:
3010 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3011 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3012 info->lower_state_info);
3013 if (err)
3014 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3015 }
3016 break;
3017 }
3018
3019 return NOTIFY_DONE;
3020}
3021
3022static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3023 unsigned long event, void *ptr)
3024{
3025 switch (event) {
3026 case NETDEV_PRECHANGEUPPER:
3027 case NETDEV_CHANGEUPPER:
3028 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3029 case NETDEV_CHANGELOWERSTATE:
3030 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3031 }
3032
3033 return NOTIFY_DONE;
3034}
3035
0d65fc13
JP		 3036static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3037 unsigned long event, void *ptr)
3038{
3039 struct net_device *dev;
3040 struct list_head *iter;
3041 int ret;
3042
3043 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3044 if (mlxsw_sp_port_dev_check(dev)) {
3045 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3046 if (ret == NOTIFY_BAD)
3047 return ret;
3048 }
3049 }
3050
3051 return NOTIFY_DONE;
3052}
3053
26f0e7fb
IS		 3054static struct mlxsw_sp_vfid *
3055mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3056 const struct net_device *br_dev)
3057{
3058 struct mlxsw_sp_vfid *vfid;
3059
3060 list_for_each_entry(vfid, &mlxsw_sp->br_vfids.list, list) {
3061 if (vfid->br_dev == br_dev)
3062 return vfid;
3063 }
3064
3065 return NULL;
3066}
3067
3068static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3069{
3070 return vfid - MLXSW_SP_VFID_PORT_MAX;
3071}
3072
3073static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3074{
3075 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3076}
3077
3078static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3079{
3080 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3081 MLXSW_SP_VFID_BR_MAX);
3082}
3083
3084static struct mlxsw_sp_vfid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3085 struct net_device *br_dev)
3086{
3087 struct device *dev = mlxsw_sp->bus_info->dev;
3088 struct mlxsw_sp_vfid *vfid;
3089 u16 n_vfid;
3090 int err;
3091
3092 n_vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3093 if (n_vfid == MLXSW_SP_VFID_MAX) {
3094 dev_err(dev, "No available vFIDs\n");
3095 return ERR_PTR(-ERANGE);
3096 }
3097
3098 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
3099 if (err) {
3100 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
3101 return ERR_PTR(err);
3102 }
3103
3104 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
3105 if (!vfid)
3106 goto err_allocate_vfid;
3107
3108 vfid->vfid = n_vfid;
3109 vfid->br_dev = br_dev;
3110
3111 list_add(&vfid->list, &mlxsw_sp->br_vfids.list);
3112 set_bit(mlxsw_sp_vfid_to_br_vfid(n_vfid), mlxsw_sp->br_vfids.mapped);
3113
3114 return vfid;
3115
3116err_allocate_vfid:
3117 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
3118 return ERR_PTR(-ENOMEM);
3119}
3120
3121static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3122 struct mlxsw_sp_vfid *vfid)
3123{
3124 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid->vfid);
3125
3126 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
3127 list_del(&vfid->list);
3128
3129 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
3130
3131 kfree(vfid);
3132}
3133
3134static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
039c49a6
IS		 3135 struct net_device *br_dev,
3136 bool flush_fdb)
26f0e7fb
IS		 3137{
3138 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3139 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3140 struct net_device *dev = mlxsw_sp_vport->dev;
3141 struct mlxsw_sp_vfid *vfid, *new_vfid;
3142 int err;
3143
3144 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3145 if (!vfid) {
3146 WARN_ON(!vfid);
3147 return -EINVAL;
3148 }
3149
3150 /* We need a vFID to go back to after leaving the bridge's vFID. */
3151 new_vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
3152 if (!new_vfid) {
3153 new_vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
3154 if (IS_ERR(new_vfid)) {
3155 netdev_err(dev, "Failed to create vFID for VID=%d\n",
3156 vid);
3157 return PTR_ERR(new_vfid);
3158 }
3159 }
3160
3161 /* Invalidate existing {Port, VID} to vFID mapping and create a new
3162 * one for the new vFID.
3163 */
3164 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3165 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3166 false,
3167 mlxsw_sp_vfid_to_fid(vfid->vfid),
3168 vid);
3169 if (err) {
3170 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3171 vfid->vfid);
3172 goto err_port_vid_to_fid_invalidate;
3173 }
3174
3175 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3176 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3177 true,
3178 mlxsw_sp_vfid_to_fid(new_vfid->vfid),
3179 vid);
3180 if (err) {
3181 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3182 new_vfid->vfid);
3183 goto err_port_vid_to_fid_validate;
3184 }
3185
3186 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3187 if (err) {
3188 netdev_err(dev, "Failed to disable learning\n");
3189 goto err_port_vid_learning_set;
3190 }
3191
3192 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
3193 false);
3194 if (err) {
3195 netdev_err(dev, "Failed clear to clear flooding\n");
3196 goto err_vport_flood_set;
3197 }
3198
6a9863a6
IS		 3199 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3200 MLXSW_REG_SPMS_STATE_FORWARDING);
3201 if (err) {
3202 netdev_err(dev, "Failed to set STP state\n");
3203 goto err_port_stp_state_set;
3204 }
3205
039c49a6
IS		 3206 if (flush_fdb && mlxsw_sp_vport_fdb_flush(mlxsw_sp_vport))
3207 netdev_err(dev, "Failed to flush FDB\n");
3208
26f0e7fb
IS		 3209 /* Switch between the vFIDs and destroy the old one if needed. */
3210 new_vfid->nr_vports++;
3211 mlxsw_sp_vport->vport.vfid = new_vfid;
3212 vfid->nr_vports--;
3213 if (!vfid->nr_vports)
3214 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3215
3216 mlxsw_sp_vport->learning = 0;
3217 mlxsw_sp_vport->learning_sync = 0;
3218 mlxsw_sp_vport->uc_flood = 0;
3219 mlxsw_sp_vport->bridged = 0;
3220
3221 return 0;
3222
6a9863a6 3223err_port_stp_state_set:
26f0e7fb
IS		 3224err_vport_flood_set:
3225err_port_vid_learning_set:
3226err_port_vid_to_fid_validate:
3227err_port_vid_to_fid_invalidate:
3228 /* Rollback vFID only if new. */
3229 if (!new_vfid->nr_vports)
3230 mlxsw_sp_vfid_destroy(mlxsw_sp, new_vfid);
3231 return err;
3232}
3233
3234static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3235 struct net_device *br_dev)
3236{
3237 struct mlxsw_sp_vfid *old_vfid = mlxsw_sp_vport->vport.vfid;
3238 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3239 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3240 struct net_device *dev = mlxsw_sp_vport->dev;
3241 struct mlxsw_sp_vfid *vfid;
3242 int err;
3243
3244 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3245 if (!vfid) {
3246 vfid = mlxsw_sp_br_vfid_create(mlxsw_sp, br_dev);
3247 if (IS_ERR(vfid)) {
3248 netdev_err(dev, "Failed to create bridge vFID\n");
3249 return PTR_ERR(vfid);
3250 }
3251 }
3252
3253 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, true, false);
3254 if (err) {
3255 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
3256 vfid->vfid);
3257 goto err_port_flood_set;
3258 }
3259
3260 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3261 if (err) {
3262 netdev_err(dev, "Failed to enable learning\n");
3263 goto err_port_vid_learning_set;
3264 }
3265
3266 /* We need to invalidate existing {Port, VID} to vFID mapping and
3267 * create a new one for the bridge's vFID.
3268 */
3269 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3270 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3271 false,
3272 mlxsw_sp_vfid_to_fid(old_vfid->vfid),
3273 vid);
3274 if (err) {
3275 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3276 old_vfid->vfid);
3277 goto err_port_vid_to_fid_invalidate;
3278 }
3279
3280 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3281 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3282 true,
3283 mlxsw_sp_vfid_to_fid(vfid->vfid),
3284 vid);
3285 if (err) {
3286 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3287 vfid->vfid);
3288 goto err_port_vid_to_fid_validate;
3289 }
3290
3291 /* Switch between the vFIDs and destroy the old one if needed. */
3292 vfid->nr_vports++;
3293 mlxsw_sp_vport->vport.vfid = vfid;
3294 old_vfid->nr_vports--;
3295 if (!old_vfid->nr_vports)
3296 mlxsw_sp_vfid_destroy(mlxsw_sp, old_vfid);
3297
3298 mlxsw_sp_vport->learning = 1;
3299 mlxsw_sp_vport->learning_sync = 1;
3300 mlxsw_sp_vport->uc_flood = 1;
3301 mlxsw_sp_vport->bridged = 1;
3302
3303 return 0;
3304
3305err_port_vid_to_fid_validate:
3306 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3307 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
3308 mlxsw_sp_vfid_to_fid(old_vfid->vfid), vid);
3309err_port_vid_to_fid_invalidate:
3310 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3311err_port_vid_learning_set:
3312 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false, false);
3313err_port_flood_set:
3314 if (!vfid->nr_vports)
3315 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3316 return err;
3317}
3318
3319static bool
3320mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3321 const struct net_device *br_dev)
3322{
3323 struct mlxsw_sp_port *mlxsw_sp_vport;
3324
3325 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3326 vport.list) {
3327 if (mlxsw_sp_vport_br_get(mlxsw_sp_vport) == br_dev)
3328 return false;
3329 }
3330
3331 return true;
3332}
3333
3334static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3335 unsigned long event, void *ptr,
3336 u16 vid)
3337{
3338 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3339 struct netdev_notifier_changeupper_info *info = ptr;
3340 struct mlxsw_sp_port *mlxsw_sp_vport;
3341 struct net_device *upper_dev;
3342 int err;
3343
3344 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3345
3346 switch (event) {
3347 case NETDEV_PRECHANGEUPPER:
3348 upper_dev = info->upper_dev;
3349 if (!info->master || !info->linking)
3350 break;
3351 if (!netif_is_bridge_master(upper_dev))
3352 return NOTIFY_BAD;
3353 /* We can't have multiple VLAN interfaces configured on
3354 * the same port and being members in the same bridge.
3355 */
3356 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3357 upper_dev))
3358 return NOTIFY_BAD;
3359 break;
3360 case NETDEV_CHANGEUPPER:
3361 upper_dev = info->upper_dev;
3362 if (!info->master)
3363 break;
3364 if (info->linking) {
3365 if (!mlxsw_sp_vport) {
3366 WARN_ON(!mlxsw_sp_vport);
3367 return NOTIFY_BAD;
3368 }
3369 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3370 upper_dev);
3371 if (err) {
3372 netdev_err(dev, "Failed to join bridge\n");
3373 return NOTIFY_BAD;
3374 }
3375 } else {
3376 /* We ignore bridge's unlinking notifications if vPort
3377 * is gone, since we already left the bridge when the
3378 * VLAN device was unlinked from the real device.
3379 */
3380 if (!mlxsw_sp_vport)
3381 return NOTIFY_DONE;
3382 err = mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport,
039c49a6 3383 upper_dev, true);
26f0e7fb
IS		 3384 if (err) {
3385 netdev_err(dev, "Failed to leave bridge\n");
3386 return NOTIFY_BAD;
3387 }
3388 }
3389 }
3390
3391 return NOTIFY_DONE;
3392}
3393
272c4470
IS		 3394static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3395 unsigned long event, void *ptr,
3396 u16 vid)
3397{
3398 struct net_device *dev;
3399 struct list_head *iter;
3400 int ret;
3401
3402 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3403 if (mlxsw_sp_port_dev_check(dev)) {
3404 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3405 vid);
3406 if (ret == NOTIFY_BAD)
3407 return ret;
3408 }
3409 }
3410
3411 return NOTIFY_DONE;
3412}
3413
26f0e7fb
IS		 3414static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3415 unsigned long event, void *ptr)
3416{
3417 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3418 u16 vid = vlan_dev_vlan_id(vlan_dev);
3419
272c4470
IS		 3420 if (mlxsw_sp_port_dev_check(real_dev))
3421 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3422 vid);
3423 else if (netif_is_lag_master(real_dev))
3424 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3425 vid);
26f0e7fb 3426
272c4470 3427 return NOTIFY_DONE;
26f0e7fb
IS		 3428}
3429
0d65fc13
JP		 3430static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3431 unsigned long event, void *ptr)
3432{
3433 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3434
3435 if (mlxsw_sp_port_dev_check(dev))
3436 return mlxsw_sp_netdevice_port_event(dev, event, ptr);
3437
3438 if (netif_is_lag_master(dev))
3439 return mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3440
26f0e7fb
IS		 3441 if (is_vlan_dev(dev))
3442 return mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
3443
0d65fc13
JP		 3444 return NOTIFY_DONE;
3445}
3446
56ade8fe
JP		 3447static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3448 .notifier_call = mlxsw_sp_netdevice_event,
3449};
3450
3451static int __init mlxsw_sp_module_init(void)
3452{
3453 int err;
3454
3455 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3456 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3457 if (err)
3458 goto err_core_driver_register;
3459 return 0;
3460
3461err_core_driver_register:
3462 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3463 return err;
3464}
3465
3466static void __exit mlxsw_sp_module_exit(void)
3467{
3468 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3469 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3470}
3471
3472module_init(mlxsw_sp_module_init);
3473module_exit(mlxsw_sp_module_exit);
3474
3475MODULE_LICENSE("Dual BSD/GPL");
3476MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3477MODULE_DESCRIPTION("Mellanox Spectrum driver");
3478MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);
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