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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
CommitLineData
56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
56ade8fe
JP		 56#include <net/switchdev.h>
57#include <generated/utsrelease.h>
763b4b70
YG		 58#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
e7322638 60#include <net/netevent.h>
56ade8fe
JP		 61
62#include "spectrum.h"
1d20d23c 63#include "pci.h"
56ade8fe
JP		 64#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
69
70static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
71static const char mlxsw_sp_driver_version[] = "1.0";
72
73/* tx_hdr_version
74 * Tx header version.
75 * Must be set to 1.
76 */
77MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
78
79/* tx_hdr_ctl
80 * Packet control type.
81 * 0 - Ethernet control (e.g. EMADs, LACP)
82 * 1 - Ethernet data
83 */
84MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
85
86/* tx_hdr_proto
87 * Packet protocol type. Must be set to 1 (Ethernet).
88 */
89MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
90
91/* tx_hdr_rx_is_router
92 * Packet is sent from the router. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
95
96/* tx_hdr_fid_valid
97 * Indicates if the 'fid' field is valid and should be used for
98 * forwarding lookup. Valid for data packets only.
99 */
100MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
101
102/* tx_hdr_swid
103 * Switch partition ID. Must be set to 0.
104 */
105MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
106
107/* tx_hdr_control_tclass
108 * Indicates if the packet should use the control TClass and not one
109 * of the data TClasses.
110 */
111MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
112
113/* tx_hdr_etclass
114 * Egress TClass to be used on the egress device on the egress port.
115 */
116MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
117
118/* tx_hdr_port_mid
119 * Destination local port for unicast packets.
120 * Destination multicast ID for multicast packets.
121 *
122 * Control packets are directed to a specific egress port, while data
123 * packets are transmitted through the CPU port (0) into the switch partition,
124 * where forwarding rules are applied.
125 */
126MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
127
128/* tx_hdr_fid
129 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
130 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
131 * Valid for data packets only.
132 */
133MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
134
135/* tx_hdr_type
136 * 0 - Data packets
137 * 6 - Control packets
138 */
139MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
140
763b4b70
YG		 141static bool mlxsw_sp_port_dev_check(const struct net_device *dev);
142
56ade8fe
JP		 143static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
144 const struct mlxsw_tx_info *tx_info)
145{
146 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
147
148 memset(txhdr, 0, MLXSW_TXHDR_LEN);
149
150 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
151 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
152 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
153 mlxsw_tx_hdr_swid_set(txhdr, 0);
154 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
155 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
156 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
157}
158
159static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
160{
161 char spad_pl[MLXSW_REG_SPAD_LEN];
162 int err;
163
164 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
165 if (err)
166 return err;
167 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
168 return 0;
169}
170
763b4b70
YG		 171static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
172{
763b4b70
YG		 173 int i;
174
c1a38311 175 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 176 return -EIO;
177
c1a38311
JP		 178 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
179 MAX_SPAN);
763b4b70
YG		 180 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
181 sizeof(struct mlxsw_sp_span_entry),
182 GFP_KERNEL);
183 if (!mlxsw_sp->span.entries)
184 return -ENOMEM;
185
186 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
187 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
188
189 return 0;
190}
191
192static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
193{
194 int i;
195
196 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
197 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
198
199 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
200 }
201 kfree(mlxsw_sp->span.entries);
202}
203
204static struct mlxsw_sp_span_entry *
205mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
206{
207 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
208 struct mlxsw_sp_span_entry *span_entry;
209 char mpat_pl[MLXSW_REG_MPAT_LEN];
210 u8 local_port = port->local_port;
211 int index;
212 int i;
213 int err;
214
215 /* find a free entry to use */
216 index = -1;
217 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
218 if (!mlxsw_sp->span.entries[i].used) {
219 index = i;
220 span_entry = &mlxsw_sp->span.entries[i];
221 break;
222 }
223 }
224 if (index < 0)
225 return NULL;
226
227 /* create a new port analayzer entry for local_port */
228 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
229 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
230 if (err)
231 return NULL;
232
233 span_entry->used = true;
234 span_entry->id = index;
235 span_entry->ref_count = 0;
236 span_entry->local_port = local_port;
237 return span_entry;
238}
239
240static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
241 struct mlxsw_sp_span_entry *span_entry)
242{
243 u8 local_port = span_entry->local_port;
244 char mpat_pl[MLXSW_REG_MPAT_LEN];
245 int pa_id = span_entry->id;
246
247 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
248 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
249 span_entry->used = false;
250}
251
1a9234e6
IS		 252static struct mlxsw_sp_span_entry *
253mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
763b4b70
YG		 254{
255 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
256 int i;
257
258 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
259 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
260
261 if (curr->used && curr->local_port == port->local_port)
262 return curr;
263 }
264 return NULL;
265}
266
1a9234e6
IS		 267static struct mlxsw_sp_span_entry
268*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 269{
270 struct mlxsw_sp_span_entry *span_entry;
271
272 span_entry = mlxsw_sp_span_entry_find(port);
273 if (span_entry) {
274 span_entry->ref_count++;
275 return span_entry;
276 }
277
278 return mlxsw_sp_span_entry_create(port);
279}
280
281static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
282 struct mlxsw_sp_span_entry *span_entry)
283{
284 if (--span_entry->ref_count == 0)
285 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
286 return 0;
287}
288
289static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
290{
291 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
292 struct mlxsw_sp_span_inspected_port *p;
293 int i;
294
295 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
296 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
297
298 list_for_each_entry(p, &curr->bound_ports_list, list)
299 if (p->local_port == port->local_port &&
300 p->type == MLXSW_SP_SPAN_EGRESS)
301 return true;
302 }
303
304 return false;
305}
306
307static int mlxsw_sp_span_mtu_to_buffsize(int mtu)
308{
309 return MLXSW_SP_BYTES_TO_CELLS(mtu * 5 / 2) + 1;
310}
311
312static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
313{
314 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
315 char sbib_pl[MLXSW_REG_SBIB_LEN];
316 int err;
317
318 /* If port is egress mirrored, the shared buffer size should be
319 * updated according to the mtu value
320 */
321 if (mlxsw_sp_span_is_egress_mirror(port)) {
322 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
323 mlxsw_sp_span_mtu_to_buffsize(mtu));
324 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
325 if (err) {
326 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
327 return err;
328 }
329 }
330
331 return 0;
332}
333
334static struct mlxsw_sp_span_inspected_port *
335mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
336 struct mlxsw_sp_span_entry *span_entry)
337{
338 struct mlxsw_sp_span_inspected_port *p;
339
340 list_for_each_entry(p, &span_entry->bound_ports_list, list)
341 if (port->local_port == p->local_port)
342 return p;
343 return NULL;
344}
345
346static int
347mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
348 struct mlxsw_sp_span_entry *span_entry,
349 enum mlxsw_sp_span_type type)
350{
351 struct mlxsw_sp_span_inspected_port *inspected_port;
352 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
353 char mpar_pl[MLXSW_REG_MPAR_LEN];
354 char sbib_pl[MLXSW_REG_SBIB_LEN];
355 int pa_id = span_entry->id;
356 int err;
357
358 /* if it is an egress SPAN, bind a shared buffer to it */
359 if (type == MLXSW_SP_SPAN_EGRESS) {
360 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
361 mlxsw_sp_span_mtu_to_buffsize(port->dev->mtu));
362 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
363 if (err) {
364 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
365 return err;
366 }
367 }
368
369 /* bind the port to the SPAN entry */
1a9234e6
IS		 370 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
371 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
763b4b70
YG		 372 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
373 if (err)
374 goto err_mpar_reg_write;
375
376 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
377 if (!inspected_port) {
378 err = -ENOMEM;
379 goto err_inspected_port_alloc;
380 }
381 inspected_port->local_port = port->local_port;
382 inspected_port->type = type;
383 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
384
385 return 0;
386
387err_mpar_reg_write:
388err_inspected_port_alloc:
389 if (type == MLXSW_SP_SPAN_EGRESS) {
390 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
391 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
392 }
393 return err;
394}
395
396static void
397mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
398 struct mlxsw_sp_span_entry *span_entry,
399 enum mlxsw_sp_span_type type)
400{
401 struct mlxsw_sp_span_inspected_port *inspected_port;
402 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
403 char mpar_pl[MLXSW_REG_MPAR_LEN];
404 char sbib_pl[MLXSW_REG_SBIB_LEN];
405 int pa_id = span_entry->id;
406
407 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
408 if (!inspected_port)
409 return;
410
411 /* remove the inspected port */
1a9234e6
IS		 412 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
413 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
763b4b70
YG		 414 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
415
416 /* remove the SBIB buffer if it was egress SPAN */
417 if (type == MLXSW_SP_SPAN_EGRESS) {
418 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
419 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
420 }
421
422 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
423
424 list_del(&inspected_port->list);
425 kfree(inspected_port);
426}
427
428static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
429 struct mlxsw_sp_port *to,
430 enum mlxsw_sp_span_type type)
431{
432 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
433 struct mlxsw_sp_span_entry *span_entry;
434 int err;
435
436 span_entry = mlxsw_sp_span_entry_get(to);
437 if (!span_entry)
438 return -ENOENT;
439
440 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
441 span_entry->id);
442
443 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
444 if (err)
445 goto err_port_bind;
446
447 return 0;
448
449err_port_bind:
450 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
451 return err;
452}
453
454static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
455 struct mlxsw_sp_port *to,
456 enum mlxsw_sp_span_type type)
457{
458 struct mlxsw_sp_span_entry *span_entry;
459
460 span_entry = mlxsw_sp_span_entry_find(to);
461 if (!span_entry) {
462 netdev_err(from->dev, "no span entry found\n");
463 return;
464 }
465
466 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
467 span_entry->id);
468 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
469}
470
56ade8fe
JP		 471static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
472 bool is_up)
473{
474 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
475 char paos_pl[MLXSW_REG_PAOS_LEN];
476
477 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
478 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
479 MLXSW_PORT_ADMIN_STATUS_DOWN);
480 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
481}
482
56ade8fe
JP		 483static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
484 unsigned char *addr)
485{
486 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
487 char ppad_pl[MLXSW_REG_PPAD_LEN];
488
489 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
490 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
491 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
492}
493
494static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
495{
496 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
497 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
498
499 ether_addr_copy(addr, mlxsw_sp->base_mac);
500 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
501 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
502}
503
56ade8fe
JP		 504static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
505{
506 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
507 char pmtu_pl[MLXSW_REG_PMTU_LEN];
508 int max_mtu;
509 int err;
510
511 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
512 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
513 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
514 if (err)
515 return err;
516 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
517
518 if (mtu > max_mtu)
519 return -EINVAL;
520
521 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
522 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
523}
524
be94535f
IS		 525static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
526 u8 swid)
56ade8fe 527{
56ade8fe
JP		 528 char pspa_pl[MLXSW_REG_PSPA_LEN];
529
be94535f 530 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
56ade8fe
JP		 531 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
532}
533
be94535f
IS		 534static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
535{
536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
537
538 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
539 swid);
540}
541
56ade8fe
JP		 542static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
543 bool enable)
544{
545 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
546 char svpe_pl[MLXSW_REG_SVPE_LEN];
547
548 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
549 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
550}
551
552int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
553 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
554 u16 vid)
555{
556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
557 char svfa_pl[MLXSW_REG_SVFA_LEN];
558
559 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
560 fid, vid);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
562}
563
584d73df
IS		 564int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
565 u16 vid_begin, u16 vid_end,
566 bool learn_enable)
56ade8fe
JP		 567{
568 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
569 char *spvmlr_pl;
570 int err;
571
572 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
573 if (!spvmlr_pl)
574 return -ENOMEM;
584d73df
IS		 575 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid_begin,
576 vid_end, learn_enable);
56ade8fe
JP		 577 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
578 kfree(spvmlr_pl);
579 return err;
580}
581
584d73df
IS		 582static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
583 u16 vid, bool learn_enable)
584{
585 return __mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, vid,
586 learn_enable);
587}
588
56ade8fe
JP		 589static int
590mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
591{
592 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
593 char sspr_pl[MLXSW_REG_SSPR_LEN];
594
595 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
596 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
597}
598
d664b41e
IS		 599static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
600 u8 local_port, u8 *p_module,
601 u8 *p_width, u8 *p_lane)
56ade8fe 602{
56ade8fe
JP		 603 char pmlp_pl[MLXSW_REG_PMLP_LEN];
604 int err;
605
558c2d5e 606 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 607 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
608 if (err)
609 return err;
558c2d5e
IS		 610 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
611 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 612 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 613 return 0;
614}
615
18f1e70c
IS		 616static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
617 u8 module, u8 width, u8 lane)
618{
619 char pmlp_pl[MLXSW_REG_PMLP_LEN];
620 int i;
621
622 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
623 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
624 for (i = 0; i < width; i++) {
625 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
626 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
627 }
628
629 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
630}
631
3e9b27b8
IS		 632static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
633{
634 char pmlp_pl[MLXSW_REG_PMLP_LEN];
635
636 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
637 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
638 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
639}
640
56ade8fe
JP		 641static int mlxsw_sp_port_open(struct net_device *dev)
642{
643 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
644 int err;
645
646 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
647 if (err)
648 return err;
649 netif_start_queue(dev);
650 return 0;
651}
652
653static int mlxsw_sp_port_stop(struct net_device *dev)
654{
655 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
656
657 netif_stop_queue(dev);
658 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
659}
660
661static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
662 struct net_device *dev)
663{
664 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
666 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
667 const struct mlxsw_tx_info tx_info = {
668 .local_port = mlxsw_sp_port->local_port,
669 .is_emad = false,
670 };
671 u64 len;
672 int err;
673
307c2431 674 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 675 return NETDEV_TX_BUSY;
676
677 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
678 struct sk_buff *skb_orig = skb;
679
680 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
681 if (!skb) {
682 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
683 dev_kfree_skb_any(skb_orig);
684 return NETDEV_TX_OK;
685 }
686 }
687
688 if (eth_skb_pad(skb)) {
689 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
690 return NETDEV_TX_OK;
691 }
692
693 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 694 /* TX header is consumed by HW on the way so we shouldn't count its
695 * bytes as being sent.
696 */
697 len = skb->len - MLXSW_TXHDR_LEN;
698
56ade8fe
JP		 699 /* Due to a race we might fail here because of a full queue. In that
700 * unlikely case we simply drop the packet.
701 */
307c2431 702 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 703
704 if (!err) {
705 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
706 u64_stats_update_begin(&pcpu_stats->syncp);
707 pcpu_stats->tx_packets++;
708 pcpu_stats->tx_bytes += len;
709 u64_stats_update_end(&pcpu_stats->syncp);
710 } else {
711 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
712 dev_kfree_skb_any(skb);
713 }
714 return NETDEV_TX_OK;
715}
716
c5b9b518
JP		 717static void mlxsw_sp_set_rx_mode(struct net_device *dev)
718{
719}
720
56ade8fe
JP		 721static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
722{
723 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
724 struct sockaddr *addr = p;
725 int err;
726
727 if (!is_valid_ether_addr(addr->sa_data))
728 return -EADDRNOTAVAIL;
729
730 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
731 if (err)
732 return err;
733 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
734 return 0;
735}
736
9f7ec052 737static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
d81a6bdb 738 bool pause_en, bool pfc_en, u16 delay)
ff6551ec 739{
ff6551ec 740 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
8e8dfe9f 741
d81a6bdb
IS		 742 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
743 MLXSW_SP_PAUSE_DELAY;
9f7ec052 744
d81a6bdb 745 if (pause_en || pfc_en)
9f7ec052 746 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
d81a6bdb
IS		 747 pg_size + delay, pg_size);
748 else
9f7ec052 749 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
8e8dfe9f
IS		 750}
751
752int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 753 u8 *prio_tc, bool pause_en,
754 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 755{
756 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 757 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
758 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 759 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 760 int i, j, err;
ff6551ec
IS		 761
762 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
763 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
764 if (err)
765 return err;
8e8dfe9f
IS		 766
767 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
768 bool configure = false;
d81a6bdb 769 bool pfc = false;
8e8dfe9f
IS		 770
771 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
772 if (prio_tc[j] == i) {
d81a6bdb 773 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 774 configure = true;
775 break;
776 }
777 }
778
779 if (!configure)
780 continue;
d81a6bdb 781 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
8e8dfe9f
IS		 782 }
783
ff6551ec
IS		 784 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
785}
786
8e8dfe9f 787static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 788 int mtu, bool pause_en)
8e8dfe9f
IS		 789{
790 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
791 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 792 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 793 u8 *prio_tc;
794
795 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 796 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 797
9f7ec052 798 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 799 pause_en, my_pfc);
8e8dfe9f
IS		 800}
801
56ade8fe
JP		 802static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
803{
804 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 805 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 806 int err;
807
9f7ec052 808 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 809 if (err)
810 return err;
763b4b70
YG		 811 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
812 if (err)
813 goto err_span_port_mtu_update;
ff6551ec
IS		 814 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
815 if (err)
816 goto err_port_mtu_set;
56ade8fe
JP		 817 dev->mtu = mtu;
818 return 0;
ff6551ec
IS		 819
820err_port_mtu_set:
763b4b70
YG		 821 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
822err_span_port_mtu_update:
9f7ec052 823 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 824 return err;
56ade8fe
JP		 825}
826
4bdcc6ca 827static int
fc1bbb0f
NF		 828mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
829 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 830{
831 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
832 struct mlxsw_sp_port_pcpu_stats *p;
833 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
834 u32 tx_dropped = 0;
835 unsigned int start;
836 int i;
837
838 for_each_possible_cpu(i) {
839 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
840 do {
841 start = u64_stats_fetch_begin_irq(&p->syncp);
842 rx_packets = p->rx_packets;
843 rx_bytes = p->rx_bytes;
844 tx_packets = p->tx_packets;
845 tx_bytes = p->tx_bytes;
846 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
847
848 stats->rx_packets += rx_packets;
849 stats->rx_bytes += rx_bytes;
850 stats->tx_packets += tx_packets;
851 stats->tx_bytes += tx_bytes;
852 /* tx_dropped is u32, updated without syncp protection. */
853 tx_dropped += p->tx_dropped;
854 }
855 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 856 return 0;
857}
858
4bdcc6ca 859static bool mlxsw_sp_port_has_offload_stats(int attr_id)
fc1bbb0f
NF		 860{
861 switch (attr_id) {
862 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
863 return true;
864 }
865
866 return false;
867}
868
4bdcc6ca
OG		 869static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
870 void *sp)
fc1bbb0f
NF		 871{
872 switch (attr_id) {
873 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
874 return mlxsw_sp_port_get_sw_stats64(dev, sp);
875 }
876
877 return -EINVAL;
878}
879
880static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
881 int prio, char *ppcnt_pl)
882{
883 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
884 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
885
886 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
887 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
888}
889
890static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
891 struct rtnl_link_stats64 *stats)
892{
893 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
894 int err;
895
896 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
897 0, ppcnt_pl);
898 if (err)
899 goto out;
900
901 stats->tx_packets =
902 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
903 stats->rx_packets =
904 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
905 stats->tx_bytes =
906 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
907 stats->rx_bytes =
908 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
909 stats->multicast =
910 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
911
912 stats->rx_crc_errors =
913 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
914 stats->rx_frame_errors =
915 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
916
917 stats->rx_length_errors = (
918 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
919 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
920 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
921
922 stats->rx_errors = (stats->rx_crc_errors +
923 stats->rx_frame_errors + stats->rx_length_errors);
924
925out:
926 return err;
927}
928
929static void update_stats_cache(struct work_struct *work)
930{
931 struct mlxsw_sp_port *mlxsw_sp_port =
932 container_of(work, struct mlxsw_sp_port,
933 hw_stats.update_dw.work);
934
935 if (!netif_carrier_ok(mlxsw_sp_port->dev))
936 goto out;
937
938 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
939 mlxsw_sp_port->hw_stats.cache);
940
941out:
942 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
943 MLXSW_HW_STATS_UPDATE_TIME);
944}
945
946/* Return the stats from a cache that is updated periodically,
947 * as this function might get called in an atomic context.
948 */
949static struct rtnl_link_stats64 *
950mlxsw_sp_port_get_stats64(struct net_device *dev,
951 struct rtnl_link_stats64 *stats)
952{
953 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
954
955 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
956
56ade8fe
JP		 957 return stats;
958}
959
960int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
961 u16 vid_end, bool is_member, bool untagged)
962{
963 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
964 char *spvm_pl;
965 int err;
966
967 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
968 if (!spvm_pl)
969 return -ENOMEM;
970
971 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
972 vid_end, is_member, untagged);
973 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
974 kfree(spvm_pl);
975 return err;
976}
977
978static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
979{
980 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
981 u16 vid, last_visited_vid;
982 int err;
983
984 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
985 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
986 vid);
987 if (err) {
988 last_visited_vid = vid;
989 goto err_port_vid_to_fid_set;
990 }
991 }
992
993 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
994 if (err) {
995 last_visited_vid = VLAN_N_VID;
996 goto err_port_vid_to_fid_set;
997 }
998
999 return 0;
1000
1001err_port_vid_to_fid_set:
1002 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1003 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1004 vid);
1005 return err;
1006}
1007
1008static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1009{
1010 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1011 u16 vid;
1012 int err;
1013
1014 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1015 if (err)
1016 return err;
1017
1018 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1019 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1020 vid, vid);
1021 if (err)
1022 return err;
1023 }
1024
1025 return 0;
1026}
1027
7f71eb46 1028static struct mlxsw_sp_port *
0355b59f 1029mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
7f71eb46
IS		 1030{
1031 struct mlxsw_sp_port *mlxsw_sp_vport;
1032
1033 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1034 if (!mlxsw_sp_vport)
1035 return NULL;
1036
1037 /* dev will be set correctly after the VLAN device is linked
1038 * with the real device. In case of bridge SELF invocation, dev
1039 * will remain as is.
1040 */
1041 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1042 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1043 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1044 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
272c4470
IS		 1045 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1046 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
0355b59f 1047 mlxsw_sp_vport->vport.vid = vid;
7f71eb46
IS		 1048
1049 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1050
1051 return mlxsw_sp_vport;
1052}
1053
1054static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1055{
1056 list_del(&mlxsw_sp_vport->vport.list);
1057 kfree(mlxsw_sp_vport);
1058}
1059
05978481
IS		 1060static int mlxsw_sp_port_add_vid(struct net_device *dev,
1061 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1062{
1063 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 1064 struct mlxsw_sp_port *mlxsw_sp_vport;
52697a9e 1065 bool untagged = vid == 1;
56ade8fe
JP		 1066 int err;
1067
1068 /* VLAN 0 is added to HW filter when device goes up, but it is
1069 * reserved in our case, so simply return.
1070 */
1071 if (!vid)
1072 return 0;
1073
fa66d7e3 1074 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
56ade8fe 1075 return 0;
56ade8fe 1076
0355b59f 1077 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
fa66d7e3 1078 if (!mlxsw_sp_vport)
0355b59f 1079 return -ENOMEM;
56ade8fe 1080
56ade8fe
JP		 1081 /* When adding the first VLAN interface on a bridged port we need to
1082 * transition all the active 802.1Q bridge VLANs to use explicit
1083 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1084 */
7f71eb46 1085 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe 1086 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
fa66d7e3 1087 if (err)
7f71eb46 1088 goto err_port_vp_mode_trans;
56ade8fe
JP		 1089 }
1090
52697a9e 1091 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
fa66d7e3 1092 if (err)
56ade8fe 1093 goto err_port_add_vid;
56ade8fe 1094
56ade8fe
JP		 1095 return 0;
1096
56ade8fe 1097err_port_add_vid:
7f71eb46
IS		 1098 if (list_is_singular(&mlxsw_sp_port->vports_list))
1099 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1100err_port_vp_mode_trans:
7f71eb46 1101 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
56ade8fe
JP		 1102 return err;
1103}
1104
32d863fb
IS		 1105static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1106 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1107{
1108 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 1109 struct mlxsw_sp_port *mlxsw_sp_vport;
1c800759 1110 struct mlxsw_sp_fid *f;
56ade8fe
JP		 1111
1112 /* VLAN 0 is removed from HW filter when device goes down, but
1113 * it is reserved in our case, so simply return.
1114 */
1115 if (!vid)
1116 return 0;
1117
7f71eb46 1118 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
7a35583e 1119 if (WARN_ON(!mlxsw_sp_vport))
56ade8fe 1120 return 0;
56ade8fe 1121
7a35583e 1122 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe 1123
1c800759
IS		 1124 /* Drop FID reference. If this was the last reference the
1125 * resources will be freed.
1126 */
1127 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1128 if (f && !WARN_ON(!f->leave))
1129 f->leave(mlxsw_sp_vport);
56ade8fe
JP		 1130
1131 /* When removing the last VLAN interface on a bridged port we need to
1132 * transition all active 802.1Q bridge VLANs to use VID to FID
1133 * mappings and set port's mode to VLAN mode.
1134 */
7a35583e
IS		 1135 if (list_is_singular(&mlxsw_sp_port->vports_list))
1136 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
56ade8fe 1137
7f71eb46
IS		 1138 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1139
56ade8fe
JP		 1140 return 0;
1141}
1142
2bf9a586
IS		 1143static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1144 size_t len)
1145{
1146 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1147 u8 module = mlxsw_sp_port->mapping.module;
1148 u8 width = mlxsw_sp_port->mapping.width;
1149 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1150 int err;
1151
2bf9a586
IS		 1152 if (!mlxsw_sp_port->split)
1153 err = snprintf(name, len, "p%d", module + 1);
1154 else
1155 err = snprintf(name, len, "p%ds%d", module + 1,
1156 lane / width);
1157
1158 if (err >= len)
1159 return -EINVAL;
1160
1161 return 0;
1162}
1163
763b4b70
YG		 1164static struct mlxsw_sp_port_mall_tc_entry *
1165mlxsw_sp_port_mirror_entry_find(struct mlxsw_sp_port *port,
1166 unsigned long cookie) {
1167 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1168
1169 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1170 if (mall_tc_entry->cookie == cookie)
1171 return mall_tc_entry;
1172
1173 return NULL;
1174}
1175
1176static int
1177mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1178 struct tc_cls_matchall_offload *cls,
1179 const struct tc_action *a,
1180 bool ingress)
1181{
1182 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1183 struct net *net = dev_net(mlxsw_sp_port->dev);
1184 enum mlxsw_sp_span_type span_type;
1185 struct mlxsw_sp_port *to_port;
1186 struct net_device *to_dev;
1187 int ifindex;
1188 int err;
1189
1190 ifindex = tcf_mirred_ifindex(a);
1191 to_dev = __dev_get_by_index(net, ifindex);
1192 if (!to_dev) {
1193 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1194 return -EINVAL;
1195 }
1196
1197 if (!mlxsw_sp_port_dev_check(to_dev)) {
1198 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
1199 return -ENOTSUPP;
1200 }
1201 to_port = netdev_priv(to_dev);
1202
1203 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1204 if (!mall_tc_entry)
1205 return -ENOMEM;
1206
1207 mall_tc_entry->cookie = cls->cookie;
1208 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1209 mall_tc_entry->mirror.to_local_port = to_port->local_port;
1210 mall_tc_entry->mirror.ingress = ingress;
1211 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1212
1213 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1214 err = mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1215 if (err)
1216 goto err_mirror_add;
1217 return 0;
1218
1219err_mirror_add:
1220 list_del(&mall_tc_entry->list);
1221 kfree(mall_tc_entry);
1222 return err;
1223}
1224
1225static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1226 __be16 protocol,
1227 struct tc_cls_matchall_offload *cls,
1228 bool ingress)
1229{
763b4b70 1230 const struct tc_action *a;
22dc13c8 1231 LIST_HEAD(actions);
763b4b70
YG		 1232 int err;
1233
86cb13e4 1234 if (!tc_single_action(cls->exts)) {
763b4b70
YG		 1235 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1236 return -ENOTSUPP;
1237 }
1238
22dc13c8
WC		 1239 tcf_exts_to_list(cls->exts, &actions);
1240 list_for_each_entry(a, &actions, list) {
5724b8b5
SL		 1241 if (!is_tcf_mirred_egress_mirror(a) ||
1242 protocol != htons(ETH_P_ALL)) {
86cb13e4 1243 return -ENOTSUPP;
5724b8b5 1244 }
86cb13e4 1245
763b4b70
YG		 1246 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, cls,
1247 a, ingress);
1248 if (err)
1249 return err;
763b4b70
YG		 1250 }
1251
1252 return 0;
1253}
1254
1255static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1256 struct tc_cls_matchall_offload *cls)
1257{
1258 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1259 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1260 enum mlxsw_sp_span_type span_type;
1261 struct mlxsw_sp_port *to_port;
1262
1263 mall_tc_entry = mlxsw_sp_port_mirror_entry_find(mlxsw_sp_port,
1264 cls->cookie);
1265 if (!mall_tc_entry) {
1266 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1267 return;
1268 }
1269
1270 switch (mall_tc_entry->type) {
1271 case MLXSW_SP_PORT_MALL_MIRROR:
1272 to_port = mlxsw_sp->ports[mall_tc_entry->mirror.to_local_port];
1273 span_type = mall_tc_entry->mirror.ingress ?
1274 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1275
1276 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
1277 break;
1278 default:
1279 WARN_ON(1);
1280 }
1281
1282 list_del(&mall_tc_entry->list);
1283 kfree(mall_tc_entry);
1284}
1285
1286static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1287 __be16 proto, struct tc_to_netdev *tc)
1288{
1289 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1290 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1291
1292 if (tc->type == TC_SETUP_MATCHALL) {
1293 switch (tc->cls_mall->command) {
1294 case TC_CLSMATCHALL_REPLACE:
1295 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1296 proto,
1297 tc->cls_mall,
1298 ingress);
1299 case TC_CLSMATCHALL_DESTROY:
1300 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1301 tc->cls_mall);
1302 return 0;
1303 default:
1304 return -EINVAL;
1305 }
1306 }
1307
1308 return -ENOTSUPP;
1309}
1310
56ade8fe
JP		 1311static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1312 .ndo_open = mlxsw_sp_port_open,
1313 .ndo_stop = mlxsw_sp_port_stop,
1314 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 1315 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 1316 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 1317 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1318 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1319 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 1320 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1321 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 1322 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1323 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
6cf3c971
JP		 1324 .ndo_neigh_construct = mlxsw_sp_router_neigh_construct,
1325 .ndo_neigh_destroy = mlxsw_sp_router_neigh_destroy,
56ade8fe
JP		 1326 .ndo_fdb_add = switchdev_port_fdb_add,
1327 .ndo_fdb_del = switchdev_port_fdb_del,
1328 .ndo_fdb_dump = switchdev_port_fdb_dump,
1329 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1330 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1331 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
2bf9a586 1332 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 1333};
1334
1335static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1336 struct ethtool_drvinfo *drvinfo)
1337{
1338 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1339 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1340
1341 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1342 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1343 sizeof(drvinfo->version));
1344 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1345 "%d.%d.%d",
1346 mlxsw_sp->bus_info->fw_rev.major,
1347 mlxsw_sp->bus_info->fw_rev.minor,
1348 mlxsw_sp->bus_info->fw_rev.subminor);
1349 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1350 sizeof(drvinfo->bus_info));
1351}
1352
9f7ec052
IS		 1353static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1354 struct ethtool_pauseparam *pause)
1355{
1356 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1357
1358 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1359 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1360}
1361
1362static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1363 struct ethtool_pauseparam *pause)
1364{
1365 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1366
1367 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1368 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1369 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1370
1371 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1372 pfcc_pl);
1373}
1374
1375static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1376 struct ethtool_pauseparam *pause)
1377{
1378 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1379 bool pause_en = pause->tx_pause || pause->rx_pause;
1380 int err;
1381
d81a6bdb
IS		 1382 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1383 netdev_err(dev, "PFC already enabled on port\n");
1384 return -EINVAL;
1385 }
1386
9f7ec052
IS		 1387 if (pause->autoneg) {
1388 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1389 return -EINVAL;
1390 }
1391
1392 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1393 if (err) {
1394 netdev_err(dev, "Failed to configure port's headroom\n");
1395 return err;
1396 }
1397
1398 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1399 if (err) {
1400 netdev_err(dev, "Failed to set PAUSE parameters\n");
1401 goto err_port_pause_configure;
1402 }
1403
1404 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1405 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1406
1407 return 0;
1408
1409err_port_pause_configure:
1410 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1411 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1412 return err;
1413}
1414
56ade8fe
JP		 1415struct mlxsw_sp_port_hw_stats {
1416 char str[ETH_GSTRING_LEN];
412791df 1417 u64 (*getter)(const char *payload);
56ade8fe
JP		 1418};
1419
7ed674bc 1420static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 1421 {
1422 .str = "a_frames_transmitted_ok",
1423 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1424 },
1425 {
1426 .str = "a_frames_received_ok",
1427 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1428 },
1429 {
1430 .str = "a_frame_check_sequence_errors",
1431 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1432 },
1433 {
1434 .str = "a_alignment_errors",
1435 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1436 },
1437 {
1438 .str = "a_octets_transmitted_ok",
1439 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1440 },
1441 {
1442 .str = "a_octets_received_ok",
1443 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1444 },
1445 {
1446 .str = "a_multicast_frames_xmitted_ok",
1447 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1448 },
1449 {
1450 .str = "a_broadcast_frames_xmitted_ok",
1451 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1452 },
1453 {
1454 .str = "a_multicast_frames_received_ok",
1455 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1456 },
1457 {
1458 .str = "a_broadcast_frames_received_ok",
1459 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1460 },
1461 {
1462 .str = "a_in_range_length_errors",
1463 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1464 },
1465 {
1466 .str = "a_out_of_range_length_field",
1467 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1468 },
1469 {
1470 .str = "a_frame_too_long_errors",
1471 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1472 },
1473 {
1474 .str = "a_symbol_error_during_carrier",
1475 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1476 },
1477 {
1478 .str = "a_mac_control_frames_transmitted",
1479 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1480 },
1481 {
1482 .str = "a_mac_control_frames_received",
1483 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1484 },
1485 {
1486 .str = "a_unsupported_opcodes_received",
1487 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1488 },
1489 {
1490 .str = "a_pause_mac_ctrl_frames_received",
1491 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1492 },
1493 {
1494 .str = "a_pause_mac_ctrl_frames_xmitted",
1495 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1496 },
1497};
1498
1499#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1500
7ed674bc
IS		 1501static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1502 {
1503 .str = "rx_octets_prio",
1504 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1505 },
1506 {
1507 .str = "rx_frames_prio",
1508 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1509 },
1510 {
1511 .str = "tx_octets_prio",
1512 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1513 },
1514 {
1515 .str = "tx_frames_prio",
1516 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1517 },
1518 {
1519 .str = "rx_pause_prio",
1520 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1521 },
1522 {
1523 .str = "rx_pause_duration_prio",
1524 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1525 },
1526 {
1527 .str = "tx_pause_prio",
1528 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1529 },
1530 {
1531 .str = "tx_pause_duration_prio",
1532 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1533 },
1534};
1535
1536#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1537
412791df 1538static u64 mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get(const char *ppcnt_pl)
df4750e8
IS		 1539{
1540 u64 transmit_queue = mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1541
1542 return MLXSW_SP_CELLS_TO_BYTES(transmit_queue);
1543}
1544
1545static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1546 {
1547 .str = "tc_transmit_queue_tc",
1548 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get,
1549 },
1550 {
1551 .str = "tc_no_buffer_discard_uc_tc",
1552 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1553 },
1554};
1555
1556#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1557
7ed674bc 1558#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 1559 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1560 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 1561 IEEE_8021QAZ_MAX_TCS)
1562
1563static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1564{
1565 int i;
1566
1567 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1568 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1569 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1570 *p += ETH_GSTRING_LEN;
1571 }
1572}
1573
df4750e8
IS		 1574static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1575{
1576 int i;
1577
1578 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1579 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1580 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1581 *p += ETH_GSTRING_LEN;
1582 }
1583}
1584
56ade8fe
JP		 1585static void mlxsw_sp_port_get_strings(struct net_device *dev,
1586 u32 stringset, u8 *data)
1587{
1588 u8 *p = data;
1589 int i;
1590
1591 switch (stringset) {
1592 case ETH_SS_STATS:
1593 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1594 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1595 ETH_GSTRING_LEN);
1596 p += ETH_GSTRING_LEN;
1597 }
7ed674bc
IS		 1598
1599 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1600 mlxsw_sp_port_get_prio_strings(&p, i);
1601
df4750e8
IS		 1602 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1603 mlxsw_sp_port_get_tc_strings(&p, i);
1604
56ade8fe
JP		 1605 break;
1606 }
1607}
1608
3a66ee38
IS		 1609static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1610 enum ethtool_phys_id_state state)
1611{
1612 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1613 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1614 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1615 bool active;
1616
1617 switch (state) {
1618 case ETHTOOL_ID_ACTIVE:
1619 active = true;
1620 break;
1621 case ETHTOOL_ID_INACTIVE:
1622 active = false;
1623 break;
1624 default:
1625 return -EOPNOTSUPP;
1626 }
1627
1628 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1629 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1630}
1631
7ed674bc
IS		 1632static int
1633mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1634 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1635{
1636 switch (grp) {
1637 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1638 *p_hw_stats = mlxsw_sp_port_hw_stats;
1639 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1640 break;
1641 case MLXSW_REG_PPCNT_PRIO_CNT:
1642 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1643 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1644 break;
df4750e8
IS		 1645 case MLXSW_REG_PPCNT_TC_CNT:
1646 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1647 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1648 break;
7ed674bc
IS		 1649 default:
1650 WARN_ON(1);
1651 return -ENOTSUPP;
1652 }
1653 return 0;
1654}
1655
1656static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1657 enum mlxsw_reg_ppcnt_grp grp, int prio,
1658 u64 *data, int data_index)
56ade8fe 1659{
7ed674bc 1660 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 1661 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 1662 int i, len;
56ade8fe
JP		 1663 int err;
1664
7ed674bc
IS		 1665 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1666 if (err)
1667 return;
fc1bbb0f 1668 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
7ed674bc 1669 for (i = 0; i < len; i++)
faac0ff0 1670 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
7ed674bc
IS		 1671}
1672
1673static void mlxsw_sp_port_get_stats(struct net_device *dev,
1674 struct ethtool_stats *stats, u64 *data)
1675{
1676 int i, data_index = 0;
1677
1678 /* IEEE 802.3 Counters */
1679 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1680 data, data_index);
1681 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1682
1683 /* Per-Priority Counters */
1684 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1685 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1686 data, data_index);
1687 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1688 }
df4750e8
IS		 1689
1690 /* Per-TC Counters */
1691 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1692 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1693 data, data_index);
1694 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1695 }
56ade8fe
JP		 1696}
1697
1698static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1699{
1700 switch (sset) {
1701 case ETH_SS_STATS:
7ed674bc 1702 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 1703 default:
1704 return -EOPNOTSUPP;
1705 }
1706}
1707
1708struct mlxsw_sp_port_link_mode {
b9d66a36 1709 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 1710 u32 mask;
56ade8fe
JP		 1711 u32 speed;
1712};
1713
1714static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1715 {
1716 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 1717 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1718 .speed = SPEED_100,
56ade8fe
JP		 1719 },
1720 {
1721 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1722 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 1723 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1724 .speed = SPEED_1000,
56ade8fe
JP		 1725 },
1726 {
1727 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 1728 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1729 .speed = SPEED_10000,
56ade8fe
JP		 1730 },
1731 {
1732 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1733 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 1734 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1735 .speed = SPEED_10000,
56ade8fe
JP		 1736 },
1737 {
1738 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1739 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1740 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1741 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 1742 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1743 .speed = SPEED_10000,
56ade8fe
JP		 1744 },
1745 {
1746 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 1747 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
1748 .speed = SPEED_20000,
56ade8fe
JP		 1749 },
1750 {
1751 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 1752 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1753 .speed = SPEED_40000,
56ade8fe
JP		 1754 },
1755 {
1756 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 1757 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1758 .speed = SPEED_40000,
56ade8fe
JP		 1759 },
1760 {
1761 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 1762 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1763 .speed = SPEED_40000,
56ade8fe
JP		 1764 },
1765 {
1766 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 1767 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1768 .speed = SPEED_40000,
1769 },
1770 {
1771 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1772 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1773 .speed = SPEED_25000,
1774 },
1775 {
1776 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1777 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1778 .speed = SPEED_25000,
1779 },
1780 {
1781 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1782 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1783 .speed = SPEED_25000,
56ade8fe
JP		 1784 },
1785 {
b9d66a36
IS		 1786 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1787 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1788 .speed = SPEED_25000,
56ade8fe
JP		 1789 },
1790 {
b9d66a36
IS		 1791 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1792 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1793 .speed = SPEED_50000,
1794 },
1795 {
1796 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1797 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1798 .speed = SPEED_50000,
1799 },
1800 {
1801 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1802 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1803 .speed = SPEED_50000,
56ade8fe
JP		 1804 },
1805 {
1806 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 1807 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
1808 .speed = SPEED_56000,
56ade8fe
JP		 1809 },
1810 {
b9d66a36
IS		 1811 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1812 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
1813 .speed = SPEED_56000,
1814 },
1815 {
1816 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1817 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
1818 .speed = SPEED_56000,
1819 },
1820 {
1821 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1822 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
1823 .speed = SPEED_56000,
1824 },
1825 {
1826 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
1827 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1828 .speed = SPEED_100000,
1829 },
1830 {
1831 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
1832 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1833 .speed = SPEED_100000,
1834 },
1835 {
1836 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
1837 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1838 .speed = SPEED_100000,
1839 },
1840 {
1841 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1842 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1843 .speed = SPEED_100000,
56ade8fe
JP		 1844 },
1845};
1846
1847#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1848
b9d66a36
IS		 1849static void
1850mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
1851 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1852{
1853 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1854 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1855 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1856 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1857 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1858 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 1859 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 1860
1861 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1862 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1863 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1864 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1865 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 1866 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 1867}
1868
b9d66a36 1869static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 1870{
56ade8fe
JP		 1871 int i;
1872
1873 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1874 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 1875 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1876 mode);
56ade8fe 1877 }
56ade8fe
JP		 1878}
1879
1880static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 1881 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1882{
1883 u32 speed = SPEED_UNKNOWN;
1884 u8 duplex = DUPLEX_UNKNOWN;
1885 int i;
1886
1887 if (!carrier_ok)
1888 goto out;
1889
1890 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1891 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1892 speed = mlxsw_sp_port_link_mode[i].speed;
1893 duplex = DUPLEX_FULL;
1894 break;
1895 }
1896 }
1897out:
b9d66a36
IS		 1898 cmd->base.speed = speed;
1899 cmd->base.duplex = duplex;
56ade8fe
JP		 1900}
1901
1902static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1903{
1904 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1905 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1906 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1907 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1908 return PORT_FIBRE;
1909
1910 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1911 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1912 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1913 return PORT_DA;
1914
1915 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1916 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1917 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1918 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1919 return PORT_NONE;
1920
1921 return PORT_OTHER;
1922}
1923
b9d66a36
IS		 1924static u32
1925mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1926{
1927 u32 ptys_proto = 0;
1928 int i;
1929
1930 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 1931 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1932 cmd->link_modes.advertising))
56ade8fe
JP		 1933 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1934 }
1935 return ptys_proto;
1936}
1937
1938static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1939{
1940 u32 ptys_proto = 0;
1941 int i;
1942
1943 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1944 if (speed == mlxsw_sp_port_link_mode[i].speed)
1945 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1946 }
1947 return ptys_proto;
1948}
1949
18f1e70c
IS		 1950static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1951{
1952 u32 ptys_proto = 0;
1953 int i;
1954
1955 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1956 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1957 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1958 }
1959 return ptys_proto;
1960}
1961
b9d66a36
IS		 1962static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
1963 struct ethtool_link_ksettings *cmd)
1964{
1965 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
1966 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
1967 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
1968
1969 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
1970 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
1971}
1972
1973static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
1974 struct ethtool_link_ksettings *cmd)
56ade8fe 1975{
b9d66a36
IS		 1976 if (!autoneg)
1977 return;
1978
1979 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
1980 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
1981}
1982
1983static void
1984mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
1985 struct ethtool_link_ksettings *cmd)
1986{
1987 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
1988 return;
1989
1990 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
1991 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
1992}
1993
1994static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
1995 struct ethtool_link_ksettings *cmd)
1996{
1997 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 1998 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1999 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2000 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2001 u8 autoneg_status;
0c83f88c 2002 bool autoneg;
56ade8fe
JP		 2003 int err;
2004
b9d66a36
IS		 2005 autoneg = mlxsw_sp_port->link.autoneg;
2006 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2007 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2008 if (err)
2009 return err;
2010 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2011 &eth_proto_oper);
2012
2013 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2014
b9d66a36
IS		 2015 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2016
2017 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2018 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2019 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2020
2021 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2022 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2023 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2024 cmd);
2025
2026 return 0;
2027}
2028
2029static int
2030mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2031 const struct ethtool_link_ksettings *cmd)
2032{
2033 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2034 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2035 char ptys_pl[MLXSW_REG_PTYS_LEN];
2036 u32 eth_proto_cap, eth_proto_new;
2037 bool autoneg;
2038 int err;
56ade8fe
JP		 2039
2040 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2041 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2042 if (err)
56ade8fe 2043 return err;
b9d66a36
IS		 2044 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2045
2046 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2047 eth_proto_new = autoneg ?
2048 mlxsw_sp_to_ptys_advert_link(cmd) :
2049 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2050
2051 eth_proto_new = eth_proto_new & eth_proto_cap;
2052 if (!eth_proto_new) {
b9d66a36 2053 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2054 return -EINVAL;
2055 }
56ade8fe
JP		 2056
2057 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
2058 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2059 if (err)
56ade8fe 2060 return err;
56ade8fe 2061
6277d46b 2062 if (!netif_running(dev))
56ade8fe
JP		 2063 return 0;
2064
0c83f88c
IS		 2065 mlxsw_sp_port->link.autoneg = autoneg;
2066
b9d66a36
IS		 2067 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2068 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2069
2070 return 0;
2071}
2072
2073static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2074 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2075 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2076 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2077 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2078 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2079 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2080 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2081 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2082 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2083 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
56ade8fe
JP		 2084};
2085
18f1e70c
IS		 2086static int
2087mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2088{
2089 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2090 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2091 char ptys_pl[MLXSW_REG_PTYS_LEN];
2092 u32 eth_proto_admin;
2093
2094 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2095 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
2096 eth_proto_admin);
2097 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2098}
2099
8e8dfe9f
IS		 2100int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2101 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2102 bool dwrr, u8 dwrr_weight)
90183b98
IS		 2103{
2104 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2105 char qeec_pl[MLXSW_REG_QEEC_LEN];
2106
2107 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2108 next_index);
2109 mlxsw_reg_qeec_de_set(qeec_pl, true);
2110 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2111 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2112 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2113}
2114
cc7cf517
IS		 2115int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2116 enum mlxsw_reg_qeec_hr hr, u8 index,
2117 u8 next_index, u32 maxrate)
90183b98
IS		 2118{
2119 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2120 char qeec_pl[MLXSW_REG_QEEC_LEN];
2121
2122 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2123 next_index);
2124 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2125 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2126 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2127}
2128
8e8dfe9f
IS		 2129int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2130 u8 switch_prio, u8 tclass)
90183b98
IS		 2131{
2132 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2133 char qtct_pl[MLXSW_REG_QTCT_LEN];
2134
2135 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2136 tclass);
2137 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2138}
2139
2140static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2141{
2142 int err, i;
2143
2144 /* Setup the elements hierarcy, so that each TC is linked to
2145 * one subgroup, which are all member in the same group.
2146 */
2147 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2148 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2149 0);
2150 if (err)
2151 return err;
2152 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2153 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2154 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2155 0, false, 0);
2156 if (err)
2157 return err;
2158 }
2159 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2160 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2161 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2162 false, 0);
2163 if (err)
2164 return err;
2165 }
2166
2167 /* Make sure the max shaper is disabled in all hierarcies that
2168 * support it.
2169 */
2170 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2171 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2172 MLXSW_REG_QEEC_MAS_DIS);
2173 if (err)
2174 return err;
2175 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2176 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2177 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2178 i, 0,
2179 MLXSW_REG_QEEC_MAS_DIS);
2180 if (err)
2181 return err;
2182 }
2183 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2184 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2185 MLXSW_REG_QEEC_HIERARCY_TC,
2186 i, i,
2187 MLXSW_REG_QEEC_MAS_DIS);
2188 if (err)
2189 return err;
2190 }
2191
2192 /* Map all priorities to traffic class 0. */
2193 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2194 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2195 if (err)
2196 return err;
2197 }
2198
2199 return 0;
2200}
2201
05978481
IS		 2202static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2203{
2204 mlxsw_sp_port->pvid = 1;
2205
2206 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2207}
2208
2209static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2210{
2211 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2212}
2213
be94535f 2214static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
d664b41e 2215 bool split, u8 module, u8 width, u8 lane)
56ade8fe
JP		 2216{
2217 struct mlxsw_sp_port *mlxsw_sp_port;
2218 struct net_device *dev;
bd40e9d6 2219 size_t bytes;
56ade8fe
JP		 2220 int err;
2221
2222 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2223 if (!dev)
2224 return -ENOMEM;
f20a91f1 2225 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 2226 mlxsw_sp_port = netdev_priv(dev);
2227 mlxsw_sp_port->dev = dev;
2228 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2229 mlxsw_sp_port->local_port = local_port;
18f1e70c 2230 mlxsw_sp_port->split = split;
d664b41e
IS		 2231 mlxsw_sp_port->mapping.module = module;
2232 mlxsw_sp_port->mapping.width = width;
2233 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 2234 mlxsw_sp_port->link.autoneg = 1;
bd40e9d6
IS		 2235 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2236 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2237 if (!mlxsw_sp_port->active_vlans) {
2238 err = -ENOMEM;
2239 goto err_port_active_vlans_alloc;
2240 }
fc1273af
ER		 2241 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2242 if (!mlxsw_sp_port->untagged_vlans) {
2243 err = -ENOMEM;
2244 goto err_port_untagged_vlans_alloc;
2245 }
7f71eb46 2246 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
763b4b70 2247 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 2248
2249 mlxsw_sp_port->pcpu_stats =
2250 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2251 if (!mlxsw_sp_port->pcpu_stats) {
2252 err = -ENOMEM;
2253 goto err_alloc_stats;
2254 }
2255
fc1bbb0f
NF		 2256 mlxsw_sp_port->hw_stats.cache =
2257 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2258
2259 if (!mlxsw_sp_port->hw_stats.cache) {
2260 err = -ENOMEM;
2261 goto err_alloc_hw_stats;
2262 }
2263 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2264 &update_stats_cache);
2265
56ade8fe
JP		 2266 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2267 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2268
3247ff2b
IS		 2269 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2270 if (err) {
2271 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2272 mlxsw_sp_port->local_port);
2273 goto err_port_swid_set;
2274 }
2275
56ade8fe
JP		 2276 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2277 if (err) {
2278 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2279 mlxsw_sp_port->local_port);
2280 goto err_dev_addr_init;
2281 }
2282
2283 netif_carrier_off(dev);
2284
2285 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 2286 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2287 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 2288
d894be57
JW		 2289 dev->min_mtu = 0;
2290 dev->max_mtu = ETH_MAX_MTU;
2291
56ade8fe
JP		 2292 /* Each packet needs to have a Tx header (metadata) on top all other
2293 * headers.
2294 */
feb7d387 2295 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 2296
56ade8fe
JP		 2297 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2298 if (err) {
2299 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2300 mlxsw_sp_port->local_port);
2301 goto err_port_system_port_mapping_set;
2302 }
2303
18f1e70c
IS		 2304 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2305 if (err) {
2306 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2307 mlxsw_sp_port->local_port);
2308 goto err_port_speed_by_width_set;
2309 }
2310
56ade8fe
JP		 2311 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2312 if (err) {
2313 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2314 mlxsw_sp_port->local_port);
2315 goto err_port_mtu_set;
2316 }
2317
2318 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2319 if (err)
2320 goto err_port_admin_status_set;
2321
2322 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2323 if (err) {
2324 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2325 mlxsw_sp_port->local_port);
2326 goto err_port_buffers_init;
2327 }
2328
90183b98
IS		 2329 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2330 if (err) {
2331 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2332 mlxsw_sp_port->local_port);
2333 goto err_port_ets_init;
2334 }
2335
f00817df
IS		 2336 /* ETS and buffers must be initialized before DCB. */
2337 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2338 if (err) {
2339 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2340 mlxsw_sp_port->local_port);
2341 goto err_port_dcb_init;
2342 }
2343
05978481
IS		 2344 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2345 if (err) {
2346 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2347 mlxsw_sp_port->local_port);
2348 goto err_port_pvid_vport_create;
2349 }
2350
56ade8fe 2351 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 2352 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 2353 err = register_netdev(dev);
2354 if (err) {
2355 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2356 mlxsw_sp_port->local_port);
2357 goto err_register_netdev;
2358 }
2359
932762b6
JP		 2360 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
2361 mlxsw_sp_port->local_port, dev,
2362 mlxsw_sp_port->split, module);
2363 if (err) {
2364 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2365 mlxsw_sp_port->local_port);
2366 goto err_core_port_init;
2367 }
c4745500 2368
fc1bbb0f 2369 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
56ade8fe
JP		 2370 return 0;
2371
932762b6 2372err_core_port_init:
56ade8fe
JP		 2373 unregister_netdev(dev);
2374err_register_netdev:
2f25844c 2375 mlxsw_sp->ports[local_port] = NULL;
0583272d 2376 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
05978481
IS		 2377 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2378err_port_pvid_vport_create:
4de34eb5 2379 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 2380err_port_dcb_init:
90183b98 2381err_port_ets_init:
56ade8fe
JP		 2382err_port_buffers_init:
2383err_port_admin_status_set:
2384err_port_mtu_set:
18f1e70c 2385err_port_speed_by_width_set:
56ade8fe 2386err_port_system_port_mapping_set:
56ade8fe 2387err_dev_addr_init:
3247ff2b
IS		 2388 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2389err_port_swid_set:
fc1bbb0f
NF		 2390 kfree(mlxsw_sp_port->hw_stats.cache);
2391err_alloc_hw_stats:
56ade8fe
JP		 2392 free_percpu(mlxsw_sp_port->pcpu_stats);
2393err_alloc_stats:
fc1273af
ER		 2394 kfree(mlxsw_sp_port->untagged_vlans);
2395err_port_untagged_vlans_alloc:
bd40e9d6
IS		 2396 kfree(mlxsw_sp_port->active_vlans);
2397err_port_active_vlans_alloc:
56ade8fe
JP		 2398 free_netdev(dev);
2399 return err;
2400}
2401
56ade8fe
JP		 2402static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2403{
2404 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2405
2406 if (!mlxsw_sp_port)
2407 return;
fc1bbb0f 2408 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
932762b6 2409 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
56ade8fe 2410 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 2411 mlxsw_sp->ports[local_port] = NULL;
0583272d 2412 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
05978481 2413 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
f00817df 2414 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8
IS		 2415 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2416 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
56ade8fe 2417 free_percpu(mlxsw_sp_port->pcpu_stats);
fc1bbb0f 2418 kfree(mlxsw_sp_port->hw_stats.cache);
fc1273af 2419 kfree(mlxsw_sp_port->untagged_vlans);
bd40e9d6 2420 kfree(mlxsw_sp_port->active_vlans);
32d863fb 2421 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
56ade8fe
JP		 2422 free_netdev(mlxsw_sp_port->dev);
2423}
2424
2425static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2426{
2427 int i;
2428
2429 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
2430 mlxsw_sp_port_remove(mlxsw_sp, i);
2431 kfree(mlxsw_sp->ports);
2432}
2433
2434static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2435{
d664b41e 2436 u8 module, width, lane;
56ade8fe
JP		 2437 size_t alloc_size;
2438 int i;
2439 int err;
2440
2441 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
2442 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2443 if (!mlxsw_sp->ports)
2444 return -ENOMEM;
2445
2446 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
558c2d5e 2447 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 2448 &width, &lane);
558c2d5e
IS		 2449 if (err)
2450 goto err_port_module_info_get;
2451 if (!width)
2452 continue;
2453 mlxsw_sp->port_to_module[i] = module;
d664b41e
IS		 2454 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
2455 lane);
56ade8fe
JP		 2456 if (err)
2457 goto err_port_create;
2458 }
2459 return 0;
2460
2461err_port_create:
558c2d5e 2462err_port_module_info_get:
56ade8fe
JP		 2463 for (i--; i >= 1; i--)
2464 mlxsw_sp_port_remove(mlxsw_sp, i);
2465 kfree(mlxsw_sp->ports);
2466 return err;
2467}
2468
18f1e70c
IS		 2469static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2470{
2471 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2472
2473 return local_port - offset;
2474}
2475
be94535f
IS		 2476static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2477 u8 module, unsigned int count)
2478{
2479 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2480 int err, i;
2481
2482 for (i = 0; i < count; i++) {
2483 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2484 width, i * width);
2485 if (err)
2486 goto err_port_module_map;
2487 }
2488
2489 for (i = 0; i < count; i++) {
2490 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2491 if (err)
2492 goto err_port_swid_set;
2493 }
2494
2495 for (i = 0; i < count; i++) {
2496 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 2497 module, width, i * width);
be94535f
IS		 2498 if (err)
2499 goto err_port_create;
2500 }
2501
2502 return 0;
2503
2504err_port_create:
2505 for (i--; i >= 0; i--)
2506 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2507 i = count;
2508err_port_swid_set:
2509 for (i--; i >= 0; i--)
2510 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2511 MLXSW_PORT_SWID_DISABLED_PORT);
2512 i = count;
2513err_port_module_map:
2514 for (i--; i >= 0; i--)
2515 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2516 return err;
2517}
2518
2519static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2520 u8 base_port, unsigned int count)
2521{
2522 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2523 int i;
2524
2525 /* Split by four means we need to re-create two ports, otherwise
2526 * only one.
2527 */
2528 count = count / 2;
2529
2530 for (i = 0; i < count; i++) {
2531 local_port = base_port + i * 2;
2532 module = mlxsw_sp->port_to_module[local_port];
2533
2534 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2535 0);
2536 }
2537
2538 for (i = 0; i < count; i++)
2539 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2540
2541 for (i = 0; i < count; i++) {
2542 local_port = base_port + i * 2;
2543 module = mlxsw_sp->port_to_module[local_port];
2544
2545 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 2546 width, 0);
be94535f
IS		 2547 }
2548}
2549
b2f10571
JP		 2550static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2551 unsigned int count)
18f1e70c 2552{
b2f10571 2553 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2554 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 2555 u8 module, cur_width, base_port;
2556 int i;
2557 int err;
2558
2559 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2560 if (!mlxsw_sp_port) {
2561 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2562 local_port);
2563 return -EINVAL;
2564 }
2565
d664b41e
IS		 2566 module = mlxsw_sp_port->mapping.module;
2567 cur_width = mlxsw_sp_port->mapping.width;
2568
18f1e70c
IS		 2569 if (count != 2 && count != 4) {
2570 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2571 return -EINVAL;
2572 }
2573
18f1e70c
IS		 2574 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2575 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2576 return -EINVAL;
2577 }
2578
2579 /* Make sure we have enough slave (even) ports for the split. */
2580 if (count == 2) {
2581 base_port = local_port;
2582 if (mlxsw_sp->ports[base_port + 1]) {
2583 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2584 return -EINVAL;
2585 }
2586 } else {
2587 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2588 if (mlxsw_sp->ports[base_port + 1] ||
2589 mlxsw_sp->ports[base_port + 3]) {
2590 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2591 return -EINVAL;
2592 }
2593 }
2594
2595 for (i = 0; i < count; i++)
2596 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2597
be94535f
IS		 2598 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2599 if (err) {
2600 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2601 goto err_port_split_create;
18f1e70c
IS		 2602 }
2603
2604 return 0;
2605
be94535f
IS		 2606err_port_split_create:
2607 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2608 return err;
2609}
2610
b2f10571 2611static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 2612{
b2f10571 2613 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2614 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 2615 u8 cur_width, base_port;
18f1e70c
IS		 2616 unsigned int count;
2617 int i;
18f1e70c
IS		 2618
2619 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2620 if (!mlxsw_sp_port) {
2621 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2622 local_port);
2623 return -EINVAL;
2624 }
2625
2626 if (!mlxsw_sp_port->split) {
2627 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2628 return -EINVAL;
2629 }
2630
d664b41e 2631 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 2632 count = cur_width == 1 ? 4 : 2;
2633
2634 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2635
2636 /* Determine which ports to remove. */
2637 if (count == 2 && local_port >= base_port + 2)
2638 base_port = base_port + 2;
2639
2640 for (i = 0; i < count; i++)
2641 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2642
be94535f 2643 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2644
2645 return 0;
2646}
2647
56ade8fe
JP		 2648static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2649 char *pude_pl, void *priv)
2650{
2651 struct mlxsw_sp *mlxsw_sp = priv;
2652 struct mlxsw_sp_port *mlxsw_sp_port;
2653 enum mlxsw_reg_pude_oper_status status;
2654 u8 local_port;
2655
2656 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2657 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 2658 if (!mlxsw_sp_port)
56ade8fe 2659 return;
56ade8fe
JP		 2660
2661 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2662 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2663 netdev_info(mlxsw_sp_port->dev, "link up\n");
2664 netif_carrier_on(mlxsw_sp_port->dev);
2665 } else {
2666 netdev_info(mlxsw_sp_port->dev, "link down\n");
2667 netif_carrier_off(mlxsw_sp_port->dev);
2668 }
2669}
2670
2671static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2672 .func = mlxsw_sp_pude_event_func,
2673 .trap_id = MLXSW_TRAP_ID_PUDE,
2674};
2675
2676static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2677 enum mlxsw_event_trap_id trap_id)
2678{
2679 struct mlxsw_event_listener *el;
2680 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2681 int err;
2682
2683 switch (trap_id) {
2684 case MLXSW_TRAP_ID_PUDE:
2685 el = &mlxsw_sp_pude_event;
2686 break;
2687 }
2688 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2689 if (err)
2690 return err;
2691
2692 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2693 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2694 if (err)
2695 goto err_event_trap_set;
2696
2697 return 0;
2698
2699err_event_trap_set:
2700 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2701 return err;
2702}
2703
2704static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2705 enum mlxsw_event_trap_id trap_id)
2706{
2707 struct mlxsw_event_listener *el;
2708
2709 switch (trap_id) {
2710 case MLXSW_TRAP_ID_PUDE:
2711 el = &mlxsw_sp_pude_event;
2712 break;
2713 }
2714 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2715}
2716
2717static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2718 void *priv)
2719{
2720 struct mlxsw_sp *mlxsw_sp = priv;
2721 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2722 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2723
2724 if (unlikely(!mlxsw_sp_port)) {
2725 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2726 local_port);
2727 return;
2728 }
2729
2730 skb->dev = mlxsw_sp_port->dev;
2731
2732 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2733 u64_stats_update_begin(&pcpu_stats->syncp);
2734 pcpu_stats->rx_packets++;
2735 pcpu_stats->rx_bytes += skb->len;
2736 u64_stats_update_end(&pcpu_stats->syncp);
2737
2738 skb->protocol = eth_type_trans(skb, skb->dev);
2739 netif_receive_skb(skb);
2740}
2741
1c6c6d22
IS		 2742static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2743 void *priv)
2744{
2745 skb->offload_fwd_mark = 1;
2746 return mlxsw_sp_rx_listener_func(skb, local_port, priv);
2747}
2748
63a81141
IS		 2749#define MLXSW_SP_RXL(_func, _trap_id, _action) \
2750 { \
2751 .func = _func, \
2752 .local_port = MLXSW_PORT_DONT_CARE, \
2753 .trap_id = MLXSW_TRAP_ID_##_trap_id, \
2754 .action = MLXSW_REG_HPKT_ACTION_##_action, \
93393b33
IS		 2755 }
2756
56ade8fe 2757static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
63a81141 2758 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, FDB_MC, TRAP_TO_CPU),
56ade8fe 2759 /* Traps for specific L2 packet types, not trapped as FDB MC */
63a81141
IS		 2760 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, STP, TRAP_TO_CPU),
2761 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, LACP, TRAP_TO_CPU),
2762 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, EAPOL, TRAP_TO_CPU),
2763 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, LLDP, TRAP_TO_CPU),
2764 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, MMRP, TRAP_TO_CPU),
2765 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, MVRP, TRAP_TO_CPU),
2766 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, RPVST, TRAP_TO_CPU),
1c6c6d22
IS		 2767 MLXSW_SP_RXL(mlxsw_sp_rx_listener_mark_func, DHCP, MIRROR_TO_CPU),
2768 MLXSW_SP_RXL(mlxsw_sp_rx_listener_mark_func, IGMP_QUERY, MIRROR_TO_CPU),
63a81141
IS		 2769 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, IGMP_V1_REPORT, TRAP_TO_CPU),
2770 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, IGMP_V2_REPORT, TRAP_TO_CPU),
2771 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, IGMP_V2_LEAVE, TRAP_TO_CPU),
2772 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, IGMP_V3_REPORT, TRAP_TO_CPU),
1c6c6d22
IS		 2773 MLXSW_SP_RXL(mlxsw_sp_rx_listener_mark_func, ARPBC, MIRROR_TO_CPU),
2774 MLXSW_SP_RXL(mlxsw_sp_rx_listener_mark_func, ARPUC, MIRROR_TO_CPU),
93393b33 2775 /* L3 traps */
63a81141
IS		 2776 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, MTUERROR, TRAP_TO_CPU),
2777 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, TTLERROR, TRAP_TO_CPU),
2778 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, LBERROR, TRAP_TO_CPU),
1c6c6d22 2779 MLXSW_SP_RXL(mlxsw_sp_rx_listener_mark_func, OSPF, TRAP_TO_CPU),
63a81141
IS		 2780 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, IP2ME, TRAP_TO_CPU),
2781 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, RTR_INGRESS0, TRAP_TO_CPU),
2782 MLXSW_SP_RXL(mlxsw_sp_rx_listener_func, HOST_MISS_IPV4, TRAP_TO_CPU),
56ade8fe
JP		 2783};
2784
2785static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2786{
2787 char htgt_pl[MLXSW_REG_HTGT_LEN];
2788 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2789 int i;
2790 int err;
2791
2792 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2793 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2794 if (err)
2795 return err;
2796
2797 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2798 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2799 if (err)
2800 return err;
2801
2802 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2803 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2804 &mlxsw_sp_rx_listener[i],
2805 mlxsw_sp);
2806 if (err)
2807 goto err_rx_listener_register;
2808
63a81141 2809 mlxsw_reg_hpkt_pack(hpkt_pl, mlxsw_sp_rx_listener[i].action,
56ade8fe
JP		 2810 mlxsw_sp_rx_listener[i].trap_id);
2811 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2812 if (err)
2813 goto err_rx_trap_set;
2814 }
2815 return 0;
2816
2817err_rx_trap_set:
2818 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2819 &mlxsw_sp_rx_listener[i],
2820 mlxsw_sp);
2821err_rx_listener_register:
2822 for (i--; i >= 0; i--) {
10f00aa1 2823 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_DISCARD,
56ade8fe
JP		 2824 mlxsw_sp_rx_listener[i].trap_id);
2825 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2826
2827 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2828 &mlxsw_sp_rx_listener[i],
2829 mlxsw_sp);
2830 }
2831 return err;
2832}
2833
2834static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2835{
2836 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2837 int i;
2838
2839 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
10f00aa1 2840 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_DISCARD,
56ade8fe
JP		 2841 mlxsw_sp_rx_listener[i].trap_id);
2842 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2843
2844 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2845 &mlxsw_sp_rx_listener[i],
2846 mlxsw_sp);
2847 }
2848}
2849
2850static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2851 enum mlxsw_reg_sfgc_type type,
2852 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2853{
2854 enum mlxsw_flood_table_type table_type;
2855 enum mlxsw_sp_flood_table flood_table;
2856 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2857
19ae6124 2858 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
56ade8fe 2859 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
19ae6124 2860 else
56ade8fe 2861 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
19ae6124
IS		 2862
2863 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2864 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2865 else
2866 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
56ade8fe
JP		 2867
2868 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2869 flood_table);
2870 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2871}
2872
2873static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2874{
2875 int type, err;
2876
56ade8fe
JP		 2877 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2878 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2879 continue;
2880
2881 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2882 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2883 if (err)
2884 return err;
56ade8fe
JP		 2885
2886 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2887 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2888 if (err)
2889 return err;
2890 }
2891
2892 return 0;
2893}
2894
0d65fc13
JP		 2895static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2896{
2897 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 2898 int err;
0d65fc13
JP		 2899
2900 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2901 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2902 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2903 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2904 MLXSW_REG_SLCR_LAG_HASH_SIP |
2905 MLXSW_REG_SLCR_LAG_HASH_DIP |
2906 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2907 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2908 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 2909 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2910 if (err)
2911 return err;
2912
c1a38311
JP		 2913 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
2914 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 2915 return -EIO;
2916
c1a38311 2917 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 2918 sizeof(struct mlxsw_sp_upper),
2919 GFP_KERNEL);
2920 if (!mlxsw_sp->lags)
2921 return -ENOMEM;
2922
2923 return 0;
2924}
2925
2926static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
2927{
2928 kfree(mlxsw_sp->lags);
0d65fc13
JP		 2929}
2930
b2f10571 2931static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 2932 const struct mlxsw_bus_info *mlxsw_bus_info)
2933{
b2f10571 2934 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 2935 int err;
2936
2937 mlxsw_sp->core = mlxsw_core;
2938 mlxsw_sp->bus_info = mlxsw_bus_info;
14d39461 2939 INIT_LIST_HEAD(&mlxsw_sp->fids);
3ba2ebf4 2940 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
3a49b4fd 2941 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
56ade8fe
JP		 2942
2943 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2944 if (err) {
2945 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2946 return err;
2947 }
2948
56ade8fe
JP		 2949 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2950 if (err) {
2951 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
bbf2a475 2952 return err;
56ade8fe
JP		 2953 }
2954
2955 err = mlxsw_sp_traps_init(mlxsw_sp);
2956 if (err) {
2957 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2958 goto err_rx_listener_register;
2959 }
2960
2961 err = mlxsw_sp_flood_init(mlxsw_sp);
2962 if (err) {
2963 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2964 goto err_flood_init;
2965 }
2966
2967 err = mlxsw_sp_buffers_init(mlxsw_sp);
2968 if (err) {
2969 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2970 goto err_buffers_init;
2971 }
2972
0d65fc13
JP		 2973 err = mlxsw_sp_lag_init(mlxsw_sp);
2974 if (err) {
2975 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2976 goto err_lag_init;
2977 }
2978
56ade8fe
JP		 2979 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2980 if (err) {
2981 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2982 goto err_switchdev_init;
2983 }
2984
464dce18
IS		 2985 err = mlxsw_sp_router_init(mlxsw_sp);
2986 if (err) {
2987 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
2988 goto err_router_init;
2989 }
2990
763b4b70
YG		 2991 err = mlxsw_sp_span_init(mlxsw_sp);
2992 if (err) {
2993 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
2994 goto err_span_init;
2995 }
2996
bbf2a475
IS		 2997 err = mlxsw_sp_ports_create(mlxsw_sp);
2998 if (err) {
2999 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3000 goto err_ports_create;
3001 }
3002
56ade8fe
JP		 3003 return 0;
3004
bbf2a475 3005err_ports_create:
763b4b70
YG		 3006 mlxsw_sp_span_fini(mlxsw_sp);
3007err_span_init:
464dce18
IS		 3008 mlxsw_sp_router_fini(mlxsw_sp);
3009err_router_init:
bbf2a475 3010 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 3011err_switchdev_init:
ce0bd2b0 3012 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 3013err_lag_init:
0f433fa0 3014 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 3015err_buffers_init:
3016err_flood_init:
3017 mlxsw_sp_traps_fini(mlxsw_sp);
3018err_rx_listener_register:
3019 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
56ade8fe
JP		 3020 return err;
3021}
3022
b2f10571 3023static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 3024{
b2f10571 3025 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 3026
bbf2a475 3027 mlxsw_sp_ports_remove(mlxsw_sp);
763b4b70 3028 mlxsw_sp_span_fini(mlxsw_sp);
464dce18 3029 mlxsw_sp_router_fini(mlxsw_sp);
56ade8fe 3030 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 3031 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 3032 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 3033 mlxsw_sp_traps_fini(mlxsw_sp);
3034 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
3ba2ebf4 3035 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
14d39461 3036 WARN_ON(!list_empty(&mlxsw_sp->fids));
56ade8fe
JP		 3037}
3038
3039static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3040 .used_max_vepa_channels = 1,
3041 .max_vepa_channels = 0,
56ade8fe 3042 .used_max_mid = 1,
53ae6283 3043 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 3044 .used_max_pgt = 1,
3045 .max_pgt = 0,
56ade8fe
JP		 3046 .used_flood_tables = 1,
3047 .used_flood_mode = 1,
3048 .flood_mode = 3,
3049 .max_fid_offset_flood_tables = 2,
3050 .fid_offset_flood_table_size = VLAN_N_VID - 1,
19ae6124
IS		 3051 .max_fid_flood_tables = 2,
3052 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
56ade8fe
JP		 3053 .used_max_ib_mc = 1,
3054 .max_ib_mc = 0,
3055 .used_max_pkey = 1,
3056 .max_pkey = 0,
403547d3
NF		 3057 .used_kvd_split_data = 1,
3058 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3059 .kvd_hash_single_parts = 2,
3060 .kvd_hash_double_parts = 1,
c6022427 3061 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 3062 .swid_config = {
3063 {
3064 .used_type = 1,
3065 .type = MLXSW_PORT_SWID_TYPE_ETH,
3066 }
3067 },
57d316ba 3068 .resource_query_enable = 1,
56ade8fe
JP		 3069};
3070
3071static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 3072 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 3073 .priv_size = sizeof(struct mlxsw_sp),
3074 .init = mlxsw_sp_init,
3075 .fini = mlxsw_sp_fini,
3076 .port_split = mlxsw_sp_port_split,
3077 .port_unsplit = mlxsw_sp_port_unsplit,
3078 .sb_pool_get = mlxsw_sp_sb_pool_get,
3079 .sb_pool_set = mlxsw_sp_sb_pool_set,
3080 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3081 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3082 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3083 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3084 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3085 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3086 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3087 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3088 .txhdr_construct = mlxsw_sp_txhdr_construct,
3089 .txhdr_len = MLXSW_TXHDR_LEN,
3090 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 3091};
3092
7ce856aa
JP		 3093static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3094{
3095 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3096}
3097
dd82364c
DA		 3098static int mlxsw_lower_dev_walk(struct net_device *lower_dev, void *data)
3099{
3100 struct mlxsw_sp_port **port = data;
3101 int ret = 0;
3102
3103 if (mlxsw_sp_port_dev_check(lower_dev)) {
3104 *port = netdev_priv(lower_dev);
3105 ret = 1;
3106 }
3107
3108 return ret;
3109}
3110
7ce856aa
JP		 3111static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3112{
dd82364c 3113 struct mlxsw_sp_port *port;
7ce856aa
JP		 3114
3115 if (mlxsw_sp_port_dev_check(dev))
3116 return netdev_priv(dev);
3117
dd82364c
DA		 3118 port = NULL;
3119 netdev_walk_all_lower_dev(dev, mlxsw_lower_dev_walk, &port);
3120
3121 return port;
7ce856aa
JP		 3122}
3123
3124static struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
3125{
3126 struct mlxsw_sp_port *mlxsw_sp_port;
3127
3128 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3129 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3130}
3131
3132static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3133{
dd82364c 3134 struct mlxsw_sp_port *port;
7ce856aa
JP		 3135
3136 if (mlxsw_sp_port_dev_check(dev))
3137 return netdev_priv(dev);
3138
dd82364c
DA		 3139 port = NULL;
3140 netdev_walk_all_lower_dev_rcu(dev, mlxsw_lower_dev_walk, &port);
3141
3142 return port;
7ce856aa
JP		 3143}
3144
3145struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3146{
3147 struct mlxsw_sp_port *mlxsw_sp_port;
3148
3149 rcu_read_lock();
3150 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3151 if (mlxsw_sp_port)
3152 dev_hold(mlxsw_sp_port->dev);
3153 rcu_read_unlock();
3154 return mlxsw_sp_port;
3155}
3156
3157void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3158{
3159 dev_put(mlxsw_sp_port->dev);
3160}
3161
99724c18
IS		 3162static bool mlxsw_sp_rif_should_config(struct mlxsw_sp_rif *r,
3163 unsigned long event)
3164{
3165 switch (event) {
3166 case NETDEV_UP:
3167 if (!r)
3168 return true;
3169 r->ref_count++;
3170 return false;
3171 case NETDEV_DOWN:
3172 if (r && --r->ref_count == 0)
3173 return true;
3174 /* It is possible we already removed the RIF ourselves
3175 * if it was assigned to a netdev that is now a bridge
3176 * or LAG slave.
3177 */
3178 return false;
3179 }
3180
3181 return false;
3182}
3183
3184static int mlxsw_sp_avail_rif_get(struct mlxsw_sp *mlxsw_sp)
3185{
3186 int i;
3187
c1a38311 3188 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
99724c18
IS		 3189 if (!mlxsw_sp->rifs[i])
3190 return i;
3191
8f8a62d4 3192 return MLXSW_SP_INVALID_RIF;
99724c18
IS		 3193}
3194
3195static void mlxsw_sp_vport_rif_sp_attr_get(struct mlxsw_sp_port *mlxsw_sp_vport,
3196 bool *p_lagged, u16 *p_system_port)
3197{
3198 u8 local_port = mlxsw_sp_vport->local_port;
3199
3200 *p_lagged = mlxsw_sp_vport->lagged;
3201 *p_system_port = *p_lagged ? mlxsw_sp_vport->lag_id : local_port;
3202}
3203
3204static int mlxsw_sp_vport_rif_sp_op(struct mlxsw_sp_port *mlxsw_sp_vport,
3205 struct net_device *l3_dev, u16 rif,
3206 bool create)
3207{
3208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3209 bool lagged = mlxsw_sp_vport->lagged;
3210 char ritr_pl[MLXSW_REG_RITR_LEN];
3211 u16 system_port;
3212
3213 mlxsw_reg_ritr_pack(ritr_pl, create, MLXSW_REG_RITR_SP_IF, rif,
3214 l3_dev->mtu, l3_dev->dev_addr);
3215
3216 mlxsw_sp_vport_rif_sp_attr_get(mlxsw_sp_vport, &lagged, &system_port);
3217 mlxsw_reg_ritr_sp_if_pack(ritr_pl, lagged, system_port,
3218 mlxsw_sp_vport_vid_get(mlxsw_sp_vport));
3219
3220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3221}
3222
3223static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3224
3225static struct mlxsw_sp_fid *
3226mlxsw_sp_rfid_alloc(u16 fid, struct net_device *l3_dev)
3227{
3228 struct mlxsw_sp_fid *f;
3229
3230 f = kzalloc(sizeof(*f), GFP_KERNEL);
3231 if (!f)
3232 return NULL;
3233
3234 f->leave = mlxsw_sp_vport_rif_sp_leave;
3235 f->ref_count = 0;
3236 f->dev = l3_dev;
3237 f->fid = fid;
3238
3239 return f;
3240}
3241
3242static struct mlxsw_sp_rif *
3243mlxsw_sp_rif_alloc(u16 rif, struct net_device *l3_dev, struct mlxsw_sp_fid *f)
3244{
3245 struct mlxsw_sp_rif *r;
3246
3247 r = kzalloc(sizeof(*r), GFP_KERNEL);
3248 if (!r)
3249 return NULL;
3250
3251 ether_addr_copy(r->addr, l3_dev->dev_addr);
3252 r->mtu = l3_dev->mtu;
3253 r->ref_count = 1;
3254 r->dev = l3_dev;
3255 r->rif = rif;
3256 r->f = f;
3257
3258 return r;
3259}
3260
3261static struct mlxsw_sp_rif *
3262mlxsw_sp_vport_rif_sp_create(struct mlxsw_sp_port *mlxsw_sp_vport,
3263 struct net_device *l3_dev)
3264{
3265 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3266 struct mlxsw_sp_fid *f;
3267 struct mlxsw_sp_rif *r;
3268 u16 fid, rif;
3269 int err;
3270
3271 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
8f8a62d4 3272 if (rif == MLXSW_SP_INVALID_RIF)
99724c18
IS		 3273 return ERR_PTR(-ERANGE);
3274
3275 err = mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, true);
3276 if (err)
3277 return ERR_PTR(err);
3278
3279 fid = mlxsw_sp_rif_sp_to_fid(rif);
3280 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, true);
3281 if (err)
3282 goto err_rif_fdb_op;
3283
3284 f = mlxsw_sp_rfid_alloc(fid, l3_dev);
3285 if (!f) {
3286 err = -ENOMEM;
3287 goto err_rfid_alloc;
3288 }
3289
3290 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3291 if (!r) {
3292 err = -ENOMEM;
3293 goto err_rif_alloc;
3294 }
3295
3296 f->r = r;
3297 mlxsw_sp->rifs[rif] = r;
3298
3299 return r;
3300
3301err_rif_alloc:
3302 kfree(f);
3303err_rfid_alloc:
3304 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3305err_rif_fdb_op:
3306 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3307 return ERR_PTR(err);
3308}
3309
3310static void mlxsw_sp_vport_rif_sp_destroy(struct mlxsw_sp_port *mlxsw_sp_vport,
3311 struct mlxsw_sp_rif *r)
3312{
3313 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3314 struct net_device *l3_dev = r->dev;
3315 struct mlxsw_sp_fid *f = r->f;
3316 u16 fid = f->fid;
3317 u16 rif = r->rif;
3318
3319 mlxsw_sp->rifs[rif] = NULL;
3320 f->r = NULL;
3321
3322 kfree(r);
3323
3324 kfree(f);
3325
3326 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3327
3328 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3329}
3330
3331static int mlxsw_sp_vport_rif_sp_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3332 struct net_device *l3_dev)
3333{
3334 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3335 struct mlxsw_sp_rif *r;
3336
3337 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, l3_dev);
3338 if (!r) {
3339 r = mlxsw_sp_vport_rif_sp_create(mlxsw_sp_vport, l3_dev);
3340 if (IS_ERR(r))
3341 return PTR_ERR(r);
3342 }
3343
3344 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, r->f);
3345 r->f->ref_count++;
3346
3347 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", r->f->fid);
3348
3349 return 0;
3350}
3351
3352static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3353{
3354 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3355
3356 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3357
3358 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
3359 if (--f->ref_count == 0)
3360 mlxsw_sp_vport_rif_sp_destroy(mlxsw_sp_vport, f->r);
3361}
3362
3363static int mlxsw_sp_inetaddr_vport_event(struct net_device *l3_dev,
3364 struct net_device *port_dev,
3365 unsigned long event, u16 vid)
3366{
3367 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(port_dev);
3368 struct mlxsw_sp_port *mlxsw_sp_vport;
3369
3370 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3371 if (WARN_ON(!mlxsw_sp_vport))
3372 return -EINVAL;
3373
3374 switch (event) {
3375 case NETDEV_UP:
3376 return mlxsw_sp_vport_rif_sp_join(mlxsw_sp_vport, l3_dev);
3377 case NETDEV_DOWN:
3378 mlxsw_sp_vport_rif_sp_leave(mlxsw_sp_vport);
3379 break;
3380 }
3381
3382 return 0;
3383}
3384
3385static int mlxsw_sp_inetaddr_port_event(struct net_device *port_dev,
3386 unsigned long event)
3387{
3388 if (netif_is_bridge_port(port_dev) || netif_is_lag_port(port_dev))
3389 return 0;
3390
3391 return mlxsw_sp_inetaddr_vport_event(port_dev, port_dev, event, 1);
3392}
3393
3394static int __mlxsw_sp_inetaddr_lag_event(struct net_device *l3_dev,
3395 struct net_device *lag_dev,
3396 unsigned long event, u16 vid)
3397{
3398 struct net_device *port_dev;
3399 struct list_head *iter;
3400 int err;
3401
3402 netdev_for_each_lower_dev(lag_dev, port_dev, iter) {
3403 if (mlxsw_sp_port_dev_check(port_dev)) {
3404 err = mlxsw_sp_inetaddr_vport_event(l3_dev, port_dev,
3405 event, vid);
3406 if (err)
3407 return err;
3408 }
3409 }
3410
3411 return 0;
3412}
3413
3414static int mlxsw_sp_inetaddr_lag_event(struct net_device *lag_dev,
3415 unsigned long event)
3416{
3417 if (netif_is_bridge_port(lag_dev))
3418 return 0;
3419
3420 return __mlxsw_sp_inetaddr_lag_event(lag_dev, lag_dev, event, 1);
3421}
3422
99f44bb3
IS		 3423static struct mlxsw_sp_fid *mlxsw_sp_bridge_fid_get(struct mlxsw_sp *mlxsw_sp,
3424 struct net_device *l3_dev)
3425{
3426 u16 fid;
3427
3428 if (is_vlan_dev(l3_dev))
3429 fid = vlan_dev_vlan_id(l3_dev);
3430 else if (mlxsw_sp->master_bridge.dev == l3_dev)
3431 fid = 1;
3432 else
3433 return mlxsw_sp_vfid_find(mlxsw_sp, l3_dev);
3434
3435 return mlxsw_sp_fid_find(mlxsw_sp, fid);
3436}
3437
f888f587
IS		 3438static enum mlxsw_flood_table_type mlxsw_sp_flood_table_type_get(u16 fid)
3439{
3440 return mlxsw_sp_fid_is_vfid(fid) ? MLXSW_REG_SFGC_TABLE_TYPE_FID :
3441 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
3442}
3443
3444static u16 mlxsw_sp_flood_table_index_get(u16 fid)
3445{
3446 return mlxsw_sp_fid_is_vfid(fid) ? mlxsw_sp_fid_to_vfid(fid) : fid;
3447}
3448
3449static int mlxsw_sp_router_port_flood_set(struct mlxsw_sp *mlxsw_sp, u16 fid,
3450 bool set)
3451{
3452 enum mlxsw_flood_table_type table_type;
3453 char *sftr_pl;
3454 u16 index;
3455 int err;
3456
3457 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
3458 if (!sftr_pl)
3459 return -ENOMEM;
3460
3461 table_type = mlxsw_sp_flood_table_type_get(fid);
3462 index = mlxsw_sp_flood_table_index_get(fid);
3463 mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, index, table_type,
3464 1, MLXSW_PORT_ROUTER_PORT, set);
3465 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl);
3466
3467 kfree(sftr_pl);
3468 return err;
3469}
3470
99f44bb3
IS		 3471static enum mlxsw_reg_ritr_if_type mlxsw_sp_rif_type_get(u16 fid)
3472{
3473 if (mlxsw_sp_fid_is_vfid(fid))
3474 return MLXSW_REG_RITR_FID_IF;
3475 else
3476 return MLXSW_REG_RITR_VLAN_IF;
3477}
3478
3479static int mlxsw_sp_rif_bridge_op(struct mlxsw_sp *mlxsw_sp,
3480 struct net_device *l3_dev,
3481 u16 fid, u16 rif,
3482 bool create)
3483{
3484 enum mlxsw_reg_ritr_if_type rif_type;
3485 char ritr_pl[MLXSW_REG_RITR_LEN];
3486
3487 rif_type = mlxsw_sp_rif_type_get(fid);
3488 mlxsw_reg_ritr_pack(ritr_pl, create, rif_type, rif, l3_dev->mtu,
3489 l3_dev->dev_addr);
3490 mlxsw_reg_ritr_fid_set(ritr_pl, rif_type, fid);
3491
3492 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3493}
3494
3495static int mlxsw_sp_rif_bridge_create(struct mlxsw_sp *mlxsw_sp,
3496 struct net_device *l3_dev,
3497 struct mlxsw_sp_fid *f)
3498{
3499 struct mlxsw_sp_rif *r;
3500 u16 rif;
3501 int err;
3502
3503 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
8f8a62d4 3504 if (rif == MLXSW_SP_INVALID_RIF)
99f44bb3
IS		 3505 return -ERANGE;
3506
f888f587 3507 err = mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, true);
99f44bb3
IS		 3508 if (err)
3509 return err;
3510
f888f587
IS		 3511 err = mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, true);
3512 if (err)
3513 goto err_rif_bridge_op;
3514
99f44bb3
IS		 3515 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, true);
3516 if (err)
3517 goto err_rif_fdb_op;
3518
3519 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3520 if (!r) {
3521 err = -ENOMEM;
3522 goto err_rif_alloc;
3523 }
3524
3525 f->r = r;
3526 mlxsw_sp->rifs[rif] = r;
3527
3528 netdev_dbg(l3_dev, "RIF=%d created\n", rif);
3529
3530 return 0;
3531
3532err_rif_alloc:
3533 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3534err_rif_fdb_op:
3535 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
f888f587
IS		 3536err_rif_bridge_op:
3537 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
99f44bb3
IS		 3538 return err;
3539}
3540
3541void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
3542 struct mlxsw_sp_rif *r)
3543{
3544 struct net_device *l3_dev = r->dev;
3545 struct mlxsw_sp_fid *f = r->f;
3546 u16 rif = r->rif;
3547
3548 mlxsw_sp->rifs[rif] = NULL;
3549 f->r = NULL;
3550
3551 kfree(r);
3552
3553 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3554
3555 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
3556
f888f587
IS		 3557 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
3558
99f44bb3
IS		 3559 netdev_dbg(l3_dev, "RIF=%d destroyed\n", rif);
3560}
3561
3562static int mlxsw_sp_inetaddr_bridge_event(struct net_device *l3_dev,
3563 struct net_device *br_dev,
3564 unsigned long event)
3565{
3566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(l3_dev);
3567 struct mlxsw_sp_fid *f;
3568
3569 /* FID can either be an actual FID if the L3 device is the
3570 * VLAN-aware bridge or a VLAN device on top. Otherwise, the
3571 * L3 device is a VLAN-unaware bridge and we get a vFID.
3572 */
3573 f = mlxsw_sp_bridge_fid_get(mlxsw_sp, l3_dev);
3574 if (WARN_ON(!f))
3575 return -EINVAL;
3576
3577 switch (event) {
3578 case NETDEV_UP:
3579 return mlxsw_sp_rif_bridge_create(mlxsw_sp, l3_dev, f);
3580 case NETDEV_DOWN:
3581 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
3582 break;
3583 }
3584
3585 return 0;
3586}
3587
99724c18
IS		 3588static int mlxsw_sp_inetaddr_vlan_event(struct net_device *vlan_dev,
3589 unsigned long event)
3590{
3591 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
99f44bb3 3592 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
99724c18
IS		 3593 u16 vid = vlan_dev_vlan_id(vlan_dev);
3594
3595 if (mlxsw_sp_port_dev_check(real_dev))
3596 return mlxsw_sp_inetaddr_vport_event(vlan_dev, real_dev, event,
3597 vid);
3598 else if (netif_is_lag_master(real_dev))
3599 return __mlxsw_sp_inetaddr_lag_event(vlan_dev, real_dev, event,
3600 vid);
99f44bb3
IS		 3601 else if (netif_is_bridge_master(real_dev) &&
3602 mlxsw_sp->master_bridge.dev == real_dev)
3603 return mlxsw_sp_inetaddr_bridge_event(vlan_dev, real_dev,
3604 event);
99724c18
IS		 3605
3606 return 0;
3607}
3608
3609static int mlxsw_sp_inetaddr_event(struct notifier_block *unused,
3610 unsigned long event, void *ptr)
3611{
3612 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
3613 struct net_device *dev = ifa->ifa_dev->dev;
3614 struct mlxsw_sp *mlxsw_sp;
3615 struct mlxsw_sp_rif *r;
3616 int err = 0;
3617
3618 mlxsw_sp = mlxsw_sp_lower_get(dev);
3619 if (!mlxsw_sp)
3620 goto out;
3621
3622 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3623 if (!mlxsw_sp_rif_should_config(r, event))
3624 goto out;
3625
3626 if (mlxsw_sp_port_dev_check(dev))
3627 err = mlxsw_sp_inetaddr_port_event(dev, event);
3628 else if (netif_is_lag_master(dev))
3629 err = mlxsw_sp_inetaddr_lag_event(dev, event);
99f44bb3
IS		 3630 else if (netif_is_bridge_master(dev))
3631 err = mlxsw_sp_inetaddr_bridge_event(dev, dev, event);
99724c18
IS		 3632 else if (is_vlan_dev(dev))
3633 err = mlxsw_sp_inetaddr_vlan_event(dev, event);
3634
3635out:
3636 return notifier_from_errno(err);
3637}
3638
6e095fd4
IS		 3639static int mlxsw_sp_rif_edit(struct mlxsw_sp *mlxsw_sp, u16 rif,
3640 const char *mac, int mtu)
3641{
3642 char ritr_pl[MLXSW_REG_RITR_LEN];
3643 int err;
3644
3645 mlxsw_reg_ritr_rif_pack(ritr_pl, rif);
3646 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3647 if (err)
3648 return err;
3649
3650 mlxsw_reg_ritr_mtu_set(ritr_pl, mtu);
3651 mlxsw_reg_ritr_if_mac_memcpy_to(ritr_pl, mac);
3652 mlxsw_reg_ritr_op_set(ritr_pl, MLXSW_REG_RITR_RIF_CREATE);
3653 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3654}
3655
3656static int mlxsw_sp_netdevice_router_port_event(struct net_device *dev)
3657{
3658 struct mlxsw_sp *mlxsw_sp;
3659 struct mlxsw_sp_rif *r;
3660 int err;
3661
3662 mlxsw_sp = mlxsw_sp_lower_get(dev);
3663 if (!mlxsw_sp)
3664 return 0;
3665
3666 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3667 if (!r)
3668 return 0;
3669
3670 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, false);
3671 if (err)
3672 return err;
3673
3674 err = mlxsw_sp_rif_edit(mlxsw_sp, r->rif, dev->dev_addr, dev->mtu);
3675 if (err)
3676 goto err_rif_edit;
3677
3678 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, dev->dev_addr, r->f->fid, true);
3679 if (err)
3680 goto err_rif_fdb_op;
3681
3682 ether_addr_copy(r->addr, dev->dev_addr);
3683 r->mtu = dev->mtu;
3684
3685 netdev_dbg(dev, "Updated RIF=%d\n", r->rif);
3686
3687 return 0;
3688
3689err_rif_fdb_op:
3690 mlxsw_sp_rif_edit(mlxsw_sp, r->rif, r->addr, r->mtu);
3691err_rif_edit:
3692 mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, true);
3693 return err;
3694}
3695
fe3f6d14
IS		 3696static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3697 u16 fid)
3698{
3699 if (mlxsw_sp_fid_is_vfid(fid))
3700 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3701 else
3702 return test_bit(fid, lag_port->active_vlans);
3703}
3704
3705static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3706 u16 fid)
039c49a6
IS		 3707{
3708 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
fe3f6d14
IS		 3709 u8 local_port = mlxsw_sp_port->local_port;
3710 u16 lag_id = mlxsw_sp_port->lag_id;
c1a38311 3711 u64 max_lag_members;
fe3f6d14 3712 int i, count = 0;
039c49a6 3713
fe3f6d14
IS		 3714 if (!mlxsw_sp_port->lagged)
3715 return true;
039c49a6 3716
c1a38311
JP		 3717 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3718 MAX_LAG_MEMBERS);
3719 for (i = 0; i < max_lag_members; i++) {
fe3f6d14
IS		 3720 struct mlxsw_sp_port *lag_port;
3721
3722 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3723 if (!lag_port || lag_port->local_port == local_port)
3724 continue;
3725 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3726 count++;
3727 }
3728
3729 return !count;
039c49a6
IS		 3730}
3731
3732static int
3733mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3734 u16 fid)
3735{
3736 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3737 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3738
3739 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3740 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3741 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3742 mlxsw_sp_port->local_port);
3743
22305378
IS		 3744 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3745 mlxsw_sp_port->local_port, fid);
3746
039c49a6
IS		 3747 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3748}
3749
039c49a6
IS		 3750static int
3751mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3752 u16 fid)
3753{
3754 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3755 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3756
3757 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3758 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3759 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3760
22305378
IS		 3761 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3762 mlxsw_sp_port->lag_id, fid);
3763
039c49a6
IS		 3764 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3765}
3766
fe3f6d14 3767int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
039c49a6 3768{
fe3f6d14
IS		 3769 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3770 return 0;
039c49a6 3771
fe3f6d14
IS		 3772 if (mlxsw_sp_port->lagged)
3773 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
039c49a6
IS		 3774 fid);
3775 else
fe3f6d14 3776 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
039c49a6
IS		 3777}
3778
701b186e
IS		 3779static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3780{
3781 struct mlxsw_sp_fid *f, *tmp;
3782
3783 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3784 if (--f->ref_count == 0)
3785 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3786 else
3787 WARN_ON_ONCE(1);
3788}
3789
7117a570
IS		 3790static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3791 struct net_device *br_dev)
3792{
3793 return !mlxsw_sp->master_bridge.dev ||
3794 mlxsw_sp->master_bridge.dev == br_dev;
3795}
3796
3797static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3798 struct net_device *br_dev)
3799{
3800 mlxsw_sp->master_bridge.dev = br_dev;
3801 mlxsw_sp->master_bridge.ref_count++;
3802}
3803
3804static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3805{
701b186e 3806 if (--mlxsw_sp->master_bridge.ref_count == 0) {
7117a570 3807 mlxsw_sp->master_bridge.dev = NULL;
701b186e
IS		 3808 /* It's possible upper VLAN devices are still holding
3809 * references to underlying FIDs. Drop the reference
3810 * and release the resources if it was the last one.
3811 * If it wasn't, then something bad happened.
3812 */
3813 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3814 }
7117a570
IS		 3815}
3816
3817static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3818 struct net_device *br_dev)
56ade8fe
JP		 3819{
3820 struct net_device *dev = mlxsw_sp_port->dev;
3821 int err;
3822
3823 /* When port is not bridged untagged packets are tagged with
3824 * PVID=VID=1, thereby creating an implicit VLAN interface in
3825 * the device. Remove it and let bridge code take care of its
3826 * own VLANs.
3827 */
3828 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
6c72a3d0
IS		 3829 if (err)
3830 return err;
56ade8fe 3831
7117a570
IS		 3832 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3833
6c72a3d0
IS		 3834 mlxsw_sp_port->learning = 1;
3835 mlxsw_sp_port->learning_sync = 1;
3836 mlxsw_sp_port->uc_flood = 1;
3837 mlxsw_sp_port->bridged = 1;
3838
3839 return 0;
56ade8fe
JP		 3840}
3841
fe3f6d14 3842static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
56ade8fe
JP		 3843{
3844 struct net_device *dev = mlxsw_sp_port->dev;
5a8f4525 3845
28a01d2d
IS		 3846 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3847
7117a570
IS		 3848 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3849
6c72a3d0
IS		 3850 mlxsw_sp_port->learning = 0;
3851 mlxsw_sp_port->learning_sync = 0;
3852 mlxsw_sp_port->uc_flood = 0;
5a8f4525 3853 mlxsw_sp_port->bridged = 0;
56ade8fe
JP		 3854
3855 /* Add implicit VLAN interface in the device, so that untagged
3856 * packets will be classified to the default vFID.
3857 */
82e6db03 3858 mlxsw_sp_port_add_vid(dev, 0, 1);
56ade8fe
JP		 3859}
3860
0d65fc13
JP		 3861static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3862{
3863 char sldr_pl[MLXSW_REG_SLDR_LEN];
3864
3865 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3867}
3868
3869static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3870{
3871 char sldr_pl[MLXSW_REG_SLDR_LEN];
3872
3873 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3874 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3875}
3876
3877static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3878 u16 lag_id, u8 port_index)
3879{
3880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3881 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3882
3883 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3884 lag_id, port_index);
3885 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3886}
3887
3888static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3889 u16 lag_id)
3890{
3891 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3892 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3893
3894 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3895 lag_id);
3896 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3897}
3898
3899static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3900 u16 lag_id)
3901{
3902 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3903 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3904
3905 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3906 lag_id);
3907 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3908}
3909
3910static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3911 u16 lag_id)
3912{
3913 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3914 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3915
3916 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3917 lag_id);
3918 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3919}
3920
3921static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3922 struct net_device *lag_dev,
3923 u16 *p_lag_id)
3924{
3925 struct mlxsw_sp_upper *lag;
3926 int free_lag_id = -1;
c1a38311 3927 u64 max_lag;
0d65fc13
JP		 3928 int i;
3929
c1a38311
JP		 3930 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3931 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 3932 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3933 if (lag->ref_count) {
3934 if (lag->dev == lag_dev) {
3935 *p_lag_id = i;
3936 return 0;
3937 }
3938 } else if (free_lag_id < 0) {
3939 free_lag_id = i;
3940 }
3941 }
3942 if (free_lag_id < 0)
3943 return -EBUSY;
3944 *p_lag_id = free_lag_id;
3945 return 0;
3946}
3947
3948static bool
3949mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3950 struct net_device *lag_dev,
3951 struct netdev_lag_upper_info *lag_upper_info)
3952{
3953 u16 lag_id;
3954
3955 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3956 return false;
3957 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3958 return false;
3959 return true;
3960}
3961
3962static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3963 u16 lag_id, u8 *p_port_index)
3964{
c1a38311 3965 u64 max_lag_members;
0d65fc13
JP		 3966 int i;
3967
c1a38311
JP		 3968 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3969 MAX_LAG_MEMBERS);
3970 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 3971 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3972 *p_port_index = i;
3973 return 0;
3974 }
3975 }
3976 return -EBUSY;
3977}
3978
86bf95b3
IS		 3979static void
3980mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3981 u16 lag_id)
3982{
3983 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 3984 struct mlxsw_sp_fid *f;
86bf95b3
IS		 3985
3986 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3987 if (WARN_ON(!mlxsw_sp_vport))
3988 return;
3989
11943ff4
IS		 3990 /* If vPort is assigned a RIF, then leave it since it's no
3991 * longer valid.
3992 */
3993 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3994 if (f)
3995 f->leave(mlxsw_sp_vport);
3996
86bf95b3
IS		 3997 mlxsw_sp_vport->lag_id = lag_id;
3998 mlxsw_sp_vport->lagged = 1;
3999}
4000
4001static void
4002mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4003{
4004 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 4005 struct mlxsw_sp_fid *f;
86bf95b3
IS		 4006
4007 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4008 if (WARN_ON(!mlxsw_sp_vport))
4009 return;
4010
11943ff4
IS		 4011 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4012 if (f)
4013 f->leave(mlxsw_sp_vport);
4014
86bf95b3
IS		 4015 mlxsw_sp_vport->lagged = 0;
4016}
4017
0d65fc13
JP		 4018static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4019 struct net_device *lag_dev)
4020{
4021 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4022 struct mlxsw_sp_upper *lag;
4023 u16 lag_id;
4024 u8 port_index;
4025 int err;
4026
4027 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4028 if (err)
4029 return err;
4030 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4031 if (!lag->ref_count) {
4032 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4033 if (err)
4034 return err;
4035 lag->dev = lag_dev;
4036 }
4037
4038 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4039 if (err)
4040 return err;
4041 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4042 if (err)
4043 goto err_col_port_add;
4044 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4045 if (err)
4046 goto err_col_port_enable;
4047
4048 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4049 mlxsw_sp_port->local_port);
4050 mlxsw_sp_port->lag_id = lag_id;
4051 mlxsw_sp_port->lagged = 1;
4052 lag->ref_count++;
86bf95b3
IS		 4053
4054 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
4055
0d65fc13
JP		 4056 return 0;
4057
51554db2
IS		 4058err_col_port_enable:
4059 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4060err_col_port_add:
4061 if (!lag->ref_count)
4062 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4063 return err;
4064}
4065
82e6db03
IS		 4066static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4067 struct net_device *lag_dev)
0d65fc13
JP		 4068{
4069 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4070 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4071 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4072
4073 if (!mlxsw_sp_port->lagged)
82e6db03 4074 return;
0d65fc13
JP		 4075 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4076 WARN_ON(lag->ref_count == 0);
4077
82e6db03
IS		 4078 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4079 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4080
4dc236c3
IS		 4081 if (mlxsw_sp_port->bridged) {
4082 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
fe3f6d14 4083 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4dc236c3
IS		 4084 }
4085
fe3f6d14 4086 if (lag->ref_count == 1)
82e6db03 4087 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4088
4089 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4090 mlxsw_sp_port->local_port);
4091 mlxsw_sp_port->lagged = 0;
4092 lag->ref_count--;
86bf95b3
IS		 4093
4094 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
0d65fc13
JP		 4095}
4096
74581206
JP		 4097static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4098 u16 lag_id)
4099{
4100 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4101 char sldr_pl[MLXSW_REG_SLDR_LEN];
4102
4103 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4104 mlxsw_sp_port->local_port);
4105 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4106}
4107
4108static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4109 u16 lag_id)
4110{
4111 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4112 char sldr_pl[MLXSW_REG_SLDR_LEN];
4113
4114 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4115 mlxsw_sp_port->local_port);
4116 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4117}
4118
4119static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4120 bool lag_tx_enabled)
4121{
4122 if (lag_tx_enabled)
4123 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4124 mlxsw_sp_port->lag_id);
4125 else
4126 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4127 mlxsw_sp_port->lag_id);
4128}
4129
4130static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4131 struct netdev_lag_lower_state_info *info)
4132{
4133 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4134}
4135
9589a7b5
IS		 4136static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4137 struct net_device *vlan_dev)
4138{
4139 struct mlxsw_sp_port *mlxsw_sp_vport;
4140 u16 vid = vlan_dev_vlan_id(vlan_dev);
4141
4142 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 4143 if (WARN_ON(!mlxsw_sp_vport))
9589a7b5 4144 return -EINVAL;
9589a7b5
IS		 4145
4146 mlxsw_sp_vport->dev = vlan_dev;
4147
4148 return 0;
4149}
4150
82e6db03
IS		 4151static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4152 struct net_device *vlan_dev)
9589a7b5
IS		 4153{
4154 struct mlxsw_sp_port *mlxsw_sp_vport;
4155 u16 vid = vlan_dev_vlan_id(vlan_dev);
4156
4157 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 4158 if (WARN_ON(!mlxsw_sp_vport))
82e6db03 4159 return;
9589a7b5
IS		 4160
4161 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
9589a7b5
IS		 4162}
4163
74581206
JP		 4164static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4165 unsigned long event, void *ptr)
56ade8fe 4166{
56ade8fe
JP		 4167 struct netdev_notifier_changeupper_info *info;
4168 struct mlxsw_sp_port *mlxsw_sp_port;
4169 struct net_device *upper_dev;
4170 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4171 int err = 0;
56ade8fe 4172
56ade8fe
JP		 4173 mlxsw_sp_port = netdev_priv(dev);
4174 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4175 info = ptr;
4176
4177 switch (event) {
4178 case NETDEV_PRECHANGEUPPER:
4179 upper_dev = info->upper_dev;
59fe9b3f
IS		 4180 if (!is_vlan_dev(upper_dev) &&
4181 !netif_is_lag_master(upper_dev) &&
4182 !netif_is_bridge_master(upper_dev))
4183 return -EINVAL;
6ec43904 4184 if (!info->linking)
0d65fc13 4185 break;
56ade8fe 4186 /* HW limitation forbids to put ports to multiple bridges. */
0d65fc13 4187 if (netif_is_bridge_master(upper_dev) &&
56ade8fe 4188 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
80bedf1a 4189 return -EINVAL;
0d65fc13
JP		 4190 if (netif_is_lag_master(upper_dev) &&
4191 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4192 info->upper_info))
80bedf1a 4193 return -EINVAL;
6ec43904
IS		 4194 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4195 return -EINVAL;
4196 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4197 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4198 return -EINVAL;
56ade8fe
JP		 4199 break;
4200 case NETDEV_CHANGEUPPER:
4201 upper_dev = info->upper_dev;
9589a7b5 4202 if (is_vlan_dev(upper_dev)) {
80bedf1a 4203 if (info->linking)
9589a7b5
IS		 4204 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4205 upper_dev);
80bedf1a 4206 else
82e6db03
IS		 4207 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4208 upper_dev);
9589a7b5 4209 } else if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4210 if (info->linking)
4211 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4212 upper_dev);
4213 else
fe3f6d14 4214 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
0d65fc13 4215 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4216 if (info->linking)
0d65fc13
JP		 4217 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4218 upper_dev);
80bedf1a 4219 else
82e6db03
IS		 4220 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4221 upper_dev);
59fe9b3f
IS		 4222 } else {
4223 err = -EINVAL;
4224 WARN_ON(1);
56ade8fe
JP		 4225 }
4226 break;
4227 }
4228
80bedf1a 4229 return err;
56ade8fe
JP		 4230}
4231
74581206
JP		 4232static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4233 unsigned long event, void *ptr)
4234{
4235 struct netdev_notifier_changelowerstate_info *info;
4236 struct mlxsw_sp_port *mlxsw_sp_port;
4237 int err;
4238
4239 mlxsw_sp_port = netdev_priv(dev);
4240 info = ptr;
4241
4242 switch (event) {
4243 case NETDEV_CHANGELOWERSTATE:
4244 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4245 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4246 info->lower_state_info);
4247 if (err)
4248 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4249 }
4250 break;
4251 }
4252
80bedf1a 4253 return 0;
74581206
JP		 4254}
4255
4256static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4257 unsigned long event, void *ptr)
4258{
4259 switch (event) {
4260 case NETDEV_PRECHANGEUPPER:
4261 case NETDEV_CHANGEUPPER:
4262 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4263 case NETDEV_CHANGELOWERSTATE:
4264 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4265 }
4266
80bedf1a 4267 return 0;
74581206
JP		 4268}
4269
0d65fc13
JP		 4270static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4271 unsigned long event, void *ptr)
4272{
4273 struct net_device *dev;
4274 struct list_head *iter;
4275 int ret;
4276
4277 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4278 if (mlxsw_sp_port_dev_check(dev)) {
4279 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
80bedf1a 4280 if (ret)
0d65fc13
JP		 4281 return ret;
4282 }
4283 }
4284
80bedf1a 4285 return 0;
0d65fc13
JP		 4286}
4287
701b186e
IS		 4288static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4289 struct net_device *vlan_dev)
26f0e7fb 4290{
701b186e 4291 u16 fid = vlan_dev_vlan_id(vlan_dev);
d0ec875a 4292 struct mlxsw_sp_fid *f;
26f0e7fb 4293
701b186e
IS		 4294 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4295 if (!f) {
4296 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4297 if (IS_ERR(f))
4298 return PTR_ERR(f);
26f0e7fb
IS		 4299 }
4300
701b186e
IS		 4301 f->ref_count++;
4302
4303 return 0;
4304}
4305
4306static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4307 struct net_device *vlan_dev)
4308{
4309 u16 fid = vlan_dev_vlan_id(vlan_dev);
4310 struct mlxsw_sp_fid *f;
4311
4312 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
99f44bb3
IS		 4313 if (f && f->r)
4314 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
701b186e
IS		 4315 if (f && --f->ref_count == 0)
4316 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4317}
4318
4319static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4320 unsigned long event, void *ptr)
4321{
4322 struct netdev_notifier_changeupper_info *info;
4323 struct net_device *upper_dev;
4324 struct mlxsw_sp *mlxsw_sp;
4325 int err;
4326
4327 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4328 if (!mlxsw_sp)
4329 return 0;
4330 if (br_dev != mlxsw_sp->master_bridge.dev)
4331 return 0;
4332
4333 info = ptr;
4334
4335 switch (event) {
4336 case NETDEV_CHANGEUPPER:
4337 upper_dev = info->upper_dev;
4338 if (!is_vlan_dev(upper_dev))
4339 break;
4340 if (info->linking) {
4341 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4342 upper_dev);
4343 if (err)
4344 return err;
4345 } else {
4346 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp, upper_dev);
4347 }
4348 break;
4349 }
4350
4351 return 0;
26f0e7fb
IS		 4352}
4353
3ba2ebf4 4354static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
26f0e7fb 4355{
3ba2ebf4 4356 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
99724c18 4357 MLXSW_SP_VFID_MAX);
26f0e7fb
IS		 4358}
4359
99724c18 4360static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
26f0e7fb 4361{
99724c18 4362 char sfmr_pl[MLXSW_REG_SFMR_LEN];
26f0e7fb 4363
99724c18
IS		 4364 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4365 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
26f0e7fb
IS		 4366}
4367
3ba2ebf4 4368static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
1c800759 4369
3ba2ebf4
IS		 4370static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4371 struct net_device *br_dev)
26f0e7fb
IS		 4372{
4373 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 4374 struct mlxsw_sp_fid *f;
c7e920b5 4375 u16 vfid, fid;
26f0e7fb
IS		 4376 int err;
4377
3ba2ebf4 4378 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
c7e920b5 4379 if (vfid == MLXSW_SP_VFID_MAX) {
26f0e7fb
IS		 4380 dev_err(dev, "No available vFIDs\n");
4381 return ERR_PTR(-ERANGE);
4382 }
4383
c7e920b5
IS		 4384 fid = mlxsw_sp_vfid_to_fid(vfid);
4385 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
26f0e7fb 4386 if (err) {
c7e920b5 4387 dev_err(dev, "Failed to create FID=%d\n", fid);
26f0e7fb
IS		 4388 return ERR_PTR(err);
4389 }
4390
c7e920b5
IS		 4391 f = kzalloc(sizeof(*f), GFP_KERNEL);
4392 if (!f)
26f0e7fb
IS		 4393 goto err_allocate_vfid;
4394
3ba2ebf4 4395 f->leave = mlxsw_sp_vport_vfid_leave;
d0ec875a
IS		 4396 f->fid = fid;
4397 f->dev = br_dev;
26f0e7fb 4398
3ba2ebf4
IS		 4399 list_add(&f->list, &mlxsw_sp->vfids.list);
4400 set_bit(vfid, mlxsw_sp->vfids.mapped);
26f0e7fb 4401
c7e920b5 4402 return f;
26f0e7fb
IS		 4403
4404err_allocate_vfid:
c7e920b5 4405 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 4406 return ERR_PTR(-ENOMEM);
4407}
4408
3ba2ebf4
IS		 4409static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4410 struct mlxsw_sp_fid *f)
26f0e7fb 4411{
d0ec875a 4412 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
99f44bb3 4413 u16 fid = f->fid;
26f0e7fb 4414
3ba2ebf4 4415 clear_bit(vfid, mlxsw_sp->vfids.mapped);
d0ec875a 4416 list_del(&f->list);
26f0e7fb 4417
99f44bb3
IS		 4418 if (f->r)
4419 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
26f0e7fb 4420
d0ec875a 4421 kfree(f);
99f44bb3
IS		 4422
4423 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 4424}
4425
99724c18
IS		 4426static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4427 bool valid)
4428{
4429 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4430 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4431
4432 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4433 vid);
4434}
4435
3ba2ebf4
IS		 4436static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4437 struct net_device *br_dev)
26f0e7fb 4438{
0355b59f 4439 struct mlxsw_sp_fid *f;
26f0e7fb
IS		 4440 int err;
4441
3ba2ebf4 4442 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
0355b59f 4443 if (!f) {
3ba2ebf4 4444 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
0355b59f
IS		 4445 if (IS_ERR(f))
4446 return PTR_ERR(f);
26f0e7fb
IS		 4447 }
4448
0355b59f
IS		 4449 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4450 if (err)
4451 goto err_vport_flood_set;
26f0e7fb 4452
0355b59f
IS		 4453 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4454 if (err)
9c4d4423 4455 goto err_vport_fid_map;
26f0e7fb 4456
41b996cc 4457 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f 4458 f->ref_count++;
6a9863a6 4459
22305378
IS		 4460 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4461
0355b59f 4462 return 0;
039c49a6 4463
0355b59f
IS		 4464err_vport_fid_map:
4465 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4466err_vport_flood_set:
d0ec875a 4467 if (!f->ref_count)
3ba2ebf4 4468 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
0355b59f
IS		 4469 return err;
4470}
26f0e7fb 4471
3ba2ebf4 4472static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f 4473{
41b996cc 4474 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb 4475
22305378
IS		 4476 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4477
0355b59f 4478 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
26f0e7fb 4479
0355b59f
IS		 4480 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4481
fe3f6d14
IS		 4482 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4483
41b996cc 4484 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f 4485 if (--f->ref_count == 0)
3ba2ebf4 4486 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
26f0e7fb
IS		 4487}
4488
4489static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4490 struct net_device *br_dev)
4491{
99724c18 4492 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb
IS		 4493 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4494 struct net_device *dev = mlxsw_sp_vport->dev;
26f0e7fb
IS		 4495 int err;
4496
99724c18
IS		 4497 if (f && !WARN_ON(!f->leave))
4498 f->leave(mlxsw_sp_vport);
26f0e7fb 4499
3ba2ebf4 4500 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
26f0e7fb 4501 if (err) {
0355b59f 4502 netdev_err(dev, "Failed to join vFID\n");
99724c18 4503 return err;
26f0e7fb
IS		 4504 }
4505
4506 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4507 if (err) {
4508 netdev_err(dev, "Failed to enable learning\n");
4509 goto err_port_vid_learning_set;
4510 }
4511
26f0e7fb
IS		 4512 mlxsw_sp_vport->learning = 1;
4513 mlxsw_sp_vport->learning_sync = 1;
4514 mlxsw_sp_vport->uc_flood = 1;
4515 mlxsw_sp_vport->bridged = 1;
4516
4517 return 0;
4518
26f0e7fb 4519err_port_vid_learning_set:
3ba2ebf4 4520 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
26f0e7fb
IS		 4521 return err;
4522}
4523
fe3f6d14 4524static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f
IS		 4525{
4526 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
0355b59f
IS		 4527
4528 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4529
3ba2ebf4 4530 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
0355b59f 4531
0355b59f
IS		 4532 mlxsw_sp_vport->learning = 0;
4533 mlxsw_sp_vport->learning_sync = 0;
4534 mlxsw_sp_vport->uc_flood = 0;
4535 mlxsw_sp_vport->bridged = 0;
4536}
4537
26f0e7fb
IS		 4538static bool
4539mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4540 const struct net_device *br_dev)
4541{
4542 struct mlxsw_sp_port *mlxsw_sp_vport;
4543
4544 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4545 vport.list) {
3ba2ebf4 4546 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
56918b6b
IS		 4547
4548 if (dev && dev == br_dev)
26f0e7fb
IS		 4549 return false;
4550 }
4551
4552 return true;
4553}
4554
4555static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4556 unsigned long event, void *ptr,
4557 u16 vid)
4558{
4559 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4560 struct netdev_notifier_changeupper_info *info = ptr;
4561 struct mlxsw_sp_port *mlxsw_sp_vport;
4562 struct net_device *upper_dev;
80bedf1a 4563 int err = 0;
26f0e7fb
IS		 4564
4565 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4566
4567 switch (event) {
4568 case NETDEV_PRECHANGEUPPER:
4569 upper_dev = info->upper_dev;
26f0e7fb 4570 if (!netif_is_bridge_master(upper_dev))
80bedf1a 4571 return -EINVAL;
ddbe993d
IS		 4572 if (!info->linking)
4573 break;
26f0e7fb
IS		 4574 /* We can't have multiple VLAN interfaces configured on
4575 * the same port and being members in the same bridge.
4576 */
4577 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
4578 upper_dev))
80bedf1a 4579 return -EINVAL;
26f0e7fb
IS		 4580 break;
4581 case NETDEV_CHANGEUPPER:
4582 upper_dev = info->upper_dev;
26f0e7fb 4583 if (info->linking) {
423b937e 4584 if (WARN_ON(!mlxsw_sp_vport))
80bedf1a 4585 return -EINVAL;
26f0e7fb
IS		 4586 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4587 upper_dev);
26f0e7fb 4588 } else {
26f0e7fb 4589 if (!mlxsw_sp_vport)
80bedf1a 4590 return 0;
fe3f6d14 4591 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
26f0e7fb
IS		 4592 }
4593 }
4594
80bedf1a 4595 return err;
26f0e7fb
IS		 4596}
4597
272c4470
IS		 4598static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4599 unsigned long event, void *ptr,
4600 u16 vid)
4601{
4602 struct net_device *dev;
4603 struct list_head *iter;
4604 int ret;
4605
4606 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4607 if (mlxsw_sp_port_dev_check(dev)) {
4608 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4609 vid);
80bedf1a 4610 if (ret)
272c4470
IS		 4611 return ret;
4612 }
4613 }
4614
80bedf1a 4615 return 0;
272c4470
IS		 4616}
4617
26f0e7fb
IS		 4618static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4619 unsigned long event, void *ptr)
4620{
4621 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4622 u16 vid = vlan_dev_vlan_id(vlan_dev);
4623
272c4470
IS		 4624 if (mlxsw_sp_port_dev_check(real_dev))
4625 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4626 vid);
4627 else if (netif_is_lag_master(real_dev))
4628 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4629 vid);
26f0e7fb 4630
80bedf1a 4631 return 0;
26f0e7fb
IS		 4632}
4633
0d65fc13
JP		 4634static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4635 unsigned long event, void *ptr)
4636{
4637 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
80bedf1a 4638 int err = 0;
0d65fc13 4639
6e095fd4
IS		 4640 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4641 err = mlxsw_sp_netdevice_router_port_event(dev);
4642 else if (mlxsw_sp_port_dev_check(dev))
80bedf1a
IS		 4643 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4644 else if (netif_is_lag_master(dev))
4645 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
701b186e
IS		 4646 else if (netif_is_bridge_master(dev))
4647 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
80bedf1a
IS		 4648 else if (is_vlan_dev(dev))
4649 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 4650
80bedf1a 4651 return notifier_from_errno(err);
0d65fc13
JP		 4652}
4653
56ade8fe
JP		 4654static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4655 .notifier_call = mlxsw_sp_netdevice_event,
4656};
4657
99724c18
IS		 4658static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4659 .notifier_call = mlxsw_sp_inetaddr_event,
4660 .priority = 10, /* Must be called before FIB notifier block */
4661};
4662
e7322638
JP		 4663static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4664 .notifier_call = mlxsw_sp_router_netevent_event,
4665};
4666
1d20d23c
JP		 4667static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4668 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4669 {0, },
4670};
4671
4672static struct pci_driver mlxsw_sp_pci_driver = {
4673 .name = mlxsw_sp_driver_name,
4674 .id_table = mlxsw_sp_pci_id_table,
4675};
4676
56ade8fe
JP		 4677static int __init mlxsw_sp_module_init(void)
4678{
4679 int err;
4680
4681 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
99724c18 4682 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
e7322638
JP		 4683 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4684
56ade8fe
JP		 4685 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4686 if (err)
4687 goto err_core_driver_register;
1d20d23c
JP		 4688
4689 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4690 if (err)
4691 goto err_pci_driver_register;
4692
56ade8fe
JP		 4693 return 0;
4694
1d20d23c
JP		 4695err_pci_driver_register:
4696 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 4697err_core_driver_register:
e7322638 4698 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
de7d6295 4699 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4700 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4701 return err;
4702}
4703
4704static void __exit mlxsw_sp_module_exit(void)
4705{
1d20d23c 4706 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 4707 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
e7322638 4708 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
99724c18 4709 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4710 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4711}
4712
4713module_init(mlxsw_sp_module_init);
4714module_exit(mlxsw_sp_module_exit);
4715
4716MODULE_LICENSE("Dual BSD/GPL");
4717MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4718MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 4719MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
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