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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
CommitLineData
56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
22a67766
JP		 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
56ade8fe
JP		 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
56ade8fe 56#include <net/switchdev.h>
763b4b70
YG		 57#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
e7322638 59#include <net/netevent.h>
98d0f7b9 60#include <net/tc_act/tc_sample.h>
5ea1237f 61#include <net/addrconf.h>
56ade8fe
JP		 62
63#include "spectrum.h"
1d20d23c 64#include "pci.h"
56ade8fe
JP		 65#include "core.h"
66#include "reg.h"
67#include "port.h"
68#include "trap.h"
69#include "txheader.h"
ff7b0d27 70#include "spectrum_cnt.h"
230ead01 71#include "spectrum_dpipe.h"
e5e5c88a 72#include "../mlxfw/mlxfw.h"
56ade8fe 73
6b742199
YG		 74#define MLXSW_FWREV_MAJOR 13
75#define MLXSW_FWREV_MINOR 1420
76#define MLXSW_FWREV_SUBMINOR 122
77
78static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
79 .major = MLXSW_FWREV_MAJOR,
80 .minor = MLXSW_FWREV_MINOR,
81 .subminor = MLXSW_FWREV_SUBMINOR
82};
83
84#define MLXSW_SP_FW_FILENAME \
a4e1ce24 85 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
6b742199
YG		 86 "." __stringify(MLXSW_FWREV_MINOR) \
87 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
88
56ade8fe
JP		 89static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
90static const char mlxsw_sp_driver_version[] = "1.0";
91
92/* tx_hdr_version
93 * Tx header version.
94 * Must be set to 1.
95 */
96MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
97
98/* tx_hdr_ctl
99 * Packet control type.
100 * 0 - Ethernet control (e.g. EMADs, LACP)
101 * 1 - Ethernet data
102 */
103MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
104
105/* tx_hdr_proto
106 * Packet protocol type. Must be set to 1 (Ethernet).
107 */
108MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
109
110/* tx_hdr_rx_is_router
111 * Packet is sent from the router. Valid for data packets only.
112 */
113MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
114
115/* tx_hdr_fid_valid
116 * Indicates if the 'fid' field is valid and should be used for
117 * forwarding lookup. Valid for data packets only.
118 */
119MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
120
121/* tx_hdr_swid
122 * Switch partition ID. Must be set to 0.
123 */
124MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
125
126/* tx_hdr_control_tclass
127 * Indicates if the packet should use the control TClass and not one
128 * of the data TClasses.
129 */
130MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
131
132/* tx_hdr_etclass
133 * Egress TClass to be used on the egress device on the egress port.
134 */
135MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
136
137/* tx_hdr_port_mid
138 * Destination local port for unicast packets.
139 * Destination multicast ID for multicast packets.
140 *
141 * Control packets are directed to a specific egress port, while data
142 * packets are transmitted through the CPU port (0) into the switch partition,
143 * where forwarding rules are applied.
144 */
145MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
146
147/* tx_hdr_fid
148 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
149 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
150 * Valid for data packets only.
151 */
152MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
153
154/* tx_hdr_type
155 * 0 - Data packets
156 * 6 - Control packets
157 */
158MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
159
e5e5c88a
YG		 160struct mlxsw_sp_mlxfw_dev {
161 struct mlxfw_dev mlxfw_dev;
162 struct mlxsw_sp *mlxsw_sp;
163};
164
165static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
166 u16 component_index, u32 *p_max_size,
167 u8 *p_align_bits, u16 *p_max_write_size)
168{
169 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
170 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
171 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
172 char mcqi_pl[MLXSW_REG_MCQI_LEN];
173 int err;
174
175 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
176 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
177 if (err)
178 return err;
179 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
180 p_max_write_size);
181
182 *p_align_bits = max_t(u8, *p_align_bits, 2);
183 *p_max_write_size = min_t(u16, *p_max_write_size,
184 MLXSW_REG_MCDA_MAX_DATA_LEN);
185 return 0;
186}
187
188static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
189{
190 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
191 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
192 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
193 char mcc_pl[MLXSW_REG_MCC_LEN];
194 u8 control_state;
195 int err;
196
197 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
198 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
199 if (err)
200 return err;
201
202 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
203 if (control_state != MLXFW_FSM_STATE_IDLE)
204 return -EBUSY;
205
206 mlxsw_reg_mcc_pack(mcc_pl,
207 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
208 0, *fwhandle, 0);
209 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
210}
211
212static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
213 u32 fwhandle, u16 component_index,
214 u32 component_size)
215{
216 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
217 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
218 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
219 char mcc_pl[MLXSW_REG_MCC_LEN];
220
221 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
222 component_index, fwhandle, component_size);
223 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
224}
225
226static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
227 u32 fwhandle, u8 *data, u16 size,
228 u32 offset)
229{
230 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
231 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
233 char mcda_pl[MLXSW_REG_MCDA_LEN];
234
235 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
236 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
237}
238
239static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
240 u32 fwhandle, u16 component_index)
241{
242 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
243 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
244 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
245 char mcc_pl[MLXSW_REG_MCC_LEN];
246
247 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
248 component_index, fwhandle, 0);
249 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
250}
251
252static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
253{
254 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
255 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
256 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
257 char mcc_pl[MLXSW_REG_MCC_LEN];
258
259 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
260 fwhandle, 0);
261 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
262}
263
264static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
265 enum mlxfw_fsm_state *fsm_state,
266 enum mlxfw_fsm_state_err *fsm_state_err)
267{
268 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
269 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
270 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
271 char mcc_pl[MLXSW_REG_MCC_LEN];
272 u8 control_state;
273 u8 error_code;
274 int err;
275
276 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
277 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
278 if (err)
279 return err;
280
281 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
282 *fsm_state = control_state;
283 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
284 MLXFW_FSM_STATE_ERR_MAX);
285 return 0;
286}
287
288static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
289{
290 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
291 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
292 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
293 char mcc_pl[MLXSW_REG_MCC_LEN];
294
295 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
296 fwhandle, 0);
297 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
298}
299
300static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
301{
302 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
303 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
304 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
305 char mcc_pl[MLXSW_REG_MCC_LEN];
306
307 mlxsw_reg_mcc_pack(mcc_pl,
308 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
309 fwhandle, 0);
310 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
311}
312
313static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
314 .component_query = mlxsw_sp_component_query,
315 .fsm_lock = mlxsw_sp_fsm_lock,
316 .fsm_component_update = mlxsw_sp_fsm_component_update,
317 .fsm_block_download = mlxsw_sp_fsm_block_download,
318 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
319 .fsm_activate = mlxsw_sp_fsm_activate,
320 .fsm_query_state = mlxsw_sp_fsm_query_state,
321 .fsm_cancel = mlxsw_sp_fsm_cancel,
322 .fsm_release = mlxsw_sp_fsm_release
323};
324
ce6ef68f
YG		 325static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
326 const struct firmware *firmware)
327{
328 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
329 .mlxfw_dev = {
330 .ops = &mlxsw_sp_mlxfw_dev_ops,
331 .psid = mlxsw_sp->bus_info->psid,
332 .psid_size = strlen(mlxsw_sp->bus_info->psid),
333 },
334 .mlxsw_sp = mlxsw_sp
335 };
336
337 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
338}
339
6b742199
YG		 340static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
341 const struct mlxsw_fw_rev *b)
342{
343 if (a->major != b->major)
344 return a->major > b->major;
345 if (a->minor != b->minor)
346 return a->minor > b->minor;
347 return a->subminor >= b->subminor;
348}
349
350static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
351{
352 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
6b742199
YG		 353 const struct firmware *firmware;
354 int err;
355
356 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
357 return 0;
358
359 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
360 rev->major, rev->minor, rev->subminor);
361 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
362 MLXSW_SP_FW_FILENAME);
363
364 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
365 mlxsw_sp->bus_info->dev);
366 if (err) {
367 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
368 MLXSW_SP_FW_FILENAME);
369 return err;
370 }
371
ce6ef68f 372 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
6b742199
YG		 373 release_firmware(firmware);
374 return err;
375}
376
1abcbcc2
AS		 377int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
378 unsigned int counter_index, u64 *packets,
379 u64 *bytes)
380{
381 char mgpc_pl[MLXSW_REG_MGPC_LEN];
382 int err;
383
384 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
385 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
386 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
387 if (err)
388 return err;
389 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
390 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
391 return 0;
392}
393
394static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
395 unsigned int counter_index)
396{
397 char mgpc_pl[MLXSW_REG_MGPC_LEN];
398
399 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
400 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
401 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
402}
403
404int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
405 unsigned int *p_counter_index)
406{
407 int err;
408
409 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
410 p_counter_index);
411 if (err)
412 return err;
413 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
414 if (err)
415 goto err_counter_clear;
416 return 0;
417
418err_counter_clear:
419 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
420 *p_counter_index);
421 return err;
422}
423
424void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
425 unsigned int counter_index)
426{
427 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
428 counter_index);
429}
430
56ade8fe
JP		 431static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
432 const struct mlxsw_tx_info *tx_info)
433{
434 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
435
436 memset(txhdr, 0, MLXSW_TXHDR_LEN);
437
438 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
439 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
440 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
441 mlxsw_tx_hdr_swid_set(txhdr, 0);
442 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
443 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
444 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
445}
446
fe9ccc78
IS		 447int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
448 u8 state)
449{
450 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
451 enum mlxsw_reg_spms_state spms_state;
452 char *spms_pl;
453 int err;
454
455 switch (state) {
456 case BR_STATE_FORWARDING:
457 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
458 break;
459 case BR_STATE_LEARNING:
460 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
461 break;
462 case BR_STATE_LISTENING: /* fall-through */
463 case BR_STATE_DISABLED: /* fall-through */
464 case BR_STATE_BLOCKING:
465 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
466 break;
467 default:
468 BUG();
469 }
470
471 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
472 if (!spms_pl)
473 return -ENOMEM;
474 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
475 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
476
477 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
478 kfree(spms_pl);
479 return err;
480}
481
56ade8fe
JP		 482static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
483{
5b090740 484 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
56ade8fe
JP		 485 int err;
486
487 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
488 if (err)
489 return err;
490 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
491 return 0;
492}
493
763b4b70
YG		 494static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
495{
763b4b70
YG		 496 int i;
497
c1a38311 498 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 499 return -EIO;
500
c1a38311
JP		 501 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
502 MAX_SPAN);
763b4b70
YG		 503 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
504 sizeof(struct mlxsw_sp_span_entry),
505 GFP_KERNEL);
506 if (!mlxsw_sp->span.entries)
507 return -ENOMEM;
508
509 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
510 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
511
512 return 0;
513}
514
515static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
516{
517 int i;
518
519 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
520 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
521
522 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
523 }
524 kfree(mlxsw_sp->span.entries);
525}
526
527static struct mlxsw_sp_span_entry *
528mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
529{
530 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
531 struct mlxsw_sp_span_entry *span_entry;
532 char mpat_pl[MLXSW_REG_MPAT_LEN];
533 u8 local_port = port->local_port;
534 int index;
535 int i;
536 int err;
537
538 /* find a free entry to use */
539 index = -1;
540 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
541 if (!mlxsw_sp->span.entries[i].used) {
542 index = i;
543 span_entry = &mlxsw_sp->span.entries[i];
544 break;
545 }
546 }
547 if (index < 0)
548 return NULL;
549
550 /* create a new port analayzer entry for local_port */
551 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
552 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
553 if (err)
554 return NULL;
555
556 span_entry->used = true;
557 span_entry->id = index;
2d644d4c 558 span_entry->ref_count = 1;
763b4b70
YG		 559 span_entry->local_port = local_port;
560 return span_entry;
561}
562
563static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
564 struct mlxsw_sp_span_entry *span_entry)
565{
566 u8 local_port = span_entry->local_port;
567 char mpat_pl[MLXSW_REG_MPAT_LEN];
568 int pa_id = span_entry->id;
569
570 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
571 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
572 span_entry->used = false;
573}
574
1a9234e6
IS		 575static struct mlxsw_sp_span_entry *
576mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
763b4b70
YG		 577{
578 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
579 int i;
580
581 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
582 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
583
584 if (curr->used && curr->local_port == port->local_port)
585 return curr;
586 }
587 return NULL;
588}
589
1a9234e6
IS		 590static struct mlxsw_sp_span_entry
591*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 592{
593 struct mlxsw_sp_span_entry *span_entry;
594
595 span_entry = mlxsw_sp_span_entry_find(port);
596 if (span_entry) {
2d644d4c 597 /* Already exists, just take a reference */
763b4b70
YG		 598 span_entry->ref_count++;
599 return span_entry;
600 }
601
602 return mlxsw_sp_span_entry_create(port);
603}
604
605static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
606 struct mlxsw_sp_span_entry *span_entry)
607{
2d644d4c 608 WARN_ON(!span_entry->ref_count);
763b4b70
YG		 609 if (--span_entry->ref_count == 0)
610 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
611 return 0;
612}
613
614static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
615{
616 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
617 struct mlxsw_sp_span_inspected_port *p;
618 int i;
619
620 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
621 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
622
623 list_for_each_entry(p, &curr->bound_ports_list, list)
624 if (p->local_port == port->local_port &&
625 p->type == MLXSW_SP_SPAN_EGRESS)
626 return true;
627 }
628
629 return false;
630}
631
18281f2d
IS		 632static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
633 int mtu)
763b4b70 634{
18281f2d 635 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
763b4b70
YG		 636}
637
638static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
639{
640 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
641 char sbib_pl[MLXSW_REG_SBIB_LEN];
642 int err;
643
644 /* If port is egress mirrored, the shared buffer size should be
645 * updated according to the mtu value
646 */
647 if (mlxsw_sp_span_is_egress_mirror(port)) {
18281f2d
IS		 648 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
649
650 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 651 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
652 if (err) {
653 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
654 return err;
655 }
656 }
657
658 return 0;
659}
660
661static struct mlxsw_sp_span_inspected_port *
662mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
663 struct mlxsw_sp_span_entry *span_entry)
664{
665 struct mlxsw_sp_span_inspected_port *p;
666
667 list_for_each_entry(p, &span_entry->bound_ports_list, list)
668 if (port->local_port == p->local_port)
669 return p;
670 return NULL;
671}
672
673static int
674mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
675 struct mlxsw_sp_span_entry *span_entry,
676 enum mlxsw_sp_span_type type)
677{
678 struct mlxsw_sp_span_inspected_port *inspected_port;
679 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
680 char mpar_pl[MLXSW_REG_MPAR_LEN];
681 char sbib_pl[MLXSW_REG_SBIB_LEN];
682 int pa_id = span_entry->id;
683 int err;
684
685 /* if it is an egress SPAN, bind a shared buffer to it */
686 if (type == MLXSW_SP_SPAN_EGRESS) {
18281f2d
IS		 687 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
688 port->dev->mtu);
689
690 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 691 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
692 if (err) {
693 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
694 return err;
695 }
696 }
697
698 /* bind the port to the SPAN entry */
1a9234e6
IS		 699 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
700 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
763b4b70
YG		 701 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
702 if (err)
703 goto err_mpar_reg_write;
704
705 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
706 if (!inspected_port) {
707 err = -ENOMEM;
708 goto err_inspected_port_alloc;
709 }
710 inspected_port->local_port = port->local_port;
711 inspected_port->type = type;
712 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
713
714 return 0;
715
716err_mpar_reg_write:
717err_inspected_port_alloc:
718 if (type == MLXSW_SP_SPAN_EGRESS) {
719 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
720 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
721 }
722 return err;
723}
724
725static void
726mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
727 struct mlxsw_sp_span_entry *span_entry,
728 enum mlxsw_sp_span_type type)
729{
730 struct mlxsw_sp_span_inspected_port *inspected_port;
731 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
732 char mpar_pl[MLXSW_REG_MPAR_LEN];
733 char sbib_pl[MLXSW_REG_SBIB_LEN];
734 int pa_id = span_entry->id;
735
736 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
737 if (!inspected_port)
738 return;
739
740 /* remove the inspected port */
1a9234e6
IS		 741 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
742 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
763b4b70
YG		 743 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
744
745 /* remove the SBIB buffer if it was egress SPAN */
746 if (type == MLXSW_SP_SPAN_EGRESS) {
747 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
748 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
749 }
750
751 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
752
753 list_del(&inspected_port->list);
754 kfree(inspected_port);
755}
756
757static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
758 struct mlxsw_sp_port *to,
759 enum mlxsw_sp_span_type type)
760{
761 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
762 struct mlxsw_sp_span_entry *span_entry;
763 int err;
764
765 span_entry = mlxsw_sp_span_entry_get(to);
766 if (!span_entry)
767 return -ENOENT;
768
769 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
770 span_entry->id);
771
772 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
773 if (err)
774 goto err_port_bind;
775
776 return 0;
777
778err_port_bind:
779 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
780 return err;
781}
782
783static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
784 struct mlxsw_sp_port *to,
785 enum mlxsw_sp_span_type type)
786{
787 struct mlxsw_sp_span_entry *span_entry;
788
789 span_entry = mlxsw_sp_span_entry_find(to);
790 if (!span_entry) {
791 netdev_err(from->dev, "no span entry found\n");
792 return;
793 }
794
795 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
796 span_entry->id);
797 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
798}
799
98d0f7b9
YG		 800static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
801 bool enable, u32 rate)
802{
803 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
804 char mpsc_pl[MLXSW_REG_MPSC_LEN];
805
806 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
807 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
808}
809
56ade8fe
JP		 810static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
811 bool is_up)
812{
813 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
814 char paos_pl[MLXSW_REG_PAOS_LEN];
815
816 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
817 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
818 MLXSW_PORT_ADMIN_STATUS_DOWN);
819 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
820}
821
56ade8fe
JP		 822static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
823 unsigned char *addr)
824{
825 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
826 char ppad_pl[MLXSW_REG_PPAD_LEN];
827
828 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
829 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
830 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
831}
832
833static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
834{
835 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
836 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
837
838 ether_addr_copy(addr, mlxsw_sp->base_mac);
839 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
840 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
841}
842
56ade8fe
JP		 843static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
844{
845 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
846 char pmtu_pl[MLXSW_REG_PMTU_LEN];
847 int max_mtu;
848 int err;
849
850 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
851 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
852 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
853 if (err)
854 return err;
855 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
856
857 if (mtu > max_mtu)
858 return -EINVAL;
859
860 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
861 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
862}
863
be94535f
IS		 864static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
865{
866 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5b153859 867 char pspa_pl[MLXSW_REG_PSPA_LEN];
be94535f 868
5b153859
IS		 869 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
870 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
be94535f
IS		 871}
872
a1107487 873int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
56ade8fe
JP		 874{
875 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
876 char svpe_pl[MLXSW_REG_SVPE_LEN];
877
878 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
879 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
880}
881
7cbc4277
IS		 882int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
883 bool learn_enable)
56ade8fe
JP		 884{
885 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
886 char *spvmlr_pl;
887 int err;
888
889 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
890 if (!spvmlr_pl)
891 return -ENOMEM;
7cbc4277
IS		 892 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
893 learn_enable);
56ade8fe
JP		 894 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
895 kfree(spvmlr_pl);
896 return err;
897}
898
b02eae9b
IS		 899static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
900 u16 vid)
901{
902 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
903 char spvid_pl[MLXSW_REG_SPVID_LEN];
904
905 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
906 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
907}
908
909static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
910 bool allow)
911{
912 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
913 char spaft_pl[MLXSW_REG_SPAFT_LEN];
914
915 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
916 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
917}
918
919int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
920{
921 int err;
922
923 if (!vid) {
924 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
925 if (err)
926 return err;
927 } else {
928 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
929 if (err)
930 return err;
931 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
932 if (err)
933 goto err_port_allow_untagged_set;
934 }
935
936 mlxsw_sp_port->pvid = vid;
937 return 0;
938
939err_port_allow_untagged_set:
940 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
941 return err;
942}
943
56ade8fe
JP		 944static int
945mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
946{
947 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
948 char sspr_pl[MLXSW_REG_SSPR_LEN];
949
950 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
951 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
952}
953
d664b41e
IS		 954static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
955 u8 local_port, u8 *p_module,
956 u8 *p_width, u8 *p_lane)
56ade8fe 957{
56ade8fe
JP		 958 char pmlp_pl[MLXSW_REG_PMLP_LEN];
959 int err;
960
558c2d5e 961 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 962 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
963 if (err)
964 return err;
558c2d5e
IS		 965 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
966 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 967 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 968 return 0;
969}
970
2e915e0b 971static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
18f1e70c
IS		 972 u8 module, u8 width, u8 lane)
973{
2e915e0b 974 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
18f1e70c
IS		 975 char pmlp_pl[MLXSW_REG_PMLP_LEN];
976 int i;
977
2e915e0b 978 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
18f1e70c
IS		 979 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
980 for (i = 0; i < width; i++) {
981 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
982 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
983 }
984
985 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
986}
987
2e915e0b 988static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
3e9b27b8 989{
2e915e0b 990 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3e9b27b8
IS		 991 char pmlp_pl[MLXSW_REG_PMLP_LEN];
992
2e915e0b 993 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
3e9b27b8
IS		 994 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
995 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
996}
997
56ade8fe
JP		 998static int mlxsw_sp_port_open(struct net_device *dev)
999{
1000 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1001 int err;
1002
1003 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1004 if (err)
1005 return err;
1006 netif_start_queue(dev);
1007 return 0;
1008}
1009
1010static int mlxsw_sp_port_stop(struct net_device *dev)
1011{
1012 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1013
1014 netif_stop_queue(dev);
1015 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1016}
1017
1018static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1019 struct net_device *dev)
1020{
1021 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1022 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1023 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1024 const struct mlxsw_tx_info tx_info = {
1025 .local_port = mlxsw_sp_port->local_port,
1026 .is_emad = false,
1027 };
1028 u64 len;
1029 int err;
1030
307c2431 1031 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 1032 return NETDEV_TX_BUSY;
1033
1034 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1035 struct sk_buff *skb_orig = skb;
1036
1037 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1038 if (!skb) {
1039 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1040 dev_kfree_skb_any(skb_orig);
1041 return NETDEV_TX_OK;
1042 }
36bf38d1 1043 dev_consume_skb_any(skb_orig);
56ade8fe
JP		 1044 }
1045
1046 if (eth_skb_pad(skb)) {
1047 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1048 return NETDEV_TX_OK;
1049 }
1050
1051 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 1052 /* TX header is consumed by HW on the way so we shouldn't count its
1053 * bytes as being sent.
1054 */
1055 len = skb->len - MLXSW_TXHDR_LEN;
1056
56ade8fe
JP		 1057 /* Due to a race we might fail here because of a full queue. In that
1058 * unlikely case we simply drop the packet.
1059 */
307c2431 1060 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 1061
1062 if (!err) {
1063 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1064 u64_stats_update_begin(&pcpu_stats->syncp);
1065 pcpu_stats->tx_packets++;
1066 pcpu_stats->tx_bytes += len;
1067 u64_stats_update_end(&pcpu_stats->syncp);
1068 } else {
1069 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1070 dev_kfree_skb_any(skb);
1071 }
1072 return NETDEV_TX_OK;
1073}
1074
c5b9b518
JP		 1075static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1076{
1077}
1078
56ade8fe
JP		 1079static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1080{
1081 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1082 struct sockaddr *addr = p;
1083 int err;
1084
1085 if (!is_valid_ether_addr(addr->sa_data))
1086 return -EADDRNOTAVAIL;
1087
1088 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1089 if (err)
1090 return err;
1091 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1092 return 0;
1093}
1094
18281f2d
IS		 1095static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1096 int mtu)
ff6551ec 1097{
18281f2d 1098 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
f417f04d 1099}
8e8dfe9f 1100
f417f04d 1101#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
18281f2d
IS		 1102
1103static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1104 u16 delay)
f417f04d 1105{
18281f2d
IS		 1106 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1107 BITS_PER_BYTE));
1108 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1109 mtu);
f417f04d
IS		 1110}
1111
18281f2d 1112/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
f417f04d
IS		 1113 * Assumes 100m cable and maximum MTU.
1114 */
18281f2d
IS		 1115#define MLXSW_SP_PAUSE_DELAY 58752
1116
1117static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1118 u16 delay, bool pfc, bool pause)
f417f04d
IS		 1119{
1120 if (pfc)
18281f2d 1121 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
f417f04d 1122 else if (pause)
18281f2d 1123 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
f417f04d
IS		 1124 else
1125 return 0;
1126}
9f7ec052 1127
f417f04d
IS		 1128static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1129 bool lossy)
1130{
1131 if (lossy)
1132 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
d81a6bdb 1133 else
f417f04d
IS		 1134 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1135 thres);
8e8dfe9f
IS		 1136}
1137
1138int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 1139 u8 *prio_tc, bool pause_en,
1140 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 1141{
1142 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 1143 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1144 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 1145 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 1146 int i, j, err;
ff6551ec
IS		 1147
1148 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1149 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1150 if (err)
1151 return err;
8e8dfe9f
IS		 1152
1153 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1154 bool configure = false;
d81a6bdb 1155 bool pfc = false;
f417f04d
IS		 1156 bool lossy;
1157 u16 thres;
8e8dfe9f
IS		 1158
1159 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1160 if (prio_tc[j] == i) {
d81a6bdb 1161 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 1162 configure = true;
1163 break;
1164 }
1165 }
1166
1167 if (!configure)
1168 continue;
f417f04d
IS		 1169
1170 lossy = !(pfc || pause_en);
18281f2d
IS		 1171 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1172 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1173 pause_en);
f417f04d 1174 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
8e8dfe9f
IS		 1175 }
1176
ff6551ec
IS		 1177 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1178}
1179
8e8dfe9f 1180static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 1181 int mtu, bool pause_en)
8e8dfe9f
IS		 1182{
1183 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1184 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 1185 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 1186 u8 *prio_tc;
1187
1188 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 1189 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 1190
9f7ec052 1191 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 1192 pause_en, my_pfc);
8e8dfe9f
IS		 1193}
1194
56ade8fe
JP		 1195static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1196{
1197 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 1198 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 1199 int err;
1200
9f7ec052 1201 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 1202 if (err)
1203 return err;
763b4b70
YG		 1204 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1205 if (err)
1206 goto err_span_port_mtu_update;
ff6551ec
IS		 1207 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1208 if (err)
1209 goto err_port_mtu_set;
56ade8fe
JP		 1210 dev->mtu = mtu;
1211 return 0;
ff6551ec
IS		 1212
1213err_port_mtu_set:
763b4b70
YG		 1214 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1215err_span_port_mtu_update:
9f7ec052 1216 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 1217 return err;
56ade8fe
JP		 1218}
1219
4bdcc6ca 1220static int
fc1bbb0f
NF		 1221mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1222 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 1223{
1224 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1225 struct mlxsw_sp_port_pcpu_stats *p;
1226 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1227 u32 tx_dropped = 0;
1228 unsigned int start;
1229 int i;
1230
1231 for_each_possible_cpu(i) {
1232 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1233 do {
1234 start = u64_stats_fetch_begin_irq(&p->syncp);
1235 rx_packets = p->rx_packets;
1236 rx_bytes = p->rx_bytes;
1237 tx_packets = p->tx_packets;
1238 tx_bytes = p->tx_bytes;
1239 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1240
1241 stats->rx_packets += rx_packets;
1242 stats->rx_bytes += rx_bytes;
1243 stats->tx_packets += tx_packets;
1244 stats->tx_bytes += tx_bytes;
1245 /* tx_dropped is u32, updated without syncp protection. */
1246 tx_dropped += p->tx_dropped;
1247 }
1248 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 1249 return 0;
1250}
1251
3df5b3c6 1252static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
fc1bbb0f
NF		 1253{
1254 switch (attr_id) {
1255 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1256 return true;
1257 }
1258
1259 return false;
1260}
1261
4bdcc6ca
OG		 1262static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1263 void *sp)
fc1bbb0f
NF		 1264{
1265 switch (attr_id) {
1266 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1267 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1268 }
1269
1270 return -EINVAL;
1271}
1272
1273static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1274 int prio, char *ppcnt_pl)
1275{
1276 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1277 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1278
1279 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1280 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1281}
1282
1283static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1284 struct rtnl_link_stats64 *stats)
1285{
1286 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1287 int err;
1288
1289 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1290 0, ppcnt_pl);
1291 if (err)
1292 goto out;
1293
1294 stats->tx_packets =
1295 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1296 stats->rx_packets =
1297 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1298 stats->tx_bytes =
1299 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1300 stats->rx_bytes =
1301 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1302 stats->multicast =
1303 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1304
1305 stats->rx_crc_errors =
1306 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1307 stats->rx_frame_errors =
1308 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1309
1310 stats->rx_length_errors = (
1311 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1312 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1313 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1314
1315 stats->rx_errors = (stats->rx_crc_errors +
1316 stats->rx_frame_errors + stats->rx_length_errors);
1317
1318out:
1319 return err;
1320}
1321
1322static void update_stats_cache(struct work_struct *work)
1323{
1324 struct mlxsw_sp_port *mlxsw_sp_port =
1325 container_of(work, struct mlxsw_sp_port,
1326 hw_stats.update_dw.work);
1327
1328 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1329 goto out;
1330
1331 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1332 mlxsw_sp_port->hw_stats.cache);
1333
1334out:
1335 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1336 MLXSW_HW_STATS_UPDATE_TIME);
1337}
1338
1339/* Return the stats from a cache that is updated periodically,
1340 * as this function might get called in an atomic context.
1341 */
bc1f4470 1342static void
fc1bbb0f
NF		 1343mlxsw_sp_port_get_stats64(struct net_device *dev,
1344 struct rtnl_link_stats64 *stats)
1345{
1346 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1347
1348 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
56ade8fe
JP		 1349}
1350
93cd0813
JP		 1351static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1352 u16 vid_begin, u16 vid_end,
1353 bool is_member, bool untagged)
56ade8fe
JP		 1354{
1355 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1356 char *spvm_pl;
1357 int err;
1358
1359 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1360 if (!spvm_pl)
1361 return -ENOMEM;
1362
1363 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1364 vid_end, is_member, untagged);
1365 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1366 kfree(spvm_pl);
1367 return err;
1368}
1369
93cd0813
JP		 1370int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1371 u16 vid_end, bool is_member, bool untagged)
1372{
1373 u16 vid, vid_e;
1374 int err;
1375
1376 for (vid = vid_begin; vid <= vid_end;
1377 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1378 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1379 vid_end);
1380
1381 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1382 is_member, untagged);
1383 if (err)
1384 return err;
1385 }
1386
1387 return 0;
1388}
1389
c57529e1 1390static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
7f71eb46 1391{
c57529e1 1392 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
7f71eb46 1393
c57529e1
IS		 1394 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1395 &mlxsw_sp_port->vlans_list, list)
1396 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
7f71eb46
IS		 1397}
1398
31a08a52
IS		 1399static struct mlxsw_sp_port_vlan *
1400mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1401{
1402 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
c57529e1
IS		 1403 bool untagged = vid == 1;
1404 int err;
1405
1406 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1407 if (err)
1408 return ERR_PTR(err);
31a08a52
IS		 1409
1410 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
c57529e1
IS		 1411 if (!mlxsw_sp_port_vlan) {
1412 err = -ENOMEM;
1413 goto err_port_vlan_alloc;
1414 }
31a08a52
IS		 1415
1416 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1417 mlxsw_sp_port_vlan->vid = vid;
1418 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1419
1420 return mlxsw_sp_port_vlan;
c57529e1
IS		 1421
1422err_port_vlan_alloc:
1423 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1424 return ERR_PTR(err);
31a08a52
IS		 1425}
1426
1427static void
1428mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1429{
c57529e1
IS		 1430 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1431 u16 vid = mlxsw_sp_port_vlan->vid;
7cbecf24 1432
31a08a52
IS		 1433 list_del(&mlxsw_sp_port_vlan->list);
1434 kfree(mlxsw_sp_port_vlan);
c57529e1
IS		 1435 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1436}
1437
1438struct mlxsw_sp_port_vlan *
1439mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1440{
1441 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1442
1443 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1444 if (mlxsw_sp_port_vlan)
1445 return mlxsw_sp_port_vlan;
1446
1447 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1448}
1449
1450void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1451{
a1107487
IS		 1452 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1453
c57529e1
IS		 1454 if (mlxsw_sp_port_vlan->bridge_port)
1455 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
a1107487
IS		 1456 else if (fid)
1457 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
c57529e1
IS		 1458
1459 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
31a08a52
IS		 1460}
1461
05978481
IS		 1462static int mlxsw_sp_port_add_vid(struct net_device *dev,
1463 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1464{
1465 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
56ade8fe
JP		 1466
1467 /* VLAN 0 is added to HW filter when device goes up, but it is
1468 * reserved in our case, so simply return.
1469 */
1470 if (!vid)
1471 return 0;
1472
c57529e1 1473 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
56ade8fe
JP		 1474}
1475
32d863fb
IS		 1476static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1477 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1478{
1479 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
31a08a52 1480 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 1481
1482 /* VLAN 0 is removed from HW filter when device goes down, but
1483 * it is reserved in our case, so simply return.
1484 */
1485 if (!vid)
1486 return 0;
1487
31a08a52 1488 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
c57529e1 1489 if (!mlxsw_sp_port_vlan)
56ade8fe 1490 return 0;
c57529e1 1491 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
31a08a52 1492
56ade8fe
JP		 1493 return 0;
1494}
1495
2bf9a586
IS		 1496static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1497 size_t len)
1498{
1499 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1500 u8 module = mlxsw_sp_port->mapping.module;
1501 u8 width = mlxsw_sp_port->mapping.width;
1502 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1503 int err;
1504
2bf9a586
IS		 1505 if (!mlxsw_sp_port->split)
1506 err = snprintf(name, len, "p%d", module + 1);
1507 else
1508 err = snprintf(name, len, "p%ds%d", module + 1,
1509 lane / width);
1510
1511 if (err >= len)
1512 return -EINVAL;
1513
1514 return 0;
1515}
1516
763b4b70 1517static struct mlxsw_sp_port_mall_tc_entry *
65acb5d0
YG		 1518mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1519 unsigned long cookie) {
763b4b70
YG		 1520 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1521
1522 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1523 if (mall_tc_entry->cookie == cookie)
1524 return mall_tc_entry;
1525
1526 return NULL;
1527}
1528
1529static int
1530mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
65acb5d0 1531 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
763b4b70
YG		 1532 const struct tc_action *a,
1533 bool ingress)
1534{
763b4b70
YG		 1535 struct net *net = dev_net(mlxsw_sp_port->dev);
1536 enum mlxsw_sp_span_type span_type;
1537 struct mlxsw_sp_port *to_port;
1538 struct net_device *to_dev;
1539 int ifindex;
763b4b70
YG		 1540
1541 ifindex = tcf_mirred_ifindex(a);
1542 to_dev = __dev_get_by_index(net, ifindex);
1543 if (!to_dev) {
1544 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1545 return -EINVAL;
1546 }
1547
1548 if (!mlxsw_sp_port_dev_check(to_dev)) {
1549 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
e915ac68 1550 return -EOPNOTSUPP;
763b4b70
YG		 1551 }
1552 to_port = netdev_priv(to_dev);
1553
65acb5d0
YG		 1554 mirror->to_local_port = to_port->local_port;
1555 mirror->ingress = ingress;
763b4b70 1556 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
65acb5d0
YG		 1557 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1558}
763b4b70 1559
65acb5d0
YG		 1560static void
1561mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1562 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1563{
1564 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1565 enum mlxsw_sp_span_type span_type;
1566 struct mlxsw_sp_port *to_port;
1567
1568 to_port = mlxsw_sp->ports[mirror->to_local_port];
1569 span_type = mirror->ingress ?
1570 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1571 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
763b4b70
YG		 1572}
1573
98d0f7b9
YG		 1574static int
1575mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1576 struct tc_cls_matchall_offload *cls,
1577 const struct tc_action *a,
1578 bool ingress)
1579{
1580 int err;
1581
1582 if (!mlxsw_sp_port->sample)
1583 return -EOPNOTSUPP;
1584 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1585 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1586 return -EEXIST;
1587 }
1588 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1589 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1590 return -EOPNOTSUPP;
1591 }
1592
1593 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1594 tcf_sample_psample_group(a));
1595 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1596 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1597 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1598
1599 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1600 if (err)
1601 goto err_port_sample_set;
1602 return 0;
1603
1604err_port_sample_set:
1605 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1606 return err;
1607}
1608
1609static void
1610mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1611{
1612 if (!mlxsw_sp_port->sample)
1613 return;
1614
1615 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1616 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1617}
1618
763b4b70 1619static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1620 struct tc_cls_matchall_offload *f,
763b4b70
YG		 1621 bool ingress)
1622{
65acb5d0 1623 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
5fd9fc4e 1624 __be16 protocol = f->common.protocol;
763b4b70 1625 const struct tc_action *a;
22dc13c8 1626 LIST_HEAD(actions);
763b4b70
YG		 1627 int err;
1628
9cbf14ed 1629 if (!tcf_exts_has_one_action(f->exts)) {
763b4b70 1630 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
e915ac68 1631 return -EOPNOTSUPP;
763b4b70
YG		 1632 }
1633
65acb5d0
YG		 1634 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1635 if (!mall_tc_entry)
1636 return -ENOMEM;
9cbf14ed 1637 mall_tc_entry->cookie = f->cookie;
65acb5d0 1638
9cbf14ed 1639 tcf_exts_to_list(f->exts, &actions);
65acb5d0 1640 a = list_first_entry(&actions, struct tc_action, list);
86cb13e4 1641
65acb5d0
YG		 1642 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1643 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1644
1645 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1646 mirror = &mall_tc_entry->mirror;
1647 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1648 mirror, a, ingress);
98d0f7b9
YG		 1649 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1650 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
9cbf14ed 1651 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
98d0f7b9 1652 a, ingress);
65acb5d0
YG		 1653 } else {
1654 err = -EOPNOTSUPP;
763b4b70
YG		 1655 }
1656
65acb5d0
YG		 1657 if (err)
1658 goto err_add_action;
1659
1660 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
763b4b70 1661 return 0;
65acb5d0
YG		 1662
1663err_add_action:
1664 kfree(mall_tc_entry);
1665 return err;
763b4b70
YG		 1666}
1667
1668static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1669 struct tc_cls_matchall_offload *f)
763b4b70 1670{
763b4b70 1671 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
763b4b70 1672
65acb5d0 1673 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
9cbf14ed 1674 f->cookie);
763b4b70
YG		 1675 if (!mall_tc_entry) {
1676 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1677 return;
1678 }
65acb5d0 1679 list_del(&mall_tc_entry->list);
763b4b70
YG		 1680
1681 switch (mall_tc_entry->type) {
1682 case MLXSW_SP_PORT_MALL_MIRROR:
65acb5d0
YG		 1683 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1684 &mall_tc_entry->mirror);
763b4b70 1685 break;
98d0f7b9
YG		 1686 case MLXSW_SP_PORT_MALL_SAMPLE:
1687 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1688 break;
763b4b70
YG		 1689 default:
1690 WARN_ON(1);
1691 }
1692
763b4b70
YG		 1693 kfree(mall_tc_entry);
1694}
1695
fd33f1df 1696static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
fd33f1df
JP		 1697 struct tc_cls_matchall_offload *f)
1698{
5fd9fc4e 1699 bool ingress = TC_H_MAJ(f->common.handle) == TC_H_MAJ(TC_H_INGRESS);
fd33f1df 1700
5fd9fc4e 1701 if (f->common.chain_index)
fd33f1df
JP		 1702 return -EOPNOTSUPP;
1703
1704 switch (f->command) {
1705 case TC_CLSMATCHALL_REPLACE:
5fd9fc4e 1706 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
fd33f1df
JP		 1707 ingress);
1708 case TC_CLSMATCHALL_DESTROY:
1709 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1710 return 0;
1711 default:
1712 return -EOPNOTSUPP;
1713 }
1714}
1715
1716static int
1717mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
fd33f1df 1718 struct tc_cls_flower_offload *f)
763b4b70 1719{
5fd9fc4e 1720 bool ingress = TC_H_MAJ(f->common.handle) == TC_H_MAJ(TC_H_INGRESS);
763b4b70 1721
5fd9fc4e 1722 if (f->common.chain_index)
a5fcf8a6
JP		 1723 return -EOPNOTSUPP;
1724
fd33f1df
JP		 1725 switch (f->command) {
1726 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 1727 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
fd33f1df
JP		 1728 case TC_CLSFLOWER_DESTROY:
1729 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
1730 return 0;
1731 case TC_CLSFLOWER_STATS:
1732 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
1733 default:
1734 return -EOPNOTSUPP;
1735 }
1736}
1737
1738static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
fd33f1df
JP		 1739 struct tc_to_netdev *tc)
1740{
1741 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1742
2572ac53 1743 switch (type) {
ade9b658 1744 case TC_SETUP_CLSMATCHALL:
5fd9fc4e 1745 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port,
fd33f1df 1746 tc->cls_mall);
7aa0f5aa 1747 case TC_SETUP_CLSFLOWER:
5fd9fc4e 1748 return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port,
fd33f1df 1749 tc->cls_flower);
2572ac53
JP		 1750 default:
1751 return -EOPNOTSUPP;
763b4b70 1752 }
763b4b70
YG		 1753}
1754
56ade8fe
JP		 1755static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1756 .ndo_open = mlxsw_sp_port_open,
1757 .ndo_stop = mlxsw_sp_port_stop,
1758 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 1759 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 1760 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 1761 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1762 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1763 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 1764 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1765 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 1766 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1767 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
2bf9a586 1768 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 1769};
1770
1771static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1772 struct ethtool_drvinfo *drvinfo)
1773{
1774 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1775 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1776
1777 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1778 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1779 sizeof(drvinfo->version));
1780 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1781 "%d.%d.%d",
1782 mlxsw_sp->bus_info->fw_rev.major,
1783 mlxsw_sp->bus_info->fw_rev.minor,
1784 mlxsw_sp->bus_info->fw_rev.subminor);
1785 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1786 sizeof(drvinfo->bus_info));
1787}
1788
9f7ec052
IS		 1789static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1790 struct ethtool_pauseparam *pause)
1791{
1792 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1793
1794 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1795 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1796}
1797
1798static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1799 struct ethtool_pauseparam *pause)
1800{
1801 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1802
1803 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1804 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1805 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1806
1807 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1808 pfcc_pl);
1809}
1810
1811static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1812 struct ethtool_pauseparam *pause)
1813{
1814 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1815 bool pause_en = pause->tx_pause || pause->rx_pause;
1816 int err;
1817
d81a6bdb
IS		 1818 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1819 netdev_err(dev, "PFC already enabled on port\n");
1820 return -EINVAL;
1821 }
1822
9f7ec052
IS		 1823 if (pause->autoneg) {
1824 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1825 return -EINVAL;
1826 }
1827
1828 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1829 if (err) {
1830 netdev_err(dev, "Failed to configure port's headroom\n");
1831 return err;
1832 }
1833
1834 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1835 if (err) {
1836 netdev_err(dev, "Failed to set PAUSE parameters\n");
1837 goto err_port_pause_configure;
1838 }
1839
1840 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1841 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1842
1843 return 0;
1844
1845err_port_pause_configure:
1846 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1847 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1848 return err;
1849}
1850
56ade8fe
JP		 1851struct mlxsw_sp_port_hw_stats {
1852 char str[ETH_GSTRING_LEN];
412791df 1853 u64 (*getter)(const char *payload);
18281f2d 1854 bool cells_bytes;
56ade8fe
JP		 1855};
1856
7ed674bc 1857static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 1858 {
1859 .str = "a_frames_transmitted_ok",
1860 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1861 },
1862 {
1863 .str = "a_frames_received_ok",
1864 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1865 },
1866 {
1867 .str = "a_frame_check_sequence_errors",
1868 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1869 },
1870 {
1871 .str = "a_alignment_errors",
1872 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1873 },
1874 {
1875 .str = "a_octets_transmitted_ok",
1876 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1877 },
1878 {
1879 .str = "a_octets_received_ok",
1880 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1881 },
1882 {
1883 .str = "a_multicast_frames_xmitted_ok",
1884 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1885 },
1886 {
1887 .str = "a_broadcast_frames_xmitted_ok",
1888 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1889 },
1890 {
1891 .str = "a_multicast_frames_received_ok",
1892 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1893 },
1894 {
1895 .str = "a_broadcast_frames_received_ok",
1896 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1897 },
1898 {
1899 .str = "a_in_range_length_errors",
1900 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1901 },
1902 {
1903 .str = "a_out_of_range_length_field",
1904 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1905 },
1906 {
1907 .str = "a_frame_too_long_errors",
1908 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1909 },
1910 {
1911 .str = "a_symbol_error_during_carrier",
1912 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1913 },
1914 {
1915 .str = "a_mac_control_frames_transmitted",
1916 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1917 },
1918 {
1919 .str = "a_mac_control_frames_received",
1920 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1921 },
1922 {
1923 .str = "a_unsupported_opcodes_received",
1924 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1925 },
1926 {
1927 .str = "a_pause_mac_ctrl_frames_received",
1928 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1929 },
1930 {
1931 .str = "a_pause_mac_ctrl_frames_xmitted",
1932 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1933 },
1934};
1935
1936#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1937
7ed674bc
IS		 1938static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1939 {
1940 .str = "rx_octets_prio",
1941 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1942 },
1943 {
1944 .str = "rx_frames_prio",
1945 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1946 },
1947 {
1948 .str = "tx_octets_prio",
1949 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1950 },
1951 {
1952 .str = "tx_frames_prio",
1953 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1954 },
1955 {
1956 .str = "rx_pause_prio",
1957 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1958 },
1959 {
1960 .str = "rx_pause_duration_prio",
1961 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1962 },
1963 {
1964 .str = "tx_pause_prio",
1965 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1966 },
1967 {
1968 .str = "tx_pause_duration_prio",
1969 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1970 },
1971};
1972
1973#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1974
df4750e8
IS		 1975static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1976 {
1977 .str = "tc_transmit_queue_tc",
18281f2d
IS		 1978 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1979 .cells_bytes = true,
df4750e8
IS		 1980 },
1981 {
1982 .str = "tc_no_buffer_discard_uc_tc",
1983 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1984 },
1985};
1986
1987#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1988
7ed674bc 1989#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 1990 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1991 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 1992 IEEE_8021QAZ_MAX_TCS)
1993
1994static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1995{
1996 int i;
1997
1998 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1999 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2000 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2001 *p += ETH_GSTRING_LEN;
2002 }
2003}
2004
df4750e8
IS		 2005static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2006{
2007 int i;
2008
2009 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2010 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2011 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2012 *p += ETH_GSTRING_LEN;
2013 }
2014}
2015
56ade8fe
JP		 2016static void mlxsw_sp_port_get_strings(struct net_device *dev,
2017 u32 stringset, u8 *data)
2018{
2019 u8 *p = data;
2020 int i;
2021
2022 switch (stringset) {
2023 case ETH_SS_STATS:
2024 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2025 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2026 ETH_GSTRING_LEN);
2027 p += ETH_GSTRING_LEN;
2028 }
7ed674bc
IS		 2029
2030 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2031 mlxsw_sp_port_get_prio_strings(&p, i);
2032
df4750e8
IS		 2033 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2034 mlxsw_sp_port_get_tc_strings(&p, i);
2035
56ade8fe
JP		 2036 break;
2037 }
2038}
2039
3a66ee38
IS		 2040static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2041 enum ethtool_phys_id_state state)
2042{
2043 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2044 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2045 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2046 bool active;
2047
2048 switch (state) {
2049 case ETHTOOL_ID_ACTIVE:
2050 active = true;
2051 break;
2052 case ETHTOOL_ID_INACTIVE:
2053 active = false;
2054 break;
2055 default:
2056 return -EOPNOTSUPP;
2057 }
2058
2059 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2060 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2061}
2062
7ed674bc
IS		 2063static int
2064mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2065 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2066{
2067 switch (grp) {
2068 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2069 *p_hw_stats = mlxsw_sp_port_hw_stats;
2070 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2071 break;
2072 case MLXSW_REG_PPCNT_PRIO_CNT:
2073 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2074 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2075 break;
df4750e8
IS		 2076 case MLXSW_REG_PPCNT_TC_CNT:
2077 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2078 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2079 break;
7ed674bc
IS		 2080 default:
2081 WARN_ON(1);
e915ac68 2082 return -EOPNOTSUPP;
7ed674bc
IS		 2083 }
2084 return 0;
2085}
2086
2087static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2088 enum mlxsw_reg_ppcnt_grp grp, int prio,
2089 u64 *data, int data_index)
56ade8fe 2090{
18281f2d
IS		 2091 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2092 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
7ed674bc 2093 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 2094 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 2095 int i, len;
56ade8fe
JP		 2096 int err;
2097
7ed674bc
IS		 2098 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2099 if (err)
2100 return;
fc1bbb0f 2101 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
18281f2d 2102 for (i = 0; i < len; i++) {
faac0ff0 2103 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
18281f2d
IS		 2104 if (!hw_stats[i].cells_bytes)
2105 continue;
2106 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2107 data[data_index + i]);
2108 }
7ed674bc
IS		 2109}
2110
2111static void mlxsw_sp_port_get_stats(struct net_device *dev,
2112 struct ethtool_stats *stats, u64 *data)
2113{
2114 int i, data_index = 0;
2115
2116 /* IEEE 802.3 Counters */
2117 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2118 data, data_index);
2119 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2120
2121 /* Per-Priority Counters */
2122 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2123 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2124 data, data_index);
2125 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2126 }
df4750e8
IS		 2127
2128 /* Per-TC Counters */
2129 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2130 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2131 data, data_index);
2132 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2133 }
56ade8fe
JP		 2134}
2135
2136static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2137{
2138 switch (sset) {
2139 case ETH_SS_STATS:
7ed674bc 2140 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 2141 default:
2142 return -EOPNOTSUPP;
2143 }
2144}
2145
2146struct mlxsw_sp_port_link_mode {
b9d66a36 2147 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 2148 u32 mask;
56ade8fe
JP		 2149 u32 speed;
2150};
2151
2152static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2153 {
2154 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 2155 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2156 .speed = SPEED_100,
56ade8fe
JP		 2157 },
2158 {
2159 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2160 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 2161 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2162 .speed = SPEED_1000,
56ade8fe
JP		 2163 },
2164 {
2165 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 2166 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2167 .speed = SPEED_10000,
56ade8fe
JP		 2168 },
2169 {
2170 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2171 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 2172 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2173 .speed = SPEED_10000,
56ade8fe
JP		 2174 },
2175 {
2176 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2177 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2178 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2179 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 2180 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2181 .speed = SPEED_10000,
56ade8fe
JP		 2182 },
2183 {
2184 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 2185 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2186 .speed = SPEED_20000,
56ade8fe
JP		 2187 },
2188 {
2189 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 2190 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2191 .speed = SPEED_40000,
56ade8fe
JP		 2192 },
2193 {
2194 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 2195 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2196 .speed = SPEED_40000,
56ade8fe
JP		 2197 },
2198 {
2199 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 2200 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2201 .speed = SPEED_40000,
56ade8fe
JP		 2202 },
2203 {
2204 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 2205 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2206 .speed = SPEED_40000,
2207 },
2208 {
2209 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2210 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2211 .speed = SPEED_25000,
2212 },
2213 {
2214 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2215 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2216 .speed = SPEED_25000,
2217 },
2218 {
2219 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2220 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2221 .speed = SPEED_25000,
56ade8fe
JP		 2222 },
2223 {
b9d66a36
IS		 2224 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2225 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2226 .speed = SPEED_25000,
56ade8fe
JP		 2227 },
2228 {
b9d66a36
IS		 2229 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2230 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2231 .speed = SPEED_50000,
2232 },
2233 {
2234 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2235 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2236 .speed = SPEED_50000,
2237 },
2238 {
2239 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2240 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2241 .speed = SPEED_50000,
56ade8fe
JP		 2242 },
2243 {
2244 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 2245 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2246 .speed = SPEED_56000,
56ade8fe
JP		 2247 },
2248 {
b9d66a36
IS		 2249 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2250 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2251 .speed = SPEED_56000,
2252 },
2253 {
2254 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2255 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2256 .speed = SPEED_56000,
2257 },
2258 {
2259 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2260 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2261 .speed = SPEED_56000,
2262 },
2263 {
2264 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2265 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2266 .speed = SPEED_100000,
2267 },
2268 {
2269 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2270 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2271 .speed = SPEED_100000,
2272 },
2273 {
2274 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2275 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2276 .speed = SPEED_100000,
2277 },
2278 {
2279 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2280 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2281 .speed = SPEED_100000,
56ade8fe
JP		 2282 },
2283};
2284
2285#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2286
b9d66a36
IS		 2287static void
2288mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2289 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2290{
2291 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2292 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2293 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2294 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2295 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2296 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 2297 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 2298
2299 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2300 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2301 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2302 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2303 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 2304 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 2305}
2306
b9d66a36 2307static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 2308{
56ade8fe
JP		 2309 int i;
2310
2311 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2312 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 2313 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2314 mode);
56ade8fe 2315 }
56ade8fe
JP		 2316}
2317
2318static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 2319 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2320{
2321 u32 speed = SPEED_UNKNOWN;
2322 u8 duplex = DUPLEX_UNKNOWN;
2323 int i;
2324
2325 if (!carrier_ok)
2326 goto out;
2327
2328 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2329 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2330 speed = mlxsw_sp_port_link_mode[i].speed;
2331 duplex = DUPLEX_FULL;
2332 break;
2333 }
2334 }
2335out:
b9d66a36
IS		 2336 cmd->base.speed = speed;
2337 cmd->base.duplex = duplex;
56ade8fe
JP		 2338}
2339
2340static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2341{
2342 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2343 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2344 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2345 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2346 return PORT_FIBRE;
2347
2348 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2349 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2350 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2351 return PORT_DA;
2352
2353 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2354 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2355 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2356 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2357 return PORT_NONE;
2358
2359 return PORT_OTHER;
2360}
2361
b9d66a36
IS		 2362static u32
2363mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2364{
2365 u32 ptys_proto = 0;
2366 int i;
2367
2368 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 2369 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2370 cmd->link_modes.advertising))
56ade8fe
JP		 2371 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2372 }
2373 return ptys_proto;
2374}
2375
2376static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2377{
2378 u32 ptys_proto = 0;
2379 int i;
2380
2381 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2382 if (speed == mlxsw_sp_port_link_mode[i].speed)
2383 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2384 }
2385 return ptys_proto;
2386}
2387
18f1e70c
IS		 2388static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2389{
2390 u32 ptys_proto = 0;
2391 int i;
2392
2393 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2394 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2395 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2396 }
2397 return ptys_proto;
2398}
2399
b9d66a36
IS		 2400static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2401 struct ethtool_link_ksettings *cmd)
2402{
2403 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2404 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2405 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2406
2407 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2408 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2409}
2410
2411static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2412 struct ethtool_link_ksettings *cmd)
56ade8fe 2413{
b9d66a36
IS		 2414 if (!autoneg)
2415 return;
2416
2417 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2418 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2419}
2420
2421static void
2422mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2423 struct ethtool_link_ksettings *cmd)
2424{
2425 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2426 return;
2427
2428 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2429 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2430}
2431
2432static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2433 struct ethtool_link_ksettings *cmd)
2434{
2435 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 2436 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2437 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2438 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2439 u8 autoneg_status;
0c83f88c 2440 bool autoneg;
56ade8fe
JP		 2441 int err;
2442
b9d66a36 2443 autoneg = mlxsw_sp_port->link.autoneg;
401c8b4e 2444 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
b9d66a36
IS		 2445 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2446 if (err)
2447 return err;
401c8b4e
ER		 2448 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2449 &eth_proto_oper);
b9d66a36
IS		 2450
2451 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2452
b9d66a36
IS		 2453 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2454
2455 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2456 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2457 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2458
2459 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2460 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2461 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2462 cmd);
2463
2464 return 0;
2465}
2466
2467static int
2468mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2469 const struct ethtool_link_ksettings *cmd)
2470{
2471 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2472 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2473 char ptys_pl[MLXSW_REG_PTYS_LEN];
2474 u32 eth_proto_cap, eth_proto_new;
2475 bool autoneg;
2476 int err;
56ade8fe 2477
401c8b4e 2478 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
56ade8fe 2479 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2480 if (err)
56ade8fe 2481 return err;
401c8b4e 2482 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
b9d66a36
IS		 2483
2484 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2485 eth_proto_new = autoneg ?
2486 mlxsw_sp_to_ptys_advert_link(cmd) :
2487 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2488
2489 eth_proto_new = eth_proto_new & eth_proto_cap;
2490 if (!eth_proto_new) {
b9d66a36 2491 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2492 return -EINVAL;
2493 }
56ade8fe 2494
401c8b4e
ER		 2495 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2496 eth_proto_new);
56ade8fe 2497 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2498 if (err)
56ade8fe 2499 return err;
56ade8fe 2500
6277d46b 2501 if (!netif_running(dev))
56ade8fe
JP		 2502 return 0;
2503
0c83f88c
IS		 2504 mlxsw_sp_port->link.autoneg = autoneg;
2505
b9d66a36
IS		 2506 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2507 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2508
2509 return 0;
2510}
2511
ce6ef68f
YG		 2512static int mlxsw_sp_flash_device(struct net_device *dev,
2513 struct ethtool_flash *flash)
2514{
2515 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2517 const struct firmware *firmware;
2518 int err;
2519
2520 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2521 return -EOPNOTSUPP;
2522
2523 dev_hold(dev);
2524 rtnl_unlock();
2525
2526 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2527 if (err)
2528 goto out;
2529 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2530 release_firmware(firmware);
2531out:
2532 rtnl_lock();
2533 dev_put(dev);
2534 return err;
2535}
2536
2ea10903
AS		 2537#define MLXSW_SP_QSFP_I2C_ADDR 0x50
2538
2539static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2540 u16 offset, u16 size, void *data,
2541 unsigned int *p_read_size)
2542{
2543 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2544 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2545 char mcia_pl[MLXSW_REG_MCIA_LEN];
2546 int status;
2547 int err;
2548
2549 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2550 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2551 0, 0, offset, size, MLXSW_SP_QSFP_I2C_ADDR);
2552
2553 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2554 if (err)
2555 return err;
2556
2557 status = mlxsw_reg_mcia_status_get(mcia_pl);
2558 if (status)
2559 return -EIO;
2560
2561 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2562 memcpy(data, eeprom_tmp, size);
2563 *p_read_size = size;
2564
2565 return 0;
2566}
2567
2568enum mlxsw_sp_eeprom_module_info_rev_id {
2569 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2570 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2571 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2572};
2573
2574enum mlxsw_sp_eeprom_module_info_id {
2575 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2576 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2577 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2578 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2579};
2580
2581enum mlxsw_sp_eeprom_module_info {
2582 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2583 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2584 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2585};
2586
2587static int mlxsw_sp_get_module_info(struct net_device *netdev,
2588 struct ethtool_modinfo *modinfo)
2589{
2590 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2591 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2592 u8 module_rev_id, module_id;
2593 unsigned int read_size;
2594 int err;
2595
2596 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2597 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2598 module_info, &read_size);
2599 if (err)
2600 return err;
2601
2602 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2603 return -EIO;
2604
2605 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2606 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2607
2608 switch (module_id) {
2609 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2610 modinfo->type = ETH_MODULE_SFF_8436;
2611 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2612 break;
2613 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2614 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2615 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2616 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2617 modinfo->type = ETH_MODULE_SFF_8636;
2618 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2619 } else {
2620 modinfo->type = ETH_MODULE_SFF_8436;
2621 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2622 }
2623 break;
2624 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2625 modinfo->type = ETH_MODULE_SFF_8472;
2626 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2627 break;
2628 default:
2629 return -EINVAL;
2630 }
2631
2632 return 0;
2633}
2634
2635static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2636 struct ethtool_eeprom *ee,
2637 u8 *data)
2638{
2639 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2640 int offset = ee->offset;
2641 unsigned int read_size;
2642 int i = 0;
2643 int err;
2644
2645 if (!ee->len)
2646 return -EINVAL;
2647
2648 memset(data, 0, ee->len);
2649
2650 while (i < ee->len) {
2651 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2652 ee->len - i, data + i,
2653 &read_size);
2654 if (err) {
2655 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2656 return err;
2657 }
2658
2659 i += read_size;
2660 offset += read_size;
2661 }
2662
2663 return 0;
2664}
2665
56ade8fe
JP		 2666static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2667 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2668 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2669 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2670 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2671 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2672 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2673 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2674 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2675 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2676 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
ce6ef68f 2677 .flash_device = mlxsw_sp_flash_device,
2ea10903
AS		 2678 .get_module_info = mlxsw_sp_get_module_info,
2679 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
56ade8fe
JP		 2680};
2681
18f1e70c
IS		 2682static int
2683mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2684{
2685 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2686 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2687 char ptys_pl[MLXSW_REG_PTYS_LEN];
2688 u32 eth_proto_admin;
2689
2690 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
401c8b4e
ER		 2691 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2692 eth_proto_admin);
18f1e70c
IS		 2693 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2694}
2695
8e8dfe9f
IS		 2696int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2697 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2698 bool dwrr, u8 dwrr_weight)
90183b98
IS		 2699{
2700 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2701 char qeec_pl[MLXSW_REG_QEEC_LEN];
2702
2703 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2704 next_index);
2705 mlxsw_reg_qeec_de_set(qeec_pl, true);
2706 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2707 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2708 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2709}
2710
cc7cf517
IS		 2711int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2712 enum mlxsw_reg_qeec_hr hr, u8 index,
2713 u8 next_index, u32 maxrate)
90183b98
IS		 2714{
2715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2716 char qeec_pl[MLXSW_REG_QEEC_LEN];
2717
2718 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2719 next_index);
2720 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2721 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2722 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2723}
2724
8e8dfe9f
IS		 2725int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2726 u8 switch_prio, u8 tclass)
90183b98
IS		 2727{
2728 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2729 char qtct_pl[MLXSW_REG_QTCT_LEN];
2730
2731 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2732 tclass);
2733 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2734}
2735
2736static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2737{
2738 int err, i;
2739
2740 /* Setup the elements hierarcy, so that each TC is linked to
2741 * one subgroup, which are all member in the same group.
2742 */
2743 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2744 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2745 0);
2746 if (err)
2747 return err;
2748 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2749 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2750 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2751 0, false, 0);
2752 if (err)
2753 return err;
2754 }
2755 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2756 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2757 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2758 false, 0);
2759 if (err)
2760 return err;
2761 }
2762
2763 /* Make sure the max shaper is disabled in all hierarcies that
2764 * support it.
2765 */
2766 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2767 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2768 MLXSW_REG_QEEC_MAS_DIS);
2769 if (err)
2770 return err;
2771 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2772 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2773 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2774 i, 0,
2775 MLXSW_REG_QEEC_MAS_DIS);
2776 if (err)
2777 return err;
2778 }
2779 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2780 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2781 MLXSW_REG_QEEC_HIERARCY_TC,
2782 i, i,
2783 MLXSW_REG_QEEC_MAS_DIS);
2784 if (err)
2785 return err;
2786 }
2787
2788 /* Map all priorities to traffic class 0. */
2789 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2790 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2791 if (err)
2792 return err;
2793 }
2794
2795 return 0;
2796}
2797
5b153859
IS		 2798static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2799 bool split, u8 module, u8 width, u8 lane)
56ade8fe 2800{
c57529e1 2801 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 2802 struct mlxsw_sp_port *mlxsw_sp_port;
2803 struct net_device *dev;
56ade8fe
JP		 2804 int err;
2805
5b153859
IS		 2806 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2807 if (err) {
2808 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2809 local_port);
2810 return err;
2811 }
2812
56ade8fe 2813 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
5b153859
IS		 2814 if (!dev) {
2815 err = -ENOMEM;
2816 goto err_alloc_etherdev;
2817 }
f20a91f1 2818 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 2819 mlxsw_sp_port = netdev_priv(dev);
2820 mlxsw_sp_port->dev = dev;
2821 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2822 mlxsw_sp_port->local_port = local_port;
c57529e1 2823 mlxsw_sp_port->pvid = 1;
18f1e70c 2824 mlxsw_sp_port->split = split;
d664b41e
IS		 2825 mlxsw_sp_port->mapping.module = module;
2826 mlxsw_sp_port->mapping.width = width;
2827 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 2828 mlxsw_sp_port->link.autoneg = 1;
31a08a52 2829 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
763b4b70 2830 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 2831
2832 mlxsw_sp_port->pcpu_stats =
2833 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2834 if (!mlxsw_sp_port->pcpu_stats) {
2835 err = -ENOMEM;
2836 goto err_alloc_stats;
2837 }
2838
98d0f7b9
YG		 2839 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2840 GFP_KERNEL);
2841 if (!mlxsw_sp_port->sample) {
2842 err = -ENOMEM;
2843 goto err_alloc_sample;
2844 }
2845
fc1bbb0f
NF		 2846 mlxsw_sp_port->hw_stats.cache =
2847 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2848
2849 if (!mlxsw_sp_port->hw_stats.cache) {
2850 err = -ENOMEM;
2851 goto err_alloc_hw_stats;
2852 }
2853 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2854 &update_stats_cache);
2855
56ade8fe
JP		 2856 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2857 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2858
2e915e0b 2859 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
5b153859
IS		 2860 if (err) {
2861 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2862 mlxsw_sp_port->local_port);
2863 goto err_port_module_map;
2864 }
2865
3247ff2b
IS		 2866 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2867 if (err) {
2868 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2869 mlxsw_sp_port->local_port);
2870 goto err_port_swid_set;
2871 }
2872
56ade8fe
JP		 2873 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2874 if (err) {
2875 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2876 mlxsw_sp_port->local_port);
2877 goto err_dev_addr_init;
2878 }
2879
2880 netif_carrier_off(dev);
2881
2882 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 2883 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2884 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 2885
d894be57
JW		 2886 dev->min_mtu = 0;
2887 dev->max_mtu = ETH_MAX_MTU;
2888
56ade8fe
JP		 2889 /* Each packet needs to have a Tx header (metadata) on top all other
2890 * headers.
2891 */
feb7d387 2892 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 2893
56ade8fe
JP		 2894 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2895 if (err) {
2896 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2897 mlxsw_sp_port->local_port);
2898 goto err_port_system_port_mapping_set;
2899 }
2900
18f1e70c
IS		 2901 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2902 if (err) {
2903 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2904 mlxsw_sp_port->local_port);
2905 goto err_port_speed_by_width_set;
2906 }
2907
56ade8fe
JP		 2908 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2909 if (err) {
2910 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2911 mlxsw_sp_port->local_port);
2912 goto err_port_mtu_set;
2913 }
2914
2915 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2916 if (err)
2917 goto err_port_admin_status_set;
2918
2919 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2920 if (err) {
2921 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2922 mlxsw_sp_port->local_port);
2923 goto err_port_buffers_init;
2924 }
2925
90183b98
IS		 2926 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2927 if (err) {
2928 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2929 mlxsw_sp_port->local_port);
2930 goto err_port_ets_init;
2931 }
2932
f00817df
IS		 2933 /* ETS and buffers must be initialized before DCB. */
2934 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2935 if (err) {
2936 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2937 mlxsw_sp_port->local_port);
2938 goto err_port_dcb_init;
2939 }
2940
a1107487 2941 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
45a4a16c 2942 if (err) {
a1107487 2943 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
45a4a16c 2944 mlxsw_sp_port->local_port);
a1107487 2945 goto err_port_fids_init;
45a4a16c
IS		 2946 }
2947
c57529e1
IS		 2948 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2949 if (IS_ERR(mlxsw_sp_port_vlan)) {
2950 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
05978481 2951 mlxsw_sp_port->local_port);
c57529e1 2952 goto err_port_vlan_get;
05978481
IS		 2953 }
2954
56ade8fe 2955 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 2956 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 2957 err = register_netdev(dev);
2958 if (err) {
2959 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2960 mlxsw_sp_port->local_port);
2961 goto err_register_netdev;
2962 }
2963
d808c7e4
ER		 2964 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2965 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2966 module);
fc1bbb0f 2967 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
56ade8fe
JP		 2968 return 0;
2969
56ade8fe 2970err_register_netdev:
2f25844c 2971 mlxsw_sp->ports[local_port] = NULL;
0583272d 2972 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1
IS		 2973 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2974err_port_vlan_get:
a1107487
IS		 2975 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2976err_port_fids_init:
4de34eb5 2977 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 2978err_port_dcb_init:
90183b98 2979err_port_ets_init:
56ade8fe
JP		 2980err_port_buffers_init:
2981err_port_admin_status_set:
2982err_port_mtu_set:
18f1e70c 2983err_port_speed_by_width_set:
56ade8fe 2984err_port_system_port_mapping_set:
56ade8fe 2985err_dev_addr_init:
3247ff2b
IS		 2986 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2987err_port_swid_set:
2e915e0b 2988 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
5b153859 2989err_port_module_map:
fc1bbb0f
NF		 2990 kfree(mlxsw_sp_port->hw_stats.cache);
2991err_alloc_hw_stats:
98d0f7b9
YG		 2992 kfree(mlxsw_sp_port->sample);
2993err_alloc_sample:
56ade8fe
JP		 2994 free_percpu(mlxsw_sp_port->pcpu_stats);
2995err_alloc_stats:
2996 free_netdev(dev);
5b153859 2997err_alloc_etherdev:
67963a33
JP		 2998 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2999 return err;
3000}
3001
5b153859 3002static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
56ade8fe
JP		 3003{
3004 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3005
fc1bbb0f 3006 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
67963a33 3007 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
56ade8fe 3008 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 3009 mlxsw_sp->ports[local_port] = NULL;
0583272d 3010 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1 3011 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
a1107487 3012 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
f00817df 3013 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8 3014 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2e915e0b 3015 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
fc1bbb0f 3016 kfree(mlxsw_sp_port->hw_stats.cache);
98d0f7b9 3017 kfree(mlxsw_sp_port->sample);
136f1445 3018 free_percpu(mlxsw_sp_port->pcpu_stats);
31a08a52 3019 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
56ade8fe 3020 free_netdev(mlxsw_sp_port->dev);
67963a33
JP		 3021 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3022}
3023
f83e2102
JP		 3024static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3025{
3026 return mlxsw_sp->ports[local_port] != NULL;
3027}
3028
56ade8fe
JP		 3029static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3030{
3031 int i;
3032
5ec2ee7d 3033 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
f83e2102
JP		 3034 if (mlxsw_sp_port_created(mlxsw_sp, i))
3035 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d 3036 kfree(mlxsw_sp->port_to_module);
56ade8fe
JP		 3037 kfree(mlxsw_sp->ports);
3038}
3039
3040static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3041{
5ec2ee7d 3042 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
d664b41e 3043 u8 module, width, lane;
56ade8fe
JP		 3044 size_t alloc_size;
3045 int i;
3046 int err;
3047
5ec2ee7d 3048 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
56ade8fe
JP		 3049 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3050 if (!mlxsw_sp->ports)
3051 return -ENOMEM;
3052
5ec2ee7d
IS		 3053 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
3054 if (!mlxsw_sp->port_to_module) {
3055 err = -ENOMEM;
3056 goto err_port_to_module_alloc;
3057 }
3058
3059 for (i = 1; i < max_ports; i++) {
558c2d5e 3060 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 3061 &width, &lane);
558c2d5e
IS		 3062 if (err)
3063 goto err_port_module_info_get;
3064 if (!width)
3065 continue;
3066 mlxsw_sp->port_to_module[i] = module;
67963a33
JP		 3067 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3068 module, width, lane);
56ade8fe
JP		 3069 if (err)
3070 goto err_port_create;
3071 }
3072 return 0;
3073
3074err_port_create:
558c2d5e 3075err_port_module_info_get:
56ade8fe 3076 for (i--; i >= 1; i--)
f83e2102
JP		 3077 if (mlxsw_sp_port_created(mlxsw_sp, i))
3078 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d
IS		 3079 kfree(mlxsw_sp->port_to_module);
3080err_port_to_module_alloc:
56ade8fe
JP		 3081 kfree(mlxsw_sp->ports);
3082 return err;
3083}
3084
18f1e70c
IS		 3085static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3086{
3087 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3088
3089 return local_port - offset;
3090}
3091
be94535f
IS		 3092static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3093 u8 module, unsigned int count)
3094{
3095 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3096 int err, i;
3097
be94535f
IS		 3098 for (i = 0; i < count; i++) {
3099 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 3100 module, width, i * width);
be94535f
IS		 3101 if (err)
3102 goto err_port_create;
3103 }
3104
3105 return 0;
3106
3107err_port_create:
3108 for (i--; i >= 0; i--)
f83e2102
JP		 3109 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3110 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
be94535f
IS		 3111 return err;
3112}
3113
3114static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3115 u8 base_port, unsigned int count)
3116{
3117 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3118 int i;
3119
3120 /* Split by four means we need to re-create two ports, otherwise
3121 * only one.
3122 */
3123 count = count / 2;
3124
be94535f
IS		 3125 for (i = 0; i < count; i++) {
3126 local_port = base_port + i * 2;
3127 module = mlxsw_sp->port_to_module[local_port];
3128
3129 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 3130 width, 0);
be94535f
IS		 3131 }
3132}
3133
b2f10571
JP		 3134static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3135 unsigned int count)
18f1e70c 3136{
b2f10571 3137 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3138 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 3139 u8 module, cur_width, base_port;
3140 int i;
3141 int err;
3142
3143 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3144 if (!mlxsw_sp_port) {
3145 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3146 local_port);
3147 return -EINVAL;
3148 }
3149
d664b41e
IS		 3150 module = mlxsw_sp_port->mapping.module;
3151 cur_width = mlxsw_sp_port->mapping.width;
3152
18f1e70c
IS		 3153 if (count != 2 && count != 4) {
3154 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3155 return -EINVAL;
3156 }
3157
18f1e70c
IS		 3158 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3159 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3160 return -EINVAL;
3161 }
3162
3163 /* Make sure we have enough slave (even) ports for the split. */
3164 if (count == 2) {
3165 base_port = local_port;
3166 if (mlxsw_sp->ports[base_port + 1]) {
3167 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3168 return -EINVAL;
3169 }
3170 } else {
3171 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3172 if (mlxsw_sp->ports[base_port + 1] ||
3173 mlxsw_sp->ports[base_port + 3]) {
3174 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3175 return -EINVAL;
3176 }
3177 }
3178
3179 for (i = 0; i < count; i++)
f83e2102
JP		 3180 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3181 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3182
be94535f
IS		 3183 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3184 if (err) {
3185 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3186 goto err_port_split_create;
18f1e70c
IS		 3187 }
3188
3189 return 0;
3190
be94535f
IS		 3191err_port_split_create:
3192 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3193 return err;
3194}
3195
b2f10571 3196static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 3197{
b2f10571 3198 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3199 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 3200 u8 cur_width, base_port;
18f1e70c
IS		 3201 unsigned int count;
3202 int i;
18f1e70c
IS		 3203
3204 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3205 if (!mlxsw_sp_port) {
3206 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3207 local_port);
3208 return -EINVAL;
3209 }
3210
3211 if (!mlxsw_sp_port->split) {
3212 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3213 return -EINVAL;
3214 }
3215
d664b41e 3216 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 3217 count = cur_width == 1 ? 4 : 2;
3218
3219 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3220
3221 /* Determine which ports to remove. */
3222 if (count == 2 && local_port >= base_port + 2)
3223 base_port = base_port + 2;
3224
3225 for (i = 0; i < count; i++)
f83e2102
JP		 3226 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3227 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3228
be94535f 3229 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3230
3231 return 0;
3232}
3233
56ade8fe
JP		 3234static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3235 char *pude_pl, void *priv)
3236{
3237 struct mlxsw_sp *mlxsw_sp = priv;
3238 struct mlxsw_sp_port *mlxsw_sp_port;
3239 enum mlxsw_reg_pude_oper_status status;
3240 u8 local_port;
3241
3242 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3243 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 3244 if (!mlxsw_sp_port)
56ade8fe 3245 return;
56ade8fe
JP		 3246
3247 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3248 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3249 netdev_info(mlxsw_sp_port->dev, "link up\n");
3250 netif_carrier_on(mlxsw_sp_port->dev);
3251 } else {
3252 netdev_info(mlxsw_sp_port->dev, "link down\n");
3253 netif_carrier_off(mlxsw_sp_port->dev);
3254 }
3255}
3256
14eeda99
NF		 3257static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3258 u8 local_port, void *priv)
56ade8fe
JP		 3259{
3260 struct mlxsw_sp *mlxsw_sp = priv;
3261 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3262 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3263
3264 if (unlikely(!mlxsw_sp_port)) {
3265 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3266 local_port);
3267 return;
3268 }
3269
3270 skb->dev = mlxsw_sp_port->dev;
3271
3272 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3273 u64_stats_update_begin(&pcpu_stats->syncp);
3274 pcpu_stats->rx_packets++;
3275 pcpu_stats->rx_bytes += skb->len;
3276 u64_stats_update_end(&pcpu_stats->syncp);
3277
3278 skb->protocol = eth_type_trans(skb, skb->dev);
3279 netif_receive_skb(skb);
3280}
3281
1c6c6d22
IS		 3282static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3283 void *priv)
3284{
3285 skb->offload_fwd_mark = 1;
14eeda99 3286 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
1c6c6d22
IS		 3287}
3288
98d0f7b9
YG		 3289static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3290 void *priv)
3291{
3292 struct mlxsw_sp *mlxsw_sp = priv;
3293 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3294 struct psample_group *psample_group;
3295 u32 size;
3296
3297 if (unlikely(!mlxsw_sp_port)) {
3298 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3299 local_port);
3300 goto out;
3301 }
3302 if (unlikely(!mlxsw_sp_port->sample)) {
3303 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3304 local_port);
3305 goto out;
3306 }
3307
3308 size = mlxsw_sp_port->sample->truncate ?
3309 mlxsw_sp_port->sample->trunc_size : skb->len;
3310
3311 rcu_read_lock();
3312 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3313 if (!psample_group)
3314 goto out_unlock;
3315 psample_sample_packet(psample_group, skb, size,
3316 mlxsw_sp_port->dev->ifindex, 0,
3317 mlxsw_sp_port->sample->rate);
3318out_unlock:
3319 rcu_read_unlock();
3320out:
3321 consume_skb(skb);
3322}
3323
117b0dad 3324#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
0fb78a4e 3325 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
117b0dad 3326 _is_ctrl, SP_##_trap_group, DISCARD)
14eeda99 3327
117b0dad 3328#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
14eeda99 3329 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
117b0dad
NF		 3330 _is_ctrl, SP_##_trap_group, DISCARD)
3331
3332#define MLXSW_SP_EVENTL(_func, _trap_id) \
3333 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
93393b33 3334
4544913e
NF		 3335static const struct mlxsw_listener mlxsw_sp_listener[] = {
3336 /* Events */
117b0dad 3337 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
ee4a60d8 3338 /* L2 traps */
117b0dad
NF		 3339 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3340 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3341 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3342 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3343 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3344 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3345 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3346 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3347 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3348 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3349 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
9d41accc 3350 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
588823f9
AS		 3351 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3352 false),
3353 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3354 false),
3355 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3356 false),
3357 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3358 false),
93393b33 3359 /* L3 traps */
0fcc4847
IS		 3360 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3361 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3362 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
0fcc4847 3363 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
8d54814e
AS		 3364 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3365 false),
3366 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3367 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3368 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3369 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3370 false),
3371 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3372 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3373 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
0fcc4847 3374 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
8d54814e
AS		 3375 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3376 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3377 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3378 false),
3379 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3380 false),
3381 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3382 false),
3383 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3384 false),
3385 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3386 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3387 false),
3388 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3389 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
7607dd35 3390 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
8d54814e 3391 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
98d0f7b9
YG		 3392 /* PKT Sample trap */
3393 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
0db7b386
JP		 3394 false, SP_IP2ME, DISCARD),
3395 /* ACL trap */
3396 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
56ade8fe
JP		 3397};
3398
9148e7cf
NF		 3399static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3400{
3401 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3402 enum mlxsw_reg_qpcr_ir_units ir_units;
3403 int max_cpu_policers;
3404 bool is_bytes;
3405 u8 burst_size;
3406 u32 rate;
3407 int i, err;
3408
3409 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3410 return -EIO;
3411
3412 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3413
3414 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3415 for (i = 0; i < max_cpu_policers; i++) {
3416 is_bytes = false;
3417 switch (i) {
3418 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3419 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3420 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3421 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3422 rate = 128;
3423 burst_size = 7;
3424 break;
3425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
588823f9 3426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
9148e7cf
NF		 3427 rate = 16 * 1024;
3428 burst_size = 10;
3429 break;
8d54814e 3430 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
9148e7cf
NF		 3431 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3432 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
8d54814e 3433 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
9148e7cf
NF		 3434 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3435 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
8d54814e 3436 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
9148e7cf
NF		 3437 rate = 1024;
3438 burst_size = 7;
3439 break;
3440 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3441 is_bytes = true;
3442 rate = 4 * 1024;
3443 burst_size = 4;
3444 break;
3445 default:
3446 continue;
3447 }
3448
3449 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3450 burst_size);
3451 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3452 if (err)
3453 return err;
3454 }
3455
3456 return 0;
3457}
3458
579c82e4 3459static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
56ade8fe
JP		 3460{
3461 char htgt_pl[MLXSW_REG_HTGT_LEN];
117b0dad 3462 enum mlxsw_reg_htgt_trap_group i;
9148e7cf 3463 int max_cpu_policers;
579c82e4
NF		 3464 int max_trap_groups;
3465 u8 priority, tc;
9148e7cf 3466 u16 policer_id;
117b0dad 3467 int err;
579c82e4
NF		 3468
3469 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3470 return -EIO;
3471
3472 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
9148e7cf 3473 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
579c82e4
NF		 3474
3475 for (i = 0; i < max_trap_groups; i++) {
9148e7cf 3476 policer_id = i;
579c82e4 3477 switch (i) {
117b0dad
NF		 3478 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3479 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3480 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3481 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3482 priority = 5;
3483 tc = 5;
3484 break;
8d54814e 3485 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
117b0dad
NF		 3486 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3487 priority = 4;
3488 tc = 4;
3489 break;
3490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3491 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
588823f9 3492 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
117b0dad
NF		 3493 priority = 3;
3494 tc = 3;
3495 break;
3496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
8d54814e 3497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
117b0dad
NF		 3498 priority = 2;
3499 tc = 2;
3500 break;
8d54814e 3501 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
117b0dad
NF		 3502 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3503 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3504 priority = 1;
3505 tc = 1;
3506 break;
3507 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
579c82e4
NF		 3508 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3509 tc = MLXSW_REG_HTGT_DEFAULT_TC;
9148e7cf 3510 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
579c82e4
NF		 3511 break;
3512 default:
3513 continue;
3514 }
117b0dad 3515
9148e7cf
NF		 3516 if (max_cpu_policers <= policer_id &&
3517 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3518 return -EIO;
3519
3520 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
579c82e4
NF		 3521 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3522 if (err)
3523 return err;
3524 }
3525
3526 return 0;
3527}
3528
3529static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3530{
56ade8fe
JP		 3531 int i;
3532 int err;
3533
9148e7cf
NF		 3534 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3535 if (err)
3536 return err;
3537
579c82e4 3538 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
56ade8fe
JP		 3539 if (err)
3540 return err;
3541
4544913e 3542 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3543 err = mlxsw_core_trap_register(mlxsw_sp->core,
4544913e 3544 &mlxsw_sp_listener[i],
14eeda99 3545 mlxsw_sp);
56ade8fe 3546 if (err)
4544913e 3547 goto err_listener_register;
56ade8fe 3548
56ade8fe
JP		 3549 }
3550 return 0;
3551
4544913e 3552err_listener_register:
56ade8fe 3553 for (i--; i >= 0; i--) {
14eeda99 3554 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3555 &mlxsw_sp_listener[i],
14eeda99 3556 mlxsw_sp);
56ade8fe
JP		 3557 }
3558 return err;
3559}
3560
3561static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3562{
56ade8fe
JP		 3563 int i;
3564
4544913e 3565 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3566 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3567 &mlxsw_sp_listener[i],
14eeda99 3568 mlxsw_sp);
56ade8fe
JP		 3569 }
3570}
3571
0d65fc13
JP		 3572static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3573{
3574 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 3575 int err;
0d65fc13
JP		 3576
3577 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3578 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3579 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3580 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3581 MLXSW_REG_SLCR_LAG_HASH_SIP |
3582 MLXSW_REG_SLCR_LAG_HASH_DIP |
3583 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3584 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3585 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 3586 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3587 if (err)
3588 return err;
3589
c1a38311
JP		 3590 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3591 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 3592 return -EIO;
3593
c1a38311 3594 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 3595 sizeof(struct mlxsw_sp_upper),
3596 GFP_KERNEL);
3597 if (!mlxsw_sp->lags)
3598 return -ENOMEM;
3599
3600 return 0;
3601}
3602
3603static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3604{
3605 kfree(mlxsw_sp->lags);
0d65fc13
JP		 3606}
3607
9d87fcea
NF		 3608static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3609{
3610 char htgt_pl[MLXSW_REG_HTGT_LEN];
3611
579c82e4
NF		 3612 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3613 MLXSW_REG_HTGT_INVALID_POLICER,
3614 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3615 MLXSW_REG_HTGT_DEFAULT_TC);
9d87fcea
NF		 3616 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3617}
3618
b2f10571 3619static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 3620 const struct mlxsw_bus_info *mlxsw_bus_info)
3621{
b2f10571 3622 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 3623 int err;
3624
3625 mlxsw_sp->core = mlxsw_core;
3626 mlxsw_sp->bus_info = mlxsw_bus_info;
3627
6b742199
YG		 3628 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3629 if (err) {
3630 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3631 return err;
3632 }
3633
56ade8fe
JP		 3634 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3635 if (err) {
3636 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3637 return err;
3638 }
3639
a1107487 3640 err = mlxsw_sp_fids_init(mlxsw_sp);
56ade8fe 3641 if (err) {
a1107487 3642 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
4544913e 3643 return err;
56ade8fe
JP		 3644 }
3645
a1107487 3646 err = mlxsw_sp_traps_init(mlxsw_sp);
56ade8fe 3647 if (err) {
a1107487
IS		 3648 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3649 goto err_traps_init;
56ade8fe
JP		 3650 }
3651
3652 err = mlxsw_sp_buffers_init(mlxsw_sp);
3653 if (err) {
3654 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3655 goto err_buffers_init;
3656 }
3657
0d65fc13
JP		 3658 err = mlxsw_sp_lag_init(mlxsw_sp);
3659 if (err) {
3660 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3661 goto err_lag_init;
3662 }
3663
56ade8fe
JP		 3664 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3665 if (err) {
3666 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3667 goto err_switchdev_init;
3668 }
3669
464dce18
IS		 3670 err = mlxsw_sp_router_init(mlxsw_sp);
3671 if (err) {
3672 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3673 goto err_router_init;
3674 }
3675
763b4b70
YG		 3676 err = mlxsw_sp_span_init(mlxsw_sp);
3677 if (err) {
3678 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3679 goto err_span_init;
3680 }
3681
22a67766
JP		 3682 err = mlxsw_sp_acl_init(mlxsw_sp);
3683 if (err) {
3684 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3685 goto err_acl_init;
3686 }
3687
ff7b0d27
AS		 3688 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3689 if (err) {
3690 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3691 goto err_counter_pool_init;
3692 }
3693
230ead01
AS		 3694 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3695 if (err) {
3696 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3697 goto err_dpipe_init;
3698 }
3699
bbf2a475
IS		 3700 err = mlxsw_sp_ports_create(mlxsw_sp);
3701 if (err) {
3702 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3703 goto err_ports_create;
3704 }
3705
56ade8fe
JP		 3706 return 0;
3707
bbf2a475 3708err_ports_create:
230ead01
AS		 3709 mlxsw_sp_dpipe_fini(mlxsw_sp);
3710err_dpipe_init:
ff7b0d27
AS		 3711 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3712err_counter_pool_init:
22a67766
JP		 3713 mlxsw_sp_acl_fini(mlxsw_sp);
3714err_acl_init:
763b4b70
YG		 3715 mlxsw_sp_span_fini(mlxsw_sp);
3716err_span_init:
464dce18
IS		 3717 mlxsw_sp_router_fini(mlxsw_sp);
3718err_router_init:
bbf2a475 3719 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 3720err_switchdev_init:
ce0bd2b0 3721 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 3722err_lag_init:
0f433fa0 3723 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3724err_buffers_init:
56ade8fe 3725 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487
IS		 3726err_traps_init:
3727 mlxsw_sp_fids_fini(mlxsw_sp);
56ade8fe
JP		 3728 return err;
3729}
3730
b2f10571 3731static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 3732{
b2f10571 3733 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 3734
bbf2a475 3735 mlxsw_sp_ports_remove(mlxsw_sp);
230ead01 3736 mlxsw_sp_dpipe_fini(mlxsw_sp);
ff7b0d27 3737 mlxsw_sp_counter_pool_fini(mlxsw_sp);
22a67766 3738 mlxsw_sp_acl_fini(mlxsw_sp);
763b4b70 3739 mlxsw_sp_span_fini(mlxsw_sp);
464dce18 3740 mlxsw_sp_router_fini(mlxsw_sp);
56ade8fe 3741 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 3742 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 3743 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3744 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487 3745 mlxsw_sp_fids_fini(mlxsw_sp);
56ade8fe
JP		 3746}
3747
3748static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3749 .used_max_vepa_channels = 1,
3750 .max_vepa_channels = 0,
56ade8fe 3751 .used_max_mid = 1,
53ae6283 3752 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 3753 .used_max_pgt = 1,
3754 .max_pgt = 0,
56ade8fe
JP		 3755 .used_flood_tables = 1,
3756 .used_flood_mode = 1,
3757 .flood_mode = 3,
71c365bd 3758 .max_fid_offset_flood_tables = 3,
56ade8fe 3759 .fid_offset_flood_table_size = VLAN_N_VID - 1,
71c365bd 3760 .max_fid_flood_tables = 3,
a1107487 3761 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
56ade8fe
JP		 3762 .used_max_ib_mc = 1,
3763 .max_ib_mc = 0,
3764 .used_max_pkey = 1,
3765 .max_pkey = 0,
403547d3
NF		 3766 .used_kvd_split_data = 1,
3767 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3768 .kvd_hash_single_parts = 2,
3769 .kvd_hash_double_parts = 1,
c6022427 3770 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 3771 .swid_config = {
3772 {
3773 .used_type = 1,
3774 .type = MLXSW_PORT_SWID_TYPE_ETH,
3775 }
3776 },
57d316ba 3777 .resource_query_enable = 1,
56ade8fe
JP		 3778};
3779
3780static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 3781 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 3782 .priv_size = sizeof(struct mlxsw_sp),
3783 .init = mlxsw_sp_init,
3784 .fini = mlxsw_sp_fini,
9d87fcea 3785 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
2d0ed39f
JP		 3786 .port_split = mlxsw_sp_port_split,
3787 .port_unsplit = mlxsw_sp_port_unsplit,
3788 .sb_pool_get = mlxsw_sp_sb_pool_get,
3789 .sb_pool_set = mlxsw_sp_sb_pool_set,
3790 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3791 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3792 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3793 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3794 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3795 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3796 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3797 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3798 .txhdr_construct = mlxsw_sp_txhdr_construct,
3799 .txhdr_len = MLXSW_TXHDR_LEN,
3800 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 3801};
3802
22a67766 3803bool mlxsw_sp_port_dev_check(const struct net_device *dev)
7ce856aa
JP		 3804{
3805 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3806}
3807
1182e536 3808static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
dd82364c 3809{
1182e536 3810 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
dd82364c
DA		 3811 int ret = 0;
3812
3813 if (mlxsw_sp_port_dev_check(lower_dev)) {
1182e536 3814 *p_mlxsw_sp_port = netdev_priv(lower_dev);
dd82364c
DA		 3815 ret = 1;
3816 }
3817
3818 return ret;
3819}
3820
c57529e1 3821struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
7ce856aa 3822{
1182e536 3823 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 3824
3825 if (mlxsw_sp_port_dev_check(dev))
3826 return netdev_priv(dev);
3827
1182e536
JP		 3828 mlxsw_sp_port = NULL;
3829 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
dd82364c 3830
1182e536 3831 return mlxsw_sp_port;
7ce856aa
JP		 3832}
3833
4724ba56 3834struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
7ce856aa
JP		 3835{
3836 struct mlxsw_sp_port *mlxsw_sp_port;
3837
3838 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3839 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3840}
3841
af061378 3842struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
7ce856aa 3843{
1182e536 3844 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 3845
3846 if (mlxsw_sp_port_dev_check(dev))
3847 return netdev_priv(dev);
3848
1182e536
JP		 3849 mlxsw_sp_port = NULL;
3850 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3851 &mlxsw_sp_port);
dd82364c 3852
1182e536 3853 return mlxsw_sp_port;
7ce856aa
JP		 3854}
3855
3856struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3857{
3858 struct mlxsw_sp_port *mlxsw_sp_port;
3859
3860 rcu_read_lock();
3861 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3862 if (mlxsw_sp_port)
3863 dev_hold(mlxsw_sp_port->dev);
3864 rcu_read_unlock();
3865 return mlxsw_sp_port;
3866}
3867
3868void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3869{
3870 dev_put(mlxsw_sp_port->dev);
3871}
3872
0d65fc13
JP		 3873static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3874{
3875 char sldr_pl[MLXSW_REG_SLDR_LEN];
3876
3877 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3878 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3879}
3880
3881static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3882{
3883 char sldr_pl[MLXSW_REG_SLDR_LEN];
3884
3885 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3886 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3887}
3888
3889static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3890 u16 lag_id, u8 port_index)
3891{
3892 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3893 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3894
3895 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3896 lag_id, port_index);
3897 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3898}
3899
3900static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3901 u16 lag_id)
3902{
3903 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3904 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3905
3906 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3907 lag_id);
3908 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3909}
3910
3911static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3912 u16 lag_id)
3913{
3914 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3915 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3916
3917 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3918 lag_id);
3919 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3920}
3921
3922static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3923 u16 lag_id)
3924{
3925 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3926 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3927
3928 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3929 lag_id);
3930 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3931}
3932
3933static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3934 struct net_device *lag_dev,
3935 u16 *p_lag_id)
3936{
3937 struct mlxsw_sp_upper *lag;
3938 int free_lag_id = -1;
c1a38311 3939 u64 max_lag;
0d65fc13
JP		 3940 int i;
3941
c1a38311
JP		 3942 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3943 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 3944 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3945 if (lag->ref_count) {
3946 if (lag->dev == lag_dev) {
3947 *p_lag_id = i;
3948 return 0;
3949 }
3950 } else if (free_lag_id < 0) {
3951 free_lag_id = i;
3952 }
3953 }
3954 if (free_lag_id < 0)
3955 return -EBUSY;
3956 *p_lag_id = free_lag_id;
3957 return 0;
3958}
3959
3960static bool
3961mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3962 struct net_device *lag_dev,
3963 struct netdev_lag_upper_info *lag_upper_info)
3964{
3965 u16 lag_id;
3966
3967 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3968 return false;
3969 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3970 return false;
3971 return true;
3972}
3973
3974static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3975 u16 lag_id, u8 *p_port_index)
3976{
c1a38311 3977 u64 max_lag_members;
0d65fc13
JP		 3978 int i;
3979
c1a38311
JP		 3980 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3981 MAX_LAG_MEMBERS);
3982 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 3983 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3984 *p_port_index = i;
3985 return 0;
3986 }
3987 }
3988 return -EBUSY;
3989}
3990
3991static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3992 struct net_device *lag_dev)
3993{
3994 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
c57529e1 3995 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
0d65fc13
JP		 3996 struct mlxsw_sp_upper *lag;
3997 u16 lag_id;
3998 u8 port_index;
3999 int err;
4000
4001 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4002 if (err)
4003 return err;
4004 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4005 if (!lag->ref_count) {
4006 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4007 if (err)
4008 return err;
4009 lag->dev = lag_dev;
4010 }
4011
4012 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4013 if (err)
4014 return err;
4015 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4016 if (err)
4017 goto err_col_port_add;
4018 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4019 if (err)
4020 goto err_col_port_enable;
4021
4022 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4023 mlxsw_sp_port->local_port);
4024 mlxsw_sp_port->lag_id = lag_id;
4025 mlxsw_sp_port->lagged = 1;
4026 lag->ref_count++;
86bf95b3 4027
c57529e1
IS		 4028 /* Port is no longer usable as a router interface */
4029 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4030 if (mlxsw_sp_port_vlan->fid)
a1107487 4031 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
86bf95b3 4032
0d65fc13
JP		 4033 return 0;
4034
51554db2
IS		 4035err_col_port_enable:
4036 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4037err_col_port_add:
4038 if (!lag->ref_count)
4039 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4040 return err;
4041}
4042
82e6db03
IS		 4043static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4044 struct net_device *lag_dev)
0d65fc13
JP		 4045{
4046 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4047 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4048 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4049
4050 if (!mlxsw_sp_port->lagged)
82e6db03 4051 return;
0d65fc13
JP		 4052 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4053 WARN_ON(lag->ref_count == 0);
4054
82e6db03
IS		 4055 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4056 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4057
c57529e1
IS		 4058 /* Any VLANs configured on the port are no longer valid */
4059 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4dc236c3 4060
fe3f6d14 4061 if (lag->ref_count == 1)
82e6db03 4062 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4063
4064 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4065 mlxsw_sp_port->local_port);
4066 mlxsw_sp_port->lagged = 0;
4067 lag->ref_count--;
86bf95b3 4068
c57529e1
IS		 4069 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4070 /* Make sure untagged frames are allowed to ingress */
4071 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
0d65fc13
JP		 4072}
4073
74581206
JP		 4074static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4075 u16 lag_id)
4076{
4077 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4078 char sldr_pl[MLXSW_REG_SLDR_LEN];
4079
4080 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4081 mlxsw_sp_port->local_port);
4082 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4083}
4084
4085static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4086 u16 lag_id)
4087{
4088 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4089 char sldr_pl[MLXSW_REG_SLDR_LEN];
4090
4091 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4092 mlxsw_sp_port->local_port);
4093 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4094}
4095
4096static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4097 bool lag_tx_enabled)
4098{
4099 if (lag_tx_enabled)
4100 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4101 mlxsw_sp_port->lag_id);
4102 else
4103 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4104 mlxsw_sp_port->lag_id);
4105}
4106
4107static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4108 struct netdev_lag_lower_state_info *info)
4109{
4110 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4111}
4112
2b94e58d
JP		 4113static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4114 bool enable)
4115{
4116 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4117 enum mlxsw_reg_spms_state spms_state;
4118 char *spms_pl;
4119 u16 vid;
4120 int err;
4121
4122 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4123 MLXSW_REG_SPMS_STATE_DISCARDING;
4124
4125 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4126 if (!spms_pl)
4127 return -ENOMEM;
4128 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4129
4130 for (vid = 0; vid < VLAN_N_VID; vid++)
4131 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4132
4133 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4134 kfree(spms_pl);
4135 return err;
4136}
4137
4138static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4139{
4140 int err;
4141
4aafc368 4142 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
2b94e58d
JP		 4143 if (err)
4144 return err;
4aafc368
IS		 4145 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4146 if (err)
4147 goto err_port_stp_set;
2b94e58d
JP		 4148 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4149 true, false);
4150 if (err)
4151 goto err_port_vlan_set;
4152 return 0;
4153
4154err_port_vlan_set:
4155 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368
IS		 4156err_port_stp_set:
4157 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4158 return err;
4159}
4160
4161static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4162{
4163 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4164 false, false);
4165 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368 4166 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4167}
4168
f0cebd81
IS		 4169static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4170 struct net_device *dev,
74581206 4171 unsigned long event, void *ptr)
56ade8fe 4172{
56ade8fe
JP		 4173 struct netdev_notifier_changeupper_info *info;
4174 struct mlxsw_sp_port *mlxsw_sp_port;
4175 struct net_device *upper_dev;
4176 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4177 int err = 0;
56ade8fe 4178
56ade8fe
JP		 4179 mlxsw_sp_port = netdev_priv(dev);
4180 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4181 info = ptr;
4182
4183 switch (event) {
4184 case NETDEV_PRECHANGEUPPER:
4185 upper_dev = info->upper_dev;
59fe9b3f
IS		 4186 if (!is_vlan_dev(upper_dev) &&
4187 !netif_is_lag_master(upper_dev) &&
7179eb5a 4188 !netif_is_bridge_master(upper_dev) &&
2b94e58d 4189 !netif_is_ovs_master(upper_dev))
59fe9b3f 4190 return -EINVAL;
6ec43904 4191 if (!info->linking)
0d65fc13 4192 break;
0d65fc13
JP		 4193 if (netif_is_lag_master(upper_dev) &&
4194 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4195 info->upper_info))
80bedf1a 4196 return -EINVAL;
6ec43904
IS		 4197 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4198 return -EINVAL;
4199 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4200 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4201 return -EINVAL;
2b94e58d
JP		 4202 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4203 return -EINVAL;
4204 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4205 return -EINVAL;
56ade8fe
JP		 4206 break;
4207 case NETDEV_CHANGEUPPER:
4208 upper_dev = info->upper_dev;
c57529e1 4209 if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4210 if (info->linking)
4211 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
f0cebd81 4212 lower_dev,
7117a570
IS		 4213 upper_dev);
4214 else
f0cebd81
IS		 4215 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4216 lower_dev,
4217 upper_dev);
0d65fc13 4218 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4219 if (info->linking)
0d65fc13
JP		 4220 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4221 upper_dev);
80bedf1a 4222 else
82e6db03
IS		 4223 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4224 upper_dev);
2b94e58d
JP		 4225 } else if (netif_is_ovs_master(upper_dev)) {
4226 if (info->linking)
4227 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4228 else
4229 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
56ade8fe
JP		 4230 }
4231 break;
4232 }
4233
80bedf1a 4234 return err;
56ade8fe
JP		 4235}
4236
74581206
JP		 4237static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4238 unsigned long event, void *ptr)
4239{
4240 struct netdev_notifier_changelowerstate_info *info;
4241 struct mlxsw_sp_port *mlxsw_sp_port;
4242 int err;
4243
4244 mlxsw_sp_port = netdev_priv(dev);
4245 info = ptr;
4246
4247 switch (event) {
4248 case NETDEV_CHANGELOWERSTATE:
4249 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4250 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4251 info->lower_state_info);
4252 if (err)
4253 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4254 }
4255 break;
4256 }
4257
80bedf1a 4258 return 0;
74581206
JP		 4259}
4260
f0cebd81
IS		 4261static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4262 struct net_device *port_dev,
74581206
JP		 4263 unsigned long event, void *ptr)
4264{
4265 switch (event) {
4266 case NETDEV_PRECHANGEUPPER:
4267 case NETDEV_CHANGEUPPER:
f0cebd81
IS		 4268 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4269 event, ptr);
74581206 4270 case NETDEV_CHANGELOWERSTATE:
f0cebd81
IS		 4271 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4272 ptr);
74581206
JP		 4273 }
4274
80bedf1a 4275 return 0;
74581206
JP		 4276}
4277
0d65fc13
JP		 4278static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4279 unsigned long event, void *ptr)
4280{
4281 struct net_device *dev;
4282 struct list_head *iter;
4283 int ret;
4284
4285 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4286 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4287 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4288 ptr);
80bedf1a 4289 if (ret)
0d65fc13
JP		 4290 return ret;
4291 }
4292 }
4293
80bedf1a 4294 return 0;
0d65fc13
JP		 4295}
4296
f0cebd81
IS		 4297static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4298 struct net_device *dev,
4299 unsigned long event, void *ptr,
4300 u16 vid)
26f0e7fb
IS		 4301{
4302 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4303 struct netdev_notifier_changeupper_info *info = ptr;
26f0e7fb 4304 struct net_device *upper_dev;
80bedf1a 4305 int err = 0;
26f0e7fb 4306
26f0e7fb
IS		 4307 switch (event) {
4308 case NETDEV_PRECHANGEUPPER:
4309 upper_dev = info->upper_dev;
b1e45526 4310 if (!netif_is_bridge_master(upper_dev))
80bedf1a 4311 return -EINVAL;
26f0e7fb
IS		 4312 break;
4313 case NETDEV_CHANGEUPPER:
4314 upper_dev = info->upper_dev;
1f88061e
IS		 4315 if (netif_is_bridge_master(upper_dev)) {
4316 if (info->linking)
c57529e1
IS		 4317 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4318 vlan_dev,
4319 upper_dev);
1f88061e 4320 else
c57529e1
IS		 4321 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4322 vlan_dev,
4323 upper_dev);
26f0e7fb 4324 } else {
1f88061e
IS		 4325 err = -EINVAL;
4326 WARN_ON(1);
26f0e7fb 4327 }
1f88061e 4328 break;
26f0e7fb
IS		 4329 }
4330
80bedf1a 4331 return err;
26f0e7fb
IS		 4332}
4333
f0cebd81
IS		 4334static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4335 struct net_device *lag_dev,
4336 unsigned long event,
4337 void *ptr, u16 vid)
272c4470
IS		 4338{
4339 struct net_device *dev;
4340 struct list_head *iter;
4341 int ret;
4342
4343 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4344 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4345 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4346 event, ptr,
4347 vid);
80bedf1a 4348 if (ret)
272c4470
IS		 4349 return ret;
4350 }
4351 }
4352
80bedf1a 4353 return 0;
272c4470
IS		 4354}
4355
26f0e7fb
IS		 4356static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4357 unsigned long event, void *ptr)
4358{
4359 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4360 u16 vid = vlan_dev_vlan_id(vlan_dev);
4361
272c4470 4362 if (mlxsw_sp_port_dev_check(real_dev))
f0cebd81
IS		 4363 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4364 event, ptr, vid);
272c4470 4365 else if (netif_is_lag_master(real_dev))
f0cebd81
IS		 4366 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4367 real_dev, event,
4368 ptr, vid);
26f0e7fb 4369
80bedf1a 4370 return 0;
26f0e7fb
IS		 4371}
4372
b1e45526
IS		 4373static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4374{
4375 struct netdev_notifier_changeupper_info *info = ptr;
4376
4377 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4378 return false;
4379 return netif_is_l3_master(info->upper_dev);
4380}
4381
0d65fc13
JP		 4382static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4383 unsigned long event, void *ptr)
4384{
4385 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
80bedf1a 4386 int err = 0;
0d65fc13 4387
6e095fd4
IS		 4388 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4389 err = mlxsw_sp_netdevice_router_port_event(dev);
b1e45526
IS		 4390 else if (mlxsw_sp_is_vrf_event(event, ptr))
4391 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6e095fd4 4392 else if (mlxsw_sp_port_dev_check(dev))
f0cebd81 4393 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
80bedf1a
IS		 4394 else if (netif_is_lag_master(dev))
4395 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4396 else if (is_vlan_dev(dev))
4397 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 4398
80bedf1a 4399 return notifier_from_errno(err);
0d65fc13
JP		 4400}
4401
56ade8fe
JP		 4402static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4403 .notifier_call = mlxsw_sp_netdevice_event,
4404};
4405
99724c18
IS		 4406static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4407 .notifier_call = mlxsw_sp_inetaddr_event,
4408 .priority = 10, /* Must be called before FIB notifier block */
4409};
4410
5ea1237f
AS		 4411static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4412 .notifier_call = mlxsw_sp_inet6addr_event,
4413};
4414
e7322638
JP		 4415static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4416 .notifier_call = mlxsw_sp_router_netevent_event,
4417};
4418
1d20d23c
JP		 4419static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4420 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4421 {0, },
4422};
4423
4424static struct pci_driver mlxsw_sp_pci_driver = {
4425 .name = mlxsw_sp_driver_name,
4426 .id_table = mlxsw_sp_pci_id_table,
4427};
4428
56ade8fe
JP		 4429static int __init mlxsw_sp_module_init(void)
4430{
4431 int err;
4432
4433 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
99724c18 4434 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5ea1237f 4435 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
e7322638
JP		 4436 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4437
56ade8fe
JP		 4438 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4439 if (err)
4440 goto err_core_driver_register;
1d20d23c
JP		 4441
4442 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4443 if (err)
4444 goto err_pci_driver_register;
4445
56ade8fe
JP		 4446 return 0;
4447
1d20d23c
JP		 4448err_pci_driver_register:
4449 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 4450err_core_driver_register:
e7322638 4451 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
5ea1237f 4452 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
de7d6295 4453 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4454 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4455 return err;
4456}
4457
4458static void __exit mlxsw_sp_module_exit(void)
4459{
1d20d23c 4460 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 4461 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
e7322638 4462 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
5ea1237f 4463 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
99724c18 4464 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4465 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4466}
4467
4468module_init(mlxsw_sp_module_init);
4469module_exit(mlxsw_sp_module_exit);
4470
4471MODULE_LICENSE("Dual BSD/GPL");
4472MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4473MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 4474MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
6b742199 4475MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);
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