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mlxsw: spectrum: Add FID get / set functions
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
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56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
7f71eb46 51#include <linux/list.h>
80bedf1a 52#include <linux/notifier.h>
90183b98 53#include <linux/dcbnl.h>
56ade8fe
JP		 54#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
56ade8fe
JP		 192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
be94535f
IS		 251static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
252 u8 swid)
56ade8fe 253{
56ade8fe
JP		 254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
be94535f 256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
56ade8fe
JP		 257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
be94535f
IS		 260static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
261{
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
263
264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
265 swid);
266}
267
56ade8fe
JP		 268static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
269 bool enable)
270{
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
273
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
276}
277
278int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
280 u16 vid)
281{
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
284
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
286 fid, vid);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
288}
289
290static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
292{
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
294 char *spvmlr_pl;
295 int err;
296
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
298 if (!spvmlr_pl)
299 return -ENOMEM;
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
301 learn_enable);
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
303 kfree(spvmlr_pl);
304 return err;
305}
306
307static int
308mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
309{
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
312
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
315}
316
d664b41e
IS		 317static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
56ade8fe 320{
56ade8fe
JP		 321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
322 int err;
323
558c2d5e 324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
326 if (err)
327 return err;
558c2d5e
IS		 328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 331 return 0;
332}
333
18f1e70c
IS		 334static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
336{
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
338 int i;
339
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
345 }
346
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
348}
349
3e9b27b8
IS		 350static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
351{
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
353
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357}
358
56ade8fe
JP		 359static int mlxsw_sp_port_open(struct net_device *dev)
360{
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
362 int err;
363
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
365 if (err)
366 return err;
367 netif_start_queue(dev);
368 return 0;
369}
370
371static int mlxsw_sp_port_stop(struct net_device *dev)
372{
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
374
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
377}
378
379static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
381{
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
387 .is_emad = false,
388 };
389 u64 len;
390 int err;
391
307c2431 392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 393 return NETDEV_TX_BUSY;
394
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
397
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
399 if (!skb) {
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
402 return NETDEV_TX_OK;
403 }
404 }
405
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
408 return NETDEV_TX_OK;
409 }
410
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
412 len = skb->len;
413 /* Due to a race we might fail here because of a full queue. In that
414 * unlikely case we simply drop the packet.
415 */
307c2431 416 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 417
418 if (!err) {
419 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
420 u64_stats_update_begin(&pcpu_stats->syncp);
421 pcpu_stats->tx_packets++;
422 pcpu_stats->tx_bytes += len;
423 u64_stats_update_end(&pcpu_stats->syncp);
424 } else {
425 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
426 dev_kfree_skb_any(skb);
427 }
428 return NETDEV_TX_OK;
429}
430
c5b9b518
JP		 431static void mlxsw_sp_set_rx_mode(struct net_device *dev)
432{
433}
434
56ade8fe
JP		 435static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
436{
437 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
438 struct sockaddr *addr = p;
439 int err;
440
441 if (!is_valid_ether_addr(addr->sa_data))
442 return -EADDRNOTAVAIL;
443
444 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
445 if (err)
446 return err;
447 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
448 return 0;
449}
450
9f7ec052 451static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
d81a6bdb 452 bool pause_en, bool pfc_en, u16 delay)
ff6551ec 453{
ff6551ec 454 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
8e8dfe9f 455
d81a6bdb
IS		 456 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
457 MLXSW_SP_PAUSE_DELAY;
9f7ec052 458
d81a6bdb 459 if (pause_en || pfc_en)
9f7ec052 460 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
d81a6bdb
IS		 461 pg_size + delay, pg_size);
462 else
9f7ec052 463 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
8e8dfe9f
IS		 464}
465
466int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 467 u8 *prio_tc, bool pause_en,
468 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 469{
470 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 471 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
472 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 473 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 474 int i, j, err;
ff6551ec
IS		 475
476 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
477 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
478 if (err)
479 return err;
8e8dfe9f
IS		 480
481 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
482 bool configure = false;
d81a6bdb 483 bool pfc = false;
8e8dfe9f
IS		 484
485 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
486 if (prio_tc[j] == i) {
d81a6bdb 487 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 488 configure = true;
489 break;
490 }
491 }
492
493 if (!configure)
494 continue;
d81a6bdb 495 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
8e8dfe9f
IS		 496 }
497
ff6551ec
IS		 498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
499}
500
8e8dfe9f 501static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 502 int mtu, bool pause_en)
8e8dfe9f
IS		 503{
504 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
505 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 506 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 507 u8 *prio_tc;
508
509 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 510 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 511
9f7ec052 512 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 513 pause_en, my_pfc);
8e8dfe9f
IS		 514}
515
56ade8fe
JP		 516static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
517{
518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 519 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 520 int err;
521
9f7ec052 522 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 523 if (err)
524 return err;
ff6551ec
IS		 525 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
526 if (err)
527 goto err_port_mtu_set;
56ade8fe
JP		 528 dev->mtu = mtu;
529 return 0;
ff6551ec
IS		 530
531err_port_mtu_set:
9f7ec052 532 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 533 return err;
56ade8fe
JP		 534}
535
536static struct rtnl_link_stats64 *
537mlxsw_sp_port_get_stats64(struct net_device *dev,
538 struct rtnl_link_stats64 *stats)
539{
540 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
541 struct mlxsw_sp_port_pcpu_stats *p;
542 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
543 u32 tx_dropped = 0;
544 unsigned int start;
545 int i;
546
547 for_each_possible_cpu(i) {
548 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
549 do {
550 start = u64_stats_fetch_begin_irq(&p->syncp);
551 rx_packets = p->rx_packets;
552 rx_bytes = p->rx_bytes;
553 tx_packets = p->tx_packets;
554 tx_bytes = p->tx_bytes;
555 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
556
557 stats->rx_packets += rx_packets;
558 stats->rx_bytes += rx_bytes;
559 stats->tx_packets += tx_packets;
560 stats->tx_bytes += tx_bytes;
561 /* tx_dropped is u32, updated without syncp protection. */
562 tx_dropped += p->tx_dropped;
563 }
564 stats->tx_dropped = tx_dropped;
565 return stats;
566}
567
568int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
569 u16 vid_end, bool is_member, bool untagged)
570{
571 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
572 char *spvm_pl;
573 int err;
574
575 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
576 if (!spvm_pl)
577 return -ENOMEM;
578
579 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
580 vid_end, is_member, untagged);
581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
582 kfree(spvm_pl);
583 return err;
584}
585
586static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
587{
588 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
589 u16 vid, last_visited_vid;
590 int err;
591
592 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
593 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
594 vid);
595 if (err) {
596 last_visited_vid = vid;
597 goto err_port_vid_to_fid_set;
598 }
599 }
600
601 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
602 if (err) {
603 last_visited_vid = VLAN_N_VID;
604 goto err_port_vid_to_fid_set;
605 }
606
607 return 0;
608
609err_port_vid_to_fid_set:
610 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
611 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
612 vid);
613 return err;
614}
615
616static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
617{
618 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
619 u16 vid;
620 int err;
621
622 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
623 if (err)
624 return err;
625
626 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
627 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
628 vid, vid);
629 if (err)
630 return err;
631 }
632
633 return 0;
634}
635
d0ec875a 636static struct mlxsw_sp_fid *
7f71eb46
IS		 637mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
638{
d0ec875a 639 struct mlxsw_sp_fid *f;
7f71eb46 640
d0ec875a
IS		 641 list_for_each_entry(f, &mlxsw_sp->port_vfids.list, list) {
642 if (f->vid == vid)
643 return f;
7f71eb46
IS		 644 }
645
646 return NULL;
647}
648
649static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
650{
651 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
652 MLXSW_SP_VFID_PORT_MAX);
653}
654
c7e920b5 655static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
7f71eb46 656{
7f71eb46
IS		 657 char sfmr_pl[MLXSW_REG_SFMR_LEN];
658
c7e920b5 659 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
7f71eb46
IS		 660 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
661}
662
d0ec875a
IS		 663static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
664 u16 vid)
7f71eb46
IS		 665{
666 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 667 struct mlxsw_sp_fid *f;
c7e920b5 668 u16 vfid, fid;
7f71eb46
IS		 669 int err;
670
c7e920b5
IS		 671 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
672 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
7f71eb46
IS		 673 dev_err(dev, "No available vFIDs\n");
674 return ERR_PTR(-ERANGE);
675 }
676
c7e920b5
IS		 677 fid = mlxsw_sp_vfid_to_fid(vfid);
678 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
7f71eb46 679 if (err) {
c7e920b5 680 dev_err(dev, "Failed to create FID=%d\n", fid);
7f71eb46
IS		 681 return ERR_PTR(err);
682 }
683
c7e920b5
IS		 684 f = kzalloc(sizeof(*f), GFP_KERNEL);
685 if (!f)
7f71eb46
IS		 686 goto err_allocate_vfid;
687
d0ec875a 688 f->fid = fid;
c7e920b5 689 f->vid = vid;
7f71eb46 690
c7e920b5
IS		 691 list_add(&f->list, &mlxsw_sp->port_vfids.list);
692 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
7f71eb46 693
c7e920b5 694 return f;
7f71eb46
IS		 695
696err_allocate_vfid:
c7e920b5 697 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
7f71eb46
IS		 698 return ERR_PTR(-ENOMEM);
699}
700
701static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
d0ec875a 702 struct mlxsw_sp_fid *f)
7f71eb46 703{
d0ec875a 704 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
c7e920b5 705
d0ec875a
IS		 706 clear_bit(vfid, mlxsw_sp->port_vfids.mapped);
707 list_del(&f->list);
7f71eb46 708
d0ec875a 709 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
7f71eb46 710
d0ec875a 711 kfree(f);
7f71eb46
IS		 712}
713
714static struct mlxsw_sp_port *
0355b59f 715mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
7f71eb46
IS		 716{
717 struct mlxsw_sp_port *mlxsw_sp_vport;
718
719 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
720 if (!mlxsw_sp_vport)
721 return NULL;
722
723 /* dev will be set correctly after the VLAN device is linked
724 * with the real device. In case of bridge SELF invocation, dev
725 * will remain as is.
726 */
727 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
728 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
729 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
730 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
272c4470
IS		 731 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
732 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
0355b59f 733 mlxsw_sp_vport->vport.vid = vid;
7f71eb46
IS		 734
735 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
736
737 return mlxsw_sp_vport;
738}
739
740static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
741{
742 list_del(&mlxsw_sp_vport->vport.list);
743 kfree(mlxsw_sp_vport);
744}
745
9c4d4423
IS		 746static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
747 bool valid)
748{
749 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
750 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
751
752 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
753 vid);
754}
755
0355b59f
IS		 756static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport)
757{
758 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
759 struct mlxsw_sp_fid *f;
760 int err;
761
762 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, vid);
763 if (!f) {
764 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, vid);
765 if (IS_ERR(f))
766 return PTR_ERR(f);
767 }
768
769 if (!f->ref_count) {
770 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
771 if (err)
772 goto err_vport_flood_set;
773 }
774
775 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
776 if (err)
777 goto err_vport_fid_map;
778
41b996cc 779 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f
IS		 780 f->ref_count++;
781
782 return 0;
783
784err_vport_fid_map:
785 if (!f->ref_count)
786 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
787err_vport_flood_set:
788 if (!f->ref_count)
789 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
790 return err;
791}
792
793static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
794{
41b996cc 795 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
0355b59f 796
41b996cc 797 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f
IS		 798
799 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
800
801 if (--f->ref_count == 0) {
802 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
803 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
804 }
805}
806
56ade8fe
JP		 807int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
808 u16 vid)
809{
810 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 811 struct mlxsw_sp_port *mlxsw_sp_vport;
56ade8fe
JP		 812 int err;
813
814 /* VLAN 0 is added to HW filter when device goes up, but it is
815 * reserved in our case, so simply return.
816 */
817 if (!vid)
818 return 0;
819
7f71eb46 820 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
56ade8fe
JP		 821 netdev_warn(dev, "VID=%d already configured\n", vid);
822 return 0;
823 }
824
0355b59f 825 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
7f71eb46
IS		 826 if (!mlxsw_sp_vport) {
827 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
0355b59f 828 return -ENOMEM;
56ade8fe
JP		 829 }
830
56ade8fe
JP		 831 /* When adding the first VLAN interface on a bridged port we need to
832 * transition all the active 802.1Q bridge VLANs to use explicit
833 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
834 */
7f71eb46 835 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 836 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
837 if (err) {
838 netdev_err(dev, "Failed to set to Virtual mode\n");
7f71eb46 839 goto err_port_vp_mode_trans;
56ade8fe
JP		 840 }
841 }
842
0355b59f 843 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
56ade8fe 844 if (err) {
0355b59f
IS		 845 netdev_err(dev, "Failed to join vFID\n");
846 goto err_vport_vfid_join;
56ade8fe
JP		 847 }
848
7f71eb46 849 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
56ade8fe
JP		 850 if (err) {
851 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
852 goto err_port_vid_learning_set;
853 }
854
7f71eb46 855 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
56ade8fe
JP		 856 if (err) {
857 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
858 vid);
859 goto err_port_add_vid;
860 }
861
7f71eb46 862 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 863 MLXSW_REG_SPMS_STATE_FORWARDING);
864 if (err) {
865 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
866 goto err_port_stp_state_set;
867 }
868
56ade8fe
JP		 869 return 0;
870
56ade8fe 871err_port_stp_state_set:
7f71eb46 872 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe 873err_port_add_vid:
7f71eb46 874 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe 875err_port_vid_learning_set:
0355b59f
IS		 876 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
877err_vport_vfid_join:
7f71eb46
IS		 878 if (list_is_singular(&mlxsw_sp_port->vports_list))
879 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
880err_port_vp_mode_trans:
7f71eb46 881 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
56ade8fe
JP		 882 return err;
883}
884
885int mlxsw_sp_port_kill_vid(struct net_device *dev,
886 __be16 __always_unused proto, u16 vid)
887{
888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 889 struct mlxsw_sp_port *mlxsw_sp_vport;
56ade8fe
JP		 890 int err;
891
892 /* VLAN 0 is removed from HW filter when device goes down, but
893 * it is reserved in our case, so simply return.
894 */
895 if (!vid)
896 return 0;
897
7f71eb46
IS		 898 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
899 if (!mlxsw_sp_vport) {
56ade8fe
JP		 900 netdev_warn(dev, "VID=%d does not exist\n", vid);
901 return 0;
902 }
903
7f71eb46 904 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 905 MLXSW_REG_SPMS_STATE_DISCARDING);
906 if (err) {
907 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
908 return err;
909 }
910
7f71eb46 911 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe
JP		 912 if (err) {
913 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
914 vid);
915 return err;
916 }
917
7f71eb46 918 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe
JP		 919 if (err) {
920 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
921 return err;
922 }
923
0355b59f 924 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
56ade8fe
JP		 925
926 /* When removing the last VLAN interface on a bridged port we need to
927 * transition all active 802.1Q bridge VLANs to use VID to FID
928 * mappings and set port's mode to VLAN mode.
929 */
7f71eb46 930 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 931 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
932 if (err) {
933 netdev_err(dev, "Failed to set to VLAN mode\n");
934 return err;
935 }
936 }
937
7f71eb46
IS		 938 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
939
56ade8fe
JP		 940 return 0;
941}
942
2bf9a586
IS		 943static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
944 size_t len)
945{
946 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 947 u8 module = mlxsw_sp_port->mapping.module;
948 u8 width = mlxsw_sp_port->mapping.width;
949 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 950 int err;
951
2bf9a586
IS		 952 if (!mlxsw_sp_port->split)
953 err = snprintf(name, len, "p%d", module + 1);
954 else
955 err = snprintf(name, len, "p%ds%d", module + 1,
956 lane / width);
957
958 if (err >= len)
959 return -EINVAL;
960
961 return 0;
962}
963
56ade8fe
JP		 964static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
965 .ndo_open = mlxsw_sp_port_open,
966 .ndo_stop = mlxsw_sp_port_stop,
967 .ndo_start_xmit = mlxsw_sp_port_xmit,
c5b9b518 968 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 969 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
970 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
971 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
972 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
973 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
974 .ndo_fdb_add = switchdev_port_fdb_add,
975 .ndo_fdb_del = switchdev_port_fdb_del,
976 .ndo_fdb_dump = switchdev_port_fdb_dump,
977 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
978 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
979 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
2bf9a586 980 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 981};
982
983static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
984 struct ethtool_drvinfo *drvinfo)
985{
986 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
987 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
988
989 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
990 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
991 sizeof(drvinfo->version));
992 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
993 "%d.%d.%d",
994 mlxsw_sp->bus_info->fw_rev.major,
995 mlxsw_sp->bus_info->fw_rev.minor,
996 mlxsw_sp->bus_info->fw_rev.subminor);
997 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
998 sizeof(drvinfo->bus_info));
999}
1000
9f7ec052
IS		 1001static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1002 struct ethtool_pauseparam *pause)
1003{
1004 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1005
1006 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1007 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1008}
1009
1010static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1011 struct ethtool_pauseparam *pause)
1012{
1013 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1014
1015 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1016 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1017 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1018
1019 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1020 pfcc_pl);
1021}
1022
1023static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1024 struct ethtool_pauseparam *pause)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 bool pause_en = pause->tx_pause || pause->rx_pause;
1028 int err;
1029
d81a6bdb
IS		 1030 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1031 netdev_err(dev, "PFC already enabled on port\n");
1032 return -EINVAL;
1033 }
1034
9f7ec052
IS		 1035 if (pause->autoneg) {
1036 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1037 return -EINVAL;
1038 }
1039
1040 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1041 if (err) {
1042 netdev_err(dev, "Failed to configure port's headroom\n");
1043 return err;
1044 }
1045
1046 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1047 if (err) {
1048 netdev_err(dev, "Failed to set PAUSE parameters\n");
1049 goto err_port_pause_configure;
1050 }
1051
1052 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1053 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1054
1055 return 0;
1056
1057err_port_pause_configure:
1058 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1059 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1060 return err;
1061}
1062
56ade8fe
JP		 1063struct mlxsw_sp_port_hw_stats {
1064 char str[ETH_GSTRING_LEN];
1065 u64 (*getter)(char *payload);
1066};
1067
1068static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1069 {
1070 .str = "a_frames_transmitted_ok",
1071 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1072 },
1073 {
1074 .str = "a_frames_received_ok",
1075 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1076 },
1077 {
1078 .str = "a_frame_check_sequence_errors",
1079 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1080 },
1081 {
1082 .str = "a_alignment_errors",
1083 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1084 },
1085 {
1086 .str = "a_octets_transmitted_ok",
1087 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1088 },
1089 {
1090 .str = "a_octets_received_ok",
1091 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1092 },
1093 {
1094 .str = "a_multicast_frames_xmitted_ok",
1095 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1096 },
1097 {
1098 .str = "a_broadcast_frames_xmitted_ok",
1099 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1100 },
1101 {
1102 .str = "a_multicast_frames_received_ok",
1103 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1104 },
1105 {
1106 .str = "a_broadcast_frames_received_ok",
1107 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1108 },
1109 {
1110 .str = "a_in_range_length_errors",
1111 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1112 },
1113 {
1114 .str = "a_out_of_range_length_field",
1115 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1116 },
1117 {
1118 .str = "a_frame_too_long_errors",
1119 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1120 },
1121 {
1122 .str = "a_symbol_error_during_carrier",
1123 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1124 },
1125 {
1126 .str = "a_mac_control_frames_transmitted",
1127 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1128 },
1129 {
1130 .str = "a_mac_control_frames_received",
1131 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1132 },
1133 {
1134 .str = "a_unsupported_opcodes_received",
1135 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1136 },
1137 {
1138 .str = "a_pause_mac_ctrl_frames_received",
1139 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1140 },
1141 {
1142 .str = "a_pause_mac_ctrl_frames_xmitted",
1143 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1144 },
1145};
1146
1147#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1148
1149static void mlxsw_sp_port_get_strings(struct net_device *dev,
1150 u32 stringset, u8 *data)
1151{
1152 u8 *p = data;
1153 int i;
1154
1155 switch (stringset) {
1156 case ETH_SS_STATS:
1157 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1158 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1159 ETH_GSTRING_LEN);
1160 p += ETH_GSTRING_LEN;
1161 }
1162 break;
1163 }
1164}
1165
3a66ee38
IS		 1166static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1167 enum ethtool_phys_id_state state)
1168{
1169 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1171 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1172 bool active;
1173
1174 switch (state) {
1175 case ETHTOOL_ID_ACTIVE:
1176 active = true;
1177 break;
1178 case ETHTOOL_ID_INACTIVE:
1179 active = false;
1180 break;
1181 default:
1182 return -EOPNOTSUPP;
1183 }
1184
1185 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1186 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1187}
1188
56ade8fe
JP		 1189static void mlxsw_sp_port_get_stats(struct net_device *dev,
1190 struct ethtool_stats *stats, u64 *data)
1191{
1192 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1193 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1194 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1195 int i;
1196 int err;
1197
34dba0a5
IS		 1198 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1199 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
56ade8fe
JP		 1200 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1201 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1202 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1203}
1204
1205static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1206{
1207 switch (sset) {
1208 case ETH_SS_STATS:
1209 return MLXSW_SP_PORT_HW_STATS_LEN;
1210 default:
1211 return -EOPNOTSUPP;
1212 }
1213}
1214
1215struct mlxsw_sp_port_link_mode {
1216 u32 mask;
1217 u32 supported;
1218 u32 advertised;
1219 u32 speed;
1220};
1221
1222static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1223 {
1224 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1225 .supported = SUPPORTED_100baseT_Full,
1226 .advertised = ADVERTISED_100baseT_Full,
1227 .speed = 100,
1228 },
1229 {
1230 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1231 .speed = 100,
1232 },
1233 {
1234 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1235 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1236 .supported = SUPPORTED_1000baseKX_Full,
1237 .advertised = ADVERTISED_1000baseKX_Full,
1238 .speed = 1000,
1239 },
1240 {
1241 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1242 .supported = SUPPORTED_10000baseT_Full,
1243 .advertised = ADVERTISED_10000baseT_Full,
1244 .speed = 10000,
1245 },
1246 {
1247 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1248 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1249 .supported = SUPPORTED_10000baseKX4_Full,
1250 .advertised = ADVERTISED_10000baseKX4_Full,
1251 .speed = 10000,
1252 },
1253 {
1254 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1255 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1256 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1257 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1258 .supported = SUPPORTED_10000baseKR_Full,
1259 .advertised = ADVERTISED_10000baseKR_Full,
1260 .speed = 10000,
1261 },
1262 {
1263 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1264 .supported = SUPPORTED_20000baseKR2_Full,
1265 .advertised = ADVERTISED_20000baseKR2_Full,
1266 .speed = 20000,
1267 },
1268 {
1269 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1270 .supported = SUPPORTED_40000baseCR4_Full,
1271 .advertised = ADVERTISED_40000baseCR4_Full,
1272 .speed = 40000,
1273 },
1274 {
1275 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1276 .supported = SUPPORTED_40000baseKR4_Full,
1277 .advertised = ADVERTISED_40000baseKR4_Full,
1278 .speed = 40000,
1279 },
1280 {
1281 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1282 .supported = SUPPORTED_40000baseSR4_Full,
1283 .advertised = ADVERTISED_40000baseSR4_Full,
1284 .speed = 40000,
1285 },
1286 {
1287 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1288 .supported = SUPPORTED_40000baseLR4_Full,
1289 .advertised = ADVERTISED_40000baseLR4_Full,
1290 .speed = 40000,
1291 },
1292 {
1293 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1294 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1295 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1296 .speed = 25000,
1297 },
1298 {
1299 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1300 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1301 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1302 .speed = 50000,
1303 },
1304 {
1305 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1306 .supported = SUPPORTED_56000baseKR4_Full,
1307 .advertised = ADVERTISED_56000baseKR4_Full,
1308 .speed = 56000,
1309 },
1310 {
1311 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1312 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1313 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1314 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1315 .speed = 100000,
1316 },
1317};
1318
1319#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1320
1321static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1322{
1323 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1324 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1325 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1326 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1327 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1328 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1329 return SUPPORTED_FIBRE;
1330
1331 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1332 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1333 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1334 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1335 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1336 return SUPPORTED_Backplane;
1337 return 0;
1338}
1339
1340static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1341{
1342 u32 modes = 0;
1343 int i;
1344
1345 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1346 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1347 modes |= mlxsw_sp_port_link_mode[i].supported;
1348 }
1349 return modes;
1350}
1351
1352static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1353{
1354 u32 modes = 0;
1355 int i;
1356
1357 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1358 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1359 modes |= mlxsw_sp_port_link_mode[i].advertised;
1360 }
1361 return modes;
1362}
1363
1364static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1365 struct ethtool_cmd *cmd)
1366{
1367 u32 speed = SPEED_UNKNOWN;
1368 u8 duplex = DUPLEX_UNKNOWN;
1369 int i;
1370
1371 if (!carrier_ok)
1372 goto out;
1373
1374 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1375 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1376 speed = mlxsw_sp_port_link_mode[i].speed;
1377 duplex = DUPLEX_FULL;
1378 break;
1379 }
1380 }
1381out:
1382 ethtool_cmd_speed_set(cmd, speed);
1383 cmd->duplex = duplex;
1384}
1385
1386static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1387{
1388 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1389 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1390 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1391 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1392 return PORT_FIBRE;
1393
1394 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1395 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1396 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1397 return PORT_DA;
1398
1399 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1400 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1401 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1402 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1403 return PORT_NONE;
1404
1405 return PORT_OTHER;
1406}
1407
1408static int mlxsw_sp_port_get_settings(struct net_device *dev,
1409 struct ethtool_cmd *cmd)
1410{
1411 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1412 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1413 char ptys_pl[MLXSW_REG_PTYS_LEN];
1414 u32 eth_proto_cap;
1415 u32 eth_proto_admin;
1416 u32 eth_proto_oper;
1417 int err;
1418
1419 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1420 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1421 if (err) {
1422 netdev_err(dev, "Failed to get proto");
1423 return err;
1424 }
1425 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1426 &eth_proto_admin, &eth_proto_oper);
1427
1428 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1429 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1430 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1431 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1432 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1433 eth_proto_oper, cmd);
1434
1435 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1436 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1437 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1438
1439 cmd->transceiver = XCVR_INTERNAL;
1440 return 0;
1441}
1442
1443static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1444{
1445 u32 ptys_proto = 0;
1446 int i;
1447
1448 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1449 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1450 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1451 }
1452 return ptys_proto;
1453}
1454
1455static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1456{
1457 u32 ptys_proto = 0;
1458 int i;
1459
1460 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1461 if (speed == mlxsw_sp_port_link_mode[i].speed)
1462 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1463 }
1464 return ptys_proto;
1465}
1466
18f1e70c
IS		 1467static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1468{
1469 u32 ptys_proto = 0;
1470 int i;
1471
1472 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1473 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1474 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1475 }
1476 return ptys_proto;
1477}
1478
56ade8fe
JP		 1479static int mlxsw_sp_port_set_settings(struct net_device *dev,
1480 struct ethtool_cmd *cmd)
1481{
1482 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1483 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1484 char ptys_pl[MLXSW_REG_PTYS_LEN];
1485 u32 speed;
1486 u32 eth_proto_new;
1487 u32 eth_proto_cap;
1488 u32 eth_proto_admin;
1489 bool is_up;
1490 int err;
1491
1492 speed = ethtool_cmd_speed(cmd);
1493
1494 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1495 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1496 mlxsw_sp_to_ptys_speed(speed);
1497
1498 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1499 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1500 if (err) {
1501 netdev_err(dev, "Failed to get proto");
1502 return err;
1503 }
1504 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1505
1506 eth_proto_new = eth_proto_new & eth_proto_cap;
1507 if (!eth_proto_new) {
1508 netdev_err(dev, "Not supported proto admin requested");
1509 return -EINVAL;
1510 }
1511 if (eth_proto_new == eth_proto_admin)
1512 return 0;
1513
1514 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1515 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1516 if (err) {
1517 netdev_err(dev, "Failed to set proto admin");
1518 return err;
1519 }
1520
1521 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1522 if (err) {
1523 netdev_err(dev, "Failed to get oper status");
1524 return err;
1525 }
1526 if (!is_up)
1527 return 0;
1528
1529 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1530 if (err) {
1531 netdev_err(dev, "Failed to set admin status");
1532 return err;
1533 }
1534
1535 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1536 if (err) {
1537 netdev_err(dev, "Failed to set admin status");
1538 return err;
1539 }
1540
1541 return 0;
1542}
1543
1544static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1545 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1546 .get_link = ethtool_op_get_link,
9f7ec052
IS		 1547 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1548 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 1549 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 1550 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 1551 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1552 .get_sset_count = mlxsw_sp_port_get_sset_count,
1553 .get_settings = mlxsw_sp_port_get_settings,
1554 .set_settings = mlxsw_sp_port_set_settings,
1555};
1556
18f1e70c
IS		 1557static int
1558mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1559{
1560 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1561 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1562 char ptys_pl[MLXSW_REG_PTYS_LEN];
1563 u32 eth_proto_admin;
1564
1565 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1566 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1567 eth_proto_admin);
1568 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1569}
1570
8e8dfe9f
IS		 1571int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1572 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1573 bool dwrr, u8 dwrr_weight)
90183b98
IS		 1574{
1575 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1576 char qeec_pl[MLXSW_REG_QEEC_LEN];
1577
1578 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1579 next_index);
1580 mlxsw_reg_qeec_de_set(qeec_pl, true);
1581 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1582 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1583 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1584}
1585
cc7cf517
IS		 1586int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1587 enum mlxsw_reg_qeec_hr hr, u8 index,
1588 u8 next_index, u32 maxrate)
90183b98
IS		 1589{
1590 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1591 char qeec_pl[MLXSW_REG_QEEC_LEN];
1592
1593 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1594 next_index);
1595 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1596 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1598}
1599
8e8dfe9f
IS		 1600int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1601 u8 switch_prio, u8 tclass)
90183b98
IS		 1602{
1603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1604 char qtct_pl[MLXSW_REG_QTCT_LEN];
1605
1606 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1607 tclass);
1608 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1609}
1610
1611static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1612{
1613 int err, i;
1614
1615 /* Setup the elements hierarcy, so that each TC is linked to
1616 * one subgroup, which are all member in the same group.
1617 */
1618 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1619 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1620 0);
1621 if (err)
1622 return err;
1623 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1624 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1625 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1626 0, false, 0);
1627 if (err)
1628 return err;
1629 }
1630 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1631 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1632 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1633 false, 0);
1634 if (err)
1635 return err;
1636 }
1637
1638 /* Make sure the max shaper is disabled in all hierarcies that
1639 * support it.
1640 */
1641 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1642 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1643 MLXSW_REG_QEEC_MAS_DIS);
1644 if (err)
1645 return err;
1646 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1647 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1648 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1649 i, 0,
1650 MLXSW_REG_QEEC_MAS_DIS);
1651 if (err)
1652 return err;
1653 }
1654 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1655 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1656 MLXSW_REG_QEEC_HIERARCY_TC,
1657 i, i,
1658 MLXSW_REG_QEEC_MAS_DIS);
1659 if (err)
1660 return err;
1661 }
1662
1663 /* Map all priorities to traffic class 0. */
1664 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1665 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1666 if (err)
1667 return err;
1668 }
1669
1670 return 0;
1671}
1672
be94535f 1673static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
d664b41e 1674 bool split, u8 module, u8 width, u8 lane)
56ade8fe
JP		 1675{
1676 struct mlxsw_sp_port *mlxsw_sp_port;
1677 struct net_device *dev;
bd40e9d6 1678 size_t bytes;
56ade8fe
JP		 1679 int err;
1680
1681 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1682 if (!dev)
1683 return -ENOMEM;
1684 mlxsw_sp_port = netdev_priv(dev);
1685 mlxsw_sp_port->dev = dev;
1686 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1687 mlxsw_sp_port->local_port = local_port;
18f1e70c 1688 mlxsw_sp_port->split = split;
d664b41e
IS		 1689 mlxsw_sp_port->mapping.module = module;
1690 mlxsw_sp_port->mapping.width = width;
1691 mlxsw_sp_port->mapping.lane = lane;
bd40e9d6
IS		 1692 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1693 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1694 if (!mlxsw_sp_port->active_vlans) {
1695 err = -ENOMEM;
1696 goto err_port_active_vlans_alloc;
1697 }
fc1273af
ER		 1698 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1699 if (!mlxsw_sp_port->untagged_vlans) {
1700 err = -ENOMEM;
1701 goto err_port_untagged_vlans_alloc;
1702 }
7f71eb46 1703 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
56ade8fe
JP		 1704
1705 mlxsw_sp_port->pcpu_stats =
1706 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1707 if (!mlxsw_sp_port->pcpu_stats) {
1708 err = -ENOMEM;
1709 goto err_alloc_stats;
1710 }
1711
1712 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1713 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1714
1715 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1716 if (err) {
1717 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1718 mlxsw_sp_port->local_port);
1719 goto err_dev_addr_init;
1720 }
1721
1722 netif_carrier_off(dev);
1723
1724 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1725 NETIF_F_HW_VLAN_CTAG_FILTER;
1726
1727 /* Each packet needs to have a Tx header (metadata) on top all other
1728 * headers.
1729 */
1730 dev->hard_header_len += MLXSW_TXHDR_LEN;
1731
56ade8fe
JP		 1732 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1733 if (err) {
1734 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1735 mlxsw_sp_port->local_port);
1736 goto err_port_system_port_mapping_set;
1737 }
1738
1739 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1740 if (err) {
1741 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1742 mlxsw_sp_port->local_port);
1743 goto err_port_swid_set;
1744 }
1745
18f1e70c
IS		 1746 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1747 if (err) {
1748 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1749 mlxsw_sp_port->local_port);
1750 goto err_port_speed_by_width_set;
1751 }
1752
56ade8fe
JP		 1753 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1754 if (err) {
1755 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1756 mlxsw_sp_port->local_port);
1757 goto err_port_mtu_set;
1758 }
1759
1760 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1761 if (err)
1762 goto err_port_admin_status_set;
1763
1764 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1765 if (err) {
1766 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1767 mlxsw_sp_port->local_port);
1768 goto err_port_buffers_init;
1769 }
1770
90183b98
IS		 1771 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1772 if (err) {
1773 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1774 mlxsw_sp_port->local_port);
1775 goto err_port_ets_init;
1776 }
1777
f00817df
IS		 1778 /* ETS and buffers must be initialized before DCB. */
1779 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1780 if (err) {
1781 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1782 mlxsw_sp_port->local_port);
1783 goto err_port_dcb_init;
1784 }
1785
56ade8fe
JP		 1786 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1787 err = register_netdev(dev);
1788 if (err) {
1789 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1790 mlxsw_sp_port->local_port);
1791 goto err_register_netdev;
1792 }
1793
932762b6
JP		 1794 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1795 mlxsw_sp_port->local_port, dev,
1796 mlxsw_sp_port->split, module);
1797 if (err) {
1798 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1799 mlxsw_sp_port->local_port);
1800 goto err_core_port_init;
1801 }
c4745500 1802
56ade8fe
JP		 1803 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1804 if (err)
1805 goto err_port_vlan_init;
1806
1807 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1808 return 0;
1809
1810err_port_vlan_init:
932762b6
JP		 1811 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1812err_core_port_init:
56ade8fe
JP		 1813 unregister_netdev(dev);
1814err_register_netdev:
f00817df 1815err_port_dcb_init:
90183b98 1816err_port_ets_init:
56ade8fe
JP		 1817err_port_buffers_init:
1818err_port_admin_status_set:
1819err_port_mtu_set:
18f1e70c 1820err_port_speed_by_width_set:
56ade8fe
JP		 1821err_port_swid_set:
1822err_port_system_port_mapping_set:
56ade8fe
JP		 1823err_dev_addr_init:
1824 free_percpu(mlxsw_sp_port->pcpu_stats);
1825err_alloc_stats:
fc1273af
ER		 1826 kfree(mlxsw_sp_port->untagged_vlans);
1827err_port_untagged_vlans_alloc:
bd40e9d6
IS		 1828 kfree(mlxsw_sp_port->active_vlans);
1829err_port_active_vlans_alloc:
56ade8fe
JP		 1830 free_netdev(dev);
1831 return err;
1832}
1833
7f71eb46 1834static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
56ade8fe 1835{
7f71eb46
IS		 1836 struct net_device *dev = mlxsw_sp_port->dev;
1837 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
56ade8fe 1838
7f71eb46
IS		 1839 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1840 &mlxsw_sp_port->vports_list, vport.list) {
1841 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1842
1843 /* vPorts created for VLAN devices should already be gone
1844 * by now, since we unregistered the port netdev.
1845 */
1846 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1847 mlxsw_sp_port_kill_vid(dev, 0, vid);
1848 }
56ade8fe
JP		 1849}
1850
1851static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1852{
1853 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1854
1855 if (!mlxsw_sp_port)
1856 return;
a133318c 1857 mlxsw_sp->ports[local_port] = NULL;
932762b6 1858 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
56ade8fe 1859 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
f00817df 1860 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
7f71eb46 1861 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
56ade8fe 1862 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3e9b27b8
IS		 1863 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1864 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
56ade8fe 1865 free_percpu(mlxsw_sp_port->pcpu_stats);
fc1273af 1866 kfree(mlxsw_sp_port->untagged_vlans);
bd40e9d6 1867 kfree(mlxsw_sp_port->active_vlans);
56ade8fe
JP		 1868 free_netdev(mlxsw_sp_port->dev);
1869}
1870
1871static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1872{
1873 int i;
1874
1875 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1876 mlxsw_sp_port_remove(mlxsw_sp, i);
1877 kfree(mlxsw_sp->ports);
1878}
1879
1880static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1881{
d664b41e 1882 u8 module, width, lane;
56ade8fe
JP		 1883 size_t alloc_size;
1884 int i;
1885 int err;
1886
1887 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1888 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1889 if (!mlxsw_sp->ports)
1890 return -ENOMEM;
1891
1892 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
558c2d5e 1893 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 1894 &width, &lane);
558c2d5e
IS		 1895 if (err)
1896 goto err_port_module_info_get;
1897 if (!width)
1898 continue;
1899 mlxsw_sp->port_to_module[i] = module;
d664b41e
IS		 1900 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1901 lane);
56ade8fe
JP		 1902 if (err)
1903 goto err_port_create;
1904 }
1905 return 0;
1906
1907err_port_create:
558c2d5e 1908err_port_module_info_get:
56ade8fe
JP		 1909 for (i--; i >= 1; i--)
1910 mlxsw_sp_port_remove(mlxsw_sp, i);
1911 kfree(mlxsw_sp->ports);
1912 return err;
1913}
1914
18f1e70c
IS		 1915static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1916{
1917 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1918
1919 return local_port - offset;
1920}
1921
be94535f
IS		 1922static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1923 u8 module, unsigned int count)
1924{
1925 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1926 int err, i;
1927
1928 for (i = 0; i < count; i++) {
1929 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1930 width, i * width);
1931 if (err)
1932 goto err_port_module_map;
1933 }
1934
1935 for (i = 0; i < count; i++) {
1936 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1937 if (err)
1938 goto err_port_swid_set;
1939 }
1940
1941 for (i = 0; i < count; i++) {
1942 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 1943 module, width, i * width);
be94535f
IS		 1944 if (err)
1945 goto err_port_create;
1946 }
1947
1948 return 0;
1949
1950err_port_create:
1951 for (i--; i >= 0; i--)
1952 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1953 i = count;
1954err_port_swid_set:
1955 for (i--; i >= 0; i--)
1956 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1957 MLXSW_PORT_SWID_DISABLED_PORT);
1958 i = count;
1959err_port_module_map:
1960 for (i--; i >= 0; i--)
1961 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1962 return err;
1963}
1964
1965static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1966 u8 base_port, unsigned int count)
1967{
1968 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1969 int i;
1970
1971 /* Split by four means we need to re-create two ports, otherwise
1972 * only one.
1973 */
1974 count = count / 2;
1975
1976 for (i = 0; i < count; i++) {
1977 local_port = base_port + i * 2;
1978 module = mlxsw_sp->port_to_module[local_port];
1979
1980 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1981 0);
1982 }
1983
1984 for (i = 0; i < count; i++)
1985 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1986
1987 for (i = 0; i < count; i++) {
1988 local_port = base_port + i * 2;
1989 module = mlxsw_sp->port_to_module[local_port];
1990
1991 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 1992 width, 0);
be94535f
IS		 1993 }
1994}
1995
b2f10571
JP		 1996static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1997 unsigned int count)
18f1e70c 1998{
b2f10571 1999 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2000 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 2001 u8 module, cur_width, base_port;
2002 int i;
2003 int err;
2004
2005 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2006 if (!mlxsw_sp_port) {
2007 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2008 local_port);
2009 return -EINVAL;
2010 }
2011
d664b41e
IS		 2012 module = mlxsw_sp_port->mapping.module;
2013 cur_width = mlxsw_sp_port->mapping.width;
2014
18f1e70c
IS		 2015 if (count != 2 && count != 4) {
2016 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2017 return -EINVAL;
2018 }
2019
18f1e70c
IS		 2020 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2021 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2022 return -EINVAL;
2023 }
2024
2025 /* Make sure we have enough slave (even) ports for the split. */
2026 if (count == 2) {
2027 base_port = local_port;
2028 if (mlxsw_sp->ports[base_port + 1]) {
2029 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2030 return -EINVAL;
2031 }
2032 } else {
2033 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2034 if (mlxsw_sp->ports[base_port + 1] ||
2035 mlxsw_sp->ports[base_port + 3]) {
2036 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2037 return -EINVAL;
2038 }
2039 }
2040
2041 for (i = 0; i < count; i++)
2042 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2043
be94535f
IS		 2044 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2045 if (err) {
2046 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2047 goto err_port_split_create;
18f1e70c
IS		 2048 }
2049
2050 return 0;
2051
be94535f
IS		 2052err_port_split_create:
2053 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2054 return err;
2055}
2056
b2f10571 2057static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 2058{
b2f10571 2059 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2060 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 2061 u8 cur_width, base_port;
18f1e70c
IS		 2062 unsigned int count;
2063 int i;
18f1e70c
IS		 2064
2065 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2066 if (!mlxsw_sp_port) {
2067 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2068 local_port);
2069 return -EINVAL;
2070 }
2071
2072 if (!mlxsw_sp_port->split) {
2073 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2074 return -EINVAL;
2075 }
2076
d664b41e 2077 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 2078 count = cur_width == 1 ? 4 : 2;
2079
2080 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2081
2082 /* Determine which ports to remove. */
2083 if (count == 2 && local_port >= base_port + 2)
2084 base_port = base_port + 2;
2085
2086 for (i = 0; i < count; i++)
2087 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2088
be94535f 2089 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2090
2091 return 0;
2092}
2093
56ade8fe
JP		 2094static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2095 char *pude_pl, void *priv)
2096{
2097 struct mlxsw_sp *mlxsw_sp = priv;
2098 struct mlxsw_sp_port *mlxsw_sp_port;
2099 enum mlxsw_reg_pude_oper_status status;
2100 u8 local_port;
2101
2102 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2103 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2104 if (!mlxsw_sp_port) {
2105 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2106 local_port);
2107 return;
2108 }
2109
2110 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2111 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2112 netdev_info(mlxsw_sp_port->dev, "link up\n");
2113 netif_carrier_on(mlxsw_sp_port->dev);
2114 } else {
2115 netdev_info(mlxsw_sp_port->dev, "link down\n");
2116 netif_carrier_off(mlxsw_sp_port->dev);
2117 }
2118}
2119
2120static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2121 .func = mlxsw_sp_pude_event_func,
2122 .trap_id = MLXSW_TRAP_ID_PUDE,
2123};
2124
2125static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2126 enum mlxsw_event_trap_id trap_id)
2127{
2128 struct mlxsw_event_listener *el;
2129 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2130 int err;
2131
2132 switch (trap_id) {
2133 case MLXSW_TRAP_ID_PUDE:
2134 el = &mlxsw_sp_pude_event;
2135 break;
2136 }
2137 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2138 if (err)
2139 return err;
2140
2141 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2142 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2143 if (err)
2144 goto err_event_trap_set;
2145
2146 return 0;
2147
2148err_event_trap_set:
2149 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2150 return err;
2151}
2152
2153static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2154 enum mlxsw_event_trap_id trap_id)
2155{
2156 struct mlxsw_event_listener *el;
2157
2158 switch (trap_id) {
2159 case MLXSW_TRAP_ID_PUDE:
2160 el = &mlxsw_sp_pude_event;
2161 break;
2162 }
2163 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2164}
2165
2166static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2167 void *priv)
2168{
2169 struct mlxsw_sp *mlxsw_sp = priv;
2170 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2171 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2172
2173 if (unlikely(!mlxsw_sp_port)) {
2174 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2175 local_port);
2176 return;
2177 }
2178
2179 skb->dev = mlxsw_sp_port->dev;
2180
2181 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2182 u64_stats_update_begin(&pcpu_stats->syncp);
2183 pcpu_stats->rx_packets++;
2184 pcpu_stats->rx_bytes += skb->len;
2185 u64_stats_update_end(&pcpu_stats->syncp);
2186
2187 skb->protocol = eth_type_trans(skb, skb->dev);
2188 netif_receive_skb(skb);
2189}
2190
2191static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2192 {
2193 .func = mlxsw_sp_rx_listener_func,
2194 .local_port = MLXSW_PORT_DONT_CARE,
2195 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2196 },
2197 /* Traps for specific L2 packet types, not trapped as FDB MC */
2198 {
2199 .func = mlxsw_sp_rx_listener_func,
2200 .local_port = MLXSW_PORT_DONT_CARE,
2201 .trap_id = MLXSW_TRAP_ID_STP,
2202 },
2203 {
2204 .func = mlxsw_sp_rx_listener_func,
2205 .local_port = MLXSW_PORT_DONT_CARE,
2206 .trap_id = MLXSW_TRAP_ID_LACP,
2207 },
2208 {
2209 .func = mlxsw_sp_rx_listener_func,
2210 .local_port = MLXSW_PORT_DONT_CARE,
2211 .trap_id = MLXSW_TRAP_ID_EAPOL,
2212 },
2213 {
2214 .func = mlxsw_sp_rx_listener_func,
2215 .local_port = MLXSW_PORT_DONT_CARE,
2216 .trap_id = MLXSW_TRAP_ID_LLDP,
2217 },
2218 {
2219 .func = mlxsw_sp_rx_listener_func,
2220 .local_port = MLXSW_PORT_DONT_CARE,
2221 .trap_id = MLXSW_TRAP_ID_MMRP,
2222 },
2223 {
2224 .func = mlxsw_sp_rx_listener_func,
2225 .local_port = MLXSW_PORT_DONT_CARE,
2226 .trap_id = MLXSW_TRAP_ID_MVRP,
2227 },
2228 {
2229 .func = mlxsw_sp_rx_listener_func,
2230 .local_port = MLXSW_PORT_DONT_CARE,
2231 .trap_id = MLXSW_TRAP_ID_RPVST,
2232 },
2233 {
2234 .func = mlxsw_sp_rx_listener_func,
2235 .local_port = MLXSW_PORT_DONT_CARE,
2236 .trap_id = MLXSW_TRAP_ID_DHCP,
2237 },
2238 {
2239 .func = mlxsw_sp_rx_listener_func,
2240 .local_port = MLXSW_PORT_DONT_CARE,
2241 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2242 },
2243 {
2244 .func = mlxsw_sp_rx_listener_func,
2245 .local_port = MLXSW_PORT_DONT_CARE,
2246 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2247 },
2248 {
2249 .func = mlxsw_sp_rx_listener_func,
2250 .local_port = MLXSW_PORT_DONT_CARE,
2251 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2252 },
2253 {
2254 .func = mlxsw_sp_rx_listener_func,
2255 .local_port = MLXSW_PORT_DONT_CARE,
2256 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2257 },
2258 {
2259 .func = mlxsw_sp_rx_listener_func,
2260 .local_port = MLXSW_PORT_DONT_CARE,
2261 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2262 },
2263};
2264
2265static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2266{
2267 char htgt_pl[MLXSW_REG_HTGT_LEN];
2268 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2269 int i;
2270 int err;
2271
2272 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2273 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2274 if (err)
2275 return err;
2276
2277 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2278 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2279 if (err)
2280 return err;
2281
2282 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2283 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2284 &mlxsw_sp_rx_listener[i],
2285 mlxsw_sp);
2286 if (err)
2287 goto err_rx_listener_register;
2288
2289 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2290 mlxsw_sp_rx_listener[i].trap_id);
2291 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2292 if (err)
2293 goto err_rx_trap_set;
2294 }
2295 return 0;
2296
2297err_rx_trap_set:
2298 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2299 &mlxsw_sp_rx_listener[i],
2300 mlxsw_sp);
2301err_rx_listener_register:
2302 for (i--; i >= 0; i--) {
2303 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2304 mlxsw_sp_rx_listener[i].trap_id);
2305 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2306
2307 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2308 &mlxsw_sp_rx_listener[i],
2309 mlxsw_sp);
2310 }
2311 return err;
2312}
2313
2314static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2315{
2316 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2317 int i;
2318
2319 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2320 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2321 mlxsw_sp_rx_listener[i].trap_id);
2322 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2323
2324 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2325 &mlxsw_sp_rx_listener[i],
2326 mlxsw_sp);
2327 }
2328}
2329
2330static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2331 enum mlxsw_reg_sfgc_type type,
2332 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2333{
2334 enum mlxsw_flood_table_type table_type;
2335 enum mlxsw_sp_flood_table flood_table;
2336 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2337
19ae6124 2338 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
56ade8fe 2339 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
19ae6124 2340 else
56ade8fe 2341 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
19ae6124
IS		 2342
2343 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2344 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2345 else
2346 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
56ade8fe
JP		 2347
2348 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2349 flood_table);
2350 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2351}
2352
2353static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2354{
2355 int type, err;
2356
56ade8fe
JP		 2357 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2358 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2359 continue;
2360
2361 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2362 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2363 if (err)
2364 return err;
56ade8fe
JP		 2365
2366 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2367 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2368 if (err)
2369 return err;
2370 }
2371
2372 return 0;
2373}
2374
0d65fc13
JP		 2375static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2376{
2377 char slcr_pl[MLXSW_REG_SLCR_LEN];
2378
2379 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2380 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2381 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2382 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2383 MLXSW_REG_SLCR_LAG_HASH_SIP |
2384 MLXSW_REG_SLCR_LAG_HASH_DIP |
2385 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2386 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2387 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2388 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2389}
2390
b2f10571 2391static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 2392 const struct mlxsw_bus_info *mlxsw_bus_info)
2393{
b2f10571 2394 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 2395 int err;
2396
2397 mlxsw_sp->core = mlxsw_core;
2398 mlxsw_sp->bus_info = mlxsw_bus_info;
14d39461 2399 INIT_LIST_HEAD(&mlxsw_sp->fids);
7f71eb46 2400 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
26f0e7fb 2401 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
3a49b4fd 2402 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
56ade8fe
JP		 2403
2404 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2405 if (err) {
2406 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2407 return err;
2408 }
2409
2410 err = mlxsw_sp_ports_create(mlxsw_sp);
2411 if (err) {
2412 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
7f71eb46 2413 return err;
56ade8fe
JP		 2414 }
2415
2416 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2417 if (err) {
2418 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2419 goto err_event_register;
2420 }
2421
2422 err = mlxsw_sp_traps_init(mlxsw_sp);
2423 if (err) {
2424 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2425 goto err_rx_listener_register;
2426 }
2427
2428 err = mlxsw_sp_flood_init(mlxsw_sp);
2429 if (err) {
2430 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2431 goto err_flood_init;
2432 }
2433
2434 err = mlxsw_sp_buffers_init(mlxsw_sp);
2435 if (err) {
2436 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2437 goto err_buffers_init;
2438 }
2439
0d65fc13
JP		 2440 err = mlxsw_sp_lag_init(mlxsw_sp);
2441 if (err) {
2442 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2443 goto err_lag_init;
2444 }
2445
56ade8fe
JP		 2446 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2447 if (err) {
2448 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2449 goto err_switchdev_init;
2450 }
2451
2452 return 0;
2453
2454err_switchdev_init:
0d65fc13 2455err_lag_init:
0f433fa0 2456 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 2457err_buffers_init:
2458err_flood_init:
2459 mlxsw_sp_traps_fini(mlxsw_sp);
2460err_rx_listener_register:
2461 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2462err_event_register:
2463 mlxsw_sp_ports_remove(mlxsw_sp);
56ade8fe
JP		 2464 return err;
2465}
2466
b2f10571 2467static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 2468{
b2f10571 2469 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 2470
2471 mlxsw_sp_switchdev_fini(mlxsw_sp);
5113bfdb 2472 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 2473 mlxsw_sp_traps_fini(mlxsw_sp);
2474 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2475 mlxsw_sp_ports_remove(mlxsw_sp);
14d39461 2476 WARN_ON(!list_empty(&mlxsw_sp->fids));
56ade8fe
JP		 2477}
2478
2479static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2480 .used_max_vepa_channels = 1,
2481 .max_vepa_channels = 0,
2482 .used_max_lag = 1,
0d65fc13 2483 .max_lag = MLXSW_SP_LAG_MAX,
56ade8fe 2484 .used_max_port_per_lag = 1,
0d65fc13 2485 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
56ade8fe 2486 .used_max_mid = 1,
53ae6283 2487 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 2488 .used_max_pgt = 1,
2489 .max_pgt = 0,
2490 .used_max_system_port = 1,
2491 .max_system_port = 64,
2492 .used_max_vlan_groups = 1,
2493 .max_vlan_groups = 127,
2494 .used_max_regions = 1,
2495 .max_regions = 400,
2496 .used_flood_tables = 1,
2497 .used_flood_mode = 1,
2498 .flood_mode = 3,
2499 .max_fid_offset_flood_tables = 2,
2500 .fid_offset_flood_table_size = VLAN_N_VID - 1,
19ae6124
IS		 2501 .max_fid_flood_tables = 2,
2502 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
56ade8fe
JP		 2503 .used_max_ib_mc = 1,
2504 .max_ib_mc = 0,
2505 .used_max_pkey = 1,
2506 .max_pkey = 0,
2507 .swid_config = {
2508 {
2509 .used_type = 1,
2510 .type = MLXSW_PORT_SWID_TYPE_ETH,
2511 }
2512 },
2513};
2514
2515static struct mlxsw_driver mlxsw_sp_driver = {
2d0ed39f
JP		 2516 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2517 .owner = THIS_MODULE,
2518 .priv_size = sizeof(struct mlxsw_sp),
2519 .init = mlxsw_sp_init,
2520 .fini = mlxsw_sp_fini,
2521 .port_split = mlxsw_sp_port_split,
2522 .port_unsplit = mlxsw_sp_port_unsplit,
2523 .sb_pool_get = mlxsw_sp_sb_pool_get,
2524 .sb_pool_set = mlxsw_sp_sb_pool_set,
2525 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2526 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2527 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2528 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2529 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2530 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2531 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2532 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2533 .txhdr_construct = mlxsw_sp_txhdr_construct,
2534 .txhdr_len = MLXSW_TXHDR_LEN,
2535 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 2536};
2537
039c49a6
IS		 2538static int
2539mlxsw_sp_port_fdb_flush_by_port(const struct mlxsw_sp_port *mlxsw_sp_port)
2540{
2541 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2542 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2543
2544 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT);
2545 mlxsw_reg_sfdf_system_port_set(sfdf_pl, mlxsw_sp_port->local_port);
2546
2547 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2548}
2549
2550static int
2551mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2552 u16 fid)
2553{
2554 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2555 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2556
2557 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2558 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2559 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2560 mlxsw_sp_port->local_port);
2561
2562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2563}
2564
2565static int
2566mlxsw_sp_port_fdb_flush_by_lag_id(const struct mlxsw_sp_port *mlxsw_sp_port)
2567{
2568 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2569 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2570
2571 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG);
2572 mlxsw_reg_sfdf_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2573
2574 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2575}
2576
2577static int
2578mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2579 u16 fid)
2580{
2581 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2582 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2583
2584 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2585 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2586 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2587
2588 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2589}
2590
2591static int
2592__mlxsw_sp_port_fdb_flush(const struct mlxsw_sp_port *mlxsw_sp_port)
2593{
2594 int err, last_err = 0;
2595 u16 vid;
2596
2597 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2598 err = mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, vid);
2599 if (err)
2600 last_err = err;
2601 }
2602
2603 return last_err;
2604}
2605
2606static int
2607__mlxsw_sp_port_fdb_flush_lagged(const struct mlxsw_sp_port *mlxsw_sp_port)
2608{
2609 int err, last_err = 0;
2610 u16 vid;
2611
2612 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2613 err = mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port, vid);
2614 if (err)
2615 last_err = err;
2616 }
2617
2618 return last_err;
2619}
2620
2621static int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port)
2622{
2623 if (!list_empty(&mlxsw_sp_port->vports_list))
2624 if (mlxsw_sp_port->lagged)
2625 return __mlxsw_sp_port_fdb_flush_lagged(mlxsw_sp_port);
2626 else
2627 return __mlxsw_sp_port_fdb_flush(mlxsw_sp_port);
2628 else
2629 if (mlxsw_sp_port->lagged)
2630 return mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port);
2631 else
2632 return mlxsw_sp_port_fdb_flush_by_port(mlxsw_sp_port);
2633}
2634
0355b59f
IS		 2635static int mlxsw_sp_vport_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_vport,
2636 u16 fid)
039c49a6 2637{
039c49a6
IS		 2638 if (mlxsw_sp_vport->lagged)
2639 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_vport,
2640 fid);
2641 else
41b996cc
IS		 2642 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_vport,
2643 fid);
039c49a6
IS		 2644}
2645
56ade8fe
JP		 2646static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2647{
2648 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2649}
2650
7117a570
IS		 2651static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2652 struct net_device *br_dev)
2653{
2654 return !mlxsw_sp->master_bridge.dev ||
2655 mlxsw_sp->master_bridge.dev == br_dev;
2656}
2657
2658static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2659 struct net_device *br_dev)
2660{
2661 mlxsw_sp->master_bridge.dev = br_dev;
2662 mlxsw_sp->master_bridge.ref_count++;
2663}
2664
2665static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2666{
2667 if (--mlxsw_sp->master_bridge.ref_count == 0)
2668 mlxsw_sp->master_bridge.dev = NULL;
2669}
2670
2671static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2672 struct net_device *br_dev)
56ade8fe
JP		 2673{
2674 struct net_device *dev = mlxsw_sp_port->dev;
2675 int err;
2676
2677 /* When port is not bridged untagged packets are tagged with
2678 * PVID=VID=1, thereby creating an implicit VLAN interface in
2679 * the device. Remove it and let bridge code take care of its
2680 * own VLANs.
2681 */
2682 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
6c72a3d0
IS		 2683 if (err)
2684 return err;
56ade8fe 2685
7117a570
IS		 2686 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2687
6c72a3d0
IS		 2688 mlxsw_sp_port->learning = 1;
2689 mlxsw_sp_port->learning_sync = 1;
2690 mlxsw_sp_port->uc_flood = 1;
2691 mlxsw_sp_port->bridged = 1;
2692
2693 return 0;
56ade8fe
JP		 2694}
2695
82e6db03
IS		 2696static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2697 bool flush_fdb)
56ade8fe
JP		 2698{
2699 struct net_device *dev = mlxsw_sp_port->dev;
5a8f4525 2700
039c49a6
IS		 2701 if (flush_fdb && mlxsw_sp_port_fdb_flush(mlxsw_sp_port))
2702 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
2703
28a01d2d
IS		 2704 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2705
7117a570
IS		 2706 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2707
6c72a3d0
IS		 2708 mlxsw_sp_port->learning = 0;
2709 mlxsw_sp_port->learning_sync = 0;
2710 mlxsw_sp_port->uc_flood = 0;
5a8f4525 2711 mlxsw_sp_port->bridged = 0;
56ade8fe
JP		 2712
2713 /* Add implicit VLAN interface in the device, so that untagged
2714 * packets will be classified to the default vFID.
2715 */
82e6db03 2716 mlxsw_sp_port_add_vid(dev, 0, 1);
56ade8fe
JP		 2717}
2718
0d65fc13
JP		 2719static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2720{
2721 char sldr_pl[MLXSW_REG_SLDR_LEN];
2722
2723 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2724 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2725}
2726
2727static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2728{
2729 char sldr_pl[MLXSW_REG_SLDR_LEN];
2730
2731 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2732 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2733}
2734
2735static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2736 u16 lag_id, u8 port_index)
2737{
2738 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2739 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2740
2741 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2742 lag_id, port_index);
2743 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2744}
2745
2746static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2747 u16 lag_id)
2748{
2749 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2750 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2751
2752 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2753 lag_id);
2754 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2755}
2756
2757static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2758 u16 lag_id)
2759{
2760 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2761 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2762
2763 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2764 lag_id);
2765 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2766}
2767
2768static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2769 u16 lag_id)
2770{
2771 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2772 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2773
2774 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2775 lag_id);
2776 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2777}
2778
2779static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2780 struct net_device *lag_dev,
2781 u16 *p_lag_id)
2782{
2783 struct mlxsw_sp_upper *lag;
2784 int free_lag_id = -1;
2785 int i;
2786
2787 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2788 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2789 if (lag->ref_count) {
2790 if (lag->dev == lag_dev) {
2791 *p_lag_id = i;
2792 return 0;
2793 }
2794 } else if (free_lag_id < 0) {
2795 free_lag_id = i;
2796 }
2797 }
2798 if (free_lag_id < 0)
2799 return -EBUSY;
2800 *p_lag_id = free_lag_id;
2801 return 0;
2802}
2803
2804static bool
2805mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2806 struct net_device *lag_dev,
2807 struct netdev_lag_upper_info *lag_upper_info)
2808{
2809 u16 lag_id;
2810
2811 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2812 return false;
2813 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2814 return false;
2815 return true;
2816}
2817
2818static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2819 u16 lag_id, u8 *p_port_index)
2820{
2821 int i;
2822
2823 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2824 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2825 *p_port_index = i;
2826 return 0;
2827 }
2828 }
2829 return -EBUSY;
2830}
2831
2832static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2833 struct net_device *lag_dev)
2834{
2835 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2836 struct mlxsw_sp_upper *lag;
2837 u16 lag_id;
2838 u8 port_index;
2839 int err;
2840
2841 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2842 if (err)
2843 return err;
2844 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2845 if (!lag->ref_count) {
2846 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2847 if (err)
2848 return err;
2849 lag->dev = lag_dev;
2850 }
2851
2852 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2853 if (err)
2854 return err;
2855 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2856 if (err)
2857 goto err_col_port_add;
2858 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2859 if (err)
2860 goto err_col_port_enable;
2861
2862 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2863 mlxsw_sp_port->local_port);
2864 mlxsw_sp_port->lag_id = lag_id;
2865 mlxsw_sp_port->lagged = 1;
2866 lag->ref_count++;
2867 return 0;
2868
51554db2
IS		 2869err_col_port_enable:
2870 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 2871err_col_port_add:
2872 if (!lag->ref_count)
2873 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 2874 return err;
2875}
2876
82e6db03 2877static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
82e6db03 2878 bool flush_fdb);
4dc236c3 2879
82e6db03
IS		 2880static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2881 struct net_device *lag_dev)
0d65fc13
JP		 2882{
2883 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4dc236c3 2884 struct mlxsw_sp_port *mlxsw_sp_vport;
0d65fc13
JP		 2885 struct mlxsw_sp_upper *lag;
2886 u16 lag_id = mlxsw_sp_port->lag_id;
0d65fc13
JP		 2887
2888 if (!mlxsw_sp_port->lagged)
82e6db03 2889 return;
0d65fc13
JP		 2890 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2891 WARN_ON(lag->ref_count == 0);
2892
82e6db03
IS		 2893 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2894 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 2895
4dc236c3
IS		 2896 /* In case we leave a LAG device that has bridges built on top,
2897 * then their teardown sequence is never issued and we need to
2898 * invoke the necessary cleanup routines ourselves.
2899 */
2900 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
2901 vport.list) {
2902 struct net_device *br_dev;
2903
2904 if (!mlxsw_sp_vport->bridged)
2905 continue;
2906
2907 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
37286d25 2908 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, false);
4dc236c3
IS		 2909 }
2910
2911 if (mlxsw_sp_port->bridged) {
2912 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
039c49a6 2913 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, false);
4dc236c3
IS		 2914 }
2915
0d65fc13 2916 if (lag->ref_count == 1) {
039c49a6
IS		 2917 if (mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port))
2918 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
82e6db03 2919 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 2920 }
2921
2922 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2923 mlxsw_sp_port->local_port);
2924 mlxsw_sp_port->lagged = 0;
2925 lag->ref_count--;
0d65fc13
JP		 2926}
2927
74581206
JP		 2928static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2929 u16 lag_id)
2930{
2931 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2932 char sldr_pl[MLXSW_REG_SLDR_LEN];
2933
2934 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2935 mlxsw_sp_port->local_port);
2936 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2937}
2938
2939static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2940 u16 lag_id)
2941{
2942 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2943 char sldr_pl[MLXSW_REG_SLDR_LEN];
2944
2945 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2946 mlxsw_sp_port->local_port);
2947 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2948}
2949
2950static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2951 bool lag_tx_enabled)
2952{
2953 if (lag_tx_enabled)
2954 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2955 mlxsw_sp_port->lag_id);
2956 else
2957 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2958 mlxsw_sp_port->lag_id);
2959}
2960
2961static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2962 struct netdev_lag_lower_state_info *info)
2963{
2964 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2965}
2966
9589a7b5
IS		 2967static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2968 struct net_device *vlan_dev)
2969{
2970 struct mlxsw_sp_port *mlxsw_sp_vport;
2971 u16 vid = vlan_dev_vlan_id(vlan_dev);
2972
2973 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 2974 if (WARN_ON(!mlxsw_sp_vport))
9589a7b5 2975 return -EINVAL;
9589a7b5
IS		 2976
2977 mlxsw_sp_vport->dev = vlan_dev;
2978
2979 return 0;
2980}
2981
82e6db03
IS		 2982static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2983 struct net_device *vlan_dev)
9589a7b5
IS		 2984{
2985 struct mlxsw_sp_port *mlxsw_sp_vport;
2986 u16 vid = vlan_dev_vlan_id(vlan_dev);
2987
2988 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 2989 if (WARN_ON(!mlxsw_sp_vport))
82e6db03 2990 return;
9589a7b5 2991
26f0e7fb
IS		 2992 /* When removing a VLAN device while still bridged we should first
2993 * remove it from the bridge, as we receive the bridge's notification
2994 * when the vPort is already gone.
2995 */
2996 if (mlxsw_sp_vport->bridged) {
2997 struct net_device *br_dev;
2998
2999 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
37286d25 3000 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, true);
26f0e7fb
IS		 3001 }
3002
9589a7b5 3003 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
9589a7b5
IS		 3004}
3005
74581206
JP		 3006static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
3007 unsigned long event, void *ptr)
56ade8fe 3008{
56ade8fe
JP		 3009 struct netdev_notifier_changeupper_info *info;
3010 struct mlxsw_sp_port *mlxsw_sp_port;
3011 struct net_device *upper_dev;
3012 struct mlxsw_sp *mlxsw_sp;
80bedf1a 3013 int err = 0;
56ade8fe 3014
56ade8fe
JP		 3015 mlxsw_sp_port = netdev_priv(dev);
3016 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3017 info = ptr;
3018
3019 switch (event) {
3020 case NETDEV_PRECHANGEUPPER:
3021 upper_dev = info->upper_dev;
59fe9b3f
IS		 3022 if (!is_vlan_dev(upper_dev) &&
3023 !netif_is_lag_master(upper_dev) &&
3024 !netif_is_bridge_master(upper_dev))
3025 return -EINVAL;
6ec43904 3026 if (!info->linking)
0d65fc13 3027 break;
56ade8fe 3028 /* HW limitation forbids to put ports to multiple bridges. */
0d65fc13 3029 if (netif_is_bridge_master(upper_dev) &&
56ade8fe 3030 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
80bedf1a 3031 return -EINVAL;
0d65fc13
JP		 3032 if (netif_is_lag_master(upper_dev) &&
3033 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3034 info->upper_info))
80bedf1a 3035 return -EINVAL;
6ec43904
IS		 3036 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
3037 return -EINVAL;
3038 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
3039 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
3040 return -EINVAL;
56ade8fe
JP		 3041 break;
3042 case NETDEV_CHANGEUPPER:
3043 upper_dev = info->upper_dev;
9589a7b5 3044 if (is_vlan_dev(upper_dev)) {
80bedf1a 3045 if (info->linking)
9589a7b5
IS		 3046 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3047 upper_dev);
80bedf1a 3048 else
82e6db03
IS		 3049 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3050 upper_dev);
9589a7b5 3051 } else if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 3052 if (info->linking)
3053 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3054 upper_dev);
3055 else
82e6db03 3056 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, true);
0d65fc13 3057 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 3058 if (info->linking)
0d65fc13
JP		 3059 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3060 upper_dev);
80bedf1a 3061 else
82e6db03
IS		 3062 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3063 upper_dev);
59fe9b3f
IS		 3064 } else {
3065 err = -EINVAL;
3066 WARN_ON(1);
56ade8fe
JP		 3067 }
3068 break;
3069 }
3070
80bedf1a 3071 return err;
56ade8fe
JP		 3072}
3073
74581206
JP		 3074static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3075 unsigned long event, void *ptr)
3076{
3077 struct netdev_notifier_changelowerstate_info *info;
3078 struct mlxsw_sp_port *mlxsw_sp_port;
3079 int err;
3080
3081 mlxsw_sp_port = netdev_priv(dev);
3082 info = ptr;
3083
3084 switch (event) {
3085 case NETDEV_CHANGELOWERSTATE:
3086 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3087 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3088 info->lower_state_info);
3089 if (err)
3090 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3091 }
3092 break;
3093 }
3094
80bedf1a 3095 return 0;
74581206
JP		 3096}
3097
3098static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3099 unsigned long event, void *ptr)
3100{
3101 switch (event) {
3102 case NETDEV_PRECHANGEUPPER:
3103 case NETDEV_CHANGEUPPER:
3104 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3105 case NETDEV_CHANGELOWERSTATE:
3106 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3107 }
3108
80bedf1a 3109 return 0;
74581206
JP		 3110}
3111
0d65fc13
JP		 3112static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3113 unsigned long event, void *ptr)
3114{
3115 struct net_device *dev;
3116 struct list_head *iter;
3117 int ret;
3118
3119 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3120 if (mlxsw_sp_port_dev_check(dev)) {
3121 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
80bedf1a 3122 if (ret)
0d65fc13
JP		 3123 return ret;
3124 }
3125 }
3126
80bedf1a 3127 return 0;
0d65fc13
JP		 3128}
3129
d0ec875a 3130static struct mlxsw_sp_fid *
26f0e7fb
IS		 3131mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3132 const struct net_device *br_dev)
3133{
d0ec875a 3134 struct mlxsw_sp_fid *f;
26f0e7fb 3135
d0ec875a
IS		 3136 list_for_each_entry(f, &mlxsw_sp->br_vfids.list, list) {
3137 if (f->dev == br_dev)
3138 return f;
26f0e7fb
IS		 3139 }
3140
3141 return NULL;
3142}
3143
3144static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3145{
3146 return vfid - MLXSW_SP_VFID_PORT_MAX;
3147}
3148
3149static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3150{
3151 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3152}
3153
3154static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3155{
3156 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3157 MLXSW_SP_VFID_BR_MAX);
3158}
3159
d0ec875a
IS		 3160static struct mlxsw_sp_fid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3161 struct net_device *br_dev)
26f0e7fb
IS		 3162{
3163 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 3164 struct mlxsw_sp_fid *f;
c7e920b5 3165 u16 vfid, fid;
26f0e7fb
IS		 3166 int err;
3167
c7e920b5
IS		 3168 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3169 if (vfid == MLXSW_SP_VFID_MAX) {
26f0e7fb
IS		 3170 dev_err(dev, "No available vFIDs\n");
3171 return ERR_PTR(-ERANGE);
3172 }
3173
c7e920b5
IS		 3174 fid = mlxsw_sp_vfid_to_fid(vfid);
3175 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
26f0e7fb 3176 if (err) {
c7e920b5 3177 dev_err(dev, "Failed to create FID=%d\n", fid);
26f0e7fb
IS		 3178 return ERR_PTR(err);
3179 }
3180
c7e920b5
IS		 3181 f = kzalloc(sizeof(*f), GFP_KERNEL);
3182 if (!f)
26f0e7fb
IS		 3183 goto err_allocate_vfid;
3184
d0ec875a
IS		 3185 f->fid = fid;
3186 f->dev = br_dev;
26f0e7fb 3187
c7e920b5
IS		 3188 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3189 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
26f0e7fb 3190
c7e920b5 3191 return f;
26f0e7fb
IS		 3192
3193err_allocate_vfid:
c7e920b5 3194 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 3195 return ERR_PTR(-ENOMEM);
3196}
3197
3198static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
d0ec875a 3199 struct mlxsw_sp_fid *f)
26f0e7fb 3200{
d0ec875a
IS		 3201 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
3202 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid);
26f0e7fb
IS		 3203
3204 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
d0ec875a 3205 list_del(&f->list);
26f0e7fb 3206
d0ec875a 3207 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
26f0e7fb 3208
d0ec875a 3209 kfree(f);
26f0e7fb
IS		 3210}
3211
0355b59f
IS		 3212static int mlxsw_sp_vport_br_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3213 struct net_device *br_dev)
26f0e7fb 3214{
0355b59f 3215 struct mlxsw_sp_fid *f;
26f0e7fb
IS		 3216 int err;
3217
0355b59f
IS		 3218 f = mlxsw_sp_br_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
3219 if (!f) {
3220 f = mlxsw_sp_br_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
3221 if (IS_ERR(f))
3222 return PTR_ERR(f);
26f0e7fb
IS		 3223 }
3224
0355b59f
IS		 3225 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
3226 if (err)
3227 goto err_vport_flood_set;
26f0e7fb 3228
0355b59f
IS		 3229 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
3230 if (err)
9c4d4423 3231 goto err_vport_fid_map;
26f0e7fb 3232
41b996cc 3233 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f 3234 f->ref_count++;
6a9863a6 3235
0355b59f 3236 return 0;
039c49a6 3237
0355b59f
IS		 3238err_vport_fid_map:
3239 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3240err_vport_flood_set:
d0ec875a 3241 if (!f->ref_count)
0355b59f
IS		 3242 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3243 return err;
3244}
26f0e7fb 3245
0355b59f
IS		 3246static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3247{
41b996cc 3248 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb 3249
0355b59f 3250 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
26f0e7fb 3251
0355b59f
IS		 3252 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3253
41b996cc 3254 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f
IS		 3255 if (--f->ref_count == 0)
3256 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
26f0e7fb
IS		 3257}
3258
3259static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3260 struct net_device *br_dev)
3261{
26f0e7fb
IS		 3262 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3263 struct net_device *dev = mlxsw_sp_vport->dev;
26f0e7fb
IS		 3264 int err;
3265
0355b59f 3266 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
26f0e7fb 3267
0355b59f 3268 err = mlxsw_sp_vport_br_vfid_join(mlxsw_sp_vport, br_dev);
26f0e7fb 3269 if (err) {
0355b59f
IS		 3270 netdev_err(dev, "Failed to join vFID\n");
3271 goto err_vport_br_vfid_join;
26f0e7fb
IS		 3272 }
3273
3274 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3275 if (err) {
3276 netdev_err(dev, "Failed to enable learning\n");
3277 goto err_port_vid_learning_set;
3278 }
3279
26f0e7fb
IS		 3280 mlxsw_sp_vport->learning = 1;
3281 mlxsw_sp_vport->learning_sync = 1;
3282 mlxsw_sp_vport->uc_flood = 1;
3283 mlxsw_sp_vport->bridged = 1;
3284
3285 return 0;
3286
26f0e7fb 3287err_port_vid_learning_set:
0355b59f
IS		 3288 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3289err_vport_br_vfid_join:
3290 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
26f0e7fb
IS		 3291 return err;
3292}
3293
0355b59f 3294static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
0355b59f
IS		 3295 bool flush_fdb)
3296{
41b996cc 3297 u16 fid = mlxsw_sp_vport_fid_get(mlxsw_sp_vport)->fid;
0355b59f 3298 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
0355b59f
IS		 3299
3300 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3301
3302 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3303
3304 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3305
3306 mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3307 MLXSW_REG_SPMS_STATE_FORWARDING);
3308
3309 if (flush_fdb)
3310 mlxsw_sp_vport_fdb_flush(mlxsw_sp_vport, fid);
3311
3312 mlxsw_sp_vport->learning = 0;
3313 mlxsw_sp_vport->learning_sync = 0;
3314 mlxsw_sp_vport->uc_flood = 0;
3315 mlxsw_sp_vport->bridged = 0;
3316}
3317
26f0e7fb
IS		 3318static bool
3319mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3320 const struct net_device *br_dev)
3321{
3322 struct mlxsw_sp_port *mlxsw_sp_vport;
3323
3324 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3325 vport.list) {
3326 if (mlxsw_sp_vport_br_get(mlxsw_sp_vport) == br_dev)
3327 return false;
3328 }
3329
3330 return true;
3331}
3332
3333static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3334 unsigned long event, void *ptr,
3335 u16 vid)
3336{
3337 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3338 struct netdev_notifier_changeupper_info *info = ptr;
3339 struct mlxsw_sp_port *mlxsw_sp_vport;
3340 struct net_device *upper_dev;
80bedf1a 3341 int err = 0;
26f0e7fb
IS		 3342
3343 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3344
3345 switch (event) {
3346 case NETDEV_PRECHANGEUPPER:
3347 upper_dev = info->upper_dev;
26f0e7fb 3348 if (!netif_is_bridge_master(upper_dev))
80bedf1a 3349 return -EINVAL;
ddbe993d
IS		 3350 if (!info->linking)
3351 break;
26f0e7fb
IS		 3352 /* We can't have multiple VLAN interfaces configured on
3353 * the same port and being members in the same bridge.
3354 */
3355 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3356 upper_dev))
80bedf1a 3357 return -EINVAL;
26f0e7fb
IS		 3358 break;
3359 case NETDEV_CHANGEUPPER:
3360 upper_dev = info->upper_dev;
26f0e7fb 3361 if (info->linking) {
423b937e 3362 if (WARN_ON(!mlxsw_sp_vport))
80bedf1a 3363 return -EINVAL;
26f0e7fb
IS		 3364 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3365 upper_dev);
26f0e7fb
IS		 3366 } else {
3367 /* We ignore bridge's unlinking notifications if vPort
3368 * is gone, since we already left the bridge when the
3369 * VLAN device was unlinked from the real device.
3370 */
3371 if (!mlxsw_sp_vport)
80bedf1a 3372 return 0;
37286d25 3373 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, true);
26f0e7fb
IS		 3374 }
3375 }
3376
80bedf1a 3377 return err;
26f0e7fb
IS		 3378}
3379
272c4470
IS		 3380static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3381 unsigned long event, void *ptr,
3382 u16 vid)
3383{
3384 struct net_device *dev;
3385 struct list_head *iter;
3386 int ret;
3387
3388 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3389 if (mlxsw_sp_port_dev_check(dev)) {
3390 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3391 vid);
80bedf1a 3392 if (ret)
272c4470
IS		 3393 return ret;
3394 }
3395 }
3396
80bedf1a 3397 return 0;
272c4470
IS		 3398}
3399
26f0e7fb
IS		 3400static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3401 unsigned long event, void *ptr)
3402{
3403 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3404 u16 vid = vlan_dev_vlan_id(vlan_dev);
3405
272c4470
IS		 3406 if (mlxsw_sp_port_dev_check(real_dev))
3407 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3408 vid);
3409 else if (netif_is_lag_master(real_dev))
3410 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3411 vid);
26f0e7fb 3412
80bedf1a 3413 return 0;
26f0e7fb
IS		 3414}
3415
0d65fc13
JP		 3416static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3417 unsigned long event, void *ptr)
3418{
3419 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
80bedf1a 3420 int err = 0;
0d65fc13
JP		 3421
3422 if (mlxsw_sp_port_dev_check(dev))
80bedf1a
IS		 3423 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3424 else if (netif_is_lag_master(dev))
3425 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3426 else if (is_vlan_dev(dev))
3427 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 3428
80bedf1a 3429 return notifier_from_errno(err);
0d65fc13
JP		 3430}
3431
56ade8fe
JP		 3432static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3433 .notifier_call = mlxsw_sp_netdevice_event,
3434};
3435
3436static int __init mlxsw_sp_module_init(void)
3437{
3438 int err;
3439
3440 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3441 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3442 if (err)
3443 goto err_core_driver_register;
3444 return 0;
3445
3446err_core_driver_register:
3447 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3448 return err;
3449}
3450
3451static void __exit mlxsw_sp_module_exit(void)
3452{
3453 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3454 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3455}
3456
3457module_init(mlxsw_sp_module_init);
3458module_exit(mlxsw_sp_module_exit);
3459
3460MODULE_LICENSE("Dual BSD/GPL");
3461MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3462MODULE_DESCRIPTION("Mellanox Spectrum driver");
3463MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);
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