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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
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56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
56ade8fe 56#include <net/switchdev.h>
763b4b70
YG		 57#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
e7322638 59#include <net/netevent.h>
98d0f7b9 60#include <net/tc_act/tc_sample.h>
56ade8fe
JP		 61
62#include "spectrum.h"
1d20d23c 63#include "pci.h"
56ade8fe
JP		 64#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
69
70static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
71static const char mlxsw_sp_driver_version[] = "1.0";
72
73/* tx_hdr_version
74 * Tx header version.
75 * Must be set to 1.
76 */
77MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
78
79/* tx_hdr_ctl
80 * Packet control type.
81 * 0 - Ethernet control (e.g. EMADs, LACP)
82 * 1 - Ethernet data
83 */
84MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
85
86/* tx_hdr_proto
87 * Packet protocol type. Must be set to 1 (Ethernet).
88 */
89MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
90
91/* tx_hdr_rx_is_router
92 * Packet is sent from the router. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
95
96/* tx_hdr_fid_valid
97 * Indicates if the 'fid' field is valid and should be used for
98 * forwarding lookup. Valid for data packets only.
99 */
100MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
101
102/* tx_hdr_swid
103 * Switch partition ID. Must be set to 0.
104 */
105MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
106
107/* tx_hdr_control_tclass
108 * Indicates if the packet should use the control TClass and not one
109 * of the data TClasses.
110 */
111MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
112
113/* tx_hdr_etclass
114 * Egress TClass to be used on the egress device on the egress port.
115 */
116MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
117
118/* tx_hdr_port_mid
119 * Destination local port for unicast packets.
120 * Destination multicast ID for multicast packets.
121 *
122 * Control packets are directed to a specific egress port, while data
123 * packets are transmitted through the CPU port (0) into the switch partition,
124 * where forwarding rules are applied.
125 */
126MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
127
128/* tx_hdr_fid
129 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
130 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
131 * Valid for data packets only.
132 */
133MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
134
135/* tx_hdr_type
136 * 0 - Data packets
137 * 6 - Control packets
138 */
139MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
140
763b4b70
YG		 141static bool mlxsw_sp_port_dev_check(const struct net_device *dev);
142
56ade8fe
JP		 143static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
144 const struct mlxsw_tx_info *tx_info)
145{
146 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
147
148 memset(txhdr, 0, MLXSW_TXHDR_LEN);
149
150 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
151 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
152 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
153 mlxsw_tx_hdr_swid_set(txhdr, 0);
154 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
155 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
156 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
157}
158
159static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
160{
5b090740 161 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
56ade8fe
JP		 162 int err;
163
164 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
165 if (err)
166 return err;
167 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
168 return 0;
169}
170
763b4b70
YG		 171static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
172{
763b4b70
YG		 173 int i;
174
c1a38311 175 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 176 return -EIO;
177
c1a38311
JP		 178 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
179 MAX_SPAN);
763b4b70
YG		 180 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
181 sizeof(struct mlxsw_sp_span_entry),
182 GFP_KERNEL);
183 if (!mlxsw_sp->span.entries)
184 return -ENOMEM;
185
186 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
187 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
188
189 return 0;
190}
191
192static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
193{
194 int i;
195
196 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
197 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
198
199 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
200 }
201 kfree(mlxsw_sp->span.entries);
202}
203
204static struct mlxsw_sp_span_entry *
205mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
206{
207 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
208 struct mlxsw_sp_span_entry *span_entry;
209 char mpat_pl[MLXSW_REG_MPAT_LEN];
210 u8 local_port = port->local_port;
211 int index;
212 int i;
213 int err;
214
215 /* find a free entry to use */
216 index = -1;
217 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
218 if (!mlxsw_sp->span.entries[i].used) {
219 index = i;
220 span_entry = &mlxsw_sp->span.entries[i];
221 break;
222 }
223 }
224 if (index < 0)
225 return NULL;
226
227 /* create a new port analayzer entry for local_port */
228 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
229 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
230 if (err)
231 return NULL;
232
233 span_entry->used = true;
234 span_entry->id = index;
2d644d4c 235 span_entry->ref_count = 1;
763b4b70
YG		 236 span_entry->local_port = local_port;
237 return span_entry;
238}
239
240static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
241 struct mlxsw_sp_span_entry *span_entry)
242{
243 u8 local_port = span_entry->local_port;
244 char mpat_pl[MLXSW_REG_MPAT_LEN];
245 int pa_id = span_entry->id;
246
247 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
248 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
249 span_entry->used = false;
250}
251
1a9234e6
IS		 252static struct mlxsw_sp_span_entry *
253mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
763b4b70
YG		 254{
255 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
256 int i;
257
258 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
259 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
260
261 if (curr->used && curr->local_port == port->local_port)
262 return curr;
263 }
264 return NULL;
265}
266
1a9234e6
IS		 267static struct mlxsw_sp_span_entry
268*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 269{
270 struct mlxsw_sp_span_entry *span_entry;
271
272 span_entry = mlxsw_sp_span_entry_find(port);
273 if (span_entry) {
2d644d4c 274 /* Already exists, just take a reference */
763b4b70
YG		 275 span_entry->ref_count++;
276 return span_entry;
277 }
278
279 return mlxsw_sp_span_entry_create(port);
280}
281
282static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
283 struct mlxsw_sp_span_entry *span_entry)
284{
2d644d4c 285 WARN_ON(!span_entry->ref_count);
763b4b70
YG		 286 if (--span_entry->ref_count == 0)
287 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
288 return 0;
289}
290
291static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
292{
293 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
294 struct mlxsw_sp_span_inspected_port *p;
295 int i;
296
297 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
298 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
299
300 list_for_each_entry(p, &curr->bound_ports_list, list)
301 if (p->local_port == port->local_port &&
302 p->type == MLXSW_SP_SPAN_EGRESS)
303 return true;
304 }
305
306 return false;
307}
308
309static int mlxsw_sp_span_mtu_to_buffsize(int mtu)
310{
311 return MLXSW_SP_BYTES_TO_CELLS(mtu * 5 / 2) + 1;
312}
313
314static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
315{
316 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
317 char sbib_pl[MLXSW_REG_SBIB_LEN];
318 int err;
319
320 /* If port is egress mirrored, the shared buffer size should be
321 * updated according to the mtu value
322 */
323 if (mlxsw_sp_span_is_egress_mirror(port)) {
324 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
325 mlxsw_sp_span_mtu_to_buffsize(mtu));
326 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
327 if (err) {
328 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
329 return err;
330 }
331 }
332
333 return 0;
334}
335
336static struct mlxsw_sp_span_inspected_port *
337mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
338 struct mlxsw_sp_span_entry *span_entry)
339{
340 struct mlxsw_sp_span_inspected_port *p;
341
342 list_for_each_entry(p, &span_entry->bound_ports_list, list)
343 if (port->local_port == p->local_port)
344 return p;
345 return NULL;
346}
347
348static int
349mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
350 struct mlxsw_sp_span_entry *span_entry,
351 enum mlxsw_sp_span_type type)
352{
353 struct mlxsw_sp_span_inspected_port *inspected_port;
354 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
355 char mpar_pl[MLXSW_REG_MPAR_LEN];
356 char sbib_pl[MLXSW_REG_SBIB_LEN];
357 int pa_id = span_entry->id;
358 int err;
359
360 /* if it is an egress SPAN, bind a shared buffer to it */
361 if (type == MLXSW_SP_SPAN_EGRESS) {
362 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
363 mlxsw_sp_span_mtu_to_buffsize(port->dev->mtu));
364 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
365 if (err) {
366 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
367 return err;
368 }
369 }
370
371 /* bind the port to the SPAN entry */
1a9234e6
IS		 372 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
373 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
763b4b70
YG		 374 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
375 if (err)
376 goto err_mpar_reg_write;
377
378 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
379 if (!inspected_port) {
380 err = -ENOMEM;
381 goto err_inspected_port_alloc;
382 }
383 inspected_port->local_port = port->local_port;
384 inspected_port->type = type;
385 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
386
387 return 0;
388
389err_mpar_reg_write:
390err_inspected_port_alloc:
391 if (type == MLXSW_SP_SPAN_EGRESS) {
392 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
393 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
394 }
395 return err;
396}
397
398static void
399mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
400 struct mlxsw_sp_span_entry *span_entry,
401 enum mlxsw_sp_span_type type)
402{
403 struct mlxsw_sp_span_inspected_port *inspected_port;
404 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
405 char mpar_pl[MLXSW_REG_MPAR_LEN];
406 char sbib_pl[MLXSW_REG_SBIB_LEN];
407 int pa_id = span_entry->id;
408
409 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
410 if (!inspected_port)
411 return;
412
413 /* remove the inspected port */
1a9234e6
IS		 414 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
415 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
763b4b70
YG		 416 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
417
418 /* remove the SBIB buffer if it was egress SPAN */
419 if (type == MLXSW_SP_SPAN_EGRESS) {
420 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
421 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
422 }
423
424 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
425
426 list_del(&inspected_port->list);
427 kfree(inspected_port);
428}
429
430static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
431 struct mlxsw_sp_port *to,
432 enum mlxsw_sp_span_type type)
433{
434 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
435 struct mlxsw_sp_span_entry *span_entry;
436 int err;
437
438 span_entry = mlxsw_sp_span_entry_get(to);
439 if (!span_entry)
440 return -ENOENT;
441
442 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
443 span_entry->id);
444
445 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
446 if (err)
447 goto err_port_bind;
448
449 return 0;
450
451err_port_bind:
452 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
453 return err;
454}
455
456static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
457 struct mlxsw_sp_port *to,
458 enum mlxsw_sp_span_type type)
459{
460 struct mlxsw_sp_span_entry *span_entry;
461
462 span_entry = mlxsw_sp_span_entry_find(to);
463 if (!span_entry) {
464 netdev_err(from->dev, "no span entry found\n");
465 return;
466 }
467
468 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
469 span_entry->id);
470 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
471}
472
98d0f7b9
YG		 473static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
474 bool enable, u32 rate)
475{
476 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
477 char mpsc_pl[MLXSW_REG_MPSC_LEN];
478
479 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
480 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
481}
482
56ade8fe
JP		 483static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
484 bool is_up)
485{
486 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
487 char paos_pl[MLXSW_REG_PAOS_LEN];
488
489 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
490 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
491 MLXSW_PORT_ADMIN_STATUS_DOWN);
492 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
493}
494
56ade8fe
JP		 495static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
496 unsigned char *addr)
497{
498 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
499 char ppad_pl[MLXSW_REG_PPAD_LEN];
500
501 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
502 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
503 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
504}
505
506static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
507{
508 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
509 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
510
511 ether_addr_copy(addr, mlxsw_sp->base_mac);
512 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
513 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
514}
515
56ade8fe
JP		 516static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
517{
518 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
519 char pmtu_pl[MLXSW_REG_PMTU_LEN];
520 int max_mtu;
521 int err;
522
523 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
524 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
525 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
526 if (err)
527 return err;
528 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
529
530 if (mtu > max_mtu)
531 return -EINVAL;
532
533 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
534 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
535}
536
be94535f
IS		 537static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
538 u8 swid)
56ade8fe 539{
56ade8fe
JP		 540 char pspa_pl[MLXSW_REG_PSPA_LEN];
541
be94535f 542 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
56ade8fe
JP		 543 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
544}
545
be94535f
IS		 546static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
547{
548 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
549
550 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
551 swid);
552}
553
56ade8fe
JP		 554static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
555 bool enable)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
558 char svpe_pl[MLXSW_REG_SVPE_LEN];
559
560 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
562}
563
564int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
565 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
566 u16 vid)
567{
568 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
569 char svfa_pl[MLXSW_REG_SVFA_LEN];
570
571 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
572 fid, vid);
573 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
574}
575
584d73df
IS		 576int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
577 u16 vid_begin, u16 vid_end,
578 bool learn_enable)
56ade8fe
JP		 579{
580 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
581 char *spvmlr_pl;
582 int err;
583
584 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
585 if (!spvmlr_pl)
586 return -ENOMEM;
584d73df
IS		 587 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid_begin,
588 vid_end, learn_enable);
56ade8fe
JP		 589 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
590 kfree(spvmlr_pl);
591 return err;
592}
593
584d73df
IS		 594static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
595 u16 vid, bool learn_enable)
596{
597 return __mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, vid,
598 learn_enable);
599}
600
56ade8fe
JP		 601static int
602mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
603{
604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
605 char sspr_pl[MLXSW_REG_SSPR_LEN];
606
607 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
608 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
609}
610
d664b41e
IS		 611static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
612 u8 local_port, u8 *p_module,
613 u8 *p_width, u8 *p_lane)
56ade8fe 614{
56ade8fe
JP		 615 char pmlp_pl[MLXSW_REG_PMLP_LEN];
616 int err;
617
558c2d5e 618 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 619 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
620 if (err)
621 return err;
558c2d5e
IS		 622 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
623 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 624 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 625 return 0;
626}
627
18f1e70c
IS		 628static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
629 u8 module, u8 width, u8 lane)
630{
631 char pmlp_pl[MLXSW_REG_PMLP_LEN];
632 int i;
633
634 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
635 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
636 for (i = 0; i < width; i++) {
637 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
638 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
639 }
640
641 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
642}
643
3e9b27b8
IS		 644static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
645{
646 char pmlp_pl[MLXSW_REG_PMLP_LEN];
647
648 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
649 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
650 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
651}
652
56ade8fe
JP		 653static int mlxsw_sp_port_open(struct net_device *dev)
654{
655 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
656 int err;
657
658 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
659 if (err)
660 return err;
661 netif_start_queue(dev);
662 return 0;
663}
664
665static int mlxsw_sp_port_stop(struct net_device *dev)
666{
667 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
668
669 netif_stop_queue(dev);
670 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
671}
672
673static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
674 struct net_device *dev)
675{
676 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
677 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
678 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
679 const struct mlxsw_tx_info tx_info = {
680 .local_port = mlxsw_sp_port->local_port,
681 .is_emad = false,
682 };
683 u64 len;
684 int err;
685
307c2431 686 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 687 return NETDEV_TX_BUSY;
688
689 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
690 struct sk_buff *skb_orig = skb;
691
692 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
693 if (!skb) {
694 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
695 dev_kfree_skb_any(skb_orig);
696 return NETDEV_TX_OK;
697 }
36bf38d1 698 dev_consume_skb_any(skb_orig);
56ade8fe
JP		 699 }
700
701 if (eth_skb_pad(skb)) {
702 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
703 return NETDEV_TX_OK;
704 }
705
706 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 707 /* TX header is consumed by HW on the way so we shouldn't count its
708 * bytes as being sent.
709 */
710 len = skb->len - MLXSW_TXHDR_LEN;
711
56ade8fe
JP		 712 /* Due to a race we might fail here because of a full queue. In that
713 * unlikely case we simply drop the packet.
714 */
307c2431 715 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 716
717 if (!err) {
718 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
719 u64_stats_update_begin(&pcpu_stats->syncp);
720 pcpu_stats->tx_packets++;
721 pcpu_stats->tx_bytes += len;
722 u64_stats_update_end(&pcpu_stats->syncp);
723 } else {
724 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
725 dev_kfree_skb_any(skb);
726 }
727 return NETDEV_TX_OK;
728}
729
c5b9b518
JP		 730static void mlxsw_sp_set_rx_mode(struct net_device *dev)
731{
732}
733
56ade8fe
JP		 734static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
735{
736 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
737 struct sockaddr *addr = p;
738 int err;
739
740 if (!is_valid_ether_addr(addr->sa_data))
741 return -EADDRNOTAVAIL;
742
743 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
744 if (err)
745 return err;
746 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
747 return 0;
748}
749
9f7ec052 750static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
d81a6bdb 751 bool pause_en, bool pfc_en, u16 delay)
ff6551ec 752{
ff6551ec 753 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
8e8dfe9f 754
d81a6bdb
IS		 755 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
756 MLXSW_SP_PAUSE_DELAY;
9f7ec052 757
d81a6bdb 758 if (pause_en || pfc_en)
9f7ec052 759 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
d81a6bdb
IS		 760 pg_size + delay, pg_size);
761 else
9f7ec052 762 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
8e8dfe9f
IS		 763}
764
765int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 766 u8 *prio_tc, bool pause_en,
767 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 768{
769 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 770 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
771 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 772 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 773 int i, j, err;
ff6551ec
IS		 774
775 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
776 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
777 if (err)
778 return err;
8e8dfe9f
IS		 779
780 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
781 bool configure = false;
d81a6bdb 782 bool pfc = false;
8e8dfe9f
IS		 783
784 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
785 if (prio_tc[j] == i) {
d81a6bdb 786 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 787 configure = true;
788 break;
789 }
790 }
791
792 if (!configure)
793 continue;
d81a6bdb 794 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
8e8dfe9f
IS		 795 }
796
ff6551ec
IS		 797 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
798}
799
8e8dfe9f 800static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 801 int mtu, bool pause_en)
8e8dfe9f
IS		 802{
803 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
804 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 805 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 806 u8 *prio_tc;
807
808 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 809 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 810
9f7ec052 811 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 812 pause_en, my_pfc);
8e8dfe9f
IS		 813}
814
56ade8fe
JP		 815static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
816{
817 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 818 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 819 int err;
820
9f7ec052 821 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 822 if (err)
823 return err;
763b4b70
YG		 824 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
825 if (err)
826 goto err_span_port_mtu_update;
ff6551ec
IS		 827 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
828 if (err)
829 goto err_port_mtu_set;
56ade8fe
JP		 830 dev->mtu = mtu;
831 return 0;
ff6551ec
IS		 832
833err_port_mtu_set:
763b4b70
YG		 834 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
835err_span_port_mtu_update:
9f7ec052 836 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 837 return err;
56ade8fe
JP		 838}
839
4bdcc6ca 840static int
fc1bbb0f
NF		 841mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
842 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 843{
844 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
845 struct mlxsw_sp_port_pcpu_stats *p;
846 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
847 u32 tx_dropped = 0;
848 unsigned int start;
849 int i;
850
851 for_each_possible_cpu(i) {
852 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
853 do {
854 start = u64_stats_fetch_begin_irq(&p->syncp);
855 rx_packets = p->rx_packets;
856 rx_bytes = p->rx_bytes;
857 tx_packets = p->tx_packets;
858 tx_bytes = p->tx_bytes;
859 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
860
861 stats->rx_packets += rx_packets;
862 stats->rx_bytes += rx_bytes;
863 stats->tx_packets += tx_packets;
864 stats->tx_bytes += tx_bytes;
865 /* tx_dropped is u32, updated without syncp protection. */
866 tx_dropped += p->tx_dropped;
867 }
868 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 869 return 0;
870}
871
3df5b3c6 872static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
fc1bbb0f
NF		 873{
874 switch (attr_id) {
875 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
876 return true;
877 }
878
879 return false;
880}
881
4bdcc6ca
OG		 882static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
883 void *sp)
fc1bbb0f
NF		 884{
885 switch (attr_id) {
886 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
887 return mlxsw_sp_port_get_sw_stats64(dev, sp);
888 }
889
890 return -EINVAL;
891}
892
893static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
894 int prio, char *ppcnt_pl)
895{
896 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
897 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
898
899 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
900 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
901}
902
903static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
904 struct rtnl_link_stats64 *stats)
905{
906 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
907 int err;
908
909 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
910 0, ppcnt_pl);
911 if (err)
912 goto out;
913
914 stats->tx_packets =
915 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
916 stats->rx_packets =
917 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
918 stats->tx_bytes =
919 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
920 stats->rx_bytes =
921 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
922 stats->multicast =
923 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
924
925 stats->rx_crc_errors =
926 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
927 stats->rx_frame_errors =
928 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
929
930 stats->rx_length_errors = (
931 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
932 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
933 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
934
935 stats->rx_errors = (stats->rx_crc_errors +
936 stats->rx_frame_errors + stats->rx_length_errors);
937
938out:
939 return err;
940}
941
942static void update_stats_cache(struct work_struct *work)
943{
944 struct mlxsw_sp_port *mlxsw_sp_port =
945 container_of(work, struct mlxsw_sp_port,
946 hw_stats.update_dw.work);
947
948 if (!netif_carrier_ok(mlxsw_sp_port->dev))
949 goto out;
950
951 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
952 mlxsw_sp_port->hw_stats.cache);
953
954out:
955 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
956 MLXSW_HW_STATS_UPDATE_TIME);
957}
958
959/* Return the stats from a cache that is updated periodically,
960 * as this function might get called in an atomic context.
961 */
bc1f4470 962static void
fc1bbb0f
NF		 963mlxsw_sp_port_get_stats64(struct net_device *dev,
964 struct rtnl_link_stats64 *stats)
965{
966 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
967
968 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
56ade8fe
JP		 969}
970
971int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
972 u16 vid_end, bool is_member, bool untagged)
973{
974 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
975 char *spvm_pl;
976 int err;
977
978 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
979 if (!spvm_pl)
980 return -ENOMEM;
981
982 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
983 vid_end, is_member, untagged);
984 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
985 kfree(spvm_pl);
986 return err;
987}
988
989static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
990{
991 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
992 u16 vid, last_visited_vid;
993 int err;
994
995 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
996 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
997 vid);
998 if (err) {
999 last_visited_vid = vid;
1000 goto err_port_vid_to_fid_set;
1001 }
1002 }
1003
1004 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
1005 if (err) {
1006 last_visited_vid = VLAN_N_VID;
1007 goto err_port_vid_to_fid_set;
1008 }
1009
1010 return 0;
1011
1012err_port_vid_to_fid_set:
1013 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1014 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1015 vid);
1016 return err;
1017}
1018
1019static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1020{
1021 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1022 u16 vid;
1023 int err;
1024
1025 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1026 if (err)
1027 return err;
1028
1029 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1030 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1031 vid, vid);
1032 if (err)
1033 return err;
1034 }
1035
1036 return 0;
1037}
1038
7f71eb46 1039static struct mlxsw_sp_port *
0355b59f 1040mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
7f71eb46
IS		 1041{
1042 struct mlxsw_sp_port *mlxsw_sp_vport;
1043
1044 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1045 if (!mlxsw_sp_vport)
1046 return NULL;
1047
1048 /* dev will be set correctly after the VLAN device is linked
1049 * with the real device. In case of bridge SELF invocation, dev
1050 * will remain as is.
1051 */
1052 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1053 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1054 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1055 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
272c4470
IS		 1056 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1057 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
0355b59f 1058 mlxsw_sp_vport->vport.vid = vid;
7f71eb46
IS		 1059
1060 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1061
1062 return mlxsw_sp_vport;
1063}
1064
1065static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1066{
1067 list_del(&mlxsw_sp_vport->vport.list);
1068 kfree(mlxsw_sp_vport);
1069}
1070
05978481
IS		 1071static int mlxsw_sp_port_add_vid(struct net_device *dev,
1072 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1073{
1074 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 1075 struct mlxsw_sp_port *mlxsw_sp_vport;
52697a9e 1076 bool untagged = vid == 1;
56ade8fe
JP		 1077 int err;
1078
1079 /* VLAN 0 is added to HW filter when device goes up, but it is
1080 * reserved in our case, so simply return.
1081 */
1082 if (!vid)
1083 return 0;
1084
fa66d7e3 1085 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
56ade8fe 1086 return 0;
56ade8fe 1087
0355b59f 1088 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
fa66d7e3 1089 if (!mlxsw_sp_vport)
0355b59f 1090 return -ENOMEM;
56ade8fe 1091
56ade8fe
JP		 1092 /* When adding the first VLAN interface on a bridged port we need to
1093 * transition all the active 802.1Q bridge VLANs to use explicit
1094 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1095 */
7f71eb46 1096 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe 1097 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
fa66d7e3 1098 if (err)
7f71eb46 1099 goto err_port_vp_mode_trans;
56ade8fe
JP		 1100 }
1101
52697a9e 1102 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
fa66d7e3 1103 if (err)
56ade8fe 1104 goto err_port_add_vid;
56ade8fe 1105
56ade8fe
JP		 1106 return 0;
1107
56ade8fe 1108err_port_add_vid:
7f71eb46
IS		 1109 if (list_is_singular(&mlxsw_sp_port->vports_list))
1110 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1111err_port_vp_mode_trans:
7f71eb46 1112 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
56ade8fe
JP		 1113 return err;
1114}
1115
32d863fb
IS		 1116static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1117 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1118{
1119 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 1120 struct mlxsw_sp_port *mlxsw_sp_vport;
1c800759 1121 struct mlxsw_sp_fid *f;
56ade8fe
JP		 1122
1123 /* VLAN 0 is removed from HW filter when device goes down, but
1124 * it is reserved in our case, so simply return.
1125 */
1126 if (!vid)
1127 return 0;
1128
7f71eb46 1129 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
7a35583e 1130 if (WARN_ON(!mlxsw_sp_vport))
56ade8fe 1131 return 0;
56ade8fe 1132
7a35583e 1133 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe 1134
1c800759
IS		 1135 /* Drop FID reference. If this was the last reference the
1136 * resources will be freed.
1137 */
1138 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1139 if (f && !WARN_ON(!f->leave))
1140 f->leave(mlxsw_sp_vport);
56ade8fe
JP		 1141
1142 /* When removing the last VLAN interface on a bridged port we need to
1143 * transition all active 802.1Q bridge VLANs to use VID to FID
1144 * mappings and set port's mode to VLAN mode.
1145 */
7a35583e
IS		 1146 if (list_is_singular(&mlxsw_sp_port->vports_list))
1147 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
56ade8fe 1148
7f71eb46
IS		 1149 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1150
56ade8fe
JP		 1151 return 0;
1152}
1153
2bf9a586
IS		 1154static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1155 size_t len)
1156{
1157 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1158 u8 module = mlxsw_sp_port->mapping.module;
1159 u8 width = mlxsw_sp_port->mapping.width;
1160 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1161 int err;
1162
2bf9a586
IS		 1163 if (!mlxsw_sp_port->split)
1164 err = snprintf(name, len, "p%d", module + 1);
1165 else
1166 err = snprintf(name, len, "p%ds%d", module + 1,
1167 lane / width);
1168
1169 if (err >= len)
1170 return -EINVAL;
1171
1172 return 0;
1173}
1174
763b4b70 1175static struct mlxsw_sp_port_mall_tc_entry *
65acb5d0
YG		 1176mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1177 unsigned long cookie) {
763b4b70
YG		 1178 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1179
1180 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1181 if (mall_tc_entry->cookie == cookie)
1182 return mall_tc_entry;
1183
1184 return NULL;
1185}
1186
1187static int
1188mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
65acb5d0 1189 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
763b4b70
YG		 1190 const struct tc_action *a,
1191 bool ingress)
1192{
763b4b70
YG		 1193 struct net *net = dev_net(mlxsw_sp_port->dev);
1194 enum mlxsw_sp_span_type span_type;
1195 struct mlxsw_sp_port *to_port;
1196 struct net_device *to_dev;
1197 int ifindex;
763b4b70
YG		 1198
1199 ifindex = tcf_mirred_ifindex(a);
1200 to_dev = __dev_get_by_index(net, ifindex);
1201 if (!to_dev) {
1202 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1203 return -EINVAL;
1204 }
1205
1206 if (!mlxsw_sp_port_dev_check(to_dev)) {
1207 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
e915ac68 1208 return -EOPNOTSUPP;
763b4b70
YG		 1209 }
1210 to_port = netdev_priv(to_dev);
1211
65acb5d0
YG		 1212 mirror->to_local_port = to_port->local_port;
1213 mirror->ingress = ingress;
763b4b70 1214 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
65acb5d0
YG		 1215 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1216}
763b4b70 1217
65acb5d0
YG		 1218static void
1219mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1220 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1221{
1222 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1223 enum mlxsw_sp_span_type span_type;
1224 struct mlxsw_sp_port *to_port;
1225
1226 to_port = mlxsw_sp->ports[mirror->to_local_port];
1227 span_type = mirror->ingress ?
1228 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1229 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
763b4b70
YG		 1230}
1231
98d0f7b9
YG		 1232static int
1233mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1234 struct tc_cls_matchall_offload *cls,
1235 const struct tc_action *a,
1236 bool ingress)
1237{
1238 int err;
1239
1240 if (!mlxsw_sp_port->sample)
1241 return -EOPNOTSUPP;
1242 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1243 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1244 return -EEXIST;
1245 }
1246 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1247 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1248 return -EOPNOTSUPP;
1249 }
1250
1251 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1252 tcf_sample_psample_group(a));
1253 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1254 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1255 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1256
1257 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1258 if (err)
1259 goto err_port_sample_set;
1260 return 0;
1261
1262err_port_sample_set:
1263 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1264 return err;
1265}
1266
1267static void
1268mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1269{
1270 if (!mlxsw_sp_port->sample)
1271 return;
1272
1273 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1274 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1275}
1276
763b4b70
YG		 1277static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1278 __be16 protocol,
1279 struct tc_cls_matchall_offload *cls,
1280 bool ingress)
1281{
65acb5d0 1282 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
763b4b70 1283 const struct tc_action *a;
22dc13c8 1284 LIST_HEAD(actions);
763b4b70
YG		 1285 int err;
1286
86cb13e4 1287 if (!tc_single_action(cls->exts)) {
763b4b70 1288 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
e915ac68 1289 return -EOPNOTSUPP;
763b4b70
YG		 1290 }
1291
65acb5d0
YG		 1292 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1293 if (!mall_tc_entry)
1294 return -ENOMEM;
1295 mall_tc_entry->cookie = cls->cookie;
1296
22dc13c8 1297 tcf_exts_to_list(cls->exts, &actions);
65acb5d0 1298 a = list_first_entry(&actions, struct tc_action, list);
86cb13e4 1299
65acb5d0
YG		 1300 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1301 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1302
1303 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1304 mirror = &mall_tc_entry->mirror;
1305 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1306 mirror, a, ingress);
98d0f7b9
YG		 1307 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1308 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1309 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1310 a, ingress);
65acb5d0
YG		 1311 } else {
1312 err = -EOPNOTSUPP;
763b4b70
YG		 1313 }
1314
65acb5d0
YG		 1315 if (err)
1316 goto err_add_action;
1317
1318 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
763b4b70 1319 return 0;
65acb5d0
YG		 1320
1321err_add_action:
1322 kfree(mall_tc_entry);
1323 return err;
763b4b70
YG		 1324}
1325
1326static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1327 struct tc_cls_matchall_offload *cls)
1328{
763b4b70 1329 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
763b4b70 1330
65acb5d0
YG		 1331 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1332 cls->cookie);
763b4b70
YG		 1333 if (!mall_tc_entry) {
1334 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1335 return;
1336 }
65acb5d0 1337 list_del(&mall_tc_entry->list);
763b4b70
YG		 1338
1339 switch (mall_tc_entry->type) {
1340 case MLXSW_SP_PORT_MALL_MIRROR:
65acb5d0
YG		 1341 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1342 &mall_tc_entry->mirror);
763b4b70 1343 break;
98d0f7b9
YG		 1344 case MLXSW_SP_PORT_MALL_SAMPLE:
1345 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1346 break;
763b4b70
YG		 1347 default:
1348 WARN_ON(1);
1349 }
1350
763b4b70
YG		 1351 kfree(mall_tc_entry);
1352}
1353
1354static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1355 __be16 proto, struct tc_to_netdev *tc)
1356{
1357 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1358 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1359
1360 if (tc->type == TC_SETUP_MATCHALL) {
1361 switch (tc->cls_mall->command) {
1362 case TC_CLSMATCHALL_REPLACE:
1363 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1364 proto,
1365 tc->cls_mall,
1366 ingress);
1367 case TC_CLSMATCHALL_DESTROY:
1368 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1369 tc->cls_mall);
1370 return 0;
1371 default:
1372 return -EINVAL;
1373 }
1374 }
1375
e915ac68 1376 return -EOPNOTSUPP;
763b4b70
YG		 1377}
1378
56ade8fe
JP		 1379static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1380 .ndo_open = mlxsw_sp_port_open,
1381 .ndo_stop = mlxsw_sp_port_stop,
1382 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 1383 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 1384 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 1385 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1386 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1387 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 1388 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1389 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 1390 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1391 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
6cf3c971
JP		 1392 .ndo_neigh_construct = mlxsw_sp_router_neigh_construct,
1393 .ndo_neigh_destroy = mlxsw_sp_router_neigh_destroy,
56ade8fe
JP		 1394 .ndo_fdb_add = switchdev_port_fdb_add,
1395 .ndo_fdb_del = switchdev_port_fdb_del,
1396 .ndo_fdb_dump = switchdev_port_fdb_dump,
1397 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1398 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1399 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
2bf9a586 1400 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 1401};
1402
1403static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1404 struct ethtool_drvinfo *drvinfo)
1405{
1406 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1407 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1408
1409 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1410 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1411 sizeof(drvinfo->version));
1412 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1413 "%d.%d.%d",
1414 mlxsw_sp->bus_info->fw_rev.major,
1415 mlxsw_sp->bus_info->fw_rev.minor,
1416 mlxsw_sp->bus_info->fw_rev.subminor);
1417 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1418 sizeof(drvinfo->bus_info));
1419}
1420
9f7ec052
IS		 1421static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1422 struct ethtool_pauseparam *pause)
1423{
1424 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1425
1426 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1427 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1428}
1429
1430static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1431 struct ethtool_pauseparam *pause)
1432{
1433 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1434
1435 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1436 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1437 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1438
1439 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1440 pfcc_pl);
1441}
1442
1443static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1444 struct ethtool_pauseparam *pause)
1445{
1446 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1447 bool pause_en = pause->tx_pause || pause->rx_pause;
1448 int err;
1449
d81a6bdb
IS		 1450 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1451 netdev_err(dev, "PFC already enabled on port\n");
1452 return -EINVAL;
1453 }
1454
9f7ec052
IS		 1455 if (pause->autoneg) {
1456 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1457 return -EINVAL;
1458 }
1459
1460 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1461 if (err) {
1462 netdev_err(dev, "Failed to configure port's headroom\n");
1463 return err;
1464 }
1465
1466 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1467 if (err) {
1468 netdev_err(dev, "Failed to set PAUSE parameters\n");
1469 goto err_port_pause_configure;
1470 }
1471
1472 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1473 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1474
1475 return 0;
1476
1477err_port_pause_configure:
1478 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1479 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1480 return err;
1481}
1482
56ade8fe
JP		 1483struct mlxsw_sp_port_hw_stats {
1484 char str[ETH_GSTRING_LEN];
412791df 1485 u64 (*getter)(const char *payload);
56ade8fe
JP		 1486};
1487
7ed674bc 1488static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 1489 {
1490 .str = "a_frames_transmitted_ok",
1491 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1492 },
1493 {
1494 .str = "a_frames_received_ok",
1495 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1496 },
1497 {
1498 .str = "a_frame_check_sequence_errors",
1499 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1500 },
1501 {
1502 .str = "a_alignment_errors",
1503 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1504 },
1505 {
1506 .str = "a_octets_transmitted_ok",
1507 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1508 },
1509 {
1510 .str = "a_octets_received_ok",
1511 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1512 },
1513 {
1514 .str = "a_multicast_frames_xmitted_ok",
1515 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1516 },
1517 {
1518 .str = "a_broadcast_frames_xmitted_ok",
1519 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1520 },
1521 {
1522 .str = "a_multicast_frames_received_ok",
1523 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1524 },
1525 {
1526 .str = "a_broadcast_frames_received_ok",
1527 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1528 },
1529 {
1530 .str = "a_in_range_length_errors",
1531 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1532 },
1533 {
1534 .str = "a_out_of_range_length_field",
1535 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1536 },
1537 {
1538 .str = "a_frame_too_long_errors",
1539 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1540 },
1541 {
1542 .str = "a_symbol_error_during_carrier",
1543 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1544 },
1545 {
1546 .str = "a_mac_control_frames_transmitted",
1547 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1548 },
1549 {
1550 .str = "a_mac_control_frames_received",
1551 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1552 },
1553 {
1554 .str = "a_unsupported_opcodes_received",
1555 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1556 },
1557 {
1558 .str = "a_pause_mac_ctrl_frames_received",
1559 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1560 },
1561 {
1562 .str = "a_pause_mac_ctrl_frames_xmitted",
1563 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1564 },
1565};
1566
1567#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1568
7ed674bc
IS		 1569static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1570 {
1571 .str = "rx_octets_prio",
1572 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1573 },
1574 {
1575 .str = "rx_frames_prio",
1576 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1577 },
1578 {
1579 .str = "tx_octets_prio",
1580 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1581 },
1582 {
1583 .str = "tx_frames_prio",
1584 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1585 },
1586 {
1587 .str = "rx_pause_prio",
1588 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1589 },
1590 {
1591 .str = "rx_pause_duration_prio",
1592 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1593 },
1594 {
1595 .str = "tx_pause_prio",
1596 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1597 },
1598 {
1599 .str = "tx_pause_duration_prio",
1600 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1601 },
1602};
1603
1604#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1605
412791df 1606static u64 mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get(const char *ppcnt_pl)
df4750e8
IS		 1607{
1608 u64 transmit_queue = mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1609
1610 return MLXSW_SP_CELLS_TO_BYTES(transmit_queue);
1611}
1612
1613static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1614 {
1615 .str = "tc_transmit_queue_tc",
1616 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get,
1617 },
1618 {
1619 .str = "tc_no_buffer_discard_uc_tc",
1620 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1621 },
1622};
1623
1624#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1625
7ed674bc 1626#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 1627 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1628 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 1629 IEEE_8021QAZ_MAX_TCS)
1630
1631static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1632{
1633 int i;
1634
1635 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1636 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1637 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1638 *p += ETH_GSTRING_LEN;
1639 }
1640}
1641
df4750e8
IS		 1642static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1643{
1644 int i;
1645
1646 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1647 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1648 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1649 *p += ETH_GSTRING_LEN;
1650 }
1651}
1652
56ade8fe
JP		 1653static void mlxsw_sp_port_get_strings(struct net_device *dev,
1654 u32 stringset, u8 *data)
1655{
1656 u8 *p = data;
1657 int i;
1658
1659 switch (stringset) {
1660 case ETH_SS_STATS:
1661 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1662 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1663 ETH_GSTRING_LEN);
1664 p += ETH_GSTRING_LEN;
1665 }
7ed674bc
IS		 1666
1667 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1668 mlxsw_sp_port_get_prio_strings(&p, i);
1669
df4750e8
IS		 1670 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1671 mlxsw_sp_port_get_tc_strings(&p, i);
1672
56ade8fe
JP		 1673 break;
1674 }
1675}
1676
3a66ee38
IS		 1677static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1678 enum ethtool_phys_id_state state)
1679{
1680 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1682 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1683 bool active;
1684
1685 switch (state) {
1686 case ETHTOOL_ID_ACTIVE:
1687 active = true;
1688 break;
1689 case ETHTOOL_ID_INACTIVE:
1690 active = false;
1691 break;
1692 default:
1693 return -EOPNOTSUPP;
1694 }
1695
1696 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1697 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1698}
1699
7ed674bc
IS		 1700static int
1701mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1702 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1703{
1704 switch (grp) {
1705 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1706 *p_hw_stats = mlxsw_sp_port_hw_stats;
1707 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1708 break;
1709 case MLXSW_REG_PPCNT_PRIO_CNT:
1710 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1711 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1712 break;
df4750e8
IS		 1713 case MLXSW_REG_PPCNT_TC_CNT:
1714 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1715 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1716 break;
7ed674bc
IS		 1717 default:
1718 WARN_ON(1);
e915ac68 1719 return -EOPNOTSUPP;
7ed674bc
IS		 1720 }
1721 return 0;
1722}
1723
1724static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1725 enum mlxsw_reg_ppcnt_grp grp, int prio,
1726 u64 *data, int data_index)
56ade8fe 1727{
7ed674bc 1728 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 1729 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 1730 int i, len;
56ade8fe
JP		 1731 int err;
1732
7ed674bc
IS		 1733 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1734 if (err)
1735 return;
fc1bbb0f 1736 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
7ed674bc 1737 for (i = 0; i < len; i++)
faac0ff0 1738 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
7ed674bc
IS		 1739}
1740
1741static void mlxsw_sp_port_get_stats(struct net_device *dev,
1742 struct ethtool_stats *stats, u64 *data)
1743{
1744 int i, data_index = 0;
1745
1746 /* IEEE 802.3 Counters */
1747 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1748 data, data_index);
1749 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1750
1751 /* Per-Priority Counters */
1752 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1753 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1754 data, data_index);
1755 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1756 }
df4750e8
IS		 1757
1758 /* Per-TC Counters */
1759 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1760 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1761 data, data_index);
1762 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1763 }
56ade8fe
JP		 1764}
1765
1766static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1767{
1768 switch (sset) {
1769 case ETH_SS_STATS:
7ed674bc 1770 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 1771 default:
1772 return -EOPNOTSUPP;
1773 }
1774}
1775
1776struct mlxsw_sp_port_link_mode {
b9d66a36 1777 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 1778 u32 mask;
56ade8fe
JP		 1779 u32 speed;
1780};
1781
1782static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1783 {
1784 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 1785 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1786 .speed = SPEED_100,
56ade8fe
JP		 1787 },
1788 {
1789 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1790 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 1791 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1792 .speed = SPEED_1000,
56ade8fe
JP		 1793 },
1794 {
1795 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 1796 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1797 .speed = SPEED_10000,
56ade8fe
JP		 1798 },
1799 {
1800 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1801 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 1802 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1803 .speed = SPEED_10000,
56ade8fe
JP		 1804 },
1805 {
1806 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1807 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1808 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1809 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 1810 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1811 .speed = SPEED_10000,
56ade8fe
JP		 1812 },
1813 {
1814 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 1815 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
1816 .speed = SPEED_20000,
56ade8fe
JP		 1817 },
1818 {
1819 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 1820 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1821 .speed = SPEED_40000,
56ade8fe
JP		 1822 },
1823 {
1824 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 1825 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1826 .speed = SPEED_40000,
56ade8fe
JP		 1827 },
1828 {
1829 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 1830 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1831 .speed = SPEED_40000,
56ade8fe
JP		 1832 },
1833 {
1834 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 1835 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1836 .speed = SPEED_40000,
1837 },
1838 {
1839 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1840 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1841 .speed = SPEED_25000,
1842 },
1843 {
1844 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1845 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1846 .speed = SPEED_25000,
1847 },
1848 {
1849 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1850 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1851 .speed = SPEED_25000,
56ade8fe
JP		 1852 },
1853 {
b9d66a36
IS		 1854 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1855 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1856 .speed = SPEED_25000,
56ade8fe
JP		 1857 },
1858 {
b9d66a36
IS		 1859 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1860 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1861 .speed = SPEED_50000,
1862 },
1863 {
1864 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1865 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1866 .speed = SPEED_50000,
1867 },
1868 {
1869 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1870 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1871 .speed = SPEED_50000,
56ade8fe
JP		 1872 },
1873 {
1874 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 1875 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
1876 .speed = SPEED_56000,
56ade8fe
JP		 1877 },
1878 {
b9d66a36
IS		 1879 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1880 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
1881 .speed = SPEED_56000,
1882 },
1883 {
1884 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1885 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
1886 .speed = SPEED_56000,
1887 },
1888 {
1889 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1890 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
1891 .speed = SPEED_56000,
1892 },
1893 {
1894 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
1895 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1896 .speed = SPEED_100000,
1897 },
1898 {
1899 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
1900 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1901 .speed = SPEED_100000,
1902 },
1903 {
1904 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
1905 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1906 .speed = SPEED_100000,
1907 },
1908 {
1909 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1910 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1911 .speed = SPEED_100000,
56ade8fe
JP		 1912 },
1913};
1914
1915#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1916
b9d66a36
IS		 1917static void
1918mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
1919 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1920{
1921 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1922 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1923 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1924 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1925 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1926 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 1927 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 1928
1929 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1930 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1931 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1932 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1933 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 1934 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 1935}
1936
b9d66a36 1937static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 1938{
56ade8fe
JP		 1939 int i;
1940
1941 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1942 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 1943 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1944 mode);
56ade8fe 1945 }
56ade8fe
JP		 1946}
1947
1948static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 1949 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1950{
1951 u32 speed = SPEED_UNKNOWN;
1952 u8 duplex = DUPLEX_UNKNOWN;
1953 int i;
1954
1955 if (!carrier_ok)
1956 goto out;
1957
1958 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1959 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1960 speed = mlxsw_sp_port_link_mode[i].speed;
1961 duplex = DUPLEX_FULL;
1962 break;
1963 }
1964 }
1965out:
b9d66a36
IS		 1966 cmd->base.speed = speed;
1967 cmd->base.duplex = duplex;
56ade8fe
JP		 1968}
1969
1970static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1971{
1972 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1973 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1974 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1975 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1976 return PORT_FIBRE;
1977
1978 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1979 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1980 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1981 return PORT_DA;
1982
1983 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1984 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1985 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1986 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1987 return PORT_NONE;
1988
1989 return PORT_OTHER;
1990}
1991
b9d66a36
IS		 1992static u32
1993mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1994{
1995 u32 ptys_proto = 0;
1996 int i;
1997
1998 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 1999 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2000 cmd->link_modes.advertising))
56ade8fe
JP		 2001 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2002 }
2003 return ptys_proto;
2004}
2005
2006static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2007{
2008 u32 ptys_proto = 0;
2009 int i;
2010
2011 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2012 if (speed == mlxsw_sp_port_link_mode[i].speed)
2013 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2014 }
2015 return ptys_proto;
2016}
2017
18f1e70c
IS		 2018static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2019{
2020 u32 ptys_proto = 0;
2021 int i;
2022
2023 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2024 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2025 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2026 }
2027 return ptys_proto;
2028}
2029
b9d66a36
IS		 2030static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2031 struct ethtool_link_ksettings *cmd)
2032{
2033 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2034 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2035 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2036
2037 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2038 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2039}
2040
2041static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2042 struct ethtool_link_ksettings *cmd)
56ade8fe 2043{
b9d66a36
IS		 2044 if (!autoneg)
2045 return;
2046
2047 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2048 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2049}
2050
2051static void
2052mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2053 struct ethtool_link_ksettings *cmd)
2054{
2055 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2056 return;
2057
2058 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2059 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2060}
2061
2062static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2063 struct ethtool_link_ksettings *cmd)
2064{
2065 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 2066 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2067 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2068 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2069 u8 autoneg_status;
0c83f88c 2070 bool autoneg;
56ade8fe
JP		 2071 int err;
2072
b9d66a36 2073 autoneg = mlxsw_sp_port->link.autoneg;
401c8b4e 2074 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
b9d66a36
IS		 2075 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2076 if (err)
2077 return err;
401c8b4e
ER		 2078 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2079 &eth_proto_oper);
b9d66a36
IS		 2080
2081 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2082
b9d66a36
IS		 2083 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2084
2085 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2086 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2087 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2088
2089 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2090 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2091 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2092 cmd);
2093
2094 return 0;
2095}
2096
2097static int
2098mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2099 const struct ethtool_link_ksettings *cmd)
2100{
2101 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2102 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2103 char ptys_pl[MLXSW_REG_PTYS_LEN];
2104 u32 eth_proto_cap, eth_proto_new;
2105 bool autoneg;
2106 int err;
56ade8fe 2107
401c8b4e 2108 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
56ade8fe 2109 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2110 if (err)
56ade8fe 2111 return err;
401c8b4e 2112 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
b9d66a36
IS		 2113
2114 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2115 eth_proto_new = autoneg ?
2116 mlxsw_sp_to_ptys_advert_link(cmd) :
2117 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2118
2119 eth_proto_new = eth_proto_new & eth_proto_cap;
2120 if (!eth_proto_new) {
b9d66a36 2121 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2122 return -EINVAL;
2123 }
56ade8fe 2124
401c8b4e
ER		 2125 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2126 eth_proto_new);
56ade8fe 2127 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2128 if (err)
56ade8fe 2129 return err;
56ade8fe 2130
6277d46b 2131 if (!netif_running(dev))
56ade8fe
JP		 2132 return 0;
2133
0c83f88c
IS		 2134 mlxsw_sp_port->link.autoneg = autoneg;
2135
b9d66a36
IS		 2136 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2137 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2138
2139 return 0;
2140}
2141
2142static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2143 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2144 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2145 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2146 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2147 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2148 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2149 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2150 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2151 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2152 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
56ade8fe
JP		 2153};
2154
18f1e70c
IS		 2155static int
2156mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2157{
2158 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2159 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2160 char ptys_pl[MLXSW_REG_PTYS_LEN];
2161 u32 eth_proto_admin;
2162
2163 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
401c8b4e
ER		 2164 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2165 eth_proto_admin);
18f1e70c
IS		 2166 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2167}
2168
8e8dfe9f
IS		 2169int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2170 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2171 bool dwrr, u8 dwrr_weight)
90183b98
IS		 2172{
2173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2174 char qeec_pl[MLXSW_REG_QEEC_LEN];
2175
2176 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2177 next_index);
2178 mlxsw_reg_qeec_de_set(qeec_pl, true);
2179 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2180 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2181 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2182}
2183
cc7cf517
IS		 2184int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2185 enum mlxsw_reg_qeec_hr hr, u8 index,
2186 u8 next_index, u32 maxrate)
90183b98
IS		 2187{
2188 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2189 char qeec_pl[MLXSW_REG_QEEC_LEN];
2190
2191 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2192 next_index);
2193 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2194 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2195 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2196}
2197
8e8dfe9f
IS		 2198int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2199 u8 switch_prio, u8 tclass)
90183b98
IS		 2200{
2201 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2202 char qtct_pl[MLXSW_REG_QTCT_LEN];
2203
2204 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2205 tclass);
2206 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2207}
2208
2209static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2210{
2211 int err, i;
2212
2213 /* Setup the elements hierarcy, so that each TC is linked to
2214 * one subgroup, which are all member in the same group.
2215 */
2216 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2217 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2218 0);
2219 if (err)
2220 return err;
2221 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2222 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2223 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2224 0, false, 0);
2225 if (err)
2226 return err;
2227 }
2228 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2229 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2230 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2231 false, 0);
2232 if (err)
2233 return err;
2234 }
2235
2236 /* Make sure the max shaper is disabled in all hierarcies that
2237 * support it.
2238 */
2239 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2240 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2241 MLXSW_REG_QEEC_MAS_DIS);
2242 if (err)
2243 return err;
2244 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2245 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2246 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2247 i, 0,
2248 MLXSW_REG_QEEC_MAS_DIS);
2249 if (err)
2250 return err;
2251 }
2252 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2253 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2254 MLXSW_REG_QEEC_HIERARCY_TC,
2255 i, i,
2256 MLXSW_REG_QEEC_MAS_DIS);
2257 if (err)
2258 return err;
2259 }
2260
2261 /* Map all priorities to traffic class 0. */
2262 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2263 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2264 if (err)
2265 return err;
2266 }
2267
2268 return 0;
2269}
2270
05978481
IS		 2271static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2272{
2273 mlxsw_sp_port->pvid = 1;
2274
2275 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2276}
2277
2278static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2279{
2280 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2281}
2282
67963a33
JP		 2283static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2284 bool split, u8 module, u8 width, u8 lane)
56ade8fe
JP		 2285{
2286 struct mlxsw_sp_port *mlxsw_sp_port;
2287 struct net_device *dev;
bd40e9d6 2288 size_t bytes;
56ade8fe
JP		 2289 int err;
2290
2291 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2292 if (!dev)
2293 return -ENOMEM;
f20a91f1 2294 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 2295 mlxsw_sp_port = netdev_priv(dev);
2296 mlxsw_sp_port->dev = dev;
2297 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2298 mlxsw_sp_port->local_port = local_port;
18f1e70c 2299 mlxsw_sp_port->split = split;
d664b41e
IS		 2300 mlxsw_sp_port->mapping.module = module;
2301 mlxsw_sp_port->mapping.width = width;
2302 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 2303 mlxsw_sp_port->link.autoneg = 1;
bd40e9d6
IS		 2304 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2305 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2306 if (!mlxsw_sp_port->active_vlans) {
2307 err = -ENOMEM;
2308 goto err_port_active_vlans_alloc;
2309 }
fc1273af
ER		 2310 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2311 if (!mlxsw_sp_port->untagged_vlans) {
2312 err = -ENOMEM;
2313 goto err_port_untagged_vlans_alloc;
2314 }
7f71eb46 2315 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
763b4b70 2316 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 2317
2318 mlxsw_sp_port->pcpu_stats =
2319 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2320 if (!mlxsw_sp_port->pcpu_stats) {
2321 err = -ENOMEM;
2322 goto err_alloc_stats;
2323 }
2324
98d0f7b9
YG		 2325 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2326 GFP_KERNEL);
2327 if (!mlxsw_sp_port->sample) {
2328 err = -ENOMEM;
2329 goto err_alloc_sample;
2330 }
2331
fc1bbb0f
NF		 2332 mlxsw_sp_port->hw_stats.cache =
2333 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2334
2335 if (!mlxsw_sp_port->hw_stats.cache) {
2336 err = -ENOMEM;
2337 goto err_alloc_hw_stats;
2338 }
2339 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2340 &update_stats_cache);
2341
56ade8fe
JP		 2342 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2343 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2344
3247ff2b
IS		 2345 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2346 if (err) {
2347 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2348 mlxsw_sp_port->local_port);
2349 goto err_port_swid_set;
2350 }
2351
56ade8fe
JP		 2352 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2353 if (err) {
2354 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2355 mlxsw_sp_port->local_port);
2356 goto err_dev_addr_init;
2357 }
2358
2359 netif_carrier_off(dev);
2360
2361 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 2362 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2363 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 2364
d894be57
JW		 2365 dev->min_mtu = 0;
2366 dev->max_mtu = ETH_MAX_MTU;
2367
56ade8fe
JP		 2368 /* Each packet needs to have a Tx header (metadata) on top all other
2369 * headers.
2370 */
feb7d387 2371 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 2372
56ade8fe
JP		 2373 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2374 if (err) {
2375 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2376 mlxsw_sp_port->local_port);
2377 goto err_port_system_port_mapping_set;
2378 }
2379
18f1e70c
IS		 2380 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2381 if (err) {
2382 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2383 mlxsw_sp_port->local_port);
2384 goto err_port_speed_by_width_set;
2385 }
2386
56ade8fe
JP		 2387 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2388 if (err) {
2389 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2390 mlxsw_sp_port->local_port);
2391 goto err_port_mtu_set;
2392 }
2393
2394 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2395 if (err)
2396 goto err_port_admin_status_set;
2397
2398 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2399 if (err) {
2400 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2401 mlxsw_sp_port->local_port);
2402 goto err_port_buffers_init;
2403 }
2404
90183b98
IS		 2405 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2406 if (err) {
2407 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2408 mlxsw_sp_port->local_port);
2409 goto err_port_ets_init;
2410 }
2411
f00817df
IS		 2412 /* ETS and buffers must be initialized before DCB. */
2413 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2414 if (err) {
2415 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2416 mlxsw_sp_port->local_port);
2417 goto err_port_dcb_init;
2418 }
2419
05978481
IS		 2420 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2421 if (err) {
2422 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2423 mlxsw_sp_port->local_port);
2424 goto err_port_pvid_vport_create;
2425 }
2426
56ade8fe 2427 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 2428 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 2429 err = register_netdev(dev);
2430 if (err) {
2431 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2432 mlxsw_sp_port->local_port);
2433 goto err_register_netdev;
2434 }
2435
d808c7e4
ER		 2436 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2437 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2438 module);
fc1bbb0f 2439 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
56ade8fe
JP		 2440 return 0;
2441
56ade8fe 2442err_register_netdev:
2f25844c 2443 mlxsw_sp->ports[local_port] = NULL;
0583272d 2444 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
05978481
IS		 2445 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2446err_port_pvid_vport_create:
4de34eb5 2447 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 2448err_port_dcb_init:
90183b98 2449err_port_ets_init:
56ade8fe
JP		 2450err_port_buffers_init:
2451err_port_admin_status_set:
2452err_port_mtu_set:
18f1e70c 2453err_port_speed_by_width_set:
56ade8fe 2454err_port_system_port_mapping_set:
56ade8fe 2455err_dev_addr_init:
3247ff2b
IS		 2456 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2457err_port_swid_set:
fc1bbb0f
NF		 2458 kfree(mlxsw_sp_port->hw_stats.cache);
2459err_alloc_hw_stats:
98d0f7b9
YG		 2460 kfree(mlxsw_sp_port->sample);
2461err_alloc_sample:
56ade8fe
JP		 2462 free_percpu(mlxsw_sp_port->pcpu_stats);
2463err_alloc_stats:
fc1273af
ER		 2464 kfree(mlxsw_sp_port->untagged_vlans);
2465err_port_untagged_vlans_alloc:
bd40e9d6
IS		 2466 kfree(mlxsw_sp_port->active_vlans);
2467err_port_active_vlans_alloc:
56ade8fe
JP		 2468 free_netdev(dev);
2469 return err;
2470}
2471
67963a33
JP		 2472static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2473 bool split, u8 module, u8 width, u8 lane)
2474{
2475 int err;
2476
2477 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2478 if (err) {
2479 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2480 local_port);
2481 return err;
2482 }
9a60c907 2483 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
67963a33
JP		 2484 module, width, lane);
2485 if (err)
2486 goto err_port_create;
2487 return 0;
2488
2489err_port_create:
2490 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2491 return err;
2492}
2493
2494static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
56ade8fe
JP		 2495{
2496 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2497
fc1bbb0f 2498 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
67963a33 2499 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
56ade8fe 2500 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 2501 mlxsw_sp->ports[local_port] = NULL;
0583272d 2502 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
05978481 2503 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
f00817df 2504 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8
IS		 2505 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2506 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
fc1bbb0f 2507 kfree(mlxsw_sp_port->hw_stats.cache);
98d0f7b9 2508 kfree(mlxsw_sp_port->sample);
136f1445 2509 free_percpu(mlxsw_sp_port->pcpu_stats);
fc1273af 2510 kfree(mlxsw_sp_port->untagged_vlans);
bd40e9d6 2511 kfree(mlxsw_sp_port->active_vlans);
32d863fb 2512 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
56ade8fe
JP		 2513 free_netdev(mlxsw_sp_port->dev);
2514}
2515
67963a33
JP		 2516static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2517{
2518 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2519 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2520}
2521
f83e2102
JP		 2522static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2523{
2524 return mlxsw_sp->ports[local_port] != NULL;
2525}
2526
56ade8fe
JP		 2527static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2528{
2529 int i;
2530
2531 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
f83e2102
JP		 2532 if (mlxsw_sp_port_created(mlxsw_sp, i))
2533 mlxsw_sp_port_remove(mlxsw_sp, i);
56ade8fe
JP		 2534 kfree(mlxsw_sp->ports);
2535}
2536
2537static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2538{
d664b41e 2539 u8 module, width, lane;
56ade8fe
JP		 2540 size_t alloc_size;
2541 int i;
2542 int err;
2543
2544 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
2545 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2546 if (!mlxsw_sp->ports)
2547 return -ENOMEM;
2548
2549 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
558c2d5e 2550 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 2551 &width, &lane);
558c2d5e
IS		 2552 if (err)
2553 goto err_port_module_info_get;
2554 if (!width)
2555 continue;
2556 mlxsw_sp->port_to_module[i] = module;
67963a33
JP		 2557 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2558 module, width, lane);
56ade8fe
JP		 2559 if (err)
2560 goto err_port_create;
2561 }
2562 return 0;
2563
2564err_port_create:
558c2d5e 2565err_port_module_info_get:
56ade8fe 2566 for (i--; i >= 1; i--)
f83e2102
JP		 2567 if (mlxsw_sp_port_created(mlxsw_sp, i))
2568 mlxsw_sp_port_remove(mlxsw_sp, i);
56ade8fe
JP		 2569 kfree(mlxsw_sp->ports);
2570 return err;
2571}
2572
18f1e70c
IS		 2573static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2574{
2575 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2576
2577 return local_port - offset;
2578}
2579
be94535f
IS		 2580static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2581 u8 module, unsigned int count)
2582{
2583 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2584 int err, i;
2585
2586 for (i = 0; i < count; i++) {
2587 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2588 width, i * width);
2589 if (err)
2590 goto err_port_module_map;
2591 }
2592
2593 for (i = 0; i < count; i++) {
2594 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2595 if (err)
2596 goto err_port_swid_set;
2597 }
2598
2599 for (i = 0; i < count; i++) {
2600 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 2601 module, width, i * width);
be94535f
IS		 2602 if (err)
2603 goto err_port_create;
2604 }
2605
2606 return 0;
2607
2608err_port_create:
2609 for (i--; i >= 0; i--)
f83e2102
JP		 2610 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2611 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
be94535f
IS		 2612 i = count;
2613err_port_swid_set:
2614 for (i--; i >= 0; i--)
2615 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2616 MLXSW_PORT_SWID_DISABLED_PORT);
2617 i = count;
2618err_port_module_map:
2619 for (i--; i >= 0; i--)
2620 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2621 return err;
2622}
2623
2624static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2625 u8 base_port, unsigned int count)
2626{
2627 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2628 int i;
2629
2630 /* Split by four means we need to re-create two ports, otherwise
2631 * only one.
2632 */
2633 count = count / 2;
2634
2635 for (i = 0; i < count; i++) {
2636 local_port = base_port + i * 2;
2637 module = mlxsw_sp->port_to_module[local_port];
2638
2639 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2640 0);
2641 }
2642
2643 for (i = 0; i < count; i++)
2644 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2645
2646 for (i = 0; i < count; i++) {
2647 local_port = base_port + i * 2;
2648 module = mlxsw_sp->port_to_module[local_port];
2649
2650 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 2651 width, 0);
be94535f
IS		 2652 }
2653}
2654
b2f10571
JP		 2655static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2656 unsigned int count)
18f1e70c 2657{
b2f10571 2658 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2659 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 2660 u8 module, cur_width, base_port;
2661 int i;
2662 int err;
2663
2664 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2665 if (!mlxsw_sp_port) {
2666 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2667 local_port);
2668 return -EINVAL;
2669 }
2670
d664b41e
IS		 2671 module = mlxsw_sp_port->mapping.module;
2672 cur_width = mlxsw_sp_port->mapping.width;
2673
18f1e70c
IS		 2674 if (count != 2 && count != 4) {
2675 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2676 return -EINVAL;
2677 }
2678
18f1e70c
IS		 2679 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2680 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2681 return -EINVAL;
2682 }
2683
2684 /* Make sure we have enough slave (even) ports for the split. */
2685 if (count == 2) {
2686 base_port = local_port;
2687 if (mlxsw_sp->ports[base_port + 1]) {
2688 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2689 return -EINVAL;
2690 }
2691 } else {
2692 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2693 if (mlxsw_sp->ports[base_port + 1] ||
2694 mlxsw_sp->ports[base_port + 3]) {
2695 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2696 return -EINVAL;
2697 }
2698 }
2699
2700 for (i = 0; i < count; i++)
f83e2102
JP		 2701 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2702 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 2703
be94535f
IS		 2704 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2705 if (err) {
2706 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2707 goto err_port_split_create;
18f1e70c
IS		 2708 }
2709
2710 return 0;
2711
be94535f
IS		 2712err_port_split_create:
2713 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2714 return err;
2715}
2716
b2f10571 2717static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 2718{
b2f10571 2719 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2720 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 2721 u8 cur_width, base_port;
18f1e70c
IS		 2722 unsigned int count;
2723 int i;
18f1e70c
IS		 2724
2725 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2726 if (!mlxsw_sp_port) {
2727 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2728 local_port);
2729 return -EINVAL;
2730 }
2731
2732 if (!mlxsw_sp_port->split) {
2733 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2734 return -EINVAL;
2735 }
2736
d664b41e 2737 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 2738 count = cur_width == 1 ? 4 : 2;
2739
2740 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2741
2742 /* Determine which ports to remove. */
2743 if (count == 2 && local_port >= base_port + 2)
2744 base_port = base_port + 2;
2745
2746 for (i = 0; i < count; i++)
f83e2102
JP		 2747 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2748 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 2749
be94535f 2750 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2751
2752 return 0;
2753}
2754
56ade8fe
JP		 2755static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2756 char *pude_pl, void *priv)
2757{
2758 struct mlxsw_sp *mlxsw_sp = priv;
2759 struct mlxsw_sp_port *mlxsw_sp_port;
2760 enum mlxsw_reg_pude_oper_status status;
2761 u8 local_port;
2762
2763 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2764 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 2765 if (!mlxsw_sp_port)
56ade8fe 2766 return;
56ade8fe
JP		 2767
2768 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2769 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2770 netdev_info(mlxsw_sp_port->dev, "link up\n");
2771 netif_carrier_on(mlxsw_sp_port->dev);
2772 } else {
2773 netdev_info(mlxsw_sp_port->dev, "link down\n");
2774 netif_carrier_off(mlxsw_sp_port->dev);
2775 }
2776}
2777
14eeda99
NF		 2778static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2779 u8 local_port, void *priv)
56ade8fe
JP		 2780{
2781 struct mlxsw_sp *mlxsw_sp = priv;
2782 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2783 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2784
2785 if (unlikely(!mlxsw_sp_port)) {
2786 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2787 local_port);
2788 return;
2789 }
2790
2791 skb->dev = mlxsw_sp_port->dev;
2792
2793 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2794 u64_stats_update_begin(&pcpu_stats->syncp);
2795 pcpu_stats->rx_packets++;
2796 pcpu_stats->rx_bytes += skb->len;
2797 u64_stats_update_end(&pcpu_stats->syncp);
2798
2799 skb->protocol = eth_type_trans(skb, skb->dev);
2800 netif_receive_skb(skb);
2801}
2802
1c6c6d22
IS		 2803static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2804 void *priv)
2805{
2806 skb->offload_fwd_mark = 1;
14eeda99 2807 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
1c6c6d22
IS		 2808}
2809
98d0f7b9
YG		 2810static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
2811 void *priv)
2812{
2813 struct mlxsw_sp *mlxsw_sp = priv;
2814 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2815 struct psample_group *psample_group;
2816 u32 size;
2817
2818 if (unlikely(!mlxsw_sp_port)) {
2819 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
2820 local_port);
2821 goto out;
2822 }
2823 if (unlikely(!mlxsw_sp_port->sample)) {
2824 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
2825 local_port);
2826 goto out;
2827 }
2828
2829 size = mlxsw_sp_port->sample->truncate ?
2830 mlxsw_sp_port->sample->trunc_size : skb->len;
2831
2832 rcu_read_lock();
2833 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
2834 if (!psample_group)
2835 goto out_unlock;
2836 psample_sample_packet(psample_group, skb, size,
2837 mlxsw_sp_port->dev->ifindex, 0,
2838 mlxsw_sp_port->sample->rate);
2839out_unlock:
2840 rcu_read_unlock();
2841out:
2842 consume_skb(skb);
2843}
2844
117b0dad 2845#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
0fb78a4e 2846 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
117b0dad 2847 _is_ctrl, SP_##_trap_group, DISCARD)
14eeda99 2848
117b0dad 2849#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
14eeda99 2850 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
117b0dad
NF		 2851 _is_ctrl, SP_##_trap_group, DISCARD)
2852
2853#define MLXSW_SP_EVENTL(_func, _trap_id) \
2854 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
93393b33 2855
4544913e
NF		 2856static const struct mlxsw_listener mlxsw_sp_listener[] = {
2857 /* Events */
117b0dad 2858 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
ee4a60d8 2859 /* L2 traps */
117b0dad
NF		 2860 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
2861 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
2862 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
2863 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
2864 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
2865 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
2866 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
2867 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
2868 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
2869 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
2870 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
93393b33 2871 /* L3 traps */
117b0dad
NF		 2872 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2873 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2874 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2875 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
2876 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
2877 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
2878 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
2879 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
98d0f7b9
YG		 2880 /* PKT Sample trap */
2881 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
2882 false, SP_IP2ME, DISCARD)
56ade8fe
JP		 2883};
2884
9148e7cf
NF		 2885static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
2886{
2887 char qpcr_pl[MLXSW_REG_QPCR_LEN];
2888 enum mlxsw_reg_qpcr_ir_units ir_units;
2889 int max_cpu_policers;
2890 bool is_bytes;
2891 u8 burst_size;
2892 u32 rate;
2893 int i, err;
2894
2895 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
2896 return -EIO;
2897
2898 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2899
2900 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
2901 for (i = 0; i < max_cpu_policers; i++) {
2902 is_bytes = false;
2903 switch (i) {
2904 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
2905 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
2906 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
2907 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
2908 rate = 128;
2909 burst_size = 7;
2910 break;
2911 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
2912 rate = 16 * 1024;
2913 burst_size = 10;
2914 break;
2915 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
2916 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
2917 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
2918 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
2919 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2920 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
2921 rate = 1024;
2922 burst_size = 7;
2923 break;
2924 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
2925 is_bytes = true;
2926 rate = 4 * 1024;
2927 burst_size = 4;
2928 break;
2929 default:
2930 continue;
2931 }
2932
2933 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
2934 burst_size);
2935 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
2936 if (err)
2937 return err;
2938 }
2939
2940 return 0;
2941}
2942
579c82e4 2943static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
56ade8fe
JP		 2944{
2945 char htgt_pl[MLXSW_REG_HTGT_LEN];
117b0dad 2946 enum mlxsw_reg_htgt_trap_group i;
9148e7cf 2947 int max_cpu_policers;
579c82e4
NF		 2948 int max_trap_groups;
2949 u8 priority, tc;
9148e7cf 2950 u16 policer_id;
117b0dad 2951 int err;
579c82e4
NF		 2952
2953 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2954 return -EIO;
2955
2956 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
9148e7cf 2957 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
579c82e4
NF		 2958
2959 for (i = 0; i < max_trap_groups; i++) {
9148e7cf 2960 policer_id = i;
579c82e4 2961 switch (i) {
117b0dad
NF		 2962 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
2963 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
2964 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
2965 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
2966 priority = 5;
2967 tc = 5;
2968 break;
2969 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
2970 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
2971 priority = 4;
2972 tc = 4;
2973 break;
2974 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
2975 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
2976 priority = 3;
2977 tc = 3;
2978 break;
2979 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
2980 priority = 2;
2981 tc = 2;
2982 break;
2983 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
2984 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2985 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
2986 priority = 1;
2987 tc = 1;
2988 break;
2989 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
579c82e4
NF		 2990 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2991 tc = MLXSW_REG_HTGT_DEFAULT_TC;
9148e7cf 2992 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
579c82e4
NF		 2993 break;
2994 default:
2995 continue;
2996 }
117b0dad 2997
9148e7cf
NF		 2998 if (max_cpu_policers <= policer_id &&
2999 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3000 return -EIO;
3001
3002 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
579c82e4
NF		 3003 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3004 if (err)
3005 return err;
3006 }
3007
3008 return 0;
3009}
3010
3011static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3012{
56ade8fe
JP		 3013 int i;
3014 int err;
3015
9148e7cf
NF		 3016 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3017 if (err)
3018 return err;
3019
579c82e4 3020 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
56ade8fe
JP		 3021 if (err)
3022 return err;
3023
4544913e 3024 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3025 err = mlxsw_core_trap_register(mlxsw_sp->core,
4544913e 3026 &mlxsw_sp_listener[i],
14eeda99 3027 mlxsw_sp);
56ade8fe 3028 if (err)
4544913e 3029 goto err_listener_register;
56ade8fe 3030
56ade8fe
JP		 3031 }
3032 return 0;
3033
4544913e 3034err_listener_register:
56ade8fe 3035 for (i--; i >= 0; i--) {
14eeda99 3036 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3037 &mlxsw_sp_listener[i],
14eeda99 3038 mlxsw_sp);
56ade8fe
JP		 3039 }
3040 return err;
3041}
3042
3043static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3044{
56ade8fe
JP		 3045 int i;
3046
4544913e 3047 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3048 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3049 &mlxsw_sp_listener[i],
14eeda99 3050 mlxsw_sp);
56ade8fe
JP		 3051 }
3052}
3053
3054static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3055 enum mlxsw_reg_sfgc_type type,
3056 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3057{
3058 enum mlxsw_flood_table_type table_type;
3059 enum mlxsw_sp_flood_table flood_table;
3060 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3061
19ae6124 3062 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
56ade8fe 3063 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
19ae6124 3064 else
56ade8fe 3065 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
19ae6124
IS		 3066
3067 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
3068 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
3069 else
3070 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
56ade8fe
JP		 3071
3072 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3073 flood_table);
3074 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3075}
3076
3077static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3078{
3079 int type, err;
3080
56ade8fe
JP		 3081 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3082 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3083 continue;
3084
3085 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3086 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3087 if (err)
3088 return err;
56ade8fe
JP		 3089
3090 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3091 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3092 if (err)
3093 return err;
3094 }
3095
3096 return 0;
3097}
3098
0d65fc13
JP		 3099static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3100{
3101 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 3102 int err;
0d65fc13
JP		 3103
3104 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3105 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3106 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3107 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3108 MLXSW_REG_SLCR_LAG_HASH_SIP |
3109 MLXSW_REG_SLCR_LAG_HASH_DIP |
3110 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3111 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3112 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 3113 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3114 if (err)
3115 return err;
3116
c1a38311
JP		 3117 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3118 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 3119 return -EIO;
3120
c1a38311 3121 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 3122 sizeof(struct mlxsw_sp_upper),
3123 GFP_KERNEL);
3124 if (!mlxsw_sp->lags)
3125 return -ENOMEM;
3126
3127 return 0;
3128}
3129
3130static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3131{
3132 kfree(mlxsw_sp->lags);
0d65fc13
JP		 3133}
3134
9d87fcea
NF		 3135static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3136{
3137 char htgt_pl[MLXSW_REG_HTGT_LEN];
3138
579c82e4
NF		 3139 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3140 MLXSW_REG_HTGT_INVALID_POLICER,
3141 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3142 MLXSW_REG_HTGT_DEFAULT_TC);
9d87fcea
NF		 3143 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3144}
3145
b2f10571 3146static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 3147 const struct mlxsw_bus_info *mlxsw_bus_info)
3148{
b2f10571 3149 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 3150 int err;
3151
3152 mlxsw_sp->core = mlxsw_core;
3153 mlxsw_sp->bus_info = mlxsw_bus_info;
14d39461 3154 INIT_LIST_HEAD(&mlxsw_sp->fids);
3ba2ebf4 3155 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
3a49b4fd 3156 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
56ade8fe
JP		 3157
3158 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3159 if (err) {
3160 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3161 return err;
3162 }
3163
56ade8fe
JP		 3164 err = mlxsw_sp_traps_init(mlxsw_sp);
3165 if (err) {
4544913e
NF		 3166 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3167 return err;
56ade8fe
JP		 3168 }
3169
3170 err = mlxsw_sp_flood_init(mlxsw_sp);
3171 if (err) {
3172 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3173 goto err_flood_init;
3174 }
3175
3176 err = mlxsw_sp_buffers_init(mlxsw_sp);
3177 if (err) {
3178 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3179 goto err_buffers_init;
3180 }
3181
0d65fc13
JP		 3182 err = mlxsw_sp_lag_init(mlxsw_sp);
3183 if (err) {
3184 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3185 goto err_lag_init;
3186 }
3187
56ade8fe
JP		 3188 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3189 if (err) {
3190 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3191 goto err_switchdev_init;
3192 }
3193
464dce18
IS		 3194 err = mlxsw_sp_router_init(mlxsw_sp);
3195 if (err) {
3196 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3197 goto err_router_init;
3198 }
3199
763b4b70
YG		 3200 err = mlxsw_sp_span_init(mlxsw_sp);
3201 if (err) {
3202 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3203 goto err_span_init;
3204 }
3205
bbf2a475
IS		 3206 err = mlxsw_sp_ports_create(mlxsw_sp);
3207 if (err) {
3208 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3209 goto err_ports_create;
3210 }
3211
56ade8fe
JP		 3212 return 0;
3213
bbf2a475 3214err_ports_create:
763b4b70
YG		 3215 mlxsw_sp_span_fini(mlxsw_sp);
3216err_span_init:
464dce18
IS		 3217 mlxsw_sp_router_fini(mlxsw_sp);
3218err_router_init:
bbf2a475 3219 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 3220err_switchdev_init:
ce0bd2b0 3221 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 3222err_lag_init:
0f433fa0 3223 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 3224err_buffers_init:
3225err_flood_init:
3226 mlxsw_sp_traps_fini(mlxsw_sp);
56ade8fe
JP		 3227 return err;
3228}
3229
b2f10571 3230static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 3231{
b2f10571 3232 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 3233
bbf2a475 3234 mlxsw_sp_ports_remove(mlxsw_sp);
763b4b70 3235 mlxsw_sp_span_fini(mlxsw_sp);
464dce18 3236 mlxsw_sp_router_fini(mlxsw_sp);
56ade8fe 3237 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 3238 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 3239 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3240 mlxsw_sp_traps_fini(mlxsw_sp);
3ba2ebf4 3241 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
14d39461 3242 WARN_ON(!list_empty(&mlxsw_sp->fids));
56ade8fe
JP		 3243}
3244
3245static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3246 .used_max_vepa_channels = 1,
3247 .max_vepa_channels = 0,
56ade8fe 3248 .used_max_mid = 1,
53ae6283 3249 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 3250 .used_max_pgt = 1,
3251 .max_pgt = 0,
56ade8fe
JP		 3252 .used_flood_tables = 1,
3253 .used_flood_mode = 1,
3254 .flood_mode = 3,
3255 .max_fid_offset_flood_tables = 2,
3256 .fid_offset_flood_table_size = VLAN_N_VID - 1,
19ae6124
IS		 3257 .max_fid_flood_tables = 2,
3258 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
56ade8fe
JP		 3259 .used_max_ib_mc = 1,
3260 .max_ib_mc = 0,
3261 .used_max_pkey = 1,
3262 .max_pkey = 0,
403547d3
NF		 3263 .used_kvd_split_data = 1,
3264 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3265 .kvd_hash_single_parts = 2,
3266 .kvd_hash_double_parts = 1,
c6022427 3267 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 3268 .swid_config = {
3269 {
3270 .used_type = 1,
3271 .type = MLXSW_PORT_SWID_TYPE_ETH,
3272 }
3273 },
57d316ba 3274 .resource_query_enable = 1,
56ade8fe
JP		 3275};
3276
3277static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 3278 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 3279 .priv_size = sizeof(struct mlxsw_sp),
3280 .init = mlxsw_sp_init,
3281 .fini = mlxsw_sp_fini,
9d87fcea 3282 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
2d0ed39f
JP		 3283 .port_split = mlxsw_sp_port_split,
3284 .port_unsplit = mlxsw_sp_port_unsplit,
3285 .sb_pool_get = mlxsw_sp_sb_pool_get,
3286 .sb_pool_set = mlxsw_sp_sb_pool_set,
3287 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3288 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3289 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3290 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3291 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3292 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3293 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3294 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3295 .txhdr_construct = mlxsw_sp_txhdr_construct,
3296 .txhdr_len = MLXSW_TXHDR_LEN,
3297 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 3298};
3299
7ce856aa
JP		 3300static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3301{
3302 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3303}
3304
dd82364c
DA		 3305static int mlxsw_lower_dev_walk(struct net_device *lower_dev, void *data)
3306{
3307 struct mlxsw_sp_port **port = data;
3308 int ret = 0;
3309
3310 if (mlxsw_sp_port_dev_check(lower_dev)) {
3311 *port = netdev_priv(lower_dev);
3312 ret = 1;
3313 }
3314
3315 return ret;
3316}
3317
7ce856aa
JP		 3318static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3319{
dd82364c 3320 struct mlxsw_sp_port *port;
7ce856aa
JP		 3321
3322 if (mlxsw_sp_port_dev_check(dev))
3323 return netdev_priv(dev);
3324
dd82364c
DA		 3325 port = NULL;
3326 netdev_walk_all_lower_dev(dev, mlxsw_lower_dev_walk, &port);
3327
3328 return port;
7ce856aa
JP		 3329}
3330
3331static struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
3332{
3333 struct mlxsw_sp_port *mlxsw_sp_port;
3334
3335 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3336 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3337}
3338
3339static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3340{
dd82364c 3341 struct mlxsw_sp_port *port;
7ce856aa
JP		 3342
3343 if (mlxsw_sp_port_dev_check(dev))
3344 return netdev_priv(dev);
3345
dd82364c
DA		 3346 port = NULL;
3347 netdev_walk_all_lower_dev_rcu(dev, mlxsw_lower_dev_walk, &port);
3348
3349 return port;
7ce856aa
JP		 3350}
3351
3352struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3353{
3354 struct mlxsw_sp_port *mlxsw_sp_port;
3355
3356 rcu_read_lock();
3357 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3358 if (mlxsw_sp_port)
3359 dev_hold(mlxsw_sp_port->dev);
3360 rcu_read_unlock();
3361 return mlxsw_sp_port;
3362}
3363
3364void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3365{
3366 dev_put(mlxsw_sp_port->dev);
3367}
3368
99724c18
IS		 3369static bool mlxsw_sp_rif_should_config(struct mlxsw_sp_rif *r,
3370 unsigned long event)
3371{
3372 switch (event) {
3373 case NETDEV_UP:
3374 if (!r)
3375 return true;
3376 r->ref_count++;
3377 return false;
3378 case NETDEV_DOWN:
3379 if (r && --r->ref_count == 0)
3380 return true;
3381 /* It is possible we already removed the RIF ourselves
3382 * if it was assigned to a netdev that is now a bridge
3383 * or LAG slave.
3384 */
3385 return false;
3386 }
3387
3388 return false;
3389}
3390
3391static int mlxsw_sp_avail_rif_get(struct mlxsw_sp *mlxsw_sp)
3392{
3393 int i;
3394
c1a38311 3395 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
99724c18
IS		 3396 if (!mlxsw_sp->rifs[i])
3397 return i;
3398
8f8a62d4 3399 return MLXSW_SP_INVALID_RIF;
99724c18
IS		 3400}
3401
3402static void mlxsw_sp_vport_rif_sp_attr_get(struct mlxsw_sp_port *mlxsw_sp_vport,
3403 bool *p_lagged, u16 *p_system_port)
3404{
3405 u8 local_port = mlxsw_sp_vport->local_port;
3406
3407 *p_lagged = mlxsw_sp_vport->lagged;
3408 *p_system_port = *p_lagged ? mlxsw_sp_vport->lag_id : local_port;
3409}
3410
3411static int mlxsw_sp_vport_rif_sp_op(struct mlxsw_sp_port *mlxsw_sp_vport,
3412 struct net_device *l3_dev, u16 rif,
3413 bool create)
3414{
3415 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3416 bool lagged = mlxsw_sp_vport->lagged;
3417 char ritr_pl[MLXSW_REG_RITR_LEN];
3418 u16 system_port;
3419
3420 mlxsw_reg_ritr_pack(ritr_pl, create, MLXSW_REG_RITR_SP_IF, rif,
3421 l3_dev->mtu, l3_dev->dev_addr);
3422
3423 mlxsw_sp_vport_rif_sp_attr_get(mlxsw_sp_vport, &lagged, &system_port);
3424 mlxsw_reg_ritr_sp_if_pack(ritr_pl, lagged, system_port,
3425 mlxsw_sp_vport_vid_get(mlxsw_sp_vport));
3426
3427 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3428}
3429
3430static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3431
3432static struct mlxsw_sp_fid *
3433mlxsw_sp_rfid_alloc(u16 fid, struct net_device *l3_dev)
3434{
3435 struct mlxsw_sp_fid *f;
3436
3437 f = kzalloc(sizeof(*f), GFP_KERNEL);
3438 if (!f)
3439 return NULL;
3440
3441 f->leave = mlxsw_sp_vport_rif_sp_leave;
3442 f->ref_count = 0;
3443 f->dev = l3_dev;
3444 f->fid = fid;
3445
3446 return f;
3447}
3448
3449static struct mlxsw_sp_rif *
3450mlxsw_sp_rif_alloc(u16 rif, struct net_device *l3_dev, struct mlxsw_sp_fid *f)
3451{
3452 struct mlxsw_sp_rif *r;
3453
3454 r = kzalloc(sizeof(*r), GFP_KERNEL);
3455 if (!r)
3456 return NULL;
3457
3458 ether_addr_copy(r->addr, l3_dev->dev_addr);
3459 r->mtu = l3_dev->mtu;
3460 r->ref_count = 1;
3461 r->dev = l3_dev;
3462 r->rif = rif;
3463 r->f = f;
3464
3465 return r;
3466}
3467
3468static struct mlxsw_sp_rif *
3469mlxsw_sp_vport_rif_sp_create(struct mlxsw_sp_port *mlxsw_sp_vport,
3470 struct net_device *l3_dev)
3471{
3472 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3473 struct mlxsw_sp_fid *f;
3474 struct mlxsw_sp_rif *r;
3475 u16 fid, rif;
3476 int err;
3477
3478 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
8f8a62d4 3479 if (rif == MLXSW_SP_INVALID_RIF)
99724c18
IS		 3480 return ERR_PTR(-ERANGE);
3481
3482 err = mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, true);
3483 if (err)
3484 return ERR_PTR(err);
3485
3486 fid = mlxsw_sp_rif_sp_to_fid(rif);
3487 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, true);
3488 if (err)
3489 goto err_rif_fdb_op;
3490
3491 f = mlxsw_sp_rfid_alloc(fid, l3_dev);
3492 if (!f) {
3493 err = -ENOMEM;
3494 goto err_rfid_alloc;
3495 }
3496
3497 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3498 if (!r) {
3499 err = -ENOMEM;
3500 goto err_rif_alloc;
3501 }
3502
3503 f->r = r;
3504 mlxsw_sp->rifs[rif] = r;
3505
3506 return r;
3507
3508err_rif_alloc:
3509 kfree(f);
3510err_rfid_alloc:
3511 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3512err_rif_fdb_op:
3513 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3514 return ERR_PTR(err);
3515}
3516
3517static void mlxsw_sp_vport_rif_sp_destroy(struct mlxsw_sp_port *mlxsw_sp_vport,
3518 struct mlxsw_sp_rif *r)
3519{
3520 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3521 struct net_device *l3_dev = r->dev;
3522 struct mlxsw_sp_fid *f = r->f;
3523 u16 fid = f->fid;
3524 u16 rif = r->rif;
3525
3526 mlxsw_sp->rifs[rif] = NULL;
3527 f->r = NULL;
3528
3529 kfree(r);
3530
3531 kfree(f);
3532
3533 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3534
3535 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3536}
3537
3538static int mlxsw_sp_vport_rif_sp_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3539 struct net_device *l3_dev)
3540{
3541 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3542 struct mlxsw_sp_rif *r;
3543
3544 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, l3_dev);
3545 if (!r) {
3546 r = mlxsw_sp_vport_rif_sp_create(mlxsw_sp_vport, l3_dev);
3547 if (IS_ERR(r))
3548 return PTR_ERR(r);
3549 }
3550
3551 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, r->f);
3552 r->f->ref_count++;
3553
3554 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", r->f->fid);
3555
3556 return 0;
3557}
3558
3559static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3560{
3561 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3562
3563 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3564
3565 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
3566 if (--f->ref_count == 0)
3567 mlxsw_sp_vport_rif_sp_destroy(mlxsw_sp_vport, f->r);
3568}
3569
3570static int mlxsw_sp_inetaddr_vport_event(struct net_device *l3_dev,
3571 struct net_device *port_dev,
3572 unsigned long event, u16 vid)
3573{
3574 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(port_dev);
3575 struct mlxsw_sp_port *mlxsw_sp_vport;
3576
3577 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3578 if (WARN_ON(!mlxsw_sp_vport))
3579 return -EINVAL;
3580
3581 switch (event) {
3582 case NETDEV_UP:
3583 return mlxsw_sp_vport_rif_sp_join(mlxsw_sp_vport, l3_dev);
3584 case NETDEV_DOWN:
3585 mlxsw_sp_vport_rif_sp_leave(mlxsw_sp_vport);
3586 break;
3587 }
3588
3589 return 0;
3590}
3591
3592static int mlxsw_sp_inetaddr_port_event(struct net_device *port_dev,
3593 unsigned long event)
3594{
3595 if (netif_is_bridge_port(port_dev) || netif_is_lag_port(port_dev))
3596 return 0;
3597
3598 return mlxsw_sp_inetaddr_vport_event(port_dev, port_dev, event, 1);
3599}
3600
3601static int __mlxsw_sp_inetaddr_lag_event(struct net_device *l3_dev,
3602 struct net_device *lag_dev,
3603 unsigned long event, u16 vid)
3604{
3605 struct net_device *port_dev;
3606 struct list_head *iter;
3607 int err;
3608
3609 netdev_for_each_lower_dev(lag_dev, port_dev, iter) {
3610 if (mlxsw_sp_port_dev_check(port_dev)) {
3611 err = mlxsw_sp_inetaddr_vport_event(l3_dev, port_dev,
3612 event, vid);
3613 if (err)
3614 return err;
3615 }
3616 }
3617
3618 return 0;
3619}
3620
3621static int mlxsw_sp_inetaddr_lag_event(struct net_device *lag_dev,
3622 unsigned long event)
3623{
3624 if (netif_is_bridge_port(lag_dev))
3625 return 0;
3626
3627 return __mlxsw_sp_inetaddr_lag_event(lag_dev, lag_dev, event, 1);
3628}
3629
99f44bb3
IS		 3630static struct mlxsw_sp_fid *mlxsw_sp_bridge_fid_get(struct mlxsw_sp *mlxsw_sp,
3631 struct net_device *l3_dev)
3632{
3633 u16 fid;
3634
3635 if (is_vlan_dev(l3_dev))
3636 fid = vlan_dev_vlan_id(l3_dev);
3637 else if (mlxsw_sp->master_bridge.dev == l3_dev)
3638 fid = 1;
3639 else
3640 return mlxsw_sp_vfid_find(mlxsw_sp, l3_dev);
3641
3642 return mlxsw_sp_fid_find(mlxsw_sp, fid);
3643}
3644
f888f587
IS		 3645static enum mlxsw_flood_table_type mlxsw_sp_flood_table_type_get(u16 fid)
3646{
3647 return mlxsw_sp_fid_is_vfid(fid) ? MLXSW_REG_SFGC_TABLE_TYPE_FID :
3648 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
3649}
3650
3651static u16 mlxsw_sp_flood_table_index_get(u16 fid)
3652{
3653 return mlxsw_sp_fid_is_vfid(fid) ? mlxsw_sp_fid_to_vfid(fid) : fid;
3654}
3655
3656static int mlxsw_sp_router_port_flood_set(struct mlxsw_sp *mlxsw_sp, u16 fid,
3657 bool set)
3658{
3659 enum mlxsw_flood_table_type table_type;
3660 char *sftr_pl;
3661 u16 index;
3662 int err;
3663
3664 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
3665 if (!sftr_pl)
3666 return -ENOMEM;
3667
3668 table_type = mlxsw_sp_flood_table_type_get(fid);
3669 index = mlxsw_sp_flood_table_index_get(fid);
3670 mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, index, table_type,
3671 1, MLXSW_PORT_ROUTER_PORT, set);
3672 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl);
3673
3674 kfree(sftr_pl);
3675 return err;
3676}
3677
99f44bb3
IS		 3678static enum mlxsw_reg_ritr_if_type mlxsw_sp_rif_type_get(u16 fid)
3679{
3680 if (mlxsw_sp_fid_is_vfid(fid))
3681 return MLXSW_REG_RITR_FID_IF;
3682 else
3683 return MLXSW_REG_RITR_VLAN_IF;
3684}
3685
3686static int mlxsw_sp_rif_bridge_op(struct mlxsw_sp *mlxsw_sp,
3687 struct net_device *l3_dev,
3688 u16 fid, u16 rif,
3689 bool create)
3690{
3691 enum mlxsw_reg_ritr_if_type rif_type;
3692 char ritr_pl[MLXSW_REG_RITR_LEN];
3693
3694 rif_type = mlxsw_sp_rif_type_get(fid);
3695 mlxsw_reg_ritr_pack(ritr_pl, create, rif_type, rif, l3_dev->mtu,
3696 l3_dev->dev_addr);
3697 mlxsw_reg_ritr_fid_set(ritr_pl, rif_type, fid);
3698
3699 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3700}
3701
3702static int mlxsw_sp_rif_bridge_create(struct mlxsw_sp *mlxsw_sp,
3703 struct net_device *l3_dev,
3704 struct mlxsw_sp_fid *f)
3705{
3706 struct mlxsw_sp_rif *r;
3707 u16 rif;
3708 int err;
3709
3710 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
8f8a62d4 3711 if (rif == MLXSW_SP_INVALID_RIF)
99f44bb3
IS		 3712 return -ERANGE;
3713
f888f587 3714 err = mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, true);
99f44bb3
IS		 3715 if (err)
3716 return err;
3717
f888f587
IS		 3718 err = mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, true);
3719 if (err)
3720 goto err_rif_bridge_op;
3721
99f44bb3
IS		 3722 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, true);
3723 if (err)
3724 goto err_rif_fdb_op;
3725
3726 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3727 if (!r) {
3728 err = -ENOMEM;
3729 goto err_rif_alloc;
3730 }
3731
3732 f->r = r;
3733 mlxsw_sp->rifs[rif] = r;
3734
3735 netdev_dbg(l3_dev, "RIF=%d created\n", rif);
3736
3737 return 0;
3738
3739err_rif_alloc:
3740 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3741err_rif_fdb_op:
3742 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
f888f587
IS		 3743err_rif_bridge_op:
3744 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
99f44bb3
IS		 3745 return err;
3746}
3747
3748void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
3749 struct mlxsw_sp_rif *r)
3750{
3751 struct net_device *l3_dev = r->dev;
3752 struct mlxsw_sp_fid *f = r->f;
3753 u16 rif = r->rif;
3754
3755 mlxsw_sp->rifs[rif] = NULL;
3756 f->r = NULL;
3757
3758 kfree(r);
3759
3760 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3761
3762 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
3763
f888f587
IS		 3764 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
3765
99f44bb3
IS		 3766 netdev_dbg(l3_dev, "RIF=%d destroyed\n", rif);
3767}
3768
3769static int mlxsw_sp_inetaddr_bridge_event(struct net_device *l3_dev,
3770 struct net_device *br_dev,
3771 unsigned long event)
3772{
3773 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(l3_dev);
3774 struct mlxsw_sp_fid *f;
3775
3776 /* FID can either be an actual FID if the L3 device is the
3777 * VLAN-aware bridge or a VLAN device on top. Otherwise, the
3778 * L3 device is a VLAN-unaware bridge and we get a vFID.
3779 */
3780 f = mlxsw_sp_bridge_fid_get(mlxsw_sp, l3_dev);
3781 if (WARN_ON(!f))
3782 return -EINVAL;
3783
3784 switch (event) {
3785 case NETDEV_UP:
3786 return mlxsw_sp_rif_bridge_create(mlxsw_sp, l3_dev, f);
3787 case NETDEV_DOWN:
3788 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
3789 break;
3790 }
3791
3792 return 0;
3793}
3794
99724c18
IS		 3795static int mlxsw_sp_inetaddr_vlan_event(struct net_device *vlan_dev,
3796 unsigned long event)
3797{
3798 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
99f44bb3 3799 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
99724c18
IS		 3800 u16 vid = vlan_dev_vlan_id(vlan_dev);
3801
3802 if (mlxsw_sp_port_dev_check(real_dev))
3803 return mlxsw_sp_inetaddr_vport_event(vlan_dev, real_dev, event,
3804 vid);
3805 else if (netif_is_lag_master(real_dev))
3806 return __mlxsw_sp_inetaddr_lag_event(vlan_dev, real_dev, event,
3807 vid);
99f44bb3
IS		 3808 else if (netif_is_bridge_master(real_dev) &&
3809 mlxsw_sp->master_bridge.dev == real_dev)
3810 return mlxsw_sp_inetaddr_bridge_event(vlan_dev, real_dev,
3811 event);
99724c18
IS		 3812
3813 return 0;
3814}
3815
3816static int mlxsw_sp_inetaddr_event(struct notifier_block *unused,
3817 unsigned long event, void *ptr)
3818{
3819 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
3820 struct net_device *dev = ifa->ifa_dev->dev;
3821 struct mlxsw_sp *mlxsw_sp;
3822 struct mlxsw_sp_rif *r;
3823 int err = 0;
3824
3825 mlxsw_sp = mlxsw_sp_lower_get(dev);
3826 if (!mlxsw_sp)
3827 goto out;
3828
3829 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3830 if (!mlxsw_sp_rif_should_config(r, event))
3831 goto out;
3832
3833 if (mlxsw_sp_port_dev_check(dev))
3834 err = mlxsw_sp_inetaddr_port_event(dev, event);
3835 else if (netif_is_lag_master(dev))
3836 err = mlxsw_sp_inetaddr_lag_event(dev, event);
99f44bb3
IS		 3837 else if (netif_is_bridge_master(dev))
3838 err = mlxsw_sp_inetaddr_bridge_event(dev, dev, event);
99724c18
IS		 3839 else if (is_vlan_dev(dev))
3840 err = mlxsw_sp_inetaddr_vlan_event(dev, event);
3841
3842out:
3843 return notifier_from_errno(err);
3844}
3845
6e095fd4
IS		 3846static int mlxsw_sp_rif_edit(struct mlxsw_sp *mlxsw_sp, u16 rif,
3847 const char *mac, int mtu)
3848{
3849 char ritr_pl[MLXSW_REG_RITR_LEN];
3850 int err;
3851
3852 mlxsw_reg_ritr_rif_pack(ritr_pl, rif);
3853 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3854 if (err)
3855 return err;
3856
3857 mlxsw_reg_ritr_mtu_set(ritr_pl, mtu);
3858 mlxsw_reg_ritr_if_mac_memcpy_to(ritr_pl, mac);
3859 mlxsw_reg_ritr_op_set(ritr_pl, MLXSW_REG_RITR_RIF_CREATE);
3860 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3861}
3862
3863static int mlxsw_sp_netdevice_router_port_event(struct net_device *dev)
3864{
3865 struct mlxsw_sp *mlxsw_sp;
3866 struct mlxsw_sp_rif *r;
3867 int err;
3868
3869 mlxsw_sp = mlxsw_sp_lower_get(dev);
3870 if (!mlxsw_sp)
3871 return 0;
3872
3873 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3874 if (!r)
3875 return 0;
3876
3877 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, false);
3878 if (err)
3879 return err;
3880
3881 err = mlxsw_sp_rif_edit(mlxsw_sp, r->rif, dev->dev_addr, dev->mtu);
3882 if (err)
3883 goto err_rif_edit;
3884
3885 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, dev->dev_addr, r->f->fid, true);
3886 if (err)
3887 goto err_rif_fdb_op;
3888
3889 ether_addr_copy(r->addr, dev->dev_addr);
3890 r->mtu = dev->mtu;
3891
3892 netdev_dbg(dev, "Updated RIF=%d\n", r->rif);
3893
3894 return 0;
3895
3896err_rif_fdb_op:
3897 mlxsw_sp_rif_edit(mlxsw_sp, r->rif, r->addr, r->mtu);
3898err_rif_edit:
3899 mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, true);
3900 return err;
3901}
3902
fe3f6d14
IS		 3903static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3904 u16 fid)
3905{
3906 if (mlxsw_sp_fid_is_vfid(fid))
3907 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3908 else
3909 return test_bit(fid, lag_port->active_vlans);
3910}
3911
3912static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3913 u16 fid)
039c49a6
IS		 3914{
3915 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
fe3f6d14
IS		 3916 u8 local_port = mlxsw_sp_port->local_port;
3917 u16 lag_id = mlxsw_sp_port->lag_id;
c1a38311 3918 u64 max_lag_members;
fe3f6d14 3919 int i, count = 0;
039c49a6 3920
fe3f6d14
IS		 3921 if (!mlxsw_sp_port->lagged)
3922 return true;
039c49a6 3923
c1a38311
JP		 3924 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3925 MAX_LAG_MEMBERS);
3926 for (i = 0; i < max_lag_members; i++) {
fe3f6d14
IS		 3927 struct mlxsw_sp_port *lag_port;
3928
3929 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3930 if (!lag_port || lag_port->local_port == local_port)
3931 continue;
3932 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3933 count++;
3934 }
3935
3936 return !count;
039c49a6
IS		 3937}
3938
3939static int
3940mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3941 u16 fid)
3942{
3943 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3944 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3945
3946 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3947 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3948 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3949 mlxsw_sp_port->local_port);
3950
22305378
IS		 3951 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3952 mlxsw_sp_port->local_port, fid);
3953
039c49a6
IS		 3954 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3955}
3956
039c49a6
IS		 3957static int
3958mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3959 u16 fid)
3960{
3961 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3962 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3963
3964 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3965 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3966 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3967
22305378
IS		 3968 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3969 mlxsw_sp_port->lag_id, fid);
3970
039c49a6
IS		 3971 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3972}
3973
fe3f6d14 3974int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
039c49a6 3975{
fe3f6d14
IS		 3976 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3977 return 0;
039c49a6 3978
fe3f6d14
IS		 3979 if (mlxsw_sp_port->lagged)
3980 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
039c49a6
IS		 3981 fid);
3982 else
fe3f6d14 3983 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
039c49a6
IS		 3984}
3985
701b186e
IS		 3986static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3987{
3988 struct mlxsw_sp_fid *f, *tmp;
3989
3990 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3991 if (--f->ref_count == 0)
3992 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3993 else
3994 WARN_ON_ONCE(1);
3995}
3996
7117a570
IS		 3997static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3998 struct net_device *br_dev)
3999{
4000 return !mlxsw_sp->master_bridge.dev ||
4001 mlxsw_sp->master_bridge.dev == br_dev;
4002}
4003
4004static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
4005 struct net_device *br_dev)
4006{
4007 mlxsw_sp->master_bridge.dev = br_dev;
4008 mlxsw_sp->master_bridge.ref_count++;
4009}
4010
4011static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
4012{
701b186e 4013 if (--mlxsw_sp->master_bridge.ref_count == 0) {
7117a570 4014 mlxsw_sp->master_bridge.dev = NULL;
701b186e
IS		 4015 /* It's possible upper VLAN devices are still holding
4016 * references to underlying FIDs. Drop the reference
4017 * and release the resources if it was the last one.
4018 * If it wasn't, then something bad happened.
4019 */
4020 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
4021 }
7117a570
IS		 4022}
4023
4024static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
4025 struct net_device *br_dev)
56ade8fe
JP		 4026{
4027 struct net_device *dev = mlxsw_sp_port->dev;
4028 int err;
4029
4030 /* When port is not bridged untagged packets are tagged with
4031 * PVID=VID=1, thereby creating an implicit VLAN interface in
4032 * the device. Remove it and let bridge code take care of its
4033 * own VLANs.
4034 */
4035 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
6c72a3d0
IS		 4036 if (err)
4037 return err;
56ade8fe 4038
7117a570
IS		 4039 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
4040
6c72a3d0
IS		 4041 mlxsw_sp_port->learning = 1;
4042 mlxsw_sp_port->learning_sync = 1;
4043 mlxsw_sp_port->uc_flood = 1;
4044 mlxsw_sp_port->bridged = 1;
4045
4046 return 0;
56ade8fe
JP		 4047}
4048
fe3f6d14 4049static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
56ade8fe
JP		 4050{
4051 struct net_device *dev = mlxsw_sp_port->dev;
5a8f4525 4052
28a01d2d
IS		 4053 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4054
7117a570
IS		 4055 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
4056
6c72a3d0
IS		 4057 mlxsw_sp_port->learning = 0;
4058 mlxsw_sp_port->learning_sync = 0;
4059 mlxsw_sp_port->uc_flood = 0;
5a8f4525 4060 mlxsw_sp_port->bridged = 0;
56ade8fe
JP		 4061
4062 /* Add implicit VLAN interface in the device, so that untagged
4063 * packets will be classified to the default vFID.
4064 */
82e6db03 4065 mlxsw_sp_port_add_vid(dev, 0, 1);
56ade8fe
JP		 4066}
4067
0d65fc13
JP		 4068static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4069{
4070 char sldr_pl[MLXSW_REG_SLDR_LEN];
4071
4072 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4073 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4074}
4075
4076static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4077{
4078 char sldr_pl[MLXSW_REG_SLDR_LEN];
4079
4080 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4081 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4082}
4083
4084static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4085 u16 lag_id, u8 port_index)
4086{
4087 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4088 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4089
4090 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4091 lag_id, port_index);
4092 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4093}
4094
4095static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4096 u16 lag_id)
4097{
4098 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4099 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4100
4101 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4102 lag_id);
4103 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4104}
4105
4106static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4107 u16 lag_id)
4108{
4109 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4110 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4111
4112 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4113 lag_id);
4114 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4115}
4116
4117static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4118 u16 lag_id)
4119{
4120 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4121 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4122
4123 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4124 lag_id);
4125 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4126}
4127
4128static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4129 struct net_device *lag_dev,
4130 u16 *p_lag_id)
4131{
4132 struct mlxsw_sp_upper *lag;
4133 int free_lag_id = -1;
c1a38311 4134 u64 max_lag;
0d65fc13
JP		 4135 int i;
4136
c1a38311
JP		 4137 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4138 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 4139 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4140 if (lag->ref_count) {
4141 if (lag->dev == lag_dev) {
4142 *p_lag_id = i;
4143 return 0;
4144 }
4145 } else if (free_lag_id < 0) {
4146 free_lag_id = i;
4147 }
4148 }
4149 if (free_lag_id < 0)
4150 return -EBUSY;
4151 *p_lag_id = free_lag_id;
4152 return 0;
4153}
4154
4155static bool
4156mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4157 struct net_device *lag_dev,
4158 struct netdev_lag_upper_info *lag_upper_info)
4159{
4160 u16 lag_id;
4161
4162 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
4163 return false;
4164 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
4165 return false;
4166 return true;
4167}
4168
4169static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4170 u16 lag_id, u8 *p_port_index)
4171{
c1a38311 4172 u64 max_lag_members;
0d65fc13
JP		 4173 int i;
4174
c1a38311
JP		 4175 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4176 MAX_LAG_MEMBERS);
4177 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 4178 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4179 *p_port_index = i;
4180 return 0;
4181 }
4182 }
4183 return -EBUSY;
4184}
4185
86bf95b3
IS		 4186static void
4187mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4188 u16 lag_id)
4189{
4190 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 4191 struct mlxsw_sp_fid *f;
86bf95b3
IS		 4192
4193 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4194 if (WARN_ON(!mlxsw_sp_vport))
4195 return;
4196
11943ff4
IS		 4197 /* If vPort is assigned a RIF, then leave it since it's no
4198 * longer valid.
4199 */
4200 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4201 if (f)
4202 f->leave(mlxsw_sp_vport);
4203
86bf95b3
IS		 4204 mlxsw_sp_vport->lag_id = lag_id;
4205 mlxsw_sp_vport->lagged = 1;
4206}
4207
4208static void
4209mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4210{
4211 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 4212 struct mlxsw_sp_fid *f;
86bf95b3
IS		 4213
4214 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4215 if (WARN_ON(!mlxsw_sp_vport))
4216 return;
4217
11943ff4
IS		 4218 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4219 if (f)
4220 f->leave(mlxsw_sp_vport);
4221
86bf95b3
IS		 4222 mlxsw_sp_vport->lagged = 0;
4223}
4224
0d65fc13
JP		 4225static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4226 struct net_device *lag_dev)
4227{
4228 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4229 struct mlxsw_sp_upper *lag;
4230 u16 lag_id;
4231 u8 port_index;
4232 int err;
4233
4234 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4235 if (err)
4236 return err;
4237 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4238 if (!lag->ref_count) {
4239 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4240 if (err)
4241 return err;
4242 lag->dev = lag_dev;
4243 }
4244
4245 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4246 if (err)
4247 return err;
4248 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4249 if (err)
4250 goto err_col_port_add;
4251 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4252 if (err)
4253 goto err_col_port_enable;
4254
4255 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4256 mlxsw_sp_port->local_port);
4257 mlxsw_sp_port->lag_id = lag_id;
4258 mlxsw_sp_port->lagged = 1;
4259 lag->ref_count++;
86bf95b3
IS		 4260
4261 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
4262
0d65fc13
JP		 4263 return 0;
4264
51554db2
IS		 4265err_col_port_enable:
4266 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4267err_col_port_add:
4268 if (!lag->ref_count)
4269 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4270 return err;
4271}
4272
82e6db03
IS		 4273static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4274 struct net_device *lag_dev)
0d65fc13
JP		 4275{
4276 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4277 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4278 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4279
4280 if (!mlxsw_sp_port->lagged)
82e6db03 4281 return;
0d65fc13
JP		 4282 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4283 WARN_ON(lag->ref_count == 0);
4284
82e6db03
IS		 4285 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4286 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4287
4dc236c3
IS		 4288 if (mlxsw_sp_port->bridged) {
4289 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
fe3f6d14 4290 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4dc236c3
IS		 4291 }
4292
fe3f6d14 4293 if (lag->ref_count == 1)
82e6db03 4294 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4295
4296 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4297 mlxsw_sp_port->local_port);
4298 mlxsw_sp_port->lagged = 0;
4299 lag->ref_count--;
86bf95b3
IS		 4300
4301 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
0d65fc13
JP		 4302}
4303
74581206
JP		 4304static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4305 u16 lag_id)
4306{
4307 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4308 char sldr_pl[MLXSW_REG_SLDR_LEN];
4309
4310 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4311 mlxsw_sp_port->local_port);
4312 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4313}
4314
4315static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4316 u16 lag_id)
4317{
4318 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4319 char sldr_pl[MLXSW_REG_SLDR_LEN];
4320
4321 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4322 mlxsw_sp_port->local_port);
4323 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4324}
4325
4326static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4327 bool lag_tx_enabled)
4328{
4329 if (lag_tx_enabled)
4330 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4331 mlxsw_sp_port->lag_id);
4332 else
4333 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4334 mlxsw_sp_port->lag_id);
4335}
4336
4337static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4338 struct netdev_lag_lower_state_info *info)
4339{
4340 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4341}
4342
9589a7b5
IS		 4343static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4344 struct net_device *vlan_dev)
4345{
4346 struct mlxsw_sp_port *mlxsw_sp_vport;
4347 u16 vid = vlan_dev_vlan_id(vlan_dev);
4348
4349 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 4350 if (WARN_ON(!mlxsw_sp_vport))
9589a7b5 4351 return -EINVAL;
9589a7b5
IS		 4352
4353 mlxsw_sp_vport->dev = vlan_dev;
4354
4355 return 0;
4356}
4357
82e6db03
IS		 4358static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4359 struct net_device *vlan_dev)
9589a7b5
IS		 4360{
4361 struct mlxsw_sp_port *mlxsw_sp_vport;
4362 u16 vid = vlan_dev_vlan_id(vlan_dev);
4363
4364 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 4365 if (WARN_ON(!mlxsw_sp_vport))
82e6db03 4366 return;
9589a7b5
IS		 4367
4368 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
9589a7b5
IS		 4369}
4370
74581206
JP		 4371static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4372 unsigned long event, void *ptr)
56ade8fe 4373{
56ade8fe
JP		 4374 struct netdev_notifier_changeupper_info *info;
4375 struct mlxsw_sp_port *mlxsw_sp_port;
4376 struct net_device *upper_dev;
4377 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4378 int err = 0;
56ade8fe 4379
56ade8fe
JP		 4380 mlxsw_sp_port = netdev_priv(dev);
4381 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4382 info = ptr;
4383
4384 switch (event) {
4385 case NETDEV_PRECHANGEUPPER:
4386 upper_dev = info->upper_dev;
59fe9b3f
IS		 4387 if (!is_vlan_dev(upper_dev) &&
4388 !netif_is_lag_master(upper_dev) &&
4389 !netif_is_bridge_master(upper_dev))
4390 return -EINVAL;
6ec43904 4391 if (!info->linking)
0d65fc13 4392 break;
56ade8fe 4393 /* HW limitation forbids to put ports to multiple bridges. */
0d65fc13 4394 if (netif_is_bridge_master(upper_dev) &&
56ade8fe 4395 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
80bedf1a 4396 return -EINVAL;
0d65fc13
JP		 4397 if (netif_is_lag_master(upper_dev) &&
4398 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4399 info->upper_info))
80bedf1a 4400 return -EINVAL;
6ec43904
IS		 4401 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4402 return -EINVAL;
4403 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4404 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4405 return -EINVAL;
56ade8fe
JP		 4406 break;
4407 case NETDEV_CHANGEUPPER:
4408 upper_dev = info->upper_dev;
9589a7b5 4409 if (is_vlan_dev(upper_dev)) {
80bedf1a 4410 if (info->linking)
9589a7b5
IS		 4411 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4412 upper_dev);
80bedf1a 4413 else
82e6db03
IS		 4414 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4415 upper_dev);
9589a7b5 4416 } else if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4417 if (info->linking)
4418 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4419 upper_dev);
4420 else
fe3f6d14 4421 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
0d65fc13 4422 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4423 if (info->linking)
0d65fc13
JP		 4424 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4425 upper_dev);
80bedf1a 4426 else
82e6db03
IS		 4427 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4428 upper_dev);
59fe9b3f
IS		 4429 } else {
4430 err = -EINVAL;
4431 WARN_ON(1);
56ade8fe
JP		 4432 }
4433 break;
4434 }
4435
80bedf1a 4436 return err;
56ade8fe
JP		 4437}
4438
74581206
JP		 4439static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4440 unsigned long event, void *ptr)
4441{
4442 struct netdev_notifier_changelowerstate_info *info;
4443 struct mlxsw_sp_port *mlxsw_sp_port;
4444 int err;
4445
4446 mlxsw_sp_port = netdev_priv(dev);
4447 info = ptr;
4448
4449 switch (event) {
4450 case NETDEV_CHANGELOWERSTATE:
4451 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4452 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4453 info->lower_state_info);
4454 if (err)
4455 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4456 }
4457 break;
4458 }
4459
80bedf1a 4460 return 0;
74581206
JP		 4461}
4462
4463static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4464 unsigned long event, void *ptr)
4465{
4466 switch (event) {
4467 case NETDEV_PRECHANGEUPPER:
4468 case NETDEV_CHANGEUPPER:
4469 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4470 case NETDEV_CHANGELOWERSTATE:
4471 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4472 }
4473
80bedf1a 4474 return 0;
74581206
JP		 4475}
4476
0d65fc13
JP		 4477static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4478 unsigned long event, void *ptr)
4479{
4480 struct net_device *dev;
4481 struct list_head *iter;
4482 int ret;
4483
4484 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4485 if (mlxsw_sp_port_dev_check(dev)) {
4486 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
80bedf1a 4487 if (ret)
0d65fc13
JP		 4488 return ret;
4489 }
4490 }
4491
80bedf1a 4492 return 0;
0d65fc13
JP		 4493}
4494
701b186e
IS		 4495static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4496 struct net_device *vlan_dev)
26f0e7fb 4497{
701b186e 4498 u16 fid = vlan_dev_vlan_id(vlan_dev);
d0ec875a 4499 struct mlxsw_sp_fid *f;
26f0e7fb 4500
701b186e
IS		 4501 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4502 if (!f) {
4503 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4504 if (IS_ERR(f))
4505 return PTR_ERR(f);
26f0e7fb
IS		 4506 }
4507
701b186e
IS		 4508 f->ref_count++;
4509
4510 return 0;
4511}
4512
4513static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4514 struct net_device *vlan_dev)
4515{
4516 u16 fid = vlan_dev_vlan_id(vlan_dev);
4517 struct mlxsw_sp_fid *f;
4518
4519 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
99f44bb3
IS		 4520 if (f && f->r)
4521 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
701b186e
IS		 4522 if (f && --f->ref_count == 0)
4523 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4524}
4525
4526static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4527 unsigned long event, void *ptr)
4528{
4529 struct netdev_notifier_changeupper_info *info;
4530 struct net_device *upper_dev;
4531 struct mlxsw_sp *mlxsw_sp;
4532 int err;
4533
4534 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4535 if (!mlxsw_sp)
4536 return 0;
4537 if (br_dev != mlxsw_sp->master_bridge.dev)
4538 return 0;
4539
4540 info = ptr;
4541
4542 switch (event) {
4543 case NETDEV_CHANGEUPPER:
4544 upper_dev = info->upper_dev;
4545 if (!is_vlan_dev(upper_dev))
4546 break;
4547 if (info->linking) {
4548 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4549 upper_dev);
4550 if (err)
4551 return err;
4552 } else {
4553 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp, upper_dev);
4554 }
4555 break;
4556 }
4557
4558 return 0;
26f0e7fb
IS		 4559}
4560
3ba2ebf4 4561static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
26f0e7fb 4562{
3ba2ebf4 4563 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
99724c18 4564 MLXSW_SP_VFID_MAX);
26f0e7fb
IS		 4565}
4566
99724c18 4567static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
26f0e7fb 4568{
99724c18 4569 char sfmr_pl[MLXSW_REG_SFMR_LEN];
26f0e7fb 4570
99724c18
IS		 4571 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4572 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
26f0e7fb
IS		 4573}
4574
3ba2ebf4 4575static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
1c800759 4576
3ba2ebf4
IS		 4577static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4578 struct net_device *br_dev)
26f0e7fb
IS		 4579{
4580 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 4581 struct mlxsw_sp_fid *f;
c7e920b5 4582 u16 vfid, fid;
26f0e7fb
IS		 4583 int err;
4584
3ba2ebf4 4585 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
c7e920b5 4586 if (vfid == MLXSW_SP_VFID_MAX) {
26f0e7fb
IS		 4587 dev_err(dev, "No available vFIDs\n");
4588 return ERR_PTR(-ERANGE);
4589 }
4590
c7e920b5
IS		 4591 fid = mlxsw_sp_vfid_to_fid(vfid);
4592 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
26f0e7fb 4593 if (err) {
c7e920b5 4594 dev_err(dev, "Failed to create FID=%d\n", fid);
26f0e7fb
IS		 4595 return ERR_PTR(err);
4596 }
4597
c7e920b5
IS		 4598 f = kzalloc(sizeof(*f), GFP_KERNEL);
4599 if (!f)
26f0e7fb
IS		 4600 goto err_allocate_vfid;
4601
3ba2ebf4 4602 f->leave = mlxsw_sp_vport_vfid_leave;
d0ec875a
IS		 4603 f->fid = fid;
4604 f->dev = br_dev;
26f0e7fb 4605
3ba2ebf4
IS		 4606 list_add(&f->list, &mlxsw_sp->vfids.list);
4607 set_bit(vfid, mlxsw_sp->vfids.mapped);
26f0e7fb 4608
c7e920b5 4609 return f;
26f0e7fb
IS		 4610
4611err_allocate_vfid:
c7e920b5 4612 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 4613 return ERR_PTR(-ENOMEM);
4614}
4615
3ba2ebf4
IS		 4616static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4617 struct mlxsw_sp_fid *f)
26f0e7fb 4618{
d0ec875a 4619 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
99f44bb3 4620 u16 fid = f->fid;
26f0e7fb 4621
3ba2ebf4 4622 clear_bit(vfid, mlxsw_sp->vfids.mapped);
d0ec875a 4623 list_del(&f->list);
26f0e7fb 4624
99f44bb3
IS		 4625 if (f->r)
4626 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
26f0e7fb 4627
d0ec875a 4628 kfree(f);
99f44bb3
IS		 4629
4630 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 4631}
4632
99724c18
IS		 4633static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4634 bool valid)
4635{
4636 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4637 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4638
4639 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4640 vid);
4641}
4642
3ba2ebf4
IS		 4643static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4644 struct net_device *br_dev)
26f0e7fb 4645{
0355b59f 4646 struct mlxsw_sp_fid *f;
26f0e7fb
IS		 4647 int err;
4648
3ba2ebf4 4649 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
0355b59f 4650 if (!f) {
3ba2ebf4 4651 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
0355b59f
IS		 4652 if (IS_ERR(f))
4653 return PTR_ERR(f);
26f0e7fb
IS		 4654 }
4655
0355b59f
IS		 4656 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4657 if (err)
4658 goto err_vport_flood_set;
26f0e7fb 4659
0355b59f
IS		 4660 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4661 if (err)
9c4d4423 4662 goto err_vport_fid_map;
26f0e7fb 4663
41b996cc 4664 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f 4665 f->ref_count++;
6a9863a6 4666
22305378
IS		 4667 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4668
0355b59f 4669 return 0;
039c49a6 4670
0355b59f
IS		 4671err_vport_fid_map:
4672 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4673err_vport_flood_set:
d0ec875a 4674 if (!f->ref_count)
3ba2ebf4 4675 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
0355b59f
IS		 4676 return err;
4677}
26f0e7fb 4678
3ba2ebf4 4679static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f 4680{
41b996cc 4681 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb 4682
22305378
IS		 4683 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4684
0355b59f 4685 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
26f0e7fb 4686
0355b59f
IS		 4687 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4688
fe3f6d14
IS		 4689 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4690
41b996cc 4691 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f 4692 if (--f->ref_count == 0)
3ba2ebf4 4693 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
26f0e7fb
IS		 4694}
4695
4696static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4697 struct net_device *br_dev)
4698{
99724c18 4699 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb
IS		 4700 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4701 struct net_device *dev = mlxsw_sp_vport->dev;
26f0e7fb
IS		 4702 int err;
4703
99724c18
IS		 4704 if (f && !WARN_ON(!f->leave))
4705 f->leave(mlxsw_sp_vport);
26f0e7fb 4706
3ba2ebf4 4707 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
26f0e7fb 4708 if (err) {
0355b59f 4709 netdev_err(dev, "Failed to join vFID\n");
99724c18 4710 return err;
26f0e7fb
IS		 4711 }
4712
4713 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4714 if (err) {
4715 netdev_err(dev, "Failed to enable learning\n");
4716 goto err_port_vid_learning_set;
4717 }
4718
26f0e7fb
IS		 4719 mlxsw_sp_vport->learning = 1;
4720 mlxsw_sp_vport->learning_sync = 1;
4721 mlxsw_sp_vport->uc_flood = 1;
4722 mlxsw_sp_vport->bridged = 1;
4723
4724 return 0;
4725
26f0e7fb 4726err_port_vid_learning_set:
3ba2ebf4 4727 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
26f0e7fb
IS		 4728 return err;
4729}
4730
fe3f6d14 4731static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f
IS		 4732{
4733 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
0355b59f
IS		 4734
4735 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4736
3ba2ebf4 4737 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
0355b59f 4738
0355b59f
IS		 4739 mlxsw_sp_vport->learning = 0;
4740 mlxsw_sp_vport->learning_sync = 0;
4741 mlxsw_sp_vport->uc_flood = 0;
4742 mlxsw_sp_vport->bridged = 0;
4743}
4744
26f0e7fb
IS		 4745static bool
4746mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4747 const struct net_device *br_dev)
4748{
4749 struct mlxsw_sp_port *mlxsw_sp_vport;
4750
4751 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4752 vport.list) {
3ba2ebf4 4753 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
56918b6b
IS		 4754
4755 if (dev && dev == br_dev)
26f0e7fb
IS		 4756 return false;
4757 }
4758
4759 return true;
4760}
4761
4762static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4763 unsigned long event, void *ptr,
4764 u16 vid)
4765{
4766 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4767 struct netdev_notifier_changeupper_info *info = ptr;
4768 struct mlxsw_sp_port *mlxsw_sp_vport;
4769 struct net_device *upper_dev;
80bedf1a 4770 int err = 0;
26f0e7fb
IS		 4771
4772 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4773
4774 switch (event) {
4775 case NETDEV_PRECHANGEUPPER:
4776 upper_dev = info->upper_dev;
26f0e7fb 4777 if (!netif_is_bridge_master(upper_dev))
80bedf1a 4778 return -EINVAL;
ddbe993d
IS		 4779 if (!info->linking)
4780 break;
26f0e7fb
IS		 4781 /* We can't have multiple VLAN interfaces configured on
4782 * the same port and being members in the same bridge.
4783 */
4784 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
4785 upper_dev))
80bedf1a 4786 return -EINVAL;
26f0e7fb
IS		 4787 break;
4788 case NETDEV_CHANGEUPPER:
4789 upper_dev = info->upper_dev;
26f0e7fb 4790 if (info->linking) {
423b937e 4791 if (WARN_ON(!mlxsw_sp_vport))
80bedf1a 4792 return -EINVAL;
26f0e7fb
IS		 4793 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4794 upper_dev);
26f0e7fb 4795 } else {
26f0e7fb 4796 if (!mlxsw_sp_vport)
80bedf1a 4797 return 0;
fe3f6d14 4798 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
26f0e7fb
IS		 4799 }
4800 }
4801
80bedf1a 4802 return err;
26f0e7fb
IS		 4803}
4804
272c4470
IS		 4805static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4806 unsigned long event, void *ptr,
4807 u16 vid)
4808{
4809 struct net_device *dev;
4810 struct list_head *iter;
4811 int ret;
4812
4813 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4814 if (mlxsw_sp_port_dev_check(dev)) {
4815 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4816 vid);
80bedf1a 4817 if (ret)
272c4470
IS		 4818 return ret;
4819 }
4820 }
4821
80bedf1a 4822 return 0;
272c4470
IS		 4823}
4824
26f0e7fb
IS		 4825static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4826 unsigned long event, void *ptr)
4827{
4828 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4829 u16 vid = vlan_dev_vlan_id(vlan_dev);
4830
272c4470
IS		 4831 if (mlxsw_sp_port_dev_check(real_dev))
4832 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4833 vid);
4834 else if (netif_is_lag_master(real_dev))
4835 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4836 vid);
26f0e7fb 4837
80bedf1a 4838 return 0;
26f0e7fb
IS		 4839}
4840
0d65fc13
JP		 4841static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4842 unsigned long event, void *ptr)
4843{
4844 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
80bedf1a 4845 int err = 0;
0d65fc13 4846
6e095fd4
IS		 4847 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4848 err = mlxsw_sp_netdevice_router_port_event(dev);
4849 else if (mlxsw_sp_port_dev_check(dev))
80bedf1a
IS		 4850 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4851 else if (netif_is_lag_master(dev))
4852 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
701b186e
IS		 4853 else if (netif_is_bridge_master(dev))
4854 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
80bedf1a
IS		 4855 else if (is_vlan_dev(dev))
4856 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 4857
80bedf1a 4858 return notifier_from_errno(err);
0d65fc13
JP		 4859}
4860
56ade8fe
JP		 4861static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4862 .notifier_call = mlxsw_sp_netdevice_event,
4863};
4864
99724c18
IS		 4865static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4866 .notifier_call = mlxsw_sp_inetaddr_event,
4867 .priority = 10, /* Must be called before FIB notifier block */
4868};
4869
e7322638
JP		 4870static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4871 .notifier_call = mlxsw_sp_router_netevent_event,
4872};
4873
1d20d23c
JP		 4874static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4875 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4876 {0, },
4877};
4878
4879static struct pci_driver mlxsw_sp_pci_driver = {
4880 .name = mlxsw_sp_driver_name,
4881 .id_table = mlxsw_sp_pci_id_table,
4882};
4883
56ade8fe
JP		 4884static int __init mlxsw_sp_module_init(void)
4885{
4886 int err;
4887
4888 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
99724c18 4889 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
e7322638
JP		 4890 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4891
56ade8fe
JP		 4892 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4893 if (err)
4894 goto err_core_driver_register;
1d20d23c
JP		 4895
4896 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4897 if (err)
4898 goto err_pci_driver_register;
4899
56ade8fe
JP		 4900 return 0;
4901
1d20d23c
JP		 4902err_pci_driver_register:
4903 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 4904err_core_driver_register:
e7322638 4905 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
de7d6295 4906 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4907 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4908 return err;
4909}
4910
4911static void __exit mlxsw_sp_module_exit(void)
4912{
1d20d23c 4913 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 4914 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
e7322638 4915 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
99724c18 4916 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4917 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4918}
4919
4920module_init(mlxsw_sp_module_init);
4921module_exit(mlxsw_sp_module_exit);
4922
4923MODULE_LICENSE("Dual BSD/GPL");
4924MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4925MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 4926MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
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