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mlxsw: pci: Add support for performing bus reset
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
CommitLineData
56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
22a67766
JP		 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
56ade8fe
JP		 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
c1f2c6d0 56#include <linux/netlink.h>
56ade8fe 57#include <net/switchdev.h>
763b4b70
YG		 58#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
e7322638 60#include <net/netevent.h>
98d0f7b9 61#include <net/tc_act/tc_sample.h>
5ea1237f 62#include <net/addrconf.h>
56ade8fe
JP		 63
64#include "spectrum.h"
1d20d23c 65#include "pci.h"
56ade8fe
JP		 66#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
ff7b0d27 71#include "spectrum_cnt.h"
230ead01 72#include "spectrum_dpipe.h"
d3b939b8 73#include "spectrum_acl_flex_actions.h"
e5e5c88a 74#include "../mlxfw/mlxfw.h"
56ade8fe 75
6b742199 76#define MLXSW_FWREV_MAJOR 13
2f53fbd5
ST		 77#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
6b742199
YG		 79
80static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
81 .major = MLXSW_FWREV_MAJOR,
82 .minor = MLXSW_FWREV_MINOR,
83 .subminor = MLXSW_FWREV_SUBMINOR
84};
85
86#define MLXSW_SP_FW_FILENAME \
a4e1ce24 87 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
6b742199
YG		 88 "." __stringify(MLXSW_FWREV_MINOR) \
89 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
90
56ade8fe
JP		 91static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
92static const char mlxsw_sp_driver_version[] = "1.0";
93
94/* tx_hdr_version
95 * Tx header version.
96 * Must be set to 1.
97 */
98MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
99
100/* tx_hdr_ctl
101 * Packet control type.
102 * 0 - Ethernet control (e.g. EMADs, LACP)
103 * 1 - Ethernet data
104 */
105MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
106
107/* tx_hdr_proto
108 * Packet protocol type. Must be set to 1 (Ethernet).
109 */
110MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
111
112/* tx_hdr_rx_is_router
113 * Packet is sent from the router. Valid for data packets only.
114 */
115MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
116
117/* tx_hdr_fid_valid
118 * Indicates if the 'fid' field is valid and should be used for
119 * forwarding lookup. Valid for data packets only.
120 */
121MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
122
123/* tx_hdr_swid
124 * Switch partition ID. Must be set to 0.
125 */
126MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
127
128/* tx_hdr_control_tclass
129 * Indicates if the packet should use the control TClass and not one
130 * of the data TClasses.
131 */
132MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
133
134/* tx_hdr_etclass
135 * Egress TClass to be used on the egress device on the egress port.
136 */
137MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
138
139/* tx_hdr_port_mid
140 * Destination local port for unicast packets.
141 * Destination multicast ID for multicast packets.
142 *
143 * Control packets are directed to a specific egress port, while data
144 * packets are transmitted through the CPU port (0) into the switch partition,
145 * where forwarding rules are applied.
146 */
147MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
148
149/* tx_hdr_fid
150 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
151 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
152 * Valid for data packets only.
153 */
154MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
155
156/* tx_hdr_type
157 * 0 - Data packets
158 * 6 - Control packets
159 */
160MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161
e5e5c88a
YG		 162struct mlxsw_sp_mlxfw_dev {
163 struct mlxfw_dev mlxfw_dev;
164 struct mlxsw_sp *mlxsw_sp;
165};
166
167static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
168 u16 component_index, u32 *p_max_size,
169 u8 *p_align_bits, u16 *p_max_write_size)
170{
171 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
172 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
174 char mcqi_pl[MLXSW_REG_MCQI_LEN];
175 int err;
176
177 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
178 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
179 if (err)
180 return err;
181 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
182 p_max_write_size);
183
184 *p_align_bits = max_t(u8, *p_align_bits, 2);
185 *p_max_write_size = min_t(u16, *p_max_write_size,
186 MLXSW_REG_MCDA_MAX_DATA_LEN);
187 return 0;
188}
189
190static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
191{
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
196 u8 control_state;
197 int err;
198
199 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
200 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
201 if (err)
202 return err;
203
204 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
205 if (control_state != MLXFW_FSM_STATE_IDLE)
206 return -EBUSY;
207
208 mlxsw_reg_mcc_pack(mcc_pl,
209 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
210 0, *fwhandle, 0);
211 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
212}
213
214static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
215 u32 fwhandle, u16 component_index,
216 u32 component_size)
217{
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
222
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
224 component_index, fwhandle, component_size);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226}
227
228static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
229 u32 fwhandle, u8 *data, u16 size,
230 u32 offset)
231{
232 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
233 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
234 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
235 char mcda_pl[MLXSW_REG_MCDA_LEN];
236
237 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
238 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
239}
240
241static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
242 u32 fwhandle, u16 component_index)
243{
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
248
249 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
250 component_index, fwhandle, 0);
251 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
252}
253
254static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
255{
256 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
257 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
258 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
259 char mcc_pl[MLXSW_REG_MCC_LEN];
260
261 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
262 fwhandle, 0);
263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
264}
265
266static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
267 enum mlxfw_fsm_state *fsm_state,
268 enum mlxfw_fsm_state_err *fsm_state_err)
269{
270 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
271 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
272 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
273 char mcc_pl[MLXSW_REG_MCC_LEN];
274 u8 control_state;
275 u8 error_code;
276 int err;
277
278 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
279 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
280 if (err)
281 return err;
282
283 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
284 *fsm_state = control_state;
285 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
286 MLXFW_FSM_STATE_ERR_MAX);
287 return 0;
288}
289
290static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
291{
292 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
293 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
294 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
295 char mcc_pl[MLXSW_REG_MCC_LEN];
296
297 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
298 fwhandle, 0);
299 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
300}
301
302static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
303{
304 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
305 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
307 char mcc_pl[MLXSW_REG_MCC_LEN];
308
309 mlxsw_reg_mcc_pack(mcc_pl,
310 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
311 fwhandle, 0);
312 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
313}
314
315static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
316 .component_query = mlxsw_sp_component_query,
317 .fsm_lock = mlxsw_sp_fsm_lock,
318 .fsm_component_update = mlxsw_sp_fsm_component_update,
319 .fsm_block_download = mlxsw_sp_fsm_block_download,
320 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
321 .fsm_activate = mlxsw_sp_fsm_activate,
322 .fsm_query_state = mlxsw_sp_fsm_query_state,
323 .fsm_cancel = mlxsw_sp_fsm_cancel,
324 .fsm_release = mlxsw_sp_fsm_release
325};
326
ce6ef68f
YG		 327static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
328 const struct firmware *firmware)
329{
330 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
331 .mlxfw_dev = {
332 .ops = &mlxsw_sp_mlxfw_dev_ops,
333 .psid = mlxsw_sp->bus_info->psid,
334 .psid_size = strlen(mlxsw_sp->bus_info->psid),
335 },
336 .mlxsw_sp = mlxsw_sp
337 };
338
339 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
340}
341
6b742199
YG		 342static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
343 const struct mlxsw_fw_rev *b)
344{
345 if (a->major != b->major)
346 return a->major > b->major;
347 if (a->minor != b->minor)
348 return a->minor > b->minor;
349 return a->subminor >= b->subminor;
350}
351
352static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
353{
354 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
6b742199
YG		 355 const struct firmware *firmware;
356 int err;
357
358 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
359 return 0;
360
d016e13d 361 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is out of date\n",
6b742199
YG		 362 rev->major, rev->minor, rev->subminor);
363 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
364 MLXSW_SP_FW_FILENAME);
365
366 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
367 mlxsw_sp->bus_info->dev);
368 if (err) {
369 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
370 MLXSW_SP_FW_FILENAME);
371 return err;
372 }
373
ce6ef68f 374 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
6b742199
YG		 375 release_firmware(firmware);
376 return err;
377}
378
1abcbcc2
AS		 379int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
380 unsigned int counter_index, u64 *packets,
381 u64 *bytes)
382{
383 char mgpc_pl[MLXSW_REG_MGPC_LEN];
384 int err;
385
386 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
6bba7e20 387 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 388 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
389 if (err)
390 return err;
7cfcbc75
AS		 391 if (packets)
392 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
393 if (bytes)
394 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
1abcbcc2
AS		 395 return 0;
396}
397
398static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
399 unsigned int counter_index)
400{
401 char mgpc_pl[MLXSW_REG_MGPC_LEN];
402
403 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
6bba7e20 404 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 405 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
406}
407
408int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
409 unsigned int *p_counter_index)
410{
411 int err;
412
413 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
414 p_counter_index);
415 if (err)
416 return err;
417 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
418 if (err)
419 goto err_counter_clear;
420 return 0;
421
422err_counter_clear:
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 *p_counter_index);
425 return err;
426}
427
428void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
429 unsigned int counter_index)
430{
431 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
432 counter_index);
433}
434
56ade8fe
JP		 435static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
436 const struct mlxsw_tx_info *tx_info)
437{
438 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
439
440 memset(txhdr, 0, MLXSW_TXHDR_LEN);
441
442 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
443 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
444 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
445 mlxsw_tx_hdr_swid_set(txhdr, 0);
446 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
447 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
448 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
449}
450
fe9ccc78
IS		 451int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
452 u8 state)
453{
454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
455 enum mlxsw_reg_spms_state spms_state;
456 char *spms_pl;
457 int err;
458
459 switch (state) {
460 case BR_STATE_FORWARDING:
461 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
462 break;
463 case BR_STATE_LEARNING:
464 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
465 break;
466 case BR_STATE_LISTENING: /* fall-through */
467 case BR_STATE_DISABLED: /* fall-through */
468 case BR_STATE_BLOCKING:
469 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
470 break;
471 default:
472 BUG();
473 }
474
475 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
476 if (!spms_pl)
477 return -ENOMEM;
478 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
479 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
480
481 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
482 kfree(spms_pl);
483 return err;
484}
485
56ade8fe
JP		 486static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
487{
5b090740 488 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
56ade8fe
JP		 489 int err;
490
491 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
492 if (err)
493 return err;
494 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
495 return 0;
496}
497
763b4b70
YG		 498static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
499{
763b4b70
YG		 500 int i;
501
c1a38311 502 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 503 return -EIO;
504
c1a38311
JP		 505 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
506 MAX_SPAN);
763b4b70
YG		 507 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
508 sizeof(struct mlxsw_sp_span_entry),
509 GFP_KERNEL);
510 if (!mlxsw_sp->span.entries)
511 return -ENOMEM;
512
513 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
514 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
515
516 return 0;
517}
518
519static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
520{
521 int i;
522
523 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
524 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
525
526 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
527 }
528 kfree(mlxsw_sp->span.entries);
529}
530
531static struct mlxsw_sp_span_entry *
532mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
533{
534 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
535 struct mlxsw_sp_span_entry *span_entry;
536 char mpat_pl[MLXSW_REG_MPAT_LEN];
537 u8 local_port = port->local_port;
538 int index;
539 int i;
540 int err;
541
542 /* find a free entry to use */
543 index = -1;
544 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
545 if (!mlxsw_sp->span.entries[i].used) {
546 index = i;
547 span_entry = &mlxsw_sp->span.entries[i];
548 break;
549 }
550 }
551 if (index < 0)
552 return NULL;
553
554 /* create a new port analayzer entry for local_port */
555 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
556 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
557 if (err)
558 return NULL;
559
560 span_entry->used = true;
561 span_entry->id = index;
2d644d4c 562 span_entry->ref_count = 1;
763b4b70
YG		 563 span_entry->local_port = local_port;
564 return span_entry;
565}
566
567static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
568 struct mlxsw_sp_span_entry *span_entry)
569{
570 u8 local_port = span_entry->local_port;
571 char mpat_pl[MLXSW_REG_MPAT_LEN];
572 int pa_id = span_entry->id;
573
574 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
575 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
576 span_entry->used = false;
577}
578
1a9234e6 579static struct mlxsw_sp_span_entry *
6399ebcc 580mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
763b4b70 581{
763b4b70
YG		 582 int i;
583
584 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
585 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
586
6399ebcc 587 if (curr->used && curr->local_port == local_port)
763b4b70
YG		 588 return curr;
589 }
590 return NULL;
591}
592
1a9234e6
IS		 593static struct mlxsw_sp_span_entry
594*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 595{
596 struct mlxsw_sp_span_entry *span_entry;
597
6399ebcc
YM		 598 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
599 port->local_port);
763b4b70 600 if (span_entry) {
2d644d4c 601 /* Already exists, just take a reference */
763b4b70
YG		 602 span_entry->ref_count++;
603 return span_entry;
604 }
605
606 return mlxsw_sp_span_entry_create(port);
607}
608
609static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
610 struct mlxsw_sp_span_entry *span_entry)
611{
2d644d4c 612 WARN_ON(!span_entry->ref_count);
763b4b70
YG		 613 if (--span_entry->ref_count == 0)
614 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
615 return 0;
616}
617
618static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
619{
620 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
621 struct mlxsw_sp_span_inspected_port *p;
622 int i;
623
624 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
625 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
626
627 list_for_each_entry(p, &curr->bound_ports_list, list)
628 if (p->local_port == port->local_port &&
629 p->type == MLXSW_SP_SPAN_EGRESS)
630 return true;
631 }
632
633 return false;
634}
635
18281f2d
IS		 636static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
637 int mtu)
763b4b70 638{
18281f2d 639 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
763b4b70
YG		 640}
641
642static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
643{
644 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
645 char sbib_pl[MLXSW_REG_SBIB_LEN];
646 int err;
647
648 /* If port is egress mirrored, the shared buffer size should be
649 * updated according to the mtu value
650 */
651 if (mlxsw_sp_span_is_egress_mirror(port)) {
18281f2d
IS		 652 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
653
654 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 655 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
656 if (err) {
657 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
658 return err;
659 }
660 }
661
662 return 0;
663}
664
665static struct mlxsw_sp_span_inspected_port *
666mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry)
668{
669 struct mlxsw_sp_span_inspected_port *p;
670
671 list_for_each_entry(p, &span_entry->bound_ports_list, list)
672 if (port->local_port == p->local_port)
673 return p;
674 return NULL;
675}
676
677static int
678mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
679 struct mlxsw_sp_span_entry *span_entry,
680 enum mlxsw_sp_span_type type)
681{
682 struct mlxsw_sp_span_inspected_port *inspected_port;
683 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
684 char mpar_pl[MLXSW_REG_MPAR_LEN];
685 char sbib_pl[MLXSW_REG_SBIB_LEN];
686 int pa_id = span_entry->id;
687 int err;
688
689 /* if it is an egress SPAN, bind a shared buffer to it */
690 if (type == MLXSW_SP_SPAN_EGRESS) {
18281f2d
IS		 691 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
692 port->dev->mtu);
693
694 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 695 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
696 if (err) {
697 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
698 return err;
699 }
700 }
701
702 /* bind the port to the SPAN entry */
1a9234e6
IS		 703 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
704 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
763b4b70
YG		 705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
706 if (err)
707 goto err_mpar_reg_write;
708
709 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
710 if (!inspected_port) {
711 err = -ENOMEM;
712 goto err_inspected_port_alloc;
713 }
714 inspected_port->local_port = port->local_port;
715 inspected_port->type = type;
716 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
717
718 return 0;
719
720err_mpar_reg_write:
721err_inspected_port_alloc:
722 if (type == MLXSW_SP_SPAN_EGRESS) {
723 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
724 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
725 }
726 return err;
727}
728
729static void
730mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
731 struct mlxsw_sp_span_entry *span_entry,
732 enum mlxsw_sp_span_type type)
733{
734 struct mlxsw_sp_span_inspected_port *inspected_port;
735 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
736 char mpar_pl[MLXSW_REG_MPAR_LEN];
737 char sbib_pl[MLXSW_REG_SBIB_LEN];
738 int pa_id = span_entry->id;
739
740 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
741 if (!inspected_port)
742 return;
743
744 /* remove the inspected port */
1a9234e6
IS		 745 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
746 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
763b4b70
YG		 747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
748
749 /* remove the SBIB buffer if it was egress SPAN */
750 if (type == MLXSW_SP_SPAN_EGRESS) {
751 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
752 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
753 }
754
755 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
756
757 list_del(&inspected_port->list);
758 kfree(inspected_port);
759}
760
761static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
762 struct mlxsw_sp_port *to,
763 enum mlxsw_sp_span_type type)
764{
765 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
766 struct mlxsw_sp_span_entry *span_entry;
767 int err;
768
769 span_entry = mlxsw_sp_span_entry_get(to);
770 if (!span_entry)
771 return -ENOENT;
772
773 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
774 span_entry->id);
775
776 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
777 if (err)
778 goto err_port_bind;
779
780 return 0;
781
782err_port_bind:
783 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
784 return err;
785}
786
787static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
6399ebcc 788 u8 destination_port,
763b4b70
YG		 789 enum mlxsw_sp_span_type type)
790{
791 struct mlxsw_sp_span_entry *span_entry;
792
6399ebcc
YM		 793 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
794 destination_port);
763b4b70
YG		 795 if (!span_entry) {
796 netdev_err(from->dev, "no span entry found\n");
797 return;
798 }
799
800 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
801 span_entry->id);
802 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
803}
804
98d0f7b9
YG		 805static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
806 bool enable, u32 rate)
807{
808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
809 char mpsc_pl[MLXSW_REG_MPSC_LEN];
810
811 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
812 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
813}
814
56ade8fe
JP		 815static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
816 bool is_up)
817{
818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
819 char paos_pl[MLXSW_REG_PAOS_LEN];
820
821 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
822 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
823 MLXSW_PORT_ADMIN_STATUS_DOWN);
824 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
825}
826
56ade8fe
JP		 827static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
828 unsigned char *addr)
829{
830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
831 char ppad_pl[MLXSW_REG_PPAD_LEN];
832
833 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
834 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
835 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
836}
837
838static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
839{
840 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
841 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
842
843 ether_addr_copy(addr, mlxsw_sp->base_mac);
844 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
845 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
846}
847
56ade8fe
JP		 848static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
849{
850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
851 char pmtu_pl[MLXSW_REG_PMTU_LEN];
852 int max_mtu;
853 int err;
854
855 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
856 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
857 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
858 if (err)
859 return err;
860 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
861
862 if (mtu > max_mtu)
863 return -EINVAL;
864
865 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
867}
868
be94535f
IS		 869static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
870{
871 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5b153859 872 char pspa_pl[MLXSW_REG_PSPA_LEN];
be94535f 873
5b153859
IS		 874 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
875 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
be94535f
IS		 876}
877
a1107487 878int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
56ade8fe
JP		 879{
880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
881 char svpe_pl[MLXSW_REG_SVPE_LEN];
882
883 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
884 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
885}
886
7cbc4277
IS		 887int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
888 bool learn_enable)
56ade8fe
JP		 889{
890 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
891 char *spvmlr_pl;
892 int err;
893
894 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
895 if (!spvmlr_pl)
896 return -ENOMEM;
7cbc4277
IS		 897 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
898 learn_enable);
56ade8fe
JP		 899 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
900 kfree(spvmlr_pl);
901 return err;
902}
903
b02eae9b
IS		 904static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
905 u16 vid)
906{
907 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
908 char spvid_pl[MLXSW_REG_SPVID_LEN];
909
910 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
912}
913
914static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
915 bool allow)
916{
917 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
918 char spaft_pl[MLXSW_REG_SPAFT_LEN];
919
920 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
922}
923
924int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
925{
926 int err;
927
928 if (!vid) {
929 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
930 if (err)
931 return err;
932 } else {
933 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
934 if (err)
935 return err;
936 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
937 if (err)
938 goto err_port_allow_untagged_set;
939 }
940
941 mlxsw_sp_port->pvid = vid;
942 return 0;
943
944err_port_allow_untagged_set:
945 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
946 return err;
947}
948
56ade8fe
JP		 949static int
950mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
951{
952 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
953 char sspr_pl[MLXSW_REG_SSPR_LEN];
954
955 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
956 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
957}
958
d664b41e
IS		 959static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
960 u8 local_port, u8 *p_module,
961 u8 *p_width, u8 *p_lane)
56ade8fe 962{
56ade8fe
JP		 963 char pmlp_pl[MLXSW_REG_PMLP_LEN];
964 int err;
965
558c2d5e 966 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 967 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
968 if (err)
969 return err;
558c2d5e
IS		 970 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
971 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 972 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 973 return 0;
974}
975
2e915e0b 976static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
18f1e70c
IS		 977 u8 module, u8 width, u8 lane)
978{
2e915e0b 979 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
18f1e70c
IS		 980 char pmlp_pl[MLXSW_REG_PMLP_LEN];
981 int i;
982
2e915e0b 983 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
18f1e70c
IS		 984 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
985 for (i = 0; i < width; i++) {
986 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
987 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
988 }
989
990 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
991}
992
2e915e0b 993static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
3e9b27b8 994{
2e915e0b 995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3e9b27b8
IS		 996 char pmlp_pl[MLXSW_REG_PMLP_LEN];
997
2e915e0b 998 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
3e9b27b8
IS		 999 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1001}
1002
56ade8fe
JP		 1003static int mlxsw_sp_port_open(struct net_device *dev)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 int err;
1007
1008 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1009 if (err)
1010 return err;
1011 netif_start_queue(dev);
1012 return 0;
1013}
1014
1015static int mlxsw_sp_port_stop(struct net_device *dev)
1016{
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018
1019 netif_stop_queue(dev);
1020 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1021}
1022
1023static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1024 struct net_device *dev)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1028 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1029 const struct mlxsw_tx_info tx_info = {
1030 .local_port = mlxsw_sp_port->local_port,
1031 .is_emad = false,
1032 };
1033 u64 len;
1034 int err;
1035
307c2431 1036 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 1037 return NETDEV_TX_BUSY;
1038
1039 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1040 struct sk_buff *skb_orig = skb;
1041
1042 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1043 if (!skb) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 dev_kfree_skb_any(skb_orig);
1046 return NETDEV_TX_OK;
1047 }
36bf38d1 1048 dev_consume_skb_any(skb_orig);
56ade8fe
JP		 1049 }
1050
1051 if (eth_skb_pad(skb)) {
1052 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1053 return NETDEV_TX_OK;
1054 }
1055
1056 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 1057 /* TX header is consumed by HW on the way so we shouldn't count its
1058 * bytes as being sent.
1059 */
1060 len = skb->len - MLXSW_TXHDR_LEN;
1061
56ade8fe
JP		 1062 /* Due to a race we might fail here because of a full queue. In that
1063 * unlikely case we simply drop the packet.
1064 */
307c2431 1065 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 1066
1067 if (!err) {
1068 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1069 u64_stats_update_begin(&pcpu_stats->syncp);
1070 pcpu_stats->tx_packets++;
1071 pcpu_stats->tx_bytes += len;
1072 u64_stats_update_end(&pcpu_stats->syncp);
1073 } else {
1074 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1075 dev_kfree_skb_any(skb);
1076 }
1077 return NETDEV_TX_OK;
1078}
1079
c5b9b518
JP		 1080static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1081{
1082}
1083
56ade8fe
JP		 1084static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1085{
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087 struct sockaddr *addr = p;
1088 int err;
1089
1090 if (!is_valid_ether_addr(addr->sa_data))
1091 return -EADDRNOTAVAIL;
1092
1093 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1094 if (err)
1095 return err;
1096 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1097 return 0;
1098}
1099
18281f2d
IS		 1100static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1101 int mtu)
ff6551ec 1102{
18281f2d 1103 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
f417f04d 1104}
8e8dfe9f 1105
f417f04d 1106#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
18281f2d
IS		 1107
1108static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1109 u16 delay)
f417f04d 1110{
18281f2d
IS		 1111 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1112 BITS_PER_BYTE));
1113 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1114 mtu);
f417f04d
IS		 1115}
1116
18281f2d 1117/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
f417f04d
IS		 1118 * Assumes 100m cable and maximum MTU.
1119 */
18281f2d
IS		 1120#define MLXSW_SP_PAUSE_DELAY 58752
1121
1122static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1123 u16 delay, bool pfc, bool pause)
f417f04d
IS		 1124{
1125 if (pfc)
18281f2d 1126 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
f417f04d 1127 else if (pause)
18281f2d 1128 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
f417f04d
IS		 1129 else
1130 return 0;
1131}
9f7ec052 1132
f417f04d
IS		 1133static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1134 bool lossy)
1135{
1136 if (lossy)
1137 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
d81a6bdb 1138 else
f417f04d
IS		 1139 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1140 thres);
8e8dfe9f
IS		 1141}
1142
1143int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 1144 u8 *prio_tc, bool pause_en,
1145 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 1146{
1147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 1148 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1149 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 1150 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 1151 int i, j, err;
ff6551ec
IS		 1152
1153 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1154 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1155 if (err)
1156 return err;
8e8dfe9f
IS		 1157
1158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1159 bool configure = false;
d81a6bdb 1160 bool pfc = false;
f417f04d
IS		 1161 bool lossy;
1162 u16 thres;
8e8dfe9f
IS		 1163
1164 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1165 if (prio_tc[j] == i) {
d81a6bdb 1166 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 1167 configure = true;
1168 break;
1169 }
1170 }
1171
1172 if (!configure)
1173 continue;
f417f04d
IS		 1174
1175 lossy = !(pfc || pause_en);
18281f2d
IS		 1176 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1177 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1178 pause_en);
f417f04d 1179 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
8e8dfe9f
IS		 1180 }
1181
ff6551ec
IS		 1182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1183}
1184
8e8dfe9f 1185static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 1186 int mtu, bool pause_en)
8e8dfe9f
IS		 1187{
1188 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1189 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 1190 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 1191 u8 *prio_tc;
1192
1193 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 1194 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 1195
9f7ec052 1196 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 1197 pause_en, my_pfc);
8e8dfe9f
IS		 1198}
1199
56ade8fe
JP		 1200static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 1203 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 1204 int err;
1205
9f7ec052 1206 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 1207 if (err)
1208 return err;
763b4b70
YG		 1209 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1210 if (err)
1211 goto err_span_port_mtu_update;
ff6551ec
IS		 1212 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1213 if (err)
1214 goto err_port_mtu_set;
56ade8fe
JP		 1215 dev->mtu = mtu;
1216 return 0;
ff6551ec
IS		 1217
1218err_port_mtu_set:
763b4b70
YG		 1219 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1220err_span_port_mtu_update:
9f7ec052 1221 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 1222 return err;
56ade8fe
JP		 1223}
1224
4bdcc6ca 1225static int
fc1bbb0f
NF		 1226mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1227 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 1228{
1229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1230 struct mlxsw_sp_port_pcpu_stats *p;
1231 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1232 u32 tx_dropped = 0;
1233 unsigned int start;
1234 int i;
1235
1236 for_each_possible_cpu(i) {
1237 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1238 do {
1239 start = u64_stats_fetch_begin_irq(&p->syncp);
1240 rx_packets = p->rx_packets;
1241 rx_bytes = p->rx_bytes;
1242 tx_packets = p->tx_packets;
1243 tx_bytes = p->tx_bytes;
1244 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1245
1246 stats->rx_packets += rx_packets;
1247 stats->rx_bytes += rx_bytes;
1248 stats->tx_packets += tx_packets;
1249 stats->tx_bytes += tx_bytes;
1250 /* tx_dropped is u32, updated without syncp protection. */
1251 tx_dropped += p->tx_dropped;
1252 }
1253 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 1254 return 0;
1255}
1256
3df5b3c6 1257static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
fc1bbb0f
NF		 1258{
1259 switch (attr_id) {
1260 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
4bdcc6ca
OG		 1267static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1268 void *sp)
fc1bbb0f
NF		 1269{
1270 switch (attr_id) {
1271 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1272 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1273 }
1274
1275 return -EINVAL;
1276}
1277
1278static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1279 int prio, char *ppcnt_pl)
1280{
1281 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1283
1284 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1285 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1286}
1287
1288static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1289 struct rtnl_link_stats64 *stats)
1290{
1291 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1292 int err;
1293
1294 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1295 0, ppcnt_pl);
1296 if (err)
1297 goto out;
1298
1299 stats->tx_packets =
1300 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1301 stats->rx_packets =
1302 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1303 stats->tx_bytes =
1304 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_bytes =
1306 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1307 stats->multicast =
1308 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1309
1310 stats->rx_crc_errors =
1311 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1312 stats->rx_frame_errors =
1313 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1314
1315 stats->rx_length_errors = (
1316 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1318 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1319
1320 stats->rx_errors = (stats->rx_crc_errors +
1321 stats->rx_frame_errors + stats->rx_length_errors);
1322
1323out:
1324 return err;
1325}
1326
075ab8ad
NF		 1327static void
1328mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1329 struct mlxsw_sp_port_xstats *xstats)
1330{
1331 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1332 int err, i;
1333
1334 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1335 ppcnt_pl);
1336 if (!err)
1337 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1338
1339 for (i = 0; i < TC_MAX_QUEUE; i++) {
1340 err = mlxsw_sp_port_get_stats_raw(dev,
1341 MLXSW_REG_PPCNT_TC_CONG_TC,
1342 i, ppcnt_pl);
1343 if (!err)
1344 xstats->wred_drop[i] =
1345 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1346
1347 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1348 i, ppcnt_pl);
1349 if (err)
1350 continue;
1351
1352 xstats->backlog[i] =
1353 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1354 xstats->tail_drop[i] =
1355 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1356 }
1357}
1358
fc1bbb0f
NF		 1359static void update_stats_cache(struct work_struct *work)
1360{
1361 struct mlxsw_sp_port *mlxsw_sp_port =
1362 container_of(work, struct mlxsw_sp_port,
9deef43d 1363 periodic_hw_stats.update_dw.work);
fc1bbb0f
NF		 1364
1365 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1366 goto out;
1367
1368 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
9deef43d 1369 &mlxsw_sp_port->periodic_hw_stats.stats);
075ab8ad
NF		 1370 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1371 &mlxsw_sp_port->periodic_hw_stats.xstats);
fc1bbb0f
NF		 1372
1373out:
9deef43d 1374 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 1375 MLXSW_HW_STATS_UPDATE_TIME);
1376}
1377
1378/* Return the stats from a cache that is updated periodically,
1379 * as this function might get called in an atomic context.
1380 */
bc1f4470 1381static void
fc1bbb0f
NF		 1382mlxsw_sp_port_get_stats64(struct net_device *dev,
1383 struct rtnl_link_stats64 *stats)
1384{
1385 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1386
9deef43d 1387 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
56ade8fe
JP		 1388}
1389
93cd0813
JP		 1390static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1391 u16 vid_begin, u16 vid_end,
1392 bool is_member, bool untagged)
56ade8fe
JP		 1393{
1394 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1395 char *spvm_pl;
1396 int err;
1397
1398 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1399 if (!spvm_pl)
1400 return -ENOMEM;
1401
1402 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1403 vid_end, is_member, untagged);
1404 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1405 kfree(spvm_pl);
1406 return err;
1407}
1408
93cd0813
JP		 1409int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1410 u16 vid_end, bool is_member, bool untagged)
1411{
1412 u16 vid, vid_e;
1413 int err;
1414
1415 for (vid = vid_begin; vid <= vid_end;
1416 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1417 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1418 vid_end);
1419
1420 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1421 is_member, untagged);
1422 if (err)
1423 return err;
1424 }
1425
1426 return 0;
1427}
1428
c57529e1 1429static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
7f71eb46 1430{
c57529e1 1431 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
7f71eb46 1432
c57529e1
IS		 1433 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1434 &mlxsw_sp_port->vlans_list, list)
1435 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
7f71eb46
IS		 1436}
1437
31a08a52
IS		 1438static struct mlxsw_sp_port_vlan *
1439mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1440{
1441 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
c57529e1
IS		 1442 bool untagged = vid == 1;
1443 int err;
1444
1445 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1446 if (err)
1447 return ERR_PTR(err);
31a08a52
IS		 1448
1449 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
c57529e1
IS		 1450 if (!mlxsw_sp_port_vlan) {
1451 err = -ENOMEM;
1452 goto err_port_vlan_alloc;
1453 }
31a08a52
IS		 1454
1455 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1456 mlxsw_sp_port_vlan->vid = vid;
1457 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1458
1459 return mlxsw_sp_port_vlan;
c57529e1
IS		 1460
1461err_port_vlan_alloc:
1462 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1463 return ERR_PTR(err);
31a08a52
IS		 1464}
1465
1466static void
1467mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1468{
c57529e1
IS		 1469 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1470 u16 vid = mlxsw_sp_port_vlan->vid;
7cbecf24 1471
31a08a52
IS		 1472 list_del(&mlxsw_sp_port_vlan->list);
1473 kfree(mlxsw_sp_port_vlan);
c57529e1
IS		 1474 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1475}
1476
1477struct mlxsw_sp_port_vlan *
1478mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1479{
1480 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1481
1482 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1483 if (mlxsw_sp_port_vlan)
1484 return mlxsw_sp_port_vlan;
1485
1486 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1487}
1488
1489void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1490{
a1107487
IS		 1491 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1492
c57529e1
IS		 1493 if (mlxsw_sp_port_vlan->bridge_port)
1494 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
a1107487
IS		 1495 else if (fid)
1496 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
c57529e1
IS		 1497
1498 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
31a08a52
IS		 1499}
1500
05978481
IS		 1501static int mlxsw_sp_port_add_vid(struct net_device *dev,
1502 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1503{
1504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
56ade8fe
JP		 1505
1506 /* VLAN 0 is added to HW filter when device goes up, but it is
1507 * reserved in our case, so simply return.
1508 */
1509 if (!vid)
1510 return 0;
1511
c57529e1 1512 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
56ade8fe
JP		 1513}
1514
32d863fb
IS		 1515static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1516 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1517{
1518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
31a08a52 1519 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 1520
1521 /* VLAN 0 is removed from HW filter when device goes down, but
1522 * it is reserved in our case, so simply return.
1523 */
1524 if (!vid)
1525 return 0;
1526
31a08a52 1527 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
c57529e1 1528 if (!mlxsw_sp_port_vlan)
56ade8fe 1529 return 0;
c57529e1 1530 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
31a08a52 1531
56ade8fe
JP		 1532 return 0;
1533}
1534
2bf9a586
IS		 1535static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1536 size_t len)
1537{
1538 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1539 u8 module = mlxsw_sp_port->mapping.module;
1540 u8 width = mlxsw_sp_port->mapping.width;
1541 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1542 int err;
1543
2bf9a586
IS		 1544 if (!mlxsw_sp_port->split)
1545 err = snprintf(name, len, "p%d", module + 1);
1546 else
1547 err = snprintf(name, len, "p%ds%d", module + 1,
1548 lane / width);
1549
1550 if (err >= len)
1551 return -EINVAL;
1552
1553 return 0;
1554}
1555
763b4b70 1556static struct mlxsw_sp_port_mall_tc_entry *
65acb5d0
YG		 1557mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1558 unsigned long cookie) {
763b4b70
YG		 1559 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1560
1561 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1562 if (mall_tc_entry->cookie == cookie)
1563 return mall_tc_entry;
1564
1565 return NULL;
1566}
1567
1568static int
1569mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
65acb5d0 1570 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
763b4b70
YG		 1571 const struct tc_action *a,
1572 bool ingress)
1573{
763b4b70
YG		 1574 enum mlxsw_sp_span_type span_type;
1575 struct mlxsw_sp_port *to_port;
1576 struct net_device *to_dev;
763b4b70 1577
9f8a739e 1578 to_dev = tcf_mirred_dev(a);
763b4b70
YG		 1579 if (!to_dev) {
1580 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1581 return -EINVAL;
1582 }
1583
1584 if (!mlxsw_sp_port_dev_check(to_dev)) {
1585 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
e915ac68 1586 return -EOPNOTSUPP;
763b4b70
YG		 1587 }
1588 to_port = netdev_priv(to_dev);
1589
65acb5d0
YG		 1590 mirror->to_local_port = to_port->local_port;
1591 mirror->ingress = ingress;
763b4b70 1592 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
65acb5d0
YG		 1593 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1594}
763b4b70 1595
65acb5d0
YG		 1596static void
1597mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1598 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1599{
65acb5d0 1600 enum mlxsw_sp_span_type span_type;
65acb5d0 1601
65acb5d0
YG		 1602 span_type = mirror->ingress ?
1603 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
6399ebcc
YM		 1604 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1605 span_type);
763b4b70
YG		 1606}
1607
98d0f7b9
YG		 1608static int
1609mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1610 struct tc_cls_matchall_offload *cls,
1611 const struct tc_action *a,
1612 bool ingress)
1613{
1614 int err;
1615
1616 if (!mlxsw_sp_port->sample)
1617 return -EOPNOTSUPP;
1618 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1619 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1620 return -EEXIST;
1621 }
1622 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1623 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1624 return -EOPNOTSUPP;
1625 }
1626
1627 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1628 tcf_sample_psample_group(a));
1629 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1630 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1631 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1632
1633 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1634 if (err)
1635 goto err_port_sample_set;
1636 return 0;
1637
1638err_port_sample_set:
1639 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1640 return err;
1641}
1642
1643static void
1644mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1645{
1646 if (!mlxsw_sp_port->sample)
1647 return;
1648
1649 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1650 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1651}
1652
763b4b70 1653static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1654 struct tc_cls_matchall_offload *f,
763b4b70
YG		 1655 bool ingress)
1656{
65acb5d0 1657 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
5fd9fc4e 1658 __be16 protocol = f->common.protocol;
763b4b70 1659 const struct tc_action *a;
22dc13c8 1660 LIST_HEAD(actions);
763b4b70
YG		 1661 int err;
1662
9cbf14ed 1663 if (!tcf_exts_has_one_action(f->exts)) {
763b4b70 1664 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
e915ac68 1665 return -EOPNOTSUPP;
763b4b70
YG		 1666 }
1667
65acb5d0
YG		 1668 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1669 if (!mall_tc_entry)
1670 return -ENOMEM;
9cbf14ed 1671 mall_tc_entry->cookie = f->cookie;
65acb5d0 1672
9cbf14ed 1673 tcf_exts_to_list(f->exts, &actions);
65acb5d0 1674 a = list_first_entry(&actions, struct tc_action, list);
86cb13e4 1675
65acb5d0
YG		 1676 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1677 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1678
1679 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1680 mirror = &mall_tc_entry->mirror;
1681 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1682 mirror, a, ingress);
98d0f7b9
YG		 1683 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1684 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
9cbf14ed 1685 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
98d0f7b9 1686 a, ingress);
65acb5d0
YG		 1687 } else {
1688 err = -EOPNOTSUPP;
763b4b70
YG		 1689 }
1690
65acb5d0
YG		 1691 if (err)
1692 goto err_add_action;
1693
1694 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
763b4b70 1695 return 0;
65acb5d0
YG		 1696
1697err_add_action:
1698 kfree(mall_tc_entry);
1699 return err;
763b4b70
YG		 1700}
1701
1702static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1703 struct tc_cls_matchall_offload *f)
763b4b70 1704{
763b4b70 1705 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
763b4b70 1706
65acb5d0 1707 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
9cbf14ed 1708 f->cookie);
763b4b70
YG		 1709 if (!mall_tc_entry) {
1710 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1711 return;
1712 }
65acb5d0 1713 list_del(&mall_tc_entry->list);
763b4b70
YG		 1714
1715 switch (mall_tc_entry->type) {
1716 case MLXSW_SP_PORT_MALL_MIRROR:
65acb5d0
YG		 1717 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1718 &mall_tc_entry->mirror);
763b4b70 1719 break;
98d0f7b9
YG		 1720 case MLXSW_SP_PORT_MALL_SAMPLE:
1721 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1722 break;
763b4b70
YG		 1723 default:
1724 WARN_ON(1);
1725 }
1726
763b4b70
YG		 1727 kfree(mall_tc_entry);
1728}
1729
fd33f1df 1730static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
eb49cfaa
JP		 1731 struct tc_cls_matchall_offload *f,
1732 bool ingress)
fd33f1df 1733{
5fd9fc4e 1734 if (f->common.chain_index)
fd33f1df
JP		 1735 return -EOPNOTSUPP;
1736
1737 switch (f->command) {
1738 case TC_CLSMATCHALL_REPLACE:
5fd9fc4e 1739 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
fd33f1df
JP		 1740 ingress);
1741 case TC_CLSMATCHALL_DESTROY:
1742 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1743 return 0;
1744 default:
1745 return -EOPNOTSUPP;
1746 }
1747}
1748
1749static int
1750mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
eb49cfaa
JP		 1751 struct tc_cls_flower_offload *f,
1752 bool ingress)
763b4b70 1753{
fd33f1df
JP		 1754 switch (f->command) {
1755 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 1756 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
fd33f1df
JP		 1757 case TC_CLSFLOWER_DESTROY:
1758 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
1759 return 0;
1760 case TC_CLSFLOWER_STATS:
1761 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
1762 default:
1763 return -EOPNOTSUPP;
1764 }
1765}
1766
eb49cfaa
JP		 1767static int mlxsw_sp_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1768 void *cb_priv, bool ingress)
1769{
1770 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1771
44ae12a7
JP		 1772 if (!tc_can_offload(mlxsw_sp_port->dev))
1773 return -EOPNOTSUPP;
1774
eb49cfaa
JP		 1775 switch (type) {
1776 case TC_SETUP_CLSMATCHALL:
1777 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1778 ingress);
1779 case TC_SETUP_CLSFLOWER:
1780 return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port, type_data,
1781 ingress);
1782 default:
1783 return -EOPNOTSUPP;
1784 }
1785}
1786
1787static int mlxsw_sp_setup_tc_block_cb_ig(enum tc_setup_type type,
1788 void *type_data, void *cb_priv)
1789{
1790 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, true);
1791}
1792
1793static int mlxsw_sp_setup_tc_block_cb_eg(enum tc_setup_type type,
1794 void *type_data, void *cb_priv)
1795{
1796 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, false);
1797}
1798
1799static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1800 struct tc_block_offload *f)
1801{
1802 tc_setup_cb_t *cb;
1803
1804 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
1805 cb = mlxsw_sp_setup_tc_block_cb_ig;
1806 else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS)
1807 cb = mlxsw_sp_setup_tc_block_cb_eg;
1808 else
1809 return -EOPNOTSUPP;
1810
1811 switch (f->command) {
1812 case TC_BLOCK_BIND:
1813 return tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1814 mlxsw_sp_port);
1815 case TC_BLOCK_UNBIND:
1816 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1817 return 0;
1818 default:
1819 return -EOPNOTSUPP;
1820 }
1821}
1822
fd33f1df 1823static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1824 void *type_data)
fd33f1df
JP		 1825{
1826 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1827
2572ac53 1828 switch (type) {
eb49cfaa
JP		 1829 case TC_SETUP_BLOCK:
1830 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
96f17e07
NF		 1831 case TC_SETUP_QDISC_RED:
1832 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
46a3615b
NF		 1833 case TC_SETUP_QDISC_PRIO:
1834 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
2572ac53
JP		 1835 default:
1836 return -EOPNOTSUPP;
763b4b70 1837 }
763b4b70
YG		 1838}
1839
9454d930
JP		 1840
1841static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1842{
1843 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1844
1845 if (!enable && (mlxsw_sp_port->acl_rule_count ||
1846 !list_empty(&mlxsw_sp_port->mall_tc_list))) {
1847 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1848 return -EINVAL;
1849 }
1850 return 0;
1851}
1852
1853typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1854
1855static int mlxsw_sp_handle_feature(struct net_device *dev,
1856 netdev_features_t wanted_features,
1857 netdev_features_t feature,
1858 mlxsw_sp_feature_handler feature_handler)
1859{
1860 netdev_features_t changes = wanted_features ^ dev->features;
1861 bool enable = !!(wanted_features & feature);
1862 int err;
1863
1864 if (!(changes & feature))
1865 return 0;
1866
1867 err = feature_handler(dev, enable);
1868 if (err) {
1869 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1870 enable ? "Enable" : "Disable", &feature, err);
1871 return err;
1872 }
1873
1874 if (enable)
1875 dev->features |= feature;
1876 else
1877 dev->features &= ~feature;
1878
1879 return 0;
1880}
1881static int mlxsw_sp_set_features(struct net_device *dev,
1882 netdev_features_t features)
1883{
1884 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1885 mlxsw_sp_feature_hw_tc);
1886}
1887
56ade8fe
JP		 1888static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1889 .ndo_open = mlxsw_sp_port_open,
1890 .ndo_stop = mlxsw_sp_port_stop,
1891 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 1892 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 1893 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 1894 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1895 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1896 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 1897 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1898 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 1899 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1900 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
2bf9a586 1901 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
9454d930 1902 .ndo_set_features = mlxsw_sp_set_features,
56ade8fe
JP		 1903};
1904
1905static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1906 struct ethtool_drvinfo *drvinfo)
1907{
1908 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1909 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1910
1911 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1912 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1913 sizeof(drvinfo->version));
1914 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1915 "%d.%d.%d",
1916 mlxsw_sp->bus_info->fw_rev.major,
1917 mlxsw_sp->bus_info->fw_rev.minor,
1918 mlxsw_sp->bus_info->fw_rev.subminor);
1919 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1920 sizeof(drvinfo->bus_info));
1921}
1922
9f7ec052
IS		 1923static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1924 struct ethtool_pauseparam *pause)
1925{
1926 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1927
1928 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1929 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1930}
1931
1932static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1933 struct ethtool_pauseparam *pause)
1934{
1935 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1936
1937 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1938 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1939 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1940
1941 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1942 pfcc_pl);
1943}
1944
1945static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1946 struct ethtool_pauseparam *pause)
1947{
1948 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1949 bool pause_en = pause->tx_pause || pause->rx_pause;
1950 int err;
1951
d81a6bdb
IS		 1952 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1953 netdev_err(dev, "PFC already enabled on port\n");
1954 return -EINVAL;
1955 }
1956
9f7ec052
IS		 1957 if (pause->autoneg) {
1958 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1959 return -EINVAL;
1960 }
1961
1962 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1963 if (err) {
1964 netdev_err(dev, "Failed to configure port's headroom\n");
1965 return err;
1966 }
1967
1968 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1969 if (err) {
1970 netdev_err(dev, "Failed to set PAUSE parameters\n");
1971 goto err_port_pause_configure;
1972 }
1973
1974 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1975 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1976
1977 return 0;
1978
1979err_port_pause_configure:
1980 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1981 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1982 return err;
1983}
1984
56ade8fe
JP		 1985struct mlxsw_sp_port_hw_stats {
1986 char str[ETH_GSTRING_LEN];
412791df 1987 u64 (*getter)(const char *payload);
18281f2d 1988 bool cells_bytes;
56ade8fe
JP		 1989};
1990
7ed674bc 1991static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 1992 {
1993 .str = "a_frames_transmitted_ok",
1994 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1995 },
1996 {
1997 .str = "a_frames_received_ok",
1998 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1999 },
2000 {
2001 .str = "a_frame_check_sequence_errors",
2002 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2003 },
2004 {
2005 .str = "a_alignment_errors",
2006 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2007 },
2008 {
2009 .str = "a_octets_transmitted_ok",
2010 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2011 },
2012 {
2013 .str = "a_octets_received_ok",
2014 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2015 },
2016 {
2017 .str = "a_multicast_frames_xmitted_ok",
2018 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2019 },
2020 {
2021 .str = "a_broadcast_frames_xmitted_ok",
2022 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2023 },
2024 {
2025 .str = "a_multicast_frames_received_ok",
2026 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2027 },
2028 {
2029 .str = "a_broadcast_frames_received_ok",
2030 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2031 },
2032 {
2033 .str = "a_in_range_length_errors",
2034 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2035 },
2036 {
2037 .str = "a_out_of_range_length_field",
2038 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2039 },
2040 {
2041 .str = "a_frame_too_long_errors",
2042 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2043 },
2044 {
2045 .str = "a_symbol_error_during_carrier",
2046 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2047 },
2048 {
2049 .str = "a_mac_control_frames_transmitted",
2050 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2051 },
2052 {
2053 .str = "a_mac_control_frames_received",
2054 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2055 },
2056 {
2057 .str = "a_unsupported_opcodes_received",
2058 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2059 },
2060 {
2061 .str = "a_pause_mac_ctrl_frames_received",
2062 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2063 },
2064 {
2065 .str = "a_pause_mac_ctrl_frames_xmitted",
2066 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2067 },
2068};
2069
2070#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2071
7ed674bc
IS		 2072static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2073 {
2074 .str = "rx_octets_prio",
2075 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2076 },
2077 {
2078 .str = "rx_frames_prio",
2079 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2080 },
2081 {
2082 .str = "tx_octets_prio",
2083 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2084 },
2085 {
2086 .str = "tx_frames_prio",
2087 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2088 },
2089 {
2090 .str = "rx_pause_prio",
2091 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2092 },
2093 {
2094 .str = "rx_pause_duration_prio",
2095 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2096 },
2097 {
2098 .str = "tx_pause_prio",
2099 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2100 },
2101 {
2102 .str = "tx_pause_duration_prio",
2103 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2104 },
2105};
2106
2107#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2108
df4750e8
IS		 2109static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2110 {
2111 .str = "tc_transmit_queue_tc",
18281f2d
IS		 2112 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2113 .cells_bytes = true,
df4750e8
IS		 2114 },
2115 {
2116 .str = "tc_no_buffer_discard_uc_tc",
2117 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2118 },
2119};
2120
2121#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2122
7ed674bc 2123#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 2124 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2125 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 2126 IEEE_8021QAZ_MAX_TCS)
2127
2128static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2129{
2130 int i;
2131
2132 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2133 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2134 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2135 *p += ETH_GSTRING_LEN;
2136 }
2137}
2138
df4750e8
IS		 2139static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2140{
2141 int i;
2142
2143 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2144 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2145 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2146 *p += ETH_GSTRING_LEN;
2147 }
2148}
2149
56ade8fe
JP		 2150static void mlxsw_sp_port_get_strings(struct net_device *dev,
2151 u32 stringset, u8 *data)
2152{
2153 u8 *p = data;
2154 int i;
2155
2156 switch (stringset) {
2157 case ETH_SS_STATS:
2158 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2159 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2160 ETH_GSTRING_LEN);
2161 p += ETH_GSTRING_LEN;
2162 }
7ed674bc
IS		 2163
2164 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2165 mlxsw_sp_port_get_prio_strings(&p, i);
2166
df4750e8
IS		 2167 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2168 mlxsw_sp_port_get_tc_strings(&p, i);
2169
56ade8fe
JP		 2170 break;
2171 }
2172}
2173
3a66ee38
IS		 2174static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2175 enum ethtool_phys_id_state state)
2176{
2177 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2179 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2180 bool active;
2181
2182 switch (state) {
2183 case ETHTOOL_ID_ACTIVE:
2184 active = true;
2185 break;
2186 case ETHTOOL_ID_INACTIVE:
2187 active = false;
2188 break;
2189 default:
2190 return -EOPNOTSUPP;
2191 }
2192
2193 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2194 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2195}
2196
7ed674bc
IS		 2197static int
2198mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2199 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2200{
2201 switch (grp) {
2202 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2203 *p_hw_stats = mlxsw_sp_port_hw_stats;
2204 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2205 break;
2206 case MLXSW_REG_PPCNT_PRIO_CNT:
2207 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2208 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2209 break;
df4750e8
IS		 2210 case MLXSW_REG_PPCNT_TC_CNT:
2211 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2212 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2213 break;
7ed674bc
IS		 2214 default:
2215 WARN_ON(1);
e915ac68 2216 return -EOPNOTSUPP;
7ed674bc
IS		 2217 }
2218 return 0;
2219}
2220
2221static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2222 enum mlxsw_reg_ppcnt_grp grp, int prio,
2223 u64 *data, int data_index)
56ade8fe 2224{
18281f2d
IS		 2225 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2226 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
7ed674bc 2227 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 2228 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 2229 int i, len;
56ade8fe
JP		 2230 int err;
2231
7ed674bc
IS		 2232 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2233 if (err)
2234 return;
fc1bbb0f 2235 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
18281f2d 2236 for (i = 0; i < len; i++) {
faac0ff0 2237 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
18281f2d
IS		 2238 if (!hw_stats[i].cells_bytes)
2239 continue;
2240 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2241 data[data_index + i]);
2242 }
7ed674bc
IS		 2243}
2244
2245static void mlxsw_sp_port_get_stats(struct net_device *dev,
2246 struct ethtool_stats *stats, u64 *data)
2247{
2248 int i, data_index = 0;
2249
2250 /* IEEE 802.3 Counters */
2251 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2252 data, data_index);
2253 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2254
2255 /* Per-Priority Counters */
2256 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2257 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2258 data, data_index);
2259 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2260 }
df4750e8
IS		 2261
2262 /* Per-TC Counters */
2263 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2264 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2265 data, data_index);
2266 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2267 }
56ade8fe
JP		 2268}
2269
2270static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2271{
2272 switch (sset) {
2273 case ETH_SS_STATS:
7ed674bc 2274 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 2275 default:
2276 return -EOPNOTSUPP;
2277 }
2278}
2279
2280struct mlxsw_sp_port_link_mode {
b9d66a36 2281 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 2282 u32 mask;
56ade8fe
JP		 2283 u32 speed;
2284};
2285
2286static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2287 {
2288 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 2289 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2290 .speed = SPEED_100,
56ade8fe
JP		 2291 },
2292 {
2293 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2294 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 2295 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2296 .speed = SPEED_1000,
56ade8fe
JP		 2297 },
2298 {
2299 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 2300 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2301 .speed = SPEED_10000,
56ade8fe
JP		 2302 },
2303 {
2304 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2305 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 2306 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2307 .speed = SPEED_10000,
56ade8fe
JP		 2308 },
2309 {
2310 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2311 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2312 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2313 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 2314 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2315 .speed = SPEED_10000,
56ade8fe
JP		 2316 },
2317 {
2318 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 2319 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2320 .speed = SPEED_20000,
56ade8fe
JP		 2321 },
2322 {
2323 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 2324 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2325 .speed = SPEED_40000,
56ade8fe
JP		 2326 },
2327 {
2328 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 2329 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2330 .speed = SPEED_40000,
56ade8fe
JP		 2331 },
2332 {
2333 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 2334 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2335 .speed = SPEED_40000,
56ade8fe
JP		 2336 },
2337 {
2338 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 2339 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2340 .speed = SPEED_40000,
2341 },
2342 {
2343 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2344 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2345 .speed = SPEED_25000,
2346 },
2347 {
2348 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2349 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2350 .speed = SPEED_25000,
2351 },
2352 {
2353 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2354 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2355 .speed = SPEED_25000,
56ade8fe
JP		 2356 },
2357 {
b9d66a36
IS		 2358 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2359 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2360 .speed = SPEED_25000,
56ade8fe
JP		 2361 },
2362 {
b9d66a36
IS		 2363 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2364 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2365 .speed = SPEED_50000,
2366 },
2367 {
2368 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2369 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2370 .speed = SPEED_50000,
2371 },
2372 {
2373 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2374 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2375 .speed = SPEED_50000,
56ade8fe
JP		 2376 },
2377 {
2378 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 2379 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2380 .speed = SPEED_56000,
56ade8fe
JP		 2381 },
2382 {
b9d66a36
IS		 2383 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2384 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2385 .speed = SPEED_56000,
2386 },
2387 {
2388 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2389 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2390 .speed = SPEED_56000,
2391 },
2392 {
2393 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2394 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2395 .speed = SPEED_56000,
2396 },
2397 {
2398 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2399 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2400 .speed = SPEED_100000,
2401 },
2402 {
2403 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2404 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2405 .speed = SPEED_100000,
2406 },
2407 {
2408 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2409 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2410 .speed = SPEED_100000,
2411 },
2412 {
2413 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2414 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2415 .speed = SPEED_100000,
56ade8fe
JP		 2416 },
2417};
2418
2419#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2420
b9d66a36
IS		 2421static void
2422mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2423 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2424{
2425 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2426 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2427 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2428 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2429 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2430 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 2431 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 2432
2433 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2434 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2435 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2436 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2437 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 2438 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 2439}
2440
b9d66a36 2441static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 2442{
56ade8fe
JP		 2443 int i;
2444
2445 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2446 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 2447 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2448 mode);
56ade8fe 2449 }
56ade8fe
JP		 2450}
2451
2452static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 2453 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2454{
2455 u32 speed = SPEED_UNKNOWN;
2456 u8 duplex = DUPLEX_UNKNOWN;
2457 int i;
2458
2459 if (!carrier_ok)
2460 goto out;
2461
2462 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2463 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2464 speed = mlxsw_sp_port_link_mode[i].speed;
2465 duplex = DUPLEX_FULL;
2466 break;
2467 }
2468 }
2469out:
b9d66a36
IS		 2470 cmd->base.speed = speed;
2471 cmd->base.duplex = duplex;
56ade8fe
JP		 2472}
2473
2474static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2475{
2476 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2477 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2478 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2479 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2480 return PORT_FIBRE;
2481
2482 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2483 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2484 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2485 return PORT_DA;
2486
2487 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2488 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2489 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2490 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2491 return PORT_NONE;
2492
2493 return PORT_OTHER;
2494}
2495
b9d66a36
IS		 2496static u32
2497mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2498{
2499 u32 ptys_proto = 0;
2500 int i;
2501
2502 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 2503 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2504 cmd->link_modes.advertising))
56ade8fe
JP		 2505 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2506 }
2507 return ptys_proto;
2508}
2509
2510static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2511{
2512 u32 ptys_proto = 0;
2513 int i;
2514
2515 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2516 if (speed == mlxsw_sp_port_link_mode[i].speed)
2517 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2518 }
2519 return ptys_proto;
2520}
2521
18f1e70c
IS		 2522static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2523{
2524 u32 ptys_proto = 0;
2525 int i;
2526
2527 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2528 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2529 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2530 }
2531 return ptys_proto;
2532}
2533
b9d66a36
IS		 2534static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2535 struct ethtool_link_ksettings *cmd)
2536{
2537 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2538 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2539 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2540
2541 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2542 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2543}
2544
2545static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2546 struct ethtool_link_ksettings *cmd)
56ade8fe 2547{
b9d66a36
IS		 2548 if (!autoneg)
2549 return;
2550
2551 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2552 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2553}
2554
2555static void
2556mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2557 struct ethtool_link_ksettings *cmd)
2558{
2559 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2560 return;
2561
2562 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2563 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2564}
2565
2566static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2567 struct ethtool_link_ksettings *cmd)
2568{
2569 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 2570 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2571 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2572 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2573 u8 autoneg_status;
0c83f88c 2574 bool autoneg;
56ade8fe
JP		 2575 int err;
2576
b9d66a36 2577 autoneg = mlxsw_sp_port->link.autoneg;
401c8b4e 2578 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
b9d66a36
IS		 2579 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2580 if (err)
2581 return err;
401c8b4e
ER		 2582 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2583 &eth_proto_oper);
b9d66a36
IS		 2584
2585 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2586
b9d66a36
IS		 2587 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2588
2589 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2590 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2591 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2592
2593 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2594 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2595 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2596 cmd);
2597
2598 return 0;
2599}
2600
2601static int
2602mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2603 const struct ethtool_link_ksettings *cmd)
2604{
2605 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2606 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2607 char ptys_pl[MLXSW_REG_PTYS_LEN];
2608 u32 eth_proto_cap, eth_proto_new;
2609 bool autoneg;
2610 int err;
56ade8fe 2611
401c8b4e 2612 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
56ade8fe 2613 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2614 if (err)
56ade8fe 2615 return err;
401c8b4e 2616 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
b9d66a36
IS		 2617
2618 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2619 eth_proto_new = autoneg ?
2620 mlxsw_sp_to_ptys_advert_link(cmd) :
2621 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2622
2623 eth_proto_new = eth_proto_new & eth_proto_cap;
2624 if (!eth_proto_new) {
b9d66a36 2625 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2626 return -EINVAL;
2627 }
56ade8fe 2628
401c8b4e
ER		 2629 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2630 eth_proto_new);
56ade8fe 2631 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2632 if (err)
56ade8fe 2633 return err;
56ade8fe 2634
6277d46b 2635 if (!netif_running(dev))
56ade8fe
JP		 2636 return 0;
2637
0c83f88c
IS		 2638 mlxsw_sp_port->link.autoneg = autoneg;
2639
b9d66a36
IS		 2640 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2641 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2642
2643 return 0;
2644}
2645
ce6ef68f
YG		 2646static int mlxsw_sp_flash_device(struct net_device *dev,
2647 struct ethtool_flash *flash)
2648{
2649 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2650 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2651 const struct firmware *firmware;
2652 int err;
2653
2654 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2655 return -EOPNOTSUPP;
2656
2657 dev_hold(dev);
2658 rtnl_unlock();
2659
2660 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2661 if (err)
2662 goto out;
2663 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2664 release_firmware(firmware);
2665out:
2666 rtnl_lock();
2667 dev_put(dev);
2668 return err;
2669}
2670
4400081b
AS		 2671#define MLXSW_SP_I2C_ADDR_LOW 0x50
2672#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2673#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2ea10903
AS		 2674
2675static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2676 u16 offset, u16 size, void *data,
2677 unsigned int *p_read_size)
2678{
2679 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2680 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2681 char mcia_pl[MLXSW_REG_MCIA_LEN];
4400081b 2682 u16 i2c_addr;
2ea10903
AS		 2683 int status;
2684 int err;
2685
2686 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
4400081b
AS		 2687
2688 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2689 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2690 /* Cross pages read, read until offset 256 in low page */
2691 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2692
2693 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2694 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2695 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2696 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2697 }
2698
2ea10903 2699 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
4400081b 2700 0, 0, offset, size, i2c_addr);
2ea10903
AS		 2701
2702 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2703 if (err)
2704 return err;
2705
2706 status = mlxsw_reg_mcia_status_get(mcia_pl);
2707 if (status)
2708 return -EIO;
2709
2710 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2711 memcpy(data, eeprom_tmp, size);
2712 *p_read_size = size;
2713
2714 return 0;
2715}
2716
2717enum mlxsw_sp_eeprom_module_info_rev_id {
2718 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2719 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2720 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2721};
2722
2723enum mlxsw_sp_eeprom_module_info_id {
2724 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2725 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2726 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2727 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2728};
2729
2730enum mlxsw_sp_eeprom_module_info {
2731 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2732 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2733 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2734};
2735
2736static int mlxsw_sp_get_module_info(struct net_device *netdev,
2737 struct ethtool_modinfo *modinfo)
2738{
2739 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2740 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2741 u8 module_rev_id, module_id;
2742 unsigned int read_size;
2743 int err;
2744
2745 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2746 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2747 module_info, &read_size);
2748 if (err)
2749 return err;
2750
2751 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2752 return -EIO;
2753
2754 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2755 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2756
2757 switch (module_id) {
2758 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2759 modinfo->type = ETH_MODULE_SFF_8436;
2760 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2761 break;
2762 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2763 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2764 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2765 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2766 modinfo->type = ETH_MODULE_SFF_8636;
2767 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2768 } else {
2769 modinfo->type = ETH_MODULE_SFF_8436;
2770 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2771 }
2772 break;
2773 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2774 modinfo->type = ETH_MODULE_SFF_8472;
2775 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2776 break;
2777 default:
2778 return -EINVAL;
2779 }
2780
2781 return 0;
2782}
2783
2784static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2785 struct ethtool_eeprom *ee,
2786 u8 *data)
2787{
2788 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2789 int offset = ee->offset;
2790 unsigned int read_size;
2791 int i = 0;
2792 int err;
2793
2794 if (!ee->len)
2795 return -EINVAL;
2796
2797 memset(data, 0, ee->len);
2798
2799 while (i < ee->len) {
2800 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2801 ee->len - i, data + i,
2802 &read_size);
2803 if (err) {
2804 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2805 return err;
2806 }
2807
2808 i += read_size;
2809 offset += read_size;
2810 }
2811
2812 return 0;
2813}
2814
56ade8fe
JP		 2815static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2816 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2817 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2818 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2819 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2820 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2821 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2822 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2823 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2824 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2825 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
ce6ef68f 2826 .flash_device = mlxsw_sp_flash_device,
2ea10903
AS		 2827 .get_module_info = mlxsw_sp_get_module_info,
2828 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
56ade8fe
JP		 2829};
2830
18f1e70c
IS		 2831static int
2832mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2833{
2834 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2835 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2836 char ptys_pl[MLXSW_REG_PTYS_LEN];
2837 u32 eth_proto_admin;
2838
2839 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
401c8b4e
ER		 2840 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2841 eth_proto_admin);
18f1e70c
IS		 2842 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2843}
2844
8e8dfe9f
IS		 2845int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2846 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2847 bool dwrr, u8 dwrr_weight)
90183b98
IS		 2848{
2849 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2850 char qeec_pl[MLXSW_REG_QEEC_LEN];
2851
2852 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2853 next_index);
2854 mlxsw_reg_qeec_de_set(qeec_pl, true);
2855 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2856 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2857 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2858}
2859
cc7cf517
IS		 2860int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2861 enum mlxsw_reg_qeec_hr hr, u8 index,
2862 u8 next_index, u32 maxrate)
90183b98
IS		 2863{
2864 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2865 char qeec_pl[MLXSW_REG_QEEC_LEN];
2866
2867 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2868 next_index);
2869 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2870 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2871 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2872}
2873
8e8dfe9f
IS		 2874int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2875 u8 switch_prio, u8 tclass)
90183b98
IS		 2876{
2877 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2878 char qtct_pl[MLXSW_REG_QTCT_LEN];
2879
2880 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2881 tclass);
2882 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2883}
2884
2885static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2886{
2887 int err, i;
2888
2889 /* Setup the elements hierarcy, so that each TC is linked to
2890 * one subgroup, which are all member in the same group.
2891 */
2892 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2893 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2894 0);
2895 if (err)
2896 return err;
2897 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2898 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2899 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2900 0, false, 0);
2901 if (err)
2902 return err;
2903 }
2904 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2905 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2906 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2907 false, 0);
2908 if (err)
2909 return err;
2910 }
2911
2912 /* Make sure the max shaper is disabled in all hierarcies that
2913 * support it.
2914 */
2915 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2916 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2917 MLXSW_REG_QEEC_MAS_DIS);
2918 if (err)
2919 return err;
2920 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2921 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2922 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2923 i, 0,
2924 MLXSW_REG_QEEC_MAS_DIS);
2925 if (err)
2926 return err;
2927 }
2928 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2929 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2930 MLXSW_REG_QEEC_HIERARCY_TC,
2931 i, i,
2932 MLXSW_REG_QEEC_MAS_DIS);
2933 if (err)
2934 return err;
2935 }
2936
2937 /* Map all priorities to traffic class 0. */
2938 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2939 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2940 if (err)
2941 return err;
2942 }
2943
2944 return 0;
2945}
2946
5b153859
IS		 2947static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2948 bool split, u8 module, u8 width, u8 lane)
56ade8fe 2949{
c57529e1 2950 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 2951 struct mlxsw_sp_port *mlxsw_sp_port;
2952 struct net_device *dev;
56ade8fe
JP		 2953 int err;
2954
5b153859
IS		 2955 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2956 if (err) {
2957 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2958 local_port);
2959 return err;
2960 }
2961
56ade8fe 2962 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
5b153859
IS		 2963 if (!dev) {
2964 err = -ENOMEM;
2965 goto err_alloc_etherdev;
2966 }
f20a91f1 2967 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 2968 mlxsw_sp_port = netdev_priv(dev);
2969 mlxsw_sp_port->dev = dev;
2970 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2971 mlxsw_sp_port->local_port = local_port;
c57529e1 2972 mlxsw_sp_port->pvid = 1;
18f1e70c 2973 mlxsw_sp_port->split = split;
d664b41e
IS		 2974 mlxsw_sp_port->mapping.module = module;
2975 mlxsw_sp_port->mapping.width = width;
2976 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 2977 mlxsw_sp_port->link.autoneg = 1;
31a08a52 2978 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
763b4b70 2979 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 2980
2981 mlxsw_sp_port->pcpu_stats =
2982 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2983 if (!mlxsw_sp_port->pcpu_stats) {
2984 err = -ENOMEM;
2985 goto err_alloc_stats;
2986 }
2987
98d0f7b9
YG		 2988 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2989 GFP_KERNEL);
2990 if (!mlxsw_sp_port->sample) {
2991 err = -ENOMEM;
2992 goto err_alloc_sample;
2993 }
2994
9deef43d 2995 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 2996 &update_stats_cache);
2997
56ade8fe
JP		 2998 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2999 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3000
2e915e0b 3001 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
5b153859
IS		 3002 if (err) {
3003 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3004 mlxsw_sp_port->local_port);
3005 goto err_port_module_map;
3006 }
3007
3247ff2b
IS		 3008 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3009 if (err) {
3010 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3011 mlxsw_sp_port->local_port);
3012 goto err_port_swid_set;
3013 }
3014
56ade8fe
JP		 3015 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3016 if (err) {
3017 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3018 mlxsw_sp_port->local_port);
3019 goto err_dev_addr_init;
3020 }
3021
3022 netif_carrier_off(dev);
3023
3024 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 3025 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3026 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 3027
d894be57
JW		 3028 dev->min_mtu = 0;
3029 dev->max_mtu = ETH_MAX_MTU;
3030
56ade8fe
JP		 3031 /* Each packet needs to have a Tx header (metadata) on top all other
3032 * headers.
3033 */
feb7d387 3034 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 3035
56ade8fe
JP		 3036 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3037 if (err) {
3038 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3039 mlxsw_sp_port->local_port);
3040 goto err_port_system_port_mapping_set;
3041 }
3042
18f1e70c
IS		 3043 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3044 if (err) {
3045 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3046 mlxsw_sp_port->local_port);
3047 goto err_port_speed_by_width_set;
3048 }
3049
56ade8fe
JP		 3050 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3051 if (err) {
3052 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3053 mlxsw_sp_port->local_port);
3054 goto err_port_mtu_set;
3055 }
3056
3057 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3058 if (err)
3059 goto err_port_admin_status_set;
3060
3061 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3062 if (err) {
3063 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3064 mlxsw_sp_port->local_port);
3065 goto err_port_buffers_init;
3066 }
3067
90183b98
IS		 3068 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3069 if (err) {
3070 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3071 mlxsw_sp_port->local_port);
3072 goto err_port_ets_init;
3073 }
3074
f00817df
IS		 3075 /* ETS and buffers must be initialized before DCB. */
3076 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3077 if (err) {
3078 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3079 mlxsw_sp_port->local_port);
3080 goto err_port_dcb_init;
3081 }
3082
a1107487 3083 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
45a4a16c 3084 if (err) {
a1107487 3085 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
45a4a16c 3086 mlxsw_sp_port->local_port);
a1107487 3087 goto err_port_fids_init;
45a4a16c
IS		 3088 }
3089
371b437a
NF		 3090 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3091 if (err) {
3092 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3093 mlxsw_sp_port->local_port);
3094 goto err_port_qdiscs_init;
3095 }
3096
c57529e1
IS		 3097 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3098 if (IS_ERR(mlxsw_sp_port_vlan)) {
3099 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
05978481 3100 mlxsw_sp_port->local_port);
d86fd113 3101 err = PTR_ERR(mlxsw_sp_port_vlan);
c57529e1 3102 goto err_port_vlan_get;
05978481
IS		 3103 }
3104
56ade8fe 3105 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 3106 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 3107 err = register_netdev(dev);
3108 if (err) {
3109 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3110 mlxsw_sp_port->local_port);
3111 goto err_register_netdev;
3112 }
3113
d808c7e4
ER		 3114 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3115 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3116 module);
9deef43d 3117 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
56ade8fe
JP		 3118 return 0;
3119
56ade8fe 3120err_register_netdev:
2f25844c 3121 mlxsw_sp->ports[local_port] = NULL;
0583272d 3122 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1
IS		 3123 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3124err_port_vlan_get:
371b437a
NF		 3125 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3126err_port_qdiscs_init:
a1107487
IS		 3127 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3128err_port_fids_init:
4de34eb5 3129 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 3130err_port_dcb_init:
90183b98 3131err_port_ets_init:
56ade8fe
JP		 3132err_port_buffers_init:
3133err_port_admin_status_set:
3134err_port_mtu_set:
18f1e70c 3135err_port_speed_by_width_set:
56ade8fe 3136err_port_system_port_mapping_set:
56ade8fe 3137err_dev_addr_init:
3247ff2b
IS		 3138 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3139err_port_swid_set:
2e915e0b 3140 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
5b153859 3141err_port_module_map:
98d0f7b9
YG		 3142 kfree(mlxsw_sp_port->sample);
3143err_alloc_sample:
56ade8fe
JP		 3144 free_percpu(mlxsw_sp_port->pcpu_stats);
3145err_alloc_stats:
3146 free_netdev(dev);
5b153859 3147err_alloc_etherdev:
67963a33
JP		 3148 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3149 return err;
3150}
3151
5b153859 3152static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
56ade8fe
JP		 3153{
3154 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3155
9deef43d 3156 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
67963a33 3157 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
56ade8fe 3158 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 3159 mlxsw_sp->ports[local_port] = NULL;
0583272d 3160 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1 3161 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
371b437a 3162 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
a1107487 3163 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
f00817df 3164 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8 3165 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2e915e0b 3166 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
98d0f7b9 3167 kfree(mlxsw_sp_port->sample);
136f1445 3168 free_percpu(mlxsw_sp_port->pcpu_stats);
31a08a52 3169 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
56ade8fe 3170 free_netdev(mlxsw_sp_port->dev);
67963a33
JP		 3171 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3172}
3173
f83e2102
JP		 3174static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3175{
3176 return mlxsw_sp->ports[local_port] != NULL;
3177}
3178
56ade8fe
JP		 3179static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3180{
3181 int i;
3182
5ec2ee7d 3183 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
f83e2102
JP		 3184 if (mlxsw_sp_port_created(mlxsw_sp, i))
3185 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d 3186 kfree(mlxsw_sp->port_to_module);
56ade8fe
JP		 3187 kfree(mlxsw_sp->ports);
3188}
3189
3190static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3191{
5ec2ee7d 3192 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
d664b41e 3193 u8 module, width, lane;
56ade8fe
JP		 3194 size_t alloc_size;
3195 int i;
3196 int err;
3197
5ec2ee7d 3198 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
56ade8fe
JP		 3199 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3200 if (!mlxsw_sp->ports)
3201 return -ENOMEM;
3202
bf4e9f24
IS		 3203 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3204 GFP_KERNEL);
5ec2ee7d
IS		 3205 if (!mlxsw_sp->port_to_module) {
3206 err = -ENOMEM;
3207 goto err_port_to_module_alloc;
3208 }
3209
3210 for (i = 1; i < max_ports; i++) {
bf4e9f24
IS		 3211 /* Mark as invalid */
3212 mlxsw_sp->port_to_module[i] = -1;
3213
558c2d5e 3214 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 3215 &width, &lane);
558c2d5e
IS		 3216 if (err)
3217 goto err_port_module_info_get;
3218 if (!width)
3219 continue;
3220 mlxsw_sp->port_to_module[i] = module;
67963a33
JP		 3221 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3222 module, width, lane);
56ade8fe
JP		 3223 if (err)
3224 goto err_port_create;
3225 }
3226 return 0;
3227
3228err_port_create:
558c2d5e 3229err_port_module_info_get:
56ade8fe 3230 for (i--; i >= 1; i--)
f83e2102
JP		 3231 if (mlxsw_sp_port_created(mlxsw_sp, i))
3232 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d
IS		 3233 kfree(mlxsw_sp->port_to_module);
3234err_port_to_module_alloc:
56ade8fe
JP		 3235 kfree(mlxsw_sp->ports);
3236 return err;
3237}
3238
18f1e70c
IS		 3239static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3240{
3241 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3242
3243 return local_port - offset;
3244}
3245
be94535f
IS		 3246static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3247 u8 module, unsigned int count)
3248{
3249 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3250 int err, i;
3251
be94535f
IS		 3252 for (i = 0; i < count; i++) {
3253 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 3254 module, width, i * width);
be94535f
IS		 3255 if (err)
3256 goto err_port_create;
3257 }
3258
3259 return 0;
3260
3261err_port_create:
3262 for (i--; i >= 0; i--)
f83e2102
JP		 3263 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3264 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
be94535f
IS		 3265 return err;
3266}
3267
3268static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3269 u8 base_port, unsigned int count)
3270{
3271 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3272 int i;
3273
3274 /* Split by four means we need to re-create two ports, otherwise
3275 * only one.
3276 */
3277 count = count / 2;
3278
be94535f
IS		 3279 for (i = 0; i < count; i++) {
3280 local_port = base_port + i * 2;
bf4e9f24
IS		 3281 if (mlxsw_sp->port_to_module[local_port] < 0)
3282 continue;
be94535f
IS		 3283 module = mlxsw_sp->port_to_module[local_port];
3284
3285 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 3286 width, 0);
be94535f
IS		 3287 }
3288}
3289
b2f10571
JP		 3290static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3291 unsigned int count)
18f1e70c 3292{
b2f10571 3293 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3294 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 3295 u8 module, cur_width, base_port;
3296 int i;
3297 int err;
3298
3299 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3300 if (!mlxsw_sp_port) {
3301 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3302 local_port);
3303 return -EINVAL;
3304 }
3305
d664b41e
IS		 3306 module = mlxsw_sp_port->mapping.module;
3307 cur_width = mlxsw_sp_port->mapping.width;
3308
18f1e70c
IS		 3309 if (count != 2 && count != 4) {
3310 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3311 return -EINVAL;
3312 }
3313
18f1e70c
IS		 3314 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3315 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3316 return -EINVAL;
3317 }
3318
3319 /* Make sure we have enough slave (even) ports for the split. */
3320 if (count == 2) {
3321 base_port = local_port;
3322 if (mlxsw_sp->ports[base_port + 1]) {
3323 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3324 return -EINVAL;
3325 }
3326 } else {
3327 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3328 if (mlxsw_sp->ports[base_port + 1] ||
3329 mlxsw_sp->ports[base_port + 3]) {
3330 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3331 return -EINVAL;
3332 }
3333 }
3334
3335 for (i = 0; i < count; i++)
f83e2102
JP		 3336 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3337 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3338
be94535f
IS		 3339 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3340 if (err) {
3341 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3342 goto err_port_split_create;
18f1e70c
IS		 3343 }
3344
3345 return 0;
3346
be94535f
IS		 3347err_port_split_create:
3348 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3349 return err;
3350}
3351
b2f10571 3352static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 3353{
b2f10571 3354 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3355 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 3356 u8 cur_width, base_port;
18f1e70c
IS		 3357 unsigned int count;
3358 int i;
18f1e70c
IS		 3359
3360 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3361 if (!mlxsw_sp_port) {
3362 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3363 local_port);
3364 return -EINVAL;
3365 }
3366
3367 if (!mlxsw_sp_port->split) {
3368 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3369 return -EINVAL;
3370 }
3371
d664b41e 3372 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 3373 count = cur_width == 1 ? 4 : 2;
3374
3375 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3376
3377 /* Determine which ports to remove. */
3378 if (count == 2 && local_port >= base_port + 2)
3379 base_port = base_port + 2;
3380
3381 for (i = 0; i < count; i++)
f83e2102
JP		 3382 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3383 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3384
be94535f 3385 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3386
3387 return 0;
3388}
3389
56ade8fe
JP		 3390static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3391 char *pude_pl, void *priv)
3392{
3393 struct mlxsw_sp *mlxsw_sp = priv;
3394 struct mlxsw_sp_port *mlxsw_sp_port;
3395 enum mlxsw_reg_pude_oper_status status;
3396 u8 local_port;
3397
3398 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3399 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 3400 if (!mlxsw_sp_port)
56ade8fe 3401 return;
56ade8fe
JP		 3402
3403 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3404 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3405 netdev_info(mlxsw_sp_port->dev, "link up\n");
3406 netif_carrier_on(mlxsw_sp_port->dev);
3407 } else {
3408 netdev_info(mlxsw_sp_port->dev, "link down\n");
3409 netif_carrier_off(mlxsw_sp_port->dev);
3410 }
3411}
3412
14eeda99
NF		 3413static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3414 u8 local_port, void *priv)
56ade8fe
JP		 3415{
3416 struct mlxsw_sp *mlxsw_sp = priv;
3417 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3418 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3419
3420 if (unlikely(!mlxsw_sp_port)) {
3421 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3422 local_port);
3423 return;
3424 }
3425
3426 skb->dev = mlxsw_sp_port->dev;
3427
3428 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3429 u64_stats_update_begin(&pcpu_stats->syncp);
3430 pcpu_stats->rx_packets++;
3431 pcpu_stats->rx_bytes += skb->len;
3432 u64_stats_update_end(&pcpu_stats->syncp);
3433
3434 skb->protocol = eth_type_trans(skb, skb->dev);
3435 netif_receive_skb(skb);
3436}
3437
1c6c6d22
IS		 3438static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3439 void *priv)
3440{
3441 skb->offload_fwd_mark = 1;
14eeda99 3442 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
1c6c6d22
IS		 3443}
3444
a0040c8c
YG		 3445static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3446 u8 local_port, void *priv)
3447{
3448 skb->offload_mr_fwd_mark = 1;
3449 skb->offload_fwd_mark = 1;
3450 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3451}
3452
98d0f7b9
YG		 3453static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3454 void *priv)
3455{
3456 struct mlxsw_sp *mlxsw_sp = priv;
3457 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3458 struct psample_group *psample_group;
3459 u32 size;
3460
3461 if (unlikely(!mlxsw_sp_port)) {
3462 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3463 local_port);
3464 goto out;
3465 }
3466 if (unlikely(!mlxsw_sp_port->sample)) {
3467 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3468 local_port);
3469 goto out;
3470 }
3471
3472 size = mlxsw_sp_port->sample->truncate ?
3473 mlxsw_sp_port->sample->trunc_size : skb->len;
3474
3475 rcu_read_lock();
3476 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3477 if (!psample_group)
3478 goto out_unlock;
3479 psample_sample_packet(psample_group, skb, size,
3480 mlxsw_sp_port->dev->ifindex, 0,
3481 mlxsw_sp_port->sample->rate);
3482out_unlock:
3483 rcu_read_unlock();
3484out:
3485 consume_skb(skb);
3486}
3487
117b0dad 3488#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
0fb78a4e 3489 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
117b0dad 3490 _is_ctrl, SP_##_trap_group, DISCARD)
14eeda99 3491
117b0dad 3492#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
14eeda99 3493 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
117b0dad
NF		 3494 _is_ctrl, SP_##_trap_group, DISCARD)
3495
a0040c8c
YG		 3496#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3497 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3498 _is_ctrl, SP_##_trap_group, DISCARD)
3499
117b0dad
NF		 3500#define MLXSW_SP_EVENTL(_func, _trap_id) \
3501 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
93393b33 3502
4544913e
NF		 3503static const struct mlxsw_listener mlxsw_sp_listener[] = {
3504 /* Events */
117b0dad 3505 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
ee4a60d8 3506 /* L2 traps */
117b0dad
NF		 3507 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3508 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3509 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3510 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3511 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3512 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3513 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3514 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3515 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3516 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3517 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
9d41accc 3518 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
588823f9
AS		 3519 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3520 false),
3521 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3522 false),
3523 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3524 false),
3525 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3526 false),
93393b33 3527 /* L3 traps */
0fcc4847
IS		 3528 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3529 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3530 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
0fcc4847 3531 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
8d54814e
AS		 3532 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3533 false),
3534 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3535 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3536 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3537 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3538 false),
3539 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3540 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3541 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
0fcc4847 3542 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
8d54814e
AS		 3543 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3544 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3545 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3546 false),
3547 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3548 false),
3549 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3550 false),
3551 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3552 false),
3553 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3554 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3555 false),
3556 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3557 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
7607dd35 3558 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
8d54814e 3559 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
86484de2 3560 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
98d0f7b9
YG		 3561 /* PKT Sample trap */
3562 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
0db7b386
JP		 3563 false, SP_IP2ME, DISCARD),
3564 /* ACL trap */
3565 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
b48cfc80
YG		 3566 /* Multicast Router Traps */
3567 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3568 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3569 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
a0040c8c 3570 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
56ade8fe
JP		 3571};
3572
9148e7cf
NF		 3573static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3574{
3575 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3576 enum mlxsw_reg_qpcr_ir_units ir_units;
3577 int max_cpu_policers;
3578 bool is_bytes;
3579 u8 burst_size;
3580 u32 rate;
3581 int i, err;
3582
3583 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3584 return -EIO;
3585
3586 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3587
3588 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3589 for (i = 0; i < max_cpu_policers; i++) {
3590 is_bytes = false;
3591 switch (i) {
3592 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3593 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3594 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3595 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80
YG		 3596 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3597 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
9148e7cf
NF		 3598 rate = 128;
3599 burst_size = 7;
3600 break;
3601 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
588823f9 3602 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
9148e7cf
NF		 3603 rate = 16 * 1024;
3604 burst_size = 10;
3605 break;
8d54814e 3606 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
9148e7cf
NF		 3607 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3608 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
8d54814e 3609 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
9148e7cf
NF		 3610 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3611 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
8d54814e 3612 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3613 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
9148e7cf
NF		 3614 rate = 1024;
3615 burst_size = 7;
3616 break;
3617 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3618 is_bytes = true;
3619 rate = 4 * 1024;
3620 burst_size = 4;
3621 break;
3622 default:
3623 continue;
3624 }
3625
3626 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3627 burst_size);
3628 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3629 if (err)
3630 return err;
3631 }
3632
3633 return 0;
3634}
3635
579c82e4 3636static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
56ade8fe
JP		 3637{
3638 char htgt_pl[MLXSW_REG_HTGT_LEN];
117b0dad 3639 enum mlxsw_reg_htgt_trap_group i;
9148e7cf 3640 int max_cpu_policers;
579c82e4
NF		 3641 int max_trap_groups;
3642 u8 priority, tc;
9148e7cf 3643 u16 policer_id;
117b0dad 3644 int err;
579c82e4
NF		 3645
3646 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3647 return -EIO;
3648
3649 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
9148e7cf 3650 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
579c82e4
NF		 3651
3652 for (i = 0; i < max_trap_groups; i++) {
9148e7cf 3653 policer_id = i;
579c82e4 3654 switch (i) {
117b0dad
NF		 3655 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3656 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3657 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3658 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80 3659 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
117b0dad
NF		 3660 priority = 5;
3661 tc = 5;
3662 break;
8d54814e 3663 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
117b0dad
NF		 3664 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3665 priority = 4;
3666 tc = 4;
3667 break;
3668 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3669 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
588823f9 3670 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
117b0dad
NF		 3671 priority = 3;
3672 tc = 3;
3673 break;
3674 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
8d54814e 3675 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3676 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
117b0dad
NF		 3677 priority = 2;
3678 tc = 2;
3679 break;
8d54814e 3680 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
117b0dad
NF		 3681 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3682 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
b48cfc80 3683 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
117b0dad
NF		 3684 priority = 1;
3685 tc = 1;
3686 break;
3687 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
579c82e4
NF		 3688 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3689 tc = MLXSW_REG_HTGT_DEFAULT_TC;
9148e7cf 3690 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
579c82e4
NF		 3691 break;
3692 default:
3693 continue;
3694 }
117b0dad 3695
9148e7cf
NF		 3696 if (max_cpu_policers <= policer_id &&
3697 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3698 return -EIO;
3699
3700 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
579c82e4
NF		 3701 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3702 if (err)
3703 return err;
3704 }
3705
3706 return 0;
3707}
3708
3709static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3710{
56ade8fe
JP		 3711 int i;
3712 int err;
3713
9148e7cf
NF		 3714 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3715 if (err)
3716 return err;
3717
579c82e4 3718 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
56ade8fe
JP		 3719 if (err)
3720 return err;
3721
4544913e 3722 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3723 err = mlxsw_core_trap_register(mlxsw_sp->core,
4544913e 3724 &mlxsw_sp_listener[i],
14eeda99 3725 mlxsw_sp);
56ade8fe 3726 if (err)
4544913e 3727 goto err_listener_register;
56ade8fe 3728
56ade8fe
JP		 3729 }
3730 return 0;
3731
4544913e 3732err_listener_register:
56ade8fe 3733 for (i--; i >= 0; i--) {
14eeda99 3734 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3735 &mlxsw_sp_listener[i],
14eeda99 3736 mlxsw_sp);
56ade8fe
JP		 3737 }
3738 return err;
3739}
3740
3741static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3742{
56ade8fe
JP		 3743 int i;
3744
4544913e 3745 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3746 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3747 &mlxsw_sp_listener[i],
14eeda99 3748 mlxsw_sp);
56ade8fe
JP		 3749 }
3750}
3751
0d65fc13
JP		 3752static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3753{
3754 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 3755 int err;
0d65fc13
JP		 3756
3757 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3758 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3759 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3760 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3761 MLXSW_REG_SLCR_LAG_HASH_SIP |
3762 MLXSW_REG_SLCR_LAG_HASH_DIP |
3763 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3764 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3765 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 3766 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3767 if (err)
3768 return err;
3769
c1a38311
JP		 3770 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3771 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 3772 return -EIO;
3773
c1a38311 3774 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 3775 sizeof(struct mlxsw_sp_upper),
3776 GFP_KERNEL);
3777 if (!mlxsw_sp->lags)
3778 return -ENOMEM;
3779
3780 return 0;
3781}
3782
3783static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3784{
3785 kfree(mlxsw_sp->lags);
0d65fc13
JP		 3786}
3787
9d87fcea
NF		 3788static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3789{
3790 char htgt_pl[MLXSW_REG_HTGT_LEN];
3791
579c82e4
NF		 3792 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3793 MLXSW_REG_HTGT_INVALID_POLICER,
3794 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3795 MLXSW_REG_HTGT_DEFAULT_TC);
9d87fcea
NF		 3796 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3797}
3798
c30f5d01
PM		 3799static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3800 unsigned long event, void *ptr);
3801
b2f10571 3802static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 3803 const struct mlxsw_bus_info *mlxsw_bus_info)
3804{
b2f10571 3805 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 3806 int err;
3807
3808 mlxsw_sp->core = mlxsw_core;
3809 mlxsw_sp->bus_info = mlxsw_bus_info;
3810
6b742199
YG		 3811 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3812 if (err) {
3813 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3814 return err;
3815 }
3816
56ade8fe
JP		 3817 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3818 if (err) {
3819 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3820 return err;
3821 }
3822
a875a2ee
IS		 3823 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3824 if (err) {
3825 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3826 return err;
3827 }
3828
a1107487 3829 err = mlxsw_sp_fids_init(mlxsw_sp);
56ade8fe 3830 if (err) {
a1107487 3831 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
a875a2ee 3832 goto err_fids_init;
56ade8fe
JP		 3833 }
3834
a1107487 3835 err = mlxsw_sp_traps_init(mlxsw_sp);
56ade8fe 3836 if (err) {
a1107487
IS		 3837 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3838 goto err_traps_init;
56ade8fe
JP		 3839 }
3840
3841 err = mlxsw_sp_buffers_init(mlxsw_sp);
3842 if (err) {
3843 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3844 goto err_buffers_init;
3845 }
3846
0d65fc13
JP		 3847 err = mlxsw_sp_lag_init(mlxsw_sp);
3848 if (err) {
3849 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3850 goto err_lag_init;
3851 }
3852
56ade8fe
JP		 3853 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3854 if (err) {
3855 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3856 goto err_switchdev_init;
3857 }
3858
e2b2d35a
YG		 3859 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3860 if (err) {
3861 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3862 goto err_counter_pool_init;
3863 }
3864
d3b939b8
YG		 3865 err = mlxsw_sp_afa_init(mlxsw_sp);
3866 if (err) {
3867 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3868 goto err_afa_init;
3869 }
3870
464dce18
IS		 3871 err = mlxsw_sp_router_init(mlxsw_sp);
3872 if (err) {
3873 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3874 goto err_router_init;
3875 }
3876
c30f5d01
PM		 3877 /* Initialize netdevice notifier after router is initialized, so that
3878 * the event handler can use router structures.
3879 */
3880 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3881 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3882 if (err) {
3883 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3884 goto err_netdev_notifier;
3885 }
3886
763b4b70
YG		 3887 err = mlxsw_sp_span_init(mlxsw_sp);
3888 if (err) {
3889 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3890 goto err_span_init;
3891 }
3892
22a67766
JP		 3893 err = mlxsw_sp_acl_init(mlxsw_sp);
3894 if (err) {
3895 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3896 goto err_acl_init;
3897 }
3898
230ead01
AS		 3899 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3900 if (err) {
3901 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3902 goto err_dpipe_init;
3903 }
3904
bbf2a475
IS		 3905 err = mlxsw_sp_ports_create(mlxsw_sp);
3906 if (err) {
3907 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3908 goto err_ports_create;
3909 }
3910
56ade8fe
JP		 3911 return 0;
3912
bbf2a475 3913err_ports_create:
230ead01
AS		 3914 mlxsw_sp_dpipe_fini(mlxsw_sp);
3915err_dpipe_init:
22a67766
JP		 3916 mlxsw_sp_acl_fini(mlxsw_sp);
3917err_acl_init:
763b4b70
YG		 3918 mlxsw_sp_span_fini(mlxsw_sp);
3919err_span_init:
c30f5d01
PM		 3920 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3921err_netdev_notifier:
464dce18
IS		 3922 mlxsw_sp_router_fini(mlxsw_sp);
3923err_router_init:
d3b939b8
YG		 3924 mlxsw_sp_afa_fini(mlxsw_sp);
3925err_afa_init:
e2b2d35a
YG		 3926 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3927err_counter_pool_init:
bbf2a475 3928 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 3929err_switchdev_init:
ce0bd2b0 3930 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 3931err_lag_init:
0f433fa0 3932 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3933err_buffers_init:
56ade8fe 3934 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487
IS		 3935err_traps_init:
3936 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee
IS		 3937err_fids_init:
3938 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 3939 return err;
3940}
3941
b2f10571 3942static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 3943{
b2f10571 3944 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 3945
bbf2a475 3946 mlxsw_sp_ports_remove(mlxsw_sp);
230ead01 3947 mlxsw_sp_dpipe_fini(mlxsw_sp);
22a67766 3948 mlxsw_sp_acl_fini(mlxsw_sp);
763b4b70 3949 mlxsw_sp_span_fini(mlxsw_sp);
c30f5d01 3950 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
464dce18 3951 mlxsw_sp_router_fini(mlxsw_sp);
d3b939b8 3952 mlxsw_sp_afa_fini(mlxsw_sp);
e2b2d35a 3953 mlxsw_sp_counter_pool_fini(mlxsw_sp);
56ade8fe 3954 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 3955 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 3956 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3957 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487 3958 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee 3959 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 3960}
3961
159fe88e 3962static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
56ade8fe
JP		 3963 .used_max_vepa_channels = 1,
3964 .max_vepa_channels = 0,
56ade8fe 3965 .used_max_mid = 1,
53ae6283 3966 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 3967 .used_max_pgt = 1,
3968 .max_pgt = 0,
56ade8fe
JP		 3969 .used_flood_tables = 1,
3970 .used_flood_mode = 1,
3971 .flood_mode = 3,
71c365bd 3972 .max_fid_offset_flood_tables = 3,
56ade8fe 3973 .fid_offset_flood_table_size = VLAN_N_VID - 1,
71c365bd 3974 .max_fid_flood_tables = 3,
a1107487 3975 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
56ade8fe
JP		 3976 .used_max_ib_mc = 1,
3977 .max_ib_mc = 0,
3978 .used_max_pkey = 1,
3979 .max_pkey = 0,
403547d3
NF		 3980 .used_kvd_split_data = 1,
3981 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
f11fbaf8
IS		 3982 .kvd_hash_single_parts = 59,
3983 .kvd_hash_double_parts = 41,
c6022427 3984 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 3985 .swid_config = {
3986 {
3987 .used_type = 1,
3988 .type = MLXSW_PORT_SWID_TYPE_ETH,
3989 }
3990 },
57d316ba 3991 .resource_query_enable = 1,
56ade8fe
JP		 3992};
3993
3994static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 3995 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 3996 .priv_size = sizeof(struct mlxsw_sp),
3997 .init = mlxsw_sp_init,
3998 .fini = mlxsw_sp_fini,
9d87fcea 3999 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
2d0ed39f
JP		 4000 .port_split = mlxsw_sp_port_split,
4001 .port_unsplit = mlxsw_sp_port_unsplit,
4002 .sb_pool_get = mlxsw_sp_sb_pool_get,
4003 .sb_pool_set = mlxsw_sp_sb_pool_set,
4004 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4005 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4006 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4007 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4008 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4009 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4010 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4011 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4012 .txhdr_construct = mlxsw_sp_txhdr_construct,
4013 .txhdr_len = MLXSW_TXHDR_LEN,
4014 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 4015};
4016
22a67766 4017bool mlxsw_sp_port_dev_check(const struct net_device *dev)
7ce856aa
JP		 4018{
4019 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4020}
4021
1182e536 4022static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
dd82364c 4023{
1182e536 4024 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
dd82364c
DA		 4025 int ret = 0;
4026
4027 if (mlxsw_sp_port_dev_check(lower_dev)) {
1182e536 4028 *p_mlxsw_sp_port = netdev_priv(lower_dev);
dd82364c
DA		 4029 ret = 1;
4030 }
4031
4032 return ret;
4033}
4034
c57529e1 4035struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
7ce856aa 4036{
1182e536 4037 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 4038
4039 if (mlxsw_sp_port_dev_check(dev))
4040 return netdev_priv(dev);
4041
1182e536
JP		 4042 mlxsw_sp_port = NULL;
4043 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
dd82364c 4044
1182e536 4045 return mlxsw_sp_port;
7ce856aa
JP		 4046}
4047
4724ba56 4048struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
7ce856aa
JP		 4049{
4050 struct mlxsw_sp_port *mlxsw_sp_port;
4051
4052 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4053 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4054}
4055
af061378 4056struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
7ce856aa 4057{
1182e536 4058 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 4059
4060 if (mlxsw_sp_port_dev_check(dev))
4061 return netdev_priv(dev);
4062
1182e536
JP		 4063 mlxsw_sp_port = NULL;
4064 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4065 &mlxsw_sp_port);
dd82364c 4066
1182e536 4067 return mlxsw_sp_port;
7ce856aa
JP		 4068}
4069
4070struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4071{
4072 struct mlxsw_sp_port *mlxsw_sp_port;
4073
4074 rcu_read_lock();
4075 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4076 if (mlxsw_sp_port)
4077 dev_hold(mlxsw_sp_port->dev);
4078 rcu_read_unlock();
4079 return mlxsw_sp_port;
4080}
4081
4082void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4083{
4084 dev_put(mlxsw_sp_port->dev);
4085}
4086
0d65fc13
JP		 4087static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4088{
4089 char sldr_pl[MLXSW_REG_SLDR_LEN];
4090
4091 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4092 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4093}
4094
4095static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4096{
4097 char sldr_pl[MLXSW_REG_SLDR_LEN];
4098
4099 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4100 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4101}
4102
4103static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4104 u16 lag_id, u8 port_index)
4105{
4106 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4107 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4108
4109 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4110 lag_id, port_index);
4111 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4112}
4113
4114static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4115 u16 lag_id)
4116{
4117 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4118 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4119
4120 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4121 lag_id);
4122 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4123}
4124
4125static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4126 u16 lag_id)
4127{
4128 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4129 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4130
4131 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4132 lag_id);
4133 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4134}
4135
4136static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4137 u16 lag_id)
4138{
4139 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4140 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4141
4142 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4143 lag_id);
4144 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4145}
4146
4147static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4148 struct net_device *lag_dev,
4149 u16 *p_lag_id)
4150{
4151 struct mlxsw_sp_upper *lag;
4152 int free_lag_id = -1;
c1a38311 4153 u64 max_lag;
0d65fc13
JP		 4154 int i;
4155
c1a38311
JP		 4156 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4157 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 4158 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4159 if (lag->ref_count) {
4160 if (lag->dev == lag_dev) {
4161 *p_lag_id = i;
4162 return 0;
4163 }
4164 } else if (free_lag_id < 0) {
4165 free_lag_id = i;
4166 }
4167 }
4168 if (free_lag_id < 0)
4169 return -EBUSY;
4170 *p_lag_id = free_lag_id;
4171 return 0;
4172}
4173
4174static bool
4175mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4176 struct net_device *lag_dev,
e58376e1
DA		 4177 struct netdev_lag_upper_info *lag_upper_info,
4178 struct netlink_ext_ack *extack)
0d65fc13
JP		 4179{
4180 u16 lag_id;
4181
e58376e1
DA		 4182 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4183 NL_SET_ERR_MSG(extack,
4184 "spectrum: Exceeded number of supported LAG devices");
0d65fc13 4185 return false;
e58376e1
DA		 4186 }
4187 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4188 NL_SET_ERR_MSG(extack,
4189 "spectrum: LAG device using unsupported Tx type");
0d65fc13 4190 return false;
e58376e1 4191 }
0d65fc13
JP		 4192 return true;
4193}
4194
4195static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4196 u16 lag_id, u8 *p_port_index)
4197{
c1a38311 4198 u64 max_lag_members;
0d65fc13
JP		 4199 int i;
4200
c1a38311
JP		 4201 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4202 MAX_LAG_MEMBERS);
4203 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 4204 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4205 *p_port_index = i;
4206 return 0;
4207 }
4208 }
4209 return -EBUSY;
4210}
4211
4212static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4213 struct net_device *lag_dev)
4214{
4215 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
c57529e1 4216 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
0d65fc13
JP		 4217 struct mlxsw_sp_upper *lag;
4218 u16 lag_id;
4219 u8 port_index;
4220 int err;
4221
4222 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4223 if (err)
4224 return err;
4225 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4226 if (!lag->ref_count) {
4227 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4228 if (err)
4229 return err;
4230 lag->dev = lag_dev;
4231 }
4232
4233 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4234 if (err)
4235 return err;
4236 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4237 if (err)
4238 goto err_col_port_add;
4239 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4240 if (err)
4241 goto err_col_port_enable;
4242
4243 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4244 mlxsw_sp_port->local_port);
4245 mlxsw_sp_port->lag_id = lag_id;
4246 mlxsw_sp_port->lagged = 1;
4247 lag->ref_count++;
86bf95b3 4248
c57529e1
IS		 4249 /* Port is no longer usable as a router interface */
4250 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4251 if (mlxsw_sp_port_vlan->fid)
a1107487 4252 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
86bf95b3 4253
0d65fc13
JP		 4254 return 0;
4255
51554db2
IS		 4256err_col_port_enable:
4257 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4258err_col_port_add:
4259 if (!lag->ref_count)
4260 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4261 return err;
4262}
4263
82e6db03
IS		 4264static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4265 struct net_device *lag_dev)
0d65fc13
JP		 4266{
4267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4268 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4269 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4270
4271 if (!mlxsw_sp_port->lagged)
82e6db03 4272 return;
0d65fc13
JP		 4273 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4274 WARN_ON(lag->ref_count == 0);
4275
82e6db03
IS		 4276 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4277 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4278
c57529e1
IS		 4279 /* Any VLANs configured on the port are no longer valid */
4280 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4dc236c3 4281
fe3f6d14 4282 if (lag->ref_count == 1)
82e6db03 4283 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4284
4285 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4286 mlxsw_sp_port->local_port);
4287 mlxsw_sp_port->lagged = 0;
4288 lag->ref_count--;
86bf95b3 4289
c57529e1
IS		 4290 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4291 /* Make sure untagged frames are allowed to ingress */
4292 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
0d65fc13
JP		 4293}
4294
74581206
JP		 4295static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4296 u16 lag_id)
4297{
4298 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4299 char sldr_pl[MLXSW_REG_SLDR_LEN];
4300
4301 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4302 mlxsw_sp_port->local_port);
4303 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4304}
4305
4306static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4307 u16 lag_id)
4308{
4309 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4310 char sldr_pl[MLXSW_REG_SLDR_LEN];
4311
4312 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4313 mlxsw_sp_port->local_port);
4314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4315}
4316
4317static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4318 bool lag_tx_enabled)
4319{
4320 if (lag_tx_enabled)
4321 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4322 mlxsw_sp_port->lag_id);
4323 else
4324 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4325 mlxsw_sp_port->lag_id);
4326}
4327
4328static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4329 struct netdev_lag_lower_state_info *info)
4330{
4331 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4332}
4333
2b94e58d
JP		 4334static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4335 bool enable)
4336{
4337 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4338 enum mlxsw_reg_spms_state spms_state;
4339 char *spms_pl;
4340 u16 vid;
4341 int err;
4342
4343 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4344 MLXSW_REG_SPMS_STATE_DISCARDING;
4345
4346 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4347 if (!spms_pl)
4348 return -ENOMEM;
4349 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4350
4351 for (vid = 0; vid < VLAN_N_VID; vid++)
4352 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4353
4354 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4355 kfree(spms_pl);
4356 return err;
4357}
4358
4359static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4360{
fccff086 4361 u16 vid = 1;
2b94e58d
JP		 4362 int err;
4363
4aafc368 4364 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
2b94e58d
JP		 4365 if (err)
4366 return err;
4aafc368
IS		 4367 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4368 if (err)
4369 goto err_port_stp_set;
2b94e58d
JP		 4370 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4371 true, false);
4372 if (err)
4373 goto err_port_vlan_set;
fccff086
YM		 4374
4375 for (; vid <= VLAN_N_VID - 1; vid++) {
4376 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4377 vid, false);
4378 if (err)
4379 goto err_vid_learning_set;
4380 }
4381
2b94e58d
JP		 4382 return 0;
4383
fccff086
YM		 4384err_vid_learning_set:
4385 for (vid--; vid >= 1; vid--)
4386 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
2b94e58d
JP		 4387err_port_vlan_set:
4388 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368
IS		 4389err_port_stp_set:
4390 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4391 return err;
4392}
4393
4394static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4395{
fccff086
YM		 4396 u16 vid;
4397
4398 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4399 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4400 vid, true);
4401
2b94e58d
JP		 4402 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4403 false, false);
4404 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368 4405 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4406}
4407
f0cebd81
IS		 4408static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4409 struct net_device *dev,
74581206 4410 unsigned long event, void *ptr)
56ade8fe 4411{
56ade8fe
JP		 4412 struct netdev_notifier_changeupper_info *info;
4413 struct mlxsw_sp_port *mlxsw_sp_port;
e58376e1 4414 struct netlink_ext_ack *extack;
56ade8fe
JP		 4415 struct net_device *upper_dev;
4416 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4417 int err = 0;
56ade8fe 4418
56ade8fe
JP		 4419 mlxsw_sp_port = netdev_priv(dev);
4420 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4421 info = ptr;
e58376e1 4422 extack = netdev_notifier_info_to_extack(&info->info);
56ade8fe
JP		 4423
4424 switch (event) {
4425 case NETDEV_PRECHANGEUPPER:
4426 upper_dev = info->upper_dev;
59fe9b3f
IS		 4427 if (!is_vlan_dev(upper_dev) &&
4428 !netif_is_lag_master(upper_dev) &&
7179eb5a 4429 !netif_is_bridge_master(upper_dev) &&
e58376e1
DA		 4430 !netif_is_ovs_master(upper_dev)) {
4431 NL_SET_ERR_MSG(extack,
4432 "spectrum: Unknown upper device type");
59fe9b3f 4433 return -EINVAL;
e58376e1 4434 }
6ec43904 4435 if (!info->linking)
0d65fc13 4436 break;
90045fc9
IS		 4437 if (netdev_has_any_upper_dev(upper_dev) &&
4438 (!netif_is_bridge_master(upper_dev) ||
4439 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4440 upper_dev))) {
e58376e1
DA		 4441 NL_SET_ERR_MSG(extack,
4442 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4443 return -EINVAL;
e58376e1 4444 }
0d65fc13
JP		 4445 if (netif_is_lag_master(upper_dev) &&
4446 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
e58376e1 4447 info->upper_info, extack))
80bedf1a 4448 return -EINVAL;
e58376e1
DA		 4449 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4450 NL_SET_ERR_MSG(extack,
4451 "spectrum: Master device is a LAG master and this device has a VLAN");
6ec43904 4452 return -EINVAL;
e58376e1 4453 }
6ec43904 4454 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
e58376e1
DA		 4455 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4456 NL_SET_ERR_MSG(extack,
4457 "spectrum: Can not put a VLAN on a LAG port");
6ec43904 4458 return -EINVAL;
e58376e1
DA		 4459 }
4460 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4461 NL_SET_ERR_MSG(extack,
4462 "spectrum: Master device is an OVS master and this device has a VLAN");
2b94e58d 4463 return -EINVAL;
e58376e1
DA		 4464 }
4465 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4466 NL_SET_ERR_MSG(extack,
4467 "spectrum: Can not put a VLAN on an OVS port");
2b94e58d 4468 return -EINVAL;
e58376e1 4469 }
56ade8fe
JP		 4470 break;
4471 case NETDEV_CHANGEUPPER:
4472 upper_dev = info->upper_dev;
c57529e1 4473 if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4474 if (info->linking)
4475 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
f0cebd81 4476 lower_dev,
9b63ef88
IS		 4477 upper_dev,
4478 extack);
7117a570 4479 else
f0cebd81
IS		 4480 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4481 lower_dev,
4482 upper_dev);
0d65fc13 4483 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4484 if (info->linking)
0d65fc13
JP		 4485 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4486 upper_dev);
80bedf1a 4487 else
82e6db03
IS		 4488 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4489 upper_dev);
2b94e58d
JP		 4490 } else if (netif_is_ovs_master(upper_dev)) {
4491 if (info->linking)
4492 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4493 else
4494 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
56ade8fe
JP		 4495 }
4496 break;
4497 }
4498
80bedf1a 4499 return err;
56ade8fe
JP		 4500}
4501
74581206
JP		 4502static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4503 unsigned long event, void *ptr)
4504{
4505 struct netdev_notifier_changelowerstate_info *info;
4506 struct mlxsw_sp_port *mlxsw_sp_port;
4507 int err;
4508
4509 mlxsw_sp_port = netdev_priv(dev);
4510 info = ptr;
4511
4512 switch (event) {
4513 case NETDEV_CHANGELOWERSTATE:
4514 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4515 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4516 info->lower_state_info);
4517 if (err)
4518 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4519 }
4520 break;
4521 }
4522
80bedf1a 4523 return 0;
74581206
JP		 4524}
4525
f0cebd81
IS		 4526static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4527 struct net_device *port_dev,
74581206
JP		 4528 unsigned long event, void *ptr)
4529{
4530 switch (event) {
4531 case NETDEV_PRECHANGEUPPER:
4532 case NETDEV_CHANGEUPPER:
f0cebd81
IS		 4533 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4534 event, ptr);
74581206 4535 case NETDEV_CHANGELOWERSTATE:
f0cebd81
IS		 4536 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4537 ptr);
74581206
JP		 4538 }
4539
80bedf1a 4540 return 0;
74581206
JP		 4541}
4542
0d65fc13
JP		 4543static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4544 unsigned long event, void *ptr)
4545{
4546 struct net_device *dev;
4547 struct list_head *iter;
4548 int ret;
4549
4550 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4551 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4552 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4553 ptr);
80bedf1a 4554 if (ret)
0d65fc13
JP		 4555 return ret;
4556 }
4557 }
4558
80bedf1a 4559 return 0;
0d65fc13
JP		 4560}
4561
f0cebd81
IS		 4562static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4563 struct net_device *dev,
4564 unsigned long event, void *ptr,
4565 u16 vid)
26f0e7fb
IS		 4566{
4567 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
90045fc9 4568 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
26f0e7fb 4569 struct netdev_notifier_changeupper_info *info = ptr;
c1f2c6d0 4570 struct netlink_ext_ack *extack;
26f0e7fb 4571 struct net_device *upper_dev;
80bedf1a 4572 int err = 0;
26f0e7fb 4573
c1f2c6d0
IS		 4574 extack = netdev_notifier_info_to_extack(&info->info);
4575
26f0e7fb
IS		 4576 switch (event) {
4577 case NETDEV_PRECHANGEUPPER:
4578 upper_dev = info->upper_dev;
c1f2c6d0
IS		 4579 if (!netif_is_bridge_master(upper_dev)) {
4580 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
80bedf1a 4581 return -EINVAL;
c1f2c6d0 4582 }
25cc72a3
IS		 4583 if (!info->linking)
4584 break;
90045fc9
IS		 4585 if (netdev_has_any_upper_dev(upper_dev) &&
4586 (!netif_is_bridge_master(upper_dev) ||
4587 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4588 upper_dev))) {
c1f2c6d0 4589 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4590 return -EINVAL;
c1f2c6d0 4591 }
26f0e7fb
IS		 4592 break;
4593 case NETDEV_CHANGEUPPER:
4594 upper_dev = info->upper_dev;
1f88061e
IS		 4595 if (netif_is_bridge_master(upper_dev)) {
4596 if (info->linking)
c57529e1
IS		 4597 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4598 vlan_dev,
9b63ef88
IS		 4599 upper_dev,
4600 extack);
1f88061e 4601 else
c57529e1
IS		 4602 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4603 vlan_dev,
4604 upper_dev);
26f0e7fb 4605 } else {
1f88061e
IS		 4606 err = -EINVAL;
4607 WARN_ON(1);
26f0e7fb 4608 }
1f88061e 4609 break;
26f0e7fb
IS		 4610 }
4611
80bedf1a 4612 return err;
26f0e7fb
IS		 4613}
4614
f0cebd81
IS		 4615static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4616 struct net_device *lag_dev,
4617 unsigned long event,
4618 void *ptr, u16 vid)
272c4470
IS		 4619{
4620 struct net_device *dev;
4621 struct list_head *iter;
4622 int ret;
4623
4624 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4625 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4626 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4627 event, ptr,
4628 vid);
80bedf1a 4629 if (ret)
272c4470
IS		 4630 return ret;
4631 }
4632 }
4633
80bedf1a 4634 return 0;
272c4470
IS		 4635}
4636
26f0e7fb
IS		 4637static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4638 unsigned long event, void *ptr)
4639{
4640 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4641 u16 vid = vlan_dev_vlan_id(vlan_dev);
4642
272c4470 4643 if (mlxsw_sp_port_dev_check(real_dev))
f0cebd81
IS		 4644 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4645 event, ptr, vid);
272c4470 4646 else if (netif_is_lag_master(real_dev))
f0cebd81
IS		 4647 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4648 real_dev, event,
4649 ptr, vid);
26f0e7fb 4650
80bedf1a 4651 return 0;
26f0e7fb
IS		 4652}
4653
b1e45526
IS		 4654static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4655{
4656 struct netdev_notifier_changeupper_info *info = ptr;
4657
4658 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4659 return false;
4660 return netif_is_l3_master(info->upper_dev);
4661}
4662
0063587d 4663static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
0d65fc13
JP		 4664 unsigned long event, void *ptr)
4665{
4666 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
0063587d 4667 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4668 int err = 0;
0d65fc13 4669
0063587d 4670 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
796ec776
PM		 4671 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4672 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4673 event, ptr);
61481f2f
PM		 4674 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4675 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4676 event, ptr);
0063587d 4677 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
6e095fd4 4678 err = mlxsw_sp_netdevice_router_port_event(dev);
b1e45526
IS		 4679 else if (mlxsw_sp_is_vrf_event(event, ptr))
4680 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6e095fd4 4681 else if (mlxsw_sp_port_dev_check(dev))
f0cebd81 4682 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
80bedf1a
IS		 4683 else if (netif_is_lag_master(dev))
4684 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4685 else if (is_vlan_dev(dev))
4686 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 4687
80bedf1a 4688 return notifier_from_errno(err);
0d65fc13
JP		 4689}
4690
89d5dd2e
DA		 4691static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4692 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4693};
4694
99724c18
IS		 4695static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4696 .notifier_call = mlxsw_sp_inetaddr_event,
89d5dd2e
DA		 4697};
4698
4699static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4700 .notifier_call = mlxsw_sp_inet6addr_valid_event,
99724c18
IS		 4701};
4702
5ea1237f
AS		 4703static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4704 .notifier_call = mlxsw_sp_inet6addr_event,
4705};
4706
1d20d23c
JP		 4707static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4708 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4709 {0, },
4710};
4711
4712static struct pci_driver mlxsw_sp_pci_driver = {
4713 .name = mlxsw_sp_driver_name,
4714 .id_table = mlxsw_sp_pci_id_table,
4715};
4716
56ade8fe
JP		 4717static int __init mlxsw_sp_module_init(void)
4718{
4719 int err;
4720
89d5dd2e 4721 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
99724c18 4722 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4723 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5ea1237f 4724 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
e7322638 4725
56ade8fe
JP		 4726 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4727 if (err)
4728 goto err_core_driver_register;
1d20d23c
JP		 4729
4730 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4731 if (err)
4732 goto err_pci_driver_register;
4733
56ade8fe
JP		 4734 return 0;
4735
1d20d23c
JP		 4736err_pci_driver_register:
4737 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 4738err_core_driver_register:
5ea1237f 4739 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 4740 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
de7d6295 4741 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4742 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 4743 return err;
4744}
4745
4746static void __exit mlxsw_sp_module_exit(void)
4747{
1d20d23c 4748 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 4749 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
5ea1237f 4750 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 4751 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
99724c18 4752 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4753 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 4754}
4755
4756module_init(mlxsw_sp_module_init);
4757module_exit(mlxsw_sp_module_exit);
4758
4759MODULE_LICENSE("Dual BSD/GPL");
4760MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4761MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 4762MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
6b742199 4763MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);
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