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mlxsw: spectrum: Add BGP trap
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
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56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
56ade8fe 56#include <net/switchdev.h>
763b4b70
YG		 57#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
e7322638 59#include <net/netevent.h>
56ade8fe
JP		 60
61#include "spectrum.h"
1d20d23c 62#include "pci.h"
56ade8fe
JP		 63#include "core.h"
64#include "reg.h"
65#include "port.h"
66#include "trap.h"
67#include "txheader.h"
68
69static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
70static const char mlxsw_sp_driver_version[] = "1.0";
71
72/* tx_hdr_version
73 * Tx header version.
74 * Must be set to 1.
75 */
76MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
77
78/* tx_hdr_ctl
79 * Packet control type.
80 * 0 - Ethernet control (e.g. EMADs, LACP)
81 * 1 - Ethernet data
82 */
83MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
84
85/* tx_hdr_proto
86 * Packet protocol type. Must be set to 1 (Ethernet).
87 */
88MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
89
90/* tx_hdr_rx_is_router
91 * Packet is sent from the router. Valid for data packets only.
92 */
93MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
94
95/* tx_hdr_fid_valid
96 * Indicates if the 'fid' field is valid and should be used for
97 * forwarding lookup. Valid for data packets only.
98 */
99MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
100
101/* tx_hdr_swid
102 * Switch partition ID. Must be set to 0.
103 */
104MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
105
106/* tx_hdr_control_tclass
107 * Indicates if the packet should use the control TClass and not one
108 * of the data TClasses.
109 */
110MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
111
112/* tx_hdr_etclass
113 * Egress TClass to be used on the egress device on the egress port.
114 */
115MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
116
117/* tx_hdr_port_mid
118 * Destination local port for unicast packets.
119 * Destination multicast ID for multicast packets.
120 *
121 * Control packets are directed to a specific egress port, while data
122 * packets are transmitted through the CPU port (0) into the switch partition,
123 * where forwarding rules are applied.
124 */
125MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
126
127/* tx_hdr_fid
128 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
129 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
130 * Valid for data packets only.
131 */
132MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
133
134/* tx_hdr_type
135 * 0 - Data packets
136 * 6 - Control packets
137 */
138MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
139
763b4b70
YG		 140static bool mlxsw_sp_port_dev_check(const struct net_device *dev);
141
56ade8fe
JP		 142static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
143 const struct mlxsw_tx_info *tx_info)
144{
145 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
146
147 memset(txhdr, 0, MLXSW_TXHDR_LEN);
148
149 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
150 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
151 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
152 mlxsw_tx_hdr_swid_set(txhdr, 0);
153 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
154 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
155 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
156}
157
158static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
159{
5b090740 160 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
56ade8fe
JP		 161 int err;
162
163 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
164 if (err)
165 return err;
166 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
167 return 0;
168}
169
763b4b70
YG		 170static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
171{
763b4b70
YG		 172 int i;
173
c1a38311 174 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 175 return -EIO;
176
c1a38311
JP		 177 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
178 MAX_SPAN);
763b4b70
YG		 179 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
180 sizeof(struct mlxsw_sp_span_entry),
181 GFP_KERNEL);
182 if (!mlxsw_sp->span.entries)
183 return -ENOMEM;
184
185 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
186 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
187
188 return 0;
189}
190
191static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
192{
193 int i;
194
195 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
196 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
197
198 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
199 }
200 kfree(mlxsw_sp->span.entries);
201}
202
203static struct mlxsw_sp_span_entry *
204mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
205{
206 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
207 struct mlxsw_sp_span_entry *span_entry;
208 char mpat_pl[MLXSW_REG_MPAT_LEN];
209 u8 local_port = port->local_port;
210 int index;
211 int i;
212 int err;
213
214 /* find a free entry to use */
215 index = -1;
216 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
217 if (!mlxsw_sp->span.entries[i].used) {
218 index = i;
219 span_entry = &mlxsw_sp->span.entries[i];
220 break;
221 }
222 }
223 if (index < 0)
224 return NULL;
225
226 /* create a new port analayzer entry for local_port */
227 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
228 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
229 if (err)
230 return NULL;
231
232 span_entry->used = true;
233 span_entry->id = index;
2d644d4c 234 span_entry->ref_count = 1;
763b4b70
YG		 235 span_entry->local_port = local_port;
236 return span_entry;
237}
238
239static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
240 struct mlxsw_sp_span_entry *span_entry)
241{
242 u8 local_port = span_entry->local_port;
243 char mpat_pl[MLXSW_REG_MPAT_LEN];
244 int pa_id = span_entry->id;
245
246 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
247 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
248 span_entry->used = false;
249}
250
1a9234e6
IS		 251static struct mlxsw_sp_span_entry *
252mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
763b4b70
YG		 253{
254 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
255 int i;
256
257 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
258 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
259
260 if (curr->used && curr->local_port == port->local_port)
261 return curr;
262 }
263 return NULL;
264}
265
1a9234e6
IS		 266static struct mlxsw_sp_span_entry
267*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 268{
269 struct mlxsw_sp_span_entry *span_entry;
270
271 span_entry = mlxsw_sp_span_entry_find(port);
272 if (span_entry) {
2d644d4c 273 /* Already exists, just take a reference */
763b4b70
YG		 274 span_entry->ref_count++;
275 return span_entry;
276 }
277
278 return mlxsw_sp_span_entry_create(port);
279}
280
281static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
282 struct mlxsw_sp_span_entry *span_entry)
283{
2d644d4c 284 WARN_ON(!span_entry->ref_count);
763b4b70
YG		 285 if (--span_entry->ref_count == 0)
286 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
287 return 0;
288}
289
290static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
291{
292 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
293 struct mlxsw_sp_span_inspected_port *p;
294 int i;
295
296 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
297 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
298
299 list_for_each_entry(p, &curr->bound_ports_list, list)
300 if (p->local_port == port->local_port &&
301 p->type == MLXSW_SP_SPAN_EGRESS)
302 return true;
303 }
304
305 return false;
306}
307
308static int mlxsw_sp_span_mtu_to_buffsize(int mtu)
309{
310 return MLXSW_SP_BYTES_TO_CELLS(mtu * 5 / 2) + 1;
311}
312
313static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
314{
315 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
316 char sbib_pl[MLXSW_REG_SBIB_LEN];
317 int err;
318
319 /* If port is egress mirrored, the shared buffer size should be
320 * updated according to the mtu value
321 */
322 if (mlxsw_sp_span_is_egress_mirror(port)) {
323 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
324 mlxsw_sp_span_mtu_to_buffsize(mtu));
325 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
326 if (err) {
327 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
328 return err;
329 }
330 }
331
332 return 0;
333}
334
335static struct mlxsw_sp_span_inspected_port *
336mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
337 struct mlxsw_sp_span_entry *span_entry)
338{
339 struct mlxsw_sp_span_inspected_port *p;
340
341 list_for_each_entry(p, &span_entry->bound_ports_list, list)
342 if (port->local_port == p->local_port)
343 return p;
344 return NULL;
345}
346
347static int
348mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
349 struct mlxsw_sp_span_entry *span_entry,
350 enum mlxsw_sp_span_type type)
351{
352 struct mlxsw_sp_span_inspected_port *inspected_port;
353 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
354 char mpar_pl[MLXSW_REG_MPAR_LEN];
355 char sbib_pl[MLXSW_REG_SBIB_LEN];
356 int pa_id = span_entry->id;
357 int err;
358
359 /* if it is an egress SPAN, bind a shared buffer to it */
360 if (type == MLXSW_SP_SPAN_EGRESS) {
361 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
362 mlxsw_sp_span_mtu_to_buffsize(port->dev->mtu));
363 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
364 if (err) {
365 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
366 return err;
367 }
368 }
369
370 /* bind the port to the SPAN entry */
1a9234e6
IS		 371 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
372 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
763b4b70
YG		 373 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
374 if (err)
375 goto err_mpar_reg_write;
376
377 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
378 if (!inspected_port) {
379 err = -ENOMEM;
380 goto err_inspected_port_alloc;
381 }
382 inspected_port->local_port = port->local_port;
383 inspected_port->type = type;
384 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
385
386 return 0;
387
388err_mpar_reg_write:
389err_inspected_port_alloc:
390 if (type == MLXSW_SP_SPAN_EGRESS) {
391 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
392 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
393 }
394 return err;
395}
396
397static void
398mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
399 struct mlxsw_sp_span_entry *span_entry,
400 enum mlxsw_sp_span_type type)
401{
402 struct mlxsw_sp_span_inspected_port *inspected_port;
403 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
404 char mpar_pl[MLXSW_REG_MPAR_LEN];
405 char sbib_pl[MLXSW_REG_SBIB_LEN];
406 int pa_id = span_entry->id;
407
408 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
409 if (!inspected_port)
410 return;
411
412 /* remove the inspected port */
1a9234e6
IS		 413 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
414 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
763b4b70
YG		 415 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
416
417 /* remove the SBIB buffer if it was egress SPAN */
418 if (type == MLXSW_SP_SPAN_EGRESS) {
419 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
420 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
421 }
422
423 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
424
425 list_del(&inspected_port->list);
426 kfree(inspected_port);
427}
428
429static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
430 struct mlxsw_sp_port *to,
431 enum mlxsw_sp_span_type type)
432{
433 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
434 struct mlxsw_sp_span_entry *span_entry;
435 int err;
436
437 span_entry = mlxsw_sp_span_entry_get(to);
438 if (!span_entry)
439 return -ENOENT;
440
441 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
442 span_entry->id);
443
444 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
445 if (err)
446 goto err_port_bind;
447
448 return 0;
449
450err_port_bind:
451 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
452 return err;
453}
454
455static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
456 struct mlxsw_sp_port *to,
457 enum mlxsw_sp_span_type type)
458{
459 struct mlxsw_sp_span_entry *span_entry;
460
461 span_entry = mlxsw_sp_span_entry_find(to);
462 if (!span_entry) {
463 netdev_err(from->dev, "no span entry found\n");
464 return;
465 }
466
467 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
468 span_entry->id);
469 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
470}
471
56ade8fe
JP		 472static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
473 bool is_up)
474{
475 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
476 char paos_pl[MLXSW_REG_PAOS_LEN];
477
478 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
479 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
480 MLXSW_PORT_ADMIN_STATUS_DOWN);
481 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
482}
483
56ade8fe
JP		 484static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
485 unsigned char *addr)
486{
487 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
488 char ppad_pl[MLXSW_REG_PPAD_LEN];
489
490 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
491 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
492 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
493}
494
495static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
496{
497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
498 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
499
500 ether_addr_copy(addr, mlxsw_sp->base_mac);
501 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
502 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
503}
504
56ade8fe
JP		 505static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
506{
507 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
508 char pmtu_pl[MLXSW_REG_PMTU_LEN];
509 int max_mtu;
510 int err;
511
512 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
513 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
514 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
515 if (err)
516 return err;
517 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
518
519 if (mtu > max_mtu)
520 return -EINVAL;
521
522 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
523 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
524}
525
be94535f
IS		 526static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
527 u8 swid)
56ade8fe 528{
56ade8fe
JP		 529 char pspa_pl[MLXSW_REG_PSPA_LEN];
530
be94535f 531 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
56ade8fe
JP		 532 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
533}
534
be94535f
IS		 535static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
536{
537 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
538
539 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
540 swid);
541}
542
56ade8fe
JP		 543static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
544 bool enable)
545{
546 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
547 char svpe_pl[MLXSW_REG_SVPE_LEN];
548
549 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
550 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
551}
552
553int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
554 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
555 u16 vid)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
558 char svfa_pl[MLXSW_REG_SVFA_LEN];
559
560 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
561 fid, vid);
562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
563}
564
584d73df
IS		 565int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
566 u16 vid_begin, u16 vid_end,
567 bool learn_enable)
56ade8fe
JP		 568{
569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
570 char *spvmlr_pl;
571 int err;
572
573 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
574 if (!spvmlr_pl)
575 return -ENOMEM;
584d73df
IS		 576 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid_begin,
577 vid_end, learn_enable);
56ade8fe
JP		 578 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
579 kfree(spvmlr_pl);
580 return err;
581}
582
584d73df
IS		 583static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
584 u16 vid, bool learn_enable)
585{
586 return __mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, vid,
587 learn_enable);
588}
589
56ade8fe
JP		 590static int
591mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
592{
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char sspr_pl[MLXSW_REG_SSPR_LEN];
595
596 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
598}
599
d664b41e
IS		 600static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
601 u8 local_port, u8 *p_module,
602 u8 *p_width, u8 *p_lane)
56ade8fe 603{
56ade8fe
JP		 604 char pmlp_pl[MLXSW_REG_PMLP_LEN];
605 int err;
606
558c2d5e 607 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 608 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
609 if (err)
610 return err;
558c2d5e
IS		 611 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
612 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 613 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 614 return 0;
615}
616
18f1e70c
IS		 617static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
618 u8 module, u8 width, u8 lane)
619{
620 char pmlp_pl[MLXSW_REG_PMLP_LEN];
621 int i;
622
623 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
624 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
625 for (i = 0; i < width; i++) {
626 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
627 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
628 }
629
630 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
631}
632
3e9b27b8
IS		 633static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
634{
635 char pmlp_pl[MLXSW_REG_PMLP_LEN];
636
637 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
638 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
639 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
640}
641
56ade8fe
JP		 642static int mlxsw_sp_port_open(struct net_device *dev)
643{
644 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
645 int err;
646
647 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
648 if (err)
649 return err;
650 netif_start_queue(dev);
651 return 0;
652}
653
654static int mlxsw_sp_port_stop(struct net_device *dev)
655{
656 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
657
658 netif_stop_queue(dev);
659 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
660}
661
662static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
663 struct net_device *dev)
664{
665 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
666 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
667 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
668 const struct mlxsw_tx_info tx_info = {
669 .local_port = mlxsw_sp_port->local_port,
670 .is_emad = false,
671 };
672 u64 len;
673 int err;
674
307c2431 675 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 676 return NETDEV_TX_BUSY;
677
678 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
679 struct sk_buff *skb_orig = skb;
680
681 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
682 if (!skb) {
683 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
684 dev_kfree_skb_any(skb_orig);
685 return NETDEV_TX_OK;
686 }
687 }
688
689 if (eth_skb_pad(skb)) {
690 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
691 return NETDEV_TX_OK;
692 }
693
694 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 695 /* TX header is consumed by HW on the way so we shouldn't count its
696 * bytes as being sent.
697 */
698 len = skb->len - MLXSW_TXHDR_LEN;
699
56ade8fe
JP		 700 /* Due to a race we might fail here because of a full queue. In that
701 * unlikely case we simply drop the packet.
702 */
307c2431 703 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 704
705 if (!err) {
706 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
707 u64_stats_update_begin(&pcpu_stats->syncp);
708 pcpu_stats->tx_packets++;
709 pcpu_stats->tx_bytes += len;
710 u64_stats_update_end(&pcpu_stats->syncp);
711 } else {
712 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
713 dev_kfree_skb_any(skb);
714 }
715 return NETDEV_TX_OK;
716}
717
c5b9b518
JP		 718static void mlxsw_sp_set_rx_mode(struct net_device *dev)
719{
720}
721
56ade8fe
JP		 722static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
723{
724 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
725 struct sockaddr *addr = p;
726 int err;
727
728 if (!is_valid_ether_addr(addr->sa_data))
729 return -EADDRNOTAVAIL;
730
731 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
732 if (err)
733 return err;
734 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
735 return 0;
736}
737
9f7ec052 738static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
d81a6bdb 739 bool pause_en, bool pfc_en, u16 delay)
ff6551ec 740{
ff6551ec 741 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
8e8dfe9f 742
d81a6bdb
IS		 743 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
744 MLXSW_SP_PAUSE_DELAY;
9f7ec052 745
d81a6bdb 746 if (pause_en || pfc_en)
9f7ec052 747 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
d81a6bdb
IS		 748 pg_size + delay, pg_size);
749 else
9f7ec052 750 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
8e8dfe9f
IS		 751}
752
753int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 754 u8 *prio_tc, bool pause_en,
755 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 756{
757 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 758 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
759 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 760 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 761 int i, j, err;
ff6551ec
IS		 762
763 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
764 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
765 if (err)
766 return err;
8e8dfe9f
IS		 767
768 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
769 bool configure = false;
d81a6bdb 770 bool pfc = false;
8e8dfe9f
IS		 771
772 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
773 if (prio_tc[j] == i) {
d81a6bdb 774 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 775 configure = true;
776 break;
777 }
778 }
779
780 if (!configure)
781 continue;
d81a6bdb 782 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
8e8dfe9f
IS		 783 }
784
ff6551ec
IS		 785 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
786}
787
8e8dfe9f 788static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 789 int mtu, bool pause_en)
8e8dfe9f
IS		 790{
791 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
792 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 793 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 794 u8 *prio_tc;
795
796 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 797 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 798
9f7ec052 799 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 800 pause_en, my_pfc);
8e8dfe9f
IS		 801}
802
56ade8fe
JP		 803static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
804{
805 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 806 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 807 int err;
808
9f7ec052 809 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 810 if (err)
811 return err;
763b4b70
YG		 812 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
813 if (err)
814 goto err_span_port_mtu_update;
ff6551ec
IS		 815 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
816 if (err)
817 goto err_port_mtu_set;
56ade8fe
JP		 818 dev->mtu = mtu;
819 return 0;
ff6551ec
IS		 820
821err_port_mtu_set:
763b4b70
YG		 822 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
823err_span_port_mtu_update:
9f7ec052 824 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 825 return err;
56ade8fe
JP		 826}
827
4bdcc6ca 828static int
fc1bbb0f
NF		 829mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
830 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 831{
832 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
833 struct mlxsw_sp_port_pcpu_stats *p;
834 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
835 u32 tx_dropped = 0;
836 unsigned int start;
837 int i;
838
839 for_each_possible_cpu(i) {
840 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
841 do {
842 start = u64_stats_fetch_begin_irq(&p->syncp);
843 rx_packets = p->rx_packets;
844 rx_bytes = p->rx_bytes;
845 tx_packets = p->tx_packets;
846 tx_bytes = p->tx_bytes;
847 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
848
849 stats->rx_packets += rx_packets;
850 stats->rx_bytes += rx_bytes;
851 stats->tx_packets += tx_packets;
852 stats->tx_bytes += tx_bytes;
853 /* tx_dropped is u32, updated without syncp protection. */
854 tx_dropped += p->tx_dropped;
855 }
856 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 857 return 0;
858}
859
3df5b3c6 860static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
fc1bbb0f
NF		 861{
862 switch (attr_id) {
863 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
864 return true;
865 }
866
867 return false;
868}
869
4bdcc6ca
OG		 870static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
871 void *sp)
fc1bbb0f
NF		 872{
873 switch (attr_id) {
874 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
875 return mlxsw_sp_port_get_sw_stats64(dev, sp);
876 }
877
878 return -EINVAL;
879}
880
881static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
882 int prio, char *ppcnt_pl)
883{
884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
885 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
886
887 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
888 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
889}
890
891static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
892 struct rtnl_link_stats64 *stats)
893{
894 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
895 int err;
896
897 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
898 0, ppcnt_pl);
899 if (err)
900 goto out;
901
902 stats->tx_packets =
903 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
904 stats->rx_packets =
905 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
906 stats->tx_bytes =
907 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
908 stats->rx_bytes =
909 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
910 stats->multicast =
911 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
912
913 stats->rx_crc_errors =
914 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
915 stats->rx_frame_errors =
916 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
917
918 stats->rx_length_errors = (
919 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
920 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
921 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
922
923 stats->rx_errors = (stats->rx_crc_errors +
924 stats->rx_frame_errors + stats->rx_length_errors);
925
926out:
927 return err;
928}
929
930static void update_stats_cache(struct work_struct *work)
931{
932 struct mlxsw_sp_port *mlxsw_sp_port =
933 container_of(work, struct mlxsw_sp_port,
934 hw_stats.update_dw.work);
935
936 if (!netif_carrier_ok(mlxsw_sp_port->dev))
937 goto out;
938
939 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
940 mlxsw_sp_port->hw_stats.cache);
941
942out:
943 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
944 MLXSW_HW_STATS_UPDATE_TIME);
945}
946
947/* Return the stats from a cache that is updated periodically,
948 * as this function might get called in an atomic context.
949 */
950static struct rtnl_link_stats64 *
951mlxsw_sp_port_get_stats64(struct net_device *dev,
952 struct rtnl_link_stats64 *stats)
953{
954 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
955
956 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
957
56ade8fe
JP		 958 return stats;
959}
960
961int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
962 u16 vid_end, bool is_member, bool untagged)
963{
964 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
965 char *spvm_pl;
966 int err;
967
968 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
969 if (!spvm_pl)
970 return -ENOMEM;
971
972 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
973 vid_end, is_member, untagged);
974 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
975 kfree(spvm_pl);
976 return err;
977}
978
979static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
980{
981 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
982 u16 vid, last_visited_vid;
983 int err;
984
985 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
986 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
987 vid);
988 if (err) {
989 last_visited_vid = vid;
990 goto err_port_vid_to_fid_set;
991 }
992 }
993
994 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
995 if (err) {
996 last_visited_vid = VLAN_N_VID;
997 goto err_port_vid_to_fid_set;
998 }
999
1000 return 0;
1001
1002err_port_vid_to_fid_set:
1003 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1004 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1005 vid);
1006 return err;
1007}
1008
1009static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1010{
1011 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1012 u16 vid;
1013 int err;
1014
1015 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1016 if (err)
1017 return err;
1018
1019 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1020 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1021 vid, vid);
1022 if (err)
1023 return err;
1024 }
1025
1026 return 0;
1027}
1028
7f71eb46 1029static struct mlxsw_sp_port *
0355b59f 1030mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
7f71eb46
IS		 1031{
1032 struct mlxsw_sp_port *mlxsw_sp_vport;
1033
1034 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1035 if (!mlxsw_sp_vport)
1036 return NULL;
1037
1038 /* dev will be set correctly after the VLAN device is linked
1039 * with the real device. In case of bridge SELF invocation, dev
1040 * will remain as is.
1041 */
1042 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1043 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1044 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1045 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
272c4470
IS		 1046 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1047 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
0355b59f 1048 mlxsw_sp_vport->vport.vid = vid;
7f71eb46
IS		 1049
1050 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1051
1052 return mlxsw_sp_vport;
1053}
1054
1055static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1056{
1057 list_del(&mlxsw_sp_vport->vport.list);
1058 kfree(mlxsw_sp_vport);
1059}
1060
05978481
IS		 1061static int mlxsw_sp_port_add_vid(struct net_device *dev,
1062 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1063{
1064 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 1065 struct mlxsw_sp_port *mlxsw_sp_vport;
52697a9e 1066 bool untagged = vid == 1;
56ade8fe
JP		 1067 int err;
1068
1069 /* VLAN 0 is added to HW filter when device goes up, but it is
1070 * reserved in our case, so simply return.
1071 */
1072 if (!vid)
1073 return 0;
1074
fa66d7e3 1075 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
56ade8fe 1076 return 0;
56ade8fe 1077
0355b59f 1078 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
fa66d7e3 1079 if (!mlxsw_sp_vport)
0355b59f 1080 return -ENOMEM;
56ade8fe 1081
56ade8fe
JP		 1082 /* When adding the first VLAN interface on a bridged port we need to
1083 * transition all the active 802.1Q bridge VLANs to use explicit
1084 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1085 */
7f71eb46 1086 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe 1087 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
fa66d7e3 1088 if (err)
7f71eb46 1089 goto err_port_vp_mode_trans;
56ade8fe
JP		 1090 }
1091
52697a9e 1092 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
fa66d7e3 1093 if (err)
56ade8fe 1094 goto err_port_add_vid;
56ade8fe 1095
56ade8fe
JP		 1096 return 0;
1097
56ade8fe 1098err_port_add_vid:
7f71eb46
IS		 1099 if (list_is_singular(&mlxsw_sp_port->vports_list))
1100 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1101err_port_vp_mode_trans:
7f71eb46 1102 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
56ade8fe
JP		 1103 return err;
1104}
1105
32d863fb
IS		 1106static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1107 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1108{
1109 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 1110 struct mlxsw_sp_port *mlxsw_sp_vport;
1c800759 1111 struct mlxsw_sp_fid *f;
56ade8fe
JP		 1112
1113 /* VLAN 0 is removed from HW filter when device goes down, but
1114 * it is reserved in our case, so simply return.
1115 */
1116 if (!vid)
1117 return 0;
1118
7f71eb46 1119 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
7a35583e 1120 if (WARN_ON(!mlxsw_sp_vport))
56ade8fe 1121 return 0;
56ade8fe 1122
7a35583e 1123 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe 1124
1c800759
IS		 1125 /* Drop FID reference. If this was the last reference the
1126 * resources will be freed.
1127 */
1128 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1129 if (f && !WARN_ON(!f->leave))
1130 f->leave(mlxsw_sp_vport);
56ade8fe
JP		 1131
1132 /* When removing the last VLAN interface on a bridged port we need to
1133 * transition all active 802.1Q bridge VLANs to use VID to FID
1134 * mappings and set port's mode to VLAN mode.
1135 */
7a35583e
IS		 1136 if (list_is_singular(&mlxsw_sp_port->vports_list))
1137 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
56ade8fe 1138
7f71eb46
IS		 1139 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1140
56ade8fe
JP		 1141 return 0;
1142}
1143
2bf9a586
IS		 1144static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1145 size_t len)
1146{
1147 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1148 u8 module = mlxsw_sp_port->mapping.module;
1149 u8 width = mlxsw_sp_port->mapping.width;
1150 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1151 int err;
1152
2bf9a586
IS		 1153 if (!mlxsw_sp_port->split)
1154 err = snprintf(name, len, "p%d", module + 1);
1155 else
1156 err = snprintf(name, len, "p%ds%d", module + 1,
1157 lane / width);
1158
1159 if (err >= len)
1160 return -EINVAL;
1161
1162 return 0;
1163}
1164
763b4b70
YG		 1165static struct mlxsw_sp_port_mall_tc_entry *
1166mlxsw_sp_port_mirror_entry_find(struct mlxsw_sp_port *port,
1167 unsigned long cookie) {
1168 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1169
1170 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1171 if (mall_tc_entry->cookie == cookie)
1172 return mall_tc_entry;
1173
1174 return NULL;
1175}
1176
1177static int
1178mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1179 struct tc_cls_matchall_offload *cls,
1180 const struct tc_action *a,
1181 bool ingress)
1182{
1183 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1184 struct net *net = dev_net(mlxsw_sp_port->dev);
1185 enum mlxsw_sp_span_type span_type;
1186 struct mlxsw_sp_port *to_port;
1187 struct net_device *to_dev;
1188 int ifindex;
1189 int err;
1190
1191 ifindex = tcf_mirred_ifindex(a);
1192 to_dev = __dev_get_by_index(net, ifindex);
1193 if (!to_dev) {
1194 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1195 return -EINVAL;
1196 }
1197
1198 if (!mlxsw_sp_port_dev_check(to_dev)) {
1199 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
1200 return -ENOTSUPP;
1201 }
1202 to_port = netdev_priv(to_dev);
1203
1204 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1205 if (!mall_tc_entry)
1206 return -ENOMEM;
1207
1208 mall_tc_entry->cookie = cls->cookie;
1209 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1210 mall_tc_entry->mirror.to_local_port = to_port->local_port;
1211 mall_tc_entry->mirror.ingress = ingress;
1212 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1213
1214 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1215 err = mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1216 if (err)
1217 goto err_mirror_add;
1218 return 0;
1219
1220err_mirror_add:
1221 list_del(&mall_tc_entry->list);
1222 kfree(mall_tc_entry);
1223 return err;
1224}
1225
1226static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1227 __be16 protocol,
1228 struct tc_cls_matchall_offload *cls,
1229 bool ingress)
1230{
763b4b70 1231 const struct tc_action *a;
22dc13c8 1232 LIST_HEAD(actions);
763b4b70
YG		 1233 int err;
1234
86cb13e4 1235 if (!tc_single_action(cls->exts)) {
763b4b70
YG		 1236 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1237 return -ENOTSUPP;
1238 }
1239
22dc13c8
WC		 1240 tcf_exts_to_list(cls->exts, &actions);
1241 list_for_each_entry(a, &actions, list) {
5724b8b5
SL		 1242 if (!is_tcf_mirred_egress_mirror(a) ||
1243 protocol != htons(ETH_P_ALL)) {
86cb13e4 1244 return -ENOTSUPP;
5724b8b5 1245 }
86cb13e4 1246
763b4b70
YG		 1247 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, cls,
1248 a, ingress);
1249 if (err)
1250 return err;
763b4b70
YG		 1251 }
1252
1253 return 0;
1254}
1255
1256static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1257 struct tc_cls_matchall_offload *cls)
1258{
1259 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1260 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1261 enum mlxsw_sp_span_type span_type;
1262 struct mlxsw_sp_port *to_port;
1263
1264 mall_tc_entry = mlxsw_sp_port_mirror_entry_find(mlxsw_sp_port,
1265 cls->cookie);
1266 if (!mall_tc_entry) {
1267 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1268 return;
1269 }
1270
1271 switch (mall_tc_entry->type) {
1272 case MLXSW_SP_PORT_MALL_MIRROR:
1273 to_port = mlxsw_sp->ports[mall_tc_entry->mirror.to_local_port];
1274 span_type = mall_tc_entry->mirror.ingress ?
1275 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1276
1277 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
1278 break;
1279 default:
1280 WARN_ON(1);
1281 }
1282
1283 list_del(&mall_tc_entry->list);
1284 kfree(mall_tc_entry);
1285}
1286
1287static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1288 __be16 proto, struct tc_to_netdev *tc)
1289{
1290 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1291 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1292
1293 if (tc->type == TC_SETUP_MATCHALL) {
1294 switch (tc->cls_mall->command) {
1295 case TC_CLSMATCHALL_REPLACE:
1296 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1297 proto,
1298 tc->cls_mall,
1299 ingress);
1300 case TC_CLSMATCHALL_DESTROY:
1301 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1302 tc->cls_mall);
1303 return 0;
1304 default:
1305 return -EINVAL;
1306 }
1307 }
1308
1309 return -ENOTSUPP;
1310}
1311
56ade8fe
JP		 1312static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1313 .ndo_open = mlxsw_sp_port_open,
1314 .ndo_stop = mlxsw_sp_port_stop,
1315 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 1316 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 1317 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 1318 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1319 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1320 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 1321 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1322 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 1323 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1324 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
6cf3c971
JP		 1325 .ndo_neigh_construct = mlxsw_sp_router_neigh_construct,
1326 .ndo_neigh_destroy = mlxsw_sp_router_neigh_destroy,
56ade8fe
JP		 1327 .ndo_fdb_add = switchdev_port_fdb_add,
1328 .ndo_fdb_del = switchdev_port_fdb_del,
1329 .ndo_fdb_dump = switchdev_port_fdb_dump,
1330 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1331 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1332 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
2bf9a586 1333 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 1334};
1335
1336static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1337 struct ethtool_drvinfo *drvinfo)
1338{
1339 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1340 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1341
1342 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1343 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1344 sizeof(drvinfo->version));
1345 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1346 "%d.%d.%d",
1347 mlxsw_sp->bus_info->fw_rev.major,
1348 mlxsw_sp->bus_info->fw_rev.minor,
1349 mlxsw_sp->bus_info->fw_rev.subminor);
1350 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1351 sizeof(drvinfo->bus_info));
1352}
1353
9f7ec052
IS		 1354static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1355 struct ethtool_pauseparam *pause)
1356{
1357 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1358
1359 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1360 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1361}
1362
1363static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1364 struct ethtool_pauseparam *pause)
1365{
1366 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1367
1368 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1369 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1370 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1371
1372 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1373 pfcc_pl);
1374}
1375
1376static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1377 struct ethtool_pauseparam *pause)
1378{
1379 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1380 bool pause_en = pause->tx_pause || pause->rx_pause;
1381 int err;
1382
d81a6bdb
IS		 1383 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1384 netdev_err(dev, "PFC already enabled on port\n");
1385 return -EINVAL;
1386 }
1387
9f7ec052
IS		 1388 if (pause->autoneg) {
1389 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1390 return -EINVAL;
1391 }
1392
1393 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1394 if (err) {
1395 netdev_err(dev, "Failed to configure port's headroom\n");
1396 return err;
1397 }
1398
1399 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1400 if (err) {
1401 netdev_err(dev, "Failed to set PAUSE parameters\n");
1402 goto err_port_pause_configure;
1403 }
1404
1405 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1406 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1407
1408 return 0;
1409
1410err_port_pause_configure:
1411 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1412 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1413 return err;
1414}
1415
56ade8fe
JP		 1416struct mlxsw_sp_port_hw_stats {
1417 char str[ETH_GSTRING_LEN];
412791df 1418 u64 (*getter)(const char *payload);
56ade8fe
JP		 1419};
1420
7ed674bc 1421static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 1422 {
1423 .str = "a_frames_transmitted_ok",
1424 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1425 },
1426 {
1427 .str = "a_frames_received_ok",
1428 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1429 },
1430 {
1431 .str = "a_frame_check_sequence_errors",
1432 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1433 },
1434 {
1435 .str = "a_alignment_errors",
1436 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1437 },
1438 {
1439 .str = "a_octets_transmitted_ok",
1440 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1441 },
1442 {
1443 .str = "a_octets_received_ok",
1444 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1445 },
1446 {
1447 .str = "a_multicast_frames_xmitted_ok",
1448 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1449 },
1450 {
1451 .str = "a_broadcast_frames_xmitted_ok",
1452 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1453 },
1454 {
1455 .str = "a_multicast_frames_received_ok",
1456 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1457 },
1458 {
1459 .str = "a_broadcast_frames_received_ok",
1460 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1461 },
1462 {
1463 .str = "a_in_range_length_errors",
1464 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1465 },
1466 {
1467 .str = "a_out_of_range_length_field",
1468 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1469 },
1470 {
1471 .str = "a_frame_too_long_errors",
1472 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1473 },
1474 {
1475 .str = "a_symbol_error_during_carrier",
1476 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1477 },
1478 {
1479 .str = "a_mac_control_frames_transmitted",
1480 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1481 },
1482 {
1483 .str = "a_mac_control_frames_received",
1484 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1485 },
1486 {
1487 .str = "a_unsupported_opcodes_received",
1488 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1489 },
1490 {
1491 .str = "a_pause_mac_ctrl_frames_received",
1492 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1493 },
1494 {
1495 .str = "a_pause_mac_ctrl_frames_xmitted",
1496 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1497 },
1498};
1499
1500#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1501
7ed674bc
IS		 1502static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1503 {
1504 .str = "rx_octets_prio",
1505 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1506 },
1507 {
1508 .str = "rx_frames_prio",
1509 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1510 },
1511 {
1512 .str = "tx_octets_prio",
1513 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1514 },
1515 {
1516 .str = "tx_frames_prio",
1517 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1518 },
1519 {
1520 .str = "rx_pause_prio",
1521 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1522 },
1523 {
1524 .str = "rx_pause_duration_prio",
1525 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1526 },
1527 {
1528 .str = "tx_pause_prio",
1529 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1530 },
1531 {
1532 .str = "tx_pause_duration_prio",
1533 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1534 },
1535};
1536
1537#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1538
412791df 1539static u64 mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get(const char *ppcnt_pl)
df4750e8
IS		 1540{
1541 u64 transmit_queue = mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1542
1543 return MLXSW_SP_CELLS_TO_BYTES(transmit_queue);
1544}
1545
1546static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1547 {
1548 .str = "tc_transmit_queue_tc",
1549 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get,
1550 },
1551 {
1552 .str = "tc_no_buffer_discard_uc_tc",
1553 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1554 },
1555};
1556
1557#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1558
7ed674bc 1559#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 1560 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1561 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 1562 IEEE_8021QAZ_MAX_TCS)
1563
1564static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1565{
1566 int i;
1567
1568 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1569 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1570 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1571 *p += ETH_GSTRING_LEN;
1572 }
1573}
1574
df4750e8
IS		 1575static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1576{
1577 int i;
1578
1579 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1580 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1581 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1582 *p += ETH_GSTRING_LEN;
1583 }
1584}
1585
56ade8fe
JP		 1586static void mlxsw_sp_port_get_strings(struct net_device *dev,
1587 u32 stringset, u8 *data)
1588{
1589 u8 *p = data;
1590 int i;
1591
1592 switch (stringset) {
1593 case ETH_SS_STATS:
1594 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1595 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1596 ETH_GSTRING_LEN);
1597 p += ETH_GSTRING_LEN;
1598 }
7ed674bc
IS		 1599
1600 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1601 mlxsw_sp_port_get_prio_strings(&p, i);
1602
df4750e8
IS		 1603 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1604 mlxsw_sp_port_get_tc_strings(&p, i);
1605
56ade8fe
JP		 1606 break;
1607 }
1608}
1609
3a66ee38
IS		 1610static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1611 enum ethtool_phys_id_state state)
1612{
1613 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1614 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1615 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1616 bool active;
1617
1618 switch (state) {
1619 case ETHTOOL_ID_ACTIVE:
1620 active = true;
1621 break;
1622 case ETHTOOL_ID_INACTIVE:
1623 active = false;
1624 break;
1625 default:
1626 return -EOPNOTSUPP;
1627 }
1628
1629 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1630 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1631}
1632
7ed674bc
IS		 1633static int
1634mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1635 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1636{
1637 switch (grp) {
1638 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1639 *p_hw_stats = mlxsw_sp_port_hw_stats;
1640 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1641 break;
1642 case MLXSW_REG_PPCNT_PRIO_CNT:
1643 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1644 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1645 break;
df4750e8
IS		 1646 case MLXSW_REG_PPCNT_TC_CNT:
1647 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1648 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1649 break;
7ed674bc
IS		 1650 default:
1651 WARN_ON(1);
1652 return -ENOTSUPP;
1653 }
1654 return 0;
1655}
1656
1657static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1658 enum mlxsw_reg_ppcnt_grp grp, int prio,
1659 u64 *data, int data_index)
56ade8fe 1660{
7ed674bc 1661 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 1662 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 1663 int i, len;
56ade8fe
JP		 1664 int err;
1665
7ed674bc
IS		 1666 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1667 if (err)
1668 return;
fc1bbb0f 1669 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
7ed674bc 1670 for (i = 0; i < len; i++)
faac0ff0 1671 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
7ed674bc
IS		 1672}
1673
1674static void mlxsw_sp_port_get_stats(struct net_device *dev,
1675 struct ethtool_stats *stats, u64 *data)
1676{
1677 int i, data_index = 0;
1678
1679 /* IEEE 802.3 Counters */
1680 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1681 data, data_index);
1682 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1683
1684 /* Per-Priority Counters */
1685 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1686 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1687 data, data_index);
1688 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1689 }
df4750e8
IS		 1690
1691 /* Per-TC Counters */
1692 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1693 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1694 data, data_index);
1695 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1696 }
56ade8fe
JP		 1697}
1698
1699static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1700{
1701 switch (sset) {
1702 case ETH_SS_STATS:
7ed674bc 1703 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 1704 default:
1705 return -EOPNOTSUPP;
1706 }
1707}
1708
1709struct mlxsw_sp_port_link_mode {
b9d66a36 1710 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 1711 u32 mask;
56ade8fe
JP		 1712 u32 speed;
1713};
1714
1715static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1716 {
1717 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 1718 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1719 .speed = SPEED_100,
56ade8fe
JP		 1720 },
1721 {
1722 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1723 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 1724 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1725 .speed = SPEED_1000,
56ade8fe
JP		 1726 },
1727 {
1728 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 1729 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1730 .speed = SPEED_10000,
56ade8fe
JP		 1731 },
1732 {
1733 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1734 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 1735 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1736 .speed = SPEED_10000,
56ade8fe
JP		 1737 },
1738 {
1739 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1740 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1741 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1742 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 1743 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1744 .speed = SPEED_10000,
56ade8fe
JP		 1745 },
1746 {
1747 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 1748 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
1749 .speed = SPEED_20000,
56ade8fe
JP		 1750 },
1751 {
1752 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 1753 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1754 .speed = SPEED_40000,
56ade8fe
JP		 1755 },
1756 {
1757 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 1758 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1759 .speed = SPEED_40000,
56ade8fe
JP		 1760 },
1761 {
1762 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 1763 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1764 .speed = SPEED_40000,
56ade8fe
JP		 1765 },
1766 {
1767 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 1768 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1769 .speed = SPEED_40000,
1770 },
1771 {
1772 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1773 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1774 .speed = SPEED_25000,
1775 },
1776 {
1777 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1778 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1779 .speed = SPEED_25000,
1780 },
1781 {
1782 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1783 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1784 .speed = SPEED_25000,
56ade8fe
JP		 1785 },
1786 {
b9d66a36
IS		 1787 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1788 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1789 .speed = SPEED_25000,
56ade8fe
JP		 1790 },
1791 {
b9d66a36
IS		 1792 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1793 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1794 .speed = SPEED_50000,
1795 },
1796 {
1797 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1798 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1799 .speed = SPEED_50000,
1800 },
1801 {
1802 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1803 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1804 .speed = SPEED_50000,
56ade8fe
JP		 1805 },
1806 {
1807 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 1808 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
1809 .speed = SPEED_56000,
56ade8fe
JP		 1810 },
1811 {
b9d66a36
IS		 1812 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1813 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
1814 .speed = SPEED_56000,
1815 },
1816 {
1817 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1818 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
1819 .speed = SPEED_56000,
1820 },
1821 {
1822 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1823 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
1824 .speed = SPEED_56000,
1825 },
1826 {
1827 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
1828 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1829 .speed = SPEED_100000,
1830 },
1831 {
1832 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
1833 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1834 .speed = SPEED_100000,
1835 },
1836 {
1837 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
1838 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1839 .speed = SPEED_100000,
1840 },
1841 {
1842 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1843 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1844 .speed = SPEED_100000,
56ade8fe
JP		 1845 },
1846};
1847
1848#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1849
b9d66a36
IS		 1850static void
1851mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
1852 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1853{
1854 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1855 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1856 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1857 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1858 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1859 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 1860 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 1861
1862 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1863 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1864 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1865 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1866 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 1867 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 1868}
1869
b9d66a36 1870static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 1871{
56ade8fe
JP		 1872 int i;
1873
1874 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1875 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 1876 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1877 mode);
56ade8fe 1878 }
56ade8fe
JP		 1879}
1880
1881static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 1882 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1883{
1884 u32 speed = SPEED_UNKNOWN;
1885 u8 duplex = DUPLEX_UNKNOWN;
1886 int i;
1887
1888 if (!carrier_ok)
1889 goto out;
1890
1891 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1892 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1893 speed = mlxsw_sp_port_link_mode[i].speed;
1894 duplex = DUPLEX_FULL;
1895 break;
1896 }
1897 }
1898out:
b9d66a36
IS		 1899 cmd->base.speed = speed;
1900 cmd->base.duplex = duplex;
56ade8fe
JP		 1901}
1902
1903static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1904{
1905 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1906 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1907 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1908 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1909 return PORT_FIBRE;
1910
1911 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1912 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1913 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1914 return PORT_DA;
1915
1916 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1917 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1918 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1919 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1920 return PORT_NONE;
1921
1922 return PORT_OTHER;
1923}
1924
b9d66a36
IS		 1925static u32
1926mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 1927{
1928 u32 ptys_proto = 0;
1929 int i;
1930
1931 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 1932 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1933 cmd->link_modes.advertising))
56ade8fe
JP		 1934 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1935 }
1936 return ptys_proto;
1937}
1938
1939static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1940{
1941 u32 ptys_proto = 0;
1942 int i;
1943
1944 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1945 if (speed == mlxsw_sp_port_link_mode[i].speed)
1946 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1947 }
1948 return ptys_proto;
1949}
1950
18f1e70c
IS		 1951static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1952{
1953 u32 ptys_proto = 0;
1954 int i;
1955
1956 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1957 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1958 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1959 }
1960 return ptys_proto;
1961}
1962
b9d66a36
IS		 1963static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
1964 struct ethtool_link_ksettings *cmd)
1965{
1966 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
1967 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
1968 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
1969
1970 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
1971 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
1972}
1973
1974static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
1975 struct ethtool_link_ksettings *cmd)
56ade8fe 1976{
b9d66a36
IS		 1977 if (!autoneg)
1978 return;
1979
1980 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
1981 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
1982}
1983
1984static void
1985mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
1986 struct ethtool_link_ksettings *cmd)
1987{
1988 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
1989 return;
1990
1991 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
1992 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
1993}
1994
1995static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
1996 struct ethtool_link_ksettings *cmd)
1997{
1998 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 1999 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2000 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2001 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2002 u8 autoneg_status;
0c83f88c 2003 bool autoneg;
56ade8fe
JP		 2004 int err;
2005
b9d66a36 2006 autoneg = mlxsw_sp_port->link.autoneg;
401c8b4e 2007 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
b9d66a36
IS		 2008 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2009 if (err)
2010 return err;
401c8b4e
ER		 2011 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2012 &eth_proto_oper);
b9d66a36
IS		 2013
2014 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2015
b9d66a36
IS		 2016 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2017
2018 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2019 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2020 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2021
2022 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2023 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2024 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2025 cmd);
2026
2027 return 0;
2028}
2029
2030static int
2031mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2032 const struct ethtool_link_ksettings *cmd)
2033{
2034 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2035 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2036 char ptys_pl[MLXSW_REG_PTYS_LEN];
2037 u32 eth_proto_cap, eth_proto_new;
2038 bool autoneg;
2039 int err;
56ade8fe 2040
401c8b4e 2041 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
56ade8fe 2042 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2043 if (err)
56ade8fe 2044 return err;
401c8b4e 2045 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
b9d66a36
IS		 2046
2047 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2048 eth_proto_new = autoneg ?
2049 mlxsw_sp_to_ptys_advert_link(cmd) :
2050 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2051
2052 eth_proto_new = eth_proto_new & eth_proto_cap;
2053 if (!eth_proto_new) {
b9d66a36 2054 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2055 return -EINVAL;
2056 }
56ade8fe 2057
401c8b4e
ER		 2058 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2059 eth_proto_new);
56ade8fe 2060 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2061 if (err)
56ade8fe 2062 return err;
56ade8fe 2063
6277d46b 2064 if (!netif_running(dev))
56ade8fe
JP		 2065 return 0;
2066
0c83f88c
IS		 2067 mlxsw_sp_port->link.autoneg = autoneg;
2068
b9d66a36
IS		 2069 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2070 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2071
2072 return 0;
2073}
2074
2075static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2076 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2077 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2078 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2079 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2080 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2081 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2082 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2083 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2084 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2085 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
56ade8fe
JP		 2086};
2087
18f1e70c
IS		 2088static int
2089mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2090{
2091 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2092 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2093 char ptys_pl[MLXSW_REG_PTYS_LEN];
2094 u32 eth_proto_admin;
2095
2096 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
401c8b4e
ER		 2097 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2098 eth_proto_admin);
18f1e70c
IS		 2099 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2100}
2101
8e8dfe9f
IS		 2102int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2103 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2104 bool dwrr, u8 dwrr_weight)
90183b98
IS		 2105{
2106 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2107 char qeec_pl[MLXSW_REG_QEEC_LEN];
2108
2109 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2110 next_index);
2111 mlxsw_reg_qeec_de_set(qeec_pl, true);
2112 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2113 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2114 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2115}
2116
cc7cf517
IS		 2117int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2118 enum mlxsw_reg_qeec_hr hr, u8 index,
2119 u8 next_index, u32 maxrate)
90183b98
IS		 2120{
2121 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2122 char qeec_pl[MLXSW_REG_QEEC_LEN];
2123
2124 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2125 next_index);
2126 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2127 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2128 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2129}
2130
8e8dfe9f
IS		 2131int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2132 u8 switch_prio, u8 tclass)
90183b98
IS		 2133{
2134 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2135 char qtct_pl[MLXSW_REG_QTCT_LEN];
2136
2137 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2138 tclass);
2139 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2140}
2141
2142static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2143{
2144 int err, i;
2145
2146 /* Setup the elements hierarcy, so that each TC is linked to
2147 * one subgroup, which are all member in the same group.
2148 */
2149 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2150 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2151 0);
2152 if (err)
2153 return err;
2154 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2155 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2156 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2157 0, false, 0);
2158 if (err)
2159 return err;
2160 }
2161 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2162 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2163 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2164 false, 0);
2165 if (err)
2166 return err;
2167 }
2168
2169 /* Make sure the max shaper is disabled in all hierarcies that
2170 * support it.
2171 */
2172 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2173 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2174 MLXSW_REG_QEEC_MAS_DIS);
2175 if (err)
2176 return err;
2177 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2178 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2179 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2180 i, 0,
2181 MLXSW_REG_QEEC_MAS_DIS);
2182 if (err)
2183 return err;
2184 }
2185 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2186 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2187 MLXSW_REG_QEEC_HIERARCY_TC,
2188 i, i,
2189 MLXSW_REG_QEEC_MAS_DIS);
2190 if (err)
2191 return err;
2192 }
2193
2194 /* Map all priorities to traffic class 0. */
2195 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2196 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2197 if (err)
2198 return err;
2199 }
2200
2201 return 0;
2202}
2203
05978481
IS		 2204static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2205{
2206 mlxsw_sp_port->pvid = 1;
2207
2208 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2209}
2210
2211static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2212{
2213 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2214}
2215
67963a33
JP		 2216static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2217 bool split, u8 module, u8 width, u8 lane)
56ade8fe
JP		 2218{
2219 struct mlxsw_sp_port *mlxsw_sp_port;
2220 struct net_device *dev;
bd40e9d6 2221 size_t bytes;
56ade8fe
JP		 2222 int err;
2223
2224 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2225 if (!dev)
2226 return -ENOMEM;
f20a91f1 2227 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 2228 mlxsw_sp_port = netdev_priv(dev);
2229 mlxsw_sp_port->dev = dev;
2230 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2231 mlxsw_sp_port->local_port = local_port;
18f1e70c 2232 mlxsw_sp_port->split = split;
d664b41e
IS		 2233 mlxsw_sp_port->mapping.module = module;
2234 mlxsw_sp_port->mapping.width = width;
2235 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 2236 mlxsw_sp_port->link.autoneg = 1;
bd40e9d6
IS		 2237 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2238 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2239 if (!mlxsw_sp_port->active_vlans) {
2240 err = -ENOMEM;
2241 goto err_port_active_vlans_alloc;
2242 }
fc1273af
ER		 2243 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2244 if (!mlxsw_sp_port->untagged_vlans) {
2245 err = -ENOMEM;
2246 goto err_port_untagged_vlans_alloc;
2247 }
7f71eb46 2248 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
763b4b70 2249 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 2250
2251 mlxsw_sp_port->pcpu_stats =
2252 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2253 if (!mlxsw_sp_port->pcpu_stats) {
2254 err = -ENOMEM;
2255 goto err_alloc_stats;
2256 }
2257
fc1bbb0f
NF		 2258 mlxsw_sp_port->hw_stats.cache =
2259 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2260
2261 if (!mlxsw_sp_port->hw_stats.cache) {
2262 err = -ENOMEM;
2263 goto err_alloc_hw_stats;
2264 }
2265 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2266 &update_stats_cache);
2267
56ade8fe
JP		 2268 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2269 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2270
3247ff2b
IS		 2271 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2272 if (err) {
2273 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2274 mlxsw_sp_port->local_port);
2275 goto err_port_swid_set;
2276 }
2277
56ade8fe
JP		 2278 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2279 if (err) {
2280 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2281 mlxsw_sp_port->local_port);
2282 goto err_dev_addr_init;
2283 }
2284
2285 netif_carrier_off(dev);
2286
2287 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 2288 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2289 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 2290
d894be57
JW		 2291 dev->min_mtu = 0;
2292 dev->max_mtu = ETH_MAX_MTU;
2293
56ade8fe
JP		 2294 /* Each packet needs to have a Tx header (metadata) on top all other
2295 * headers.
2296 */
feb7d387 2297 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 2298
56ade8fe
JP		 2299 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2300 if (err) {
2301 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2302 mlxsw_sp_port->local_port);
2303 goto err_port_system_port_mapping_set;
2304 }
2305
18f1e70c
IS		 2306 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2307 if (err) {
2308 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2309 mlxsw_sp_port->local_port);
2310 goto err_port_speed_by_width_set;
2311 }
2312
56ade8fe
JP		 2313 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2314 if (err) {
2315 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2316 mlxsw_sp_port->local_port);
2317 goto err_port_mtu_set;
2318 }
2319
2320 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2321 if (err)
2322 goto err_port_admin_status_set;
2323
2324 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2325 if (err) {
2326 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2327 mlxsw_sp_port->local_port);
2328 goto err_port_buffers_init;
2329 }
2330
90183b98
IS		 2331 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2332 if (err) {
2333 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2334 mlxsw_sp_port->local_port);
2335 goto err_port_ets_init;
2336 }
2337
f00817df
IS		 2338 /* ETS and buffers must be initialized before DCB. */
2339 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2340 if (err) {
2341 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2342 mlxsw_sp_port->local_port);
2343 goto err_port_dcb_init;
2344 }
2345
05978481
IS		 2346 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2347 if (err) {
2348 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2349 mlxsw_sp_port->local_port);
2350 goto err_port_pvid_vport_create;
2351 }
2352
56ade8fe 2353 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 2354 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 2355 err = register_netdev(dev);
2356 if (err) {
2357 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2358 mlxsw_sp_port->local_port);
2359 goto err_register_netdev;
2360 }
2361
d808c7e4
ER		 2362 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2363 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2364 module);
fc1bbb0f 2365 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
56ade8fe
JP		 2366 return 0;
2367
56ade8fe 2368err_register_netdev:
2f25844c 2369 mlxsw_sp->ports[local_port] = NULL;
0583272d 2370 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
05978481
IS		 2371 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2372err_port_pvid_vport_create:
4de34eb5 2373 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 2374err_port_dcb_init:
90183b98 2375err_port_ets_init:
56ade8fe
JP		 2376err_port_buffers_init:
2377err_port_admin_status_set:
2378err_port_mtu_set:
18f1e70c 2379err_port_speed_by_width_set:
56ade8fe 2380err_port_system_port_mapping_set:
56ade8fe 2381err_dev_addr_init:
3247ff2b
IS		 2382 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2383err_port_swid_set:
fc1bbb0f
NF		 2384 kfree(mlxsw_sp_port->hw_stats.cache);
2385err_alloc_hw_stats:
56ade8fe
JP		 2386 free_percpu(mlxsw_sp_port->pcpu_stats);
2387err_alloc_stats:
fc1273af
ER		 2388 kfree(mlxsw_sp_port->untagged_vlans);
2389err_port_untagged_vlans_alloc:
bd40e9d6
IS		 2390 kfree(mlxsw_sp_port->active_vlans);
2391err_port_active_vlans_alloc:
56ade8fe
JP		 2392 free_netdev(dev);
2393 return err;
2394}
2395
67963a33
JP		 2396static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2397 bool split, u8 module, u8 width, u8 lane)
2398{
2399 int err;
2400
2401 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2402 if (err) {
2403 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2404 local_port);
2405 return err;
2406 }
2407 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, false,
2408 module, width, lane);
2409 if (err)
2410 goto err_port_create;
2411 return 0;
2412
2413err_port_create:
2414 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2415 return err;
2416}
2417
2418static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
56ade8fe
JP		 2419{
2420 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2421
fc1bbb0f 2422 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
67963a33 2423 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
56ade8fe 2424 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 2425 mlxsw_sp->ports[local_port] = NULL;
0583272d 2426 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
05978481 2427 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
f00817df 2428 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8
IS		 2429 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2430 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
56ade8fe 2431 free_percpu(mlxsw_sp_port->pcpu_stats);
fc1bbb0f 2432 kfree(mlxsw_sp_port->hw_stats.cache);
fc1273af 2433 kfree(mlxsw_sp_port->untagged_vlans);
bd40e9d6 2434 kfree(mlxsw_sp_port->active_vlans);
32d863fb 2435 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
56ade8fe
JP		 2436 free_netdev(mlxsw_sp_port->dev);
2437}
2438
67963a33
JP		 2439static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2440{
2441 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2442 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2443}
2444
f83e2102
JP		 2445static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2446{
2447 return mlxsw_sp->ports[local_port] != NULL;
2448}
2449
56ade8fe
JP		 2450static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2451{
2452 int i;
2453
2454 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
f83e2102
JP		 2455 if (mlxsw_sp_port_created(mlxsw_sp, i))
2456 mlxsw_sp_port_remove(mlxsw_sp, i);
56ade8fe
JP		 2457 kfree(mlxsw_sp->ports);
2458}
2459
2460static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2461{
d664b41e 2462 u8 module, width, lane;
56ade8fe
JP		 2463 size_t alloc_size;
2464 int i;
2465 int err;
2466
2467 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
2468 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2469 if (!mlxsw_sp->ports)
2470 return -ENOMEM;
2471
2472 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
558c2d5e 2473 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 2474 &width, &lane);
558c2d5e
IS		 2475 if (err)
2476 goto err_port_module_info_get;
2477 if (!width)
2478 continue;
2479 mlxsw_sp->port_to_module[i] = module;
67963a33
JP		 2480 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2481 module, width, lane);
56ade8fe
JP		 2482 if (err)
2483 goto err_port_create;
2484 }
2485 return 0;
2486
2487err_port_create:
558c2d5e 2488err_port_module_info_get:
56ade8fe 2489 for (i--; i >= 1; i--)
f83e2102
JP		 2490 if (mlxsw_sp_port_created(mlxsw_sp, i))
2491 mlxsw_sp_port_remove(mlxsw_sp, i);
56ade8fe
JP		 2492 kfree(mlxsw_sp->ports);
2493 return err;
2494}
2495
18f1e70c
IS		 2496static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2497{
2498 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2499
2500 return local_port - offset;
2501}
2502
be94535f
IS		 2503static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2504 u8 module, unsigned int count)
2505{
2506 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2507 int err, i;
2508
2509 for (i = 0; i < count; i++) {
2510 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2511 width, i * width);
2512 if (err)
2513 goto err_port_module_map;
2514 }
2515
2516 for (i = 0; i < count; i++) {
2517 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2518 if (err)
2519 goto err_port_swid_set;
2520 }
2521
2522 for (i = 0; i < count; i++) {
2523 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 2524 module, width, i * width);
be94535f
IS		 2525 if (err)
2526 goto err_port_create;
2527 }
2528
2529 return 0;
2530
2531err_port_create:
2532 for (i--; i >= 0; i--)
f83e2102
JP		 2533 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2534 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
be94535f
IS		 2535 i = count;
2536err_port_swid_set:
2537 for (i--; i >= 0; i--)
2538 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2539 MLXSW_PORT_SWID_DISABLED_PORT);
2540 i = count;
2541err_port_module_map:
2542 for (i--; i >= 0; i--)
2543 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2544 return err;
2545}
2546
2547static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2548 u8 base_port, unsigned int count)
2549{
2550 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2551 int i;
2552
2553 /* Split by four means we need to re-create two ports, otherwise
2554 * only one.
2555 */
2556 count = count / 2;
2557
2558 for (i = 0; i < count; i++) {
2559 local_port = base_port + i * 2;
2560 module = mlxsw_sp->port_to_module[local_port];
2561
2562 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2563 0);
2564 }
2565
2566 for (i = 0; i < count; i++)
2567 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2568
2569 for (i = 0; i < count; i++) {
2570 local_port = base_port + i * 2;
2571 module = mlxsw_sp->port_to_module[local_port];
2572
2573 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 2574 width, 0);
be94535f
IS		 2575 }
2576}
2577
b2f10571
JP		 2578static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2579 unsigned int count)
18f1e70c 2580{
b2f10571 2581 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2582 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 2583 u8 module, cur_width, base_port;
2584 int i;
2585 int err;
2586
2587 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2588 if (!mlxsw_sp_port) {
2589 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2590 local_port);
2591 return -EINVAL;
2592 }
2593
d664b41e
IS		 2594 module = mlxsw_sp_port->mapping.module;
2595 cur_width = mlxsw_sp_port->mapping.width;
2596
18f1e70c
IS		 2597 if (count != 2 && count != 4) {
2598 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2599 return -EINVAL;
2600 }
2601
18f1e70c
IS		 2602 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2603 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2604 return -EINVAL;
2605 }
2606
2607 /* Make sure we have enough slave (even) ports for the split. */
2608 if (count == 2) {
2609 base_port = local_port;
2610 if (mlxsw_sp->ports[base_port + 1]) {
2611 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2612 return -EINVAL;
2613 }
2614 } else {
2615 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2616 if (mlxsw_sp->ports[base_port + 1] ||
2617 mlxsw_sp->ports[base_port + 3]) {
2618 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2619 return -EINVAL;
2620 }
2621 }
2622
2623 for (i = 0; i < count; i++)
f83e2102
JP		 2624 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2625 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 2626
be94535f
IS		 2627 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2628 if (err) {
2629 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2630 goto err_port_split_create;
18f1e70c
IS		 2631 }
2632
2633 return 0;
2634
be94535f
IS		 2635err_port_split_create:
2636 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2637 return err;
2638}
2639
b2f10571 2640static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 2641{
b2f10571 2642 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2643 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 2644 u8 cur_width, base_port;
18f1e70c
IS		 2645 unsigned int count;
2646 int i;
18f1e70c
IS		 2647
2648 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2649 if (!mlxsw_sp_port) {
2650 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2651 local_port);
2652 return -EINVAL;
2653 }
2654
2655 if (!mlxsw_sp_port->split) {
2656 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2657 return -EINVAL;
2658 }
2659
d664b41e 2660 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 2661 count = cur_width == 1 ? 4 : 2;
2662
2663 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2664
2665 /* Determine which ports to remove. */
2666 if (count == 2 && local_port >= base_port + 2)
2667 base_port = base_port + 2;
2668
2669 for (i = 0; i < count; i++)
f83e2102
JP		 2670 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2671 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 2672
be94535f 2673 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2674
2675 return 0;
2676}
2677
56ade8fe
JP		 2678static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2679 char *pude_pl, void *priv)
2680{
2681 struct mlxsw_sp *mlxsw_sp = priv;
2682 struct mlxsw_sp_port *mlxsw_sp_port;
2683 enum mlxsw_reg_pude_oper_status status;
2684 u8 local_port;
2685
2686 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2687 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 2688 if (!mlxsw_sp_port)
56ade8fe 2689 return;
56ade8fe
JP		 2690
2691 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2692 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2693 netdev_info(mlxsw_sp_port->dev, "link up\n");
2694 netif_carrier_on(mlxsw_sp_port->dev);
2695 } else {
2696 netdev_info(mlxsw_sp_port->dev, "link down\n");
2697 netif_carrier_off(mlxsw_sp_port->dev);
2698 }
2699}
2700
14eeda99
NF		 2701static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2702 u8 local_port, void *priv)
56ade8fe
JP		 2703{
2704 struct mlxsw_sp *mlxsw_sp = priv;
2705 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2706 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2707
2708 if (unlikely(!mlxsw_sp_port)) {
2709 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2710 local_port);
2711 return;
2712 }
2713
2714 skb->dev = mlxsw_sp_port->dev;
2715
2716 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2717 u64_stats_update_begin(&pcpu_stats->syncp);
2718 pcpu_stats->rx_packets++;
2719 pcpu_stats->rx_bytes += skb->len;
2720 u64_stats_update_end(&pcpu_stats->syncp);
2721
2722 skb->protocol = eth_type_trans(skb, skb->dev);
2723 netif_receive_skb(skb);
2724}
2725
1c6c6d22
IS		 2726static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2727 void *priv)
2728{
2729 skb->offload_fwd_mark = 1;
14eeda99 2730 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
1c6c6d22
IS		 2731}
2732
d570b7ee 2733#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _is_ctrl) \
0fb78a4e
NF		 2734 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
2735 _is_ctrl, RX, DISCARD)
14eeda99 2736
d570b7ee 2737#define MLXSW_SP_RXL_MARK(_trap_id, _action, _is_ctrl) \
14eeda99 2738 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
0fb78a4e 2739 _is_ctrl, RX, DISCARD)
93393b33 2740
4544913e
NF		 2741static const struct mlxsw_listener mlxsw_sp_listener[] = {
2742 /* Events */
0fb78a4e 2743 MLXSW_EVENTL(mlxsw_sp_pude_event_func, PUDE, EMAD),
ee4a60d8 2744 /* L2 traps */
d570b7ee
NF		 2745 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, true),
2746 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, true),
2747 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, true),
2748 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, false),
2749 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, false),
2750 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, false),
2751 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, false),
2752 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, false),
2753 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, false),
2754 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, false),
2755 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, false),
93393b33 2756 /* L3 traps */
d570b7ee
NF		 2757 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, false),
2758 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, false),
2759 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, false),
2760 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, false),
2761 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, false),
2762 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, false),
2763 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, false),
616d8040 2764 MLXSW_SP_RXL_MARK(BGP_IPV4, TRAP_TO_CPU, false),
56ade8fe
JP		 2765};
2766
579c82e4 2767static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
56ade8fe
JP		 2768{
2769 char htgt_pl[MLXSW_REG_HTGT_LEN];
579c82e4
NF		 2770 int max_trap_groups;
2771 u8 priority, tc;
2772 int i, err;
2773
2774 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2775 return -EIO;
2776
2777 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
2778
2779 for (i = 0; i < max_trap_groups; i++) {
2780 switch (i) {
2781 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
2782 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
2783 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
2784 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2785 tc = MLXSW_REG_HTGT_DEFAULT_TC;
2786 break;
2787 default:
2788 continue;
2789 }
2790 mlxsw_reg_htgt_pack(htgt_pl, i, MLXSW_REG_HTGT_INVALID_POLICER,
2791 priority, tc);
2792 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2793 if (err)
2794 return err;
2795 }
2796
2797 return 0;
2798}
2799
2800static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2801{
56ade8fe
JP		 2802 int i;
2803 int err;
2804
579c82e4 2805 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
56ade8fe
JP		 2806 if (err)
2807 return err;
2808
4544913e 2809 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 2810 err = mlxsw_core_trap_register(mlxsw_sp->core,
4544913e 2811 &mlxsw_sp_listener[i],
14eeda99 2812 mlxsw_sp);
56ade8fe 2813 if (err)
4544913e 2814 goto err_listener_register;
56ade8fe 2815
56ade8fe
JP		 2816 }
2817 return 0;
2818
4544913e 2819err_listener_register:
56ade8fe 2820 for (i--; i >= 0; i--) {
14eeda99 2821 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 2822 &mlxsw_sp_listener[i],
14eeda99 2823 mlxsw_sp);
56ade8fe
JP		 2824 }
2825 return err;
2826}
2827
2828static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2829{
56ade8fe
JP		 2830 int i;
2831
4544913e 2832 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 2833 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 2834 &mlxsw_sp_listener[i],
14eeda99 2835 mlxsw_sp);
56ade8fe
JP		 2836 }
2837}
2838
2839static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2840 enum mlxsw_reg_sfgc_type type,
2841 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2842{
2843 enum mlxsw_flood_table_type table_type;
2844 enum mlxsw_sp_flood_table flood_table;
2845 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2846
19ae6124 2847 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
56ade8fe 2848 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
19ae6124 2849 else
56ade8fe 2850 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
19ae6124
IS		 2851
2852 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2853 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2854 else
2855 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
56ade8fe
JP		 2856
2857 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2858 flood_table);
2859 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2860}
2861
2862static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2863{
2864 int type, err;
2865
56ade8fe
JP		 2866 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2867 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2868 continue;
2869
2870 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2871 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2872 if (err)
2873 return err;
56ade8fe
JP		 2874
2875 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2876 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2877 if (err)
2878 return err;
2879 }
2880
2881 return 0;
2882}
2883
0d65fc13
JP		 2884static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2885{
2886 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 2887 int err;
0d65fc13
JP		 2888
2889 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2890 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2891 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2892 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2893 MLXSW_REG_SLCR_LAG_HASH_SIP |
2894 MLXSW_REG_SLCR_LAG_HASH_DIP |
2895 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2896 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2897 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 2898 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2899 if (err)
2900 return err;
2901
c1a38311
JP		 2902 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
2903 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 2904 return -EIO;
2905
c1a38311 2906 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 2907 sizeof(struct mlxsw_sp_upper),
2908 GFP_KERNEL);
2909 if (!mlxsw_sp->lags)
2910 return -ENOMEM;
2911
2912 return 0;
2913}
2914
2915static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
2916{
2917 kfree(mlxsw_sp->lags);
0d65fc13
JP		 2918}
2919
9d87fcea
NF		 2920static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
2921{
2922 char htgt_pl[MLXSW_REG_HTGT_LEN];
2923
579c82e4
NF		 2924 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
2925 MLXSW_REG_HTGT_INVALID_POLICER,
2926 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
2927 MLXSW_REG_HTGT_DEFAULT_TC);
9d87fcea
NF		 2928 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2929}
2930
b2f10571 2931static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 2932 const struct mlxsw_bus_info *mlxsw_bus_info)
2933{
b2f10571 2934 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 2935 int err;
2936
2937 mlxsw_sp->core = mlxsw_core;
2938 mlxsw_sp->bus_info = mlxsw_bus_info;
14d39461 2939 INIT_LIST_HEAD(&mlxsw_sp->fids);
3ba2ebf4 2940 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
3a49b4fd 2941 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
56ade8fe
JP		 2942
2943 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2944 if (err) {
2945 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2946 return err;
2947 }
2948
56ade8fe
JP		 2949 err = mlxsw_sp_traps_init(mlxsw_sp);
2950 if (err) {
4544913e
NF		 2951 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
2952 return err;
56ade8fe
JP		 2953 }
2954
2955 err = mlxsw_sp_flood_init(mlxsw_sp);
2956 if (err) {
2957 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2958 goto err_flood_init;
2959 }
2960
2961 err = mlxsw_sp_buffers_init(mlxsw_sp);
2962 if (err) {
2963 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2964 goto err_buffers_init;
2965 }
2966
0d65fc13
JP		 2967 err = mlxsw_sp_lag_init(mlxsw_sp);
2968 if (err) {
2969 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2970 goto err_lag_init;
2971 }
2972
56ade8fe
JP		 2973 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2974 if (err) {
2975 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2976 goto err_switchdev_init;
2977 }
2978
464dce18
IS		 2979 err = mlxsw_sp_router_init(mlxsw_sp);
2980 if (err) {
2981 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
2982 goto err_router_init;
2983 }
2984
763b4b70
YG		 2985 err = mlxsw_sp_span_init(mlxsw_sp);
2986 if (err) {
2987 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
2988 goto err_span_init;
2989 }
2990
bbf2a475
IS		 2991 err = mlxsw_sp_ports_create(mlxsw_sp);
2992 if (err) {
2993 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
2994 goto err_ports_create;
2995 }
2996
56ade8fe
JP		 2997 return 0;
2998
bbf2a475 2999err_ports_create:
763b4b70
YG		 3000 mlxsw_sp_span_fini(mlxsw_sp);
3001err_span_init:
464dce18
IS		 3002 mlxsw_sp_router_fini(mlxsw_sp);
3003err_router_init:
bbf2a475 3004 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 3005err_switchdev_init:
ce0bd2b0 3006 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 3007err_lag_init:
0f433fa0 3008 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 3009err_buffers_init:
3010err_flood_init:
3011 mlxsw_sp_traps_fini(mlxsw_sp);
56ade8fe
JP		 3012 return err;
3013}
3014
b2f10571 3015static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 3016{
b2f10571 3017 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 3018
bbf2a475 3019 mlxsw_sp_ports_remove(mlxsw_sp);
763b4b70 3020 mlxsw_sp_span_fini(mlxsw_sp);
464dce18 3021 mlxsw_sp_router_fini(mlxsw_sp);
56ade8fe 3022 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 3023 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 3024 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3025 mlxsw_sp_traps_fini(mlxsw_sp);
3ba2ebf4 3026 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
14d39461 3027 WARN_ON(!list_empty(&mlxsw_sp->fids));
56ade8fe
JP		 3028}
3029
3030static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3031 .used_max_vepa_channels = 1,
3032 .max_vepa_channels = 0,
56ade8fe 3033 .used_max_mid = 1,
53ae6283 3034 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 3035 .used_max_pgt = 1,
3036 .max_pgt = 0,
56ade8fe
JP		 3037 .used_flood_tables = 1,
3038 .used_flood_mode = 1,
3039 .flood_mode = 3,
3040 .max_fid_offset_flood_tables = 2,
3041 .fid_offset_flood_table_size = VLAN_N_VID - 1,
19ae6124
IS		 3042 .max_fid_flood_tables = 2,
3043 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
56ade8fe
JP		 3044 .used_max_ib_mc = 1,
3045 .max_ib_mc = 0,
3046 .used_max_pkey = 1,
3047 .max_pkey = 0,
403547d3
NF		 3048 .used_kvd_split_data = 1,
3049 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3050 .kvd_hash_single_parts = 2,
3051 .kvd_hash_double_parts = 1,
c6022427 3052 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 3053 .swid_config = {
3054 {
3055 .used_type = 1,
3056 .type = MLXSW_PORT_SWID_TYPE_ETH,
3057 }
3058 },
57d316ba 3059 .resource_query_enable = 1,
56ade8fe
JP		 3060};
3061
3062static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 3063 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 3064 .priv_size = sizeof(struct mlxsw_sp),
3065 .init = mlxsw_sp_init,
3066 .fini = mlxsw_sp_fini,
9d87fcea 3067 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
2d0ed39f
JP		 3068 .port_split = mlxsw_sp_port_split,
3069 .port_unsplit = mlxsw_sp_port_unsplit,
3070 .sb_pool_get = mlxsw_sp_sb_pool_get,
3071 .sb_pool_set = mlxsw_sp_sb_pool_set,
3072 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3073 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3074 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3075 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3076 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3077 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3078 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3079 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3080 .txhdr_construct = mlxsw_sp_txhdr_construct,
3081 .txhdr_len = MLXSW_TXHDR_LEN,
3082 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 3083};
3084
7ce856aa
JP		 3085static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3086{
3087 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3088}
3089
dd82364c
DA		 3090static int mlxsw_lower_dev_walk(struct net_device *lower_dev, void *data)
3091{
3092 struct mlxsw_sp_port **port = data;
3093 int ret = 0;
3094
3095 if (mlxsw_sp_port_dev_check(lower_dev)) {
3096 *port = netdev_priv(lower_dev);
3097 ret = 1;
3098 }
3099
3100 return ret;
3101}
3102
7ce856aa
JP		 3103static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3104{
dd82364c 3105 struct mlxsw_sp_port *port;
7ce856aa
JP		 3106
3107 if (mlxsw_sp_port_dev_check(dev))
3108 return netdev_priv(dev);
3109
dd82364c
DA		 3110 port = NULL;
3111 netdev_walk_all_lower_dev(dev, mlxsw_lower_dev_walk, &port);
3112
3113 return port;
7ce856aa
JP		 3114}
3115
3116static struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
3117{
3118 struct mlxsw_sp_port *mlxsw_sp_port;
3119
3120 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3121 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3122}
3123
3124static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3125{
dd82364c 3126 struct mlxsw_sp_port *port;
7ce856aa
JP		 3127
3128 if (mlxsw_sp_port_dev_check(dev))
3129 return netdev_priv(dev);
3130
dd82364c
DA		 3131 port = NULL;
3132 netdev_walk_all_lower_dev_rcu(dev, mlxsw_lower_dev_walk, &port);
3133
3134 return port;
7ce856aa
JP		 3135}
3136
3137struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3138{
3139 struct mlxsw_sp_port *mlxsw_sp_port;
3140
3141 rcu_read_lock();
3142 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3143 if (mlxsw_sp_port)
3144 dev_hold(mlxsw_sp_port->dev);
3145 rcu_read_unlock();
3146 return mlxsw_sp_port;
3147}
3148
3149void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3150{
3151 dev_put(mlxsw_sp_port->dev);
3152}
3153
99724c18
IS		 3154static bool mlxsw_sp_rif_should_config(struct mlxsw_sp_rif *r,
3155 unsigned long event)
3156{
3157 switch (event) {
3158 case NETDEV_UP:
3159 if (!r)
3160 return true;
3161 r->ref_count++;
3162 return false;
3163 case NETDEV_DOWN:
3164 if (r && --r->ref_count == 0)
3165 return true;
3166 /* It is possible we already removed the RIF ourselves
3167 * if it was assigned to a netdev that is now a bridge
3168 * or LAG slave.
3169 */
3170 return false;
3171 }
3172
3173 return false;
3174}
3175
3176static int mlxsw_sp_avail_rif_get(struct mlxsw_sp *mlxsw_sp)
3177{
3178 int i;
3179
c1a38311 3180 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
99724c18
IS		 3181 if (!mlxsw_sp->rifs[i])
3182 return i;
3183
8f8a62d4 3184 return MLXSW_SP_INVALID_RIF;
99724c18
IS		 3185}
3186
3187static void mlxsw_sp_vport_rif_sp_attr_get(struct mlxsw_sp_port *mlxsw_sp_vport,
3188 bool *p_lagged, u16 *p_system_port)
3189{
3190 u8 local_port = mlxsw_sp_vport->local_port;
3191
3192 *p_lagged = mlxsw_sp_vport->lagged;
3193 *p_system_port = *p_lagged ? mlxsw_sp_vport->lag_id : local_port;
3194}
3195
3196static int mlxsw_sp_vport_rif_sp_op(struct mlxsw_sp_port *mlxsw_sp_vport,
3197 struct net_device *l3_dev, u16 rif,
3198 bool create)
3199{
3200 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3201 bool lagged = mlxsw_sp_vport->lagged;
3202 char ritr_pl[MLXSW_REG_RITR_LEN];
3203 u16 system_port;
3204
3205 mlxsw_reg_ritr_pack(ritr_pl, create, MLXSW_REG_RITR_SP_IF, rif,
3206 l3_dev->mtu, l3_dev->dev_addr);
3207
3208 mlxsw_sp_vport_rif_sp_attr_get(mlxsw_sp_vport, &lagged, &system_port);
3209 mlxsw_reg_ritr_sp_if_pack(ritr_pl, lagged, system_port,
3210 mlxsw_sp_vport_vid_get(mlxsw_sp_vport));
3211
3212 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3213}
3214
3215static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3216
3217static struct mlxsw_sp_fid *
3218mlxsw_sp_rfid_alloc(u16 fid, struct net_device *l3_dev)
3219{
3220 struct mlxsw_sp_fid *f;
3221
3222 f = kzalloc(sizeof(*f), GFP_KERNEL);
3223 if (!f)
3224 return NULL;
3225
3226 f->leave = mlxsw_sp_vport_rif_sp_leave;
3227 f->ref_count = 0;
3228 f->dev = l3_dev;
3229 f->fid = fid;
3230
3231 return f;
3232}
3233
3234static struct mlxsw_sp_rif *
3235mlxsw_sp_rif_alloc(u16 rif, struct net_device *l3_dev, struct mlxsw_sp_fid *f)
3236{
3237 struct mlxsw_sp_rif *r;
3238
3239 r = kzalloc(sizeof(*r), GFP_KERNEL);
3240 if (!r)
3241 return NULL;
3242
3243 ether_addr_copy(r->addr, l3_dev->dev_addr);
3244 r->mtu = l3_dev->mtu;
3245 r->ref_count = 1;
3246 r->dev = l3_dev;
3247 r->rif = rif;
3248 r->f = f;
3249
3250 return r;
3251}
3252
3253static struct mlxsw_sp_rif *
3254mlxsw_sp_vport_rif_sp_create(struct mlxsw_sp_port *mlxsw_sp_vport,
3255 struct net_device *l3_dev)
3256{
3257 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3258 struct mlxsw_sp_fid *f;
3259 struct mlxsw_sp_rif *r;
3260 u16 fid, rif;
3261 int err;
3262
3263 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
8f8a62d4 3264 if (rif == MLXSW_SP_INVALID_RIF)
99724c18
IS		 3265 return ERR_PTR(-ERANGE);
3266
3267 err = mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, true);
3268 if (err)
3269 return ERR_PTR(err);
3270
3271 fid = mlxsw_sp_rif_sp_to_fid(rif);
3272 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, true);
3273 if (err)
3274 goto err_rif_fdb_op;
3275
3276 f = mlxsw_sp_rfid_alloc(fid, l3_dev);
3277 if (!f) {
3278 err = -ENOMEM;
3279 goto err_rfid_alloc;
3280 }
3281
3282 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3283 if (!r) {
3284 err = -ENOMEM;
3285 goto err_rif_alloc;
3286 }
3287
3288 f->r = r;
3289 mlxsw_sp->rifs[rif] = r;
3290
3291 return r;
3292
3293err_rif_alloc:
3294 kfree(f);
3295err_rfid_alloc:
3296 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3297err_rif_fdb_op:
3298 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3299 return ERR_PTR(err);
3300}
3301
3302static void mlxsw_sp_vport_rif_sp_destroy(struct mlxsw_sp_port *mlxsw_sp_vport,
3303 struct mlxsw_sp_rif *r)
3304{
3305 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3306 struct net_device *l3_dev = r->dev;
3307 struct mlxsw_sp_fid *f = r->f;
3308 u16 fid = f->fid;
3309 u16 rif = r->rif;
3310
3311 mlxsw_sp->rifs[rif] = NULL;
3312 f->r = NULL;
3313
3314 kfree(r);
3315
3316 kfree(f);
3317
3318 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3319
3320 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3321}
3322
3323static int mlxsw_sp_vport_rif_sp_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3324 struct net_device *l3_dev)
3325{
3326 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3327 struct mlxsw_sp_rif *r;
3328
3329 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, l3_dev);
3330 if (!r) {
3331 r = mlxsw_sp_vport_rif_sp_create(mlxsw_sp_vport, l3_dev);
3332 if (IS_ERR(r))
3333 return PTR_ERR(r);
3334 }
3335
3336 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, r->f);
3337 r->f->ref_count++;
3338
3339 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", r->f->fid);
3340
3341 return 0;
3342}
3343
3344static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3345{
3346 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3347
3348 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3349
3350 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
3351 if (--f->ref_count == 0)
3352 mlxsw_sp_vport_rif_sp_destroy(mlxsw_sp_vport, f->r);
3353}
3354
3355static int mlxsw_sp_inetaddr_vport_event(struct net_device *l3_dev,
3356 struct net_device *port_dev,
3357 unsigned long event, u16 vid)
3358{
3359 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(port_dev);
3360 struct mlxsw_sp_port *mlxsw_sp_vport;
3361
3362 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3363 if (WARN_ON(!mlxsw_sp_vport))
3364 return -EINVAL;
3365
3366 switch (event) {
3367 case NETDEV_UP:
3368 return mlxsw_sp_vport_rif_sp_join(mlxsw_sp_vport, l3_dev);
3369 case NETDEV_DOWN:
3370 mlxsw_sp_vport_rif_sp_leave(mlxsw_sp_vport);
3371 break;
3372 }
3373
3374 return 0;
3375}
3376
3377static int mlxsw_sp_inetaddr_port_event(struct net_device *port_dev,
3378 unsigned long event)
3379{
3380 if (netif_is_bridge_port(port_dev) || netif_is_lag_port(port_dev))
3381 return 0;
3382
3383 return mlxsw_sp_inetaddr_vport_event(port_dev, port_dev, event, 1);
3384}
3385
3386static int __mlxsw_sp_inetaddr_lag_event(struct net_device *l3_dev,
3387 struct net_device *lag_dev,
3388 unsigned long event, u16 vid)
3389{
3390 struct net_device *port_dev;
3391 struct list_head *iter;
3392 int err;
3393
3394 netdev_for_each_lower_dev(lag_dev, port_dev, iter) {
3395 if (mlxsw_sp_port_dev_check(port_dev)) {
3396 err = mlxsw_sp_inetaddr_vport_event(l3_dev, port_dev,
3397 event, vid);
3398 if (err)
3399 return err;
3400 }
3401 }
3402
3403 return 0;
3404}
3405
3406static int mlxsw_sp_inetaddr_lag_event(struct net_device *lag_dev,
3407 unsigned long event)
3408{
3409 if (netif_is_bridge_port(lag_dev))
3410 return 0;
3411
3412 return __mlxsw_sp_inetaddr_lag_event(lag_dev, lag_dev, event, 1);
3413}
3414
99f44bb3
IS		 3415static struct mlxsw_sp_fid *mlxsw_sp_bridge_fid_get(struct mlxsw_sp *mlxsw_sp,
3416 struct net_device *l3_dev)
3417{
3418 u16 fid;
3419
3420 if (is_vlan_dev(l3_dev))
3421 fid = vlan_dev_vlan_id(l3_dev);
3422 else if (mlxsw_sp->master_bridge.dev == l3_dev)
3423 fid = 1;
3424 else
3425 return mlxsw_sp_vfid_find(mlxsw_sp, l3_dev);
3426
3427 return mlxsw_sp_fid_find(mlxsw_sp, fid);
3428}
3429
f888f587
IS		 3430static enum mlxsw_flood_table_type mlxsw_sp_flood_table_type_get(u16 fid)
3431{
3432 return mlxsw_sp_fid_is_vfid(fid) ? MLXSW_REG_SFGC_TABLE_TYPE_FID :
3433 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
3434}
3435
3436static u16 mlxsw_sp_flood_table_index_get(u16 fid)
3437{
3438 return mlxsw_sp_fid_is_vfid(fid) ? mlxsw_sp_fid_to_vfid(fid) : fid;
3439}
3440
3441static int mlxsw_sp_router_port_flood_set(struct mlxsw_sp *mlxsw_sp, u16 fid,
3442 bool set)
3443{
3444 enum mlxsw_flood_table_type table_type;
3445 char *sftr_pl;
3446 u16 index;
3447 int err;
3448
3449 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
3450 if (!sftr_pl)
3451 return -ENOMEM;
3452
3453 table_type = mlxsw_sp_flood_table_type_get(fid);
3454 index = mlxsw_sp_flood_table_index_get(fid);
3455 mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, index, table_type,
3456 1, MLXSW_PORT_ROUTER_PORT, set);
3457 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl);
3458
3459 kfree(sftr_pl);
3460 return err;
3461}
3462
99f44bb3
IS		 3463static enum mlxsw_reg_ritr_if_type mlxsw_sp_rif_type_get(u16 fid)
3464{
3465 if (mlxsw_sp_fid_is_vfid(fid))
3466 return MLXSW_REG_RITR_FID_IF;
3467 else
3468 return MLXSW_REG_RITR_VLAN_IF;
3469}
3470
3471static int mlxsw_sp_rif_bridge_op(struct mlxsw_sp *mlxsw_sp,
3472 struct net_device *l3_dev,
3473 u16 fid, u16 rif,
3474 bool create)
3475{
3476 enum mlxsw_reg_ritr_if_type rif_type;
3477 char ritr_pl[MLXSW_REG_RITR_LEN];
3478
3479 rif_type = mlxsw_sp_rif_type_get(fid);
3480 mlxsw_reg_ritr_pack(ritr_pl, create, rif_type, rif, l3_dev->mtu,
3481 l3_dev->dev_addr);
3482 mlxsw_reg_ritr_fid_set(ritr_pl, rif_type, fid);
3483
3484 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3485}
3486
3487static int mlxsw_sp_rif_bridge_create(struct mlxsw_sp *mlxsw_sp,
3488 struct net_device *l3_dev,
3489 struct mlxsw_sp_fid *f)
3490{
3491 struct mlxsw_sp_rif *r;
3492 u16 rif;
3493 int err;
3494
3495 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
8f8a62d4 3496 if (rif == MLXSW_SP_INVALID_RIF)
99f44bb3
IS		 3497 return -ERANGE;
3498
f888f587 3499 err = mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, true);
99f44bb3
IS		 3500 if (err)
3501 return err;
3502
f888f587
IS		 3503 err = mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, true);
3504 if (err)
3505 goto err_rif_bridge_op;
3506
99f44bb3
IS		 3507 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, true);
3508 if (err)
3509 goto err_rif_fdb_op;
3510
3511 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3512 if (!r) {
3513 err = -ENOMEM;
3514 goto err_rif_alloc;
3515 }
3516
3517 f->r = r;
3518 mlxsw_sp->rifs[rif] = r;
3519
3520 netdev_dbg(l3_dev, "RIF=%d created\n", rif);
3521
3522 return 0;
3523
3524err_rif_alloc:
3525 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3526err_rif_fdb_op:
3527 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
f888f587
IS		 3528err_rif_bridge_op:
3529 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
99f44bb3
IS		 3530 return err;
3531}
3532
3533void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
3534 struct mlxsw_sp_rif *r)
3535{
3536 struct net_device *l3_dev = r->dev;
3537 struct mlxsw_sp_fid *f = r->f;
3538 u16 rif = r->rif;
3539
3540 mlxsw_sp->rifs[rif] = NULL;
3541 f->r = NULL;
3542
3543 kfree(r);
3544
3545 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3546
3547 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
3548
f888f587
IS		 3549 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
3550
99f44bb3
IS		 3551 netdev_dbg(l3_dev, "RIF=%d destroyed\n", rif);
3552}
3553
3554static int mlxsw_sp_inetaddr_bridge_event(struct net_device *l3_dev,
3555 struct net_device *br_dev,
3556 unsigned long event)
3557{
3558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(l3_dev);
3559 struct mlxsw_sp_fid *f;
3560
3561 /* FID can either be an actual FID if the L3 device is the
3562 * VLAN-aware bridge or a VLAN device on top. Otherwise, the
3563 * L3 device is a VLAN-unaware bridge and we get a vFID.
3564 */
3565 f = mlxsw_sp_bridge_fid_get(mlxsw_sp, l3_dev);
3566 if (WARN_ON(!f))
3567 return -EINVAL;
3568
3569 switch (event) {
3570 case NETDEV_UP:
3571 return mlxsw_sp_rif_bridge_create(mlxsw_sp, l3_dev, f);
3572 case NETDEV_DOWN:
3573 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
3574 break;
3575 }
3576
3577 return 0;
3578}
3579
99724c18
IS		 3580static int mlxsw_sp_inetaddr_vlan_event(struct net_device *vlan_dev,
3581 unsigned long event)
3582{
3583 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
99f44bb3 3584 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
99724c18
IS		 3585 u16 vid = vlan_dev_vlan_id(vlan_dev);
3586
3587 if (mlxsw_sp_port_dev_check(real_dev))
3588 return mlxsw_sp_inetaddr_vport_event(vlan_dev, real_dev, event,
3589 vid);
3590 else if (netif_is_lag_master(real_dev))
3591 return __mlxsw_sp_inetaddr_lag_event(vlan_dev, real_dev, event,
3592 vid);
99f44bb3
IS		 3593 else if (netif_is_bridge_master(real_dev) &&
3594 mlxsw_sp->master_bridge.dev == real_dev)
3595 return mlxsw_sp_inetaddr_bridge_event(vlan_dev, real_dev,
3596 event);
99724c18
IS		 3597
3598 return 0;
3599}
3600
3601static int mlxsw_sp_inetaddr_event(struct notifier_block *unused,
3602 unsigned long event, void *ptr)
3603{
3604 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
3605 struct net_device *dev = ifa->ifa_dev->dev;
3606 struct mlxsw_sp *mlxsw_sp;
3607 struct mlxsw_sp_rif *r;
3608 int err = 0;
3609
3610 mlxsw_sp = mlxsw_sp_lower_get(dev);
3611 if (!mlxsw_sp)
3612 goto out;
3613
3614 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3615 if (!mlxsw_sp_rif_should_config(r, event))
3616 goto out;
3617
3618 if (mlxsw_sp_port_dev_check(dev))
3619 err = mlxsw_sp_inetaddr_port_event(dev, event);
3620 else if (netif_is_lag_master(dev))
3621 err = mlxsw_sp_inetaddr_lag_event(dev, event);
99f44bb3
IS		 3622 else if (netif_is_bridge_master(dev))
3623 err = mlxsw_sp_inetaddr_bridge_event(dev, dev, event);
99724c18
IS		 3624 else if (is_vlan_dev(dev))
3625 err = mlxsw_sp_inetaddr_vlan_event(dev, event);
3626
3627out:
3628 return notifier_from_errno(err);
3629}
3630
6e095fd4
IS		 3631static int mlxsw_sp_rif_edit(struct mlxsw_sp *mlxsw_sp, u16 rif,
3632 const char *mac, int mtu)
3633{
3634 char ritr_pl[MLXSW_REG_RITR_LEN];
3635 int err;
3636
3637 mlxsw_reg_ritr_rif_pack(ritr_pl, rif);
3638 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3639 if (err)
3640 return err;
3641
3642 mlxsw_reg_ritr_mtu_set(ritr_pl, mtu);
3643 mlxsw_reg_ritr_if_mac_memcpy_to(ritr_pl, mac);
3644 mlxsw_reg_ritr_op_set(ritr_pl, MLXSW_REG_RITR_RIF_CREATE);
3645 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3646}
3647
3648static int mlxsw_sp_netdevice_router_port_event(struct net_device *dev)
3649{
3650 struct mlxsw_sp *mlxsw_sp;
3651 struct mlxsw_sp_rif *r;
3652 int err;
3653
3654 mlxsw_sp = mlxsw_sp_lower_get(dev);
3655 if (!mlxsw_sp)
3656 return 0;
3657
3658 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3659 if (!r)
3660 return 0;
3661
3662 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, false);
3663 if (err)
3664 return err;
3665
3666 err = mlxsw_sp_rif_edit(mlxsw_sp, r->rif, dev->dev_addr, dev->mtu);
3667 if (err)
3668 goto err_rif_edit;
3669
3670 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, dev->dev_addr, r->f->fid, true);
3671 if (err)
3672 goto err_rif_fdb_op;
3673
3674 ether_addr_copy(r->addr, dev->dev_addr);
3675 r->mtu = dev->mtu;
3676
3677 netdev_dbg(dev, "Updated RIF=%d\n", r->rif);
3678
3679 return 0;
3680
3681err_rif_fdb_op:
3682 mlxsw_sp_rif_edit(mlxsw_sp, r->rif, r->addr, r->mtu);
3683err_rif_edit:
3684 mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, true);
3685 return err;
3686}
3687
fe3f6d14
IS		 3688static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3689 u16 fid)
3690{
3691 if (mlxsw_sp_fid_is_vfid(fid))
3692 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3693 else
3694 return test_bit(fid, lag_port->active_vlans);
3695}
3696
3697static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3698 u16 fid)
039c49a6
IS		 3699{
3700 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
fe3f6d14
IS		 3701 u8 local_port = mlxsw_sp_port->local_port;
3702 u16 lag_id = mlxsw_sp_port->lag_id;
c1a38311 3703 u64 max_lag_members;
fe3f6d14 3704 int i, count = 0;
039c49a6 3705
fe3f6d14
IS		 3706 if (!mlxsw_sp_port->lagged)
3707 return true;
039c49a6 3708
c1a38311
JP		 3709 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3710 MAX_LAG_MEMBERS);
3711 for (i = 0; i < max_lag_members; i++) {
fe3f6d14
IS		 3712 struct mlxsw_sp_port *lag_port;
3713
3714 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3715 if (!lag_port || lag_port->local_port == local_port)
3716 continue;
3717 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3718 count++;
3719 }
3720
3721 return !count;
039c49a6
IS		 3722}
3723
3724static int
3725mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3726 u16 fid)
3727{
3728 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3729 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3730
3731 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3732 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3733 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3734 mlxsw_sp_port->local_port);
3735
22305378
IS		 3736 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3737 mlxsw_sp_port->local_port, fid);
3738
039c49a6
IS		 3739 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3740}
3741
039c49a6
IS		 3742static int
3743mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3744 u16 fid)
3745{
3746 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3747 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3748
3749 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3750 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3751 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3752
22305378
IS		 3753 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3754 mlxsw_sp_port->lag_id, fid);
3755
039c49a6
IS		 3756 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3757}
3758
fe3f6d14 3759int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
039c49a6 3760{
fe3f6d14
IS		 3761 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3762 return 0;
039c49a6 3763
fe3f6d14
IS		 3764 if (mlxsw_sp_port->lagged)
3765 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
039c49a6
IS		 3766 fid);
3767 else
fe3f6d14 3768 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
039c49a6
IS		 3769}
3770
701b186e
IS		 3771static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3772{
3773 struct mlxsw_sp_fid *f, *tmp;
3774
3775 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3776 if (--f->ref_count == 0)
3777 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3778 else
3779 WARN_ON_ONCE(1);
3780}
3781
7117a570
IS		 3782static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3783 struct net_device *br_dev)
3784{
3785 return !mlxsw_sp->master_bridge.dev ||
3786 mlxsw_sp->master_bridge.dev == br_dev;
3787}
3788
3789static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3790 struct net_device *br_dev)
3791{
3792 mlxsw_sp->master_bridge.dev = br_dev;
3793 mlxsw_sp->master_bridge.ref_count++;
3794}
3795
3796static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3797{
701b186e 3798 if (--mlxsw_sp->master_bridge.ref_count == 0) {
7117a570 3799 mlxsw_sp->master_bridge.dev = NULL;
701b186e
IS		 3800 /* It's possible upper VLAN devices are still holding
3801 * references to underlying FIDs. Drop the reference
3802 * and release the resources if it was the last one.
3803 * If it wasn't, then something bad happened.
3804 */
3805 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3806 }
7117a570
IS		 3807}
3808
3809static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3810 struct net_device *br_dev)
56ade8fe
JP		 3811{
3812 struct net_device *dev = mlxsw_sp_port->dev;
3813 int err;
3814
3815 /* When port is not bridged untagged packets are tagged with
3816 * PVID=VID=1, thereby creating an implicit VLAN interface in
3817 * the device. Remove it and let bridge code take care of its
3818 * own VLANs.
3819 */
3820 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
6c72a3d0
IS		 3821 if (err)
3822 return err;
56ade8fe 3823
7117a570
IS		 3824 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3825
6c72a3d0
IS		 3826 mlxsw_sp_port->learning = 1;
3827 mlxsw_sp_port->learning_sync = 1;
3828 mlxsw_sp_port->uc_flood = 1;
3829 mlxsw_sp_port->bridged = 1;
3830
3831 return 0;
56ade8fe
JP		 3832}
3833
fe3f6d14 3834static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
56ade8fe
JP		 3835{
3836 struct net_device *dev = mlxsw_sp_port->dev;
5a8f4525 3837
28a01d2d
IS		 3838 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3839
7117a570
IS		 3840 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3841
6c72a3d0
IS		 3842 mlxsw_sp_port->learning = 0;
3843 mlxsw_sp_port->learning_sync = 0;
3844 mlxsw_sp_port->uc_flood = 0;
5a8f4525 3845 mlxsw_sp_port->bridged = 0;
56ade8fe
JP		 3846
3847 /* Add implicit VLAN interface in the device, so that untagged
3848 * packets will be classified to the default vFID.
3849 */
82e6db03 3850 mlxsw_sp_port_add_vid(dev, 0, 1);
56ade8fe
JP		 3851}
3852
0d65fc13
JP		 3853static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3854{
3855 char sldr_pl[MLXSW_REG_SLDR_LEN];
3856
3857 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3858 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3859}
3860
3861static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3862{
3863 char sldr_pl[MLXSW_REG_SLDR_LEN];
3864
3865 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3867}
3868
3869static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3870 u16 lag_id, u8 port_index)
3871{
3872 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3873 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3874
3875 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3876 lag_id, port_index);
3877 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3878}
3879
3880static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3881 u16 lag_id)
3882{
3883 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3884 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3885
3886 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3887 lag_id);
3888 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3889}
3890
3891static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3892 u16 lag_id)
3893{
3894 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3895 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3896
3897 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3898 lag_id);
3899 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3900}
3901
3902static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3903 u16 lag_id)
3904{
3905 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3906 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3907
3908 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3909 lag_id);
3910 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3911}
3912
3913static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3914 struct net_device *lag_dev,
3915 u16 *p_lag_id)
3916{
3917 struct mlxsw_sp_upper *lag;
3918 int free_lag_id = -1;
c1a38311 3919 u64 max_lag;
0d65fc13
JP		 3920 int i;
3921
c1a38311
JP		 3922 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3923 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 3924 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3925 if (lag->ref_count) {
3926 if (lag->dev == lag_dev) {
3927 *p_lag_id = i;
3928 return 0;
3929 }
3930 } else if (free_lag_id < 0) {
3931 free_lag_id = i;
3932 }
3933 }
3934 if (free_lag_id < 0)
3935 return -EBUSY;
3936 *p_lag_id = free_lag_id;
3937 return 0;
3938}
3939
3940static bool
3941mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3942 struct net_device *lag_dev,
3943 struct netdev_lag_upper_info *lag_upper_info)
3944{
3945 u16 lag_id;
3946
3947 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3948 return false;
3949 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3950 return false;
3951 return true;
3952}
3953
3954static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3955 u16 lag_id, u8 *p_port_index)
3956{
c1a38311 3957 u64 max_lag_members;
0d65fc13
JP		 3958 int i;
3959
c1a38311
JP		 3960 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3961 MAX_LAG_MEMBERS);
3962 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 3963 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3964 *p_port_index = i;
3965 return 0;
3966 }
3967 }
3968 return -EBUSY;
3969}
3970
86bf95b3
IS		 3971static void
3972mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3973 u16 lag_id)
3974{
3975 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 3976 struct mlxsw_sp_fid *f;
86bf95b3
IS		 3977
3978 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3979 if (WARN_ON(!mlxsw_sp_vport))
3980 return;
3981
11943ff4
IS		 3982 /* If vPort is assigned a RIF, then leave it since it's no
3983 * longer valid.
3984 */
3985 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3986 if (f)
3987 f->leave(mlxsw_sp_vport);
3988
86bf95b3
IS		 3989 mlxsw_sp_vport->lag_id = lag_id;
3990 mlxsw_sp_vport->lagged = 1;
3991}
3992
3993static void
3994mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3995{
3996 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 3997 struct mlxsw_sp_fid *f;
86bf95b3
IS		 3998
3999 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4000 if (WARN_ON(!mlxsw_sp_vport))
4001 return;
4002
11943ff4
IS		 4003 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4004 if (f)
4005 f->leave(mlxsw_sp_vport);
4006
86bf95b3
IS		 4007 mlxsw_sp_vport->lagged = 0;
4008}
4009
0d65fc13
JP		 4010static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4011 struct net_device *lag_dev)
4012{
4013 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4014 struct mlxsw_sp_upper *lag;
4015 u16 lag_id;
4016 u8 port_index;
4017 int err;
4018
4019 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4020 if (err)
4021 return err;
4022 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4023 if (!lag->ref_count) {
4024 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4025 if (err)
4026 return err;
4027 lag->dev = lag_dev;
4028 }
4029
4030 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4031 if (err)
4032 return err;
4033 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4034 if (err)
4035 goto err_col_port_add;
4036 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4037 if (err)
4038 goto err_col_port_enable;
4039
4040 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4041 mlxsw_sp_port->local_port);
4042 mlxsw_sp_port->lag_id = lag_id;
4043 mlxsw_sp_port->lagged = 1;
4044 lag->ref_count++;
86bf95b3
IS		 4045
4046 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
4047
0d65fc13
JP		 4048 return 0;
4049
51554db2
IS		 4050err_col_port_enable:
4051 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4052err_col_port_add:
4053 if (!lag->ref_count)
4054 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4055 return err;
4056}
4057
82e6db03
IS		 4058static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4059 struct net_device *lag_dev)
0d65fc13
JP		 4060{
4061 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4062 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4063 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4064
4065 if (!mlxsw_sp_port->lagged)
82e6db03 4066 return;
0d65fc13
JP		 4067 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4068 WARN_ON(lag->ref_count == 0);
4069
82e6db03
IS		 4070 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4071 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4072
4dc236c3
IS		 4073 if (mlxsw_sp_port->bridged) {
4074 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
fe3f6d14 4075 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4dc236c3
IS		 4076 }
4077
fe3f6d14 4078 if (lag->ref_count == 1)
82e6db03 4079 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4080
4081 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4082 mlxsw_sp_port->local_port);
4083 mlxsw_sp_port->lagged = 0;
4084 lag->ref_count--;
86bf95b3
IS		 4085
4086 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
0d65fc13
JP		 4087}
4088
74581206
JP		 4089static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4090 u16 lag_id)
4091{
4092 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4093 char sldr_pl[MLXSW_REG_SLDR_LEN];
4094
4095 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4096 mlxsw_sp_port->local_port);
4097 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4098}
4099
4100static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4101 u16 lag_id)
4102{
4103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4104 char sldr_pl[MLXSW_REG_SLDR_LEN];
4105
4106 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4107 mlxsw_sp_port->local_port);
4108 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4109}
4110
4111static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4112 bool lag_tx_enabled)
4113{
4114 if (lag_tx_enabled)
4115 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4116 mlxsw_sp_port->lag_id);
4117 else
4118 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4119 mlxsw_sp_port->lag_id);
4120}
4121
4122static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4123 struct netdev_lag_lower_state_info *info)
4124{
4125 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4126}
4127
9589a7b5
IS		 4128static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4129 struct net_device *vlan_dev)
4130{
4131 struct mlxsw_sp_port *mlxsw_sp_vport;
4132 u16 vid = vlan_dev_vlan_id(vlan_dev);
4133
4134 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 4135 if (WARN_ON(!mlxsw_sp_vport))
9589a7b5 4136 return -EINVAL;
9589a7b5
IS		 4137
4138 mlxsw_sp_vport->dev = vlan_dev;
4139
4140 return 0;
4141}
4142
82e6db03
IS		 4143static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4144 struct net_device *vlan_dev)
9589a7b5
IS		 4145{
4146 struct mlxsw_sp_port *mlxsw_sp_vport;
4147 u16 vid = vlan_dev_vlan_id(vlan_dev);
4148
4149 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 4150 if (WARN_ON(!mlxsw_sp_vport))
82e6db03 4151 return;
9589a7b5
IS		 4152
4153 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
9589a7b5
IS		 4154}
4155
74581206
JP		 4156static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4157 unsigned long event, void *ptr)
56ade8fe 4158{
56ade8fe
JP		 4159 struct netdev_notifier_changeupper_info *info;
4160 struct mlxsw_sp_port *mlxsw_sp_port;
4161 struct net_device *upper_dev;
4162 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4163 int err = 0;
56ade8fe 4164
56ade8fe
JP		 4165 mlxsw_sp_port = netdev_priv(dev);
4166 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4167 info = ptr;
4168
4169 switch (event) {
4170 case NETDEV_PRECHANGEUPPER:
4171 upper_dev = info->upper_dev;
59fe9b3f
IS		 4172 if (!is_vlan_dev(upper_dev) &&
4173 !netif_is_lag_master(upper_dev) &&
4174 !netif_is_bridge_master(upper_dev))
4175 return -EINVAL;
6ec43904 4176 if (!info->linking)
0d65fc13 4177 break;
56ade8fe 4178 /* HW limitation forbids to put ports to multiple bridges. */
0d65fc13 4179 if (netif_is_bridge_master(upper_dev) &&
56ade8fe 4180 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
80bedf1a 4181 return -EINVAL;
0d65fc13
JP		 4182 if (netif_is_lag_master(upper_dev) &&
4183 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4184 info->upper_info))
80bedf1a 4185 return -EINVAL;
6ec43904
IS		 4186 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4187 return -EINVAL;
4188 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4189 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4190 return -EINVAL;
56ade8fe
JP		 4191 break;
4192 case NETDEV_CHANGEUPPER:
4193 upper_dev = info->upper_dev;
9589a7b5 4194 if (is_vlan_dev(upper_dev)) {
80bedf1a 4195 if (info->linking)
9589a7b5
IS		 4196 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4197 upper_dev);
80bedf1a 4198 else
82e6db03
IS		 4199 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4200 upper_dev);
9589a7b5 4201 } else if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4202 if (info->linking)
4203 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4204 upper_dev);
4205 else
fe3f6d14 4206 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
0d65fc13 4207 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4208 if (info->linking)
0d65fc13
JP		 4209 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4210 upper_dev);
80bedf1a 4211 else
82e6db03
IS		 4212 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4213 upper_dev);
59fe9b3f
IS		 4214 } else {
4215 err = -EINVAL;
4216 WARN_ON(1);
56ade8fe
JP		 4217 }
4218 break;
4219 }
4220
80bedf1a 4221 return err;
56ade8fe
JP		 4222}
4223
74581206
JP		 4224static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4225 unsigned long event, void *ptr)
4226{
4227 struct netdev_notifier_changelowerstate_info *info;
4228 struct mlxsw_sp_port *mlxsw_sp_port;
4229 int err;
4230
4231 mlxsw_sp_port = netdev_priv(dev);
4232 info = ptr;
4233
4234 switch (event) {
4235 case NETDEV_CHANGELOWERSTATE:
4236 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4237 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4238 info->lower_state_info);
4239 if (err)
4240 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4241 }
4242 break;
4243 }
4244
80bedf1a 4245 return 0;
74581206
JP		 4246}
4247
4248static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4249 unsigned long event, void *ptr)
4250{
4251 switch (event) {
4252 case NETDEV_PRECHANGEUPPER:
4253 case NETDEV_CHANGEUPPER:
4254 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4255 case NETDEV_CHANGELOWERSTATE:
4256 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4257 }
4258
80bedf1a 4259 return 0;
74581206
JP		 4260}
4261
0d65fc13
JP		 4262static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4263 unsigned long event, void *ptr)
4264{
4265 struct net_device *dev;
4266 struct list_head *iter;
4267 int ret;
4268
4269 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4270 if (mlxsw_sp_port_dev_check(dev)) {
4271 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
80bedf1a 4272 if (ret)
0d65fc13
JP		 4273 return ret;
4274 }
4275 }
4276
80bedf1a 4277 return 0;
0d65fc13
JP		 4278}
4279
701b186e
IS		 4280static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4281 struct net_device *vlan_dev)
26f0e7fb 4282{
701b186e 4283 u16 fid = vlan_dev_vlan_id(vlan_dev);
d0ec875a 4284 struct mlxsw_sp_fid *f;
26f0e7fb 4285
701b186e
IS		 4286 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4287 if (!f) {
4288 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4289 if (IS_ERR(f))
4290 return PTR_ERR(f);
26f0e7fb
IS		 4291 }
4292
701b186e
IS		 4293 f->ref_count++;
4294
4295 return 0;
4296}
4297
4298static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4299 struct net_device *vlan_dev)
4300{
4301 u16 fid = vlan_dev_vlan_id(vlan_dev);
4302 struct mlxsw_sp_fid *f;
4303
4304 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
99f44bb3
IS		 4305 if (f && f->r)
4306 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
701b186e
IS		 4307 if (f && --f->ref_count == 0)
4308 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4309}
4310
4311static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4312 unsigned long event, void *ptr)
4313{
4314 struct netdev_notifier_changeupper_info *info;
4315 struct net_device *upper_dev;
4316 struct mlxsw_sp *mlxsw_sp;
4317 int err;
4318
4319 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4320 if (!mlxsw_sp)
4321 return 0;
4322 if (br_dev != mlxsw_sp->master_bridge.dev)
4323 return 0;
4324
4325 info = ptr;
4326
4327 switch (event) {
4328 case NETDEV_CHANGEUPPER:
4329 upper_dev = info->upper_dev;
4330 if (!is_vlan_dev(upper_dev))
4331 break;
4332 if (info->linking) {
4333 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4334 upper_dev);
4335 if (err)
4336 return err;
4337 } else {
4338 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp, upper_dev);
4339 }
4340 break;
4341 }
4342
4343 return 0;
26f0e7fb
IS		 4344}
4345
3ba2ebf4 4346static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
26f0e7fb 4347{
3ba2ebf4 4348 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
99724c18 4349 MLXSW_SP_VFID_MAX);
26f0e7fb
IS		 4350}
4351
99724c18 4352static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
26f0e7fb 4353{
99724c18 4354 char sfmr_pl[MLXSW_REG_SFMR_LEN];
26f0e7fb 4355
99724c18
IS		 4356 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4357 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
26f0e7fb
IS		 4358}
4359
3ba2ebf4 4360static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
1c800759 4361
3ba2ebf4
IS		 4362static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4363 struct net_device *br_dev)
26f0e7fb
IS		 4364{
4365 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 4366 struct mlxsw_sp_fid *f;
c7e920b5 4367 u16 vfid, fid;
26f0e7fb
IS		 4368 int err;
4369
3ba2ebf4 4370 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
c7e920b5 4371 if (vfid == MLXSW_SP_VFID_MAX) {
26f0e7fb
IS		 4372 dev_err(dev, "No available vFIDs\n");
4373 return ERR_PTR(-ERANGE);
4374 }
4375
c7e920b5
IS		 4376 fid = mlxsw_sp_vfid_to_fid(vfid);
4377 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
26f0e7fb 4378 if (err) {
c7e920b5 4379 dev_err(dev, "Failed to create FID=%d\n", fid);
26f0e7fb
IS		 4380 return ERR_PTR(err);
4381 }
4382
c7e920b5
IS		 4383 f = kzalloc(sizeof(*f), GFP_KERNEL);
4384 if (!f)
26f0e7fb
IS		 4385 goto err_allocate_vfid;
4386
3ba2ebf4 4387 f->leave = mlxsw_sp_vport_vfid_leave;
d0ec875a
IS		 4388 f->fid = fid;
4389 f->dev = br_dev;
26f0e7fb 4390
3ba2ebf4
IS		 4391 list_add(&f->list, &mlxsw_sp->vfids.list);
4392 set_bit(vfid, mlxsw_sp->vfids.mapped);
26f0e7fb 4393
c7e920b5 4394 return f;
26f0e7fb
IS		 4395
4396err_allocate_vfid:
c7e920b5 4397 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 4398 return ERR_PTR(-ENOMEM);
4399}
4400
3ba2ebf4
IS		 4401static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4402 struct mlxsw_sp_fid *f)
26f0e7fb 4403{
d0ec875a 4404 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
99f44bb3 4405 u16 fid = f->fid;
26f0e7fb 4406
3ba2ebf4 4407 clear_bit(vfid, mlxsw_sp->vfids.mapped);
d0ec875a 4408 list_del(&f->list);
26f0e7fb 4409
99f44bb3
IS		 4410 if (f->r)
4411 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
26f0e7fb 4412
d0ec875a 4413 kfree(f);
99f44bb3
IS		 4414
4415 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 4416}
4417
99724c18
IS		 4418static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4419 bool valid)
4420{
4421 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4422 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4423
4424 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4425 vid);
4426}
4427
3ba2ebf4
IS		 4428static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4429 struct net_device *br_dev)
26f0e7fb 4430{
0355b59f 4431 struct mlxsw_sp_fid *f;
26f0e7fb
IS		 4432 int err;
4433
3ba2ebf4 4434 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
0355b59f 4435 if (!f) {
3ba2ebf4 4436 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
0355b59f
IS		 4437 if (IS_ERR(f))
4438 return PTR_ERR(f);
26f0e7fb
IS		 4439 }
4440
0355b59f
IS		 4441 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4442 if (err)
4443 goto err_vport_flood_set;
26f0e7fb 4444
0355b59f
IS		 4445 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4446 if (err)
9c4d4423 4447 goto err_vport_fid_map;
26f0e7fb 4448
41b996cc 4449 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f 4450 f->ref_count++;
6a9863a6 4451
22305378
IS		 4452 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4453
0355b59f 4454 return 0;
039c49a6 4455
0355b59f
IS		 4456err_vport_fid_map:
4457 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4458err_vport_flood_set:
d0ec875a 4459 if (!f->ref_count)
3ba2ebf4 4460 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
0355b59f
IS		 4461 return err;
4462}
26f0e7fb 4463
3ba2ebf4 4464static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f 4465{
41b996cc 4466 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb 4467
22305378
IS		 4468 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4469
0355b59f 4470 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
26f0e7fb 4471
0355b59f
IS		 4472 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4473
fe3f6d14
IS		 4474 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4475
41b996cc 4476 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f 4477 if (--f->ref_count == 0)
3ba2ebf4 4478 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
26f0e7fb
IS		 4479}
4480
4481static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4482 struct net_device *br_dev)
4483{
99724c18 4484 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb
IS		 4485 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4486 struct net_device *dev = mlxsw_sp_vport->dev;
26f0e7fb
IS		 4487 int err;
4488
99724c18
IS		 4489 if (f && !WARN_ON(!f->leave))
4490 f->leave(mlxsw_sp_vport);
26f0e7fb 4491
3ba2ebf4 4492 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
26f0e7fb 4493 if (err) {
0355b59f 4494 netdev_err(dev, "Failed to join vFID\n");
99724c18 4495 return err;
26f0e7fb
IS		 4496 }
4497
4498 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4499 if (err) {
4500 netdev_err(dev, "Failed to enable learning\n");
4501 goto err_port_vid_learning_set;
4502 }
4503
26f0e7fb
IS		 4504 mlxsw_sp_vport->learning = 1;
4505 mlxsw_sp_vport->learning_sync = 1;
4506 mlxsw_sp_vport->uc_flood = 1;
4507 mlxsw_sp_vport->bridged = 1;
4508
4509 return 0;
4510
26f0e7fb 4511err_port_vid_learning_set:
3ba2ebf4 4512 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
26f0e7fb
IS		 4513 return err;
4514}
4515
fe3f6d14 4516static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f
IS		 4517{
4518 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
0355b59f
IS		 4519
4520 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4521
3ba2ebf4 4522 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
0355b59f 4523
0355b59f
IS		 4524 mlxsw_sp_vport->learning = 0;
4525 mlxsw_sp_vport->learning_sync = 0;
4526 mlxsw_sp_vport->uc_flood = 0;
4527 mlxsw_sp_vport->bridged = 0;
4528}
4529
26f0e7fb
IS		 4530static bool
4531mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4532 const struct net_device *br_dev)
4533{
4534 struct mlxsw_sp_port *mlxsw_sp_vport;
4535
4536 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4537 vport.list) {
3ba2ebf4 4538 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
56918b6b
IS		 4539
4540 if (dev && dev == br_dev)
26f0e7fb
IS		 4541 return false;
4542 }
4543
4544 return true;
4545}
4546
4547static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4548 unsigned long event, void *ptr,
4549 u16 vid)
4550{
4551 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4552 struct netdev_notifier_changeupper_info *info = ptr;
4553 struct mlxsw_sp_port *mlxsw_sp_vport;
4554 struct net_device *upper_dev;
80bedf1a 4555 int err = 0;
26f0e7fb
IS		 4556
4557 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4558
4559 switch (event) {
4560 case NETDEV_PRECHANGEUPPER:
4561 upper_dev = info->upper_dev;
26f0e7fb 4562 if (!netif_is_bridge_master(upper_dev))
80bedf1a 4563 return -EINVAL;
ddbe993d
IS		 4564 if (!info->linking)
4565 break;
26f0e7fb
IS		 4566 /* We can't have multiple VLAN interfaces configured on
4567 * the same port and being members in the same bridge.
4568 */
4569 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
4570 upper_dev))
80bedf1a 4571 return -EINVAL;
26f0e7fb
IS		 4572 break;
4573 case NETDEV_CHANGEUPPER:
4574 upper_dev = info->upper_dev;
26f0e7fb 4575 if (info->linking) {
423b937e 4576 if (WARN_ON(!mlxsw_sp_vport))
80bedf1a 4577 return -EINVAL;
26f0e7fb
IS		 4578 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4579 upper_dev);
26f0e7fb 4580 } else {
26f0e7fb 4581 if (!mlxsw_sp_vport)
80bedf1a 4582 return 0;
fe3f6d14 4583 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
26f0e7fb
IS		 4584 }
4585 }
4586
80bedf1a 4587 return err;
26f0e7fb
IS		 4588}
4589
272c4470
IS		 4590static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4591 unsigned long event, void *ptr,
4592 u16 vid)
4593{
4594 struct net_device *dev;
4595 struct list_head *iter;
4596 int ret;
4597
4598 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4599 if (mlxsw_sp_port_dev_check(dev)) {
4600 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4601 vid);
80bedf1a 4602 if (ret)
272c4470
IS		 4603 return ret;
4604 }
4605 }
4606
80bedf1a 4607 return 0;
272c4470
IS		 4608}
4609
26f0e7fb
IS		 4610static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4611 unsigned long event, void *ptr)
4612{
4613 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4614 u16 vid = vlan_dev_vlan_id(vlan_dev);
4615
272c4470
IS		 4616 if (mlxsw_sp_port_dev_check(real_dev))
4617 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4618 vid);
4619 else if (netif_is_lag_master(real_dev))
4620 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4621 vid);
26f0e7fb 4622
80bedf1a 4623 return 0;
26f0e7fb
IS		 4624}
4625
0d65fc13
JP		 4626static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4627 unsigned long event, void *ptr)
4628{
4629 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
80bedf1a 4630 int err = 0;
0d65fc13 4631
6e095fd4
IS		 4632 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4633 err = mlxsw_sp_netdevice_router_port_event(dev);
4634 else if (mlxsw_sp_port_dev_check(dev))
80bedf1a
IS		 4635 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4636 else if (netif_is_lag_master(dev))
4637 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
701b186e
IS		 4638 else if (netif_is_bridge_master(dev))
4639 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
80bedf1a
IS		 4640 else if (is_vlan_dev(dev))
4641 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 4642
80bedf1a 4643 return notifier_from_errno(err);
0d65fc13
JP		 4644}
4645
56ade8fe
JP		 4646static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4647 .notifier_call = mlxsw_sp_netdevice_event,
4648};
4649
99724c18
IS		 4650static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4651 .notifier_call = mlxsw_sp_inetaddr_event,
4652 .priority = 10, /* Must be called before FIB notifier block */
4653};
4654
e7322638
JP		 4655static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4656 .notifier_call = mlxsw_sp_router_netevent_event,
4657};
4658
1d20d23c
JP		 4659static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4660 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4661 {0, },
4662};
4663
4664static struct pci_driver mlxsw_sp_pci_driver = {
4665 .name = mlxsw_sp_driver_name,
4666 .id_table = mlxsw_sp_pci_id_table,
4667};
4668
56ade8fe
JP		 4669static int __init mlxsw_sp_module_init(void)
4670{
4671 int err;
4672
4673 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
99724c18 4674 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
e7322638
JP		 4675 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4676
56ade8fe
JP		 4677 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4678 if (err)
4679 goto err_core_driver_register;
1d20d23c
JP		 4680
4681 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4682 if (err)
4683 goto err_pci_driver_register;
4684
56ade8fe
JP		 4685 return 0;
4686
1d20d23c
JP		 4687err_pci_driver_register:
4688 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 4689err_core_driver_register:
e7322638 4690 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
de7d6295 4691 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4692 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4693 return err;
4694}
4695
4696static void __exit mlxsw_sp_module_exit(void)
4697{
1d20d23c 4698 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 4699 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
e7322638 4700 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
99724c18 4701 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
56ade8fe
JP		 4702 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4703}
4704
4705module_init(mlxsw_sp_module_init);
4706module_exit(mlxsw_sp_module_exit);
4707
4708MODULE_LICENSE("Dual BSD/GPL");
4709MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4710MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 4711MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
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