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mlxsw: spectrum: Initialize ports at the end of init sequence
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
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56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
7f71eb46 51#include <linux/list.h>
80bedf1a 52#include <linux/notifier.h>
90183b98 53#include <linux/dcbnl.h>
56ade8fe
JP		 54#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
56ade8fe
JP		 192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
be94535f
IS		 251static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
252 u8 swid)
56ade8fe 253{
56ade8fe
JP		 254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
be94535f 256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
56ade8fe
JP		 257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
be94535f
IS		 260static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
261{
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
263
264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
265 swid);
266}
267
56ade8fe
JP		 268static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
269 bool enable)
270{
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
273
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
276}
277
278int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
280 u16 vid)
281{
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
284
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
286 fid, vid);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
288}
289
290static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
292{
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
294 char *spvmlr_pl;
295 int err;
296
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
298 if (!spvmlr_pl)
299 return -ENOMEM;
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
301 learn_enable);
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
303 kfree(spvmlr_pl);
304 return err;
305}
306
307static int
308mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
309{
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
312
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
315}
316
d664b41e
IS		 317static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
56ade8fe 320{
56ade8fe
JP		 321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
322 int err;
323
558c2d5e 324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
326 if (err)
327 return err;
558c2d5e
IS		 328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 331 return 0;
332}
333
18f1e70c
IS		 334static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
336{
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
338 int i;
339
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
345 }
346
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
348}
349
3e9b27b8
IS		 350static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
351{
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
353
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357}
358
56ade8fe
JP		 359static int mlxsw_sp_port_open(struct net_device *dev)
360{
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
362 int err;
363
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
365 if (err)
366 return err;
367 netif_start_queue(dev);
368 return 0;
369}
370
371static int mlxsw_sp_port_stop(struct net_device *dev)
372{
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
374
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
377}
378
379static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
381{
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
387 .is_emad = false,
388 };
389 u64 len;
390 int err;
391
307c2431 392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 393 return NETDEV_TX_BUSY;
394
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
397
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
399 if (!skb) {
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
402 return NETDEV_TX_OK;
403 }
404 }
405
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
408 return NETDEV_TX_OK;
409 }
410
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 412 /* TX header is consumed by HW on the way so we shouldn't count its
413 * bytes as being sent.
414 */
415 len = skb->len - MLXSW_TXHDR_LEN;
416
56ade8fe
JP		 417 /* Due to a race we might fail here because of a full queue. In that
418 * unlikely case we simply drop the packet.
419 */
307c2431 420 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 421
422 if (!err) {
423 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
424 u64_stats_update_begin(&pcpu_stats->syncp);
425 pcpu_stats->tx_packets++;
426 pcpu_stats->tx_bytes += len;
427 u64_stats_update_end(&pcpu_stats->syncp);
428 } else {
429 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
430 dev_kfree_skb_any(skb);
431 }
432 return NETDEV_TX_OK;
433}
434
c5b9b518
JP		 435static void mlxsw_sp_set_rx_mode(struct net_device *dev)
436{
437}
438
56ade8fe
JP		 439static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
440{
441 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
442 struct sockaddr *addr = p;
443 int err;
444
445 if (!is_valid_ether_addr(addr->sa_data))
446 return -EADDRNOTAVAIL;
447
448 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
449 if (err)
450 return err;
451 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
452 return 0;
453}
454
9f7ec052 455static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
d81a6bdb 456 bool pause_en, bool pfc_en, u16 delay)
ff6551ec 457{
ff6551ec 458 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
8e8dfe9f 459
d81a6bdb
IS		 460 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
461 MLXSW_SP_PAUSE_DELAY;
9f7ec052 462
d81a6bdb 463 if (pause_en || pfc_en)
9f7ec052 464 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
d81a6bdb
IS		 465 pg_size + delay, pg_size);
466 else
9f7ec052 467 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
8e8dfe9f
IS		 468}
469
470int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 471 u8 *prio_tc, bool pause_en,
472 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 473{
474 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 475 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
476 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 477 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 478 int i, j, err;
ff6551ec
IS		 479
480 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
481 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
482 if (err)
483 return err;
8e8dfe9f
IS		 484
485 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
486 bool configure = false;
d81a6bdb 487 bool pfc = false;
8e8dfe9f
IS		 488
489 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
490 if (prio_tc[j] == i) {
d81a6bdb 491 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 492 configure = true;
493 break;
494 }
495 }
496
497 if (!configure)
498 continue;
d81a6bdb 499 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
8e8dfe9f
IS		 500 }
501
ff6551ec
IS		 502 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
503}
504
8e8dfe9f 505static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 506 int mtu, bool pause_en)
8e8dfe9f
IS		 507{
508 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
509 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 510 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 511 u8 *prio_tc;
512
513 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 514 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 515
9f7ec052 516 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 517 pause_en, my_pfc);
8e8dfe9f
IS		 518}
519
56ade8fe
JP		 520static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
521{
522 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 523 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 524 int err;
525
9f7ec052 526 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 527 if (err)
528 return err;
ff6551ec
IS		 529 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
530 if (err)
531 goto err_port_mtu_set;
56ade8fe
JP		 532 dev->mtu = mtu;
533 return 0;
ff6551ec
IS		 534
535err_port_mtu_set:
9f7ec052 536 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 537 return err;
56ade8fe
JP		 538}
539
540static struct rtnl_link_stats64 *
541mlxsw_sp_port_get_stats64(struct net_device *dev,
542 struct rtnl_link_stats64 *stats)
543{
544 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
545 struct mlxsw_sp_port_pcpu_stats *p;
546 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
547 u32 tx_dropped = 0;
548 unsigned int start;
549 int i;
550
551 for_each_possible_cpu(i) {
552 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
553 do {
554 start = u64_stats_fetch_begin_irq(&p->syncp);
555 rx_packets = p->rx_packets;
556 rx_bytes = p->rx_bytes;
557 tx_packets = p->tx_packets;
558 tx_bytes = p->tx_bytes;
559 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
560
561 stats->rx_packets += rx_packets;
562 stats->rx_bytes += rx_bytes;
563 stats->tx_packets += tx_packets;
564 stats->tx_bytes += tx_bytes;
565 /* tx_dropped is u32, updated without syncp protection. */
566 tx_dropped += p->tx_dropped;
567 }
568 stats->tx_dropped = tx_dropped;
569 return stats;
570}
571
572int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
573 u16 vid_end, bool is_member, bool untagged)
574{
575 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
576 char *spvm_pl;
577 int err;
578
579 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
580 if (!spvm_pl)
581 return -ENOMEM;
582
583 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
584 vid_end, is_member, untagged);
585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
586 kfree(spvm_pl);
587 return err;
588}
589
590static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
591{
592 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
593 u16 vid, last_visited_vid;
594 int err;
595
596 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
597 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
598 vid);
599 if (err) {
600 last_visited_vid = vid;
601 goto err_port_vid_to_fid_set;
602 }
603 }
604
605 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
606 if (err) {
607 last_visited_vid = VLAN_N_VID;
608 goto err_port_vid_to_fid_set;
609 }
610
611 return 0;
612
613err_port_vid_to_fid_set:
614 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
615 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
616 vid);
617 return err;
618}
619
620static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
621{
622 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
623 u16 vid;
624 int err;
625
626 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
627 if (err)
628 return err;
629
630 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
631 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
632 vid, vid);
633 if (err)
634 return err;
635 }
636
637 return 0;
638}
639
d0ec875a 640static struct mlxsw_sp_fid *
7f71eb46
IS		 641mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
642{
d0ec875a 643 struct mlxsw_sp_fid *f;
7f71eb46 644
d0ec875a
IS		 645 list_for_each_entry(f, &mlxsw_sp->port_vfids.list, list) {
646 if (f->vid == vid)
647 return f;
7f71eb46
IS		 648 }
649
650 return NULL;
651}
652
653static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
654{
655 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
656 MLXSW_SP_VFID_PORT_MAX);
657}
658
c7e920b5 659static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
7f71eb46 660{
7f71eb46
IS		 661 char sfmr_pl[MLXSW_REG_SFMR_LEN];
662
c7e920b5 663 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
7f71eb46
IS		 664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
665}
666
1c800759
IS		 667static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
668
d0ec875a
IS		 669static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
670 u16 vid)
7f71eb46
IS		 671{
672 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 673 struct mlxsw_sp_fid *f;
c7e920b5 674 u16 vfid, fid;
7f71eb46
IS		 675 int err;
676
c7e920b5
IS		 677 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
678 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
7f71eb46
IS		 679 dev_err(dev, "No available vFIDs\n");
680 return ERR_PTR(-ERANGE);
681 }
682
c7e920b5
IS		 683 fid = mlxsw_sp_vfid_to_fid(vfid);
684 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
7f71eb46 685 if (err) {
c7e920b5 686 dev_err(dev, "Failed to create FID=%d\n", fid);
7f71eb46
IS		 687 return ERR_PTR(err);
688 }
689
c7e920b5
IS		 690 f = kzalloc(sizeof(*f), GFP_KERNEL);
691 if (!f)
7f71eb46
IS		 692 goto err_allocate_vfid;
693
1c800759 694 f->leave = mlxsw_sp_vport_vfid_leave;
d0ec875a 695 f->fid = fid;
c7e920b5 696 f->vid = vid;
7f71eb46 697
c7e920b5
IS		 698 list_add(&f->list, &mlxsw_sp->port_vfids.list);
699 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
7f71eb46 700
c7e920b5 701 return f;
7f71eb46
IS		 702
703err_allocate_vfid:
c7e920b5 704 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
7f71eb46
IS		 705 return ERR_PTR(-ENOMEM);
706}
707
708static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
d0ec875a 709 struct mlxsw_sp_fid *f)
7f71eb46 710{
d0ec875a 711 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
c7e920b5 712
d0ec875a
IS		 713 clear_bit(vfid, mlxsw_sp->port_vfids.mapped);
714 list_del(&f->list);
7f71eb46 715
d0ec875a 716 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
7f71eb46 717
d0ec875a 718 kfree(f);
7f71eb46
IS		 719}
720
721static struct mlxsw_sp_port *
0355b59f 722mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
7f71eb46
IS		 723{
724 struct mlxsw_sp_port *mlxsw_sp_vport;
725
726 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
727 if (!mlxsw_sp_vport)
728 return NULL;
729
730 /* dev will be set correctly after the VLAN device is linked
731 * with the real device. In case of bridge SELF invocation, dev
732 * will remain as is.
733 */
734 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
735 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
736 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
737 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
272c4470
IS		 738 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
739 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
0355b59f 740 mlxsw_sp_vport->vport.vid = vid;
7f71eb46
IS		 741
742 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
743
744 return mlxsw_sp_vport;
745}
746
747static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
748{
749 list_del(&mlxsw_sp_vport->vport.list);
750 kfree(mlxsw_sp_vport);
751}
752
9c4d4423
IS		 753static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
754 bool valid)
755{
756 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
757 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
758
759 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
760 vid);
761}
762
0355b59f
IS		 763static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport)
764{
765 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
766 struct mlxsw_sp_fid *f;
767 int err;
768
769 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, vid);
770 if (!f) {
771 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, vid);
772 if (IS_ERR(f))
773 return PTR_ERR(f);
774 }
775
776 if (!f->ref_count) {
777 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
778 if (err)
779 goto err_vport_flood_set;
780 }
781
782 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
783 if (err)
784 goto err_vport_fid_map;
785
41b996cc 786 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f
IS		 787 f->ref_count++;
788
789 return 0;
790
791err_vport_fid_map:
792 if (!f->ref_count)
793 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
794err_vport_flood_set:
795 if (!f->ref_count)
796 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
797 return err;
798}
799
800static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
801{
41b996cc 802 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
0355b59f 803
41b996cc 804 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f
IS		 805
806 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
807
808 if (--f->ref_count == 0) {
809 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
810 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
811 }
812}
813
56ade8fe
JP		 814int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
815 u16 vid)
816{
817 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 818 struct mlxsw_sp_port *mlxsw_sp_vport;
52697a9e 819 bool untagged = vid == 1;
56ade8fe
JP		 820 int err;
821
822 /* VLAN 0 is added to HW filter when device goes up, but it is
823 * reserved in our case, so simply return.
824 */
825 if (!vid)
826 return 0;
827
7f71eb46 828 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
56ade8fe
JP		 829 netdev_warn(dev, "VID=%d already configured\n", vid);
830 return 0;
831 }
832
0355b59f 833 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
7f71eb46
IS		 834 if (!mlxsw_sp_vport) {
835 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
0355b59f 836 return -ENOMEM;
56ade8fe
JP		 837 }
838
56ade8fe
JP		 839 /* When adding the first VLAN interface on a bridged port we need to
840 * transition all the active 802.1Q bridge VLANs to use explicit
841 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
842 */
7f71eb46 843 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 844 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
845 if (err) {
846 netdev_err(dev, "Failed to set to Virtual mode\n");
7f71eb46 847 goto err_port_vp_mode_trans;
56ade8fe
JP		 848 }
849 }
850
0355b59f 851 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
56ade8fe 852 if (err) {
0355b59f
IS		 853 netdev_err(dev, "Failed to join vFID\n");
854 goto err_vport_vfid_join;
56ade8fe
JP		 855 }
856
7f71eb46 857 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
56ade8fe
JP		 858 if (err) {
859 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
860 goto err_port_vid_learning_set;
861 }
862
52697a9e 863 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
56ade8fe
JP		 864 if (err) {
865 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
866 vid);
867 goto err_port_add_vid;
868 }
869
7f71eb46 870 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 871 MLXSW_REG_SPMS_STATE_FORWARDING);
872 if (err) {
873 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
874 goto err_port_stp_state_set;
875 }
876
56ade8fe
JP		 877 return 0;
878
56ade8fe 879err_port_stp_state_set:
7f71eb46 880 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe 881err_port_add_vid:
7f71eb46 882 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe 883err_port_vid_learning_set:
0355b59f
IS		 884 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
885err_vport_vfid_join:
7f71eb46
IS		 886 if (list_is_singular(&mlxsw_sp_port->vports_list))
887 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
888err_port_vp_mode_trans:
7f71eb46 889 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
56ade8fe
JP		 890 return err;
891}
892
32d863fb
IS		 893static int mlxsw_sp_port_kill_vid(struct net_device *dev,
894 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 895{
896 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
7f71eb46 897 struct mlxsw_sp_port *mlxsw_sp_vport;
1c800759 898 struct mlxsw_sp_fid *f;
56ade8fe
JP		 899 int err;
900
901 /* VLAN 0 is removed from HW filter when device goes down, but
902 * it is reserved in our case, so simply return.
903 */
904 if (!vid)
905 return 0;
906
7f71eb46
IS		 907 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
908 if (!mlxsw_sp_vport) {
56ade8fe
JP		 909 netdev_warn(dev, "VID=%d does not exist\n", vid);
910 return 0;
911 }
912
7f71eb46 913 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
56ade8fe
JP		 914 MLXSW_REG_SPMS_STATE_DISCARDING);
915 if (err) {
916 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
917 return err;
918 }
919
7f71eb46 920 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
56ade8fe
JP		 921 if (err) {
922 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
923 vid);
924 return err;
925 }
926
7f71eb46 927 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
56ade8fe
JP		 928 if (err) {
929 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
930 return err;
931 }
932
1c800759
IS		 933 /* Drop FID reference. If this was the last reference the
934 * resources will be freed.
935 */
936 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
937 if (f && !WARN_ON(!f->leave))
938 f->leave(mlxsw_sp_vport);
56ade8fe
JP		 939
940 /* When removing the last VLAN interface on a bridged port we need to
941 * transition all active 802.1Q bridge VLANs to use VID to FID
942 * mappings and set port's mode to VLAN mode.
943 */
7f71eb46 944 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
56ade8fe
JP		 945 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
946 if (err) {
947 netdev_err(dev, "Failed to set to VLAN mode\n");
948 return err;
949 }
950 }
951
7f71eb46
IS		 952 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
953
56ade8fe
JP		 954 return 0;
955}
956
2bf9a586
IS		 957static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
958 size_t len)
959{
960 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 961 u8 module = mlxsw_sp_port->mapping.module;
962 u8 width = mlxsw_sp_port->mapping.width;
963 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 964 int err;
965
2bf9a586
IS		 966 if (!mlxsw_sp_port->split)
967 err = snprintf(name, len, "p%d", module + 1);
968 else
969 err = snprintf(name, len, "p%ds%d", module + 1,
970 lane / width);
971
972 if (err >= len)
973 return -EINVAL;
974
975 return 0;
976}
977
56ade8fe
JP		 978static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
979 .ndo_open = mlxsw_sp_port_open,
980 .ndo_stop = mlxsw_sp_port_stop,
981 .ndo_start_xmit = mlxsw_sp_port_xmit,
c5b9b518 982 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 983 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
984 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
985 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
986 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
987 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
988 .ndo_fdb_add = switchdev_port_fdb_add,
989 .ndo_fdb_del = switchdev_port_fdb_del,
990 .ndo_fdb_dump = switchdev_port_fdb_dump,
991 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
992 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
993 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
2bf9a586 994 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 995};
996
997static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
998 struct ethtool_drvinfo *drvinfo)
999{
1000 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1001 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1002
1003 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1004 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1005 sizeof(drvinfo->version));
1006 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1007 "%d.%d.%d",
1008 mlxsw_sp->bus_info->fw_rev.major,
1009 mlxsw_sp->bus_info->fw_rev.minor,
1010 mlxsw_sp->bus_info->fw_rev.subminor);
1011 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1012 sizeof(drvinfo->bus_info));
1013}
1014
9f7ec052
IS		 1015static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1016 struct ethtool_pauseparam *pause)
1017{
1018 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1019
1020 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1021 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1022}
1023
1024static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1025 struct ethtool_pauseparam *pause)
1026{
1027 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1028
1029 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1030 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1031 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1032
1033 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1034 pfcc_pl);
1035}
1036
1037static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1038 struct ethtool_pauseparam *pause)
1039{
1040 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1041 bool pause_en = pause->tx_pause || pause->rx_pause;
1042 int err;
1043
d81a6bdb
IS		 1044 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1045 netdev_err(dev, "PFC already enabled on port\n");
1046 return -EINVAL;
1047 }
1048
9f7ec052
IS		 1049 if (pause->autoneg) {
1050 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1051 return -EINVAL;
1052 }
1053
1054 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1055 if (err) {
1056 netdev_err(dev, "Failed to configure port's headroom\n");
1057 return err;
1058 }
1059
1060 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1061 if (err) {
1062 netdev_err(dev, "Failed to set PAUSE parameters\n");
1063 goto err_port_pause_configure;
1064 }
1065
1066 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1067 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1068
1069 return 0;
1070
1071err_port_pause_configure:
1072 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1073 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1074 return err;
1075}
1076
56ade8fe
JP		 1077struct mlxsw_sp_port_hw_stats {
1078 char str[ETH_GSTRING_LEN];
1079 u64 (*getter)(char *payload);
1080};
1081
1082static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1083 {
1084 .str = "a_frames_transmitted_ok",
1085 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1086 },
1087 {
1088 .str = "a_frames_received_ok",
1089 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1090 },
1091 {
1092 .str = "a_frame_check_sequence_errors",
1093 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1094 },
1095 {
1096 .str = "a_alignment_errors",
1097 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1098 },
1099 {
1100 .str = "a_octets_transmitted_ok",
1101 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1102 },
1103 {
1104 .str = "a_octets_received_ok",
1105 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1106 },
1107 {
1108 .str = "a_multicast_frames_xmitted_ok",
1109 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1110 },
1111 {
1112 .str = "a_broadcast_frames_xmitted_ok",
1113 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1114 },
1115 {
1116 .str = "a_multicast_frames_received_ok",
1117 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1118 },
1119 {
1120 .str = "a_broadcast_frames_received_ok",
1121 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1122 },
1123 {
1124 .str = "a_in_range_length_errors",
1125 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1126 },
1127 {
1128 .str = "a_out_of_range_length_field",
1129 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1130 },
1131 {
1132 .str = "a_frame_too_long_errors",
1133 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1134 },
1135 {
1136 .str = "a_symbol_error_during_carrier",
1137 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1138 },
1139 {
1140 .str = "a_mac_control_frames_transmitted",
1141 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1142 },
1143 {
1144 .str = "a_mac_control_frames_received",
1145 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1146 },
1147 {
1148 .str = "a_unsupported_opcodes_received",
1149 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1150 },
1151 {
1152 .str = "a_pause_mac_ctrl_frames_received",
1153 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1154 },
1155 {
1156 .str = "a_pause_mac_ctrl_frames_xmitted",
1157 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1158 },
1159};
1160
1161#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1162
1163static void mlxsw_sp_port_get_strings(struct net_device *dev,
1164 u32 stringset, u8 *data)
1165{
1166 u8 *p = data;
1167 int i;
1168
1169 switch (stringset) {
1170 case ETH_SS_STATS:
1171 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1172 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1173 ETH_GSTRING_LEN);
1174 p += ETH_GSTRING_LEN;
1175 }
1176 break;
1177 }
1178}
1179
3a66ee38
IS		 1180static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1181 enum ethtool_phys_id_state state)
1182{
1183 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1184 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1185 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1186 bool active;
1187
1188 switch (state) {
1189 case ETHTOOL_ID_ACTIVE:
1190 active = true;
1191 break;
1192 case ETHTOOL_ID_INACTIVE:
1193 active = false;
1194 break;
1195 default:
1196 return -EOPNOTSUPP;
1197 }
1198
1199 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1201}
1202
56ade8fe
JP		 1203static void mlxsw_sp_port_get_stats(struct net_device *dev,
1204 struct ethtool_stats *stats, u64 *data)
1205{
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1207 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1208 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1209 int i;
1210 int err;
1211
34dba0a5
IS		 1212 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1213 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
56ade8fe
JP		 1214 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1215 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1216 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1217}
1218
1219static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1220{
1221 switch (sset) {
1222 case ETH_SS_STATS:
1223 return MLXSW_SP_PORT_HW_STATS_LEN;
1224 default:
1225 return -EOPNOTSUPP;
1226 }
1227}
1228
1229struct mlxsw_sp_port_link_mode {
1230 u32 mask;
1231 u32 supported;
1232 u32 advertised;
1233 u32 speed;
1234};
1235
1236static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1237 {
1238 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1239 .supported = SUPPORTED_100baseT_Full,
1240 .advertised = ADVERTISED_100baseT_Full,
1241 .speed = 100,
1242 },
1243 {
1244 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1245 .speed = 100,
1246 },
1247 {
1248 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1249 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1250 .supported = SUPPORTED_1000baseKX_Full,
1251 .advertised = ADVERTISED_1000baseKX_Full,
1252 .speed = 1000,
1253 },
1254 {
1255 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1256 .supported = SUPPORTED_10000baseT_Full,
1257 .advertised = ADVERTISED_10000baseT_Full,
1258 .speed = 10000,
1259 },
1260 {
1261 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1262 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1263 .supported = SUPPORTED_10000baseKX4_Full,
1264 .advertised = ADVERTISED_10000baseKX4_Full,
1265 .speed = 10000,
1266 },
1267 {
1268 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1269 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1270 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1271 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1272 .supported = SUPPORTED_10000baseKR_Full,
1273 .advertised = ADVERTISED_10000baseKR_Full,
1274 .speed = 10000,
1275 },
1276 {
1277 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1278 .supported = SUPPORTED_20000baseKR2_Full,
1279 .advertised = ADVERTISED_20000baseKR2_Full,
1280 .speed = 20000,
1281 },
1282 {
1283 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1284 .supported = SUPPORTED_40000baseCR4_Full,
1285 .advertised = ADVERTISED_40000baseCR4_Full,
1286 .speed = 40000,
1287 },
1288 {
1289 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1290 .supported = SUPPORTED_40000baseKR4_Full,
1291 .advertised = ADVERTISED_40000baseKR4_Full,
1292 .speed = 40000,
1293 },
1294 {
1295 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1296 .supported = SUPPORTED_40000baseSR4_Full,
1297 .advertised = ADVERTISED_40000baseSR4_Full,
1298 .speed = 40000,
1299 },
1300 {
1301 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1302 .supported = SUPPORTED_40000baseLR4_Full,
1303 .advertised = ADVERTISED_40000baseLR4_Full,
1304 .speed = 40000,
1305 },
1306 {
1307 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1308 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1309 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1310 .speed = 25000,
1311 },
1312 {
1313 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1314 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1315 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1316 .speed = 50000,
1317 },
1318 {
1319 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1320 .supported = SUPPORTED_56000baseKR4_Full,
1321 .advertised = ADVERTISED_56000baseKR4_Full,
1322 .speed = 56000,
1323 },
1324 {
1325 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1326 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1327 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1328 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1329 .speed = 100000,
1330 },
1331};
1332
1333#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1334
1335static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1336{
1337 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1338 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1339 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1340 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1341 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1342 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1343 return SUPPORTED_FIBRE;
1344
1345 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1346 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1347 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1348 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1349 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1350 return SUPPORTED_Backplane;
1351 return 0;
1352}
1353
1354static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1355{
1356 u32 modes = 0;
1357 int i;
1358
1359 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1360 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1361 modes |= mlxsw_sp_port_link_mode[i].supported;
1362 }
1363 return modes;
1364}
1365
1366static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1367{
1368 u32 modes = 0;
1369 int i;
1370
1371 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1372 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1373 modes |= mlxsw_sp_port_link_mode[i].advertised;
1374 }
1375 return modes;
1376}
1377
1378static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1379 struct ethtool_cmd *cmd)
1380{
1381 u32 speed = SPEED_UNKNOWN;
1382 u8 duplex = DUPLEX_UNKNOWN;
1383 int i;
1384
1385 if (!carrier_ok)
1386 goto out;
1387
1388 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1389 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1390 speed = mlxsw_sp_port_link_mode[i].speed;
1391 duplex = DUPLEX_FULL;
1392 break;
1393 }
1394 }
1395out:
1396 ethtool_cmd_speed_set(cmd, speed);
1397 cmd->duplex = duplex;
1398}
1399
1400static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1401{
1402 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1403 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1404 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1405 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1406 return PORT_FIBRE;
1407
1408 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1409 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1410 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1411 return PORT_DA;
1412
1413 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1414 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1415 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1416 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1417 return PORT_NONE;
1418
1419 return PORT_OTHER;
1420}
1421
1422static int mlxsw_sp_port_get_settings(struct net_device *dev,
1423 struct ethtool_cmd *cmd)
1424{
1425 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1426 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1427 char ptys_pl[MLXSW_REG_PTYS_LEN];
1428 u32 eth_proto_cap;
1429 u32 eth_proto_admin;
1430 u32 eth_proto_oper;
1431 int err;
1432
1433 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1434 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1435 if (err) {
1436 netdev_err(dev, "Failed to get proto");
1437 return err;
1438 }
1439 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1440 &eth_proto_admin, &eth_proto_oper);
1441
1442 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1443 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1444 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1445 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1446 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1447 eth_proto_oper, cmd);
1448
1449 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1450 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1451 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1452
1453 cmd->transceiver = XCVR_INTERNAL;
1454 return 0;
1455}
1456
1457static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1458{
1459 u32 ptys_proto = 0;
1460 int i;
1461
1462 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1463 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1464 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1465 }
1466 return ptys_proto;
1467}
1468
1469static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1470{
1471 u32 ptys_proto = 0;
1472 int i;
1473
1474 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1475 if (speed == mlxsw_sp_port_link_mode[i].speed)
1476 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1477 }
1478 return ptys_proto;
1479}
1480
18f1e70c
IS		 1481static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1482{
1483 u32 ptys_proto = 0;
1484 int i;
1485
1486 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1487 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1488 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1489 }
1490 return ptys_proto;
1491}
1492
56ade8fe
JP		 1493static int mlxsw_sp_port_set_settings(struct net_device *dev,
1494 struct ethtool_cmd *cmd)
1495{
1496 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1498 char ptys_pl[MLXSW_REG_PTYS_LEN];
1499 u32 speed;
1500 u32 eth_proto_new;
1501 u32 eth_proto_cap;
1502 u32 eth_proto_admin;
1503 bool is_up;
1504 int err;
1505
1506 speed = ethtool_cmd_speed(cmd);
1507
1508 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1509 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1510 mlxsw_sp_to_ptys_speed(speed);
1511
1512 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1513 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1514 if (err) {
1515 netdev_err(dev, "Failed to get proto");
1516 return err;
1517 }
1518 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1519
1520 eth_proto_new = eth_proto_new & eth_proto_cap;
1521 if (!eth_proto_new) {
1522 netdev_err(dev, "Not supported proto admin requested");
1523 return -EINVAL;
1524 }
1525 if (eth_proto_new == eth_proto_admin)
1526 return 0;
1527
1528 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1529 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1530 if (err) {
1531 netdev_err(dev, "Failed to set proto admin");
1532 return err;
1533 }
1534
1535 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1536 if (err) {
1537 netdev_err(dev, "Failed to get oper status");
1538 return err;
1539 }
1540 if (!is_up)
1541 return 0;
1542
1543 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1544 if (err) {
1545 netdev_err(dev, "Failed to set admin status");
1546 return err;
1547 }
1548
1549 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1550 if (err) {
1551 netdev_err(dev, "Failed to set admin status");
1552 return err;
1553 }
1554
1555 return 0;
1556}
1557
1558static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1559 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1560 .get_link = ethtool_op_get_link,
9f7ec052
IS		 1561 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1562 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 1563 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 1564 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 1565 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1566 .get_sset_count = mlxsw_sp_port_get_sset_count,
1567 .get_settings = mlxsw_sp_port_get_settings,
1568 .set_settings = mlxsw_sp_port_set_settings,
1569};
1570
18f1e70c
IS		 1571static int
1572mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1573{
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1576 char ptys_pl[MLXSW_REG_PTYS_LEN];
1577 u32 eth_proto_admin;
1578
1579 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1580 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1581 eth_proto_admin);
1582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1583}
1584
8e8dfe9f
IS		 1585int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1586 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1587 bool dwrr, u8 dwrr_weight)
90183b98
IS		 1588{
1589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1590 char qeec_pl[MLXSW_REG_QEEC_LEN];
1591
1592 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1593 next_index);
1594 mlxsw_reg_qeec_de_set(qeec_pl, true);
1595 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1596 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1598}
1599
cc7cf517
IS		 1600int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1601 enum mlxsw_reg_qeec_hr hr, u8 index,
1602 u8 next_index, u32 maxrate)
90183b98
IS		 1603{
1604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1605 char qeec_pl[MLXSW_REG_QEEC_LEN];
1606
1607 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1608 next_index);
1609 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1610 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1611 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1612}
1613
8e8dfe9f
IS		 1614int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1615 u8 switch_prio, u8 tclass)
90183b98
IS		 1616{
1617 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1618 char qtct_pl[MLXSW_REG_QTCT_LEN];
1619
1620 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1621 tclass);
1622 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1623}
1624
1625static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1626{
1627 int err, i;
1628
1629 /* Setup the elements hierarcy, so that each TC is linked to
1630 * one subgroup, which are all member in the same group.
1631 */
1632 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1633 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1634 0);
1635 if (err)
1636 return err;
1637 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1638 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1639 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1640 0, false, 0);
1641 if (err)
1642 return err;
1643 }
1644 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1645 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1646 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1647 false, 0);
1648 if (err)
1649 return err;
1650 }
1651
1652 /* Make sure the max shaper is disabled in all hierarcies that
1653 * support it.
1654 */
1655 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1656 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1657 MLXSW_REG_QEEC_MAS_DIS);
1658 if (err)
1659 return err;
1660 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1661 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1662 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1663 i, 0,
1664 MLXSW_REG_QEEC_MAS_DIS);
1665 if (err)
1666 return err;
1667 }
1668 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1669 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1670 MLXSW_REG_QEEC_HIERARCY_TC,
1671 i, i,
1672 MLXSW_REG_QEEC_MAS_DIS);
1673 if (err)
1674 return err;
1675 }
1676
1677 /* Map all priorities to traffic class 0. */
1678 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1679 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1680 if (err)
1681 return err;
1682 }
1683
1684 return 0;
1685}
1686
be94535f 1687static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
d664b41e 1688 bool split, u8 module, u8 width, u8 lane)
56ade8fe
JP		 1689{
1690 struct mlxsw_sp_port *mlxsw_sp_port;
1691 struct net_device *dev;
bd40e9d6 1692 size_t bytes;
56ade8fe
JP		 1693 int err;
1694
1695 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1696 if (!dev)
1697 return -ENOMEM;
1698 mlxsw_sp_port = netdev_priv(dev);
1699 mlxsw_sp_port->dev = dev;
1700 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1701 mlxsw_sp_port->local_port = local_port;
18f1e70c 1702 mlxsw_sp_port->split = split;
d664b41e
IS		 1703 mlxsw_sp_port->mapping.module = module;
1704 mlxsw_sp_port->mapping.width = width;
1705 mlxsw_sp_port->mapping.lane = lane;
bd40e9d6
IS		 1706 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1707 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1708 if (!mlxsw_sp_port->active_vlans) {
1709 err = -ENOMEM;
1710 goto err_port_active_vlans_alloc;
1711 }
fc1273af
ER		 1712 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1713 if (!mlxsw_sp_port->untagged_vlans) {
1714 err = -ENOMEM;
1715 goto err_port_untagged_vlans_alloc;
1716 }
7f71eb46 1717 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
56ade8fe
JP		 1718
1719 mlxsw_sp_port->pcpu_stats =
1720 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1721 if (!mlxsw_sp_port->pcpu_stats) {
1722 err = -ENOMEM;
1723 goto err_alloc_stats;
1724 }
1725
1726 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1727 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1728
1729 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1730 if (err) {
1731 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1732 mlxsw_sp_port->local_port);
1733 goto err_dev_addr_init;
1734 }
1735
1736 netif_carrier_off(dev);
1737
1738 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1739 NETIF_F_HW_VLAN_CTAG_FILTER;
1740
1741 /* Each packet needs to have a Tx header (metadata) on top all other
1742 * headers.
1743 */
1744 dev->hard_header_len += MLXSW_TXHDR_LEN;
1745
56ade8fe
JP		 1746 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1747 if (err) {
1748 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1749 mlxsw_sp_port->local_port);
1750 goto err_port_system_port_mapping_set;
1751 }
1752
1753 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1754 if (err) {
1755 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1756 mlxsw_sp_port->local_port);
1757 goto err_port_swid_set;
1758 }
1759
18f1e70c
IS		 1760 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1761 if (err) {
1762 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1763 mlxsw_sp_port->local_port);
1764 goto err_port_speed_by_width_set;
1765 }
1766
56ade8fe
JP		 1767 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1768 if (err) {
1769 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1770 mlxsw_sp_port->local_port);
1771 goto err_port_mtu_set;
1772 }
1773
1774 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1775 if (err)
1776 goto err_port_admin_status_set;
1777
1778 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1779 if (err) {
1780 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1781 mlxsw_sp_port->local_port);
1782 goto err_port_buffers_init;
1783 }
1784
90183b98
IS		 1785 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1786 if (err) {
1787 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1788 mlxsw_sp_port->local_port);
1789 goto err_port_ets_init;
1790 }
1791
f00817df
IS		 1792 /* ETS and buffers must be initialized before DCB. */
1793 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1794 if (err) {
1795 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1796 mlxsw_sp_port->local_port);
1797 goto err_port_dcb_init;
1798 }
1799
56ade8fe
JP		 1800 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1801 err = register_netdev(dev);
1802 if (err) {
1803 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1804 mlxsw_sp_port->local_port);
1805 goto err_register_netdev;
1806 }
1807
932762b6
JP		 1808 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1809 mlxsw_sp_port->local_port, dev,
1810 mlxsw_sp_port->split, module);
1811 if (err) {
1812 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1813 mlxsw_sp_port->local_port);
1814 goto err_core_port_init;
1815 }
c4745500 1816
56ade8fe
JP		 1817 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1818 if (err)
1819 goto err_port_vlan_init;
1820
1821 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1822 return 0;
1823
1824err_port_vlan_init:
932762b6
JP		 1825 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1826err_core_port_init:
56ade8fe
JP		 1827 unregister_netdev(dev);
1828err_register_netdev:
f00817df 1829err_port_dcb_init:
90183b98 1830err_port_ets_init:
56ade8fe
JP		 1831err_port_buffers_init:
1832err_port_admin_status_set:
1833err_port_mtu_set:
18f1e70c 1834err_port_speed_by_width_set:
56ade8fe
JP		 1835err_port_swid_set:
1836err_port_system_port_mapping_set:
56ade8fe
JP		 1837err_dev_addr_init:
1838 free_percpu(mlxsw_sp_port->pcpu_stats);
1839err_alloc_stats:
fc1273af
ER		 1840 kfree(mlxsw_sp_port->untagged_vlans);
1841err_port_untagged_vlans_alloc:
bd40e9d6
IS		 1842 kfree(mlxsw_sp_port->active_vlans);
1843err_port_active_vlans_alloc:
56ade8fe
JP		 1844 free_netdev(dev);
1845 return err;
1846}
1847
56ade8fe
JP		 1848static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1849{
1850 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1851
1852 if (!mlxsw_sp_port)
1853 return;
a133318c 1854 mlxsw_sp->ports[local_port] = NULL;
932762b6 1855 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
56ade8fe 1856 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
f00817df 1857 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
32d863fb 1858 mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
56ade8fe 1859 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3e9b27b8
IS		 1860 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1861 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
56ade8fe 1862 free_percpu(mlxsw_sp_port->pcpu_stats);
fc1273af 1863 kfree(mlxsw_sp_port->untagged_vlans);
bd40e9d6 1864 kfree(mlxsw_sp_port->active_vlans);
32d863fb 1865 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
56ade8fe
JP		 1866 free_netdev(mlxsw_sp_port->dev);
1867}
1868
1869static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1870{
1871 int i;
1872
1873 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1874 mlxsw_sp_port_remove(mlxsw_sp, i);
1875 kfree(mlxsw_sp->ports);
1876}
1877
1878static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1879{
d664b41e 1880 u8 module, width, lane;
56ade8fe
JP		 1881 size_t alloc_size;
1882 int i;
1883 int err;
1884
1885 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1886 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1887 if (!mlxsw_sp->ports)
1888 return -ENOMEM;
1889
1890 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
558c2d5e 1891 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 1892 &width, &lane);
558c2d5e
IS		 1893 if (err)
1894 goto err_port_module_info_get;
1895 if (!width)
1896 continue;
1897 mlxsw_sp->port_to_module[i] = module;
d664b41e
IS		 1898 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1899 lane);
56ade8fe
JP		 1900 if (err)
1901 goto err_port_create;
1902 }
1903 return 0;
1904
1905err_port_create:
558c2d5e 1906err_port_module_info_get:
56ade8fe
JP		 1907 for (i--; i >= 1; i--)
1908 mlxsw_sp_port_remove(mlxsw_sp, i);
1909 kfree(mlxsw_sp->ports);
1910 return err;
1911}
1912
18f1e70c
IS		 1913static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1914{
1915 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1916
1917 return local_port - offset;
1918}
1919
be94535f
IS		 1920static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1921 u8 module, unsigned int count)
1922{
1923 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1924 int err, i;
1925
1926 for (i = 0; i < count; i++) {
1927 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1928 width, i * width);
1929 if (err)
1930 goto err_port_module_map;
1931 }
1932
1933 for (i = 0; i < count; i++) {
1934 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1935 if (err)
1936 goto err_port_swid_set;
1937 }
1938
1939 for (i = 0; i < count; i++) {
1940 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 1941 module, width, i * width);
be94535f
IS		 1942 if (err)
1943 goto err_port_create;
1944 }
1945
1946 return 0;
1947
1948err_port_create:
1949 for (i--; i >= 0; i--)
1950 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1951 i = count;
1952err_port_swid_set:
1953 for (i--; i >= 0; i--)
1954 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1955 MLXSW_PORT_SWID_DISABLED_PORT);
1956 i = count;
1957err_port_module_map:
1958 for (i--; i >= 0; i--)
1959 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1960 return err;
1961}
1962
1963static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1964 u8 base_port, unsigned int count)
1965{
1966 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1967 int i;
1968
1969 /* Split by four means we need to re-create two ports, otherwise
1970 * only one.
1971 */
1972 count = count / 2;
1973
1974 for (i = 0; i < count; i++) {
1975 local_port = base_port + i * 2;
1976 module = mlxsw_sp->port_to_module[local_port];
1977
1978 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1979 0);
1980 }
1981
1982 for (i = 0; i < count; i++)
1983 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1984
1985 for (i = 0; i < count; i++) {
1986 local_port = base_port + i * 2;
1987 module = mlxsw_sp->port_to_module[local_port];
1988
1989 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 1990 width, 0);
be94535f
IS		 1991 }
1992}
1993
b2f10571
JP		 1994static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1995 unsigned int count)
18f1e70c 1996{
b2f10571 1997 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 1998 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 1999 u8 module, cur_width, base_port;
2000 int i;
2001 int err;
2002
2003 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2004 if (!mlxsw_sp_port) {
2005 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2006 local_port);
2007 return -EINVAL;
2008 }
2009
d664b41e
IS		 2010 module = mlxsw_sp_port->mapping.module;
2011 cur_width = mlxsw_sp_port->mapping.width;
2012
18f1e70c
IS		 2013 if (count != 2 && count != 4) {
2014 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2015 return -EINVAL;
2016 }
2017
18f1e70c
IS		 2018 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2019 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2020 return -EINVAL;
2021 }
2022
2023 /* Make sure we have enough slave (even) ports for the split. */
2024 if (count == 2) {
2025 base_port = local_port;
2026 if (mlxsw_sp->ports[base_port + 1]) {
2027 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2028 return -EINVAL;
2029 }
2030 } else {
2031 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2032 if (mlxsw_sp->ports[base_port + 1] ||
2033 mlxsw_sp->ports[base_port + 3]) {
2034 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2035 return -EINVAL;
2036 }
2037 }
2038
2039 for (i = 0; i < count; i++)
2040 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2041
be94535f
IS		 2042 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2043 if (err) {
2044 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2045 goto err_port_split_create;
18f1e70c
IS		 2046 }
2047
2048 return 0;
2049
be94535f
IS		 2050err_port_split_create:
2051 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2052 return err;
2053}
2054
b2f10571 2055static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 2056{
b2f10571 2057 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 2058 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 2059 u8 cur_width, base_port;
18f1e70c
IS		 2060 unsigned int count;
2061 int i;
18f1e70c
IS		 2062
2063 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2064 if (!mlxsw_sp_port) {
2065 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2066 local_port);
2067 return -EINVAL;
2068 }
2069
2070 if (!mlxsw_sp_port->split) {
2071 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2072 return -EINVAL;
2073 }
2074
d664b41e 2075 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 2076 count = cur_width == 1 ? 4 : 2;
2077
2078 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2079
2080 /* Determine which ports to remove. */
2081 if (count == 2 && local_port >= base_port + 2)
2082 base_port = base_port + 2;
2083
2084 for (i = 0; i < count; i++)
2085 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2086
be94535f 2087 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 2088
2089 return 0;
2090}
2091
56ade8fe
JP		 2092static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2093 char *pude_pl, void *priv)
2094{
2095 struct mlxsw_sp *mlxsw_sp = priv;
2096 struct mlxsw_sp_port *mlxsw_sp_port;
2097 enum mlxsw_reg_pude_oper_status status;
2098 u8 local_port;
2099
2100 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2101 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 2102 if (!mlxsw_sp_port)
56ade8fe 2103 return;
56ade8fe
JP		 2104
2105 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2106 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2107 netdev_info(mlxsw_sp_port->dev, "link up\n");
2108 netif_carrier_on(mlxsw_sp_port->dev);
2109 } else {
2110 netdev_info(mlxsw_sp_port->dev, "link down\n");
2111 netif_carrier_off(mlxsw_sp_port->dev);
2112 }
2113}
2114
2115static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2116 .func = mlxsw_sp_pude_event_func,
2117 .trap_id = MLXSW_TRAP_ID_PUDE,
2118};
2119
2120static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2121 enum mlxsw_event_trap_id trap_id)
2122{
2123 struct mlxsw_event_listener *el;
2124 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2125 int err;
2126
2127 switch (trap_id) {
2128 case MLXSW_TRAP_ID_PUDE:
2129 el = &mlxsw_sp_pude_event;
2130 break;
2131 }
2132 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2133 if (err)
2134 return err;
2135
2136 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2137 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2138 if (err)
2139 goto err_event_trap_set;
2140
2141 return 0;
2142
2143err_event_trap_set:
2144 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2145 return err;
2146}
2147
2148static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2149 enum mlxsw_event_trap_id trap_id)
2150{
2151 struct mlxsw_event_listener *el;
2152
2153 switch (trap_id) {
2154 case MLXSW_TRAP_ID_PUDE:
2155 el = &mlxsw_sp_pude_event;
2156 break;
2157 }
2158 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2159}
2160
2161static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2162 void *priv)
2163{
2164 struct mlxsw_sp *mlxsw_sp = priv;
2165 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2166 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2167
2168 if (unlikely(!mlxsw_sp_port)) {
2169 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2170 local_port);
2171 return;
2172 }
2173
2174 skb->dev = mlxsw_sp_port->dev;
2175
2176 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2177 u64_stats_update_begin(&pcpu_stats->syncp);
2178 pcpu_stats->rx_packets++;
2179 pcpu_stats->rx_bytes += skb->len;
2180 u64_stats_update_end(&pcpu_stats->syncp);
2181
2182 skb->protocol = eth_type_trans(skb, skb->dev);
2183 netif_receive_skb(skb);
2184}
2185
2186static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2187 {
2188 .func = mlxsw_sp_rx_listener_func,
2189 .local_port = MLXSW_PORT_DONT_CARE,
2190 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2191 },
2192 /* Traps for specific L2 packet types, not trapped as FDB MC */
2193 {
2194 .func = mlxsw_sp_rx_listener_func,
2195 .local_port = MLXSW_PORT_DONT_CARE,
2196 .trap_id = MLXSW_TRAP_ID_STP,
2197 },
2198 {
2199 .func = mlxsw_sp_rx_listener_func,
2200 .local_port = MLXSW_PORT_DONT_CARE,
2201 .trap_id = MLXSW_TRAP_ID_LACP,
2202 },
2203 {
2204 .func = mlxsw_sp_rx_listener_func,
2205 .local_port = MLXSW_PORT_DONT_CARE,
2206 .trap_id = MLXSW_TRAP_ID_EAPOL,
2207 },
2208 {
2209 .func = mlxsw_sp_rx_listener_func,
2210 .local_port = MLXSW_PORT_DONT_CARE,
2211 .trap_id = MLXSW_TRAP_ID_LLDP,
2212 },
2213 {
2214 .func = mlxsw_sp_rx_listener_func,
2215 .local_port = MLXSW_PORT_DONT_CARE,
2216 .trap_id = MLXSW_TRAP_ID_MMRP,
2217 },
2218 {
2219 .func = mlxsw_sp_rx_listener_func,
2220 .local_port = MLXSW_PORT_DONT_CARE,
2221 .trap_id = MLXSW_TRAP_ID_MVRP,
2222 },
2223 {
2224 .func = mlxsw_sp_rx_listener_func,
2225 .local_port = MLXSW_PORT_DONT_CARE,
2226 .trap_id = MLXSW_TRAP_ID_RPVST,
2227 },
2228 {
2229 .func = mlxsw_sp_rx_listener_func,
2230 .local_port = MLXSW_PORT_DONT_CARE,
2231 .trap_id = MLXSW_TRAP_ID_DHCP,
2232 },
2233 {
2234 .func = mlxsw_sp_rx_listener_func,
2235 .local_port = MLXSW_PORT_DONT_CARE,
2236 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2237 },
2238 {
2239 .func = mlxsw_sp_rx_listener_func,
2240 .local_port = MLXSW_PORT_DONT_CARE,
2241 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2242 },
2243 {
2244 .func = mlxsw_sp_rx_listener_func,
2245 .local_port = MLXSW_PORT_DONT_CARE,
2246 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2247 },
2248 {
2249 .func = mlxsw_sp_rx_listener_func,
2250 .local_port = MLXSW_PORT_DONT_CARE,
2251 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2252 },
2253 {
2254 .func = mlxsw_sp_rx_listener_func,
2255 .local_port = MLXSW_PORT_DONT_CARE,
2256 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2257 },
2258};
2259
2260static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2261{
2262 char htgt_pl[MLXSW_REG_HTGT_LEN];
2263 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2264 int i;
2265 int err;
2266
2267 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2268 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2269 if (err)
2270 return err;
2271
2272 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2273 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2274 if (err)
2275 return err;
2276
2277 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2278 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2279 &mlxsw_sp_rx_listener[i],
2280 mlxsw_sp);
2281 if (err)
2282 goto err_rx_listener_register;
2283
2284 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2285 mlxsw_sp_rx_listener[i].trap_id);
2286 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2287 if (err)
2288 goto err_rx_trap_set;
2289 }
2290 return 0;
2291
2292err_rx_trap_set:
2293 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2294 &mlxsw_sp_rx_listener[i],
2295 mlxsw_sp);
2296err_rx_listener_register:
2297 for (i--; i >= 0; i--) {
2298 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2299 mlxsw_sp_rx_listener[i].trap_id);
2300 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2301
2302 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2303 &mlxsw_sp_rx_listener[i],
2304 mlxsw_sp);
2305 }
2306 return err;
2307}
2308
2309static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2310{
2311 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2312 int i;
2313
2314 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2315 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2316 mlxsw_sp_rx_listener[i].trap_id);
2317 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2318
2319 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2320 &mlxsw_sp_rx_listener[i],
2321 mlxsw_sp);
2322 }
2323}
2324
2325static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2326 enum mlxsw_reg_sfgc_type type,
2327 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2328{
2329 enum mlxsw_flood_table_type table_type;
2330 enum mlxsw_sp_flood_table flood_table;
2331 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2332
19ae6124 2333 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
56ade8fe 2334 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
19ae6124 2335 else
56ade8fe 2336 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
19ae6124
IS		 2337
2338 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2339 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2340 else
2341 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
56ade8fe
JP		 2342
2343 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2344 flood_table);
2345 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2346}
2347
2348static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2349{
2350 int type, err;
2351
56ade8fe
JP		 2352 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2353 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2354 continue;
2355
2356 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2357 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2358 if (err)
2359 return err;
56ade8fe
JP		 2360
2361 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2362 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2363 if (err)
2364 return err;
2365 }
2366
2367 return 0;
2368}
2369
0d65fc13
JP		 2370static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2371{
2372 char slcr_pl[MLXSW_REG_SLCR_LEN];
2373
2374 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2375 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2376 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2377 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2378 MLXSW_REG_SLCR_LAG_HASH_SIP |
2379 MLXSW_REG_SLCR_LAG_HASH_DIP |
2380 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2381 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2382 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2383 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2384}
2385
b2f10571 2386static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 2387 const struct mlxsw_bus_info *mlxsw_bus_info)
2388{
b2f10571 2389 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 2390 int err;
2391
2392 mlxsw_sp->core = mlxsw_core;
2393 mlxsw_sp->bus_info = mlxsw_bus_info;
14d39461 2394 INIT_LIST_HEAD(&mlxsw_sp->fids);
7f71eb46 2395 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
26f0e7fb 2396 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
3a49b4fd 2397 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
56ade8fe
JP		 2398
2399 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2400 if (err) {
2401 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2402 return err;
2403 }
2404
56ade8fe
JP		 2405 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2406 if (err) {
2407 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
bbf2a475 2408 return err;
56ade8fe
JP		 2409 }
2410
2411 err = mlxsw_sp_traps_init(mlxsw_sp);
2412 if (err) {
2413 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2414 goto err_rx_listener_register;
2415 }
2416
2417 err = mlxsw_sp_flood_init(mlxsw_sp);
2418 if (err) {
2419 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2420 goto err_flood_init;
2421 }
2422
2423 err = mlxsw_sp_buffers_init(mlxsw_sp);
2424 if (err) {
2425 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2426 goto err_buffers_init;
2427 }
2428
0d65fc13
JP		 2429 err = mlxsw_sp_lag_init(mlxsw_sp);
2430 if (err) {
2431 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2432 goto err_lag_init;
2433 }
2434
56ade8fe
JP		 2435 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2436 if (err) {
2437 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2438 goto err_switchdev_init;
2439 }
2440
bbf2a475
IS		 2441 err = mlxsw_sp_ports_create(mlxsw_sp);
2442 if (err) {
2443 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
2444 goto err_ports_create;
2445 }
2446
56ade8fe
JP		 2447 return 0;
2448
bbf2a475
IS		 2449err_ports_create:
2450 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 2451err_switchdev_init:
0d65fc13 2452err_lag_init:
0f433fa0 2453 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 2454err_buffers_init:
2455err_flood_init:
2456 mlxsw_sp_traps_fini(mlxsw_sp);
2457err_rx_listener_register:
2458 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
56ade8fe
JP		 2459 return err;
2460}
2461
b2f10571 2462static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 2463{
b2f10571 2464 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 2465
bbf2a475 2466 mlxsw_sp_ports_remove(mlxsw_sp);
56ade8fe 2467 mlxsw_sp_switchdev_fini(mlxsw_sp);
5113bfdb 2468 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe
JP		 2469 mlxsw_sp_traps_fini(mlxsw_sp);
2470 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
14d39461 2471 WARN_ON(!list_empty(&mlxsw_sp->fids));
56ade8fe
JP		 2472}
2473
2474static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2475 .used_max_vepa_channels = 1,
2476 .max_vepa_channels = 0,
2477 .used_max_lag = 1,
0d65fc13 2478 .max_lag = MLXSW_SP_LAG_MAX,
56ade8fe 2479 .used_max_port_per_lag = 1,
0d65fc13 2480 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
56ade8fe 2481 .used_max_mid = 1,
53ae6283 2482 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 2483 .used_max_pgt = 1,
2484 .max_pgt = 0,
2485 .used_max_system_port = 1,
2486 .max_system_port = 64,
2487 .used_max_vlan_groups = 1,
2488 .max_vlan_groups = 127,
2489 .used_max_regions = 1,
2490 .max_regions = 400,
2491 .used_flood_tables = 1,
2492 .used_flood_mode = 1,
2493 .flood_mode = 3,
2494 .max_fid_offset_flood_tables = 2,
2495 .fid_offset_flood_table_size = VLAN_N_VID - 1,
19ae6124
IS		 2496 .max_fid_flood_tables = 2,
2497 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
56ade8fe
JP		 2498 .used_max_ib_mc = 1,
2499 .max_ib_mc = 0,
2500 .used_max_pkey = 1,
2501 .max_pkey = 0,
2502 .swid_config = {
2503 {
2504 .used_type = 1,
2505 .type = MLXSW_PORT_SWID_TYPE_ETH,
2506 }
2507 },
2508};
2509
2510static struct mlxsw_driver mlxsw_sp_driver = {
2d0ed39f
JP		 2511 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2512 .owner = THIS_MODULE,
2513 .priv_size = sizeof(struct mlxsw_sp),
2514 .init = mlxsw_sp_init,
2515 .fini = mlxsw_sp_fini,
2516 .port_split = mlxsw_sp_port_split,
2517 .port_unsplit = mlxsw_sp_port_unsplit,
2518 .sb_pool_get = mlxsw_sp_sb_pool_get,
2519 .sb_pool_set = mlxsw_sp_sb_pool_set,
2520 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2521 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2522 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2523 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2524 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2525 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2526 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2527 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2528 .txhdr_construct = mlxsw_sp_txhdr_construct,
2529 .txhdr_len = MLXSW_TXHDR_LEN,
2530 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 2531};
2532
fe3f6d14
IS		 2533static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
2534 u16 fid)
2535{
2536 if (mlxsw_sp_fid_is_vfid(fid))
2537 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
2538 else
2539 return test_bit(fid, lag_port->active_vlans);
2540}
2541
2542static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
2543 u16 fid)
039c49a6
IS		 2544{
2545 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
fe3f6d14
IS		 2546 u8 local_port = mlxsw_sp_port->local_port;
2547 u16 lag_id = mlxsw_sp_port->lag_id;
2548 int i, count = 0;
039c49a6 2549
fe3f6d14
IS		 2550 if (!mlxsw_sp_port->lagged)
2551 return true;
039c49a6 2552
fe3f6d14
IS		 2553 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2554 struct mlxsw_sp_port *lag_port;
2555
2556 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
2557 if (!lag_port || lag_port->local_port == local_port)
2558 continue;
2559 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
2560 count++;
2561 }
2562
2563 return !count;
039c49a6
IS		 2564}
2565
2566static int
2567mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2568 u16 fid)
2569{
2570 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2571 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2572
2573 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2574 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2575 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2576 mlxsw_sp_port->local_port);
2577
22305378
IS		 2578 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
2579 mlxsw_sp_port->local_port, fid);
2580
039c49a6
IS		 2581 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2582}
2583
039c49a6
IS		 2584static int
2585mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2586 u16 fid)
2587{
2588 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2589 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2590
2591 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2592 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2593 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2594
22305378
IS		 2595 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
2596 mlxsw_sp_port->lag_id, fid);
2597
039c49a6
IS		 2598 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2599}
2600
fe3f6d14 2601int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
039c49a6 2602{
fe3f6d14
IS		 2603 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
2604 return 0;
039c49a6 2605
fe3f6d14
IS		 2606 if (mlxsw_sp_port->lagged)
2607 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
039c49a6
IS		 2608 fid);
2609 else
fe3f6d14 2610 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
039c49a6
IS		 2611}
2612
56ade8fe
JP		 2613static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2614{
2615 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2616}
2617
7117a570
IS		 2618static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2619 struct net_device *br_dev)
2620{
2621 return !mlxsw_sp->master_bridge.dev ||
2622 mlxsw_sp->master_bridge.dev == br_dev;
2623}
2624
2625static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2626 struct net_device *br_dev)
2627{
2628 mlxsw_sp->master_bridge.dev = br_dev;
2629 mlxsw_sp->master_bridge.ref_count++;
2630}
2631
2632static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2633{
2634 if (--mlxsw_sp->master_bridge.ref_count == 0)
2635 mlxsw_sp->master_bridge.dev = NULL;
2636}
2637
2638static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2639 struct net_device *br_dev)
56ade8fe
JP		 2640{
2641 struct net_device *dev = mlxsw_sp_port->dev;
2642 int err;
2643
2644 /* When port is not bridged untagged packets are tagged with
2645 * PVID=VID=1, thereby creating an implicit VLAN interface in
2646 * the device. Remove it and let bridge code take care of its
2647 * own VLANs.
2648 */
2649 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
6c72a3d0
IS		 2650 if (err)
2651 return err;
56ade8fe 2652
7117a570
IS		 2653 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2654
6c72a3d0
IS		 2655 mlxsw_sp_port->learning = 1;
2656 mlxsw_sp_port->learning_sync = 1;
2657 mlxsw_sp_port->uc_flood = 1;
2658 mlxsw_sp_port->bridged = 1;
2659
2660 return 0;
56ade8fe
JP		 2661}
2662
fe3f6d14 2663static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
56ade8fe
JP		 2664{
2665 struct net_device *dev = mlxsw_sp_port->dev;
5a8f4525 2666
28a01d2d
IS		 2667 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2668
7117a570
IS		 2669 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2670
6c72a3d0
IS		 2671 mlxsw_sp_port->learning = 0;
2672 mlxsw_sp_port->learning_sync = 0;
2673 mlxsw_sp_port->uc_flood = 0;
5a8f4525 2674 mlxsw_sp_port->bridged = 0;
56ade8fe
JP		 2675
2676 /* Add implicit VLAN interface in the device, so that untagged
2677 * packets will be classified to the default vFID.
2678 */
82e6db03 2679 mlxsw_sp_port_add_vid(dev, 0, 1);
56ade8fe
JP		 2680}
2681
0d65fc13
JP		 2682static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2683{
2684 char sldr_pl[MLXSW_REG_SLDR_LEN];
2685
2686 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2687 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2688}
2689
2690static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2691{
2692 char sldr_pl[MLXSW_REG_SLDR_LEN];
2693
2694 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2695 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2696}
2697
2698static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2699 u16 lag_id, u8 port_index)
2700{
2701 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2702 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2703
2704 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2705 lag_id, port_index);
2706 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2707}
2708
2709static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2710 u16 lag_id)
2711{
2712 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2713 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2714
2715 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2716 lag_id);
2717 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2718}
2719
2720static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2721 u16 lag_id)
2722{
2723 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2724 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2725
2726 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2727 lag_id);
2728 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2729}
2730
2731static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2732 u16 lag_id)
2733{
2734 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2735 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2736
2737 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2738 lag_id);
2739 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2740}
2741
2742static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2743 struct net_device *lag_dev,
2744 u16 *p_lag_id)
2745{
2746 struct mlxsw_sp_upper *lag;
2747 int free_lag_id = -1;
2748 int i;
2749
2750 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2751 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2752 if (lag->ref_count) {
2753 if (lag->dev == lag_dev) {
2754 *p_lag_id = i;
2755 return 0;
2756 }
2757 } else if (free_lag_id < 0) {
2758 free_lag_id = i;
2759 }
2760 }
2761 if (free_lag_id < 0)
2762 return -EBUSY;
2763 *p_lag_id = free_lag_id;
2764 return 0;
2765}
2766
2767static bool
2768mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2769 struct net_device *lag_dev,
2770 struct netdev_lag_upper_info *lag_upper_info)
2771{
2772 u16 lag_id;
2773
2774 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2775 return false;
2776 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2777 return false;
2778 return true;
2779}
2780
2781static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2782 u16 lag_id, u8 *p_port_index)
2783{
2784 int i;
2785
2786 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2787 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2788 *p_port_index = i;
2789 return 0;
2790 }
2791 }
2792 return -EBUSY;
2793}
2794
86bf95b3
IS		 2795static void
2796mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2797 u16 lag_id)
2798{
2799 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 2800 struct mlxsw_sp_fid *f;
86bf95b3
IS		 2801
2802 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
2803 if (WARN_ON(!mlxsw_sp_vport))
2804 return;
2805
11943ff4
IS		 2806 /* If vPort is assigned a RIF, then leave it since it's no
2807 * longer valid.
2808 */
2809 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
2810 if (f)
2811 f->leave(mlxsw_sp_vport);
2812
86bf95b3
IS		 2813 mlxsw_sp_vport->lag_id = lag_id;
2814 mlxsw_sp_vport->lagged = 1;
2815}
2816
2817static void
2818mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
2819{
2820 struct mlxsw_sp_port *mlxsw_sp_vport;
11943ff4 2821 struct mlxsw_sp_fid *f;
86bf95b3
IS		 2822
2823 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
2824 if (WARN_ON(!mlxsw_sp_vport))
2825 return;
2826
11943ff4
IS		 2827 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
2828 if (f)
2829 f->leave(mlxsw_sp_vport);
2830
86bf95b3
IS		 2831 mlxsw_sp_vport->lagged = 0;
2832}
2833
0d65fc13
JP		 2834static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2835 struct net_device *lag_dev)
2836{
2837 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2838 struct mlxsw_sp_upper *lag;
2839 u16 lag_id;
2840 u8 port_index;
2841 int err;
2842
2843 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2844 if (err)
2845 return err;
2846 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2847 if (!lag->ref_count) {
2848 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2849 if (err)
2850 return err;
2851 lag->dev = lag_dev;
2852 }
2853
2854 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2855 if (err)
2856 return err;
2857 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2858 if (err)
2859 goto err_col_port_add;
2860 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2861 if (err)
2862 goto err_col_port_enable;
2863
2864 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2865 mlxsw_sp_port->local_port);
2866 mlxsw_sp_port->lag_id = lag_id;
2867 mlxsw_sp_port->lagged = 1;
2868 lag->ref_count++;
86bf95b3
IS		 2869
2870 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
2871
0d65fc13
JP		 2872 return 0;
2873
51554db2
IS		 2874err_col_port_enable:
2875 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 2876err_col_port_add:
2877 if (!lag->ref_count)
2878 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 2879 return err;
2880}
2881
82e6db03
IS		 2882static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2883 struct net_device *lag_dev)
0d65fc13
JP		 2884{
2885 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 2886 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 2887 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 2888
2889 if (!mlxsw_sp_port->lagged)
82e6db03 2890 return;
0d65fc13
JP		 2891 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2892 WARN_ON(lag->ref_count == 0);
2893
82e6db03
IS		 2894 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2895 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 2896
4dc236c3
IS		 2897 if (mlxsw_sp_port->bridged) {
2898 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
fe3f6d14 2899 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4dc236c3
IS		 2900 }
2901
fe3f6d14 2902 if (lag->ref_count == 1)
82e6db03 2903 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 2904
2905 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2906 mlxsw_sp_port->local_port);
2907 mlxsw_sp_port->lagged = 0;
2908 lag->ref_count--;
86bf95b3
IS		 2909
2910 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
0d65fc13
JP		 2911}
2912
74581206
JP		 2913static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2914 u16 lag_id)
2915{
2916 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2917 char sldr_pl[MLXSW_REG_SLDR_LEN];
2918
2919 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2920 mlxsw_sp_port->local_port);
2921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2922}
2923
2924static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2925 u16 lag_id)
2926{
2927 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2928 char sldr_pl[MLXSW_REG_SLDR_LEN];
2929
2930 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2931 mlxsw_sp_port->local_port);
2932 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2933}
2934
2935static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2936 bool lag_tx_enabled)
2937{
2938 if (lag_tx_enabled)
2939 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2940 mlxsw_sp_port->lag_id);
2941 else
2942 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2943 mlxsw_sp_port->lag_id);
2944}
2945
2946static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2947 struct netdev_lag_lower_state_info *info)
2948{
2949 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2950}
2951
9589a7b5
IS		 2952static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2953 struct net_device *vlan_dev)
2954{
2955 struct mlxsw_sp_port *mlxsw_sp_vport;
2956 u16 vid = vlan_dev_vlan_id(vlan_dev);
2957
2958 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 2959 if (WARN_ON(!mlxsw_sp_vport))
9589a7b5 2960 return -EINVAL;
9589a7b5
IS		 2961
2962 mlxsw_sp_vport->dev = vlan_dev;
2963
2964 return 0;
2965}
2966
82e6db03
IS		 2967static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2968 struct net_device *vlan_dev)
9589a7b5
IS		 2969{
2970 struct mlxsw_sp_port *mlxsw_sp_vport;
2971 u16 vid = vlan_dev_vlan_id(vlan_dev);
2972
2973 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
423b937e 2974 if (WARN_ON(!mlxsw_sp_vport))
82e6db03 2975 return;
9589a7b5
IS		 2976
2977 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
9589a7b5
IS		 2978}
2979
74581206
JP		 2980static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
2981 unsigned long event, void *ptr)
56ade8fe 2982{
56ade8fe
JP		 2983 struct netdev_notifier_changeupper_info *info;
2984 struct mlxsw_sp_port *mlxsw_sp_port;
2985 struct net_device *upper_dev;
2986 struct mlxsw_sp *mlxsw_sp;
80bedf1a 2987 int err = 0;
56ade8fe 2988
56ade8fe
JP		 2989 mlxsw_sp_port = netdev_priv(dev);
2990 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2991 info = ptr;
2992
2993 switch (event) {
2994 case NETDEV_PRECHANGEUPPER:
2995 upper_dev = info->upper_dev;
59fe9b3f
IS		 2996 if (!is_vlan_dev(upper_dev) &&
2997 !netif_is_lag_master(upper_dev) &&
2998 !netif_is_bridge_master(upper_dev))
2999 return -EINVAL;
6ec43904 3000 if (!info->linking)
0d65fc13 3001 break;
56ade8fe 3002 /* HW limitation forbids to put ports to multiple bridges. */
0d65fc13 3003 if (netif_is_bridge_master(upper_dev) &&
56ade8fe 3004 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
80bedf1a 3005 return -EINVAL;
0d65fc13
JP		 3006 if (netif_is_lag_master(upper_dev) &&
3007 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3008 info->upper_info))
80bedf1a 3009 return -EINVAL;
6ec43904
IS		 3010 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
3011 return -EINVAL;
3012 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
3013 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
3014 return -EINVAL;
56ade8fe
JP		 3015 break;
3016 case NETDEV_CHANGEUPPER:
3017 upper_dev = info->upper_dev;
9589a7b5 3018 if (is_vlan_dev(upper_dev)) {
80bedf1a 3019 if (info->linking)
9589a7b5
IS		 3020 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3021 upper_dev);
80bedf1a 3022 else
82e6db03
IS		 3023 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3024 upper_dev);
9589a7b5 3025 } else if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 3026 if (info->linking)
3027 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3028 upper_dev);
3029 else
fe3f6d14 3030 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
0d65fc13 3031 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 3032 if (info->linking)
0d65fc13
JP		 3033 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3034 upper_dev);
80bedf1a 3035 else
82e6db03
IS		 3036 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3037 upper_dev);
59fe9b3f
IS		 3038 } else {
3039 err = -EINVAL;
3040 WARN_ON(1);
56ade8fe
JP		 3041 }
3042 break;
3043 }
3044
80bedf1a 3045 return err;
56ade8fe
JP		 3046}
3047
74581206
JP		 3048static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3049 unsigned long event, void *ptr)
3050{
3051 struct netdev_notifier_changelowerstate_info *info;
3052 struct mlxsw_sp_port *mlxsw_sp_port;
3053 int err;
3054
3055 mlxsw_sp_port = netdev_priv(dev);
3056 info = ptr;
3057
3058 switch (event) {
3059 case NETDEV_CHANGELOWERSTATE:
3060 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3061 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3062 info->lower_state_info);
3063 if (err)
3064 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3065 }
3066 break;
3067 }
3068
80bedf1a 3069 return 0;
74581206
JP		 3070}
3071
3072static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3073 unsigned long event, void *ptr)
3074{
3075 switch (event) {
3076 case NETDEV_PRECHANGEUPPER:
3077 case NETDEV_CHANGEUPPER:
3078 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3079 case NETDEV_CHANGELOWERSTATE:
3080 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3081 }
3082
80bedf1a 3083 return 0;
74581206
JP		 3084}
3085
0d65fc13
JP		 3086static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3087 unsigned long event, void *ptr)
3088{
3089 struct net_device *dev;
3090 struct list_head *iter;
3091 int ret;
3092
3093 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3094 if (mlxsw_sp_port_dev_check(dev)) {
3095 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
80bedf1a 3096 if (ret)
0d65fc13
JP		 3097 return ret;
3098 }
3099 }
3100
80bedf1a 3101 return 0;
0d65fc13
JP		 3102}
3103
d0ec875a 3104static struct mlxsw_sp_fid *
26f0e7fb
IS		 3105mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3106 const struct net_device *br_dev)
3107{
d0ec875a 3108 struct mlxsw_sp_fid *f;
26f0e7fb 3109
d0ec875a
IS		 3110 list_for_each_entry(f, &mlxsw_sp->br_vfids.list, list) {
3111 if (f->dev == br_dev)
3112 return f;
26f0e7fb
IS		 3113 }
3114
3115 return NULL;
3116}
3117
3118static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3119{
3120 return vfid - MLXSW_SP_VFID_PORT_MAX;
3121}
3122
3123static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3124{
3125 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3126}
3127
3128static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3129{
3130 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3131 MLXSW_SP_VFID_BR_MAX);
3132}
3133
1c800759
IS		 3134static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3135
d0ec875a
IS		 3136static struct mlxsw_sp_fid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3137 struct net_device *br_dev)
26f0e7fb
IS		 3138{
3139 struct device *dev = mlxsw_sp->bus_info->dev;
d0ec875a 3140 struct mlxsw_sp_fid *f;
c7e920b5 3141 u16 vfid, fid;
26f0e7fb
IS		 3142 int err;
3143
c7e920b5
IS		 3144 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3145 if (vfid == MLXSW_SP_VFID_MAX) {
26f0e7fb
IS		 3146 dev_err(dev, "No available vFIDs\n");
3147 return ERR_PTR(-ERANGE);
3148 }
3149
c7e920b5
IS		 3150 fid = mlxsw_sp_vfid_to_fid(vfid);
3151 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
26f0e7fb 3152 if (err) {
c7e920b5 3153 dev_err(dev, "Failed to create FID=%d\n", fid);
26f0e7fb
IS		 3154 return ERR_PTR(err);
3155 }
3156
c7e920b5
IS		 3157 f = kzalloc(sizeof(*f), GFP_KERNEL);
3158 if (!f)
26f0e7fb
IS		 3159 goto err_allocate_vfid;
3160
1c800759 3161 f->leave = mlxsw_sp_vport_br_vfid_leave;
d0ec875a
IS		 3162 f->fid = fid;
3163 f->dev = br_dev;
26f0e7fb 3164
c7e920b5
IS		 3165 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3166 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
26f0e7fb 3167
c7e920b5 3168 return f;
26f0e7fb
IS		 3169
3170err_allocate_vfid:
c7e920b5 3171 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
26f0e7fb
IS		 3172 return ERR_PTR(-ENOMEM);
3173}
3174
3175static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
d0ec875a 3176 struct mlxsw_sp_fid *f)
26f0e7fb 3177{
d0ec875a
IS		 3178 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
3179 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid);
26f0e7fb
IS		 3180
3181 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
d0ec875a 3182 list_del(&f->list);
26f0e7fb 3183
d0ec875a 3184 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
26f0e7fb 3185
d0ec875a 3186 kfree(f);
26f0e7fb
IS		 3187}
3188
0355b59f
IS		 3189static int mlxsw_sp_vport_br_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3190 struct net_device *br_dev)
26f0e7fb 3191{
0355b59f 3192 struct mlxsw_sp_fid *f;
26f0e7fb
IS		 3193 int err;
3194
0355b59f
IS		 3195 f = mlxsw_sp_br_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
3196 if (!f) {
3197 f = mlxsw_sp_br_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
3198 if (IS_ERR(f))
3199 return PTR_ERR(f);
26f0e7fb
IS		 3200 }
3201
0355b59f
IS		 3202 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
3203 if (err)
3204 goto err_vport_flood_set;
26f0e7fb 3205
0355b59f
IS		 3206 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
3207 if (err)
9c4d4423 3208 goto err_vport_fid_map;
26f0e7fb 3209
41b996cc 3210 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
0355b59f 3211 f->ref_count++;
6a9863a6 3212
22305378
IS		 3213 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
3214
0355b59f 3215 return 0;
039c49a6 3216
0355b59f
IS		 3217err_vport_fid_map:
3218 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3219err_vport_flood_set:
d0ec875a 3220 if (!f->ref_count)
0355b59f
IS		 3221 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3222 return err;
3223}
26f0e7fb 3224
0355b59f
IS		 3225static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3226{
41b996cc 3227 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
26f0e7fb 3228
22305378
IS		 3229 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3230
0355b59f 3231 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
26f0e7fb 3232
0355b59f
IS		 3233 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3234
fe3f6d14
IS		 3235 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
3236
41b996cc 3237 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
0355b59f
IS		 3238 if (--f->ref_count == 0)
3239 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
26f0e7fb
IS		 3240}
3241
3242static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3243 struct net_device *br_dev)
3244{
26f0e7fb
IS		 3245 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3246 struct net_device *dev = mlxsw_sp_vport->dev;
26f0e7fb
IS		 3247 int err;
3248
0355b59f 3249 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
26f0e7fb 3250
0355b59f 3251 err = mlxsw_sp_vport_br_vfid_join(mlxsw_sp_vport, br_dev);
26f0e7fb 3252 if (err) {
0355b59f
IS		 3253 netdev_err(dev, "Failed to join vFID\n");
3254 goto err_vport_br_vfid_join;
26f0e7fb
IS		 3255 }
3256
3257 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3258 if (err) {
3259 netdev_err(dev, "Failed to enable learning\n");
3260 goto err_port_vid_learning_set;
3261 }
3262
26f0e7fb
IS		 3263 mlxsw_sp_vport->learning = 1;
3264 mlxsw_sp_vport->learning_sync = 1;
3265 mlxsw_sp_vport->uc_flood = 1;
3266 mlxsw_sp_vport->bridged = 1;
3267
3268 return 0;
3269
26f0e7fb 3270err_port_vid_learning_set:
0355b59f
IS		 3271 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3272err_vport_br_vfid_join:
3273 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
26f0e7fb
IS		 3274 return err;
3275}
3276
fe3f6d14 3277static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
0355b59f
IS		 3278{
3279 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
0355b59f
IS		 3280
3281 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3282
3283 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3284
3285 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3286
3287 mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3288 MLXSW_REG_SPMS_STATE_FORWARDING);
3289
0355b59f
IS		 3290 mlxsw_sp_vport->learning = 0;
3291 mlxsw_sp_vport->learning_sync = 0;
3292 mlxsw_sp_vport->uc_flood = 0;
3293 mlxsw_sp_vport->bridged = 0;
3294}
3295
26f0e7fb
IS		 3296static bool
3297mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3298 const struct net_device *br_dev)
3299{
3300 struct mlxsw_sp_port *mlxsw_sp_vport;
3301
3302 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3303 vport.list) {
56918b6b
IS		 3304 struct net_device *dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
3305
3306 if (dev && dev == br_dev)
26f0e7fb
IS		 3307 return false;
3308 }
3309
3310 return true;
3311}
3312
3313static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3314 unsigned long event, void *ptr,
3315 u16 vid)
3316{
3317 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3318 struct netdev_notifier_changeupper_info *info = ptr;
3319 struct mlxsw_sp_port *mlxsw_sp_vport;
3320 struct net_device *upper_dev;
80bedf1a 3321 int err = 0;
26f0e7fb
IS		 3322
3323 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3324
3325 switch (event) {
3326 case NETDEV_PRECHANGEUPPER:
3327 upper_dev = info->upper_dev;
26f0e7fb 3328 if (!netif_is_bridge_master(upper_dev))
80bedf1a 3329 return -EINVAL;
ddbe993d
IS		 3330 if (!info->linking)
3331 break;
26f0e7fb
IS		 3332 /* We can't have multiple VLAN interfaces configured on
3333 * the same port and being members in the same bridge.
3334 */
3335 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3336 upper_dev))
80bedf1a 3337 return -EINVAL;
26f0e7fb
IS		 3338 break;
3339 case NETDEV_CHANGEUPPER:
3340 upper_dev = info->upper_dev;
26f0e7fb 3341 if (info->linking) {
423b937e 3342 if (WARN_ON(!mlxsw_sp_vport))
80bedf1a 3343 return -EINVAL;
26f0e7fb
IS		 3344 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3345 upper_dev);
26f0e7fb 3346 } else {
26f0e7fb 3347 if (!mlxsw_sp_vport)
80bedf1a 3348 return 0;
fe3f6d14 3349 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
26f0e7fb
IS		 3350 }
3351 }
3352
80bedf1a 3353 return err;
26f0e7fb
IS		 3354}
3355
272c4470
IS		 3356static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3357 unsigned long event, void *ptr,
3358 u16 vid)
3359{
3360 struct net_device *dev;
3361 struct list_head *iter;
3362 int ret;
3363
3364 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3365 if (mlxsw_sp_port_dev_check(dev)) {
3366 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3367 vid);
80bedf1a 3368 if (ret)
272c4470
IS		 3369 return ret;
3370 }
3371 }
3372
80bedf1a 3373 return 0;
272c4470
IS		 3374}
3375
26f0e7fb
IS		 3376static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3377 unsigned long event, void *ptr)
3378{
3379 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3380 u16 vid = vlan_dev_vlan_id(vlan_dev);
3381
272c4470
IS		 3382 if (mlxsw_sp_port_dev_check(real_dev))
3383 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3384 vid);
3385 else if (netif_is_lag_master(real_dev))
3386 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3387 vid);
26f0e7fb 3388
80bedf1a 3389 return 0;
26f0e7fb
IS		 3390}
3391
0d65fc13
JP		 3392static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3393 unsigned long event, void *ptr)
3394{
3395 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
80bedf1a 3396 int err = 0;
0d65fc13
JP		 3397
3398 if (mlxsw_sp_port_dev_check(dev))
80bedf1a
IS		 3399 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3400 else if (netif_is_lag_master(dev))
3401 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3402 else if (is_vlan_dev(dev))
3403 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 3404
80bedf1a 3405 return notifier_from_errno(err);
0d65fc13
JP		 3406}
3407
56ade8fe
JP		 3408static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3409 .notifier_call = mlxsw_sp_netdevice_event,
3410};
3411
3412static int __init mlxsw_sp_module_init(void)
3413{
3414 int err;
3415
3416 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3417 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3418 if (err)
3419 goto err_core_driver_register;
3420 return 0;
3421
3422err_core_driver_register:
3423 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3424 return err;
3425}
3426
3427static void __exit mlxsw_sp_module_exit(void)
3428{
3429 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3430 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3431}
3432
3433module_init(mlxsw_sp_module_init);
3434module_exit(mlxsw_sp_module_exit);
3435
3436MODULE_LICENSE("Dual BSD/GPL");
3437MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3438MODULE_DESCRIPTION("Mellanox Spectrum driver");
3439MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);
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