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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
CommitLineData
56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
22a67766
JP		 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
56ade8fe
JP		 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
c1f2c6d0 56#include <linux/netlink.h>
56ade8fe 57#include <net/switchdev.h>
763b4b70
YG		 58#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
e7322638 60#include <net/netevent.h>
98d0f7b9 61#include <net/tc_act/tc_sample.h>
5ea1237f 62#include <net/addrconf.h>
56ade8fe
JP		 63
64#include "spectrum.h"
1d20d23c 65#include "pci.h"
56ade8fe
JP		 66#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
ff7b0d27 71#include "spectrum_cnt.h"
230ead01 72#include "spectrum_dpipe.h"
d3b939b8 73#include "spectrum_acl_flex_actions.h"
e5e5c88a 74#include "../mlxfw/mlxfw.h"
56ade8fe 75
6b742199 76#define MLXSW_FWREV_MAJOR 13
2f53fbd5
ST		 77#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
6b742199
YG		 79
80static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
81 .major = MLXSW_FWREV_MAJOR,
82 .minor = MLXSW_FWREV_MINOR,
83 .subminor = MLXSW_FWREV_SUBMINOR
84};
85
86#define MLXSW_SP_FW_FILENAME \
a4e1ce24 87 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
6b742199
YG		 88 "." __stringify(MLXSW_FWREV_MINOR) \
89 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
90
56ade8fe
JP		 91static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
92static const char mlxsw_sp_driver_version[] = "1.0";
93
94/* tx_hdr_version
95 * Tx header version.
96 * Must be set to 1.
97 */
98MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
99
100/* tx_hdr_ctl
101 * Packet control type.
102 * 0 - Ethernet control (e.g. EMADs, LACP)
103 * 1 - Ethernet data
104 */
105MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
106
107/* tx_hdr_proto
108 * Packet protocol type. Must be set to 1 (Ethernet).
109 */
110MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
111
112/* tx_hdr_rx_is_router
113 * Packet is sent from the router. Valid for data packets only.
114 */
115MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
116
117/* tx_hdr_fid_valid
118 * Indicates if the 'fid' field is valid and should be used for
119 * forwarding lookup. Valid for data packets only.
120 */
121MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
122
123/* tx_hdr_swid
124 * Switch partition ID. Must be set to 0.
125 */
126MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
127
128/* tx_hdr_control_tclass
129 * Indicates if the packet should use the control TClass and not one
130 * of the data TClasses.
131 */
132MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
133
134/* tx_hdr_etclass
135 * Egress TClass to be used on the egress device on the egress port.
136 */
137MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
138
139/* tx_hdr_port_mid
140 * Destination local port for unicast packets.
141 * Destination multicast ID for multicast packets.
142 *
143 * Control packets are directed to a specific egress port, while data
144 * packets are transmitted through the CPU port (0) into the switch partition,
145 * where forwarding rules are applied.
146 */
147MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
148
149/* tx_hdr_fid
150 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
151 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
152 * Valid for data packets only.
153 */
154MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
155
156/* tx_hdr_type
157 * 0 - Data packets
158 * 6 - Control packets
159 */
160MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161
e5e5c88a
YG		 162struct mlxsw_sp_mlxfw_dev {
163 struct mlxfw_dev mlxfw_dev;
164 struct mlxsw_sp *mlxsw_sp;
165};
166
167static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
168 u16 component_index, u32 *p_max_size,
169 u8 *p_align_bits, u16 *p_max_write_size)
170{
171 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
172 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
174 char mcqi_pl[MLXSW_REG_MCQI_LEN];
175 int err;
176
177 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
178 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
179 if (err)
180 return err;
181 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
182 p_max_write_size);
183
184 *p_align_bits = max_t(u8, *p_align_bits, 2);
185 *p_max_write_size = min_t(u16, *p_max_write_size,
186 MLXSW_REG_MCDA_MAX_DATA_LEN);
187 return 0;
188}
189
190static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
191{
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
196 u8 control_state;
197 int err;
198
199 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
200 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
201 if (err)
202 return err;
203
204 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
205 if (control_state != MLXFW_FSM_STATE_IDLE)
206 return -EBUSY;
207
208 mlxsw_reg_mcc_pack(mcc_pl,
209 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
210 0, *fwhandle, 0);
211 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
212}
213
214static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
215 u32 fwhandle, u16 component_index,
216 u32 component_size)
217{
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
222
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
224 component_index, fwhandle, component_size);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226}
227
228static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
229 u32 fwhandle, u8 *data, u16 size,
230 u32 offset)
231{
232 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
233 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
234 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
235 char mcda_pl[MLXSW_REG_MCDA_LEN];
236
237 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
238 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
239}
240
241static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
242 u32 fwhandle, u16 component_index)
243{
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
248
249 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
250 component_index, fwhandle, 0);
251 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
252}
253
254static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
255{
256 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
257 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
258 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
259 char mcc_pl[MLXSW_REG_MCC_LEN];
260
261 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
262 fwhandle, 0);
263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
264}
265
266static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
267 enum mlxfw_fsm_state *fsm_state,
268 enum mlxfw_fsm_state_err *fsm_state_err)
269{
270 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
271 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
272 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
273 char mcc_pl[MLXSW_REG_MCC_LEN];
274 u8 control_state;
275 u8 error_code;
276 int err;
277
278 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
279 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
280 if (err)
281 return err;
282
283 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
284 *fsm_state = control_state;
285 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
286 MLXFW_FSM_STATE_ERR_MAX);
287 return 0;
288}
289
290static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
291{
292 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
293 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
294 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
295 char mcc_pl[MLXSW_REG_MCC_LEN];
296
297 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
298 fwhandle, 0);
299 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
300}
301
302static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
303{
304 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
305 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
307 char mcc_pl[MLXSW_REG_MCC_LEN];
308
309 mlxsw_reg_mcc_pack(mcc_pl,
310 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
311 fwhandle, 0);
312 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
313}
314
315static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
316 .component_query = mlxsw_sp_component_query,
317 .fsm_lock = mlxsw_sp_fsm_lock,
318 .fsm_component_update = mlxsw_sp_fsm_component_update,
319 .fsm_block_download = mlxsw_sp_fsm_block_download,
320 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
321 .fsm_activate = mlxsw_sp_fsm_activate,
322 .fsm_query_state = mlxsw_sp_fsm_query_state,
323 .fsm_cancel = mlxsw_sp_fsm_cancel,
324 .fsm_release = mlxsw_sp_fsm_release
325};
326
ce6ef68f
YG		 327static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
328 const struct firmware *firmware)
329{
330 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
331 .mlxfw_dev = {
332 .ops = &mlxsw_sp_mlxfw_dev_ops,
333 .psid = mlxsw_sp->bus_info->psid,
334 .psid_size = strlen(mlxsw_sp->bus_info->psid),
335 },
336 .mlxsw_sp = mlxsw_sp
337 };
338
339 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
340}
341
6b742199
YG		 342static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
343 const struct mlxsw_fw_rev *b)
344{
345 if (a->major != b->major)
346 return a->major > b->major;
347 if (a->minor != b->minor)
348 return a->minor > b->minor;
349 return a->subminor >= b->subminor;
350}
351
352static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
353{
354 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
6b742199
YG		 355 const struct firmware *firmware;
356 int err;
357
358 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
359 return 0;
360
361 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
362 rev->major, rev->minor, rev->subminor);
363 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
364 MLXSW_SP_FW_FILENAME);
365
366 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
367 mlxsw_sp->bus_info->dev);
368 if (err) {
369 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
370 MLXSW_SP_FW_FILENAME);
371 return err;
372 }
373
ce6ef68f 374 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
6b742199
YG		 375 release_firmware(firmware);
376 return err;
377}
378
1abcbcc2
AS		 379int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
380 unsigned int counter_index, u64 *packets,
381 u64 *bytes)
382{
383 char mgpc_pl[MLXSW_REG_MGPC_LEN];
384 int err;
385
386 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
6bba7e20 387 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 388 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
389 if (err)
390 return err;
7cfcbc75
AS		 391 if (packets)
392 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
393 if (bytes)
394 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
1abcbcc2
AS		 395 return 0;
396}
397
398static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
399 unsigned int counter_index)
400{
401 char mgpc_pl[MLXSW_REG_MGPC_LEN];
402
403 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
6bba7e20 404 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 405 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
406}
407
408int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
409 unsigned int *p_counter_index)
410{
411 int err;
412
413 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
414 p_counter_index);
415 if (err)
416 return err;
417 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
418 if (err)
419 goto err_counter_clear;
420 return 0;
421
422err_counter_clear:
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 *p_counter_index);
425 return err;
426}
427
428void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
429 unsigned int counter_index)
430{
431 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
432 counter_index);
433}
434
56ade8fe
JP		 435static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
436 const struct mlxsw_tx_info *tx_info)
437{
438 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
439
440 memset(txhdr, 0, MLXSW_TXHDR_LEN);
441
442 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
443 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
444 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
445 mlxsw_tx_hdr_swid_set(txhdr, 0);
446 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
447 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
448 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
449}
450
fe9ccc78
IS		 451int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
452 u8 state)
453{
454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
455 enum mlxsw_reg_spms_state spms_state;
456 char *spms_pl;
457 int err;
458
459 switch (state) {
460 case BR_STATE_FORWARDING:
461 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
462 break;
463 case BR_STATE_LEARNING:
464 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
465 break;
466 case BR_STATE_LISTENING: /* fall-through */
467 case BR_STATE_DISABLED: /* fall-through */
468 case BR_STATE_BLOCKING:
469 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
470 break;
471 default:
472 BUG();
473 }
474
475 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
476 if (!spms_pl)
477 return -ENOMEM;
478 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
479 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
480
481 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
482 kfree(spms_pl);
483 return err;
484}
485
56ade8fe
JP		 486static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
487{
5b090740 488 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
56ade8fe
JP		 489 int err;
490
491 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
492 if (err)
493 return err;
494 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
495 return 0;
496}
497
763b4b70
YG		 498static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
499{
763b4b70
YG		 500 int i;
501
c1a38311 502 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 503 return -EIO;
504
c1a38311
JP		 505 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
506 MAX_SPAN);
763b4b70
YG		 507 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
508 sizeof(struct mlxsw_sp_span_entry),
509 GFP_KERNEL);
510 if (!mlxsw_sp->span.entries)
511 return -ENOMEM;
512
513 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
514 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
515
516 return 0;
517}
518
519static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
520{
521 int i;
522
523 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
524 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
525
526 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
527 }
528 kfree(mlxsw_sp->span.entries);
529}
530
531static struct mlxsw_sp_span_entry *
532mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
533{
534 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
535 struct mlxsw_sp_span_entry *span_entry;
536 char mpat_pl[MLXSW_REG_MPAT_LEN];
537 u8 local_port = port->local_port;
538 int index;
539 int i;
540 int err;
541
542 /* find a free entry to use */
543 index = -1;
544 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
545 if (!mlxsw_sp->span.entries[i].used) {
546 index = i;
547 span_entry = &mlxsw_sp->span.entries[i];
548 break;
549 }
550 }
551 if (index < 0)
552 return NULL;
553
554 /* create a new port analayzer entry for local_port */
555 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
556 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
557 if (err)
558 return NULL;
559
560 span_entry->used = true;
561 span_entry->id = index;
2d644d4c 562 span_entry->ref_count = 1;
763b4b70
YG		 563 span_entry->local_port = local_port;
564 return span_entry;
565}
566
567static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
568 struct mlxsw_sp_span_entry *span_entry)
569{
570 u8 local_port = span_entry->local_port;
571 char mpat_pl[MLXSW_REG_MPAT_LEN];
572 int pa_id = span_entry->id;
573
574 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
575 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
576 span_entry->used = false;
577}
578
1a9234e6 579static struct mlxsw_sp_span_entry *
6399ebcc 580mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
763b4b70 581{
763b4b70
YG		 582 int i;
583
584 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
585 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
586
6399ebcc 587 if (curr->used && curr->local_port == local_port)
763b4b70
YG		 588 return curr;
589 }
590 return NULL;
591}
592
1a9234e6
IS		 593static struct mlxsw_sp_span_entry
594*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 595{
596 struct mlxsw_sp_span_entry *span_entry;
597
6399ebcc
YM		 598 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
599 port->local_port);
763b4b70 600 if (span_entry) {
2d644d4c 601 /* Already exists, just take a reference */
763b4b70
YG		 602 span_entry->ref_count++;
603 return span_entry;
604 }
605
606 return mlxsw_sp_span_entry_create(port);
607}
608
609static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
610 struct mlxsw_sp_span_entry *span_entry)
611{
2d644d4c 612 WARN_ON(!span_entry->ref_count);
763b4b70
YG		 613 if (--span_entry->ref_count == 0)
614 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
615 return 0;
616}
617
618static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
619{
620 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
621 struct mlxsw_sp_span_inspected_port *p;
622 int i;
623
624 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
625 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
626
627 list_for_each_entry(p, &curr->bound_ports_list, list)
628 if (p->local_port == port->local_port &&
629 p->type == MLXSW_SP_SPAN_EGRESS)
630 return true;
631 }
632
633 return false;
634}
635
18281f2d
IS		 636static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
637 int mtu)
763b4b70 638{
18281f2d 639 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
763b4b70
YG		 640}
641
642static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
643{
644 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
645 char sbib_pl[MLXSW_REG_SBIB_LEN];
646 int err;
647
648 /* If port is egress mirrored, the shared buffer size should be
649 * updated according to the mtu value
650 */
651 if (mlxsw_sp_span_is_egress_mirror(port)) {
18281f2d
IS		 652 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
653
654 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 655 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
656 if (err) {
657 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
658 return err;
659 }
660 }
661
662 return 0;
663}
664
665static struct mlxsw_sp_span_inspected_port *
666mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry)
668{
669 struct mlxsw_sp_span_inspected_port *p;
670
671 list_for_each_entry(p, &span_entry->bound_ports_list, list)
672 if (port->local_port == p->local_port)
673 return p;
674 return NULL;
675}
676
677static int
678mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
679 struct mlxsw_sp_span_entry *span_entry,
680 enum mlxsw_sp_span_type type)
681{
682 struct mlxsw_sp_span_inspected_port *inspected_port;
683 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
684 char mpar_pl[MLXSW_REG_MPAR_LEN];
685 char sbib_pl[MLXSW_REG_SBIB_LEN];
686 int pa_id = span_entry->id;
687 int err;
688
689 /* if it is an egress SPAN, bind a shared buffer to it */
690 if (type == MLXSW_SP_SPAN_EGRESS) {
18281f2d
IS		 691 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
692 port->dev->mtu);
693
694 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 695 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
696 if (err) {
697 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
698 return err;
699 }
700 }
701
702 /* bind the port to the SPAN entry */
1a9234e6
IS		 703 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
704 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
763b4b70
YG		 705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
706 if (err)
707 goto err_mpar_reg_write;
708
709 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
710 if (!inspected_port) {
711 err = -ENOMEM;
712 goto err_inspected_port_alloc;
713 }
714 inspected_port->local_port = port->local_port;
715 inspected_port->type = type;
716 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
717
718 return 0;
719
720err_mpar_reg_write:
721err_inspected_port_alloc:
722 if (type == MLXSW_SP_SPAN_EGRESS) {
723 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
724 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
725 }
726 return err;
727}
728
729static void
730mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
731 struct mlxsw_sp_span_entry *span_entry,
732 enum mlxsw_sp_span_type type)
733{
734 struct mlxsw_sp_span_inspected_port *inspected_port;
735 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
736 char mpar_pl[MLXSW_REG_MPAR_LEN];
737 char sbib_pl[MLXSW_REG_SBIB_LEN];
738 int pa_id = span_entry->id;
739
740 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
741 if (!inspected_port)
742 return;
743
744 /* remove the inspected port */
1a9234e6
IS		 745 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
746 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
763b4b70
YG		 747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
748
749 /* remove the SBIB buffer if it was egress SPAN */
750 if (type == MLXSW_SP_SPAN_EGRESS) {
751 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
752 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
753 }
754
755 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
756
757 list_del(&inspected_port->list);
758 kfree(inspected_port);
759}
760
761static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
762 struct mlxsw_sp_port *to,
763 enum mlxsw_sp_span_type type)
764{
765 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
766 struct mlxsw_sp_span_entry *span_entry;
767 int err;
768
769 span_entry = mlxsw_sp_span_entry_get(to);
770 if (!span_entry)
771 return -ENOENT;
772
773 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
774 span_entry->id);
775
776 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
777 if (err)
778 goto err_port_bind;
779
780 return 0;
781
782err_port_bind:
783 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
784 return err;
785}
786
787static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
6399ebcc 788 u8 destination_port,
763b4b70
YG		 789 enum mlxsw_sp_span_type type)
790{
791 struct mlxsw_sp_span_entry *span_entry;
792
6399ebcc
YM		 793 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
794 destination_port);
763b4b70
YG		 795 if (!span_entry) {
796 netdev_err(from->dev, "no span entry found\n");
797 return;
798 }
799
800 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
801 span_entry->id);
802 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
803}
804
98d0f7b9
YG		 805static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
806 bool enable, u32 rate)
807{
808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
809 char mpsc_pl[MLXSW_REG_MPSC_LEN];
810
811 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
812 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
813}
814
56ade8fe
JP		 815static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
816 bool is_up)
817{
818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
819 char paos_pl[MLXSW_REG_PAOS_LEN];
820
821 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
822 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
823 MLXSW_PORT_ADMIN_STATUS_DOWN);
824 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
825}
826
56ade8fe
JP		 827static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
828 unsigned char *addr)
829{
830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
831 char ppad_pl[MLXSW_REG_PPAD_LEN];
832
833 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
834 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
835 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
836}
837
838static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
839{
840 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
841 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
842
843 ether_addr_copy(addr, mlxsw_sp->base_mac);
844 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
845 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
846}
847
56ade8fe
JP		 848static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
849{
850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
851 char pmtu_pl[MLXSW_REG_PMTU_LEN];
852 int max_mtu;
853 int err;
854
855 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
856 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
857 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
858 if (err)
859 return err;
860 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
861
862 if (mtu > max_mtu)
863 return -EINVAL;
864
865 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
867}
868
be94535f
IS		 869static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
870{
871 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5b153859 872 char pspa_pl[MLXSW_REG_PSPA_LEN];
be94535f 873
5b153859
IS		 874 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
875 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
be94535f
IS		 876}
877
a1107487 878int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
56ade8fe
JP		 879{
880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
881 char svpe_pl[MLXSW_REG_SVPE_LEN];
882
883 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
884 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
885}
886
7cbc4277
IS		 887int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
888 bool learn_enable)
56ade8fe
JP		 889{
890 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
891 char *spvmlr_pl;
892 int err;
893
894 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
895 if (!spvmlr_pl)
896 return -ENOMEM;
7cbc4277
IS		 897 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
898 learn_enable);
56ade8fe
JP		 899 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
900 kfree(spvmlr_pl);
901 return err;
902}
903
b02eae9b
IS		 904static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
905 u16 vid)
906{
907 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
908 char spvid_pl[MLXSW_REG_SPVID_LEN];
909
910 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
912}
913
914static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
915 bool allow)
916{
917 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
918 char spaft_pl[MLXSW_REG_SPAFT_LEN];
919
920 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
922}
923
924int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
925{
926 int err;
927
928 if (!vid) {
929 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
930 if (err)
931 return err;
932 } else {
933 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
934 if (err)
935 return err;
936 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
937 if (err)
938 goto err_port_allow_untagged_set;
939 }
940
941 mlxsw_sp_port->pvid = vid;
942 return 0;
943
944err_port_allow_untagged_set:
945 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
946 return err;
947}
948
56ade8fe
JP		 949static int
950mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
951{
952 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
953 char sspr_pl[MLXSW_REG_SSPR_LEN];
954
955 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
956 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
957}
958
d664b41e
IS		 959static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
960 u8 local_port, u8 *p_module,
961 u8 *p_width, u8 *p_lane)
56ade8fe 962{
56ade8fe
JP		 963 char pmlp_pl[MLXSW_REG_PMLP_LEN];
964 int err;
965
558c2d5e 966 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 967 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
968 if (err)
969 return err;
558c2d5e
IS		 970 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
971 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 972 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 973 return 0;
974}
975
2e915e0b 976static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
18f1e70c
IS		 977 u8 module, u8 width, u8 lane)
978{
2e915e0b 979 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
18f1e70c
IS		 980 char pmlp_pl[MLXSW_REG_PMLP_LEN];
981 int i;
982
2e915e0b 983 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
18f1e70c
IS		 984 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
985 for (i = 0; i < width; i++) {
986 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
987 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
988 }
989
990 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
991}
992
2e915e0b 993static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
3e9b27b8 994{
2e915e0b 995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3e9b27b8
IS		 996 char pmlp_pl[MLXSW_REG_PMLP_LEN];
997
2e915e0b 998 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
3e9b27b8
IS		 999 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1001}
1002
56ade8fe
JP		 1003static int mlxsw_sp_port_open(struct net_device *dev)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 int err;
1007
1008 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1009 if (err)
1010 return err;
1011 netif_start_queue(dev);
1012 return 0;
1013}
1014
1015static int mlxsw_sp_port_stop(struct net_device *dev)
1016{
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018
1019 netif_stop_queue(dev);
1020 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1021}
1022
1023static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1024 struct net_device *dev)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1028 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1029 const struct mlxsw_tx_info tx_info = {
1030 .local_port = mlxsw_sp_port->local_port,
1031 .is_emad = false,
1032 };
1033 u64 len;
1034 int err;
1035
307c2431 1036 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 1037 return NETDEV_TX_BUSY;
1038
1039 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1040 struct sk_buff *skb_orig = skb;
1041
1042 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1043 if (!skb) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 dev_kfree_skb_any(skb_orig);
1046 return NETDEV_TX_OK;
1047 }
36bf38d1 1048 dev_consume_skb_any(skb_orig);
56ade8fe
JP		 1049 }
1050
1051 if (eth_skb_pad(skb)) {
1052 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1053 return NETDEV_TX_OK;
1054 }
1055
1056 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 1057 /* TX header is consumed by HW on the way so we shouldn't count its
1058 * bytes as being sent.
1059 */
1060 len = skb->len - MLXSW_TXHDR_LEN;
1061
56ade8fe
JP		 1062 /* Due to a race we might fail here because of a full queue. In that
1063 * unlikely case we simply drop the packet.
1064 */
307c2431 1065 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 1066
1067 if (!err) {
1068 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1069 u64_stats_update_begin(&pcpu_stats->syncp);
1070 pcpu_stats->tx_packets++;
1071 pcpu_stats->tx_bytes += len;
1072 u64_stats_update_end(&pcpu_stats->syncp);
1073 } else {
1074 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1075 dev_kfree_skb_any(skb);
1076 }
1077 return NETDEV_TX_OK;
1078}
1079
c5b9b518
JP		 1080static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1081{
1082}
1083
56ade8fe
JP		 1084static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1085{
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087 struct sockaddr *addr = p;
1088 int err;
1089
1090 if (!is_valid_ether_addr(addr->sa_data))
1091 return -EADDRNOTAVAIL;
1092
1093 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1094 if (err)
1095 return err;
1096 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1097 return 0;
1098}
1099
18281f2d
IS		 1100static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1101 int mtu)
ff6551ec 1102{
18281f2d 1103 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
f417f04d 1104}
8e8dfe9f 1105
f417f04d 1106#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
18281f2d
IS		 1107
1108static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1109 u16 delay)
f417f04d 1110{
18281f2d
IS		 1111 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1112 BITS_PER_BYTE));
1113 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1114 mtu);
f417f04d
IS		 1115}
1116
18281f2d 1117/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
f417f04d
IS		 1118 * Assumes 100m cable and maximum MTU.
1119 */
18281f2d
IS		 1120#define MLXSW_SP_PAUSE_DELAY 58752
1121
1122static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1123 u16 delay, bool pfc, bool pause)
f417f04d
IS		 1124{
1125 if (pfc)
18281f2d 1126 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
f417f04d 1127 else if (pause)
18281f2d 1128 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
f417f04d
IS		 1129 else
1130 return 0;
1131}
9f7ec052 1132
f417f04d
IS		 1133static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1134 bool lossy)
1135{
1136 if (lossy)
1137 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
d81a6bdb 1138 else
f417f04d
IS		 1139 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1140 thres);
8e8dfe9f
IS		 1141}
1142
1143int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 1144 u8 *prio_tc, bool pause_en,
1145 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 1146{
1147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 1148 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1149 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 1150 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 1151 int i, j, err;
ff6551ec
IS		 1152
1153 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1154 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1155 if (err)
1156 return err;
8e8dfe9f
IS		 1157
1158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1159 bool configure = false;
d81a6bdb 1160 bool pfc = false;
f417f04d
IS		 1161 bool lossy;
1162 u16 thres;
8e8dfe9f
IS		 1163
1164 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1165 if (prio_tc[j] == i) {
d81a6bdb 1166 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 1167 configure = true;
1168 break;
1169 }
1170 }
1171
1172 if (!configure)
1173 continue;
f417f04d
IS		 1174
1175 lossy = !(pfc || pause_en);
18281f2d
IS		 1176 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1177 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1178 pause_en);
f417f04d 1179 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
8e8dfe9f
IS		 1180 }
1181
ff6551ec
IS		 1182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1183}
1184
8e8dfe9f 1185static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 1186 int mtu, bool pause_en)
8e8dfe9f
IS		 1187{
1188 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1189 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 1190 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 1191 u8 *prio_tc;
1192
1193 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 1194 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 1195
9f7ec052 1196 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 1197 pause_en, my_pfc);
8e8dfe9f
IS		 1198}
1199
56ade8fe
JP		 1200static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 1203 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 1204 int err;
1205
9f7ec052 1206 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 1207 if (err)
1208 return err;
763b4b70
YG		 1209 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1210 if (err)
1211 goto err_span_port_mtu_update;
ff6551ec
IS		 1212 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1213 if (err)
1214 goto err_port_mtu_set;
56ade8fe
JP		 1215 dev->mtu = mtu;
1216 return 0;
ff6551ec
IS		 1217
1218err_port_mtu_set:
763b4b70
YG		 1219 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1220err_span_port_mtu_update:
9f7ec052 1221 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 1222 return err;
56ade8fe
JP		 1223}
1224
4bdcc6ca 1225static int
fc1bbb0f
NF		 1226mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1227 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 1228{
1229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1230 struct mlxsw_sp_port_pcpu_stats *p;
1231 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1232 u32 tx_dropped = 0;
1233 unsigned int start;
1234 int i;
1235
1236 for_each_possible_cpu(i) {
1237 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1238 do {
1239 start = u64_stats_fetch_begin_irq(&p->syncp);
1240 rx_packets = p->rx_packets;
1241 rx_bytes = p->rx_bytes;
1242 tx_packets = p->tx_packets;
1243 tx_bytes = p->tx_bytes;
1244 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1245
1246 stats->rx_packets += rx_packets;
1247 stats->rx_bytes += rx_bytes;
1248 stats->tx_packets += tx_packets;
1249 stats->tx_bytes += tx_bytes;
1250 /* tx_dropped is u32, updated without syncp protection. */
1251 tx_dropped += p->tx_dropped;
1252 }
1253 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 1254 return 0;
1255}
1256
3df5b3c6 1257static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
fc1bbb0f
NF		 1258{
1259 switch (attr_id) {
1260 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
4bdcc6ca
OG		 1267static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1268 void *sp)
fc1bbb0f
NF		 1269{
1270 switch (attr_id) {
1271 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1272 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1273 }
1274
1275 return -EINVAL;
1276}
1277
1278static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1279 int prio, char *ppcnt_pl)
1280{
1281 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1283
1284 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1285 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1286}
1287
1288static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1289 struct rtnl_link_stats64 *stats)
1290{
1291 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1292 int err;
1293
1294 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1295 0, ppcnt_pl);
1296 if (err)
1297 goto out;
1298
1299 stats->tx_packets =
1300 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1301 stats->rx_packets =
1302 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1303 stats->tx_bytes =
1304 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_bytes =
1306 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1307 stats->multicast =
1308 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1309
1310 stats->rx_crc_errors =
1311 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1312 stats->rx_frame_errors =
1313 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1314
1315 stats->rx_length_errors = (
1316 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1318 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1319
1320 stats->rx_errors = (stats->rx_crc_errors +
1321 stats->rx_frame_errors + stats->rx_length_errors);
1322
1323out:
1324 return err;
1325}
1326
075ab8ad
NF		 1327static void
1328mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1329 struct mlxsw_sp_port_xstats *xstats)
1330{
1331 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1332 int err, i;
1333
1334 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1335 ppcnt_pl);
1336 if (!err)
1337 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1338
1339 for (i = 0; i < TC_MAX_QUEUE; i++) {
1340 err = mlxsw_sp_port_get_stats_raw(dev,
1341 MLXSW_REG_PPCNT_TC_CONG_TC,
1342 i, ppcnt_pl);
1343 if (!err)
1344 xstats->wred_drop[i] =
1345 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1346
1347 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1348 i, ppcnt_pl);
1349 if (err)
1350 continue;
1351
1352 xstats->backlog[i] =
1353 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1354 xstats->tail_drop[i] =
1355 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1356 }
1357}
1358
fc1bbb0f
NF		 1359static void update_stats_cache(struct work_struct *work)
1360{
1361 struct mlxsw_sp_port *mlxsw_sp_port =
1362 container_of(work, struct mlxsw_sp_port,
9deef43d 1363 periodic_hw_stats.update_dw.work);
fc1bbb0f
NF		 1364
1365 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1366 goto out;
1367
1368 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
9deef43d 1369 &mlxsw_sp_port->periodic_hw_stats.stats);
075ab8ad
NF		 1370 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1371 &mlxsw_sp_port->periodic_hw_stats.xstats);
fc1bbb0f
NF		 1372
1373out:
9deef43d 1374 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 1375 MLXSW_HW_STATS_UPDATE_TIME);
1376}
1377
1378/* Return the stats from a cache that is updated periodically,
1379 * as this function might get called in an atomic context.
1380 */
bc1f4470 1381static void
fc1bbb0f
NF		 1382mlxsw_sp_port_get_stats64(struct net_device *dev,
1383 struct rtnl_link_stats64 *stats)
1384{
1385 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1386
9deef43d 1387 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
56ade8fe
JP		 1388}
1389
93cd0813
JP		 1390static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1391 u16 vid_begin, u16 vid_end,
1392 bool is_member, bool untagged)
56ade8fe
JP		 1393{
1394 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1395 char *spvm_pl;
1396 int err;
1397
1398 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1399 if (!spvm_pl)
1400 return -ENOMEM;
1401
1402 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1403 vid_end, is_member, untagged);
1404 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1405 kfree(spvm_pl);
1406 return err;
1407}
1408
93cd0813
JP		 1409int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1410 u16 vid_end, bool is_member, bool untagged)
1411{
1412 u16 vid, vid_e;
1413 int err;
1414
1415 for (vid = vid_begin; vid <= vid_end;
1416 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1417 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1418 vid_end);
1419
1420 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1421 is_member, untagged);
1422 if (err)
1423 return err;
1424 }
1425
1426 return 0;
1427}
1428
c57529e1 1429static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
7f71eb46 1430{
c57529e1 1431 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
7f71eb46 1432
c57529e1
IS		 1433 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1434 &mlxsw_sp_port->vlans_list, list)
1435 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
7f71eb46
IS		 1436}
1437
31a08a52
IS		 1438static struct mlxsw_sp_port_vlan *
1439mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1440{
1441 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
c57529e1
IS		 1442 bool untagged = vid == 1;
1443 int err;
1444
1445 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1446 if (err)
1447 return ERR_PTR(err);
31a08a52
IS		 1448
1449 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
c57529e1
IS		 1450 if (!mlxsw_sp_port_vlan) {
1451 err = -ENOMEM;
1452 goto err_port_vlan_alloc;
1453 }
31a08a52
IS		 1454
1455 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1456 mlxsw_sp_port_vlan->vid = vid;
1457 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1458
1459 return mlxsw_sp_port_vlan;
c57529e1
IS		 1460
1461err_port_vlan_alloc:
1462 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1463 return ERR_PTR(err);
31a08a52
IS		 1464}
1465
1466static void
1467mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1468{
c57529e1
IS		 1469 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1470 u16 vid = mlxsw_sp_port_vlan->vid;
7cbecf24 1471
31a08a52
IS		 1472 list_del(&mlxsw_sp_port_vlan->list);
1473 kfree(mlxsw_sp_port_vlan);
c57529e1
IS		 1474 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1475}
1476
1477struct mlxsw_sp_port_vlan *
1478mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1479{
1480 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1481
1482 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1483 if (mlxsw_sp_port_vlan)
1484 return mlxsw_sp_port_vlan;
1485
1486 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1487}
1488
1489void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1490{
a1107487
IS		 1491 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1492
c57529e1
IS		 1493 if (mlxsw_sp_port_vlan->bridge_port)
1494 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
a1107487
IS		 1495 else if (fid)
1496 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
c57529e1
IS		 1497
1498 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
31a08a52
IS		 1499}
1500
05978481
IS		 1501static int mlxsw_sp_port_add_vid(struct net_device *dev,
1502 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1503{
1504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
56ade8fe
JP		 1505
1506 /* VLAN 0 is added to HW filter when device goes up, but it is
1507 * reserved in our case, so simply return.
1508 */
1509 if (!vid)
1510 return 0;
1511
c57529e1 1512 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
56ade8fe
JP		 1513}
1514
32d863fb
IS		 1515static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1516 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1517{
1518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
31a08a52 1519 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 1520
1521 /* VLAN 0 is removed from HW filter when device goes down, but
1522 * it is reserved in our case, so simply return.
1523 */
1524 if (!vid)
1525 return 0;
1526
31a08a52 1527 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
c57529e1 1528 if (!mlxsw_sp_port_vlan)
56ade8fe 1529 return 0;
c57529e1 1530 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
31a08a52 1531
56ade8fe
JP		 1532 return 0;
1533}
1534
2bf9a586
IS		 1535static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1536 size_t len)
1537{
1538 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1539 u8 module = mlxsw_sp_port->mapping.module;
1540 u8 width = mlxsw_sp_port->mapping.width;
1541 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1542 int err;
1543
2bf9a586
IS		 1544 if (!mlxsw_sp_port->split)
1545 err = snprintf(name, len, "p%d", module + 1);
1546 else
1547 err = snprintf(name, len, "p%ds%d", module + 1,
1548 lane / width);
1549
1550 if (err >= len)
1551 return -EINVAL;
1552
1553 return 0;
1554}
1555
763b4b70 1556static struct mlxsw_sp_port_mall_tc_entry *
65acb5d0
YG		 1557mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1558 unsigned long cookie) {
763b4b70
YG		 1559 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1560
1561 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1562 if (mall_tc_entry->cookie == cookie)
1563 return mall_tc_entry;
1564
1565 return NULL;
1566}
1567
1568static int
1569mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
65acb5d0 1570 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
763b4b70
YG		 1571 const struct tc_action *a,
1572 bool ingress)
1573{
763b4b70
YG		 1574 enum mlxsw_sp_span_type span_type;
1575 struct mlxsw_sp_port *to_port;
1576 struct net_device *to_dev;
763b4b70 1577
9f8a739e 1578 to_dev = tcf_mirred_dev(a);
763b4b70
YG		 1579 if (!to_dev) {
1580 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1581 return -EINVAL;
1582 }
1583
1584 if (!mlxsw_sp_port_dev_check(to_dev)) {
1585 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
e915ac68 1586 return -EOPNOTSUPP;
763b4b70
YG		 1587 }
1588 to_port = netdev_priv(to_dev);
1589
65acb5d0
YG		 1590 mirror->to_local_port = to_port->local_port;
1591 mirror->ingress = ingress;
763b4b70 1592 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
65acb5d0
YG		 1593 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1594}
763b4b70 1595
65acb5d0
YG		 1596static void
1597mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1598 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1599{
65acb5d0 1600 enum mlxsw_sp_span_type span_type;
65acb5d0 1601
65acb5d0
YG		 1602 span_type = mirror->ingress ?
1603 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
6399ebcc
YM		 1604 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1605 span_type);
763b4b70
YG		 1606}
1607
98d0f7b9
YG		 1608static int
1609mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1610 struct tc_cls_matchall_offload *cls,
1611 const struct tc_action *a,
1612 bool ingress)
1613{
1614 int err;
1615
1616 if (!mlxsw_sp_port->sample)
1617 return -EOPNOTSUPP;
1618 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1619 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1620 return -EEXIST;
1621 }
1622 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1623 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1624 return -EOPNOTSUPP;
1625 }
1626
1627 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1628 tcf_sample_psample_group(a));
1629 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1630 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1631 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1632
1633 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1634 if (err)
1635 goto err_port_sample_set;
1636 return 0;
1637
1638err_port_sample_set:
1639 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1640 return err;
1641}
1642
1643static void
1644mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1645{
1646 if (!mlxsw_sp_port->sample)
1647 return;
1648
1649 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1650 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1651}
1652
763b4b70 1653static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1654 struct tc_cls_matchall_offload *f,
763b4b70
YG		 1655 bool ingress)
1656{
65acb5d0 1657 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
5fd9fc4e 1658 __be16 protocol = f->common.protocol;
763b4b70 1659 const struct tc_action *a;
22dc13c8 1660 LIST_HEAD(actions);
763b4b70
YG		 1661 int err;
1662
9cbf14ed 1663 if (!tcf_exts_has_one_action(f->exts)) {
763b4b70 1664 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
e915ac68 1665 return -EOPNOTSUPP;
763b4b70
YG		 1666 }
1667
65acb5d0
YG		 1668 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1669 if (!mall_tc_entry)
1670 return -ENOMEM;
9cbf14ed 1671 mall_tc_entry->cookie = f->cookie;
65acb5d0 1672
9cbf14ed 1673 tcf_exts_to_list(f->exts, &actions);
65acb5d0 1674 a = list_first_entry(&actions, struct tc_action, list);
86cb13e4 1675
65acb5d0
YG		 1676 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1677 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1678
1679 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1680 mirror = &mall_tc_entry->mirror;
1681 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1682 mirror, a, ingress);
98d0f7b9
YG		 1683 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1684 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
9cbf14ed 1685 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
98d0f7b9 1686 a, ingress);
65acb5d0
YG		 1687 } else {
1688 err = -EOPNOTSUPP;
763b4b70
YG		 1689 }
1690
65acb5d0
YG		 1691 if (err)
1692 goto err_add_action;
1693
1694 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
763b4b70 1695 return 0;
65acb5d0
YG		 1696
1697err_add_action:
1698 kfree(mall_tc_entry);
1699 return err;
763b4b70
YG		 1700}
1701
1702static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1703 struct tc_cls_matchall_offload *f)
763b4b70 1704{
763b4b70 1705 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
763b4b70 1706
65acb5d0 1707 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
9cbf14ed 1708 f->cookie);
763b4b70
YG		 1709 if (!mall_tc_entry) {
1710 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1711 return;
1712 }
65acb5d0 1713 list_del(&mall_tc_entry->list);
763b4b70
YG		 1714
1715 switch (mall_tc_entry->type) {
1716 case MLXSW_SP_PORT_MALL_MIRROR:
65acb5d0
YG		 1717 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1718 &mall_tc_entry->mirror);
763b4b70 1719 break;
98d0f7b9
YG		 1720 case MLXSW_SP_PORT_MALL_SAMPLE:
1721 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1722 break;
763b4b70
YG		 1723 default:
1724 WARN_ON(1);
1725 }
1726
763b4b70
YG		 1727 kfree(mall_tc_entry);
1728}
1729
fd33f1df 1730static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
eb49cfaa
JP		 1731 struct tc_cls_matchall_offload *f,
1732 bool ingress)
fd33f1df 1733{
5fd9fc4e 1734 if (f->common.chain_index)
fd33f1df
JP		 1735 return -EOPNOTSUPP;
1736
1737 switch (f->command) {
1738 case TC_CLSMATCHALL_REPLACE:
5fd9fc4e 1739 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
fd33f1df
JP		 1740 ingress);
1741 case TC_CLSMATCHALL_DESTROY:
1742 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1743 return 0;
1744 default:
1745 return -EOPNOTSUPP;
1746 }
1747}
1748
1749static int
1750mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
eb49cfaa
JP		 1751 struct tc_cls_flower_offload *f,
1752 bool ingress)
763b4b70 1753{
fd33f1df
JP		 1754 switch (f->command) {
1755 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 1756 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
fd33f1df
JP		 1757 case TC_CLSFLOWER_DESTROY:
1758 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
1759 return 0;
1760 case TC_CLSFLOWER_STATS:
1761 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
1762 default:
1763 return -EOPNOTSUPP;
1764 }
1765}
1766
eb49cfaa
JP		 1767static int mlxsw_sp_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1768 void *cb_priv, bool ingress)
1769{
1770 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1771
44ae12a7
JP		 1772 if (!tc_can_offload(mlxsw_sp_port->dev))
1773 return -EOPNOTSUPP;
1774
eb49cfaa
JP		 1775 switch (type) {
1776 case TC_SETUP_CLSMATCHALL:
1777 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1778 ingress);
1779 case TC_SETUP_CLSFLOWER:
1780 return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port, type_data,
1781 ingress);
1782 default:
1783 return -EOPNOTSUPP;
1784 }
1785}
1786
1787static int mlxsw_sp_setup_tc_block_cb_ig(enum tc_setup_type type,
1788 void *type_data, void *cb_priv)
1789{
1790 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, true);
1791}
1792
1793static int mlxsw_sp_setup_tc_block_cb_eg(enum tc_setup_type type,
1794 void *type_data, void *cb_priv)
1795{
1796 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, false);
1797}
1798
1799static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1800 struct tc_block_offload *f)
1801{
1802 tc_setup_cb_t *cb;
1803
1804 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
1805 cb = mlxsw_sp_setup_tc_block_cb_ig;
1806 else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS)
1807 cb = mlxsw_sp_setup_tc_block_cb_eg;
1808 else
1809 return -EOPNOTSUPP;
1810
1811 switch (f->command) {
1812 case TC_BLOCK_BIND:
1813 return tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1814 mlxsw_sp_port);
1815 case TC_BLOCK_UNBIND:
1816 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1817 return 0;
1818 default:
1819 return -EOPNOTSUPP;
1820 }
1821}
1822
fd33f1df 1823static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1824 void *type_data)
fd33f1df
JP		 1825{
1826 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1827
2572ac53 1828 switch (type) {
eb49cfaa
JP		 1829 case TC_SETUP_BLOCK:
1830 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
96f17e07
NF		 1831 case TC_SETUP_QDISC_RED:
1832 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
2572ac53
JP		 1833 default:
1834 return -EOPNOTSUPP;
763b4b70 1835 }
763b4b70
YG		 1836}
1837
56ade8fe
JP		 1838static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1839 .ndo_open = mlxsw_sp_port_open,
1840 .ndo_stop = mlxsw_sp_port_stop,
1841 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 1842 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 1843 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 1844 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1845 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1846 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 1847 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1848 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 1849 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1850 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
2bf9a586 1851 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
56ade8fe
JP		 1852};
1853
1854static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1855 struct ethtool_drvinfo *drvinfo)
1856{
1857 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1858 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1859
1860 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1861 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1862 sizeof(drvinfo->version));
1863 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1864 "%d.%d.%d",
1865 mlxsw_sp->bus_info->fw_rev.major,
1866 mlxsw_sp->bus_info->fw_rev.minor,
1867 mlxsw_sp->bus_info->fw_rev.subminor);
1868 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1869 sizeof(drvinfo->bus_info));
1870}
1871
9f7ec052
IS		 1872static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1873 struct ethtool_pauseparam *pause)
1874{
1875 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1876
1877 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1878 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1879}
1880
1881static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1882 struct ethtool_pauseparam *pause)
1883{
1884 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1885
1886 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1887 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1888 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1889
1890 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1891 pfcc_pl);
1892}
1893
1894static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1895 struct ethtool_pauseparam *pause)
1896{
1897 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1898 bool pause_en = pause->tx_pause || pause->rx_pause;
1899 int err;
1900
d81a6bdb
IS		 1901 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1902 netdev_err(dev, "PFC already enabled on port\n");
1903 return -EINVAL;
1904 }
1905
9f7ec052
IS		 1906 if (pause->autoneg) {
1907 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1908 return -EINVAL;
1909 }
1910
1911 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1912 if (err) {
1913 netdev_err(dev, "Failed to configure port's headroom\n");
1914 return err;
1915 }
1916
1917 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1918 if (err) {
1919 netdev_err(dev, "Failed to set PAUSE parameters\n");
1920 goto err_port_pause_configure;
1921 }
1922
1923 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1924 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1925
1926 return 0;
1927
1928err_port_pause_configure:
1929 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1930 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1931 return err;
1932}
1933
56ade8fe
JP		 1934struct mlxsw_sp_port_hw_stats {
1935 char str[ETH_GSTRING_LEN];
412791df 1936 u64 (*getter)(const char *payload);
18281f2d 1937 bool cells_bytes;
56ade8fe
JP		 1938};
1939
7ed674bc 1940static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 1941 {
1942 .str = "a_frames_transmitted_ok",
1943 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1944 },
1945 {
1946 .str = "a_frames_received_ok",
1947 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1948 },
1949 {
1950 .str = "a_frame_check_sequence_errors",
1951 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1952 },
1953 {
1954 .str = "a_alignment_errors",
1955 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1956 },
1957 {
1958 .str = "a_octets_transmitted_ok",
1959 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1960 },
1961 {
1962 .str = "a_octets_received_ok",
1963 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1964 },
1965 {
1966 .str = "a_multicast_frames_xmitted_ok",
1967 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1968 },
1969 {
1970 .str = "a_broadcast_frames_xmitted_ok",
1971 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1972 },
1973 {
1974 .str = "a_multicast_frames_received_ok",
1975 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1976 },
1977 {
1978 .str = "a_broadcast_frames_received_ok",
1979 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1980 },
1981 {
1982 .str = "a_in_range_length_errors",
1983 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1984 },
1985 {
1986 .str = "a_out_of_range_length_field",
1987 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1988 },
1989 {
1990 .str = "a_frame_too_long_errors",
1991 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1992 },
1993 {
1994 .str = "a_symbol_error_during_carrier",
1995 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1996 },
1997 {
1998 .str = "a_mac_control_frames_transmitted",
1999 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2000 },
2001 {
2002 .str = "a_mac_control_frames_received",
2003 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2004 },
2005 {
2006 .str = "a_unsupported_opcodes_received",
2007 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2008 },
2009 {
2010 .str = "a_pause_mac_ctrl_frames_received",
2011 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2012 },
2013 {
2014 .str = "a_pause_mac_ctrl_frames_xmitted",
2015 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2016 },
2017};
2018
2019#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2020
7ed674bc
IS		 2021static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2022 {
2023 .str = "rx_octets_prio",
2024 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2025 },
2026 {
2027 .str = "rx_frames_prio",
2028 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2029 },
2030 {
2031 .str = "tx_octets_prio",
2032 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2033 },
2034 {
2035 .str = "tx_frames_prio",
2036 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2037 },
2038 {
2039 .str = "rx_pause_prio",
2040 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2041 },
2042 {
2043 .str = "rx_pause_duration_prio",
2044 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2045 },
2046 {
2047 .str = "tx_pause_prio",
2048 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2049 },
2050 {
2051 .str = "tx_pause_duration_prio",
2052 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2053 },
2054};
2055
2056#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2057
df4750e8
IS		 2058static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2059 {
2060 .str = "tc_transmit_queue_tc",
18281f2d
IS		 2061 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2062 .cells_bytes = true,
df4750e8
IS		 2063 },
2064 {
2065 .str = "tc_no_buffer_discard_uc_tc",
2066 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2067 },
2068};
2069
2070#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2071
7ed674bc 2072#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 2073 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2074 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 2075 IEEE_8021QAZ_MAX_TCS)
2076
2077static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2078{
2079 int i;
2080
2081 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2082 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2083 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2084 *p += ETH_GSTRING_LEN;
2085 }
2086}
2087
df4750e8
IS		 2088static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2089{
2090 int i;
2091
2092 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2093 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2094 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2095 *p += ETH_GSTRING_LEN;
2096 }
2097}
2098
56ade8fe
JP		 2099static void mlxsw_sp_port_get_strings(struct net_device *dev,
2100 u32 stringset, u8 *data)
2101{
2102 u8 *p = data;
2103 int i;
2104
2105 switch (stringset) {
2106 case ETH_SS_STATS:
2107 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2108 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2109 ETH_GSTRING_LEN);
2110 p += ETH_GSTRING_LEN;
2111 }
7ed674bc
IS		 2112
2113 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2114 mlxsw_sp_port_get_prio_strings(&p, i);
2115
df4750e8
IS		 2116 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2117 mlxsw_sp_port_get_tc_strings(&p, i);
2118
56ade8fe
JP		 2119 break;
2120 }
2121}
2122
3a66ee38
IS		 2123static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2124 enum ethtool_phys_id_state state)
2125{
2126 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2127 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2128 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2129 bool active;
2130
2131 switch (state) {
2132 case ETHTOOL_ID_ACTIVE:
2133 active = true;
2134 break;
2135 case ETHTOOL_ID_INACTIVE:
2136 active = false;
2137 break;
2138 default:
2139 return -EOPNOTSUPP;
2140 }
2141
2142 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2143 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2144}
2145
7ed674bc
IS		 2146static int
2147mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2148 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2149{
2150 switch (grp) {
2151 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2152 *p_hw_stats = mlxsw_sp_port_hw_stats;
2153 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2154 break;
2155 case MLXSW_REG_PPCNT_PRIO_CNT:
2156 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2157 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2158 break;
df4750e8
IS		 2159 case MLXSW_REG_PPCNT_TC_CNT:
2160 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2161 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2162 break;
7ed674bc
IS		 2163 default:
2164 WARN_ON(1);
e915ac68 2165 return -EOPNOTSUPP;
7ed674bc
IS		 2166 }
2167 return 0;
2168}
2169
2170static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2171 enum mlxsw_reg_ppcnt_grp grp, int prio,
2172 u64 *data, int data_index)
56ade8fe 2173{
18281f2d
IS		 2174 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2175 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
7ed674bc 2176 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 2177 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 2178 int i, len;
56ade8fe
JP		 2179 int err;
2180
7ed674bc
IS		 2181 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2182 if (err)
2183 return;
fc1bbb0f 2184 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
18281f2d 2185 for (i = 0; i < len; i++) {
faac0ff0 2186 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
18281f2d
IS		 2187 if (!hw_stats[i].cells_bytes)
2188 continue;
2189 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2190 data[data_index + i]);
2191 }
7ed674bc
IS		 2192}
2193
2194static void mlxsw_sp_port_get_stats(struct net_device *dev,
2195 struct ethtool_stats *stats, u64 *data)
2196{
2197 int i, data_index = 0;
2198
2199 /* IEEE 802.3 Counters */
2200 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2201 data, data_index);
2202 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2203
2204 /* Per-Priority Counters */
2205 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2206 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2207 data, data_index);
2208 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2209 }
df4750e8
IS		 2210
2211 /* Per-TC Counters */
2212 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2213 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2214 data, data_index);
2215 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2216 }
56ade8fe
JP		 2217}
2218
2219static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2220{
2221 switch (sset) {
2222 case ETH_SS_STATS:
7ed674bc 2223 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 2224 default:
2225 return -EOPNOTSUPP;
2226 }
2227}
2228
2229struct mlxsw_sp_port_link_mode {
b9d66a36 2230 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 2231 u32 mask;
56ade8fe
JP		 2232 u32 speed;
2233};
2234
2235static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2236 {
2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 2238 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2239 .speed = SPEED_100,
56ade8fe
JP		 2240 },
2241 {
2242 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2243 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 2244 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2245 .speed = SPEED_1000,
56ade8fe
JP		 2246 },
2247 {
2248 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 2249 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2250 .speed = SPEED_10000,
56ade8fe
JP		 2251 },
2252 {
2253 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2254 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 2255 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2256 .speed = SPEED_10000,
56ade8fe
JP		 2257 },
2258 {
2259 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2260 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2261 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2262 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 2263 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2264 .speed = SPEED_10000,
56ade8fe
JP		 2265 },
2266 {
2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 2268 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2269 .speed = SPEED_20000,
56ade8fe
JP		 2270 },
2271 {
2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 2273 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2274 .speed = SPEED_40000,
56ade8fe
JP		 2275 },
2276 {
2277 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 2278 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2279 .speed = SPEED_40000,
56ade8fe
JP		 2280 },
2281 {
2282 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 2283 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2284 .speed = SPEED_40000,
56ade8fe
JP		 2285 },
2286 {
2287 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 2288 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2289 .speed = SPEED_40000,
2290 },
2291 {
2292 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2293 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2294 .speed = SPEED_25000,
2295 },
2296 {
2297 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2298 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2299 .speed = SPEED_25000,
2300 },
2301 {
2302 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2303 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2304 .speed = SPEED_25000,
56ade8fe
JP		 2305 },
2306 {
b9d66a36
IS		 2307 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2308 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2309 .speed = SPEED_25000,
56ade8fe
JP		 2310 },
2311 {
b9d66a36
IS		 2312 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2313 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2314 .speed = SPEED_50000,
2315 },
2316 {
2317 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2318 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2319 .speed = SPEED_50000,
2320 },
2321 {
2322 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2323 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2324 .speed = SPEED_50000,
56ade8fe
JP		 2325 },
2326 {
2327 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 2328 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2329 .speed = SPEED_56000,
56ade8fe
JP		 2330 },
2331 {
b9d66a36
IS		 2332 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2333 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2334 .speed = SPEED_56000,
2335 },
2336 {
2337 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2338 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2339 .speed = SPEED_56000,
2340 },
2341 {
2342 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2343 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2344 .speed = SPEED_56000,
2345 },
2346 {
2347 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2348 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2349 .speed = SPEED_100000,
2350 },
2351 {
2352 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2353 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2354 .speed = SPEED_100000,
2355 },
2356 {
2357 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2358 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2359 .speed = SPEED_100000,
2360 },
2361 {
2362 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2363 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2364 .speed = SPEED_100000,
56ade8fe
JP		 2365 },
2366};
2367
2368#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2369
b9d66a36
IS		 2370static void
2371mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2372 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2373{
2374 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2375 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2376 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2377 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2378 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2379 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 2380 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 2381
2382 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2383 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2384 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2385 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2386 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 2387 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 2388}
2389
b9d66a36 2390static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 2391{
56ade8fe
JP		 2392 int i;
2393
2394 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2395 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 2396 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2397 mode);
56ade8fe 2398 }
56ade8fe
JP		 2399}
2400
2401static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 2402 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2403{
2404 u32 speed = SPEED_UNKNOWN;
2405 u8 duplex = DUPLEX_UNKNOWN;
2406 int i;
2407
2408 if (!carrier_ok)
2409 goto out;
2410
2411 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2412 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2413 speed = mlxsw_sp_port_link_mode[i].speed;
2414 duplex = DUPLEX_FULL;
2415 break;
2416 }
2417 }
2418out:
b9d66a36
IS		 2419 cmd->base.speed = speed;
2420 cmd->base.duplex = duplex;
56ade8fe
JP		 2421}
2422
2423static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2424{
2425 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2426 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2427 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2428 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2429 return PORT_FIBRE;
2430
2431 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2432 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2433 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2434 return PORT_DA;
2435
2436 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2437 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2438 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2439 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2440 return PORT_NONE;
2441
2442 return PORT_OTHER;
2443}
2444
b9d66a36
IS		 2445static u32
2446mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2447{
2448 u32 ptys_proto = 0;
2449 int i;
2450
2451 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 2452 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2453 cmd->link_modes.advertising))
56ade8fe
JP		 2454 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2455 }
2456 return ptys_proto;
2457}
2458
2459static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2460{
2461 u32 ptys_proto = 0;
2462 int i;
2463
2464 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2465 if (speed == mlxsw_sp_port_link_mode[i].speed)
2466 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2467 }
2468 return ptys_proto;
2469}
2470
18f1e70c
IS		 2471static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2472{
2473 u32 ptys_proto = 0;
2474 int i;
2475
2476 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2477 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2478 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2479 }
2480 return ptys_proto;
2481}
2482
b9d66a36
IS		 2483static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2484 struct ethtool_link_ksettings *cmd)
2485{
2486 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2487 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2488 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2489
2490 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2491 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2492}
2493
2494static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2495 struct ethtool_link_ksettings *cmd)
56ade8fe 2496{
b9d66a36
IS		 2497 if (!autoneg)
2498 return;
2499
2500 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2501 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2502}
2503
2504static void
2505mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2506 struct ethtool_link_ksettings *cmd)
2507{
2508 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2509 return;
2510
2511 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2512 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2513}
2514
2515static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2516 struct ethtool_link_ksettings *cmd)
2517{
2518 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 2519 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2520 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2521 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2522 u8 autoneg_status;
0c83f88c 2523 bool autoneg;
56ade8fe
JP		 2524 int err;
2525
b9d66a36 2526 autoneg = mlxsw_sp_port->link.autoneg;
401c8b4e 2527 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
b9d66a36
IS		 2528 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2529 if (err)
2530 return err;
401c8b4e
ER		 2531 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2532 &eth_proto_oper);
b9d66a36
IS		 2533
2534 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2535
b9d66a36
IS		 2536 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2537
2538 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2539 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2540 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2541
2542 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2543 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2544 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2545 cmd);
2546
2547 return 0;
2548}
2549
2550static int
2551mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2552 const struct ethtool_link_ksettings *cmd)
2553{
2554 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2555 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2556 char ptys_pl[MLXSW_REG_PTYS_LEN];
2557 u32 eth_proto_cap, eth_proto_new;
2558 bool autoneg;
2559 int err;
56ade8fe 2560
401c8b4e 2561 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
56ade8fe 2562 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2563 if (err)
56ade8fe 2564 return err;
401c8b4e 2565 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
b9d66a36
IS		 2566
2567 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2568 eth_proto_new = autoneg ?
2569 mlxsw_sp_to_ptys_advert_link(cmd) :
2570 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2571
2572 eth_proto_new = eth_proto_new & eth_proto_cap;
2573 if (!eth_proto_new) {
b9d66a36 2574 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2575 return -EINVAL;
2576 }
56ade8fe 2577
401c8b4e
ER		 2578 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2579 eth_proto_new);
56ade8fe 2580 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2581 if (err)
56ade8fe 2582 return err;
56ade8fe 2583
6277d46b 2584 if (!netif_running(dev))
56ade8fe
JP		 2585 return 0;
2586
0c83f88c
IS		 2587 mlxsw_sp_port->link.autoneg = autoneg;
2588
b9d66a36
IS		 2589 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2590 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2591
2592 return 0;
2593}
2594
ce6ef68f
YG		 2595static int mlxsw_sp_flash_device(struct net_device *dev,
2596 struct ethtool_flash *flash)
2597{
2598 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2600 const struct firmware *firmware;
2601 int err;
2602
2603 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2604 return -EOPNOTSUPP;
2605
2606 dev_hold(dev);
2607 rtnl_unlock();
2608
2609 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2610 if (err)
2611 goto out;
2612 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2613 release_firmware(firmware);
2614out:
2615 rtnl_lock();
2616 dev_put(dev);
2617 return err;
2618}
2619
4400081b
AS		 2620#define MLXSW_SP_I2C_ADDR_LOW 0x50
2621#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2622#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2ea10903
AS		 2623
2624static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2625 u16 offset, u16 size, void *data,
2626 unsigned int *p_read_size)
2627{
2628 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2629 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2630 char mcia_pl[MLXSW_REG_MCIA_LEN];
4400081b 2631 u16 i2c_addr;
2ea10903
AS		 2632 int status;
2633 int err;
2634
2635 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
4400081b
AS		 2636
2637 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2638 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2639 /* Cross pages read, read until offset 256 in low page */
2640 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2641
2642 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2643 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2644 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2645 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2646 }
2647
2ea10903 2648 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
4400081b 2649 0, 0, offset, size, i2c_addr);
2ea10903
AS		 2650
2651 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2652 if (err)
2653 return err;
2654
2655 status = mlxsw_reg_mcia_status_get(mcia_pl);
2656 if (status)
2657 return -EIO;
2658
2659 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2660 memcpy(data, eeprom_tmp, size);
2661 *p_read_size = size;
2662
2663 return 0;
2664}
2665
2666enum mlxsw_sp_eeprom_module_info_rev_id {
2667 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2668 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2669 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2670};
2671
2672enum mlxsw_sp_eeprom_module_info_id {
2673 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2674 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2675 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2676 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2677};
2678
2679enum mlxsw_sp_eeprom_module_info {
2680 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2681 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2682 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2683};
2684
2685static int mlxsw_sp_get_module_info(struct net_device *netdev,
2686 struct ethtool_modinfo *modinfo)
2687{
2688 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2689 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2690 u8 module_rev_id, module_id;
2691 unsigned int read_size;
2692 int err;
2693
2694 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2695 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2696 module_info, &read_size);
2697 if (err)
2698 return err;
2699
2700 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2701 return -EIO;
2702
2703 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2704 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2705
2706 switch (module_id) {
2707 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2708 modinfo->type = ETH_MODULE_SFF_8436;
2709 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2710 break;
2711 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2712 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2713 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2714 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2715 modinfo->type = ETH_MODULE_SFF_8636;
2716 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2717 } else {
2718 modinfo->type = ETH_MODULE_SFF_8436;
2719 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2720 }
2721 break;
2722 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2723 modinfo->type = ETH_MODULE_SFF_8472;
2724 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2725 break;
2726 default:
2727 return -EINVAL;
2728 }
2729
2730 return 0;
2731}
2732
2733static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2734 struct ethtool_eeprom *ee,
2735 u8 *data)
2736{
2737 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2738 int offset = ee->offset;
2739 unsigned int read_size;
2740 int i = 0;
2741 int err;
2742
2743 if (!ee->len)
2744 return -EINVAL;
2745
2746 memset(data, 0, ee->len);
2747
2748 while (i < ee->len) {
2749 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2750 ee->len - i, data + i,
2751 &read_size);
2752 if (err) {
2753 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2754 return err;
2755 }
2756
2757 i += read_size;
2758 offset += read_size;
2759 }
2760
2761 return 0;
2762}
2763
56ade8fe
JP		 2764static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2765 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2766 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2767 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2768 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2769 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2770 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2771 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2772 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2773 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2774 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
ce6ef68f 2775 .flash_device = mlxsw_sp_flash_device,
2ea10903
AS		 2776 .get_module_info = mlxsw_sp_get_module_info,
2777 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
56ade8fe
JP		 2778};
2779
18f1e70c
IS		 2780static int
2781mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2782{
2783 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2784 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2785 char ptys_pl[MLXSW_REG_PTYS_LEN];
2786 u32 eth_proto_admin;
2787
2788 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
401c8b4e
ER		 2789 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2790 eth_proto_admin);
18f1e70c
IS		 2791 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2792}
2793
8e8dfe9f
IS		 2794int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2795 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2796 bool dwrr, u8 dwrr_weight)
90183b98
IS		 2797{
2798 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2799 char qeec_pl[MLXSW_REG_QEEC_LEN];
2800
2801 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2802 next_index);
2803 mlxsw_reg_qeec_de_set(qeec_pl, true);
2804 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2805 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2806 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2807}
2808
cc7cf517
IS		 2809int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2810 enum mlxsw_reg_qeec_hr hr, u8 index,
2811 u8 next_index, u32 maxrate)
90183b98
IS		 2812{
2813 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2814 char qeec_pl[MLXSW_REG_QEEC_LEN];
2815
2816 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2817 next_index);
2818 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2819 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2820 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2821}
2822
8e8dfe9f
IS		 2823int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2824 u8 switch_prio, u8 tclass)
90183b98
IS		 2825{
2826 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2827 char qtct_pl[MLXSW_REG_QTCT_LEN];
2828
2829 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2830 tclass);
2831 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2832}
2833
2834static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2835{
2836 int err, i;
2837
2838 /* Setup the elements hierarcy, so that each TC is linked to
2839 * one subgroup, which are all member in the same group.
2840 */
2841 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2842 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2843 0);
2844 if (err)
2845 return err;
2846 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2847 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2848 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2849 0, false, 0);
2850 if (err)
2851 return err;
2852 }
2853 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2854 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2855 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2856 false, 0);
2857 if (err)
2858 return err;
2859 }
2860
2861 /* Make sure the max shaper is disabled in all hierarcies that
2862 * support it.
2863 */
2864 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2865 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2866 MLXSW_REG_QEEC_MAS_DIS);
2867 if (err)
2868 return err;
2869 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2870 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2871 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2872 i, 0,
2873 MLXSW_REG_QEEC_MAS_DIS);
2874 if (err)
2875 return err;
2876 }
2877 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2878 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2879 MLXSW_REG_QEEC_HIERARCY_TC,
2880 i, i,
2881 MLXSW_REG_QEEC_MAS_DIS);
2882 if (err)
2883 return err;
2884 }
2885
2886 /* Map all priorities to traffic class 0. */
2887 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2888 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2889 if (err)
2890 return err;
2891 }
2892
2893 return 0;
2894}
2895
5b153859
IS		 2896static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2897 bool split, u8 module, u8 width, u8 lane)
56ade8fe 2898{
c57529e1 2899 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 2900 struct mlxsw_sp_port *mlxsw_sp_port;
2901 struct net_device *dev;
56ade8fe
JP		 2902 int err;
2903
5b153859
IS		 2904 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2905 if (err) {
2906 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2907 local_port);
2908 return err;
2909 }
2910
56ade8fe 2911 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
5b153859
IS		 2912 if (!dev) {
2913 err = -ENOMEM;
2914 goto err_alloc_etherdev;
2915 }
f20a91f1 2916 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 2917 mlxsw_sp_port = netdev_priv(dev);
2918 mlxsw_sp_port->dev = dev;
2919 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2920 mlxsw_sp_port->local_port = local_port;
c57529e1 2921 mlxsw_sp_port->pvid = 1;
18f1e70c 2922 mlxsw_sp_port->split = split;
d664b41e
IS		 2923 mlxsw_sp_port->mapping.module = module;
2924 mlxsw_sp_port->mapping.width = width;
2925 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 2926 mlxsw_sp_port->link.autoneg = 1;
31a08a52 2927 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
763b4b70 2928 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 2929
2930 mlxsw_sp_port->pcpu_stats =
2931 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2932 if (!mlxsw_sp_port->pcpu_stats) {
2933 err = -ENOMEM;
2934 goto err_alloc_stats;
2935 }
2936
98d0f7b9
YG		 2937 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2938 GFP_KERNEL);
2939 if (!mlxsw_sp_port->sample) {
2940 err = -ENOMEM;
2941 goto err_alloc_sample;
2942 }
2943
9deef43d 2944 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 2945 &update_stats_cache);
2946
56ade8fe
JP		 2947 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2948 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2949
2e915e0b 2950 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
5b153859
IS		 2951 if (err) {
2952 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2953 mlxsw_sp_port->local_port);
2954 goto err_port_module_map;
2955 }
2956
3247ff2b
IS		 2957 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2958 if (err) {
2959 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2960 mlxsw_sp_port->local_port);
2961 goto err_port_swid_set;
2962 }
2963
56ade8fe
JP		 2964 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2965 if (err) {
2966 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2967 mlxsw_sp_port->local_port);
2968 goto err_dev_addr_init;
2969 }
2970
2971 netif_carrier_off(dev);
2972
2973 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 2974 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2975 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 2976
d894be57
JW		 2977 dev->min_mtu = 0;
2978 dev->max_mtu = ETH_MAX_MTU;
2979
56ade8fe
JP		 2980 /* Each packet needs to have a Tx header (metadata) on top all other
2981 * headers.
2982 */
feb7d387 2983 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 2984
56ade8fe
JP		 2985 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2986 if (err) {
2987 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2988 mlxsw_sp_port->local_port);
2989 goto err_port_system_port_mapping_set;
2990 }
2991
18f1e70c
IS		 2992 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2993 if (err) {
2994 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2995 mlxsw_sp_port->local_port);
2996 goto err_port_speed_by_width_set;
2997 }
2998
56ade8fe
JP		 2999 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3000 if (err) {
3001 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3002 mlxsw_sp_port->local_port);
3003 goto err_port_mtu_set;
3004 }
3005
3006 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3007 if (err)
3008 goto err_port_admin_status_set;
3009
3010 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3011 if (err) {
3012 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3013 mlxsw_sp_port->local_port);
3014 goto err_port_buffers_init;
3015 }
3016
90183b98
IS		 3017 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3018 if (err) {
3019 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3020 mlxsw_sp_port->local_port);
3021 goto err_port_ets_init;
3022 }
3023
f00817df
IS		 3024 /* ETS and buffers must be initialized before DCB. */
3025 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3026 if (err) {
3027 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3028 mlxsw_sp_port->local_port);
3029 goto err_port_dcb_init;
3030 }
3031
a1107487 3032 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
45a4a16c 3033 if (err) {
a1107487 3034 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
45a4a16c 3035 mlxsw_sp_port->local_port);
a1107487 3036 goto err_port_fids_init;
45a4a16c
IS		 3037 }
3038
c57529e1
IS		 3039 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3040 if (IS_ERR(mlxsw_sp_port_vlan)) {
3041 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
05978481 3042 mlxsw_sp_port->local_port);
d86fd113 3043 err = PTR_ERR(mlxsw_sp_port_vlan);
c57529e1 3044 goto err_port_vlan_get;
05978481
IS		 3045 }
3046
56ade8fe 3047 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 3048 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 3049 err = register_netdev(dev);
3050 if (err) {
3051 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3052 mlxsw_sp_port->local_port);
3053 goto err_register_netdev;
3054 }
3055
d808c7e4
ER		 3056 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3057 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3058 module);
9deef43d 3059 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
56ade8fe
JP		 3060 return 0;
3061
56ade8fe 3062err_register_netdev:
2f25844c 3063 mlxsw_sp->ports[local_port] = NULL;
0583272d 3064 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1
IS		 3065 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3066err_port_vlan_get:
a1107487
IS		 3067 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3068err_port_fids_init:
4de34eb5 3069 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 3070err_port_dcb_init:
90183b98 3071err_port_ets_init:
56ade8fe
JP		 3072err_port_buffers_init:
3073err_port_admin_status_set:
3074err_port_mtu_set:
18f1e70c 3075err_port_speed_by_width_set:
56ade8fe 3076err_port_system_port_mapping_set:
56ade8fe 3077err_dev_addr_init:
3247ff2b
IS		 3078 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3079err_port_swid_set:
2e915e0b 3080 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
5b153859 3081err_port_module_map:
98d0f7b9
YG		 3082 kfree(mlxsw_sp_port->sample);
3083err_alloc_sample:
56ade8fe
JP		 3084 free_percpu(mlxsw_sp_port->pcpu_stats);
3085err_alloc_stats:
3086 free_netdev(dev);
5b153859 3087err_alloc_etherdev:
67963a33
JP		 3088 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3089 return err;
3090}
3091
5b153859 3092static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
56ade8fe
JP		 3093{
3094 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3095
9deef43d 3096 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
67963a33 3097 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
56ade8fe 3098 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 3099 mlxsw_sp->ports[local_port] = NULL;
0583272d 3100 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1 3101 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
a1107487 3102 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
f00817df 3103 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8 3104 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2e915e0b 3105 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
98d0f7b9 3106 kfree(mlxsw_sp_port->sample);
136f1445 3107 free_percpu(mlxsw_sp_port->pcpu_stats);
31a08a52 3108 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
56ade8fe 3109 free_netdev(mlxsw_sp_port->dev);
67963a33
JP		 3110 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3111}
3112
f83e2102
JP		 3113static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3114{
3115 return mlxsw_sp->ports[local_port] != NULL;
3116}
3117
56ade8fe
JP		 3118static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3119{
3120 int i;
3121
5ec2ee7d 3122 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
f83e2102
JP		 3123 if (mlxsw_sp_port_created(mlxsw_sp, i))
3124 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d 3125 kfree(mlxsw_sp->port_to_module);
56ade8fe
JP		 3126 kfree(mlxsw_sp->ports);
3127}
3128
3129static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3130{
5ec2ee7d 3131 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
d664b41e 3132 u8 module, width, lane;
56ade8fe
JP		 3133 size_t alloc_size;
3134 int i;
3135 int err;
3136
5ec2ee7d 3137 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
56ade8fe
JP		 3138 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3139 if (!mlxsw_sp->ports)
3140 return -ENOMEM;
3141
bf4e9f24
IS		 3142 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3143 GFP_KERNEL);
5ec2ee7d
IS		 3144 if (!mlxsw_sp->port_to_module) {
3145 err = -ENOMEM;
3146 goto err_port_to_module_alloc;
3147 }
3148
3149 for (i = 1; i < max_ports; i++) {
bf4e9f24
IS		 3150 /* Mark as invalid */
3151 mlxsw_sp->port_to_module[i] = -1;
3152
558c2d5e 3153 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 3154 &width, &lane);
558c2d5e
IS		 3155 if (err)
3156 goto err_port_module_info_get;
3157 if (!width)
3158 continue;
3159 mlxsw_sp->port_to_module[i] = module;
67963a33
JP		 3160 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3161 module, width, lane);
56ade8fe
JP		 3162 if (err)
3163 goto err_port_create;
3164 }
3165 return 0;
3166
3167err_port_create:
558c2d5e 3168err_port_module_info_get:
56ade8fe 3169 for (i--; i >= 1; i--)
f83e2102
JP		 3170 if (mlxsw_sp_port_created(mlxsw_sp, i))
3171 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d
IS		 3172 kfree(mlxsw_sp->port_to_module);
3173err_port_to_module_alloc:
56ade8fe
JP		 3174 kfree(mlxsw_sp->ports);
3175 return err;
3176}
3177
18f1e70c
IS		 3178static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3179{
3180 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3181
3182 return local_port - offset;
3183}
3184
be94535f
IS		 3185static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3186 u8 module, unsigned int count)
3187{
3188 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3189 int err, i;
3190
be94535f
IS		 3191 for (i = 0; i < count; i++) {
3192 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 3193 module, width, i * width);
be94535f
IS		 3194 if (err)
3195 goto err_port_create;
3196 }
3197
3198 return 0;
3199
3200err_port_create:
3201 for (i--; i >= 0; i--)
f83e2102
JP		 3202 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3203 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
be94535f
IS		 3204 return err;
3205}
3206
3207static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3208 u8 base_port, unsigned int count)
3209{
3210 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3211 int i;
3212
3213 /* Split by four means we need to re-create two ports, otherwise
3214 * only one.
3215 */
3216 count = count / 2;
3217
be94535f
IS		 3218 for (i = 0; i < count; i++) {
3219 local_port = base_port + i * 2;
bf4e9f24
IS		 3220 if (mlxsw_sp->port_to_module[local_port] < 0)
3221 continue;
be94535f
IS		 3222 module = mlxsw_sp->port_to_module[local_port];
3223
3224 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 3225 width, 0);
be94535f
IS		 3226 }
3227}
3228
b2f10571
JP		 3229static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3230 unsigned int count)
18f1e70c 3231{
b2f10571 3232 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3233 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 3234 u8 module, cur_width, base_port;
3235 int i;
3236 int err;
3237
3238 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3239 if (!mlxsw_sp_port) {
3240 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3241 local_port);
3242 return -EINVAL;
3243 }
3244
d664b41e
IS		 3245 module = mlxsw_sp_port->mapping.module;
3246 cur_width = mlxsw_sp_port->mapping.width;
3247
18f1e70c
IS		 3248 if (count != 2 && count != 4) {
3249 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3250 return -EINVAL;
3251 }
3252
18f1e70c
IS		 3253 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3254 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3255 return -EINVAL;
3256 }
3257
3258 /* Make sure we have enough slave (even) ports for the split. */
3259 if (count == 2) {
3260 base_port = local_port;
3261 if (mlxsw_sp->ports[base_port + 1]) {
3262 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3263 return -EINVAL;
3264 }
3265 } else {
3266 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3267 if (mlxsw_sp->ports[base_port + 1] ||
3268 mlxsw_sp->ports[base_port + 3]) {
3269 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3270 return -EINVAL;
3271 }
3272 }
3273
3274 for (i = 0; i < count; i++)
f83e2102
JP		 3275 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3276 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3277
be94535f
IS		 3278 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3279 if (err) {
3280 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3281 goto err_port_split_create;
18f1e70c
IS		 3282 }
3283
3284 return 0;
3285
be94535f
IS		 3286err_port_split_create:
3287 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3288 return err;
3289}
3290
b2f10571 3291static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 3292{
b2f10571 3293 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3294 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 3295 u8 cur_width, base_port;
18f1e70c
IS		 3296 unsigned int count;
3297 int i;
18f1e70c
IS		 3298
3299 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3300 if (!mlxsw_sp_port) {
3301 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3302 local_port);
3303 return -EINVAL;
3304 }
3305
3306 if (!mlxsw_sp_port->split) {
3307 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3308 return -EINVAL;
3309 }
3310
d664b41e 3311 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 3312 count = cur_width == 1 ? 4 : 2;
3313
3314 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3315
3316 /* Determine which ports to remove. */
3317 if (count == 2 && local_port >= base_port + 2)
3318 base_port = base_port + 2;
3319
3320 for (i = 0; i < count; i++)
f83e2102
JP		 3321 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3322 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3323
be94535f 3324 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3325
3326 return 0;
3327}
3328
56ade8fe
JP		 3329static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3330 char *pude_pl, void *priv)
3331{
3332 struct mlxsw_sp *mlxsw_sp = priv;
3333 struct mlxsw_sp_port *mlxsw_sp_port;
3334 enum mlxsw_reg_pude_oper_status status;
3335 u8 local_port;
3336
3337 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3338 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 3339 if (!mlxsw_sp_port)
56ade8fe 3340 return;
56ade8fe
JP		 3341
3342 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3343 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3344 netdev_info(mlxsw_sp_port->dev, "link up\n");
3345 netif_carrier_on(mlxsw_sp_port->dev);
3346 } else {
3347 netdev_info(mlxsw_sp_port->dev, "link down\n");
3348 netif_carrier_off(mlxsw_sp_port->dev);
3349 }
3350}
3351
14eeda99
NF		 3352static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3353 u8 local_port, void *priv)
56ade8fe
JP		 3354{
3355 struct mlxsw_sp *mlxsw_sp = priv;
3356 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3357 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3358
3359 if (unlikely(!mlxsw_sp_port)) {
3360 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3361 local_port);
3362 return;
3363 }
3364
3365 skb->dev = mlxsw_sp_port->dev;
3366
3367 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3368 u64_stats_update_begin(&pcpu_stats->syncp);
3369 pcpu_stats->rx_packets++;
3370 pcpu_stats->rx_bytes += skb->len;
3371 u64_stats_update_end(&pcpu_stats->syncp);
3372
3373 skb->protocol = eth_type_trans(skb, skb->dev);
3374 netif_receive_skb(skb);
3375}
3376
1c6c6d22
IS		 3377static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3378 void *priv)
3379{
3380 skb->offload_fwd_mark = 1;
14eeda99 3381 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
1c6c6d22
IS		 3382}
3383
a0040c8c
YG		 3384static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3385 u8 local_port, void *priv)
3386{
3387 skb->offload_mr_fwd_mark = 1;
3388 skb->offload_fwd_mark = 1;
3389 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3390}
3391
98d0f7b9
YG		 3392static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3393 void *priv)
3394{
3395 struct mlxsw_sp *mlxsw_sp = priv;
3396 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3397 struct psample_group *psample_group;
3398 u32 size;
3399
3400 if (unlikely(!mlxsw_sp_port)) {
3401 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3402 local_port);
3403 goto out;
3404 }
3405 if (unlikely(!mlxsw_sp_port->sample)) {
3406 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3407 local_port);
3408 goto out;
3409 }
3410
3411 size = mlxsw_sp_port->sample->truncate ?
3412 mlxsw_sp_port->sample->trunc_size : skb->len;
3413
3414 rcu_read_lock();
3415 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3416 if (!psample_group)
3417 goto out_unlock;
3418 psample_sample_packet(psample_group, skb, size,
3419 mlxsw_sp_port->dev->ifindex, 0,
3420 mlxsw_sp_port->sample->rate);
3421out_unlock:
3422 rcu_read_unlock();
3423out:
3424 consume_skb(skb);
3425}
3426
117b0dad 3427#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
0fb78a4e 3428 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
117b0dad 3429 _is_ctrl, SP_##_trap_group, DISCARD)
14eeda99 3430
117b0dad 3431#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
14eeda99 3432 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
117b0dad
NF		 3433 _is_ctrl, SP_##_trap_group, DISCARD)
3434
a0040c8c
YG		 3435#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3436 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3437 _is_ctrl, SP_##_trap_group, DISCARD)
3438
117b0dad
NF		 3439#define MLXSW_SP_EVENTL(_func, _trap_id) \
3440 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
93393b33 3441
4544913e
NF		 3442static const struct mlxsw_listener mlxsw_sp_listener[] = {
3443 /* Events */
117b0dad 3444 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
ee4a60d8 3445 /* L2 traps */
117b0dad
NF		 3446 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3447 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3448 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3449 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3450 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3451 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3452 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3453 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3454 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3455 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3456 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
9d41accc 3457 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
588823f9
AS		 3458 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3459 false),
3460 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3461 false),
3462 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3463 false),
3464 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3465 false),
93393b33 3466 /* L3 traps */
0fcc4847
IS		 3467 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3468 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3469 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
0fcc4847 3470 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
8d54814e
AS		 3471 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3472 false),
3473 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3474 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3475 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3476 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3477 false),
3478 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3479 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3480 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
0fcc4847 3481 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
8d54814e
AS		 3482 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3483 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3484 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3485 false),
3486 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3487 false),
3488 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3489 false),
3490 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3491 false),
3492 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3493 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3494 false),
3495 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3496 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
7607dd35 3497 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
8d54814e 3498 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
86484de2 3499 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
98d0f7b9
YG		 3500 /* PKT Sample trap */
3501 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
0db7b386
JP		 3502 false, SP_IP2ME, DISCARD),
3503 /* ACL trap */
3504 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
b48cfc80
YG		 3505 /* Multicast Router Traps */
3506 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3507 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3508 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
a0040c8c 3509 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
56ade8fe
JP		 3510};
3511
9148e7cf
NF		 3512static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3513{
3514 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3515 enum mlxsw_reg_qpcr_ir_units ir_units;
3516 int max_cpu_policers;
3517 bool is_bytes;
3518 u8 burst_size;
3519 u32 rate;
3520 int i, err;
3521
3522 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3523 return -EIO;
3524
3525 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3526
3527 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3528 for (i = 0; i < max_cpu_policers; i++) {
3529 is_bytes = false;
3530 switch (i) {
3531 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3532 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3533 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3534 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80
YG		 3535 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3536 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
9148e7cf
NF		 3537 rate = 128;
3538 burst_size = 7;
3539 break;
3540 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
588823f9 3541 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
9148e7cf
NF		 3542 rate = 16 * 1024;
3543 burst_size = 10;
3544 break;
8d54814e 3545 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
9148e7cf
NF		 3546 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3547 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
8d54814e 3548 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
9148e7cf
NF		 3549 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3550 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
8d54814e 3551 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3552 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
9148e7cf
NF		 3553 rate = 1024;
3554 burst_size = 7;
3555 break;
3556 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3557 is_bytes = true;
3558 rate = 4 * 1024;
3559 burst_size = 4;
3560 break;
3561 default:
3562 continue;
3563 }
3564
3565 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3566 burst_size);
3567 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3568 if (err)
3569 return err;
3570 }
3571
3572 return 0;
3573}
3574
579c82e4 3575static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
56ade8fe
JP		 3576{
3577 char htgt_pl[MLXSW_REG_HTGT_LEN];
117b0dad 3578 enum mlxsw_reg_htgt_trap_group i;
9148e7cf 3579 int max_cpu_policers;
579c82e4
NF		 3580 int max_trap_groups;
3581 u8 priority, tc;
9148e7cf 3582 u16 policer_id;
117b0dad 3583 int err;
579c82e4
NF		 3584
3585 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3586 return -EIO;
3587
3588 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
9148e7cf 3589 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
579c82e4
NF		 3590
3591 for (i = 0; i < max_trap_groups; i++) {
9148e7cf 3592 policer_id = i;
579c82e4 3593 switch (i) {
117b0dad
NF		 3594 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3595 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3596 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3597 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80 3598 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
117b0dad
NF		 3599 priority = 5;
3600 tc = 5;
3601 break;
8d54814e 3602 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
117b0dad
NF		 3603 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3604 priority = 4;
3605 tc = 4;
3606 break;
3607 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3608 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
588823f9 3609 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
117b0dad
NF		 3610 priority = 3;
3611 tc = 3;
3612 break;
3613 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
8d54814e 3614 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3615 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
117b0dad
NF		 3616 priority = 2;
3617 tc = 2;
3618 break;
8d54814e 3619 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
117b0dad
NF		 3620 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3621 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
b48cfc80 3622 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
117b0dad
NF		 3623 priority = 1;
3624 tc = 1;
3625 break;
3626 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
579c82e4
NF		 3627 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3628 tc = MLXSW_REG_HTGT_DEFAULT_TC;
9148e7cf 3629 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
579c82e4
NF		 3630 break;
3631 default:
3632 continue;
3633 }
117b0dad 3634
9148e7cf
NF		 3635 if (max_cpu_policers <= policer_id &&
3636 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3637 return -EIO;
3638
3639 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
579c82e4
NF		 3640 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3641 if (err)
3642 return err;
3643 }
3644
3645 return 0;
3646}
3647
3648static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3649{
56ade8fe
JP		 3650 int i;
3651 int err;
3652
9148e7cf
NF		 3653 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3654 if (err)
3655 return err;
3656
579c82e4 3657 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
56ade8fe
JP		 3658 if (err)
3659 return err;
3660
4544913e 3661 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3662 err = mlxsw_core_trap_register(mlxsw_sp->core,
4544913e 3663 &mlxsw_sp_listener[i],
14eeda99 3664 mlxsw_sp);
56ade8fe 3665 if (err)
4544913e 3666 goto err_listener_register;
56ade8fe 3667
56ade8fe
JP		 3668 }
3669 return 0;
3670
4544913e 3671err_listener_register:
56ade8fe 3672 for (i--; i >= 0; i--) {
14eeda99 3673 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3674 &mlxsw_sp_listener[i],
14eeda99 3675 mlxsw_sp);
56ade8fe
JP		 3676 }
3677 return err;
3678}
3679
3680static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3681{
56ade8fe
JP		 3682 int i;
3683
4544913e 3684 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3685 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3686 &mlxsw_sp_listener[i],
14eeda99 3687 mlxsw_sp);
56ade8fe
JP		 3688 }
3689}
3690
0d65fc13
JP		 3691static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3692{
3693 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 3694 int err;
0d65fc13
JP		 3695
3696 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3697 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3698 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3699 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3700 MLXSW_REG_SLCR_LAG_HASH_SIP |
3701 MLXSW_REG_SLCR_LAG_HASH_DIP |
3702 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3703 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3704 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 3705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3706 if (err)
3707 return err;
3708
c1a38311
JP		 3709 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3710 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 3711 return -EIO;
3712
c1a38311 3713 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 3714 sizeof(struct mlxsw_sp_upper),
3715 GFP_KERNEL);
3716 if (!mlxsw_sp->lags)
3717 return -ENOMEM;
3718
3719 return 0;
3720}
3721
3722static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3723{
3724 kfree(mlxsw_sp->lags);
0d65fc13
JP		 3725}
3726
9d87fcea
NF		 3727static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3728{
3729 char htgt_pl[MLXSW_REG_HTGT_LEN];
3730
579c82e4
NF		 3731 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3732 MLXSW_REG_HTGT_INVALID_POLICER,
3733 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3734 MLXSW_REG_HTGT_DEFAULT_TC);
9d87fcea
NF		 3735 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3736}
3737
c30f5d01
PM		 3738static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3739 unsigned long event, void *ptr);
3740
b2f10571 3741static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 3742 const struct mlxsw_bus_info *mlxsw_bus_info)
3743{
b2f10571 3744 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 3745 int err;
3746
3747 mlxsw_sp->core = mlxsw_core;
3748 mlxsw_sp->bus_info = mlxsw_bus_info;
3749
6b742199
YG		 3750 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3751 if (err) {
3752 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3753 return err;
3754 }
3755
56ade8fe
JP		 3756 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3757 if (err) {
3758 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3759 return err;
3760 }
3761
a875a2ee
IS		 3762 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3763 if (err) {
3764 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3765 return err;
3766 }
3767
a1107487 3768 err = mlxsw_sp_fids_init(mlxsw_sp);
56ade8fe 3769 if (err) {
a1107487 3770 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
a875a2ee 3771 goto err_fids_init;
56ade8fe
JP		 3772 }
3773
a1107487 3774 err = mlxsw_sp_traps_init(mlxsw_sp);
56ade8fe 3775 if (err) {
a1107487
IS		 3776 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3777 goto err_traps_init;
56ade8fe
JP		 3778 }
3779
3780 err = mlxsw_sp_buffers_init(mlxsw_sp);
3781 if (err) {
3782 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3783 goto err_buffers_init;
3784 }
3785
0d65fc13
JP		 3786 err = mlxsw_sp_lag_init(mlxsw_sp);
3787 if (err) {
3788 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3789 goto err_lag_init;
3790 }
3791
56ade8fe
JP		 3792 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3793 if (err) {
3794 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3795 goto err_switchdev_init;
3796 }
3797
e2b2d35a
YG		 3798 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3799 if (err) {
3800 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3801 goto err_counter_pool_init;
3802 }
3803
d3b939b8
YG		 3804 err = mlxsw_sp_afa_init(mlxsw_sp);
3805 if (err) {
3806 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3807 goto err_afa_init;
3808 }
3809
464dce18
IS		 3810 err = mlxsw_sp_router_init(mlxsw_sp);
3811 if (err) {
3812 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3813 goto err_router_init;
3814 }
3815
c30f5d01
PM		 3816 /* Initialize netdevice notifier after router is initialized, so that
3817 * the event handler can use router structures.
3818 */
3819 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3820 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3821 if (err) {
3822 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3823 goto err_netdev_notifier;
3824 }
3825
763b4b70
YG		 3826 err = mlxsw_sp_span_init(mlxsw_sp);
3827 if (err) {
3828 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3829 goto err_span_init;
3830 }
3831
22a67766
JP		 3832 err = mlxsw_sp_acl_init(mlxsw_sp);
3833 if (err) {
3834 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3835 goto err_acl_init;
3836 }
3837
230ead01
AS		 3838 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3839 if (err) {
3840 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3841 goto err_dpipe_init;
3842 }
3843
bbf2a475
IS		 3844 err = mlxsw_sp_ports_create(mlxsw_sp);
3845 if (err) {
3846 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3847 goto err_ports_create;
3848 }
3849
56ade8fe
JP		 3850 return 0;
3851
bbf2a475 3852err_ports_create:
230ead01
AS		 3853 mlxsw_sp_dpipe_fini(mlxsw_sp);
3854err_dpipe_init:
22a67766
JP		 3855 mlxsw_sp_acl_fini(mlxsw_sp);
3856err_acl_init:
763b4b70
YG		 3857 mlxsw_sp_span_fini(mlxsw_sp);
3858err_span_init:
c30f5d01
PM		 3859 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3860err_netdev_notifier:
464dce18
IS		 3861 mlxsw_sp_router_fini(mlxsw_sp);
3862err_router_init:
d3b939b8
YG		 3863 mlxsw_sp_afa_fini(mlxsw_sp);
3864err_afa_init:
e2b2d35a
YG		 3865 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3866err_counter_pool_init:
bbf2a475 3867 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 3868err_switchdev_init:
ce0bd2b0 3869 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 3870err_lag_init:
0f433fa0 3871 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3872err_buffers_init:
56ade8fe 3873 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487
IS		 3874err_traps_init:
3875 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee
IS		 3876err_fids_init:
3877 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 3878 return err;
3879}
3880
b2f10571 3881static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 3882{
b2f10571 3883 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 3884
bbf2a475 3885 mlxsw_sp_ports_remove(mlxsw_sp);
230ead01 3886 mlxsw_sp_dpipe_fini(mlxsw_sp);
22a67766 3887 mlxsw_sp_acl_fini(mlxsw_sp);
763b4b70 3888 mlxsw_sp_span_fini(mlxsw_sp);
c30f5d01 3889 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
464dce18 3890 mlxsw_sp_router_fini(mlxsw_sp);
d3b939b8 3891 mlxsw_sp_afa_fini(mlxsw_sp);
e2b2d35a 3892 mlxsw_sp_counter_pool_fini(mlxsw_sp);
56ade8fe 3893 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 3894 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 3895 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 3896 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487 3897 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee 3898 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 3899}
3900
159fe88e 3901static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
56ade8fe
JP		 3902 .used_max_vepa_channels = 1,
3903 .max_vepa_channels = 0,
56ade8fe 3904 .used_max_mid = 1,
53ae6283 3905 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 3906 .used_max_pgt = 1,
3907 .max_pgt = 0,
56ade8fe
JP		 3908 .used_flood_tables = 1,
3909 .used_flood_mode = 1,
3910 .flood_mode = 3,
71c365bd 3911 .max_fid_offset_flood_tables = 3,
56ade8fe 3912 .fid_offset_flood_table_size = VLAN_N_VID - 1,
71c365bd 3913 .max_fid_flood_tables = 3,
a1107487 3914 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
56ade8fe
JP		 3915 .used_max_ib_mc = 1,
3916 .max_ib_mc = 0,
3917 .used_max_pkey = 1,
3918 .max_pkey = 0,
403547d3
NF		 3919 .used_kvd_split_data = 1,
3920 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
f11fbaf8
IS		 3921 .kvd_hash_single_parts = 59,
3922 .kvd_hash_double_parts = 41,
c6022427 3923 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 3924 .swid_config = {
3925 {
3926 .used_type = 1,
3927 .type = MLXSW_PORT_SWID_TYPE_ETH,
3928 }
3929 },
57d316ba 3930 .resource_query_enable = 1,
56ade8fe
JP		 3931};
3932
3933static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 3934 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 3935 .priv_size = sizeof(struct mlxsw_sp),
3936 .init = mlxsw_sp_init,
3937 .fini = mlxsw_sp_fini,
9d87fcea 3938 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
2d0ed39f
JP		 3939 .port_split = mlxsw_sp_port_split,
3940 .port_unsplit = mlxsw_sp_port_unsplit,
3941 .sb_pool_get = mlxsw_sp_sb_pool_get,
3942 .sb_pool_set = mlxsw_sp_sb_pool_set,
3943 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3944 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3945 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3946 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3947 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3948 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3949 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3950 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3951 .txhdr_construct = mlxsw_sp_txhdr_construct,
3952 .txhdr_len = MLXSW_TXHDR_LEN,
3953 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 3954};
3955
22a67766 3956bool mlxsw_sp_port_dev_check(const struct net_device *dev)
7ce856aa
JP		 3957{
3958 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3959}
3960
1182e536 3961static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
dd82364c 3962{
1182e536 3963 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
dd82364c
DA		 3964 int ret = 0;
3965
3966 if (mlxsw_sp_port_dev_check(lower_dev)) {
1182e536 3967 *p_mlxsw_sp_port = netdev_priv(lower_dev);
dd82364c
DA		 3968 ret = 1;
3969 }
3970
3971 return ret;
3972}
3973
c57529e1 3974struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
7ce856aa 3975{
1182e536 3976 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 3977
3978 if (mlxsw_sp_port_dev_check(dev))
3979 return netdev_priv(dev);
3980
1182e536
JP		 3981 mlxsw_sp_port = NULL;
3982 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
dd82364c 3983
1182e536 3984 return mlxsw_sp_port;
7ce856aa
JP		 3985}
3986
4724ba56 3987struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
7ce856aa
JP		 3988{
3989 struct mlxsw_sp_port *mlxsw_sp_port;
3990
3991 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3992 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3993}
3994
af061378 3995struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
7ce856aa 3996{
1182e536 3997 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 3998
3999 if (mlxsw_sp_port_dev_check(dev))
4000 return netdev_priv(dev);
4001
1182e536
JP		 4002 mlxsw_sp_port = NULL;
4003 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4004 &mlxsw_sp_port);
dd82364c 4005
1182e536 4006 return mlxsw_sp_port;
7ce856aa
JP		 4007}
4008
4009struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4010{
4011 struct mlxsw_sp_port *mlxsw_sp_port;
4012
4013 rcu_read_lock();
4014 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4015 if (mlxsw_sp_port)
4016 dev_hold(mlxsw_sp_port->dev);
4017 rcu_read_unlock();
4018 return mlxsw_sp_port;
4019}
4020
4021void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4022{
4023 dev_put(mlxsw_sp_port->dev);
4024}
4025
0d65fc13
JP		 4026static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4027{
4028 char sldr_pl[MLXSW_REG_SLDR_LEN];
4029
4030 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4031 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4032}
4033
4034static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4035{
4036 char sldr_pl[MLXSW_REG_SLDR_LEN];
4037
4038 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4039 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4040}
4041
4042static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4043 u16 lag_id, u8 port_index)
4044{
4045 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4046 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4047
4048 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4049 lag_id, port_index);
4050 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4051}
4052
4053static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4054 u16 lag_id)
4055{
4056 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4057 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4058
4059 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4060 lag_id);
4061 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4062}
4063
4064static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4065 u16 lag_id)
4066{
4067 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4068 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4069
4070 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4071 lag_id);
4072 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4073}
4074
4075static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4076 u16 lag_id)
4077{
4078 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4079 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4080
4081 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4082 lag_id);
4083 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4084}
4085
4086static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4087 struct net_device *lag_dev,
4088 u16 *p_lag_id)
4089{
4090 struct mlxsw_sp_upper *lag;
4091 int free_lag_id = -1;
c1a38311 4092 u64 max_lag;
0d65fc13
JP		 4093 int i;
4094
c1a38311
JP		 4095 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4096 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 4097 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4098 if (lag->ref_count) {
4099 if (lag->dev == lag_dev) {
4100 *p_lag_id = i;
4101 return 0;
4102 }
4103 } else if (free_lag_id < 0) {
4104 free_lag_id = i;
4105 }
4106 }
4107 if (free_lag_id < 0)
4108 return -EBUSY;
4109 *p_lag_id = free_lag_id;
4110 return 0;
4111}
4112
4113static bool
4114mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4115 struct net_device *lag_dev,
e58376e1
DA		 4116 struct netdev_lag_upper_info *lag_upper_info,
4117 struct netlink_ext_ack *extack)
0d65fc13
JP		 4118{
4119 u16 lag_id;
4120
e58376e1
DA		 4121 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4122 NL_SET_ERR_MSG(extack,
4123 "spectrum: Exceeded number of supported LAG devices");
0d65fc13 4124 return false;
e58376e1
DA		 4125 }
4126 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4127 NL_SET_ERR_MSG(extack,
4128 "spectrum: LAG device using unsupported Tx type");
0d65fc13 4129 return false;
e58376e1 4130 }
0d65fc13
JP		 4131 return true;
4132}
4133
4134static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4135 u16 lag_id, u8 *p_port_index)
4136{
c1a38311 4137 u64 max_lag_members;
0d65fc13
JP		 4138 int i;
4139
c1a38311
JP		 4140 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4141 MAX_LAG_MEMBERS);
4142 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 4143 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4144 *p_port_index = i;
4145 return 0;
4146 }
4147 }
4148 return -EBUSY;
4149}
4150
4151static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4152 struct net_device *lag_dev)
4153{
4154 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
c57529e1 4155 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
0d65fc13
JP		 4156 struct mlxsw_sp_upper *lag;
4157 u16 lag_id;
4158 u8 port_index;
4159 int err;
4160
4161 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4162 if (err)
4163 return err;
4164 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4165 if (!lag->ref_count) {
4166 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4167 if (err)
4168 return err;
4169 lag->dev = lag_dev;
4170 }
4171
4172 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4173 if (err)
4174 return err;
4175 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4176 if (err)
4177 goto err_col_port_add;
4178 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4179 if (err)
4180 goto err_col_port_enable;
4181
4182 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4183 mlxsw_sp_port->local_port);
4184 mlxsw_sp_port->lag_id = lag_id;
4185 mlxsw_sp_port->lagged = 1;
4186 lag->ref_count++;
86bf95b3 4187
c57529e1
IS		 4188 /* Port is no longer usable as a router interface */
4189 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4190 if (mlxsw_sp_port_vlan->fid)
a1107487 4191 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
86bf95b3 4192
0d65fc13
JP		 4193 return 0;
4194
51554db2
IS		 4195err_col_port_enable:
4196 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4197err_col_port_add:
4198 if (!lag->ref_count)
4199 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4200 return err;
4201}
4202
82e6db03
IS		 4203static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4204 struct net_device *lag_dev)
0d65fc13
JP		 4205{
4206 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4207 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4208 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4209
4210 if (!mlxsw_sp_port->lagged)
82e6db03 4211 return;
0d65fc13
JP		 4212 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4213 WARN_ON(lag->ref_count == 0);
4214
82e6db03
IS		 4215 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4216 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4217
c57529e1
IS		 4218 /* Any VLANs configured on the port are no longer valid */
4219 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4dc236c3 4220
fe3f6d14 4221 if (lag->ref_count == 1)
82e6db03 4222 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4223
4224 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4225 mlxsw_sp_port->local_port);
4226 mlxsw_sp_port->lagged = 0;
4227 lag->ref_count--;
86bf95b3 4228
c57529e1
IS		 4229 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4230 /* Make sure untagged frames are allowed to ingress */
4231 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
0d65fc13
JP		 4232}
4233
74581206
JP		 4234static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4235 u16 lag_id)
4236{
4237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4238 char sldr_pl[MLXSW_REG_SLDR_LEN];
4239
4240 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4241 mlxsw_sp_port->local_port);
4242 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4243}
4244
4245static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4246 u16 lag_id)
4247{
4248 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4249 char sldr_pl[MLXSW_REG_SLDR_LEN];
4250
4251 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4252 mlxsw_sp_port->local_port);
4253 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4254}
4255
4256static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4257 bool lag_tx_enabled)
4258{
4259 if (lag_tx_enabled)
4260 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4261 mlxsw_sp_port->lag_id);
4262 else
4263 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4264 mlxsw_sp_port->lag_id);
4265}
4266
4267static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4268 struct netdev_lag_lower_state_info *info)
4269{
4270 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4271}
4272
2b94e58d
JP		 4273static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4274 bool enable)
4275{
4276 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4277 enum mlxsw_reg_spms_state spms_state;
4278 char *spms_pl;
4279 u16 vid;
4280 int err;
4281
4282 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4283 MLXSW_REG_SPMS_STATE_DISCARDING;
4284
4285 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4286 if (!spms_pl)
4287 return -ENOMEM;
4288 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4289
4290 for (vid = 0; vid < VLAN_N_VID; vid++)
4291 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4292
4293 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4294 kfree(spms_pl);
4295 return err;
4296}
4297
4298static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4299{
4300 int err;
4301
4aafc368 4302 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
2b94e58d
JP		 4303 if (err)
4304 return err;
4aafc368
IS		 4305 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4306 if (err)
4307 goto err_port_stp_set;
2b94e58d
JP		 4308 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4309 true, false);
4310 if (err)
4311 goto err_port_vlan_set;
4312 return 0;
4313
4314err_port_vlan_set:
4315 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368
IS		 4316err_port_stp_set:
4317 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4318 return err;
4319}
4320
4321static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4322{
4323 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4324 false, false);
4325 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368 4326 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4327}
4328
f0cebd81
IS		 4329static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4330 struct net_device *dev,
74581206 4331 unsigned long event, void *ptr)
56ade8fe 4332{
56ade8fe
JP		 4333 struct netdev_notifier_changeupper_info *info;
4334 struct mlxsw_sp_port *mlxsw_sp_port;
e58376e1 4335 struct netlink_ext_ack *extack;
56ade8fe
JP		 4336 struct net_device *upper_dev;
4337 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4338 int err = 0;
56ade8fe 4339
56ade8fe
JP		 4340 mlxsw_sp_port = netdev_priv(dev);
4341 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4342 info = ptr;
e58376e1 4343 extack = netdev_notifier_info_to_extack(&info->info);
56ade8fe
JP		 4344
4345 switch (event) {
4346 case NETDEV_PRECHANGEUPPER:
4347 upper_dev = info->upper_dev;
59fe9b3f
IS		 4348 if (!is_vlan_dev(upper_dev) &&
4349 !netif_is_lag_master(upper_dev) &&
7179eb5a 4350 !netif_is_bridge_master(upper_dev) &&
e58376e1
DA		 4351 !netif_is_ovs_master(upper_dev)) {
4352 NL_SET_ERR_MSG(extack,
4353 "spectrum: Unknown upper device type");
59fe9b3f 4354 return -EINVAL;
e58376e1 4355 }
6ec43904 4356 if (!info->linking)
0d65fc13 4357 break;
e58376e1
DA		 4358 if (netdev_has_any_upper_dev(upper_dev)) {
4359 NL_SET_ERR_MSG(extack,
4360 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4361 return -EINVAL;
e58376e1 4362 }
0d65fc13
JP		 4363 if (netif_is_lag_master(upper_dev) &&
4364 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
e58376e1 4365 info->upper_info, extack))
80bedf1a 4366 return -EINVAL;
e58376e1
DA		 4367 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4368 NL_SET_ERR_MSG(extack,
4369 "spectrum: Master device is a LAG master and this device has a VLAN");
6ec43904 4370 return -EINVAL;
e58376e1 4371 }
6ec43904 4372 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
e58376e1
DA		 4373 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4374 NL_SET_ERR_MSG(extack,
4375 "spectrum: Can not put a VLAN on a LAG port");
6ec43904 4376 return -EINVAL;
e58376e1
DA		 4377 }
4378 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4379 NL_SET_ERR_MSG(extack,
4380 "spectrum: Master device is an OVS master and this device has a VLAN");
2b94e58d 4381 return -EINVAL;
e58376e1
DA		 4382 }
4383 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4384 NL_SET_ERR_MSG(extack,
4385 "spectrum: Can not put a VLAN on an OVS port");
2b94e58d 4386 return -EINVAL;
e58376e1 4387 }
56ade8fe
JP		 4388 break;
4389 case NETDEV_CHANGEUPPER:
4390 upper_dev = info->upper_dev;
c57529e1 4391 if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4392 if (info->linking)
4393 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
f0cebd81 4394 lower_dev,
9b63ef88
IS		 4395 upper_dev,
4396 extack);
7117a570 4397 else
f0cebd81
IS		 4398 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4399 lower_dev,
4400 upper_dev);
0d65fc13 4401 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4402 if (info->linking)
0d65fc13
JP		 4403 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4404 upper_dev);
80bedf1a 4405 else
82e6db03
IS		 4406 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4407 upper_dev);
2b94e58d
JP		 4408 } else if (netif_is_ovs_master(upper_dev)) {
4409 if (info->linking)
4410 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4411 else
4412 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
56ade8fe
JP		 4413 }
4414 break;
4415 }
4416
80bedf1a 4417 return err;
56ade8fe
JP		 4418}
4419
74581206
JP		 4420static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4421 unsigned long event, void *ptr)
4422{
4423 struct netdev_notifier_changelowerstate_info *info;
4424 struct mlxsw_sp_port *mlxsw_sp_port;
4425 int err;
4426
4427 mlxsw_sp_port = netdev_priv(dev);
4428 info = ptr;
4429
4430 switch (event) {
4431 case NETDEV_CHANGELOWERSTATE:
4432 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4433 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4434 info->lower_state_info);
4435 if (err)
4436 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4437 }
4438 break;
4439 }
4440
80bedf1a 4441 return 0;
74581206
JP		 4442}
4443
f0cebd81
IS		 4444static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4445 struct net_device *port_dev,
74581206
JP		 4446 unsigned long event, void *ptr)
4447{
4448 switch (event) {
4449 case NETDEV_PRECHANGEUPPER:
4450 case NETDEV_CHANGEUPPER:
f0cebd81
IS		 4451 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4452 event, ptr);
74581206 4453 case NETDEV_CHANGELOWERSTATE:
f0cebd81
IS		 4454 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4455 ptr);
74581206
JP		 4456 }
4457
80bedf1a 4458 return 0;
74581206
JP		 4459}
4460
0d65fc13
JP		 4461static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4462 unsigned long event, void *ptr)
4463{
4464 struct net_device *dev;
4465 struct list_head *iter;
4466 int ret;
4467
4468 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4469 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4470 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4471 ptr);
80bedf1a 4472 if (ret)
0d65fc13
JP		 4473 return ret;
4474 }
4475 }
4476
80bedf1a 4477 return 0;
0d65fc13
JP		 4478}
4479
f0cebd81
IS		 4480static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4481 struct net_device *dev,
4482 unsigned long event, void *ptr,
4483 u16 vid)
26f0e7fb
IS		 4484{
4485 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4486 struct netdev_notifier_changeupper_info *info = ptr;
c1f2c6d0 4487 struct netlink_ext_ack *extack;
26f0e7fb 4488 struct net_device *upper_dev;
80bedf1a 4489 int err = 0;
26f0e7fb 4490
c1f2c6d0
IS		 4491 extack = netdev_notifier_info_to_extack(&info->info);
4492
26f0e7fb
IS		 4493 switch (event) {
4494 case NETDEV_PRECHANGEUPPER:
4495 upper_dev = info->upper_dev;
c1f2c6d0
IS		 4496 if (!netif_is_bridge_master(upper_dev)) {
4497 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
80bedf1a 4498 return -EINVAL;
c1f2c6d0 4499 }
25cc72a3
IS		 4500 if (!info->linking)
4501 break;
c1f2c6d0
IS		 4502 if (netdev_has_any_upper_dev(upper_dev)) {
4503 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4504 return -EINVAL;
c1f2c6d0 4505 }
26f0e7fb
IS		 4506 break;
4507 case NETDEV_CHANGEUPPER:
4508 upper_dev = info->upper_dev;
1f88061e
IS		 4509 if (netif_is_bridge_master(upper_dev)) {
4510 if (info->linking)
c57529e1
IS		 4511 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4512 vlan_dev,
9b63ef88
IS		 4513 upper_dev,
4514 extack);
1f88061e 4515 else
c57529e1
IS		 4516 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4517 vlan_dev,
4518 upper_dev);
26f0e7fb 4519 } else {
1f88061e
IS		 4520 err = -EINVAL;
4521 WARN_ON(1);
26f0e7fb 4522 }
1f88061e 4523 break;
26f0e7fb
IS		 4524 }
4525
80bedf1a 4526 return err;
26f0e7fb
IS		 4527}
4528
f0cebd81
IS		 4529static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4530 struct net_device *lag_dev,
4531 unsigned long event,
4532 void *ptr, u16 vid)
272c4470
IS		 4533{
4534 struct net_device *dev;
4535 struct list_head *iter;
4536 int ret;
4537
4538 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4539 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4540 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4541 event, ptr,
4542 vid);
80bedf1a 4543 if (ret)
272c4470
IS		 4544 return ret;
4545 }
4546 }
4547
80bedf1a 4548 return 0;
272c4470
IS		 4549}
4550
26f0e7fb
IS		 4551static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4552 unsigned long event, void *ptr)
4553{
4554 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4555 u16 vid = vlan_dev_vlan_id(vlan_dev);
4556
272c4470 4557 if (mlxsw_sp_port_dev_check(real_dev))
f0cebd81
IS		 4558 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4559 event, ptr, vid);
272c4470 4560 else if (netif_is_lag_master(real_dev))
f0cebd81
IS		 4561 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4562 real_dev, event,
4563 ptr, vid);
26f0e7fb 4564
80bedf1a 4565 return 0;
26f0e7fb
IS		 4566}
4567
b1e45526
IS		 4568static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4569{
4570 struct netdev_notifier_changeupper_info *info = ptr;
4571
4572 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4573 return false;
4574 return netif_is_l3_master(info->upper_dev);
4575}
4576
0063587d 4577static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
0d65fc13
JP		 4578 unsigned long event, void *ptr)
4579{
4580 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
0063587d 4581 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4582 int err = 0;
0d65fc13 4583
0063587d 4584 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
796ec776
PM		 4585 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4586 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4587 event, ptr);
61481f2f
PM		 4588 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4589 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4590 event, ptr);
0063587d 4591 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
6e095fd4 4592 err = mlxsw_sp_netdevice_router_port_event(dev);
b1e45526
IS		 4593 else if (mlxsw_sp_is_vrf_event(event, ptr))
4594 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6e095fd4 4595 else if (mlxsw_sp_port_dev_check(dev))
f0cebd81 4596 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
80bedf1a
IS		 4597 else if (netif_is_lag_master(dev))
4598 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4599 else if (is_vlan_dev(dev))
4600 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 4601
80bedf1a 4602 return notifier_from_errno(err);
0d65fc13
JP		 4603}
4604
89d5dd2e
DA		 4605static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4606 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4607};
4608
99724c18
IS		 4609static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4610 .notifier_call = mlxsw_sp_inetaddr_event,
89d5dd2e
DA		 4611};
4612
4613static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4614 .notifier_call = mlxsw_sp_inet6addr_valid_event,
99724c18
IS		 4615};
4616
5ea1237f
AS		 4617static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4618 .notifier_call = mlxsw_sp_inet6addr_event,
4619};
4620
1d20d23c
JP		 4621static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4622 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4623 {0, },
4624};
4625
4626static struct pci_driver mlxsw_sp_pci_driver = {
4627 .name = mlxsw_sp_driver_name,
4628 .id_table = mlxsw_sp_pci_id_table,
4629};
4630
56ade8fe
JP		 4631static int __init mlxsw_sp_module_init(void)
4632{
4633 int err;
4634
89d5dd2e 4635 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
99724c18 4636 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4637 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5ea1237f 4638 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
e7322638 4639
56ade8fe
JP		 4640 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4641 if (err)
4642 goto err_core_driver_register;
1d20d23c
JP		 4643
4644 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4645 if (err)
4646 goto err_pci_driver_register;
4647
56ade8fe
JP		 4648 return 0;
4649
1d20d23c
JP		 4650err_pci_driver_register:
4651 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 4652err_core_driver_register:
5ea1237f 4653 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 4654 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
de7d6295 4655 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4656 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 4657 return err;
4658}
4659
4660static void __exit mlxsw_sp_module_exit(void)
4661{
1d20d23c 4662 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 4663 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
5ea1237f 4664 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 4665 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
99724c18 4666 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 4667 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 4668}
4669
4670module_init(mlxsw_sp_module_init);
4671module_exit(mlxsw_sp_module_exit);
4672
4673MODULE_LICENSE("Dual BSD/GPL");
4674MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4675MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 4676MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
6b742199 4677MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);
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