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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
CommitLineData
56ade8fe
JP		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
22a67766
JP		 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
56ade8fe
JP		 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
1d20d23c 40#include <linux/pci.h>
56ade8fe
JP		 41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
7f71eb46 52#include <linux/list.h>
80bedf1a 53#include <linux/notifier.h>
90183b98 54#include <linux/dcbnl.h>
99724c18 55#include <linux/inetdevice.h>
c1f2c6d0 56#include <linux/netlink.h>
56ade8fe 57#include <net/switchdev.h>
763b4b70
YG		 58#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
e7322638 60#include <net/netevent.h>
98d0f7b9 61#include <net/tc_act/tc_sample.h>
5ea1237f 62#include <net/addrconf.h>
56ade8fe
JP		 63
64#include "spectrum.h"
1d20d23c 65#include "pci.h"
56ade8fe
JP		 66#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
ff7b0d27 71#include "spectrum_cnt.h"
230ead01 72#include "spectrum_dpipe.h"
d3b939b8 73#include "spectrum_acl_flex_actions.h"
e5e5c88a 74#include "../mlxfw/mlxfw.h"
56ade8fe 75
6b742199 76#define MLXSW_FWREV_MAJOR 13
2f53fbd5
ST		 77#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
fd5204cd 79#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
6b742199
YG		 80
81#define MLXSW_SP_FW_FILENAME \
a4e1ce24 82 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
6b742199
YG		 83 "." __stringify(MLXSW_FWREV_MINOR) \
84 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
85
56ade8fe
JP		 86static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
87static const char mlxsw_sp_driver_version[] = "1.0";
88
89/* tx_hdr_version
90 * Tx header version.
91 * Must be set to 1.
92 */
93MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
94
95/* tx_hdr_ctl
96 * Packet control type.
97 * 0 - Ethernet control (e.g. EMADs, LACP)
98 * 1 - Ethernet data
99 */
100MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
101
102/* tx_hdr_proto
103 * Packet protocol type. Must be set to 1 (Ethernet).
104 */
105MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
106
107/* tx_hdr_rx_is_router
108 * Packet is sent from the router. Valid for data packets only.
109 */
110MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
111
112/* tx_hdr_fid_valid
113 * Indicates if the 'fid' field is valid and should be used for
114 * forwarding lookup. Valid for data packets only.
115 */
116MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
117
118/* tx_hdr_swid
119 * Switch partition ID. Must be set to 0.
120 */
121MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
122
123/* tx_hdr_control_tclass
124 * Indicates if the packet should use the control TClass and not one
125 * of the data TClasses.
126 */
127MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
128
129/* tx_hdr_etclass
130 * Egress TClass to be used on the egress device on the egress port.
131 */
132MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
133
134/* tx_hdr_port_mid
135 * Destination local port for unicast packets.
136 * Destination multicast ID for multicast packets.
137 *
138 * Control packets are directed to a specific egress port, while data
139 * packets are transmitted through the CPU port (0) into the switch partition,
140 * where forwarding rules are applied.
141 */
142MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
143
144/* tx_hdr_fid
145 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
146 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
147 * Valid for data packets only.
148 */
149MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
150
151/* tx_hdr_type
152 * 0 - Data packets
153 * 6 - Control packets
154 */
155MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
156
e5e5c88a
YG		 157struct mlxsw_sp_mlxfw_dev {
158 struct mlxfw_dev mlxfw_dev;
159 struct mlxsw_sp *mlxsw_sp;
160};
161
162static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
163 u16 component_index, u32 *p_max_size,
164 u8 *p_align_bits, u16 *p_max_write_size)
165{
166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
169 char mcqi_pl[MLXSW_REG_MCQI_LEN];
170 int err;
171
172 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
173 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
174 if (err)
175 return err;
176 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
177 p_max_write_size);
178
179 *p_align_bits = max_t(u8, *p_align_bits, 2);
180 *p_max_write_size = min_t(u16, *p_max_write_size,
181 MLXSW_REG_MCDA_MAX_DATA_LEN);
182 return 0;
183}
184
185static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
186{
187 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
188 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
190 char mcc_pl[MLXSW_REG_MCC_LEN];
191 u8 control_state;
192 int err;
193
194 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
195 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
196 if (err)
197 return err;
198
199 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
200 if (control_state != MLXFW_FSM_STATE_IDLE)
201 return -EBUSY;
202
203 mlxsw_reg_mcc_pack(mcc_pl,
204 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
205 0, *fwhandle, 0);
206 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
207}
208
209static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
210 u32 fwhandle, u16 component_index,
211 u32 component_size)
212{
213 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
214 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
215 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
216 char mcc_pl[MLXSW_REG_MCC_LEN];
217
218 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
219 component_index, fwhandle, component_size);
220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
221}
222
223static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
224 u32 fwhandle, u8 *data, u16 size,
225 u32 offset)
226{
227 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
228 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
229 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
230 char mcda_pl[MLXSW_REG_MCDA_LEN];
231
232 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
233 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
234}
235
236static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
237 u32 fwhandle, u16 component_index)
238{
239 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
240 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
242 char mcc_pl[MLXSW_REG_MCC_LEN];
243
244 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
245 component_index, fwhandle, 0);
246 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
247}
248
249static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
250{
251 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
252 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
254 char mcc_pl[MLXSW_REG_MCC_LEN];
255
256 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
257 fwhandle, 0);
258 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
259}
260
261static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
262 enum mlxfw_fsm_state *fsm_state,
263 enum mlxfw_fsm_state_err *fsm_state_err)
264{
265 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
266 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
268 char mcc_pl[MLXSW_REG_MCC_LEN];
269 u8 control_state;
270 u8 error_code;
271 int err;
272
273 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
274 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
275 if (err)
276 return err;
277
278 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
279 *fsm_state = control_state;
280 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
281 MLXFW_FSM_STATE_ERR_MAX);
282 return 0;
283}
284
285static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
286{
287 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
288 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
289 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
290 char mcc_pl[MLXSW_REG_MCC_LEN];
291
292 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
293 fwhandle, 0);
294 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
295}
296
297static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
298{
299 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
300 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
301 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
302 char mcc_pl[MLXSW_REG_MCC_LEN];
303
304 mlxsw_reg_mcc_pack(mcc_pl,
305 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
306 fwhandle, 0);
307 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
308}
309
310static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
311 .component_query = mlxsw_sp_component_query,
312 .fsm_lock = mlxsw_sp_fsm_lock,
313 .fsm_component_update = mlxsw_sp_fsm_component_update,
314 .fsm_block_download = mlxsw_sp_fsm_block_download,
315 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
316 .fsm_activate = mlxsw_sp_fsm_activate,
317 .fsm_query_state = mlxsw_sp_fsm_query_state,
318 .fsm_cancel = mlxsw_sp_fsm_cancel,
319 .fsm_release = mlxsw_sp_fsm_release
320};
321
ce6ef68f
YG		 322static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
323 const struct firmware *firmware)
324{
325 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
326 .mlxfw_dev = {
327 .ops = &mlxsw_sp_mlxfw_dev_ops,
328 .psid = mlxsw_sp->bus_info->psid,
329 .psid_size = strlen(mlxsw_sp->bus_info->psid),
330 },
331 .mlxsw_sp = mlxsw_sp
332 };
333
334 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
335}
336
6b742199
YG		 337static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
338{
339 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
6b742199
YG		 340 const struct firmware *firmware;
341 int err;
342
fd5204cd
YM		 343 /* Validate driver & FW are compatible */
344 if (rev->major != MLXSW_FWREV_MAJOR) {
345 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
346 rev->major, MLXSW_FWREV_MAJOR);
347 return -EINVAL;
348 }
349 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
350 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
6b742199
YG		 351 return 0;
352
fd5204cd 353 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
6b742199 354 rev->major, rev->minor, rev->subminor);
fd5204cd 355 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
6b742199
YG		 356 MLXSW_SP_FW_FILENAME);
357
358 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
359 mlxsw_sp->bus_info->dev);
360 if (err) {
361 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
362 MLXSW_SP_FW_FILENAME);
363 return err;
364 }
365
ce6ef68f 366 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
6b742199
YG		 367 release_firmware(firmware);
368 return err;
369}
370
1abcbcc2
AS		 371int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
372 unsigned int counter_index, u64 *packets,
373 u64 *bytes)
374{
375 char mgpc_pl[MLXSW_REG_MGPC_LEN];
376 int err;
377
378 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
6bba7e20 379 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 380 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
381 if (err)
382 return err;
7cfcbc75
AS		 383 if (packets)
384 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
385 if (bytes)
386 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
1abcbcc2
AS		 387 return 0;
388}
389
390static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
391 unsigned int counter_index)
392{
393 char mgpc_pl[MLXSW_REG_MGPC_LEN];
394
395 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
6bba7e20 396 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
1abcbcc2
AS		 397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
398}
399
400int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
401 unsigned int *p_counter_index)
402{
403 int err;
404
405 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
406 p_counter_index);
407 if (err)
408 return err;
409 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
410 if (err)
411 goto err_counter_clear;
412 return 0;
413
414err_counter_clear:
415 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
416 *p_counter_index);
417 return err;
418}
419
420void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
421 unsigned int counter_index)
422{
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 counter_index);
425}
426
56ade8fe
JP		 427static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
428 const struct mlxsw_tx_info *tx_info)
429{
430 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
431
432 memset(txhdr, 0, MLXSW_TXHDR_LEN);
433
434 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
435 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
436 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
437 mlxsw_tx_hdr_swid_set(txhdr, 0);
438 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
439 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
440 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
441}
442
fe9ccc78
IS		 443int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
444 u8 state)
445{
446 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
447 enum mlxsw_reg_spms_state spms_state;
448 char *spms_pl;
449 int err;
450
451 switch (state) {
452 case BR_STATE_FORWARDING:
453 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
454 break;
455 case BR_STATE_LEARNING:
456 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
457 break;
458 case BR_STATE_LISTENING: /* fall-through */
459 case BR_STATE_DISABLED: /* fall-through */
460 case BR_STATE_BLOCKING:
461 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
462 break;
463 default:
464 BUG();
465 }
466
467 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
468 if (!spms_pl)
469 return -ENOMEM;
470 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
471 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
472
473 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
474 kfree(spms_pl);
475 return err;
476}
477
56ade8fe
JP		 478static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
479{
5b090740 480 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
56ade8fe
JP		 481 int err;
482
483 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
484 if (err)
485 return err;
486 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
487 return 0;
488}
489
763b4b70
YG		 490static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
491{
763b4b70
YG		 492 int i;
493
c1a38311 494 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
763b4b70
YG		 495 return -EIO;
496
c1a38311
JP		 497 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
498 MAX_SPAN);
763b4b70
YG		 499 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
500 sizeof(struct mlxsw_sp_span_entry),
501 GFP_KERNEL);
502 if (!mlxsw_sp->span.entries)
503 return -ENOMEM;
504
505 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
506 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
507
508 return 0;
509}
510
511static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
512{
513 int i;
514
515 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
516 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
517
518 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
519 }
520 kfree(mlxsw_sp->span.entries);
521}
522
523static struct mlxsw_sp_span_entry *
524mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
525{
526 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
527 struct mlxsw_sp_span_entry *span_entry;
528 char mpat_pl[MLXSW_REG_MPAT_LEN];
529 u8 local_port = port->local_port;
530 int index;
531 int i;
532 int err;
533
534 /* find a free entry to use */
535 index = -1;
536 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
537 if (!mlxsw_sp->span.entries[i].used) {
538 index = i;
539 span_entry = &mlxsw_sp->span.entries[i];
540 break;
541 }
542 }
543 if (index < 0)
544 return NULL;
545
546 /* create a new port analayzer entry for local_port */
547 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
548 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
549 if (err)
550 return NULL;
551
552 span_entry->used = true;
553 span_entry->id = index;
2d644d4c 554 span_entry->ref_count = 1;
763b4b70
YG		 555 span_entry->local_port = local_port;
556 return span_entry;
557}
558
559static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
560 struct mlxsw_sp_span_entry *span_entry)
561{
562 u8 local_port = span_entry->local_port;
563 char mpat_pl[MLXSW_REG_MPAT_LEN];
564 int pa_id = span_entry->id;
565
566 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
567 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
568 span_entry->used = false;
569}
570
5c8d39c9 571struct mlxsw_sp_span_entry *
6399ebcc 572mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
763b4b70 573{
763b4b70
YG		 574 int i;
575
576 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
577 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
578
6399ebcc 579 if (curr->used && curr->local_port == local_port)
763b4b70
YG		 580 return curr;
581 }
582 return NULL;
583}
584
1a9234e6
IS		 585static struct mlxsw_sp_span_entry
586*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
763b4b70
YG		 587{
588 struct mlxsw_sp_span_entry *span_entry;
589
6399ebcc
YM		 590 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
591 port->local_port);
763b4b70 592 if (span_entry) {
2d644d4c 593 /* Already exists, just take a reference */
763b4b70
YG		 594 span_entry->ref_count++;
595 return span_entry;
596 }
597
598 return mlxsw_sp_span_entry_create(port);
599}
600
601static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
602 struct mlxsw_sp_span_entry *span_entry)
603{
2d644d4c 604 WARN_ON(!span_entry->ref_count);
763b4b70
YG		 605 if (--span_entry->ref_count == 0)
606 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
607 return 0;
608}
609
610static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
611{
612 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
613 struct mlxsw_sp_span_inspected_port *p;
614 int i;
615
616 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
617 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
618
619 list_for_each_entry(p, &curr->bound_ports_list, list)
620 if (p->local_port == port->local_port &&
621 p->type == MLXSW_SP_SPAN_EGRESS)
622 return true;
623 }
624
625 return false;
626}
627
18281f2d
IS		 628static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
629 int mtu)
763b4b70 630{
18281f2d 631 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
763b4b70
YG		 632}
633
634static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
635{
636 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
637 char sbib_pl[MLXSW_REG_SBIB_LEN];
638 int err;
639
640 /* If port is egress mirrored, the shared buffer size should be
641 * updated according to the mtu value
642 */
643 if (mlxsw_sp_span_is_egress_mirror(port)) {
18281f2d
IS		 644 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
645
646 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 647 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
648 if (err) {
649 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
650 return err;
651 }
652 }
653
654 return 0;
655}
656
657static struct mlxsw_sp_span_inspected_port *
663f1b26
PM		 658mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_span_entry *span_entry,
659 enum mlxsw_sp_span_type type,
660 struct mlxsw_sp_port *port,
661 bool bind)
763b4b70
YG		 662{
663 struct mlxsw_sp_span_inspected_port *p;
664
665 list_for_each_entry(p, &span_entry->bound_ports_list, list)
663f1b26
PM		 666 if (type == p->type &&
667 port->local_port == p->local_port &&
668 bind == p->bound)
763b4b70
YG		 669 return p;
670 return NULL;
671}
672
673static int
674mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
675 struct mlxsw_sp_span_entry *span_entry,
5c8d39c9
AS		 676 enum mlxsw_sp_span_type type,
677 bool bind)
763b4b70 678{
763b4b70
YG		 679 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
680 char mpar_pl[MLXSW_REG_MPAR_LEN];
763b4b70 681 int pa_id = span_entry->id;
5c8d39c9
AS		 682
683 /* bind the port to the SPAN entry */
684 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
685 (enum mlxsw_reg_mpar_i_e) type, bind, pa_id);
686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
687}
688
689static int
690mlxsw_sp_span_inspected_port_add(struct mlxsw_sp_port *port,
691 struct mlxsw_sp_span_entry *span_entry,
692 enum mlxsw_sp_span_type type,
693 bool bind)
694{
695 struct mlxsw_sp_span_inspected_port *inspected_port;
696 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
697 char sbib_pl[MLXSW_REG_SBIB_LEN];
663f1b26 698 int i;
763b4b70
YG		 699 int err;
700
663f1b26
PM		 701 /* A given (source port, direction) can only be bound to one analyzer,
702 * so if a binding is requested, check for conflicts.
703 */
704 if (bind)
705 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
706 struct mlxsw_sp_span_entry *curr =
707 &mlxsw_sp->span.entries[i];
708
709 if (mlxsw_sp_span_entry_bound_port_find(curr, type,
710 port, bind))
711 return -EEXIST;
712 }
713
763b4b70
YG		 714 /* if it is an egress SPAN, bind a shared buffer to it */
715 if (type == MLXSW_SP_SPAN_EGRESS) {
18281f2d
IS		 716 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
717 port->dev->mtu);
718
719 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
763b4b70
YG		 720 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
721 if (err) {
722 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
723 return err;
724 }
725 }
726
5c8d39c9
AS		 727 if (bind) {
728 err = mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
729 true);
730 if (err)
731 goto err_port_bind;
732 }
763b4b70
YG		 733
734 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
735 if (!inspected_port) {
736 err = -ENOMEM;
737 goto err_inspected_port_alloc;
738 }
739 inspected_port->local_port = port->local_port;
740 inspected_port->type = type;
663f1b26 741 inspected_port->bound = bind;
763b4b70
YG		 742 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
743
744 return 0;
745
763b4b70 746err_inspected_port_alloc:
5c8d39c9
AS		 747 if (bind)
748 mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
749 false);
750err_port_bind:
763b4b70
YG		 751 if (type == MLXSW_SP_SPAN_EGRESS) {
752 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
753 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
754 }
755 return err;
756}
757
758static void
5c8d39c9
AS		 759mlxsw_sp_span_inspected_port_del(struct mlxsw_sp_port *port,
760 struct mlxsw_sp_span_entry *span_entry,
761 enum mlxsw_sp_span_type type,
762 bool bind)
763b4b70
YG		 763{
764 struct mlxsw_sp_span_inspected_port *inspected_port;
765 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
763b4b70 766 char sbib_pl[MLXSW_REG_SBIB_LEN];
763b4b70 767
663f1b26
PM		 768 inspected_port = mlxsw_sp_span_entry_bound_port_find(span_entry, type,
769 port, bind);
763b4b70
YG		 770 if (!inspected_port)
771 return;
772
5c8d39c9
AS		 773 if (bind)
774 mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
775 false);
763b4b70
YG		 776 /* remove the SBIB buffer if it was egress SPAN */
777 if (type == MLXSW_SP_SPAN_EGRESS) {
778 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
779 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
780 }
781
782 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
783
784 list_del(&inspected_port->list);
785 kfree(inspected_port);
786}
787
5c8d39c9
AS		 788int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
789 struct mlxsw_sp_port *to,
790 enum mlxsw_sp_span_type type, bool bind)
763b4b70
YG		 791{
792 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
793 struct mlxsw_sp_span_entry *span_entry;
794 int err;
795
796 span_entry = mlxsw_sp_span_entry_get(to);
797 if (!span_entry)
798 return -ENOENT;
799
800 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
801 span_entry->id);
802
5c8d39c9 803 err = mlxsw_sp_span_inspected_port_add(from, span_entry, type, bind);
763b4b70
YG		 804 if (err)
805 goto err_port_bind;
806
807 return 0;
808
809err_port_bind:
810 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
811 return err;
812}
813
5c8d39c9
AS		 814void mlxsw_sp_span_mirror_del(struct mlxsw_sp_port *from, u8 destination_port,
815 enum mlxsw_sp_span_type type, bool bind)
763b4b70
YG		 816{
817 struct mlxsw_sp_span_entry *span_entry;
818
6399ebcc
YM		 819 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
820 destination_port);
763b4b70
YG		 821 if (!span_entry) {
822 netdev_err(from->dev, "no span entry found\n");
823 return;
824 }
825
826 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
827 span_entry->id);
5c8d39c9 828 mlxsw_sp_span_inspected_port_del(from, span_entry, type, bind);
763b4b70
YG		 829}
830
98d0f7b9
YG		 831static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
832 bool enable, u32 rate)
833{
834 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
835 char mpsc_pl[MLXSW_REG_MPSC_LEN];
836
837 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
838 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
839}
840
56ade8fe
JP		 841static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
842 bool is_up)
843{
844 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
845 char paos_pl[MLXSW_REG_PAOS_LEN];
846
847 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
848 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
849 MLXSW_PORT_ADMIN_STATUS_DOWN);
850 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
851}
852
56ade8fe
JP		 853static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
854 unsigned char *addr)
855{
856 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
857 char ppad_pl[MLXSW_REG_PPAD_LEN];
858
859 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
860 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
861 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
862}
863
864static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
865{
866 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
867 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
868
869 ether_addr_copy(addr, mlxsw_sp->base_mac);
870 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
871 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
872}
873
56ade8fe
JP		 874static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
875{
876 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
877 char pmtu_pl[MLXSW_REG_PMTU_LEN];
878 int max_mtu;
879 int err;
880
881 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
882 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
883 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
884 if (err)
885 return err;
886 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
887
888 if (mtu > max_mtu)
889 return -EINVAL;
890
891 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
892 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
893}
894
be94535f
IS		 895static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
896{
897 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5b153859 898 char pspa_pl[MLXSW_REG_PSPA_LEN];
be94535f 899
5b153859
IS		 900 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
901 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
be94535f
IS		 902}
903
a1107487 904int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
56ade8fe
JP		 905{
906 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
907 char svpe_pl[MLXSW_REG_SVPE_LEN];
908
909 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
910 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
911}
912
7cbc4277
IS		 913int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
914 bool learn_enable)
56ade8fe
JP		 915{
916 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
917 char *spvmlr_pl;
918 int err;
919
920 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
921 if (!spvmlr_pl)
922 return -ENOMEM;
7cbc4277
IS		 923 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
924 learn_enable);
56ade8fe
JP		 925 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
926 kfree(spvmlr_pl);
927 return err;
928}
929
b02eae9b
IS		 930static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
931 u16 vid)
932{
933 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
934 char spvid_pl[MLXSW_REG_SPVID_LEN];
935
936 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
937 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
938}
939
940static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
941 bool allow)
942{
943 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
944 char spaft_pl[MLXSW_REG_SPAFT_LEN];
945
946 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
947 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
948}
949
950int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
951{
952 int err;
953
954 if (!vid) {
955 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
956 if (err)
957 return err;
958 } else {
959 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
960 if (err)
961 return err;
962 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
963 if (err)
964 goto err_port_allow_untagged_set;
965 }
966
967 mlxsw_sp_port->pvid = vid;
968 return 0;
969
970err_port_allow_untagged_set:
971 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
972 return err;
973}
974
56ade8fe
JP		 975static int
976mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
977{
978 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
979 char sspr_pl[MLXSW_REG_SSPR_LEN];
980
981 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
982 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
983}
984
d664b41e
IS		 985static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
986 u8 local_port, u8 *p_module,
987 u8 *p_width, u8 *p_lane)
56ade8fe 988{
56ade8fe
JP		 989 char pmlp_pl[MLXSW_REG_PMLP_LEN];
990 int err;
991
558c2d5e 992 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
56ade8fe
JP		 993 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
994 if (err)
995 return err;
558c2d5e
IS		 996 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
997 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
2bf9a586 998 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
56ade8fe
JP		 999 return 0;
1000}
1001
2e915e0b 1002static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
18f1e70c
IS		 1003 u8 module, u8 width, u8 lane)
1004{
2e915e0b 1005 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
18f1e70c
IS		 1006 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1007 int i;
1008
2e915e0b 1009 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
18f1e70c
IS		 1010 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
1011 for (i = 0; i < width; i++) {
1012 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
1013 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
1014 }
1015
1016 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1017}
1018
2e915e0b 1019static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
3e9b27b8 1020{
2e915e0b 1021 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3e9b27b8
IS		 1022 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1023
2e915e0b 1024 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
3e9b27b8
IS		 1025 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1026 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1027}
1028
56ade8fe
JP		 1029static int mlxsw_sp_port_open(struct net_device *dev)
1030{
1031 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1032 int err;
1033
1034 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1035 if (err)
1036 return err;
1037 netif_start_queue(dev);
1038 return 0;
1039}
1040
1041static int mlxsw_sp_port_stop(struct net_device *dev)
1042{
1043 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1044
1045 netif_stop_queue(dev);
1046 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1047}
1048
1049static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1050 struct net_device *dev)
1051{
1052 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1053 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1054 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1055 const struct mlxsw_tx_info tx_info = {
1056 .local_port = mlxsw_sp_port->local_port,
1057 .is_emad = false,
1058 };
1059 u64 len;
1060 int err;
1061
307c2431 1062 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
56ade8fe
JP		 1063 return NETDEV_TX_BUSY;
1064
1065 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1066 struct sk_buff *skb_orig = skb;
1067
1068 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1069 if (!skb) {
1070 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1071 dev_kfree_skb_any(skb_orig);
1072 return NETDEV_TX_OK;
1073 }
36bf38d1 1074 dev_consume_skb_any(skb_orig);
56ade8fe
JP		 1075 }
1076
1077 if (eth_skb_pad(skb)) {
1078 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1079 return NETDEV_TX_OK;
1080 }
1081
1082 mlxsw_sp_txhdr_construct(skb, &tx_info);
63dcdd35
NF		 1083 /* TX header is consumed by HW on the way so we shouldn't count its
1084 * bytes as being sent.
1085 */
1086 len = skb->len - MLXSW_TXHDR_LEN;
1087
56ade8fe
JP		 1088 /* Due to a race we might fail here because of a full queue. In that
1089 * unlikely case we simply drop the packet.
1090 */
307c2431 1091 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
56ade8fe
JP		 1092
1093 if (!err) {
1094 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1095 u64_stats_update_begin(&pcpu_stats->syncp);
1096 pcpu_stats->tx_packets++;
1097 pcpu_stats->tx_bytes += len;
1098 u64_stats_update_end(&pcpu_stats->syncp);
1099 } else {
1100 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1101 dev_kfree_skb_any(skb);
1102 }
1103 return NETDEV_TX_OK;
1104}
1105
c5b9b518
JP		 1106static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1107{
1108}
1109
56ade8fe
JP		 1110static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1111{
1112 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1113 struct sockaddr *addr = p;
1114 int err;
1115
1116 if (!is_valid_ether_addr(addr->sa_data))
1117 return -EADDRNOTAVAIL;
1118
1119 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1120 if (err)
1121 return err;
1122 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1123 return 0;
1124}
1125
18281f2d
IS		 1126static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1127 int mtu)
ff6551ec 1128{
18281f2d 1129 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
f417f04d 1130}
8e8dfe9f 1131
f417f04d 1132#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
18281f2d
IS		 1133
1134static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1135 u16 delay)
f417f04d 1136{
18281f2d
IS		 1137 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1138 BITS_PER_BYTE));
1139 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1140 mtu);
f417f04d
IS		 1141}
1142
18281f2d 1143/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
f417f04d
IS		 1144 * Assumes 100m cable and maximum MTU.
1145 */
18281f2d
IS		 1146#define MLXSW_SP_PAUSE_DELAY 58752
1147
1148static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1149 u16 delay, bool pfc, bool pause)
f417f04d
IS		 1150{
1151 if (pfc)
18281f2d 1152 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
f417f04d 1153 else if (pause)
18281f2d 1154 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
f417f04d
IS		 1155 else
1156 return 0;
1157}
9f7ec052 1158
f417f04d
IS		 1159static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1160 bool lossy)
1161{
1162 if (lossy)
1163 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
d81a6bdb 1164 else
f417f04d
IS		 1165 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1166 thres);
8e8dfe9f
IS		 1167}
1168
1169int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
d81a6bdb
IS		 1170 u8 *prio_tc, bool pause_en,
1171 struct ieee_pfc *my_pfc)
8e8dfe9f
IS		 1172{
1173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
d81a6bdb
IS		 1174 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1175 u16 delay = !!my_pfc ? my_pfc->delay : 0;
ff6551ec 1176 char pbmc_pl[MLXSW_REG_PBMC_LEN];
8e8dfe9f 1177 int i, j, err;
ff6551ec
IS		 1178
1179 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1180 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1181 if (err)
1182 return err;
8e8dfe9f
IS		 1183
1184 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1185 bool configure = false;
d81a6bdb 1186 bool pfc = false;
f417f04d
IS		 1187 bool lossy;
1188 u16 thres;
8e8dfe9f
IS		 1189
1190 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1191 if (prio_tc[j] == i) {
d81a6bdb 1192 pfc = pfc_en & BIT(j);
8e8dfe9f
IS		 1193 configure = true;
1194 break;
1195 }
1196 }
1197
1198 if (!configure)
1199 continue;
f417f04d
IS		 1200
1201 lossy = !(pfc || pause_en);
18281f2d
IS		 1202 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1203 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1204 pause_en);
f417f04d 1205 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
8e8dfe9f
IS		 1206 }
1207
ff6551ec
IS		 1208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1209}
1210
8e8dfe9f 1211static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
9f7ec052 1212 int mtu, bool pause_en)
8e8dfe9f
IS		 1213{
1214 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1215 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
d81a6bdb 1216 struct ieee_pfc *my_pfc;
8e8dfe9f
IS		 1217 u8 *prio_tc;
1218
1219 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
d81a6bdb 1220 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
8e8dfe9f 1221
9f7ec052 1222 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
d81a6bdb 1223 pause_en, my_pfc);
8e8dfe9f
IS		 1224}
1225
56ade8fe
JP		 1226static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1227{
1228 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
9f7ec052 1229 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
56ade8fe
JP		 1230 int err;
1231
9f7ec052 1232 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
56ade8fe
JP		 1233 if (err)
1234 return err;
763b4b70
YG		 1235 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1236 if (err)
1237 goto err_span_port_mtu_update;
ff6551ec
IS		 1238 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1239 if (err)
1240 goto err_port_mtu_set;
56ade8fe
JP		 1241 dev->mtu = mtu;
1242 return 0;
ff6551ec
IS		 1243
1244err_port_mtu_set:
763b4b70
YG		 1245 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1246err_span_port_mtu_update:
9f7ec052 1247 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
ff6551ec 1248 return err;
56ade8fe
JP		 1249}
1250
4bdcc6ca 1251static int
fc1bbb0f
NF		 1252mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1253 struct rtnl_link_stats64 *stats)
56ade8fe
JP		 1254{
1255 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1256 struct mlxsw_sp_port_pcpu_stats *p;
1257 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1258 u32 tx_dropped = 0;
1259 unsigned int start;
1260 int i;
1261
1262 for_each_possible_cpu(i) {
1263 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1264 do {
1265 start = u64_stats_fetch_begin_irq(&p->syncp);
1266 rx_packets = p->rx_packets;
1267 rx_bytes = p->rx_bytes;
1268 tx_packets = p->tx_packets;
1269 tx_bytes = p->tx_bytes;
1270 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1271
1272 stats->rx_packets += rx_packets;
1273 stats->rx_bytes += rx_bytes;
1274 stats->tx_packets += tx_packets;
1275 stats->tx_bytes += tx_bytes;
1276 /* tx_dropped is u32, updated without syncp protection. */
1277 tx_dropped += p->tx_dropped;
1278 }
1279 stats->tx_dropped = tx_dropped;
fc1bbb0f
NF		 1280 return 0;
1281}
1282
3df5b3c6 1283static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
fc1bbb0f
NF		 1284{
1285 switch (attr_id) {
1286 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1287 return true;
1288 }
1289
1290 return false;
1291}
1292
4bdcc6ca
OG		 1293static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1294 void *sp)
fc1bbb0f
NF		 1295{
1296 switch (attr_id) {
1297 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1298 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1299 }
1300
1301 return -EINVAL;
1302}
1303
1304static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1305 int prio, char *ppcnt_pl)
1306{
1307 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1308 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1309
1310 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1311 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1312}
1313
1314static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1315 struct rtnl_link_stats64 *stats)
1316{
1317 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1318 int err;
1319
1320 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1321 0, ppcnt_pl);
1322 if (err)
1323 goto out;
1324
1325 stats->tx_packets =
1326 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1327 stats->rx_packets =
1328 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1329 stats->tx_bytes =
1330 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1331 stats->rx_bytes =
1332 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1333 stats->multicast =
1334 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1335
1336 stats->rx_crc_errors =
1337 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1338 stats->rx_frame_errors =
1339 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1340
1341 stats->rx_length_errors = (
1342 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1343 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1344 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1345
1346 stats->rx_errors = (stats->rx_crc_errors +
1347 stats->rx_frame_errors + stats->rx_length_errors);
1348
1349out:
1350 return err;
1351}
1352
075ab8ad
NF		 1353static void
1354mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1355 struct mlxsw_sp_port_xstats *xstats)
1356{
1357 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1358 int err, i;
1359
1360 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1361 ppcnt_pl);
1362 if (!err)
1363 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1364
1365 for (i = 0; i < TC_MAX_QUEUE; i++) {
1366 err = mlxsw_sp_port_get_stats_raw(dev,
1367 MLXSW_REG_PPCNT_TC_CONG_TC,
1368 i, ppcnt_pl);
1369 if (!err)
1370 xstats->wred_drop[i] =
1371 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1372
1373 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1374 i, ppcnt_pl);
1375 if (err)
1376 continue;
1377
1378 xstats->backlog[i] =
1379 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1380 xstats->tail_drop[i] =
1381 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1382 }
1383}
1384
fc1bbb0f
NF		 1385static void update_stats_cache(struct work_struct *work)
1386{
1387 struct mlxsw_sp_port *mlxsw_sp_port =
1388 container_of(work, struct mlxsw_sp_port,
9deef43d 1389 periodic_hw_stats.update_dw.work);
fc1bbb0f
NF		 1390
1391 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1392 goto out;
1393
1394 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
9deef43d 1395 &mlxsw_sp_port->periodic_hw_stats.stats);
075ab8ad
NF		 1396 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1397 &mlxsw_sp_port->periodic_hw_stats.xstats);
fc1bbb0f
NF		 1398
1399out:
9deef43d 1400 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 1401 MLXSW_HW_STATS_UPDATE_TIME);
1402}
1403
1404/* Return the stats from a cache that is updated periodically,
1405 * as this function might get called in an atomic context.
1406 */
bc1f4470 1407static void
fc1bbb0f
NF		 1408mlxsw_sp_port_get_stats64(struct net_device *dev,
1409 struct rtnl_link_stats64 *stats)
1410{
1411 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1412
9deef43d 1413 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
56ade8fe
JP		 1414}
1415
93cd0813
JP		 1416static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1417 u16 vid_begin, u16 vid_end,
1418 bool is_member, bool untagged)
56ade8fe
JP		 1419{
1420 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1421 char *spvm_pl;
1422 int err;
1423
1424 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1425 if (!spvm_pl)
1426 return -ENOMEM;
1427
1428 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1429 vid_end, is_member, untagged);
1430 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1431 kfree(spvm_pl);
1432 return err;
1433}
1434
93cd0813
JP		 1435int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1436 u16 vid_end, bool is_member, bool untagged)
1437{
1438 u16 vid, vid_e;
1439 int err;
1440
1441 for (vid = vid_begin; vid <= vid_end;
1442 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1443 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1444 vid_end);
1445
1446 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1447 is_member, untagged);
1448 if (err)
1449 return err;
1450 }
1451
1452 return 0;
1453}
1454
c57529e1 1455static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
7f71eb46 1456{
c57529e1 1457 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
7f71eb46 1458
c57529e1
IS		 1459 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1460 &mlxsw_sp_port->vlans_list, list)
1461 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
7f71eb46
IS		 1462}
1463
31a08a52
IS		 1464static struct mlxsw_sp_port_vlan *
1465mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1466{
1467 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
c57529e1
IS		 1468 bool untagged = vid == 1;
1469 int err;
1470
1471 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1472 if (err)
1473 return ERR_PTR(err);
31a08a52
IS		 1474
1475 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
c57529e1
IS		 1476 if (!mlxsw_sp_port_vlan) {
1477 err = -ENOMEM;
1478 goto err_port_vlan_alloc;
1479 }
31a08a52
IS		 1480
1481 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
b3529af6 1482 mlxsw_sp_port_vlan->ref_count = 1;
31a08a52
IS		 1483 mlxsw_sp_port_vlan->vid = vid;
1484 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1485
1486 return mlxsw_sp_port_vlan;
c57529e1
IS		 1487
1488err_port_vlan_alloc:
1489 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1490 return ERR_PTR(err);
31a08a52
IS		 1491}
1492
1493static void
1494mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1495{
c57529e1
IS		 1496 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1497 u16 vid = mlxsw_sp_port_vlan->vid;
7cbecf24 1498
31a08a52
IS		 1499 list_del(&mlxsw_sp_port_vlan->list);
1500 kfree(mlxsw_sp_port_vlan);
c57529e1
IS		 1501 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1502}
1503
1504struct mlxsw_sp_port_vlan *
1505mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1506{
1507 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1508
1509 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
b3529af6
IS		 1510 if (mlxsw_sp_port_vlan) {
1511 mlxsw_sp_port_vlan->ref_count++;
c57529e1 1512 return mlxsw_sp_port_vlan;
b3529af6 1513 }
c57529e1
IS		 1514
1515 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1516}
1517
1518void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1519{
a1107487
IS		 1520 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1521
b3529af6
IS		 1522 if (--mlxsw_sp_port_vlan->ref_count != 0)
1523 return;
1524
c57529e1
IS		 1525 if (mlxsw_sp_port_vlan->bridge_port)
1526 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
a1107487
IS		 1527 else if (fid)
1528 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
c57529e1
IS		 1529
1530 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
31a08a52
IS		 1531}
1532
05978481
IS		 1533static int mlxsw_sp_port_add_vid(struct net_device *dev,
1534 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1535{
1536 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
56ade8fe
JP		 1537
1538 /* VLAN 0 is added to HW filter when device goes up, but it is
1539 * reserved in our case, so simply return.
1540 */
1541 if (!vid)
1542 return 0;
1543
c57529e1 1544 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
56ade8fe
JP		 1545}
1546
32d863fb
IS		 1547static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1548 __be16 __always_unused proto, u16 vid)
56ade8fe
JP		 1549{
1550 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
31a08a52 1551 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 1552
1553 /* VLAN 0 is removed from HW filter when device goes down, but
1554 * it is reserved in our case, so simply return.
1555 */
1556 if (!vid)
1557 return 0;
1558
31a08a52 1559 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
c57529e1 1560 if (!mlxsw_sp_port_vlan)
56ade8fe 1561 return 0;
c57529e1 1562 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
31a08a52 1563
56ade8fe
JP		 1564 return 0;
1565}
1566
2bf9a586
IS		 1567static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1568 size_t len)
1569{
1570 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
d664b41e
IS		 1571 u8 module = mlxsw_sp_port->mapping.module;
1572 u8 width = mlxsw_sp_port->mapping.width;
1573 u8 lane = mlxsw_sp_port->mapping.lane;
2bf9a586
IS		 1574 int err;
1575
2bf9a586
IS		 1576 if (!mlxsw_sp_port->split)
1577 err = snprintf(name, len, "p%d", module + 1);
1578 else
1579 err = snprintf(name, len, "p%ds%d", module + 1,
1580 lane / width);
1581
1582 if (err >= len)
1583 return -EINVAL;
1584
1585 return 0;
1586}
1587
763b4b70 1588static struct mlxsw_sp_port_mall_tc_entry *
65acb5d0
YG		 1589mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1590 unsigned long cookie) {
763b4b70
YG		 1591 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1592
1593 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1594 if (mall_tc_entry->cookie == cookie)
1595 return mall_tc_entry;
1596
1597 return NULL;
1598}
1599
1600static int
1601mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
65acb5d0 1602 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
763b4b70
YG		 1603 const struct tc_action *a,
1604 bool ingress)
1605{
763b4b70
YG		 1606 enum mlxsw_sp_span_type span_type;
1607 struct mlxsw_sp_port *to_port;
1608 struct net_device *to_dev;
763b4b70 1609
9f8a739e 1610 to_dev = tcf_mirred_dev(a);
763b4b70
YG		 1611 if (!to_dev) {
1612 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1613 return -EINVAL;
1614 }
1615
1616 if (!mlxsw_sp_port_dev_check(to_dev)) {
1617 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
e915ac68 1618 return -EOPNOTSUPP;
763b4b70
YG		 1619 }
1620 to_port = netdev_priv(to_dev);
1621
65acb5d0
YG		 1622 mirror->to_local_port = to_port->local_port;
1623 mirror->ingress = ingress;
763b4b70 1624 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
5c8d39c9
AS		 1625 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type,
1626 true);
65acb5d0 1627}
763b4b70 1628
65acb5d0
YG		 1629static void
1630mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1631 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1632{
65acb5d0 1633 enum mlxsw_sp_span_type span_type;
65acb5d0 1634
65acb5d0
YG		 1635 span_type = mirror->ingress ?
1636 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
5c8d39c9
AS		 1637 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->to_local_port,
1638 span_type, true);
763b4b70
YG		 1639}
1640
98d0f7b9
YG		 1641static int
1642mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1643 struct tc_cls_matchall_offload *cls,
1644 const struct tc_action *a,
1645 bool ingress)
1646{
1647 int err;
1648
1649 if (!mlxsw_sp_port->sample)
1650 return -EOPNOTSUPP;
1651 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1652 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1653 return -EEXIST;
1654 }
1655 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1656 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1657 return -EOPNOTSUPP;
1658 }
1659
1660 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1661 tcf_sample_psample_group(a));
1662 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1663 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1664 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1665
1666 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1667 if (err)
1668 goto err_port_sample_set;
1669 return 0;
1670
1671err_port_sample_set:
1672 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1673 return err;
1674}
1675
1676static void
1677mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1678{
1679 if (!mlxsw_sp_port->sample)
1680 return;
1681
1682 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1683 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1684}
1685
763b4b70 1686static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1687 struct tc_cls_matchall_offload *f,
763b4b70
YG		 1688 bool ingress)
1689{
65acb5d0 1690 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
5fd9fc4e 1691 __be16 protocol = f->common.protocol;
763b4b70 1692 const struct tc_action *a;
22dc13c8 1693 LIST_HEAD(actions);
763b4b70
YG		 1694 int err;
1695
9cbf14ed 1696 if (!tcf_exts_has_one_action(f->exts)) {
763b4b70 1697 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
e915ac68 1698 return -EOPNOTSUPP;
763b4b70
YG		 1699 }
1700
65acb5d0
YG		 1701 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1702 if (!mall_tc_entry)
1703 return -ENOMEM;
9cbf14ed 1704 mall_tc_entry->cookie = f->cookie;
65acb5d0 1705
9cbf14ed 1706 tcf_exts_to_list(f->exts, &actions);
65acb5d0 1707 a = list_first_entry(&actions, struct tc_action, list);
86cb13e4 1708
65acb5d0
YG		 1709 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1710 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1711
1712 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1713 mirror = &mall_tc_entry->mirror;
1714 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1715 mirror, a, ingress);
98d0f7b9
YG		 1716 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1717 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
9cbf14ed 1718 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
98d0f7b9 1719 a, ingress);
65acb5d0
YG		 1720 } else {
1721 err = -EOPNOTSUPP;
763b4b70
YG		 1722 }
1723
65acb5d0
YG		 1724 if (err)
1725 goto err_add_action;
1726
1727 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
763b4b70 1728 return 0;
65acb5d0
YG		 1729
1730err_add_action:
1731 kfree(mall_tc_entry);
1732 return err;
763b4b70
YG		 1733}
1734
1735static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
9cbf14ed 1736 struct tc_cls_matchall_offload *f)
763b4b70 1737{
763b4b70 1738 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
763b4b70 1739
65acb5d0 1740 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
9cbf14ed 1741 f->cookie);
763b4b70
YG		 1742 if (!mall_tc_entry) {
1743 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1744 return;
1745 }
65acb5d0 1746 list_del(&mall_tc_entry->list);
763b4b70
YG		 1747
1748 switch (mall_tc_entry->type) {
1749 case MLXSW_SP_PORT_MALL_MIRROR:
65acb5d0
YG		 1750 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1751 &mall_tc_entry->mirror);
763b4b70 1752 break;
98d0f7b9
YG		 1753 case MLXSW_SP_PORT_MALL_SAMPLE:
1754 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1755 break;
763b4b70
YG		 1756 default:
1757 WARN_ON(1);
1758 }
1759
763b4b70
YG		 1760 kfree(mall_tc_entry);
1761}
1762
fd33f1df 1763static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
eb49cfaa
JP		 1764 struct tc_cls_matchall_offload *f,
1765 bool ingress)
fd33f1df 1766{
fd33f1df
JP		 1767 switch (f->command) {
1768 case TC_CLSMATCHALL_REPLACE:
5fd9fc4e 1769 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
fd33f1df
JP		 1770 ingress);
1771 case TC_CLSMATCHALL_DESTROY:
1772 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1773 return 0;
1774 default:
1775 return -EOPNOTSUPP;
1776 }
1777}
1778
1779static int
3aaff323
JP		 1780mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1781 struct tc_cls_flower_offload *f)
763b4b70 1782{
3aaff323
JP		 1783 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1784
fd33f1df
JP		 1785 switch (f->command) {
1786 case TC_CLSFLOWER_REPLACE:
3aaff323 1787 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
fd33f1df 1788 case TC_CLSFLOWER_DESTROY:
3aaff323 1789 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
fd33f1df
JP		 1790 return 0;
1791 case TC_CLSFLOWER_STATS:
3aaff323 1792 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
fd33f1df
JP		 1793 default:
1794 return -EOPNOTSUPP;
1795 }
1796}
1797
3aaff323
JP		 1798static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1799 void *type_data,
1800 void *cb_priv, bool ingress)
eb49cfaa
JP		 1801{
1802 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1803
1804 switch (type) {
1805 case TC_SETUP_CLSMATCHALL:
15f4edb3
JK		 1806 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1807 type_data))
3aaff323
JP		 1808 return -EOPNOTSUPP;
1809
eb49cfaa
JP		 1810 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1811 ingress);
1812 case TC_SETUP_CLSFLOWER:
3aaff323 1813 return 0;
eb49cfaa
JP		 1814 default:
1815 return -EOPNOTSUPP;
1816 }
1817}
1818
3aaff323
JP		 1819static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1820 void *type_data,
1821 void *cb_priv)
1822{
1823 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1824 cb_priv, true);
1825}
1826
1827static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1828 void *type_data,
1829 void *cb_priv)
eb49cfaa 1830{
3aaff323
JP		 1831 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1832 cb_priv, false);
eb49cfaa
JP		 1833}
1834
3aaff323
JP		 1835static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1836 void *type_data, void *cb_priv)
eb49cfaa 1837{
3aaff323
JP		 1838 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1839
1840 switch (type) {
1841 case TC_SETUP_CLSMATCHALL:
1842 return 0;
1843 case TC_SETUP_CLSFLOWER:
1844 if (mlxsw_sp_acl_block_disabled(acl_block))
1845 return -EOPNOTSUPP;
1846
1847 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1848 default:
1849 return -EOPNOTSUPP;
1850 }
1851}
1852
1853static int
1854mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1855 struct tcf_block *block, bool ingress)
1856{
1857 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1858 struct mlxsw_sp_acl_block *acl_block;
1859 struct tcf_block_cb *block_cb;
1860 int err;
1861
1862 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1863 mlxsw_sp);
1864 if (!block_cb) {
1865 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1866 if (!acl_block)
1867 return -ENOMEM;
1868 block_cb = __tcf_block_cb_register(block,
1869 mlxsw_sp_setup_tc_block_cb_flower,
1870 mlxsw_sp, acl_block);
1871 if (IS_ERR(block_cb)) {
1872 err = PTR_ERR(block_cb);
1873 goto err_cb_register;
1874 }
1875 } else {
1876 acl_block = tcf_block_cb_priv(block_cb);
1877 }
1878 tcf_block_cb_incref(block_cb);
1879 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1880 mlxsw_sp_port, ingress);
1881 if (err)
1882 goto err_block_bind;
1883
1884 if (ingress)
1885 mlxsw_sp_port->ing_acl_block = acl_block;
1886 else
1887 mlxsw_sp_port->eg_acl_block = acl_block;
1888
1889 return 0;
1890
1891err_block_bind:
1892 if (!tcf_block_cb_decref(block_cb)) {
1893 __tcf_block_cb_unregister(block_cb);
1894err_cb_register:
1895 mlxsw_sp_acl_block_destroy(acl_block);
1896 }
1897 return err;
1898}
1899
1900static void
1901mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1902 struct tcf_block *block, bool ingress)
1903{
1904 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1905 struct mlxsw_sp_acl_block *acl_block;
1906 struct tcf_block_cb *block_cb;
1907 int err;
1908
1909 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1910 mlxsw_sp);
1911 if (!block_cb)
1912 return;
1913
1914 if (ingress)
1915 mlxsw_sp_port->ing_acl_block = NULL;
1916 else
1917 mlxsw_sp_port->eg_acl_block = NULL;
1918
1919 acl_block = tcf_block_cb_priv(block_cb);
1920 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1921 mlxsw_sp_port, ingress);
1922 if (!err && !tcf_block_cb_decref(block_cb)) {
1923 __tcf_block_cb_unregister(block_cb);
1924 mlxsw_sp_acl_block_destroy(acl_block);
1925 }
eb49cfaa
JP		 1926}
1927
1928static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1929 struct tc_block_offload *f)
1930{
1931 tc_setup_cb_t *cb;
3aaff323
JP		 1932 bool ingress;
1933 int err;
eb49cfaa 1934
3aaff323
JP		 1935 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1936 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1937 ingress = true;
1938 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1939 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1940 ingress = false;
1941 } else {
eb49cfaa 1942 return -EOPNOTSUPP;
3aaff323 1943 }
eb49cfaa
JP		 1944
1945 switch (f->command) {
1946 case TC_BLOCK_BIND:
3aaff323
JP		 1947 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1948 mlxsw_sp_port);
1949 if (err)
1950 return err;
1951 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1952 f->block, ingress);
1953 if (err) {
1954 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1955 return err;
1956 }
1957 return 0;
eb49cfaa 1958 case TC_BLOCK_UNBIND:
3aaff323
JP		 1959 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1960 f->block, ingress);
eb49cfaa
JP		 1961 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1962 return 0;
1963 default:
1964 return -EOPNOTSUPP;
1965 }
1966}
1967
fd33f1df 1968static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1969 void *type_data)
fd33f1df
JP		 1970{
1971 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1972
2572ac53 1973 switch (type) {
eb49cfaa
JP		 1974 case TC_SETUP_BLOCK:
1975 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
96f17e07
NF		 1976 case TC_SETUP_QDISC_RED:
1977 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
46a3615b
NF		 1978 case TC_SETUP_QDISC_PRIO:
1979 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
2572ac53
JP		 1980 default:
1981 return -EOPNOTSUPP;
763b4b70 1982 }
763b4b70
YG		 1983}
1984
9454d930
JP		 1985
1986static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1987{
1988 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1989
3aaff323
JP		 1990 if (!enable) {
1991 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1992 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1993 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1994 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1995 return -EINVAL;
1996 }
1997 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1998 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1999 } else {
2000 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
2001 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
9454d930
JP		 2002 }
2003 return 0;
2004}
2005
2006typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
2007
2008static int mlxsw_sp_handle_feature(struct net_device *dev,
2009 netdev_features_t wanted_features,
2010 netdev_features_t feature,
2011 mlxsw_sp_feature_handler feature_handler)
2012{
2013 netdev_features_t changes = wanted_features ^ dev->features;
2014 bool enable = !!(wanted_features & feature);
2015 int err;
2016
2017 if (!(changes & feature))
2018 return 0;
2019
2020 err = feature_handler(dev, enable);
2021 if (err) {
2022 netdev_err(dev, "%s feature %pNF failed, err %d\n",
2023 enable ? "Enable" : "Disable", &feature, err);
2024 return err;
2025 }
2026
2027 if (enable)
2028 dev->features |= feature;
2029 else
2030 dev->features &= ~feature;
2031
2032 return 0;
2033}
2034static int mlxsw_sp_set_features(struct net_device *dev,
2035 netdev_features_t features)
2036{
2037 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
2038 mlxsw_sp_feature_hw_tc);
2039}
2040
56ade8fe
JP		 2041static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
2042 .ndo_open = mlxsw_sp_port_open,
2043 .ndo_stop = mlxsw_sp_port_stop,
2044 .ndo_start_xmit = mlxsw_sp_port_xmit,
763b4b70 2045 .ndo_setup_tc = mlxsw_sp_setup_tc,
c5b9b518 2046 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
56ade8fe
JP		 2047 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
2048 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
2049 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
fc1bbb0f
NF		 2050 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
2051 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
56ade8fe
JP		 2052 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
2053 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
2bf9a586 2054 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
9454d930 2055 .ndo_set_features = mlxsw_sp_set_features,
56ade8fe
JP		 2056};
2057
2058static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
2059 struct ethtool_drvinfo *drvinfo)
2060{
2061 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2062 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2063
2064 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
2065 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
2066 sizeof(drvinfo->version));
2067 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
2068 "%d.%d.%d",
2069 mlxsw_sp->bus_info->fw_rev.major,
2070 mlxsw_sp->bus_info->fw_rev.minor,
2071 mlxsw_sp->bus_info->fw_rev.subminor);
2072 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
2073 sizeof(drvinfo->bus_info));
2074}
2075
9f7ec052
IS		 2076static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
2077 struct ethtool_pauseparam *pause)
2078{
2079 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2080
2081 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
2082 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
2083}
2084
2085static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
2086 struct ethtool_pauseparam *pause)
2087{
2088 char pfcc_pl[MLXSW_REG_PFCC_LEN];
2089
2090 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
2091 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
2092 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
2093
2094 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
2095 pfcc_pl);
2096}
2097
2098static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
2099 struct ethtool_pauseparam *pause)
2100{
2101 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2102 bool pause_en = pause->tx_pause || pause->rx_pause;
2103 int err;
2104
d81a6bdb
IS		 2105 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
2106 netdev_err(dev, "PFC already enabled on port\n");
2107 return -EINVAL;
2108 }
2109
9f7ec052
IS		 2110 if (pause->autoneg) {
2111 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
2112 return -EINVAL;
2113 }
2114
2115 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2116 if (err) {
2117 netdev_err(dev, "Failed to configure port's headroom\n");
2118 return err;
2119 }
2120
2121 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
2122 if (err) {
2123 netdev_err(dev, "Failed to set PAUSE parameters\n");
2124 goto err_port_pause_configure;
2125 }
2126
2127 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
2128 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2129
2130 return 0;
2131
2132err_port_pause_configure:
2133 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2134 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2135 return err;
2136}
2137
56ade8fe
JP		 2138struct mlxsw_sp_port_hw_stats {
2139 char str[ETH_GSTRING_LEN];
412791df 2140 u64 (*getter)(const char *payload);
18281f2d 2141 bool cells_bytes;
56ade8fe
JP		 2142};
2143
7ed674bc 2144static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
56ade8fe
JP		 2145 {
2146 .str = "a_frames_transmitted_ok",
2147 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2148 },
2149 {
2150 .str = "a_frames_received_ok",
2151 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2152 },
2153 {
2154 .str = "a_frame_check_sequence_errors",
2155 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2156 },
2157 {
2158 .str = "a_alignment_errors",
2159 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2160 },
2161 {
2162 .str = "a_octets_transmitted_ok",
2163 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2164 },
2165 {
2166 .str = "a_octets_received_ok",
2167 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2168 },
2169 {
2170 .str = "a_multicast_frames_xmitted_ok",
2171 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2172 },
2173 {
2174 .str = "a_broadcast_frames_xmitted_ok",
2175 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2176 },
2177 {
2178 .str = "a_multicast_frames_received_ok",
2179 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2180 },
2181 {
2182 .str = "a_broadcast_frames_received_ok",
2183 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2184 },
2185 {
2186 .str = "a_in_range_length_errors",
2187 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2188 },
2189 {
2190 .str = "a_out_of_range_length_field",
2191 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2192 },
2193 {
2194 .str = "a_frame_too_long_errors",
2195 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2196 },
2197 {
2198 .str = "a_symbol_error_during_carrier",
2199 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2200 },
2201 {
2202 .str = "a_mac_control_frames_transmitted",
2203 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2204 },
2205 {
2206 .str = "a_mac_control_frames_received",
2207 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2208 },
2209 {
2210 .str = "a_unsupported_opcodes_received",
2211 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2212 },
2213 {
2214 .str = "a_pause_mac_ctrl_frames_received",
2215 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2216 },
2217 {
2218 .str = "a_pause_mac_ctrl_frames_xmitted",
2219 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2220 },
2221};
2222
2223#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2224
7ed674bc
IS		 2225static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2226 {
2227 .str = "rx_octets_prio",
2228 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2229 },
2230 {
2231 .str = "rx_frames_prio",
2232 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2233 },
2234 {
2235 .str = "tx_octets_prio",
2236 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2237 },
2238 {
2239 .str = "tx_frames_prio",
2240 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2241 },
2242 {
2243 .str = "rx_pause_prio",
2244 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2245 },
2246 {
2247 .str = "rx_pause_duration_prio",
2248 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2249 },
2250 {
2251 .str = "tx_pause_prio",
2252 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2253 },
2254 {
2255 .str = "tx_pause_duration_prio",
2256 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2257 },
2258};
2259
2260#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2261
df4750e8
IS		 2262static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2263 {
2264 .str = "tc_transmit_queue_tc",
18281f2d
IS		 2265 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2266 .cells_bytes = true,
df4750e8
IS		 2267 },
2268 {
2269 .str = "tc_no_buffer_discard_uc_tc",
2270 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2271 },
2272};
2273
2274#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2275
7ed674bc 2276#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
df4750e8
IS		 2277 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2278 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
7ed674bc
IS		 2279 IEEE_8021QAZ_MAX_TCS)
2280
2281static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2282{
2283 int i;
2284
2285 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2286 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2287 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2288 *p += ETH_GSTRING_LEN;
2289 }
2290}
2291
df4750e8
IS		 2292static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2293{
2294 int i;
2295
2296 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2297 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2298 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2299 *p += ETH_GSTRING_LEN;
2300 }
2301}
2302
56ade8fe
JP		 2303static void mlxsw_sp_port_get_strings(struct net_device *dev,
2304 u32 stringset, u8 *data)
2305{
2306 u8 *p = data;
2307 int i;
2308
2309 switch (stringset) {
2310 case ETH_SS_STATS:
2311 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2312 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2313 ETH_GSTRING_LEN);
2314 p += ETH_GSTRING_LEN;
2315 }
7ed674bc
IS		 2316
2317 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2318 mlxsw_sp_port_get_prio_strings(&p, i);
2319
df4750e8
IS		 2320 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2321 mlxsw_sp_port_get_tc_strings(&p, i);
2322
56ade8fe
JP		 2323 break;
2324 }
2325}
2326
3a66ee38
IS		 2327static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2328 enum ethtool_phys_id_state state)
2329{
2330 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2331 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2332 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2333 bool active;
2334
2335 switch (state) {
2336 case ETHTOOL_ID_ACTIVE:
2337 active = true;
2338 break;
2339 case ETHTOOL_ID_INACTIVE:
2340 active = false;
2341 break;
2342 default:
2343 return -EOPNOTSUPP;
2344 }
2345
2346 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2348}
2349
7ed674bc
IS		 2350static int
2351mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2352 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2353{
2354 switch (grp) {
2355 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2356 *p_hw_stats = mlxsw_sp_port_hw_stats;
2357 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2358 break;
2359 case MLXSW_REG_PPCNT_PRIO_CNT:
2360 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2361 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2362 break;
df4750e8
IS		 2363 case MLXSW_REG_PPCNT_TC_CNT:
2364 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2365 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2366 break;
7ed674bc
IS		 2367 default:
2368 WARN_ON(1);
e915ac68 2369 return -EOPNOTSUPP;
7ed674bc
IS		 2370 }
2371 return 0;
2372}
2373
2374static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2375 enum mlxsw_reg_ppcnt_grp grp, int prio,
2376 u64 *data, int data_index)
56ade8fe 2377{
18281f2d
IS		 2378 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2379 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
7ed674bc 2380 struct mlxsw_sp_port_hw_stats *hw_stats;
56ade8fe 2381 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
7ed674bc 2382 int i, len;
56ade8fe
JP		 2383 int err;
2384
7ed674bc
IS		 2385 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2386 if (err)
2387 return;
fc1bbb0f 2388 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
18281f2d 2389 for (i = 0; i < len; i++) {
faac0ff0 2390 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
18281f2d
IS		 2391 if (!hw_stats[i].cells_bytes)
2392 continue;
2393 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2394 data[data_index + i]);
2395 }
7ed674bc
IS		 2396}
2397
2398static void mlxsw_sp_port_get_stats(struct net_device *dev,
2399 struct ethtool_stats *stats, u64 *data)
2400{
2401 int i, data_index = 0;
2402
2403 /* IEEE 802.3 Counters */
2404 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2405 data, data_index);
2406 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2407
2408 /* Per-Priority Counters */
2409 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2410 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2411 data, data_index);
2412 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2413 }
df4750e8
IS		 2414
2415 /* Per-TC Counters */
2416 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2417 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2418 data, data_index);
2419 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2420 }
56ade8fe
JP		 2421}
2422
2423static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2424{
2425 switch (sset) {
2426 case ETH_SS_STATS:
7ed674bc 2427 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
56ade8fe
JP		 2428 default:
2429 return -EOPNOTSUPP;
2430 }
2431}
2432
2433struct mlxsw_sp_port_link_mode {
b9d66a36 2434 enum ethtool_link_mode_bit_indices mask_ethtool;
56ade8fe 2435 u32 mask;
56ade8fe
JP		 2436 u32 speed;
2437};
2438
2439static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2440 {
2441 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
b9d66a36
IS		 2442 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2443 .speed = SPEED_100,
56ade8fe
JP		 2444 },
2445 {
2446 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2447 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
b9d66a36
IS		 2448 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2449 .speed = SPEED_1000,
56ade8fe
JP		 2450 },
2451 {
2452 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
b9d66a36
IS		 2453 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2454 .speed = SPEED_10000,
56ade8fe
JP		 2455 },
2456 {
2457 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2458 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
b9d66a36
IS		 2459 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2460 .speed = SPEED_10000,
56ade8fe
JP		 2461 },
2462 {
2463 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2464 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2465 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2466 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
b9d66a36
IS		 2467 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2468 .speed = SPEED_10000,
56ade8fe
JP		 2469 },
2470 {
2471 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
b9d66a36
IS		 2472 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2473 .speed = SPEED_20000,
56ade8fe
JP		 2474 },
2475 {
2476 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
b9d66a36
IS		 2477 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2478 .speed = SPEED_40000,
56ade8fe
JP		 2479 },
2480 {
2481 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
b9d66a36
IS		 2482 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2483 .speed = SPEED_40000,
56ade8fe
JP		 2484 },
2485 {
2486 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
b9d66a36
IS		 2487 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2488 .speed = SPEED_40000,
56ade8fe
JP		 2489 },
2490 {
2491 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
b9d66a36
IS		 2492 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2493 .speed = SPEED_40000,
2494 },
2495 {
2496 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2497 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2498 .speed = SPEED_25000,
2499 },
2500 {
2501 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2502 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2503 .speed = SPEED_25000,
2504 },
2505 {
2506 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2507 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2508 .speed = SPEED_25000,
56ade8fe
JP		 2509 },
2510 {
b9d66a36
IS		 2511 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2512 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2513 .speed = SPEED_25000,
56ade8fe
JP		 2514 },
2515 {
b9d66a36
IS		 2516 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2517 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2518 .speed = SPEED_50000,
2519 },
2520 {
2521 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2522 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2523 .speed = SPEED_50000,
2524 },
2525 {
2526 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2527 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2528 .speed = SPEED_50000,
56ade8fe
JP		 2529 },
2530 {
2531 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
b9d66a36
IS		 2532 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2533 .speed = SPEED_56000,
56ade8fe
JP		 2534 },
2535 {
b9d66a36
IS		 2536 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2537 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2538 .speed = SPEED_56000,
2539 },
2540 {
2541 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2542 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2543 .speed = SPEED_56000,
2544 },
2545 {
2546 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2547 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2548 .speed = SPEED_56000,
2549 },
2550 {
2551 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2552 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2553 .speed = SPEED_100000,
2554 },
2555 {
2556 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2557 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2558 .speed = SPEED_100000,
2559 },
2560 {
2561 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2562 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2563 .speed = SPEED_100000,
2564 },
2565 {
2566 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2567 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2568 .speed = SPEED_100000,
56ade8fe
JP		 2569 },
2570};
2571
2572#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2573
b9d66a36
IS		 2574static void
2575mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2576 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2577{
2578 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2579 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2580 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2581 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2582 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2583 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
b9d66a36 2584 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
56ade8fe
JP		 2585
2586 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2587 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2588 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2589 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2590 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
b9d66a36 2591 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
56ade8fe
JP		 2592}
2593
b9d66a36 2594static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
56ade8fe 2595{
56ade8fe
JP		 2596 int i;
2597
2598 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2599 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
b9d66a36
IS		 2600 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2601 mode);
56ade8fe 2602 }
56ade8fe
JP		 2603}
2604
2605static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
b9d66a36 2606 struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2607{
2608 u32 speed = SPEED_UNKNOWN;
2609 u8 duplex = DUPLEX_UNKNOWN;
2610 int i;
2611
2612 if (!carrier_ok)
2613 goto out;
2614
2615 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2616 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2617 speed = mlxsw_sp_port_link_mode[i].speed;
2618 duplex = DUPLEX_FULL;
2619 break;
2620 }
2621 }
2622out:
b9d66a36
IS		 2623 cmd->base.speed = speed;
2624 cmd->base.duplex = duplex;
56ade8fe
JP		 2625}
2626
2627static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2628{
2629 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2630 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2631 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2632 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2633 return PORT_FIBRE;
2634
2635 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2636 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2637 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2638 return PORT_DA;
2639
2640 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2641 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2642 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2643 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2644 return PORT_NONE;
2645
2646 return PORT_OTHER;
2647}
2648
b9d66a36
IS		 2649static u32
2650mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
56ade8fe
JP		 2651{
2652 u32 ptys_proto = 0;
2653 int i;
2654
2655 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
b9d66a36
IS		 2656 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2657 cmd->link_modes.advertising))
56ade8fe
JP		 2658 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2659 }
2660 return ptys_proto;
2661}
2662
2663static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2664{
2665 u32 ptys_proto = 0;
2666 int i;
2667
2668 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2669 if (speed == mlxsw_sp_port_link_mode[i].speed)
2670 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2671 }
2672 return ptys_proto;
2673}
2674
18f1e70c
IS		 2675static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2676{
2677 u32 ptys_proto = 0;
2678 int i;
2679
2680 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2681 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2682 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2683 }
2684 return ptys_proto;
2685}
2686
b9d66a36
IS		 2687static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2688 struct ethtool_link_ksettings *cmd)
2689{
2690 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2691 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2692 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2693
2694 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2695 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2696}
2697
2698static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2699 struct ethtool_link_ksettings *cmd)
56ade8fe 2700{
b9d66a36
IS		 2701 if (!autoneg)
2702 return;
2703
2704 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2705 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2706}
2707
2708static void
2709mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2710 struct ethtool_link_ksettings *cmd)
2711{
2712 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2713 return;
2714
2715 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2716 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2717}
2718
2719static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2720 struct ethtool_link_ksettings *cmd)
2721{
2722 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
56ade8fe
JP		 2723 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2724 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2725 char ptys_pl[MLXSW_REG_PTYS_LEN];
b9d66a36 2726 u8 autoneg_status;
0c83f88c 2727 bool autoneg;
56ade8fe
JP		 2728 int err;
2729
b9d66a36 2730 autoneg = mlxsw_sp_port->link.autoneg;
401c8b4e 2731 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
b9d66a36
IS		 2732 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2733 if (err)
2734 return err;
401c8b4e
ER		 2735 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2736 &eth_proto_oper);
b9d66a36
IS		 2737
2738 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
56ade8fe 2739
b9d66a36
IS		 2740 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2741
2742 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2743 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2744 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2745
2746 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2747 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2748 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2749 cmd);
2750
2751 return 0;
2752}
2753
2754static int
2755mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2756 const struct ethtool_link_ksettings *cmd)
2757{
2758 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2759 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2760 char ptys_pl[MLXSW_REG_PTYS_LEN];
2761 u32 eth_proto_cap, eth_proto_new;
2762 bool autoneg;
2763 int err;
56ade8fe 2764
401c8b4e 2765 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
56ade8fe 2766 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2767 if (err)
56ade8fe 2768 return err;
401c8b4e 2769 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
b9d66a36
IS		 2770
2771 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2772 eth_proto_new = autoneg ?
2773 mlxsw_sp_to_ptys_advert_link(cmd) :
2774 mlxsw_sp_to_ptys_speed(cmd->base.speed);
56ade8fe
JP		 2775
2776 eth_proto_new = eth_proto_new & eth_proto_cap;
2777 if (!eth_proto_new) {
b9d66a36 2778 netdev_err(dev, "No supported speed requested\n");
56ade8fe
JP		 2779 return -EINVAL;
2780 }
56ade8fe 2781
401c8b4e
ER		 2782 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2783 eth_proto_new);
56ade8fe 2784 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
b9d66a36 2785 if (err)
56ade8fe 2786 return err;
56ade8fe 2787
6277d46b 2788 if (!netif_running(dev))
56ade8fe
JP		 2789 return 0;
2790
0c83f88c
IS		 2791 mlxsw_sp_port->link.autoneg = autoneg;
2792
b9d66a36
IS		 2793 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2794 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
56ade8fe
JP		 2795
2796 return 0;
2797}
2798
ce6ef68f
YG		 2799static int mlxsw_sp_flash_device(struct net_device *dev,
2800 struct ethtool_flash *flash)
2801{
2802 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2803 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2804 const struct firmware *firmware;
2805 int err;
2806
2807 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2808 return -EOPNOTSUPP;
2809
2810 dev_hold(dev);
2811 rtnl_unlock();
2812
2813 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2814 if (err)
2815 goto out;
2816 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2817 release_firmware(firmware);
2818out:
2819 rtnl_lock();
2820 dev_put(dev);
2821 return err;
2822}
2823
4400081b
AS		 2824#define MLXSW_SP_I2C_ADDR_LOW 0x50
2825#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2826#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2ea10903
AS		 2827
2828static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2829 u16 offset, u16 size, void *data,
2830 unsigned int *p_read_size)
2831{
2832 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2833 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2834 char mcia_pl[MLXSW_REG_MCIA_LEN];
4400081b 2835 u16 i2c_addr;
2ea10903
AS		 2836 int status;
2837 int err;
2838
2839 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
4400081b
AS		 2840
2841 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2842 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2843 /* Cross pages read, read until offset 256 in low page */
2844 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2845
2846 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2847 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2848 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2849 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2850 }
2851
2ea10903 2852 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
4400081b 2853 0, 0, offset, size, i2c_addr);
2ea10903
AS		 2854
2855 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2856 if (err)
2857 return err;
2858
2859 status = mlxsw_reg_mcia_status_get(mcia_pl);
2860 if (status)
2861 return -EIO;
2862
2863 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2864 memcpy(data, eeprom_tmp, size);
2865 *p_read_size = size;
2866
2867 return 0;
2868}
2869
2870enum mlxsw_sp_eeprom_module_info_rev_id {
2871 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2872 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2873 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2874};
2875
2876enum mlxsw_sp_eeprom_module_info_id {
2877 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2878 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2879 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2880 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2881};
2882
2883enum mlxsw_sp_eeprom_module_info {
2884 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2885 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2886 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2887};
2888
2889static int mlxsw_sp_get_module_info(struct net_device *netdev,
2890 struct ethtool_modinfo *modinfo)
2891{
2892 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2893 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2894 u8 module_rev_id, module_id;
2895 unsigned int read_size;
2896 int err;
2897
2898 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2899 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2900 module_info, &read_size);
2901 if (err)
2902 return err;
2903
2904 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2905 return -EIO;
2906
2907 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2908 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2909
2910 switch (module_id) {
2911 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2912 modinfo->type = ETH_MODULE_SFF_8436;
2913 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2914 break;
2915 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2916 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2917 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2918 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2919 modinfo->type = ETH_MODULE_SFF_8636;
2920 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2921 } else {
2922 modinfo->type = ETH_MODULE_SFF_8436;
2923 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2924 }
2925 break;
2926 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2927 modinfo->type = ETH_MODULE_SFF_8472;
2928 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2929 break;
2930 default:
2931 return -EINVAL;
2932 }
2933
2934 return 0;
2935}
2936
2937static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2938 struct ethtool_eeprom *ee,
2939 u8 *data)
2940{
2941 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2942 int offset = ee->offset;
2943 unsigned int read_size;
2944 int i = 0;
2945 int err;
2946
2947 if (!ee->len)
2948 return -EINVAL;
2949
2950 memset(data, 0, ee->len);
2951
2952 while (i < ee->len) {
2953 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2954 ee->len - i, data + i,
2955 &read_size);
2956 if (err) {
2957 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2958 return err;
2959 }
2960
2961 i += read_size;
2962 offset += read_size;
2963 }
2964
2965 return 0;
2966}
2967
56ade8fe
JP		 2968static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2969 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2970 .get_link = ethtool_op_get_link,
9f7ec052
IS		 2971 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2972 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
56ade8fe 2973 .get_strings = mlxsw_sp_port_get_strings,
3a66ee38 2974 .set_phys_id = mlxsw_sp_port_set_phys_id,
56ade8fe
JP		 2975 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2976 .get_sset_count = mlxsw_sp_port_get_sset_count,
b9d66a36
IS		 2977 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2978 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
ce6ef68f 2979 .flash_device = mlxsw_sp_flash_device,
2ea10903
AS		 2980 .get_module_info = mlxsw_sp_get_module_info,
2981 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
56ade8fe
JP		 2982};
2983
18f1e70c
IS		 2984static int
2985mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2986{
2987 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2988 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2989 char ptys_pl[MLXSW_REG_PTYS_LEN];
2990 u32 eth_proto_admin;
2991
2992 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
401c8b4e
ER		 2993 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2994 eth_proto_admin);
18f1e70c
IS		 2995 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2996}
2997
8e8dfe9f
IS		 2998int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2999 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
3000 bool dwrr, u8 dwrr_weight)
90183b98
IS		 3001{
3002 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3003 char qeec_pl[MLXSW_REG_QEEC_LEN];
3004
3005 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3006 next_index);
3007 mlxsw_reg_qeec_de_set(qeec_pl, true);
3008 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
3009 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
3010 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3011}
3012
cc7cf517
IS		 3013int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
3014 enum mlxsw_reg_qeec_hr hr, u8 index,
3015 u8 next_index, u32 maxrate)
90183b98
IS		 3016{
3017 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3018 char qeec_pl[MLXSW_REG_QEEC_LEN];
3019
3020 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3021 next_index);
3022 mlxsw_reg_qeec_mase_set(qeec_pl, true);
3023 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3024 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3025}
3026
8e8dfe9f
IS		 3027int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3028 u8 switch_prio, u8 tclass)
90183b98
IS		 3029{
3030 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3031 char qtct_pl[MLXSW_REG_QTCT_LEN];
3032
3033 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3034 tclass);
3035 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3036}
3037
3038static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3039{
3040 int err, i;
3041
3042 /* Setup the elements hierarcy, so that each TC is linked to
3043 * one subgroup, which are all member in the same group.
3044 */
3045 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3046 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3047 0);
3048 if (err)
3049 return err;
3050 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3051 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3052 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3053 0, false, 0);
3054 if (err)
3055 return err;
3056 }
3057 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3058 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3059 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3060 false, 0);
3061 if (err)
3062 return err;
3063 }
3064
3065 /* Make sure the max shaper is disabled in all hierarcies that
3066 * support it.
3067 */
3068 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3069 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3070 MLXSW_REG_QEEC_MAS_DIS);
3071 if (err)
3072 return err;
3073 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3074 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3075 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3076 i, 0,
3077 MLXSW_REG_QEEC_MAS_DIS);
3078 if (err)
3079 return err;
3080 }
3081 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3082 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3083 MLXSW_REG_QEEC_HIERARCY_TC,
3084 i, i,
3085 MLXSW_REG_QEEC_MAS_DIS);
3086 if (err)
3087 return err;
3088 }
3089
3090 /* Map all priorities to traffic class 0. */
3091 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3092 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3093 if (err)
3094 return err;
3095 }
3096
3097 return 0;
3098}
3099
5b153859
IS		 3100static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3101 bool split, u8 module, u8 width, u8 lane)
56ade8fe 3102{
c57529e1 3103 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
56ade8fe
JP		 3104 struct mlxsw_sp_port *mlxsw_sp_port;
3105 struct net_device *dev;
56ade8fe
JP		 3106 int err;
3107
5b153859
IS		 3108 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
3109 if (err) {
3110 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3111 local_port);
3112 return err;
3113 }
3114
56ade8fe 3115 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
5b153859
IS		 3116 if (!dev) {
3117 err = -ENOMEM;
3118 goto err_alloc_etherdev;
3119 }
f20a91f1 3120 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
56ade8fe
JP		 3121 mlxsw_sp_port = netdev_priv(dev);
3122 mlxsw_sp_port->dev = dev;
3123 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3124 mlxsw_sp_port->local_port = local_port;
c57529e1 3125 mlxsw_sp_port->pvid = 1;
18f1e70c 3126 mlxsw_sp_port->split = split;
d664b41e
IS		 3127 mlxsw_sp_port->mapping.module = module;
3128 mlxsw_sp_port->mapping.width = width;
3129 mlxsw_sp_port->mapping.lane = lane;
0c83f88c 3130 mlxsw_sp_port->link.autoneg = 1;
31a08a52 3131 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
763b4b70 3132 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
56ade8fe
JP		 3133
3134 mlxsw_sp_port->pcpu_stats =
3135 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3136 if (!mlxsw_sp_port->pcpu_stats) {
3137 err = -ENOMEM;
3138 goto err_alloc_stats;
3139 }
3140
98d0f7b9
YG		 3141 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3142 GFP_KERNEL);
3143 if (!mlxsw_sp_port->sample) {
3144 err = -ENOMEM;
3145 goto err_alloc_sample;
3146 }
3147
9deef43d 3148 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
fc1bbb0f
NF		 3149 &update_stats_cache);
3150
56ade8fe
JP		 3151 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3152 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3153
2e915e0b 3154 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
5b153859
IS		 3155 if (err) {
3156 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3157 mlxsw_sp_port->local_port);
3158 goto err_port_module_map;
3159 }
3160
3247ff2b
IS		 3161 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3162 if (err) {
3163 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3164 mlxsw_sp_port->local_port);
3165 goto err_port_swid_set;
3166 }
3167
56ade8fe
JP		 3168 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3169 if (err) {
3170 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3171 mlxsw_sp_port->local_port);
3172 goto err_dev_addr_init;
3173 }
3174
3175 netif_carrier_off(dev);
3176
3177 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
763b4b70
YG		 3178 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3179 dev->hw_features |= NETIF_F_HW_TC;
56ade8fe 3180
d894be57
JW		 3181 dev->min_mtu = 0;
3182 dev->max_mtu = ETH_MAX_MTU;
3183
56ade8fe
JP		 3184 /* Each packet needs to have a Tx header (metadata) on top all other
3185 * headers.
3186 */
feb7d387 3187 dev->needed_headroom = MLXSW_TXHDR_LEN;
56ade8fe 3188
56ade8fe
JP		 3189 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3190 if (err) {
3191 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3192 mlxsw_sp_port->local_port);
3193 goto err_port_system_port_mapping_set;
3194 }
3195
18f1e70c
IS		 3196 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3197 if (err) {
3198 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3199 mlxsw_sp_port->local_port);
3200 goto err_port_speed_by_width_set;
3201 }
3202
56ade8fe
JP		 3203 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3204 if (err) {
3205 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3206 mlxsw_sp_port->local_port);
3207 goto err_port_mtu_set;
3208 }
3209
3210 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3211 if (err)
3212 goto err_port_admin_status_set;
3213
3214 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3215 if (err) {
3216 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3217 mlxsw_sp_port->local_port);
3218 goto err_port_buffers_init;
3219 }
3220
90183b98
IS		 3221 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3222 if (err) {
3223 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3224 mlxsw_sp_port->local_port);
3225 goto err_port_ets_init;
3226 }
3227
f00817df
IS		 3228 /* ETS and buffers must be initialized before DCB. */
3229 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3230 if (err) {
3231 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3232 mlxsw_sp_port->local_port);
3233 goto err_port_dcb_init;
3234 }
3235
a1107487 3236 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
45a4a16c 3237 if (err) {
a1107487 3238 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
45a4a16c 3239 mlxsw_sp_port->local_port);
a1107487 3240 goto err_port_fids_init;
45a4a16c
IS		 3241 }
3242
371b437a
NF		 3243 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3244 if (err) {
3245 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3246 mlxsw_sp_port->local_port);
3247 goto err_port_qdiscs_init;
3248 }
3249
c57529e1
IS		 3250 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3251 if (IS_ERR(mlxsw_sp_port_vlan)) {
3252 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
05978481 3253 mlxsw_sp_port->local_port);
d86fd113 3254 err = PTR_ERR(mlxsw_sp_port_vlan);
c57529e1 3255 goto err_port_vlan_get;
05978481
IS		 3256 }
3257
56ade8fe 3258 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2f25844c 3259 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
56ade8fe
JP		 3260 err = register_netdev(dev);
3261 if (err) {
3262 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3263 mlxsw_sp_port->local_port);
3264 goto err_register_netdev;
3265 }
3266
d808c7e4
ER		 3267 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3268 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3269 module);
9deef43d 3270 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
56ade8fe
JP		 3271 return 0;
3272
56ade8fe 3273err_register_netdev:
2f25844c 3274 mlxsw_sp->ports[local_port] = NULL;
0583272d 3275 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1
IS		 3276 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3277err_port_vlan_get:
371b437a
NF		 3278 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3279err_port_qdiscs_init:
a1107487
IS		 3280 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3281err_port_fids_init:
4de34eb5 3282 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
f00817df 3283err_port_dcb_init:
90183b98 3284err_port_ets_init:
56ade8fe
JP		 3285err_port_buffers_init:
3286err_port_admin_status_set:
3287err_port_mtu_set:
18f1e70c 3288err_port_speed_by_width_set:
56ade8fe 3289err_port_system_port_mapping_set:
56ade8fe 3290err_dev_addr_init:
3247ff2b
IS		 3291 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3292err_port_swid_set:
2e915e0b 3293 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
5b153859 3294err_port_module_map:
98d0f7b9
YG		 3295 kfree(mlxsw_sp_port->sample);
3296err_alloc_sample:
56ade8fe
JP		 3297 free_percpu(mlxsw_sp_port->pcpu_stats);
3298err_alloc_stats:
3299 free_netdev(dev);
5b153859 3300err_alloc_etherdev:
67963a33
JP		 3301 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3302 return err;
3303}
3304
5b153859 3305static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
56ade8fe
JP		 3306{
3307 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3308
9deef43d 3309 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
67963a33 3310 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
56ade8fe 3311 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2f25844c 3312 mlxsw_sp->ports[local_port] = NULL;
0583272d 3313 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
c57529e1 3314 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
371b437a 3315 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
a1107487 3316 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
f00817df 3317 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3e9b27b8 3318 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2e915e0b 3319 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
98d0f7b9 3320 kfree(mlxsw_sp_port->sample);
136f1445 3321 free_percpu(mlxsw_sp_port->pcpu_stats);
31a08a52 3322 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
56ade8fe 3323 free_netdev(mlxsw_sp_port->dev);
67963a33
JP		 3324 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3325}
3326
f83e2102
JP		 3327static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3328{
3329 return mlxsw_sp->ports[local_port] != NULL;
3330}
3331
56ade8fe
JP		 3332static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3333{
3334 int i;
3335
5ec2ee7d 3336 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
f83e2102
JP		 3337 if (mlxsw_sp_port_created(mlxsw_sp, i))
3338 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d 3339 kfree(mlxsw_sp->port_to_module);
56ade8fe
JP		 3340 kfree(mlxsw_sp->ports);
3341}
3342
3343static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3344{
5ec2ee7d 3345 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
d664b41e 3346 u8 module, width, lane;
56ade8fe
JP		 3347 size_t alloc_size;
3348 int i;
3349 int err;
3350
5ec2ee7d 3351 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
56ade8fe
JP		 3352 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3353 if (!mlxsw_sp->ports)
3354 return -ENOMEM;
3355
bf4e9f24
IS		 3356 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3357 GFP_KERNEL);
5ec2ee7d
IS		 3358 if (!mlxsw_sp->port_to_module) {
3359 err = -ENOMEM;
3360 goto err_port_to_module_alloc;
3361 }
3362
3363 for (i = 1; i < max_ports; i++) {
bf4e9f24
IS		 3364 /* Mark as invalid */
3365 mlxsw_sp->port_to_module[i] = -1;
3366
558c2d5e 3367 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
d664b41e 3368 &width, &lane);
558c2d5e
IS		 3369 if (err)
3370 goto err_port_module_info_get;
3371 if (!width)
3372 continue;
3373 mlxsw_sp->port_to_module[i] = module;
67963a33
JP		 3374 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3375 module, width, lane);
56ade8fe
JP		 3376 if (err)
3377 goto err_port_create;
3378 }
3379 return 0;
3380
3381err_port_create:
558c2d5e 3382err_port_module_info_get:
56ade8fe 3383 for (i--; i >= 1; i--)
f83e2102
JP		 3384 if (mlxsw_sp_port_created(mlxsw_sp, i))
3385 mlxsw_sp_port_remove(mlxsw_sp, i);
5ec2ee7d
IS		 3386 kfree(mlxsw_sp->port_to_module);
3387err_port_to_module_alloc:
56ade8fe
JP		 3388 kfree(mlxsw_sp->ports);
3389 return err;
3390}
3391
18f1e70c
IS		 3392static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3393{
3394 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3395
3396 return local_port - offset;
3397}
3398
be94535f
IS		 3399static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3400 u8 module, unsigned int count)
3401{
3402 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3403 int err, i;
3404
be94535f
IS		 3405 for (i = 0; i < count; i++) {
3406 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
d664b41e 3407 module, width, i * width);
be94535f
IS		 3408 if (err)
3409 goto err_port_create;
3410 }
3411
3412 return 0;
3413
3414err_port_create:
3415 for (i--; i >= 0; i--)
f83e2102
JP		 3416 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3417 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
be94535f
IS		 3418 return err;
3419}
3420
3421static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3422 u8 base_port, unsigned int count)
3423{
3424 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3425 int i;
3426
3427 /* Split by four means we need to re-create two ports, otherwise
3428 * only one.
3429 */
3430 count = count / 2;
3431
be94535f
IS		 3432 for (i = 0; i < count; i++) {
3433 local_port = base_port + i * 2;
bf4e9f24
IS		 3434 if (mlxsw_sp->port_to_module[local_port] < 0)
3435 continue;
be94535f
IS		 3436 module = mlxsw_sp->port_to_module[local_port];
3437
3438 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
d664b41e 3439 width, 0);
be94535f
IS		 3440 }
3441}
3442
b2f10571
JP		 3443static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3444 unsigned int count)
18f1e70c 3445{
b2f10571 3446 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3447 struct mlxsw_sp_port *mlxsw_sp_port;
18f1e70c
IS		 3448 u8 module, cur_width, base_port;
3449 int i;
3450 int err;
3451
3452 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3453 if (!mlxsw_sp_port) {
3454 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3455 local_port);
3456 return -EINVAL;
3457 }
3458
d664b41e
IS		 3459 module = mlxsw_sp_port->mapping.module;
3460 cur_width = mlxsw_sp_port->mapping.width;
3461
18f1e70c
IS		 3462 if (count != 2 && count != 4) {
3463 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3464 return -EINVAL;
3465 }
3466
18f1e70c
IS		 3467 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3468 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3469 return -EINVAL;
3470 }
3471
3472 /* Make sure we have enough slave (even) ports for the split. */
3473 if (count == 2) {
3474 base_port = local_port;
3475 if (mlxsw_sp->ports[base_port + 1]) {
3476 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3477 return -EINVAL;
3478 }
3479 } else {
3480 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3481 if (mlxsw_sp->ports[base_port + 1] ||
3482 mlxsw_sp->ports[base_port + 3]) {
3483 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3484 return -EINVAL;
3485 }
3486 }
3487
3488 for (i = 0; i < count; i++)
f83e2102
JP		 3489 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3490 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3491
be94535f
IS		 3492 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3493 if (err) {
3494 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3495 goto err_port_split_create;
18f1e70c
IS		 3496 }
3497
3498 return 0;
3499
be94535f
IS		 3500err_port_split_create:
3501 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3502 return err;
3503}
3504
b2f10571 3505static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
18f1e70c 3506{
b2f10571 3507 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
18f1e70c 3508 struct mlxsw_sp_port *mlxsw_sp_port;
d664b41e 3509 u8 cur_width, base_port;
18f1e70c
IS		 3510 unsigned int count;
3511 int i;
18f1e70c
IS		 3512
3513 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3514 if (!mlxsw_sp_port) {
3515 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3516 local_port);
3517 return -EINVAL;
3518 }
3519
3520 if (!mlxsw_sp_port->split) {
3521 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3522 return -EINVAL;
3523 }
3524
d664b41e 3525 cur_width = mlxsw_sp_port->mapping.width;
18f1e70c
IS		 3526 count = cur_width == 1 ? 4 : 2;
3527
3528 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3529
3530 /* Determine which ports to remove. */
3531 if (count == 2 && local_port >= base_port + 2)
3532 base_port = base_port + 2;
3533
3534 for (i = 0; i < count; i++)
f83e2102
JP		 3535 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3536 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
18f1e70c 3537
be94535f 3538 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
18f1e70c
IS		 3539
3540 return 0;
3541}
3542
56ade8fe
JP		 3543static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3544 char *pude_pl, void *priv)
3545{
3546 struct mlxsw_sp *mlxsw_sp = priv;
3547 struct mlxsw_sp_port *mlxsw_sp_port;
3548 enum mlxsw_reg_pude_oper_status status;
3549 u8 local_port;
3550
3551 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3552 mlxsw_sp_port = mlxsw_sp->ports[local_port];
bbf2a475 3553 if (!mlxsw_sp_port)
56ade8fe 3554 return;
56ade8fe
JP		 3555
3556 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3557 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3558 netdev_info(mlxsw_sp_port->dev, "link up\n");
3559 netif_carrier_on(mlxsw_sp_port->dev);
3560 } else {
3561 netdev_info(mlxsw_sp_port->dev, "link down\n");
3562 netif_carrier_off(mlxsw_sp_port->dev);
3563 }
3564}
3565
14eeda99
NF		 3566static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3567 u8 local_port, void *priv)
56ade8fe
JP		 3568{
3569 struct mlxsw_sp *mlxsw_sp = priv;
3570 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3571 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3572
3573 if (unlikely(!mlxsw_sp_port)) {
3574 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3575 local_port);
3576 return;
3577 }
3578
3579 skb->dev = mlxsw_sp_port->dev;
3580
3581 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3582 u64_stats_update_begin(&pcpu_stats->syncp);
3583 pcpu_stats->rx_packets++;
3584 pcpu_stats->rx_bytes += skb->len;
3585 u64_stats_update_end(&pcpu_stats->syncp);
3586
3587 skb->protocol = eth_type_trans(skb, skb->dev);
3588 netif_receive_skb(skb);
3589}
3590
1c6c6d22
IS		 3591static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3592 void *priv)
3593{
3594 skb->offload_fwd_mark = 1;
14eeda99 3595 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
1c6c6d22
IS		 3596}
3597
a0040c8c
YG		 3598static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3599 u8 local_port, void *priv)
3600{
3601 skb->offload_mr_fwd_mark = 1;
3602 skb->offload_fwd_mark = 1;
3603 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3604}
3605
98d0f7b9
YG		 3606static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3607 void *priv)
3608{
3609 struct mlxsw_sp *mlxsw_sp = priv;
3610 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3611 struct psample_group *psample_group;
3612 u32 size;
3613
3614 if (unlikely(!mlxsw_sp_port)) {
3615 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3616 local_port);
3617 goto out;
3618 }
3619 if (unlikely(!mlxsw_sp_port->sample)) {
3620 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3621 local_port);
3622 goto out;
3623 }
3624
3625 size = mlxsw_sp_port->sample->truncate ?
3626 mlxsw_sp_port->sample->trunc_size : skb->len;
3627
3628 rcu_read_lock();
3629 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3630 if (!psample_group)
3631 goto out_unlock;
3632 psample_sample_packet(psample_group, skb, size,
3633 mlxsw_sp_port->dev->ifindex, 0,
3634 mlxsw_sp_port->sample->rate);
3635out_unlock:
3636 rcu_read_unlock();
3637out:
3638 consume_skb(skb);
3639}
3640
117b0dad 3641#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
0fb78a4e 3642 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
117b0dad 3643 _is_ctrl, SP_##_trap_group, DISCARD)
14eeda99 3644
117b0dad 3645#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
14eeda99 3646 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
117b0dad
NF		 3647 _is_ctrl, SP_##_trap_group, DISCARD)
3648
a0040c8c
YG		 3649#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3650 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3651 _is_ctrl, SP_##_trap_group, DISCARD)
3652
117b0dad
NF		 3653#define MLXSW_SP_EVENTL(_func, _trap_id) \
3654 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
93393b33 3655
4544913e
NF		 3656static const struct mlxsw_listener mlxsw_sp_listener[] = {
3657 /* Events */
117b0dad 3658 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
ee4a60d8 3659 /* L2 traps */
117b0dad
NF		 3660 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3661 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3662 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3663 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3664 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3665 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3666 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3667 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3668 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3669 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3670 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
9d41accc 3671 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
588823f9
AS		 3672 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3673 false),
3674 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3675 false),
3676 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3677 false),
3678 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3679 false),
93393b33 3680 /* L3 traps */
0fcc4847
IS		 3681 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3682 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3683 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
0fcc4847 3684 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
8d54814e
AS		 3685 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3686 false),
3687 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3688 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3689 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3690 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3691 false),
3692 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3693 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3694 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
0fcc4847 3695 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
8d54814e
AS		 3696 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3697 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3698 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3699 false),
3700 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3701 false),
3702 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3703 false),
3704 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3705 false),
3706 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3707 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3708 false),
3709 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3710 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
7607dd35 3711 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
8d54814e 3712 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
86484de2 3713 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
98d0f7b9
YG		 3714 /* PKT Sample trap */
3715 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
0db7b386
JP		 3716 false, SP_IP2ME, DISCARD),
3717 /* ACL trap */
3718 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
b48cfc80
YG		 3719 /* Multicast Router Traps */
3720 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3721 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3722 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
a0040c8c 3723 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
56ade8fe
JP		 3724};
3725
9148e7cf
NF		 3726static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3727{
3728 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3729 enum mlxsw_reg_qpcr_ir_units ir_units;
3730 int max_cpu_policers;
3731 bool is_bytes;
3732 u8 burst_size;
3733 u32 rate;
3734 int i, err;
3735
3736 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3737 return -EIO;
3738
3739 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3740
3741 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3742 for (i = 0; i < max_cpu_policers; i++) {
3743 is_bytes = false;
3744 switch (i) {
3745 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3746 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3747 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3748 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80
YG		 3749 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3750 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
9148e7cf
NF		 3751 rate = 128;
3752 burst_size = 7;
3753 break;
3754 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
588823f9 3755 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
9148e7cf
NF		 3756 rate = 16 * 1024;
3757 burst_size = 10;
3758 break;
8d54814e 3759 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
9148e7cf
NF		 3760 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3761 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
8d54814e 3762 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
9148e7cf
NF		 3763 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3764 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
8d54814e 3765 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3766 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
9148e7cf
NF		 3767 rate = 1024;
3768 burst_size = 7;
3769 break;
3770 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3771 is_bytes = true;
3772 rate = 4 * 1024;
3773 burst_size = 4;
3774 break;
3775 default:
3776 continue;
3777 }
3778
3779 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3780 burst_size);
3781 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3782 if (err)
3783 return err;
3784 }
3785
3786 return 0;
3787}
3788
579c82e4 3789static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
56ade8fe
JP		 3790{
3791 char htgt_pl[MLXSW_REG_HTGT_LEN];
117b0dad 3792 enum mlxsw_reg_htgt_trap_group i;
9148e7cf 3793 int max_cpu_policers;
579c82e4
NF		 3794 int max_trap_groups;
3795 u8 priority, tc;
9148e7cf 3796 u16 policer_id;
117b0dad 3797 int err;
579c82e4
NF		 3798
3799 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3800 return -EIO;
3801
3802 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
9148e7cf 3803 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
579c82e4
NF		 3804
3805 for (i = 0; i < max_trap_groups; i++) {
9148e7cf 3806 policer_id = i;
579c82e4 3807 switch (i) {
117b0dad
NF		 3808 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3809 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3810 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3811 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
b48cfc80 3812 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
117b0dad
NF		 3813 priority = 5;
3814 tc = 5;
3815 break;
8d54814e 3816 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
117b0dad
NF		 3817 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3818 priority = 4;
3819 tc = 4;
3820 break;
3821 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3822 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
588823f9 3823 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
117b0dad
NF		 3824 priority = 3;
3825 tc = 3;
3826 break;
3827 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
8d54814e 3828 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
b48cfc80 3829 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
117b0dad
NF		 3830 priority = 2;
3831 tc = 2;
3832 break;
8d54814e 3833 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
117b0dad
NF		 3834 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3835 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
b48cfc80 3836 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
117b0dad
NF		 3837 priority = 1;
3838 tc = 1;
3839 break;
3840 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
579c82e4
NF		 3841 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3842 tc = MLXSW_REG_HTGT_DEFAULT_TC;
9148e7cf 3843 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
579c82e4
NF		 3844 break;
3845 default:
3846 continue;
3847 }
117b0dad 3848
9148e7cf
NF		 3849 if (max_cpu_policers <= policer_id &&
3850 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3851 return -EIO;
3852
3853 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
579c82e4
NF		 3854 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3855 if (err)
3856 return err;
3857 }
3858
3859 return 0;
3860}
3861
3862static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3863{
56ade8fe
JP		 3864 int i;
3865 int err;
3866
9148e7cf
NF		 3867 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3868 if (err)
3869 return err;
3870
579c82e4 3871 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
56ade8fe
JP		 3872 if (err)
3873 return err;
3874
4544913e 3875 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3876 err = mlxsw_core_trap_register(mlxsw_sp->core,
4544913e 3877 &mlxsw_sp_listener[i],
14eeda99 3878 mlxsw_sp);
56ade8fe 3879 if (err)
4544913e 3880 goto err_listener_register;
56ade8fe 3881
56ade8fe
JP		 3882 }
3883 return 0;
3884
4544913e 3885err_listener_register:
56ade8fe 3886 for (i--; i >= 0; i--) {
14eeda99 3887 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3888 &mlxsw_sp_listener[i],
14eeda99 3889 mlxsw_sp);
56ade8fe
JP		 3890 }
3891 return err;
3892}
3893
3894static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3895{
56ade8fe
JP		 3896 int i;
3897
4544913e 3898 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
14eeda99 3899 mlxsw_core_trap_unregister(mlxsw_sp->core,
4544913e 3900 &mlxsw_sp_listener[i],
14eeda99 3901 mlxsw_sp);
56ade8fe
JP		 3902 }
3903}
3904
0d65fc13
JP		 3905static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3906{
3907 char slcr_pl[MLXSW_REG_SLCR_LEN];
ce0bd2b0 3908 int err;
0d65fc13
JP		 3909
3910 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3911 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3912 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3913 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3914 MLXSW_REG_SLCR_LAG_HASH_SIP |
3915 MLXSW_REG_SLCR_LAG_HASH_DIP |
3916 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3917 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3918 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
ce0bd2b0
NF		 3919 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3920 if (err)
3921 return err;
3922
c1a38311
JP		 3923 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3924 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
ce0bd2b0
NF		 3925 return -EIO;
3926
c1a38311 3927 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
ce0bd2b0
NF		 3928 sizeof(struct mlxsw_sp_upper),
3929 GFP_KERNEL);
3930 if (!mlxsw_sp->lags)
3931 return -ENOMEM;
3932
3933 return 0;
3934}
3935
3936static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3937{
3938 kfree(mlxsw_sp->lags);
0d65fc13
JP		 3939}
3940
9d87fcea
NF		 3941static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3942{
3943 char htgt_pl[MLXSW_REG_HTGT_LEN];
3944
579c82e4
NF		 3945 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3946 MLXSW_REG_HTGT_INVALID_POLICER,
3947 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3948 MLXSW_REG_HTGT_DEFAULT_TC);
9d87fcea
NF		 3949 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3950}
3951
c30f5d01
PM		 3952static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3953 unsigned long event, void *ptr);
3954
b2f10571 3955static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
56ade8fe
JP		 3956 const struct mlxsw_bus_info *mlxsw_bus_info)
3957{
b2f10571 3958 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe
JP		 3959 int err;
3960
3961 mlxsw_sp->core = mlxsw_core;
3962 mlxsw_sp->bus_info = mlxsw_bus_info;
3963
6b742199
YG		 3964 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3965 if (err) {
3966 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3967 return err;
3968 }
3969
56ade8fe
JP		 3970 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3971 if (err) {
3972 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3973 return err;
3974 }
3975
a875a2ee
IS		 3976 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3977 if (err) {
3978 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3979 return err;
3980 }
3981
a1107487 3982 err = mlxsw_sp_fids_init(mlxsw_sp);
56ade8fe 3983 if (err) {
a1107487 3984 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
a875a2ee 3985 goto err_fids_init;
56ade8fe
JP		 3986 }
3987
a1107487 3988 err = mlxsw_sp_traps_init(mlxsw_sp);
56ade8fe 3989 if (err) {
a1107487
IS		 3990 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3991 goto err_traps_init;
56ade8fe
JP		 3992 }
3993
3994 err = mlxsw_sp_buffers_init(mlxsw_sp);
3995 if (err) {
3996 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3997 goto err_buffers_init;
3998 }
3999
0d65fc13
JP		 4000 err = mlxsw_sp_lag_init(mlxsw_sp);
4001 if (err) {
4002 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
4003 goto err_lag_init;
4004 }
4005
56ade8fe
JP		 4006 err = mlxsw_sp_switchdev_init(mlxsw_sp);
4007 if (err) {
4008 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
4009 goto err_switchdev_init;
4010 }
4011
e2b2d35a
YG		 4012 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
4013 if (err) {
4014 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
4015 goto err_counter_pool_init;
4016 }
4017
d3b939b8
YG		 4018 err = mlxsw_sp_afa_init(mlxsw_sp);
4019 if (err) {
4020 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
4021 goto err_afa_init;
4022 }
4023
464dce18
IS		 4024 err = mlxsw_sp_router_init(mlxsw_sp);
4025 if (err) {
4026 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4027 goto err_router_init;
4028 }
4029
c30f5d01
PM		 4030 /* Initialize netdevice notifier after router is initialized, so that
4031 * the event handler can use router structures.
4032 */
4033 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4034 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4035 if (err) {
4036 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4037 goto err_netdev_notifier;
4038 }
4039
763b4b70
YG		 4040 err = mlxsw_sp_span_init(mlxsw_sp);
4041 if (err) {
4042 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4043 goto err_span_init;
4044 }
4045
22a67766
JP		 4046 err = mlxsw_sp_acl_init(mlxsw_sp);
4047 if (err) {
4048 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4049 goto err_acl_init;
4050 }
4051
230ead01
AS		 4052 err = mlxsw_sp_dpipe_init(mlxsw_sp);
4053 if (err) {
4054 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4055 goto err_dpipe_init;
4056 }
4057
bbf2a475
IS		 4058 err = mlxsw_sp_ports_create(mlxsw_sp);
4059 if (err) {
4060 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4061 goto err_ports_create;
4062 }
4063
56ade8fe
JP		 4064 return 0;
4065
bbf2a475 4066err_ports_create:
230ead01
AS		 4067 mlxsw_sp_dpipe_fini(mlxsw_sp);
4068err_dpipe_init:
22a67766
JP		 4069 mlxsw_sp_acl_fini(mlxsw_sp);
4070err_acl_init:
763b4b70
YG		 4071 mlxsw_sp_span_fini(mlxsw_sp);
4072err_span_init:
c30f5d01
PM		 4073 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4074err_netdev_notifier:
464dce18
IS		 4075 mlxsw_sp_router_fini(mlxsw_sp);
4076err_router_init:
d3b939b8
YG		 4077 mlxsw_sp_afa_fini(mlxsw_sp);
4078err_afa_init:
e2b2d35a
YG		 4079 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4080err_counter_pool_init:
bbf2a475 4081 mlxsw_sp_switchdev_fini(mlxsw_sp);
56ade8fe 4082err_switchdev_init:
ce0bd2b0 4083 mlxsw_sp_lag_fini(mlxsw_sp);
0d65fc13 4084err_lag_init:
0f433fa0 4085 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 4086err_buffers_init:
56ade8fe 4087 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487
IS		 4088err_traps_init:
4089 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee
IS		 4090err_fids_init:
4091 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 4092 return err;
4093}
4094
b2f10571 4095static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
56ade8fe 4096{
b2f10571 4097 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
56ade8fe 4098
bbf2a475 4099 mlxsw_sp_ports_remove(mlxsw_sp);
230ead01 4100 mlxsw_sp_dpipe_fini(mlxsw_sp);
22a67766 4101 mlxsw_sp_acl_fini(mlxsw_sp);
763b4b70 4102 mlxsw_sp_span_fini(mlxsw_sp);
c30f5d01 4103 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
464dce18 4104 mlxsw_sp_router_fini(mlxsw_sp);
d3b939b8 4105 mlxsw_sp_afa_fini(mlxsw_sp);
e2b2d35a 4106 mlxsw_sp_counter_pool_fini(mlxsw_sp);
56ade8fe 4107 mlxsw_sp_switchdev_fini(mlxsw_sp);
ce0bd2b0 4108 mlxsw_sp_lag_fini(mlxsw_sp);
5113bfdb 4109 mlxsw_sp_buffers_fini(mlxsw_sp);
56ade8fe 4110 mlxsw_sp_traps_fini(mlxsw_sp);
a1107487 4111 mlxsw_sp_fids_fini(mlxsw_sp);
a875a2ee 4112 mlxsw_sp_kvdl_fini(mlxsw_sp);
56ade8fe
JP		 4113}
4114
159fe88e 4115static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
56ade8fe
JP		 4116 .used_max_vepa_channels = 1,
4117 .max_vepa_channels = 0,
56ade8fe 4118 .used_max_mid = 1,
53ae6283 4119 .max_mid = MLXSW_SP_MID_MAX,
56ade8fe
JP		 4120 .used_max_pgt = 1,
4121 .max_pgt = 0,
56ade8fe
JP		 4122 .used_flood_tables = 1,
4123 .used_flood_mode = 1,
4124 .flood_mode = 3,
71c365bd 4125 .max_fid_offset_flood_tables = 3,
56ade8fe 4126 .fid_offset_flood_table_size = VLAN_N_VID - 1,
71c365bd 4127 .max_fid_flood_tables = 3,
a1107487 4128 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
56ade8fe
JP		 4129 .used_max_ib_mc = 1,
4130 .max_ib_mc = 0,
4131 .used_max_pkey = 1,
4132 .max_pkey = 0,
403547d3
NF		 4133 .used_kvd_split_data = 1,
4134 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
f11fbaf8
IS		 4135 .kvd_hash_single_parts = 59,
4136 .kvd_hash_double_parts = 41,
c6022427 4137 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
56ade8fe
JP		 4138 .swid_config = {
4139 {
4140 .used_type = 1,
4141 .type = MLXSW_PORT_SWID_TYPE_ETH,
4142 }
4143 },
57d316ba 4144 .resource_query_enable = 1,
56ade8fe
JP		 4145};
4146
ef3116e5
AS		 4147static bool
4148mlxsw_sp_resource_kvd_granularity_validate(struct netlink_ext_ack *extack,
4149 u64 size)
4150{
4151 const struct mlxsw_config_profile *profile;
4152
4153 profile = &mlxsw_sp_config_profile;
4154 if (size % profile->kvd_hash_granularity) {
4155 NL_SET_ERR_MSG_MOD(extack, "resource set with wrong granularity");
4156 return false;
4157 }
4158 return true;
4159}
4160
4161static int
4162mlxsw_sp_resource_kvd_size_validate(struct devlink *devlink, u64 size,
4163 struct netlink_ext_ack *extack)
4164{
4165 NL_SET_ERR_MSG_MOD(extack, "kvd size cannot be changed");
4166 return -EINVAL;
4167}
4168
4169static int
4170mlxsw_sp_resource_kvd_linear_size_validate(struct devlink *devlink, u64 size,
4171 struct netlink_ext_ack *extack)
4172{
4173 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4174 return -EINVAL;
4175
4176 return 0;
4177}
4178
4179static int
4180mlxsw_sp_resource_kvd_hash_single_size_validate(struct devlink *devlink, u64 size,
4181 struct netlink_ext_ack *extack)
4182{
4183 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4184
4185 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4186 return -EINVAL;
4187
4188 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE)) {
4189 NL_SET_ERR_MSG_MOD(extack, "hash single size is smaller than minimum");
4190 return -EINVAL;
4191 }
4192 return 0;
4193}
4194
4195static int
4196mlxsw_sp_resource_kvd_hash_double_size_validate(struct devlink *devlink, u64 size,
4197 struct netlink_ext_ack *extack)
4198{
4199 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4200
4201 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4202 return -EINVAL;
4203
4204 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) {
4205 NL_SET_ERR_MSG_MOD(extack, "hash double size is smaller than minimum");
4206 return -EINVAL;
4207 }
4208 return 0;
4209}
4210
afadc26b
AS		 4211static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
4212{
4213 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4214 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4215
4216 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
4217}
4218
ef3116e5
AS		 4219static struct devlink_resource_ops mlxsw_sp_resource_kvd_ops = {
4220 .size_validate = mlxsw_sp_resource_kvd_size_validate,
4221};
4222
4223static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
4224 .size_validate = mlxsw_sp_resource_kvd_linear_size_validate,
afadc26b 4225 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
ef3116e5
AS		 4226};
4227
4228static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_single_ops = {
4229 .size_validate = mlxsw_sp_resource_kvd_hash_single_size_validate,
4230};
4231
4232static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_double_ops = {
4233 .size_validate = mlxsw_sp_resource_kvd_hash_double_size_validate,
4234};
4235
ef3116e5 4236static void
77d27096
JP		 4237mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
4238 struct devlink_resource_size_params *kvd_size_params,
4239 struct devlink_resource_size_params *linear_size_params,
4240 struct devlink_resource_size_params *hash_double_size_params,
4241 struct devlink_resource_size_params *hash_single_size_params)
ef3116e5
AS		 4242{
4243 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4244 KVD_SINGLE_MIN_SIZE);
4245 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4246 KVD_DOUBLE_MIN_SIZE);
4247 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4248 u32 linear_size_min = 0;
4249
77d27096
JP		 4250 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
4251 MLXSW_SP_KVD_GRANULARITY,
4252 DEVLINK_RESOURCE_UNIT_ENTRY);
4253 devlink_resource_size_params_init(linear_size_params, linear_size_min,
4254 kvd_size - single_size_min -
4255 double_size_min,
4256 MLXSW_SP_KVD_GRANULARITY,
4257 DEVLINK_RESOURCE_UNIT_ENTRY);
4258 devlink_resource_size_params_init(hash_double_size_params,
4259 double_size_min,
4260 kvd_size - single_size_min -
4261 linear_size_min,
4262 MLXSW_SP_KVD_GRANULARITY,
4263 DEVLINK_RESOURCE_UNIT_ENTRY);
4264 devlink_resource_size_params_init(hash_single_size_params,
4265 single_size_min,
4266 kvd_size - double_size_min -
4267 linear_size_min,
4268 MLXSW_SP_KVD_GRANULARITY,
4269 DEVLINK_RESOURCE_UNIT_ENTRY);
ef3116e5
AS		 4270}
4271
4272static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
4273{
4274 struct devlink *devlink = priv_to_devlink(mlxsw_core);
77d27096
JP		 4275 struct devlink_resource_size_params hash_single_size_params;
4276 struct devlink_resource_size_params hash_double_size_params;
4277 struct devlink_resource_size_params linear_size_params;
4278 struct devlink_resource_size_params kvd_size_params;
ef3116e5
AS		 4279 u32 kvd_size, single_size, double_size, linear_size;
4280 const struct mlxsw_config_profile *profile;
4281 int err;
4282
4283 profile = &mlxsw_sp_config_profile;
4284 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4285 return -EIO;
4286
77d27096
JP		 4287 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
4288 &linear_size_params,
4289 &hash_double_size_params,
4290 &hash_single_size_params);
4291
ef3116e5
AS		 4292 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4293 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4294 true, kvd_size,
4295 MLXSW_SP_RESOURCE_KVD,
4296 DEVLINK_RESOURCE_ID_PARENT_TOP,
77d27096 4297 &kvd_size_params,
ef3116e5
AS		 4298 &mlxsw_sp_resource_kvd_ops);
4299 if (err)
4300 return err;
4301
4302 linear_size = profile->kvd_linear_size;
4303 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4304 false, linear_size,
4305 MLXSW_SP_RESOURCE_KVD_LINEAR,
4306 MLXSW_SP_RESOURCE_KVD,
77d27096 4307 &linear_size_params,
ef3116e5
AS		 4308 &mlxsw_sp_resource_kvd_linear_ops);
4309 if (err)
4310 return err;
4311
4312 double_size = kvd_size - linear_size;
4313 double_size *= profile->kvd_hash_double_parts;
4314 double_size /= profile->kvd_hash_double_parts +
4315 profile->kvd_hash_single_parts;
4316 double_size = rounddown(double_size, profile->kvd_hash_granularity);
4317 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4318 false, double_size,
4319 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4320 MLXSW_SP_RESOURCE_KVD,
77d27096 4321 &hash_double_size_params,
ef3116e5
AS		 4322 &mlxsw_sp_resource_kvd_hash_double_ops);
4323 if (err)
4324 return err;
4325
4326 single_size = kvd_size - double_size - linear_size;
4327 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4328 false, single_size,
4329 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4330 MLXSW_SP_RESOURCE_KVD,
77d27096 4331 &hash_single_size_params,
ef3116e5
AS		 4332 &mlxsw_sp_resource_kvd_hash_single_ops);
4333 if (err)
4334 return err;
4335
4336 return 0;
4337}
4338
e21d21ca
AS		 4339static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4340 const struct mlxsw_config_profile *profile,
4341 u64 *p_single_size, u64 *p_double_size,
4342 u64 *p_linear_size)
4343{
4344 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4345 u32 double_size;
4346 int err;
4347
4348 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4349 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4350 !profile->used_kvd_split_data)
4351 return -EIO;
4352
4353 /* The hash part is what left of the kvd without the
4354 * linear part. It is split to the single size and
4355 * double size by the parts ratio from the profile.
4356 * Both sizes must be a multiplications of the
4357 * granularity from the profile. In case the user
4358 * provided the sizes they are obtained via devlink.
4359 */
4360 err = devlink_resource_size_get(devlink,
4361 MLXSW_SP_RESOURCE_KVD_LINEAR,
4362 p_linear_size);
4363 if (err)
4364 *p_linear_size = profile->kvd_linear_size;
4365
4366 err = devlink_resource_size_get(devlink,
4367 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4368 p_double_size);
4369 if (err) {
4370 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4371 *p_linear_size;
4372 double_size *= profile->kvd_hash_double_parts;
4373 double_size /= profile->kvd_hash_double_parts +
4374 profile->kvd_hash_single_parts;
4375 *p_double_size = rounddown(double_size,
4376 profile->kvd_hash_granularity);
4377 }
4378
4379 err = devlink_resource_size_get(devlink,
4380 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4381 p_single_size);
4382 if (err)
4383 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4384 *p_double_size - *p_linear_size;
4385
4386 /* Check results are legal. */
4387 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4388 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4389 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4390 return -EIO;
4391
4392 return 0;
4393}
4394
56ade8fe 4395static struct mlxsw_driver mlxsw_sp_driver = {
1d20d23c 4396 .kind = mlxsw_sp_driver_name,
2d0ed39f
JP		 4397 .priv_size = sizeof(struct mlxsw_sp),
4398 .init = mlxsw_sp_init,
4399 .fini = mlxsw_sp_fini,
9d87fcea 4400 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
2d0ed39f
JP		 4401 .port_split = mlxsw_sp_port_split,
4402 .port_unsplit = mlxsw_sp_port_unsplit,
4403 .sb_pool_get = mlxsw_sp_sb_pool_get,
4404 .sb_pool_set = mlxsw_sp_sb_pool_set,
4405 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4406 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4407 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4408 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4409 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4410 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4411 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4412 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4413 .txhdr_construct = mlxsw_sp_txhdr_construct,
ef3116e5 4414 .resources_register = mlxsw_sp_resources_register,
e21d21ca 4415 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
2d0ed39f
JP		 4416 .txhdr_len = MLXSW_TXHDR_LEN,
4417 .profile = &mlxsw_sp_config_profile,
56ade8fe
JP		 4418};
4419
22a67766 4420bool mlxsw_sp_port_dev_check(const struct net_device *dev)
7ce856aa
JP		 4421{
4422 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4423}
4424
1182e536 4425static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
dd82364c 4426{
1182e536 4427 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
dd82364c
DA		 4428 int ret = 0;
4429
4430 if (mlxsw_sp_port_dev_check(lower_dev)) {
1182e536 4431 *p_mlxsw_sp_port = netdev_priv(lower_dev);
dd82364c
DA		 4432 ret = 1;
4433 }
4434
4435 return ret;
4436}
4437
c57529e1 4438struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
7ce856aa 4439{
1182e536 4440 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 4441
4442 if (mlxsw_sp_port_dev_check(dev))
4443 return netdev_priv(dev);
4444
1182e536
JP		 4445 mlxsw_sp_port = NULL;
4446 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
dd82364c 4447
1182e536 4448 return mlxsw_sp_port;
7ce856aa
JP		 4449}
4450
4724ba56 4451struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
7ce856aa
JP		 4452{
4453 struct mlxsw_sp_port *mlxsw_sp_port;
4454
4455 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4456 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4457}
4458
af061378 4459struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
7ce856aa 4460{
1182e536 4461 struct mlxsw_sp_port *mlxsw_sp_port;
7ce856aa
JP		 4462
4463 if (mlxsw_sp_port_dev_check(dev))
4464 return netdev_priv(dev);
4465
1182e536
JP		 4466 mlxsw_sp_port = NULL;
4467 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4468 &mlxsw_sp_port);
dd82364c 4469
1182e536 4470 return mlxsw_sp_port;
7ce856aa
JP		 4471}
4472
4473struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4474{
4475 struct mlxsw_sp_port *mlxsw_sp_port;
4476
4477 rcu_read_lock();
4478 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4479 if (mlxsw_sp_port)
4480 dev_hold(mlxsw_sp_port->dev);
4481 rcu_read_unlock();
4482 return mlxsw_sp_port;
4483}
4484
4485void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4486{
4487 dev_put(mlxsw_sp_port->dev);
4488}
4489
0d65fc13
JP		 4490static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4491{
4492 char sldr_pl[MLXSW_REG_SLDR_LEN];
4493
4494 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4495 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4496}
4497
4498static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4499{
4500 char sldr_pl[MLXSW_REG_SLDR_LEN];
4501
4502 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4503 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4504}
4505
4506static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4507 u16 lag_id, u8 port_index)
4508{
4509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4510 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4511
4512 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4513 lag_id, port_index);
4514 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4515}
4516
4517static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4518 u16 lag_id)
4519{
4520 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4521 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4522
4523 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4524 lag_id);
4525 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4526}
4527
4528static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4529 u16 lag_id)
4530{
4531 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4532 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4533
4534 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4535 lag_id);
4536 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4537}
4538
4539static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4540 u16 lag_id)
4541{
4542 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4543 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4544
4545 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4546 lag_id);
4547 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4548}
4549
4550static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4551 struct net_device *lag_dev,
4552 u16 *p_lag_id)
4553{
4554 struct mlxsw_sp_upper *lag;
4555 int free_lag_id = -1;
c1a38311 4556 u64 max_lag;
0d65fc13
JP		 4557 int i;
4558
c1a38311
JP		 4559 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4560 for (i = 0; i < max_lag; i++) {
0d65fc13
JP		 4561 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4562 if (lag->ref_count) {
4563 if (lag->dev == lag_dev) {
4564 *p_lag_id = i;
4565 return 0;
4566 }
4567 } else if (free_lag_id < 0) {
4568 free_lag_id = i;
4569 }
4570 }
4571 if (free_lag_id < 0)
4572 return -EBUSY;
4573 *p_lag_id = free_lag_id;
4574 return 0;
4575}
4576
4577static bool
4578mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4579 struct net_device *lag_dev,
e58376e1
DA		 4580 struct netdev_lag_upper_info *lag_upper_info,
4581 struct netlink_ext_ack *extack)
0d65fc13
JP		 4582{
4583 u16 lag_id;
4584
e58376e1
DA		 4585 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4586 NL_SET_ERR_MSG(extack,
4587 "spectrum: Exceeded number of supported LAG devices");
0d65fc13 4588 return false;
e58376e1
DA		 4589 }
4590 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4591 NL_SET_ERR_MSG(extack,
4592 "spectrum: LAG device using unsupported Tx type");
0d65fc13 4593 return false;
e58376e1 4594 }
0d65fc13
JP		 4595 return true;
4596}
4597
4598static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4599 u16 lag_id, u8 *p_port_index)
4600{
c1a38311 4601 u64 max_lag_members;
0d65fc13
JP		 4602 int i;
4603
c1a38311
JP		 4604 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4605 MAX_LAG_MEMBERS);
4606 for (i = 0; i < max_lag_members; i++) {
0d65fc13
JP		 4607 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4608 *p_port_index = i;
4609 return 0;
4610 }
4611 }
4612 return -EBUSY;
4613}
4614
4615static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4616 struct net_device *lag_dev)
4617{
4618 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
c57529e1 4619 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
0d65fc13
JP		 4620 struct mlxsw_sp_upper *lag;
4621 u16 lag_id;
4622 u8 port_index;
4623 int err;
4624
4625 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4626 if (err)
4627 return err;
4628 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4629 if (!lag->ref_count) {
4630 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4631 if (err)
4632 return err;
4633 lag->dev = lag_dev;
4634 }
4635
4636 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4637 if (err)
4638 return err;
4639 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4640 if (err)
4641 goto err_col_port_add;
4642 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4643 if (err)
4644 goto err_col_port_enable;
4645
4646 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4647 mlxsw_sp_port->local_port);
4648 mlxsw_sp_port->lag_id = lag_id;
4649 mlxsw_sp_port->lagged = 1;
4650 lag->ref_count++;
86bf95b3 4651
c57529e1
IS		 4652 /* Port is no longer usable as a router interface */
4653 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4654 if (mlxsw_sp_port_vlan->fid)
a1107487 4655 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
86bf95b3 4656
0d65fc13
JP		 4657 return 0;
4658
51554db2
IS		 4659err_col_port_enable:
4660 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13
JP		 4661err_col_port_add:
4662 if (!lag->ref_count)
4663 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4664 return err;
4665}
4666
82e6db03
IS		 4667static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4668 struct net_device *lag_dev)
0d65fc13
JP		 4669{
4670 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
0d65fc13 4671 u16 lag_id = mlxsw_sp_port->lag_id;
1c800759 4672 struct mlxsw_sp_upper *lag;
0d65fc13
JP		 4673
4674 if (!mlxsw_sp_port->lagged)
82e6db03 4675 return;
0d65fc13
JP		 4676 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4677 WARN_ON(lag->ref_count == 0);
4678
82e6db03
IS		 4679 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4680 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
0d65fc13 4681
c57529e1
IS		 4682 /* Any VLANs configured on the port are no longer valid */
4683 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4dc236c3 4684
fe3f6d14 4685 if (lag->ref_count == 1)
82e6db03 4686 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
0d65fc13
JP		 4687
4688 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4689 mlxsw_sp_port->local_port);
4690 mlxsw_sp_port->lagged = 0;
4691 lag->ref_count--;
86bf95b3 4692
c57529e1
IS		 4693 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4694 /* Make sure untagged frames are allowed to ingress */
4695 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
0d65fc13
JP		 4696}
4697
74581206
JP		 4698static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4699 u16 lag_id)
4700{
4701 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4702 char sldr_pl[MLXSW_REG_SLDR_LEN];
4703
4704 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4705 mlxsw_sp_port->local_port);
4706 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4707}
4708
4709static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4710 u16 lag_id)
4711{
4712 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4713 char sldr_pl[MLXSW_REG_SLDR_LEN];
4714
4715 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4716 mlxsw_sp_port->local_port);
4717 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4718}
4719
4720static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4721 bool lag_tx_enabled)
4722{
4723 if (lag_tx_enabled)
4724 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4725 mlxsw_sp_port->lag_id);
4726 else
4727 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4728 mlxsw_sp_port->lag_id);
4729}
4730
4731static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4732 struct netdev_lag_lower_state_info *info)
4733{
4734 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4735}
4736
2b94e58d
JP		 4737static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4738 bool enable)
4739{
4740 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4741 enum mlxsw_reg_spms_state spms_state;
4742 char *spms_pl;
4743 u16 vid;
4744 int err;
4745
4746 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4747 MLXSW_REG_SPMS_STATE_DISCARDING;
4748
4749 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4750 if (!spms_pl)
4751 return -ENOMEM;
4752 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4753
4754 for (vid = 0; vid < VLAN_N_VID; vid++)
4755 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4756
4757 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4758 kfree(spms_pl);
4759 return err;
4760}
4761
4762static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4763{
fccff086 4764 u16 vid = 1;
2b94e58d
JP		 4765 int err;
4766
4aafc368 4767 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
2b94e58d
JP		 4768 if (err)
4769 return err;
4aafc368
IS		 4770 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4771 if (err)
4772 goto err_port_stp_set;
2b94e58d
JP		 4773 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4774 true, false);
4775 if (err)
4776 goto err_port_vlan_set;
fccff086
YM		 4777
4778 for (; vid <= VLAN_N_VID - 1; vid++) {
4779 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4780 vid, false);
4781 if (err)
4782 goto err_vid_learning_set;
4783 }
4784
2b94e58d
JP		 4785 return 0;
4786
fccff086
YM		 4787err_vid_learning_set:
4788 for (vid--; vid >= 1; vid--)
4789 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
2b94e58d
JP		 4790err_port_vlan_set:
4791 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368
IS		 4792err_port_stp_set:
4793 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4794 return err;
4795}
4796
4797static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4798{
fccff086
YM		 4799 u16 vid;
4800
4801 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4802 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4803 vid, true);
4804
2b94e58d
JP		 4805 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4806 false, false);
4807 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4aafc368 4808 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2b94e58d
JP		 4809}
4810
f0cebd81
IS		 4811static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4812 struct net_device *dev,
74581206 4813 unsigned long event, void *ptr)
56ade8fe 4814{
56ade8fe
JP		 4815 struct netdev_notifier_changeupper_info *info;
4816 struct mlxsw_sp_port *mlxsw_sp_port;
e58376e1 4817 struct netlink_ext_ack *extack;
56ade8fe
JP		 4818 struct net_device *upper_dev;
4819 struct mlxsw_sp *mlxsw_sp;
80bedf1a 4820 int err = 0;
56ade8fe 4821
56ade8fe
JP		 4822 mlxsw_sp_port = netdev_priv(dev);
4823 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4824 info = ptr;
e58376e1 4825 extack = netdev_notifier_info_to_extack(&info->info);
56ade8fe
JP		 4826
4827 switch (event) {
4828 case NETDEV_PRECHANGEUPPER:
4829 upper_dev = info->upper_dev;
59fe9b3f
IS		 4830 if (!is_vlan_dev(upper_dev) &&
4831 !netif_is_lag_master(upper_dev) &&
7179eb5a 4832 !netif_is_bridge_master(upper_dev) &&
e58376e1
DA		 4833 !netif_is_ovs_master(upper_dev)) {
4834 NL_SET_ERR_MSG(extack,
4835 "spectrum: Unknown upper device type");
59fe9b3f 4836 return -EINVAL;
e58376e1 4837 }
6ec43904 4838 if (!info->linking)
0d65fc13 4839 break;
90045fc9
IS		 4840 if (netdev_has_any_upper_dev(upper_dev) &&
4841 (!netif_is_bridge_master(upper_dev) ||
4842 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4843 upper_dev))) {
e58376e1
DA		 4844 NL_SET_ERR_MSG(extack,
4845 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4846 return -EINVAL;
e58376e1 4847 }
0d65fc13
JP		 4848 if (netif_is_lag_master(upper_dev) &&
4849 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
e58376e1 4850 info->upper_info, extack))
80bedf1a 4851 return -EINVAL;
e58376e1
DA		 4852 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4853 NL_SET_ERR_MSG(extack,
4854 "spectrum: Master device is a LAG master and this device has a VLAN");
6ec43904 4855 return -EINVAL;
e58376e1 4856 }
6ec43904 4857 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
e58376e1
DA		 4858 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4859 NL_SET_ERR_MSG(extack,
4860 "spectrum: Can not put a VLAN on a LAG port");
6ec43904 4861 return -EINVAL;
e58376e1
DA		 4862 }
4863 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4864 NL_SET_ERR_MSG(extack,
4865 "spectrum: Master device is an OVS master and this device has a VLAN");
2b94e58d 4866 return -EINVAL;
e58376e1
DA		 4867 }
4868 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4869 NL_SET_ERR_MSG(extack,
4870 "spectrum: Can not put a VLAN on an OVS port");
2b94e58d 4871 return -EINVAL;
e58376e1 4872 }
56ade8fe
JP		 4873 break;
4874 case NETDEV_CHANGEUPPER:
4875 upper_dev = info->upper_dev;
c57529e1 4876 if (netif_is_bridge_master(upper_dev)) {
7117a570
IS		 4877 if (info->linking)
4878 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
f0cebd81 4879 lower_dev,
9b63ef88
IS		 4880 upper_dev,
4881 extack);
7117a570 4882 else
f0cebd81
IS		 4883 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4884 lower_dev,
4885 upper_dev);
0d65fc13 4886 } else if (netif_is_lag_master(upper_dev)) {
80bedf1a 4887 if (info->linking)
0d65fc13
JP		 4888 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4889 upper_dev);
80bedf1a 4890 else
82e6db03
IS		 4891 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4892 upper_dev);
2b94e58d
JP		 4893 } else if (netif_is_ovs_master(upper_dev)) {
4894 if (info->linking)
4895 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4896 else
4897 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
56ade8fe
JP		 4898 }
4899 break;
4900 }
4901
80bedf1a 4902 return err;
56ade8fe
JP		 4903}
4904
74581206
JP		 4905static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4906 unsigned long event, void *ptr)
4907{
4908 struct netdev_notifier_changelowerstate_info *info;
4909 struct mlxsw_sp_port *mlxsw_sp_port;
4910 int err;
4911
4912 mlxsw_sp_port = netdev_priv(dev);
4913 info = ptr;
4914
4915 switch (event) {
4916 case NETDEV_CHANGELOWERSTATE:
4917 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4918 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4919 info->lower_state_info);
4920 if (err)
4921 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4922 }
4923 break;
4924 }
4925
80bedf1a 4926 return 0;
74581206
JP		 4927}
4928
f0cebd81
IS		 4929static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4930 struct net_device *port_dev,
74581206
JP		 4931 unsigned long event, void *ptr)
4932{
4933 switch (event) {
4934 case NETDEV_PRECHANGEUPPER:
4935 case NETDEV_CHANGEUPPER:
f0cebd81
IS		 4936 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4937 event, ptr);
74581206 4938 case NETDEV_CHANGELOWERSTATE:
f0cebd81
IS		 4939 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4940 ptr);
74581206
JP		 4941 }
4942
80bedf1a 4943 return 0;
74581206
JP		 4944}
4945
0d65fc13
JP		 4946static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4947 unsigned long event, void *ptr)
4948{
4949 struct net_device *dev;
4950 struct list_head *iter;
4951 int ret;
4952
4953 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4954 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 4955 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4956 ptr);
80bedf1a 4957 if (ret)
0d65fc13
JP		 4958 return ret;
4959 }
4960 }
4961
80bedf1a 4962 return 0;
0d65fc13
JP		 4963}
4964
f0cebd81
IS		 4965static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4966 struct net_device *dev,
4967 unsigned long event, void *ptr,
4968 u16 vid)
26f0e7fb
IS		 4969{
4970 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
90045fc9 4971 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
26f0e7fb 4972 struct netdev_notifier_changeupper_info *info = ptr;
c1f2c6d0 4973 struct netlink_ext_ack *extack;
26f0e7fb 4974 struct net_device *upper_dev;
80bedf1a 4975 int err = 0;
26f0e7fb 4976
c1f2c6d0
IS		 4977 extack = netdev_notifier_info_to_extack(&info->info);
4978
26f0e7fb
IS		 4979 switch (event) {
4980 case NETDEV_PRECHANGEUPPER:
4981 upper_dev = info->upper_dev;
c1f2c6d0
IS		 4982 if (!netif_is_bridge_master(upper_dev)) {
4983 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
80bedf1a 4984 return -EINVAL;
c1f2c6d0 4985 }
25cc72a3
IS		 4986 if (!info->linking)
4987 break;
90045fc9
IS		 4988 if (netdev_has_any_upper_dev(upper_dev) &&
4989 (!netif_is_bridge_master(upper_dev) ||
4990 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4991 upper_dev))) {
c1f2c6d0 4992 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
25cc72a3 4993 return -EINVAL;
c1f2c6d0 4994 }
26f0e7fb
IS		 4995 break;
4996 case NETDEV_CHANGEUPPER:
4997 upper_dev = info->upper_dev;
1f88061e
IS		 4998 if (netif_is_bridge_master(upper_dev)) {
4999 if (info->linking)
c57529e1
IS		 5000 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
5001 vlan_dev,
9b63ef88
IS		 5002 upper_dev,
5003 extack);
1f88061e 5004 else
c57529e1
IS		 5005 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
5006 vlan_dev,
5007 upper_dev);
26f0e7fb 5008 } else {
1f88061e
IS		 5009 err = -EINVAL;
5010 WARN_ON(1);
26f0e7fb 5011 }
1f88061e 5012 break;
26f0e7fb
IS		 5013 }
5014
80bedf1a 5015 return err;
26f0e7fb
IS		 5016}
5017
f0cebd81
IS		 5018static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
5019 struct net_device *lag_dev,
5020 unsigned long event,
5021 void *ptr, u16 vid)
272c4470
IS		 5022{
5023 struct net_device *dev;
5024 struct list_head *iter;
5025 int ret;
5026
5027 netdev_for_each_lower_dev(lag_dev, dev, iter) {
5028 if (mlxsw_sp_port_dev_check(dev)) {
f0cebd81
IS		 5029 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
5030 event, ptr,
5031 vid);
80bedf1a 5032 if (ret)
272c4470
IS		 5033 return ret;
5034 }
5035 }
5036
80bedf1a 5037 return 0;
272c4470
IS		 5038}
5039
26f0e7fb
IS		 5040static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
5041 unsigned long event, void *ptr)
5042{
5043 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
5044 u16 vid = vlan_dev_vlan_id(vlan_dev);
5045
272c4470 5046 if (mlxsw_sp_port_dev_check(real_dev))
f0cebd81
IS		 5047 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5048 event, ptr, vid);
272c4470 5049 else if (netif_is_lag_master(real_dev))
f0cebd81
IS		 5050 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5051 real_dev, event,
5052 ptr, vid);
26f0e7fb 5053
80bedf1a 5054 return 0;
26f0e7fb
IS		 5055}
5056
b1e45526
IS		 5057static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
5058{
5059 struct netdev_notifier_changeupper_info *info = ptr;
5060
5061 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
5062 return false;
5063 return netif_is_l3_master(info->upper_dev);
5064}
5065
0063587d 5066static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
0d65fc13
JP		 5067 unsigned long event, void *ptr)
5068{
5069 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
0063587d 5070 struct mlxsw_sp *mlxsw_sp;
80bedf1a 5071 int err = 0;
0d65fc13 5072
0063587d 5073 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
796ec776
PM		 5074 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5075 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5076 event, ptr);
61481f2f
PM		 5077 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5078 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5079 event, ptr);
0063587d 5080 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
6e095fd4 5081 err = mlxsw_sp_netdevice_router_port_event(dev);
b1e45526
IS		 5082 else if (mlxsw_sp_is_vrf_event(event, ptr))
5083 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6e095fd4 5084 else if (mlxsw_sp_port_dev_check(dev))
f0cebd81 5085 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
80bedf1a
IS		 5086 else if (netif_is_lag_master(dev))
5087 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5088 else if (is_vlan_dev(dev))
5089 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
26f0e7fb 5090
80bedf1a 5091 return notifier_from_errno(err);
0d65fc13
JP		 5092}
5093
89d5dd2e
DA		 5094static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5095 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5096};
5097
99724c18
IS		 5098static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5099 .notifier_call = mlxsw_sp_inetaddr_event,
89d5dd2e
DA		 5100};
5101
5102static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5103 .notifier_call = mlxsw_sp_inet6addr_valid_event,
99724c18
IS		 5104};
5105
5ea1237f
AS		 5106static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5107 .notifier_call = mlxsw_sp_inet6addr_event,
5108};
5109
1d20d23c
JP		 5110static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
5111 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5112 {0, },
5113};
5114
5115static struct pci_driver mlxsw_sp_pci_driver = {
5116 .name = mlxsw_sp_driver_name,
5117 .id_table = mlxsw_sp_pci_id_table,
5118};
5119
56ade8fe
JP		 5120static int __init mlxsw_sp_module_init(void)
5121{
5122 int err;
5123
89d5dd2e 5124 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
99724c18 5125 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 5126 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5ea1237f 5127 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
e7322638 5128
56ade8fe
JP		 5129 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
5130 if (err)
5131 goto err_core_driver_register;
1d20d23c
JP		 5132
5133 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
5134 if (err)
5135 goto err_pci_driver_register;
5136
56ade8fe
JP		 5137 return 0;
5138
1d20d23c
JP		 5139err_pci_driver_register:
5140 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
56ade8fe 5141err_core_driver_register:
5ea1237f 5142 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 5143 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
de7d6295 5144 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 5145 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 5146 return err;
5147}
5148
5149static void __exit mlxsw_sp_module_exit(void)
5150{
1d20d23c 5151 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
56ade8fe 5152 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
5ea1237f 5153 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
89d5dd2e 5154 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
99724c18 5155 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
89d5dd2e 5156 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
56ade8fe
JP		 5157}
5158
5159module_init(mlxsw_sp_module_init);
5160module_exit(mlxsw_sp_module_exit);
5161
5162MODULE_LICENSE("Dual BSD/GPL");
5163MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5164MODULE_DESCRIPTION("Mellanox Spectrum driver");
1d20d23c 5165MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
6b742199 5166MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);
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