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mlxsw: spectrum: Check if port is vPort using its VID
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1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
7f71eb46 44#include <linux/list.h>
8e8dfe9f 45#include <linux/dcbnl.h>
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46#include <net/switchdev.h>
47
3a49b4fd 48#include "port.h"
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49#include "core.h"
50
51#define MLXSW_SP_VFID_BASE VLAN_N_VID
7f71eb46 52#define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
b555cf4a 53#define MLXSW_SP_VFID_BR_MAX 6144 /* Bridged VLAN interfaces */
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54#define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
55
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56#define MLXSW_SP_LAG_MAX 64
57#define MLXSW_SP_PORT_PER_LAG_MAX 16
56ade8fe 58
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59#define MLXSW_SP_MID_MAX 7000
60
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61#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
62
63#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
64
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65#define MLXSW_SP_BYTES_PER_CELL 96
66
67#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
0f433fa0 68#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
1a198449 69
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70/* Maximum delay buffer needed in case of PAUSE frames, in cells.
71 * Assumes 100m cable and maximum MTU.
72 */
73#define MLXSW_SP_PAUSE_DELAY 612
74
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75#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
76
77static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
78{
79 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
80 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
81}
82
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83struct mlxsw_sp_port;
84
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85struct mlxsw_sp_upper {
86 struct net_device *dev;
87 unsigned int ref_count;
88};
89
d0ec875a 90struct mlxsw_sp_fid {
7f71eb46 91 struct list_head list;
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92 unsigned int ref_count;
93 struct net_device *dev;
94 u16 fid;
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95 u16 vid;
96};
97
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98struct mlxsw_sp_mid {
99 struct list_head list;
100 unsigned char addr[ETH_ALEN];
101 u16 vid;
102 u16 mid;
103 unsigned int ref_count;
104};
105
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106static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
107{
108 return MLXSW_SP_VFID_BASE + vfid;
109}
110
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111static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
112{
113 return fid - MLXSW_SP_VFID_BASE;
114}
115
116static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
117{
118 return fid >= MLXSW_SP_VFID_BASE;
119}
120
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121struct mlxsw_sp_sb_pr {
122 enum mlxsw_reg_sbpr_mode mode;
123 u32 size;
124};
125
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126struct mlxsw_cp_sb_occ {
127 u32 cur;
128 u32 max;
129};
130
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131struct mlxsw_sp_sb_cm {
132 u32 min_buff;
133 u32 max_buff;
134 u8 pool;
2d0ed39f 135 struct mlxsw_cp_sb_occ occ;
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136};
137
138struct mlxsw_sp_sb_pm {
139 u32 min_buff;
140 u32 max_buff;
2d0ed39f 141 struct mlxsw_cp_sb_occ occ;
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142};
143
144#define MLXSW_SP_SB_POOL_COUNT 4
145#define MLXSW_SP_SB_TC_COUNT 8
146
147struct mlxsw_sp_sb {
148 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
149 struct {
150 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
151 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
152 } ports[MLXSW_PORT_MAX_PORTS];
153};
154
56ade8fe 155struct mlxsw_sp {
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156 struct {
157 struct list_head list;
d8651fd8 158 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_PORT_MAX);
7f71eb46 159 } port_vfids;
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160 struct {
161 struct list_head list;
d8651fd8 162 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_BR_MAX);
26f0e7fb 163 } br_vfids;
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164 struct {
165 struct list_head list;
d8651fd8 166 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
3a49b4fd 167 } br_mids;
14d39461 168 struct list_head fids; /* VLAN-aware bridge FIDs */
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169 struct mlxsw_sp_port **ports;
170 struct mlxsw_core *core;
171 const struct mlxsw_bus_info *bus_info;
172 unsigned char base_mac[ETH_ALEN];
173 struct {
174 struct delayed_work dw;
175#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
176 unsigned int interval; /* ms */
177 } fdb_notify;
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178#define MLXSW_SP_MIN_AGEING_TIME 10
179#define MLXSW_SP_MAX_AGEING_TIME 1000000
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180#define MLXSW_SP_DEFAULT_AGEING_TIME 300
181 u32 ageing_time;
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182 struct mlxsw_sp_upper master_bridge;
183 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
558c2d5e 184 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
078f9c71 185 struct mlxsw_sp_sb sb;
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186};
187
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188static inline struct mlxsw_sp_upper *
189mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
190{
191 return &mlxsw_sp->lags[lag_id];
192}
193
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194struct mlxsw_sp_port_pcpu_stats {
195 u64 rx_packets;
196 u64 rx_bytes;
197 u64 tx_packets;
198 u64 tx_bytes;
199 struct u64_stats_sync syncp;
200 u32 tx_dropped;
201};
202
203struct mlxsw_sp_port {
932762b6 204 struct mlxsw_core_port core_port; /* must be first */
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205 struct net_device *dev;
206 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
207 struct mlxsw_sp *mlxsw_sp;
208 u8 local_port;
209 u8 stp_state;
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210 u8 learning:1,
211 learning_sync:1,
0293038e 212 uc_flood:1,
0d65fc13 213 bridged:1,
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214 lagged:1,
215 split:1;
56ade8fe 216 u16 pvid;
0d65fc13 217 u16 lag_id;
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218 struct {
219 struct list_head list;
d0ec875a 220 struct mlxsw_sp_fid *f;
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221 u16 vid;
222 } vport;
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223 struct {
224 u8 tx_pause:1,
225 rx_pause:1;
226 } link;
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227 struct {
228 struct ieee_ets *ets;
cc7cf517 229 struct ieee_maxrate *maxrate;
d81a6bdb 230 struct ieee_pfc *pfc;
8e8dfe9f 231 } dcb;
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232 struct {
233 u8 module;
234 u8 width;
235 u8 lane;
236 } mapping;
56ade8fe 237 /* 802.1Q bridge VLANs */
bd40e9d6 238 unsigned long *active_vlans;
fc1273af 239 unsigned long *untagged_vlans;
56ade8fe 240 /* VLAN interfaces */
7f71eb46 241 struct list_head vports_list;
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242};
243
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244static inline bool
245mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
246{
247 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
248}
249
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250static inline struct mlxsw_sp_port *
251mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
252{
253 struct mlxsw_sp_port *mlxsw_sp_port;
254 u8 local_port;
255
256 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
257 lag_id, port_index);
258 mlxsw_sp_port = mlxsw_sp->ports[local_port];
259 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
260}
261
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262static inline struct net_device *
263mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
264{
d0ec875a 265 return mlxsw_sp_vport->vport.f->dev;
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266}
267
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268static inline u16
269mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
270{
271 return mlxsw_sp_vport->vport.vid;
272}
273
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274static inline bool
275mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
276{
277 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
278
279 return vid != 0;
280}
281
7f71eb46 282static inline u16
d0ec875a 283mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
7f71eb46 284{
d0ec875a 285 return mlxsw_sp_vport->vport.f->fid;
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286}
287
288static inline struct mlxsw_sp_port *
289mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
290{
291 struct mlxsw_sp_port *mlxsw_sp_vport;
292
293 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
294 vport.list) {
295 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
296 return mlxsw_sp_vport;
297 }
298
299 return NULL;
300}
301
aac78a44 302static inline struct mlxsw_sp_port *
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303mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
304 u16 fid)
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305{
306 struct mlxsw_sp_port *mlxsw_sp_vport;
307
308 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
309 vport.list) {
d0ec875a 310 if (mlxsw_sp_vport_fid_get(mlxsw_sp_vport) == fid)
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311 return mlxsw_sp_vport;
312 }
313
314 return NULL;
315}
316
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317enum mlxsw_sp_flood_table {
318 MLXSW_SP_FLOOD_TABLE_UC,
319 MLXSW_SP_FLOOD_TABLE_BM,
320};
321
322int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
0f433fa0 323void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
56ade8fe 324int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
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325int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
326 unsigned int sb_index, u16 pool_index,
327 struct devlink_sb_pool_info *pool_info);
328int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
329 unsigned int sb_index, u16 pool_index, u32 size,
330 enum devlink_sb_threshold_type threshold_type);
331int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
332 unsigned int sb_index, u16 pool_index,
333 u32 *p_threshold);
334int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
335 unsigned int sb_index, u16 pool_index,
336 u32 threshold);
337int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
338 unsigned int sb_index, u16 tc_index,
339 enum devlink_sb_pool_type pool_type,
340 u16 *p_pool_index, u32 *p_threshold);
341int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
342 unsigned int sb_index, u16 tc_index,
343 enum devlink_sb_pool_type pool_type,
344 u16 pool_index, u32 threshold);
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345int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
346 unsigned int sb_index);
347int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
348 unsigned int sb_index);
349int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
350 unsigned int sb_index, u16 pool_index,
351 u32 *p_cur, u32 *p_max);
352int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
353 unsigned int sb_index, u16 tc_index,
354 enum devlink_sb_pool_type pool_type,
355 u32 *p_cur, u32 *p_max);
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356
357int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
358void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
359int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
360void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
361void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
362int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
363 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
364 u16 vid);
365int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
366 u16 vid_end, bool is_member, bool untagged);
367int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
368 u16 vid);
369int mlxsw_sp_port_kill_vid(struct net_device *dev,
370 __be16 __always_unused proto, u16 vid);
e6060027 371int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
47a0a9e6 372 bool set);
4dc236c3 373void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
28a01d2d 374int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
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375int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
376 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
377 bool dwrr, u8 dwrr_weight);
378int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
379 u8 switch_prio, u8 tclass);
380int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
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381 u8 *prio_tc, bool pause_en,
382 struct ieee_pfc *my_pfc);
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383int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
384 enum mlxsw_reg_qeec_hr hr, u8 index,
385 u8 next_index, u32 maxrate);
56ade8fe 386
f00817df
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387#ifdef CONFIG_MLXSW_SPECTRUM_DCB
388
389int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
390void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
391
392#else
393
394static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
395{
396 return 0;
397}
398
399static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
400{}
401
402#endif
403
56ade8fe 404#endif