[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum_buffers.c

/*
 * drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of the copyright holders nor the names of its
 *    contributors may be used to endorse or promote products derived from
 *    this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/dcbnl.h>

#include "spectrum.h"
#include "core.h"
#include "port.h"
#include "reg.h"

struct mlxsw_sp_pb {
	u8 index;
	u16 size;
};

#define MLXSW_SP_PB(_index, _size)	\
	{				\
		.index = _index,	\
		.size = _size,		\
	}

static const struct mlxsw_sp_pb mlxsw_sp_pbs[] = {
	MLXSW_SP_PB(0, 208),
	MLXSW_SP_PB(1, 208),
	MLXSW_SP_PB(2, 208),
	MLXSW_SP_PB(3, 208),
	MLXSW_SP_PB(4, 208),
	MLXSW_SP_PB(5, 208),
	MLXSW_SP_PB(6, 208),
	MLXSW_SP_PB(7, 208),
	MLXSW_SP_PB(9, 208),
};

#define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)

static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
	char pbmc_pl[MLXSW_REG_PBMC_LEN];
	int i;

	mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
			    0xffff, 0xffff / 2);
	for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
		const struct mlxsw_sp_pb *pb;

		pb = &mlxsw_sp_pbs[i];
		mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pb->index, pb->size);
	}
	return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
			       MLXSW_REG(pbmc), pbmc_pl);
}

static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
	char pptb_pl[MLXSW_REG_PPTB_LEN];
	int i;

	mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
		mlxsw_reg_pptb_prio_to_buff_set(pptb_pl, i, 0);
	return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
			       pptb_pl);
}

static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
	int err;

	err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
	if (err)
		return err;
	return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
}

struct mlxsw_sp_sb_pool {
	u8 pool;
	enum mlxsw_reg_sbpr_dir dir;
	enum mlxsw_reg_sbpr_mode mode;
	u32 size;
};

#define MLXSW_SP_SB_POOL_INGRESS_SIZE				\
	(15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS))
#define MLXSW_SP_SB_POOL_EGRESS_SIZE				\
	(14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS))

#define MLXSW_SP_SB_POOL(_pool, _dir, _mode, _size)		\
	{							\
		.pool = _pool,					\
		.dir = _dir,					\
		.mode = _mode,					\
		.size = _size,					\
	}

#define MLXSW_SP_SB_POOL_INGRESS(_pool, _size)			\
	MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_INGRESS,	\
			 MLXSW_REG_SBPR_MODE_DYNAMIC, _size)

#define MLXSW_SP_SB_POOL_EGRESS(_pool, _size)			\
	MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_EGRESS,	\
			 MLXSW_REG_SBPR_MODE_DYNAMIC, _size)

static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = {
	MLXSW_SP_SB_POOL_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_INGRESS_SIZE)),
	MLXSW_SP_SB_POOL_INGRESS(1, 0),
	MLXSW_SP_SB_POOL_INGRESS(2, 0),
	MLXSW_SP_SB_POOL_INGRESS(3, 0),
	MLXSW_SP_SB_POOL_EGRESS(0, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_EGRESS_SIZE)),
	MLXSW_SP_SB_POOL_EGRESS(1, 0),
	MLXSW_SP_SB_POOL_EGRESS(2, 0),
	MLXSW_SP_SB_POOL_EGRESS(2, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_EGRESS_SIZE)),
};

#define MLXSW_SP_SB_POOLS_LEN ARRAY_SIZE(mlxsw_sp_sb_pools)

static int mlxsw_sp_sb_pools_init(struct mlxsw_sp *mlxsw_sp)
{
	char sbpr_pl[MLXSW_REG_SBPR_LEN];
	int i;
	int err;

	for (i = 0; i < MLXSW_SP_SB_POOLS_LEN; i++) {
		const struct mlxsw_sp_sb_pool *pool;

		pool = &mlxsw_sp_sb_pools[i];
		mlxsw_reg_sbpr_pack(sbpr_pl, pool->pool, pool->dir,
				    pool->mode, pool->size);
		err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
		if (err)
			return err;
	}
	return 0;
}

struct mlxsw_sp_sb_cm {
	union {
		u8 pg;
		u8 tc;
	} u;
	enum mlxsw_reg_sbcm_dir dir;
	u32 min_buff;
	u32 max_buff;
	u8 pool;
};

#define MLXSW_SP_SB_CM(_pg_tc, _dir, _min_buff, _max_buff, _pool)	\
	{								\
		.u.pg = _pg_tc,						\
		.dir = _dir,						\
		.min_buff = _min_buff,					\
		.max_buff = _max_buff,					\
		.pool = _pool,						\
	}

#define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff)		\
	MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBCM_DIR_INGRESS,			\
		       _min_buff, _max_buff, 0)

#define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff)		\
	MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS,			\
		       _min_buff, _max_buff, 0)

#define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc)				\
	MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, 104, 2, 3)

static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = {
	MLXSW_SP_SB_CM_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(10000), 8),
	MLXSW_SP_SB_CM_INGRESS(1, 0, 0),
	MLXSW_SP_SB_CM_INGRESS(2, 0, 0),
	MLXSW_SP_SB_CM_INGRESS(3, 0, 0),
	MLXSW_SP_SB_CM_INGRESS(4, 0, 0),
	MLXSW_SP_SB_CM_INGRESS(5, 0, 0),
	MLXSW_SP_SB_CM_INGRESS(6, 0, 0),
	MLXSW_SP_SB_CM_INGRESS(7, 0, 0),
	MLXSW_SP_SB_CM_INGRESS(9, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff),
	MLXSW_SP_SB_CM_EGRESS(0, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(1, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(2, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(3, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(4, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(5, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(6, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(7, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	MLXSW_SP_SB_CM_EGRESS(8, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(9, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(10, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(11, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(12, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(13, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(14, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(15, 0, 0),
	MLXSW_SP_SB_CM_EGRESS(16, 1, 0xff),
};

#define MLXSW_SP_SB_CMS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms)

static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(0),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(1),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(2),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(3),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(4),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(5),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(6),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(7),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(8),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(9),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(10),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(11),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(12),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(13),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(14),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(15),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(16),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(17),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(18),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(19),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(20),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(21),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(22),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(23),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(24),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(25),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(26),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(27),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(28),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(29),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(30),
	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(31),
};

#define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
	ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)

static int mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
				const struct mlxsw_sp_sb_cm *cms,
				size_t cms_len)
{
	char sbcm_pl[MLXSW_REG_SBCM_LEN];
	int i;
	int err;

	for (i = 0; i < cms_len; i++) {
		const struct mlxsw_sp_sb_cm *cm;

		cm = &cms[i];
		mlxsw_reg_sbcm_pack(sbcm_pl, local_port, cm->u.pg, cm->dir,
				    cm->min_buff, cm->max_buff, cm->pool);
		err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
		if (err)
			return err;
	}
	return 0;
}

static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
	return mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
				    mlxsw_sp_port->local_port, mlxsw_sp_sb_cms,
				    MLXSW_SP_SB_CMS_LEN);
}

static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
{
	return mlxsw_sp_sb_cms_init(mlxsw_sp, 0, mlxsw_sp_cpu_port_sb_cms,
				    MLXSW_SP_CPU_PORT_SB_MCS_LEN);
}

struct mlxsw_sp_sb_pm {
	u8 pool;
	enum mlxsw_reg_sbpm_dir dir;
	u32 min_buff;
	u32 max_buff;
};

#define MLXSW_SP_SB_PM(_pool, _dir, _min_buff, _max_buff)	\
	{							\
		.pool = _pool,					\
		.dir = _dir,					\
		.min_buff = _min_buff,				\
		.max_buff = _max_buff,				\
	}

#define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff)	\
	MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_INGRESS,	\
		       _min_buff, _max_buff)

#define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff)	\
	MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_EGRESS,	\
		       _min_buff, _max_buff)

static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
	MLXSW_SP_SB_PM_INGRESS(0, 0, 0xff),
	MLXSW_SP_SB_PM_INGRESS(1, 0, 0),
	MLXSW_SP_SB_PM_INGRESS(2, 0, 0),
	MLXSW_SP_SB_PM_INGRESS(3, 0, 0),
	MLXSW_SP_SB_PM_EGRESS(0, 0, 7),
	MLXSW_SP_SB_PM_EGRESS(1, 0, 0),
	MLXSW_SP_SB_PM_EGRESS(2, 0, 0),
	MLXSW_SP_SB_PM_EGRESS(3, 0, 0),
};

#define MLXSW_SP_SB_PMS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms)

static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
	char sbpm_pl[MLXSW_REG_SBPM_LEN];
	int i;
	int err;

	for (i = 0; i < MLXSW_SP_SB_PMS_LEN; i++) {
		const struct mlxsw_sp_sb_pm *pm;

		pm = &mlxsw_sp_sb_pms[i];
		mlxsw_reg_sbpm_pack(sbpm_pl, mlxsw_sp_port->local_port,
				    pm->pool, pm->dir,
				    pm->min_buff, pm->max_buff);
		err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
				      MLXSW_REG(sbpm), sbpm_pl);
		if (err)
			return err;
	}
	return 0;
}

struct mlxsw_sp_sb_mm {
	u8 prio;
	u32 min_buff;
	u32 max_buff;
	u8 pool;
};

#define MLXSW_SP_SB_MM(_prio, _min_buff, _max_buff, _pool)	\
	{							\
		.prio = _prio,					\
		.min_buff = _min_buff,				\
		.max_buff = _max_buff,				\
		.pool = _pool,					\
	}

static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
	MLXSW_SP_SB_MM(0, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(1, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(2, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(3, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(4, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(5, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(6, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(7, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(8, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(9, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(10, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(11, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(12, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(13, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	MLXSW_SP_SB_MM(14, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
};

#define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)

static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
{
	char sbmm_pl[MLXSW_REG_SBMM_LEN];
	int i;
	int err;

	for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
		const struct mlxsw_sp_sb_mm *mc;

		mc = &mlxsw_sp_sb_mms[i];
		mlxsw_reg_sbmm_pack(sbmm_pl, mc->prio, mc->min_buff,
				    mc->max_buff, mc->pool);
		err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
		if (err)
			return err;
	}
	return 0;
}

int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
{
	int err;

	err = mlxsw_sp_sb_pools_init(mlxsw_sp);
	if (err)
		return err;
	err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
	if (err)
		return err;
	err = mlxsw_sp_sb_mms_init(mlxsw_sp);

	return err;
}

int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
	int err;

	err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
	if (err)
		return err;
	err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
	if (err)
		return err;
	err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);

	return err;
}
Commit	Line	Data
56ade8fe JP	1	/*
	2	* drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
	3	* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
	4	* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	*
	9	* 1. Redistributions of source code must retain the above copyright
	10	* notice, this list of conditions and the following disclaimer.
	11	* 2. Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	* 3. Neither the names of the copyright holders nor the names of its
	15	* contributors may be used to endorse or promote products derived from
	16	* this software without specific prior written permission.
	17	*
	18	* Alternatively, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") version 2 as published by the Free
	20	* Software Foundation.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	26	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	29	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	30	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	31	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	32	* POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/kernel.h>
	36	#include <linux/types.h>
dd6cb0f9	37	#include <linux/dcbnl.h>
56ade8fe JP	38
	39	#include "spectrum.h"
	40	#include "core.h"
	41	#include "port.h"
	42	#include "reg.h"
	43
	44	struct mlxsw_sp_pb {
	45	u8 index;
	46	u16 size;
	47	};
	48
	49	#define MLXSW_SP_PB(_index, _size) \
	50	{ \
	51	.index = _index, \
	52	.size = _size, \
	53	}
	54
	55	static const struct mlxsw_sp_pb mlxsw_sp_pbs[] = {
	56	MLXSW_SP_PB(0, 208),
	57	MLXSW_SP_PB(1, 208),
	58	MLXSW_SP_PB(2, 208),
	59	MLXSW_SP_PB(3, 208),
	60	MLXSW_SP_PB(4, 208),
	61	MLXSW_SP_PB(5, 208),
	62	MLXSW_SP_PB(6, 208),
	63	MLXSW_SP_PB(7, 208),
	64	MLXSW_SP_PB(9, 208),
	65	};
	66
	67	#define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
	68
	69	static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
	70	{
	71	char pbmc_pl[MLXSW_REG_PBMC_LEN];
	72	int i;
	73
	74	mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
	75	0xffff, 0xffff / 2);
	76	for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
	77	const struct mlxsw_sp_pb *pb;
	78
	79	pb = &mlxsw_sp_pbs[i];
	80	mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pb->index, pb->size);
	81	}
	82	return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
	83	MLXSW_REG(pbmc), pbmc_pl);
	84	}
	85
dd6cb0f9 IS	86	static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
	87	{
	88	char pptb_pl[MLXSW_REG_PPTB_LEN];
	89	int i;
	90
	91	mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
	92	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
	93	mlxsw_reg_pptb_prio_to_buff_set(pptb_pl, i, 0);
	94	return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
	95	pptb_pl);
	96	}
	97
	98	static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
	99	{
	100	int err;
	101
	102	err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
	103	if (err)
	104	return err;
	105	return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
	106	}
	107
56ade8fe JP	108	struct mlxsw_sp_sb_pool {
	109	u8 pool;
	110	enum mlxsw_reg_sbpr_dir dir;
	111	enum mlxsw_reg_sbpr_mode mode;
	112	u32 size;
	113	};
	114
	115	#define MLXSW_SP_SB_POOL_INGRESS_SIZE \
1a198449	116	(15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS))
56ade8fe	117	#define MLXSW_SP_SB_POOL_EGRESS_SIZE \
1a198449	118	(14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS))
56ade8fe JP	119
	120	#define MLXSW_SP_SB_POOL(_pool, _dir, _mode, _size) \
	121	{ \
	122	.pool = _pool, \
	123	.dir = _dir, \
	124	.mode = _mode, \
	125	.size = _size, \
	126	}
	127
	128	#define MLXSW_SP_SB_POOL_INGRESS(_pool, _size) \
	129	MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_INGRESS, \
	130	MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
	131
	132	#define MLXSW_SP_SB_POOL_EGRESS(_pool, _size) \
	133	MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_EGRESS, \
	134	MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
	135
	136	static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = {
1a198449	137	MLXSW_SP_SB_POOL_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_INGRESS_SIZE)),
56ade8fe JP	138	MLXSW_SP_SB_POOL_INGRESS(1, 0),
	139	MLXSW_SP_SB_POOL_INGRESS(2, 0),
	140	MLXSW_SP_SB_POOL_INGRESS(3, 0),
1a198449	141	MLXSW_SP_SB_POOL_EGRESS(0, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_EGRESS_SIZE)),
56ade8fe JP	142	MLXSW_SP_SB_POOL_EGRESS(1, 0),
56ade8fe JP	143	MLXSW_SP_SB_POOL_EGRESS(2, 0),
1a198449	144	MLXSW_SP_SB_POOL_EGRESS(2, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_EGRESS_SIZE)),
56ade8fe JP	145	};
	146
	147	#define MLXSW_SP_SB_POOLS_LEN ARRAY_SIZE(mlxsw_sp_sb_pools)
	148
	149	static int mlxsw_sp_sb_pools_init(struct mlxsw_sp *mlxsw_sp)
	150	{
	151	char sbpr_pl[MLXSW_REG_SBPR_LEN];
	152	int i;
	153	int err;
	154
	155	for (i = 0; i < MLXSW_SP_SB_POOLS_LEN; i++) {
	156	const struct mlxsw_sp_sb_pool *pool;
	157
	158	pool = &mlxsw_sp_sb_pools[i];
	159	mlxsw_reg_sbpr_pack(sbpr_pl, pool->pool, pool->dir,
	160	pool->mode, pool->size);
	161	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
	162	if (err)
	163	return err;
	164	}
	165	return 0;
	166	}
	167
	168	struct mlxsw_sp_sb_cm {
	169	union {
	170	u8 pg;
	171	u8 tc;
	172	} u;
	173	enum mlxsw_reg_sbcm_dir dir;
	174	u32 min_buff;
	175	u32 max_buff;
	176	u8 pool;
	177	};
	178
	179	#define MLXSW_SP_SB_CM(_pg_tc, _dir, _min_buff, _max_buff, _pool) \
	180	{ \
	181	.u.pg = _pg_tc, \
	182	.dir = _dir, \
	183	.min_buff = _min_buff, \
	184	.max_buff = _max_buff, \
	185	.pool = _pool, \
	186	}
	187
	188	#define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff) \
	189	MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBCM_DIR_INGRESS, \
	190	_min_buff, _max_buff, 0)
	191
	192	#define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff) \
	193	MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, \
	194	_min_buff, _max_buff, 0)
	195
	196	#define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc) \
	197	MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, 104, 2, 3)
	198
	199	static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = {
1a198449	200	MLXSW_SP_SB_CM_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(10000), 8),
56ade8fe JP	201	MLXSW_SP_SB_CM_INGRESS(1, 0, 0),
	202	MLXSW_SP_SB_CM_INGRESS(2, 0, 0),
	203	MLXSW_SP_SB_CM_INGRESS(3, 0, 0),
	204	MLXSW_SP_SB_CM_INGRESS(4, 0, 0),
	205	MLXSW_SP_SB_CM_INGRESS(5, 0, 0),
	206	MLXSW_SP_SB_CM_INGRESS(6, 0, 0),
	207	MLXSW_SP_SB_CM_INGRESS(7, 0, 0),
1a198449 IS	208	MLXSW_SP_SB_CM_INGRESS(9, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff),
	209	MLXSW_SP_SB_CM_EGRESS(0, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	210	MLXSW_SP_SB_CM_EGRESS(1, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	211	MLXSW_SP_SB_CM_EGRESS(2, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	212	MLXSW_SP_SB_CM_EGRESS(3, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	213	MLXSW_SP_SB_CM_EGRESS(4, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	214	MLXSW_SP_SB_CM_EGRESS(5, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	215	MLXSW_SP_SB_CM_EGRESS(6, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
	216	MLXSW_SP_SB_CM_EGRESS(7, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
56ade8fe JP	217	MLXSW_SP_SB_CM_EGRESS(8, 0, 0),
	218	MLXSW_SP_SB_CM_EGRESS(9, 0, 0),
	219	MLXSW_SP_SB_CM_EGRESS(10, 0, 0),
	220	MLXSW_SP_SB_CM_EGRESS(11, 0, 0),
	221	MLXSW_SP_SB_CM_EGRESS(12, 0, 0),
	222	MLXSW_SP_SB_CM_EGRESS(13, 0, 0),
	223	MLXSW_SP_SB_CM_EGRESS(14, 0, 0),
	224	MLXSW_SP_SB_CM_EGRESS(15, 0, 0),
	225	MLXSW_SP_SB_CM_EGRESS(16, 1, 0xff),
	226	};
	227
	228	#define MLXSW_SP_SB_CMS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms)
	229
	230	static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
	231	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(0),
	232	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(1),
	233	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(2),
	234	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(3),
	235	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(4),
	236	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(5),
	237	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(6),
	238	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(7),
	239	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(8),
	240	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(9),
	241	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(10),
	242	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(11),
	243	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(12),
	244	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(13),
	245	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(14),
	246	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(15),
	247	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(16),
	248	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(17),
	249	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(18),
	250	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(19),
	251	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(20),
	252	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(21),
	253	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(22),
	254	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(23),
	255	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(24),
	256	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(25),
	257	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(26),
	258	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(27),
	259	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(28),
	260	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(29),
	261	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(30),
	262	MLXSW_SP_CPU_PORT_SB_CM_EGRESS(31),
	263	};
	264
	265	#define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
	266	ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
	267
	268	static int mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
	269	const struct mlxsw_sp_sb_cm *cms,
	270	size_t cms_len)
	271	{
	272	char sbcm_pl[MLXSW_REG_SBCM_LEN];
	273	int i;
	274	int err;
	275
	276	for (i = 0; i < cms_len; i++) {
	277	const struct mlxsw_sp_sb_cm *cm;
	278
	279	cm = &cms[i];
	280	mlxsw_reg_sbcm_pack(sbcm_pl, local_port, cm->u.pg, cm->dir,
281	cm->min_buff, cm->max_buff, cm->pool);
282	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
283	if (err)
284	return err;
285	}
286	return 0;
287	}
288
289	static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
290	{
291	return mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
292	mlxsw_sp_port->local_port, mlxsw_sp_sb_cms,
293	MLXSW_SP_SB_CMS_LEN);
294	}
295
296	static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
297	{
298	return mlxsw_sp_sb_cms_init(mlxsw_sp, 0, mlxsw_sp_cpu_port_sb_cms,
299	MLXSW_SP_CPU_PORT_SB_MCS_LEN);
300	}
301
302	struct mlxsw_sp_sb_pm {
303	u8 pool;
304	enum mlxsw_reg_sbpm_dir dir;
305	u32 min_buff;
306	u32 max_buff;
307	};
308
309	#define MLXSW_SP_SB_PM(_pool, _dir, _min_buff, _max_buff) \
310	{ \
311	.pool = _pool, \
312	.dir = _dir, \
313	.min_buff = _min_buff, \
314	.max_buff = _max_buff, \
315	}
316
317	#define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff) \
318	MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_INGRESS, \
319	_min_buff, _max_buff)
320
321	#define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff) \
322	MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_EGRESS, \
323	_min_buff, _max_buff)
324
325	static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
326	MLXSW_SP_SB_PM_INGRESS(0, 0, 0xff),
327	MLXSW_SP_SB_PM_INGRESS(1, 0, 0),
328	MLXSW_SP_SB_PM_INGRESS(2, 0, 0),
329	MLXSW_SP_SB_PM_INGRESS(3, 0, 0),
330	MLXSW_SP_SB_PM_EGRESS(0, 0, 7),
331	MLXSW_SP_SB_PM_EGRESS(1, 0, 0),
332	MLXSW_SP_SB_PM_EGRESS(2, 0, 0),
333	MLXSW_SP_SB_PM_EGRESS(3, 0, 0),
334	};
335
336	#define MLXSW_SP_SB_PMS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms)
337
338	static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
339	{
340	char sbpm_pl[MLXSW_REG_SBPM_LEN];
341	int i;
342	int err;
343
344	for (i = 0; i < MLXSW_SP_SB_PMS_LEN; i++) {
345	const struct mlxsw_sp_sb_pm *pm;
346
347	pm = &mlxsw_sp_sb_pms[i];
348	mlxsw_reg_sbpm_pack(sbpm_pl, mlxsw_sp_port->local_port,
349	pm->pool, pm->dir,
350	pm->min_buff, pm->max_buff);
351	err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
352	MLXSW_REG(sbpm), sbpm_pl);
353	if (err)
354	return err;
355	}
356	return 0;
357	}
358
359	struct mlxsw_sp_sb_mm {
360	u8 prio;
361	u32 min_buff;
362	u32 max_buff;
363	u8 pool;
364	};
365
366	#define MLXSW_SP_SB_MM(_prio, _min_buff, _max_buff, _pool) \
367	{ \
368	.prio = _prio, \
369	.min_buff = _min_buff, \
370	.max_buff = _max_buff, \
371	.pool = _pool, \
372	}
373
374	static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
1a198449 IS	375	MLXSW_SP_SB_MM(0, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	376	MLXSW_SP_SB_MM(1, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	377	MLXSW_SP_SB_MM(2, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	378	MLXSW_SP_SB_MM(3, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	379	MLXSW_SP_SB_MM(4, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	380	MLXSW_SP_SB_MM(5, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	381	MLXSW_SP_SB_MM(6, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	382	MLXSW_SP_SB_MM(7, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	383	MLXSW_SP_SB_MM(8, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	384	MLXSW_SP_SB_MM(9, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	385	MLXSW_SP_SB_MM(10, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	386	MLXSW_SP_SB_MM(11, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	387	MLXSW_SP_SB_MM(12, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	388	MLXSW_SP_SB_MM(13, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
	389	MLXSW_SP_SB_MM(14, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
56ade8fe JP	390	};
	391
	392	#define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
	393
	394	static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
	395	{
	396	char sbmm_pl[MLXSW_REG_SBMM_LEN];
	397	int i;
	398	int err;
	399
	400	for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
	401	const struct mlxsw_sp_sb_mm *mc;
	402
	403	mc = &mlxsw_sp_sb_mms[i];
	404	mlxsw_reg_sbmm_pack(sbmm_pl, mc->prio, mc->min_buff,
	405	mc->max_buff, mc->pool);
	406	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
	407	if (err)
	408	return err;
	409	}
	410	return 0;
	411	}
	412
	413	int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
	414	{
	415	int err;
	416
	417	err = mlxsw_sp_sb_pools_init(mlxsw_sp);
	418	if (err)
	419	return err;
	420	err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
	421	if (err)
	422	return err;
	423	err = mlxsw_sp_sb_mms_init(mlxsw_sp);
	424
	425	return err;
	426	}
	427
	428	int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
	429	{
	430	int err;
	431
dd6cb0f9	432	err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
56ade8fe JP	433	if (err)
	434	return err;
	435	err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
	436	if (err)
	437	return err;
	438	err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
	439
	440	return err;
	441	}