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56ade8fe JP |
1 | /* |
2 | * drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c | |
3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> | |
5 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> | |
6 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. Neither the names of the copyright holders nor the names of its | |
17 | * contributors may be used to endorse or promote products derived from | |
18 | * this software without specific prior written permission. | |
19 | * | |
20 | * Alternatively, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") version 2 as published by the Free | |
22 | * Software Foundation. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
34 | * POSSIBILITY OF SUCH DAMAGE. | |
35 | */ | |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/types.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/etherdevice.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/skbuff.h> | |
44 | #include <linux/if_vlan.h> | |
45 | #include <linux/if_bridge.h> | |
46 | #include <linux/workqueue.h> | |
47 | #include <linux/jiffies.h> | |
48 | #include <net/switchdev.h> | |
49 | ||
50 | #include "spectrum.h" | |
51 | #include "core.h" | |
52 | #include "reg.h" | |
53 | ||
54 | static int mlxsw_sp_port_attr_get(struct net_device *dev, | |
55 | struct switchdev_attr *attr) | |
56 | { | |
57 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
58 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
59 | ||
60 | switch (attr->id) { | |
61 | case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: | |
62 | attr->u.ppid.id_len = sizeof(mlxsw_sp->base_mac); | |
63 | memcpy(&attr->u.ppid.id, &mlxsw_sp->base_mac, | |
64 | attr->u.ppid.id_len); | |
65 | break; | |
66 | case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: | |
67 | attr->u.brport_flags = | |
68 | (mlxsw_sp_port->learning ? BR_LEARNING : 0) | | |
0293038e IS |
69 | (mlxsw_sp_port->learning_sync ? BR_LEARNING_SYNC : 0) | |
70 | (mlxsw_sp_port->uc_flood ? BR_FLOOD : 0); | |
56ade8fe JP |
71 | break; |
72 | default: | |
73 | return -EOPNOTSUPP; | |
74 | } | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
80 | u8 state) | |
81 | { | |
82 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
83 | enum mlxsw_reg_spms_state spms_state; | |
84 | char *spms_pl; | |
85 | u16 vid; | |
86 | int err; | |
87 | ||
88 | switch (state) { | |
89 | case BR_STATE_DISABLED: /* fall-through */ | |
90 | case BR_STATE_FORWARDING: | |
91 | spms_state = MLXSW_REG_SPMS_STATE_FORWARDING; | |
92 | break; | |
93 | case BR_STATE_LISTENING: /* fall-through */ | |
94 | case BR_STATE_LEARNING: | |
95 | spms_state = MLXSW_REG_SPMS_STATE_LEARNING; | |
96 | break; | |
97 | case BR_STATE_BLOCKING: | |
98 | spms_state = MLXSW_REG_SPMS_STATE_DISCARDING; | |
99 | break; | |
100 | default: | |
101 | BUG(); | |
102 | } | |
103 | ||
104 | spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); | |
105 | if (!spms_pl) | |
106 | return -ENOMEM; | |
107 | mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); | |
108 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) | |
109 | mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); | |
110 | ||
111 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); | |
112 | kfree(spms_pl); | |
113 | return err; | |
114 | } | |
115 | ||
116 | static int mlxsw_sp_port_attr_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
117 | struct switchdev_trans *trans, | |
118 | u8 state) | |
119 | { | |
120 | if (switchdev_trans_ph_prepare(trans)) | |
121 | return 0; | |
122 | ||
123 | mlxsw_sp_port->stp_state = state; | |
124 | return mlxsw_sp_port_stp_state_set(mlxsw_sp_port, state); | |
125 | } | |
126 | ||
0293038e | 127 | static int __mlxsw_sp_port_flood_set(struct mlxsw_sp_port *mlxsw_sp_port, |
c06a94ef | 128 | u16 idx_begin, u16 idx_end, bool set, |
0293038e IS |
129 | bool only_uc) |
130 | { | |
131 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
7f71eb46 IS |
132 | u16 local_port = mlxsw_sp_port->local_port; |
133 | enum mlxsw_flood_table_type table_type; | |
c06a94ef | 134 | u16 range = idx_end - idx_begin + 1; |
0293038e IS |
135 | char *sftr_pl; |
136 | int err; | |
137 | ||
7f71eb46 IS |
138 | if (mlxsw_sp_port_is_vport(mlxsw_sp_port)) { |
139 | table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID; | |
140 | local_port = MLXSW_PORT_CPU_PORT; | |
141 | } else { | |
142 | table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST; | |
143 | } | |
144 | ||
0293038e IS |
145 | sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL); |
146 | if (!sftr_pl) | |
147 | return -ENOMEM; | |
148 | ||
c06a94ef | 149 | mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_UC, idx_begin, |
7f71eb46 | 150 | table_type, range, local_port, set); |
0293038e IS |
151 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl); |
152 | if (err) | |
153 | goto buffer_out; | |
154 | ||
155 | /* Flooding control allows one to decide whether a given port will | |
156 | * flood unicast traffic for which there is no FDB entry. | |
157 | */ | |
158 | if (only_uc) | |
159 | goto buffer_out; | |
160 | ||
c06a94ef | 161 | mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, idx_begin, |
7f71eb46 | 162 | table_type, range, local_port, set); |
0293038e IS |
163 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl); |
164 | ||
165 | buffer_out: | |
166 | kfree(sftr_pl); | |
167 | return err; | |
168 | } | |
169 | ||
170 | static int mlxsw_sp_port_uc_flood_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
171 | bool set) | |
172 | { | |
173 | struct net_device *dev = mlxsw_sp_port->dev; | |
174 | u16 vid, last_visited_vid; | |
175 | int err; | |
176 | ||
177 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) { | |
178 | err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid, vid, set, | |
179 | true); | |
180 | if (err) { | |
181 | last_visited_vid = vid; | |
182 | goto err_port_flood_set; | |
183 | } | |
184 | } | |
185 | ||
186 | return 0; | |
187 | ||
188 | err_port_flood_set: | |
189 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid) | |
190 | __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid, vid, !set, true); | |
191 | netdev_err(dev, "Failed to configure unicast flooding\n"); | |
192 | return err; | |
193 | } | |
194 | ||
7f71eb46 | 195 | int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 vfid, |
19ae6124 | 196 | bool set, bool only_uc) |
7f71eb46 IS |
197 | { |
198 | /* In case of vFIDs, index into the flooding table is relative to | |
199 | * the start of the vFIDs range. | |
200 | */ | |
19ae6124 IS |
201 | return __mlxsw_sp_port_flood_set(mlxsw_sp_vport, vfid, vfid, set, |
202 | only_uc); | |
7f71eb46 IS |
203 | } |
204 | ||
56ade8fe JP |
205 | static int mlxsw_sp_port_attr_br_flags_set(struct mlxsw_sp_port *mlxsw_sp_port, |
206 | struct switchdev_trans *trans, | |
207 | unsigned long brport_flags) | |
208 | { | |
0293038e IS |
209 | unsigned long uc_flood = mlxsw_sp_port->uc_flood ? BR_FLOOD : 0; |
210 | bool set; | |
211 | int err; | |
212 | ||
56ade8fe JP |
213 | if (switchdev_trans_ph_prepare(trans)) |
214 | return 0; | |
215 | ||
0293038e IS |
216 | if ((uc_flood ^ brport_flags) & BR_FLOOD) { |
217 | set = mlxsw_sp_port->uc_flood ? false : true; | |
218 | err = mlxsw_sp_port_uc_flood_set(mlxsw_sp_port, set); | |
219 | if (err) | |
220 | return err; | |
221 | } | |
222 | ||
223 | mlxsw_sp_port->uc_flood = brport_flags & BR_FLOOD ? 1 : 0; | |
56ade8fe JP |
224 | mlxsw_sp_port->learning = brport_flags & BR_LEARNING ? 1 : 0; |
225 | mlxsw_sp_port->learning_sync = brport_flags & BR_LEARNING_SYNC ? 1 : 0; | |
0293038e | 226 | |
56ade8fe JP |
227 | return 0; |
228 | } | |
229 | ||
230 | static int mlxsw_sp_ageing_set(struct mlxsw_sp *mlxsw_sp, u32 ageing_time) | |
231 | { | |
232 | char sfdat_pl[MLXSW_REG_SFDAT_LEN]; | |
233 | int err; | |
234 | ||
235 | mlxsw_reg_sfdat_pack(sfdat_pl, ageing_time); | |
236 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdat), sfdat_pl); | |
237 | if (err) | |
238 | return err; | |
239 | mlxsw_sp->ageing_time = ageing_time; | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static int mlxsw_sp_port_attr_br_ageing_set(struct mlxsw_sp_port *mlxsw_sp_port, | |
244 | struct switchdev_trans *trans, | |
135f9ece | 245 | unsigned long ageing_clock_t) |
56ade8fe JP |
246 | { |
247 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
135f9ece | 248 | unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); |
56ade8fe JP |
249 | u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; |
250 | ||
251 | if (switchdev_trans_ph_prepare(trans)) | |
252 | return 0; | |
253 | ||
254 | return mlxsw_sp_ageing_set(mlxsw_sp, ageing_time); | |
255 | } | |
256 | ||
257 | static int mlxsw_sp_port_attr_set(struct net_device *dev, | |
258 | const struct switchdev_attr *attr, | |
259 | struct switchdev_trans *trans) | |
260 | { | |
261 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
262 | int err = 0; | |
263 | ||
264 | switch (attr->id) { | |
265 | case SWITCHDEV_ATTR_ID_PORT_STP_STATE: | |
266 | err = mlxsw_sp_port_attr_stp_state_set(mlxsw_sp_port, trans, | |
267 | attr->u.stp_state); | |
268 | break; | |
269 | case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: | |
270 | err = mlxsw_sp_port_attr_br_flags_set(mlxsw_sp_port, trans, | |
271 | attr->u.brport_flags); | |
272 | break; | |
273 | case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: | |
274 | err = mlxsw_sp_port_attr_br_ageing_set(mlxsw_sp_port, trans, | |
275 | attr->u.ageing_time); | |
276 | break; | |
277 | default: | |
278 | err = -EOPNOTSUPP; | |
279 | break; | |
280 | } | |
281 | ||
282 | return err; | |
283 | } | |
284 | ||
285 | static int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) | |
286 | { | |
287 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
288 | char spvid_pl[MLXSW_REG_SPVID_LEN]; | |
289 | ||
290 | mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); | |
291 | return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); | |
292 | } | |
293 | ||
294 | static int mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid) | |
295 | { | |
296 | char sfmr_pl[MLXSW_REG_SFMR_LEN]; | |
297 | int err; | |
298 | ||
299 | mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID, fid, fid); | |
300 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl); | |
301 | ||
302 | if (err) | |
303 | return err; | |
304 | ||
305 | set_bit(fid, mlxsw_sp->active_fids); | |
306 | return 0; | |
307 | } | |
308 | ||
309 | static void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, u16 fid) | |
310 | { | |
311 | char sfmr_pl[MLXSW_REG_SFMR_LEN]; | |
312 | ||
313 | clear_bit(fid, mlxsw_sp->active_fids); | |
314 | ||
315 | mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_DESTROY_FID, | |
316 | fid, fid); | |
317 | mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl); | |
318 | } | |
319 | ||
320 | static int mlxsw_sp_port_fid_map(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid) | |
321 | { | |
322 | enum mlxsw_reg_svfa_mt mt; | |
323 | ||
7f71eb46 | 324 | if (!list_empty(&mlxsw_sp_port->vports_list)) |
56ade8fe JP |
325 | mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; |
326 | else | |
327 | mt = MLXSW_REG_SVFA_MT_VID_TO_FID; | |
328 | ||
329 | return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, fid, fid); | |
330 | } | |
331 | ||
332 | static int mlxsw_sp_port_fid_unmap(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid) | |
333 | { | |
334 | enum mlxsw_reg_svfa_mt mt; | |
335 | ||
7f71eb46 | 336 | if (list_empty(&mlxsw_sp_port->vports_list)) |
56ade8fe JP |
337 | return 0; |
338 | ||
339 | mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; | |
340 | return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, fid, fid); | |
341 | } | |
342 | ||
56ade8fe JP |
343 | static int mlxsw_sp_port_add_vids(struct net_device *dev, u16 vid_begin, |
344 | u16 vid_end) | |
345 | { | |
346 | u16 vid; | |
347 | int err; | |
348 | ||
349 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
350 | err = mlxsw_sp_port_add_vid(dev, 0, vid); | |
351 | if (err) | |
352 | goto err_port_add_vid; | |
353 | } | |
354 | return 0; | |
355 | ||
356 | err_port_add_vid: | |
357 | for (vid--; vid >= vid_begin; vid--) | |
358 | mlxsw_sp_port_kill_vid(dev, 0, vid); | |
359 | return err; | |
360 | } | |
361 | ||
3b7ad5ec IS |
362 | static int __mlxsw_sp_port_vlans_set(struct mlxsw_sp_port *mlxsw_sp_port, |
363 | u16 vid_begin, u16 vid_end, bool is_member, | |
364 | bool untagged) | |
365 | { | |
366 | u16 vid, vid_e; | |
367 | int err; | |
368 | ||
369 | for (vid = vid_begin; vid <= vid_end; | |
370 | vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { | |
371 | vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), | |
372 | vid_end); | |
373 | ||
374 | err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, | |
375 | is_member, untagged); | |
376 | if (err) | |
377 | return err; | |
378 | } | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
56ade8fe JP |
383 | static int __mlxsw_sp_port_vlans_add(struct mlxsw_sp_port *mlxsw_sp_port, |
384 | u16 vid_begin, u16 vid_end, | |
385 | bool flag_untagged, bool flag_pvid) | |
386 | { | |
387 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
388 | struct net_device *dev = mlxsw_sp_port->dev; | |
b07a966c | 389 | u16 vid, last_visited_vid, old_pvid; |
56ade8fe | 390 | enum mlxsw_reg_svfa_mt mt; |
56ade8fe JP |
391 | int err; |
392 | ||
393 | /* In case this is invoked with BRIDGE_FLAGS_SELF and port is | |
394 | * not bridged, then packets ingressing through the port with | |
395 | * the specified VIDs will be directed to CPU. | |
396 | */ | |
397 | if (!mlxsw_sp_port->bridged) | |
398 | return mlxsw_sp_port_add_vids(dev, vid_begin, vid_end); | |
399 | ||
400 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
401 | if (!test_bit(vid, mlxsw_sp->active_fids)) { | |
402 | err = mlxsw_sp_fid_create(mlxsw_sp, vid); | |
403 | if (err) { | |
404 | netdev_err(dev, "Failed to create FID=%d\n", | |
405 | vid); | |
406 | return err; | |
407 | } | |
408 | ||
409 | /* When creating a FID, we set a VID to FID mapping | |
410 | * regardless of the port's mode. | |
411 | */ | |
412 | mt = MLXSW_REG_SVFA_MT_VID_TO_FID; | |
413 | err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, | |
414 | true, vid, vid); | |
415 | if (err) { | |
416 | netdev_err(dev, "Failed to create FID=VID=%d mapping\n", | |
417 | vid); | |
b07a966c | 418 | goto err_port_vid_to_fid_set; |
56ade8fe JP |
419 | } |
420 | } | |
b07a966c | 421 | } |
56ade8fe | 422 | |
b07a966c IS |
423 | /* Set FID mapping according to port's mode */ |
424 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
56ade8fe JP |
425 | err = mlxsw_sp_port_fid_map(mlxsw_sp_port, vid); |
426 | if (err) { | |
427 | netdev_err(dev, "Failed to map FID=%d", vid); | |
b07a966c IS |
428 | last_visited_vid = --vid; |
429 | goto err_port_fid_map; | |
56ade8fe | 430 | } |
1b3433a9 | 431 | } |
56ade8fe | 432 | |
1b3433a9 IS |
433 | err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid_begin, vid_end, |
434 | true, false); | |
435 | if (err) { | |
436 | netdev_err(dev, "Failed to configure flooding\n"); | |
b07a966c | 437 | goto err_port_flood_set; |
56ade8fe JP |
438 | } |
439 | ||
3b7ad5ec IS |
440 | err = __mlxsw_sp_port_vlans_set(mlxsw_sp_port, vid_begin, vid_end, |
441 | true, flag_untagged); | |
442 | if (err) { | |
443 | netdev_err(dev, "Unable to add VIDs %d-%d\n", vid_begin, | |
444 | vid_end); | |
b07a966c | 445 | goto err_port_vlans_set; |
56ade8fe JP |
446 | } |
447 | ||
b07a966c IS |
448 | old_pvid = mlxsw_sp_port->pvid; |
449 | if (flag_pvid && old_pvid != vid_begin) { | |
450 | err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid_begin); | |
56ade8fe | 451 | if (err) { |
b07a966c IS |
452 | netdev_err(dev, "Unable to add PVID %d\n", vid_begin); |
453 | goto err_port_pvid_set; | |
56ade8fe | 454 | } |
b07a966c | 455 | mlxsw_sp_port->pvid = vid_begin; |
56ade8fe JP |
456 | } |
457 | ||
458 | /* Changing activity bits only if HW operation succeded */ | |
459 | for (vid = vid_begin; vid <= vid_end; vid++) | |
460 | set_bit(vid, mlxsw_sp_port->active_vlans); | |
461 | ||
b07a966c IS |
462 | /* STP state change must be done after we set active VLANs */ |
463 | err = mlxsw_sp_port_stp_state_set(mlxsw_sp_port, | |
464 | mlxsw_sp_port->stp_state); | |
465 | if (err) { | |
466 | netdev_err(dev, "Failed to set STP state\n"); | |
467 | goto err_port_stp_state_set; | |
468 | } | |
469 | ||
470 | return 0; | |
471 | ||
472 | err_port_vid_to_fid_set: | |
473 | mlxsw_sp_fid_destroy(mlxsw_sp, vid); | |
474 | return err; | |
475 | ||
476 | err_port_stp_state_set: | |
477 | for (vid = vid_begin; vid <= vid_end; vid++) | |
478 | clear_bit(vid, mlxsw_sp_port->active_vlans); | |
479 | if (old_pvid != mlxsw_sp_port->pvid) | |
480 | mlxsw_sp_port_pvid_set(mlxsw_sp_port, old_pvid); | |
481 | err_port_pvid_set: | |
482 | __mlxsw_sp_port_vlans_set(mlxsw_sp_port, vid_begin, vid_end, false, | |
483 | false); | |
484 | err_port_vlans_set: | |
485 | __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid_begin, vid_end, false, | |
486 | false); | |
487 | err_port_flood_set: | |
488 | last_visited_vid = vid_end; | |
489 | err_port_fid_map: | |
490 | for (vid = last_visited_vid; vid >= vid_begin; vid--) | |
491 | mlxsw_sp_port_fid_unmap(mlxsw_sp_port, vid); | |
492 | return err; | |
56ade8fe JP |
493 | } |
494 | ||
495 | static int mlxsw_sp_port_vlans_add(struct mlxsw_sp_port *mlxsw_sp_port, | |
496 | const struct switchdev_obj_port_vlan *vlan, | |
497 | struct switchdev_trans *trans) | |
498 | { | |
499 | bool untagged_flag = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
500 | bool pvid_flag = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
501 | ||
502 | if (switchdev_trans_ph_prepare(trans)) | |
503 | return 0; | |
504 | ||
505 | return __mlxsw_sp_port_vlans_add(mlxsw_sp_port, | |
506 | vlan->vid_begin, vlan->vid_end, | |
507 | untagged_flag, pvid_flag); | |
508 | } | |
509 | ||
8a1ab5d7 | 510 | static enum mlxsw_reg_sfd_rec_policy mlxsw_sp_sfd_rec_policy(bool dynamic) |
56ade8fe | 511 | { |
8a1ab5d7 JP |
512 | return dynamic ? MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS : |
513 | MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY; | |
514 | } | |
515 | ||
516 | static enum mlxsw_reg_sfd_op mlxsw_sp_sfd_op(bool adding) | |
517 | { | |
518 | return adding ? MLXSW_REG_SFD_OP_WRITE_EDIT : | |
519 | MLXSW_REG_SFD_OP_WRITE_REMOVE; | |
520 | } | |
521 | ||
522 | static int mlxsw_sp_port_fdb_uc_op(struct mlxsw_sp_port *mlxsw_sp_port, | |
9de6a80e | 523 | const char *mac, u16 fid, bool adding, |
8a1ab5d7 JP |
524 | bool dynamic) |
525 | { | |
526 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; | |
56ade8fe JP |
527 | char *sfd_pl; |
528 | int err; | |
529 | ||
56ade8fe JP |
530 | sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL); |
531 | if (!sfd_pl) | |
532 | return -ENOMEM; | |
533 | ||
8a1ab5d7 JP |
534 | mlxsw_reg_sfd_pack(sfd_pl, mlxsw_sp_sfd_op(adding), 0); |
535 | mlxsw_reg_sfd_uc_pack(sfd_pl, 0, mlxsw_sp_sfd_rec_policy(dynamic), | |
9de6a80e | 536 | mac, fid, MLXSW_REG_SFD_REC_ACTION_NOP, |
56ade8fe | 537 | mlxsw_sp_port->local_port); |
8a1ab5d7 JP |
538 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfd), sfd_pl); |
539 | kfree(sfd_pl); | |
540 | ||
541 | return err; | |
542 | } | |
543 | ||
544 | static int mlxsw_sp_port_fdb_uc_lag_op(struct mlxsw_sp *mlxsw_sp, u16 lag_id, | |
9de6a80e | 545 | const char *mac, u16 fid, bool adding, |
8a1ab5d7 JP |
546 | bool dynamic) |
547 | { | |
548 | char *sfd_pl; | |
549 | int err; | |
550 | ||
551 | sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL); | |
552 | if (!sfd_pl) | |
553 | return -ENOMEM; | |
554 | ||
555 | mlxsw_reg_sfd_pack(sfd_pl, mlxsw_sp_sfd_op(adding), 0); | |
556 | mlxsw_reg_sfd_uc_lag_pack(sfd_pl, 0, mlxsw_sp_sfd_rec_policy(dynamic), | |
9de6a80e | 557 | mac, fid, MLXSW_REG_SFD_REC_ACTION_NOP, |
8a1ab5d7 JP |
558 | lag_id); |
559 | err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfd), sfd_pl); | |
56ade8fe JP |
560 | kfree(sfd_pl); |
561 | ||
562 | return err; | |
563 | } | |
564 | ||
565 | static int | |
566 | mlxsw_sp_port_fdb_static_add(struct mlxsw_sp_port *mlxsw_sp_port, | |
567 | const struct switchdev_obj_port_fdb *fdb, | |
568 | struct switchdev_trans *trans) | |
569 | { | |
9de6a80e | 570 | u16 fid = fdb->vid; |
8a1ab5d7 | 571 | |
56ade8fe JP |
572 | if (switchdev_trans_ph_prepare(trans)) |
573 | return 0; | |
574 | ||
9de6a80e IS |
575 | if (!fid) |
576 | fid = mlxsw_sp_port->pvid; | |
8a1ab5d7 JP |
577 | |
578 | if (!mlxsw_sp_port->lagged) | |
579 | return mlxsw_sp_port_fdb_uc_op(mlxsw_sp_port, | |
9de6a80e | 580 | fdb->addr, fid, true, false); |
8a1ab5d7 JP |
581 | else |
582 | return mlxsw_sp_port_fdb_uc_lag_op(mlxsw_sp_port->mlxsw_sp, | |
583 | mlxsw_sp_port->lag_id, | |
9de6a80e | 584 | fdb->addr, fid, true, false); |
56ade8fe JP |
585 | } |
586 | ||
587 | static int mlxsw_sp_port_obj_add(struct net_device *dev, | |
588 | const struct switchdev_obj *obj, | |
589 | struct switchdev_trans *trans) | |
590 | { | |
591 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
592 | int err = 0; | |
593 | ||
594 | switch (obj->id) { | |
595 | case SWITCHDEV_OBJ_ID_PORT_VLAN: | |
596 | err = mlxsw_sp_port_vlans_add(mlxsw_sp_port, | |
597 | SWITCHDEV_OBJ_PORT_VLAN(obj), | |
598 | trans); | |
599 | break; | |
600 | case SWITCHDEV_OBJ_ID_PORT_FDB: | |
601 | err = mlxsw_sp_port_fdb_static_add(mlxsw_sp_port, | |
602 | SWITCHDEV_OBJ_PORT_FDB(obj), | |
603 | trans); | |
604 | break; | |
605 | default: | |
606 | err = -EOPNOTSUPP; | |
607 | break; | |
608 | } | |
609 | ||
610 | return err; | |
611 | } | |
612 | ||
613 | static int mlxsw_sp_port_kill_vids(struct net_device *dev, u16 vid_begin, | |
614 | u16 vid_end) | |
615 | { | |
616 | u16 vid; | |
617 | int err; | |
618 | ||
619 | for (vid = vid_begin; vid <= vid_end; vid++) { | |
620 | err = mlxsw_sp_port_kill_vid(dev, 0, vid); | |
621 | if (err) | |
622 | return err; | |
623 | } | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
628 | static int __mlxsw_sp_port_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port, | |
629 | u16 vid_begin, u16 vid_end, bool init) | |
630 | { | |
631 | struct net_device *dev = mlxsw_sp_port->dev; | |
3b7ad5ec | 632 | u16 vid, pvid; |
56ade8fe JP |
633 | int err; |
634 | ||
635 | /* In case this is invoked with BRIDGE_FLAGS_SELF and port is | |
636 | * not bridged, then prevent packets ingressing through the | |
637 | * port with the specified VIDs from being trapped to CPU. | |
638 | */ | |
639 | if (!init && !mlxsw_sp_port->bridged) | |
640 | return mlxsw_sp_port_kill_vids(dev, vid_begin, vid_end); | |
641 | ||
3b7ad5ec IS |
642 | err = __mlxsw_sp_port_vlans_set(mlxsw_sp_port, vid_begin, vid_end, |
643 | false, false); | |
644 | if (err) { | |
645 | netdev_err(dev, "Unable to del VIDs %d-%d\n", vid_begin, | |
646 | vid_end); | |
647 | return err; | |
56ade8fe JP |
648 | } |
649 | ||
06c071f6 IS |
650 | pvid = mlxsw_sp_port->pvid; |
651 | if (pvid >= vid_begin && pvid <= vid_end && pvid != 1) { | |
56ade8fe | 652 | /* Default VLAN is always 1 */ |
06c071f6 | 653 | err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); |
56ade8fe | 654 | if (err) { |
06c071f6 | 655 | netdev_err(dev, "Unable to del PVID %d\n", pvid); |
56ade8fe JP |
656 | return err; |
657 | } | |
06c071f6 | 658 | mlxsw_sp_port->pvid = 1; |
56ade8fe JP |
659 | } |
660 | ||
661 | if (init) | |
662 | goto out; | |
663 | ||
1b3433a9 IS |
664 | err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid_begin, vid_end, |
665 | false, false); | |
666 | if (err) { | |
667 | netdev_err(dev, "Failed to clear flooding\n"); | |
668 | return err; | |
669 | } | |
56ade8fe | 670 | |
1b3433a9 | 671 | for (vid = vid_begin; vid <= vid_end; vid++) { |
56ade8fe JP |
672 | /* Remove FID mapping in case of Virtual mode */ |
673 | err = mlxsw_sp_port_fid_unmap(mlxsw_sp_port, vid); | |
674 | if (err) { | |
675 | netdev_err(dev, "Failed to unmap FID=%d", vid); | |
676 | return err; | |
677 | } | |
678 | } | |
679 | ||
680 | out: | |
681 | /* Changing activity bits only if HW operation succeded */ | |
682 | for (vid = vid_begin; vid <= vid_end; vid++) | |
683 | clear_bit(vid, mlxsw_sp_port->active_vlans); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | static int mlxsw_sp_port_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port, | |
689 | const struct switchdev_obj_port_vlan *vlan) | |
690 | { | |
691 | return __mlxsw_sp_port_vlans_del(mlxsw_sp_port, | |
692 | vlan->vid_begin, vlan->vid_end, false); | |
693 | } | |
694 | ||
695 | static int | |
696 | mlxsw_sp_port_fdb_static_del(struct mlxsw_sp_port *mlxsw_sp_port, | |
697 | const struct switchdev_obj_port_fdb *fdb) | |
698 | { | |
9de6a80e IS |
699 | u16 fid = fdb->vid; |
700 | ||
8a1ab5d7 JP |
701 | if (!mlxsw_sp_port->lagged) |
702 | return mlxsw_sp_port_fdb_uc_op(mlxsw_sp_port, | |
9de6a80e | 703 | fdb->addr, fid, |
8a1ab5d7 JP |
704 | false, false); |
705 | else | |
706 | return mlxsw_sp_port_fdb_uc_lag_op(mlxsw_sp_port->mlxsw_sp, | |
707 | mlxsw_sp_port->lag_id, | |
9de6a80e | 708 | fdb->addr, fid, |
8a1ab5d7 | 709 | false, false); |
56ade8fe JP |
710 | } |
711 | ||
712 | static int mlxsw_sp_port_obj_del(struct net_device *dev, | |
713 | const struct switchdev_obj *obj) | |
714 | { | |
715 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
716 | int err = 0; | |
717 | ||
718 | switch (obj->id) { | |
719 | case SWITCHDEV_OBJ_ID_PORT_VLAN: | |
720 | err = mlxsw_sp_port_vlans_del(mlxsw_sp_port, | |
721 | SWITCHDEV_OBJ_PORT_VLAN(obj)); | |
722 | break; | |
723 | case SWITCHDEV_OBJ_ID_PORT_FDB: | |
724 | err = mlxsw_sp_port_fdb_static_del(mlxsw_sp_port, | |
725 | SWITCHDEV_OBJ_PORT_FDB(obj)); | |
726 | break; | |
727 | default: | |
728 | err = -EOPNOTSUPP; | |
729 | break; | |
730 | } | |
731 | ||
732 | return err; | |
733 | } | |
734 | ||
8a1ab5d7 JP |
735 | static struct mlxsw_sp_port *mlxsw_sp_lag_rep_port(struct mlxsw_sp *mlxsw_sp, |
736 | u16 lag_id) | |
737 | { | |
738 | struct mlxsw_sp_port *mlxsw_sp_port; | |
739 | int i; | |
740 | ||
741 | for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) { | |
742 | mlxsw_sp_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i); | |
743 | if (mlxsw_sp_port) | |
744 | return mlxsw_sp_port; | |
745 | } | |
746 | return NULL; | |
747 | } | |
748 | ||
56ade8fe JP |
749 | static int mlxsw_sp_port_fdb_dump(struct mlxsw_sp_port *mlxsw_sp_port, |
750 | struct switchdev_obj_port_fdb *fdb, | |
751 | switchdev_obj_dump_cb_t *cb) | |
752 | { | |
8a1ab5d7 | 753 | struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; |
56ade8fe JP |
754 | char *sfd_pl; |
755 | char mac[ETH_ALEN]; | |
9de6a80e | 756 | u16 fid; |
56ade8fe | 757 | u8 local_port; |
8a1ab5d7 | 758 | u16 lag_id; |
56ade8fe JP |
759 | u8 num_rec; |
760 | int stored_err = 0; | |
761 | int i; | |
762 | int err; | |
763 | ||
764 | sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL); | |
765 | if (!sfd_pl) | |
766 | return -ENOMEM; | |
767 | ||
768 | mlxsw_reg_sfd_pack(sfd_pl, MLXSW_REG_SFD_OP_QUERY_DUMP, 0); | |
769 | do { | |
770 | mlxsw_reg_sfd_num_rec_set(sfd_pl, MLXSW_REG_SFD_REC_MAX_COUNT); | |
8a1ab5d7 | 771 | err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(sfd), sfd_pl); |
56ade8fe JP |
772 | if (err) |
773 | goto out; | |
774 | ||
775 | num_rec = mlxsw_reg_sfd_num_rec_get(sfd_pl); | |
776 | ||
777 | /* Even in case of error, we have to run the dump to the end | |
778 | * so the session in firmware is finished. | |
779 | */ | |
780 | if (stored_err) | |
781 | continue; | |
782 | ||
783 | for (i = 0; i < num_rec; i++) { | |
784 | switch (mlxsw_reg_sfd_rec_type_get(sfd_pl, i)) { | |
785 | case MLXSW_REG_SFD_REC_TYPE_UNICAST: | |
9de6a80e | 786 | mlxsw_reg_sfd_uc_unpack(sfd_pl, i, mac, &fid, |
56ade8fe JP |
787 | &local_port); |
788 | if (local_port == mlxsw_sp_port->local_port) { | |
789 | ether_addr_copy(fdb->addr, mac); | |
790 | fdb->ndm_state = NUD_REACHABLE; | |
9de6a80e | 791 | fdb->vid = fid; |
56ade8fe JP |
792 | err = cb(&fdb->obj); |
793 | if (err) | |
794 | stored_err = err; | |
795 | } | |
8a1ab5d7 JP |
796 | break; |
797 | case MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG: | |
798 | mlxsw_reg_sfd_uc_lag_unpack(sfd_pl, i, | |
9de6a80e | 799 | mac, &fid, &lag_id); |
8a1ab5d7 JP |
800 | if (mlxsw_sp_port == |
801 | mlxsw_sp_lag_rep_port(mlxsw_sp, lag_id)) { | |
802 | ether_addr_copy(fdb->addr, mac); | |
803 | fdb->ndm_state = NUD_REACHABLE; | |
9de6a80e | 804 | fdb->vid = fid; |
8a1ab5d7 JP |
805 | err = cb(&fdb->obj); |
806 | if (err) | |
807 | stored_err = err; | |
808 | } | |
809 | break; | |
56ade8fe JP |
810 | } |
811 | } | |
812 | } while (num_rec == MLXSW_REG_SFD_REC_MAX_COUNT); | |
813 | ||
814 | out: | |
815 | kfree(sfd_pl); | |
816 | return stored_err ? stored_err : err; | |
817 | } | |
818 | ||
819 | static int mlxsw_sp_port_vlan_dump(struct mlxsw_sp_port *mlxsw_sp_port, | |
820 | struct switchdev_obj_port_vlan *vlan, | |
821 | switchdev_obj_dump_cb_t *cb) | |
822 | { | |
823 | u16 vid; | |
824 | int err = 0; | |
825 | ||
826 | for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) { | |
827 | vlan->flags = 0; | |
828 | if (vid == mlxsw_sp_port->pvid) | |
829 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
830 | vlan->vid_begin = vid; | |
831 | vlan->vid_end = vid; | |
832 | err = cb(&vlan->obj); | |
833 | if (err) | |
834 | break; | |
835 | } | |
836 | return err; | |
837 | } | |
838 | ||
839 | static int mlxsw_sp_port_obj_dump(struct net_device *dev, | |
840 | struct switchdev_obj *obj, | |
841 | switchdev_obj_dump_cb_t *cb) | |
842 | { | |
843 | struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); | |
844 | int err = 0; | |
845 | ||
846 | switch (obj->id) { | |
847 | case SWITCHDEV_OBJ_ID_PORT_VLAN: | |
848 | err = mlxsw_sp_port_vlan_dump(mlxsw_sp_port, | |
849 | SWITCHDEV_OBJ_PORT_VLAN(obj), cb); | |
850 | break; | |
851 | case SWITCHDEV_OBJ_ID_PORT_FDB: | |
852 | err = mlxsw_sp_port_fdb_dump(mlxsw_sp_port, | |
853 | SWITCHDEV_OBJ_PORT_FDB(obj), cb); | |
854 | break; | |
855 | default: | |
856 | err = -EOPNOTSUPP; | |
857 | break; | |
858 | } | |
859 | ||
860 | return err; | |
861 | } | |
862 | ||
c7070fc4 | 863 | static const struct switchdev_ops mlxsw_sp_port_switchdev_ops = { |
56ade8fe JP |
864 | .switchdev_port_attr_get = mlxsw_sp_port_attr_get, |
865 | .switchdev_port_attr_set = mlxsw_sp_port_attr_set, | |
866 | .switchdev_port_obj_add = mlxsw_sp_port_obj_add, | |
867 | .switchdev_port_obj_del = mlxsw_sp_port_obj_del, | |
868 | .switchdev_port_obj_dump = mlxsw_sp_port_obj_dump, | |
869 | }; | |
870 | ||
8a1ab5d7 JP |
871 | static void mlxsw_sp_fdb_call_notifiers(bool learning, bool learning_sync, |
872 | bool adding, char *mac, u16 vid, | |
873 | struct net_device *dev) | |
874 | { | |
875 | struct switchdev_notifier_fdb_info info; | |
876 | unsigned long notifier_type; | |
877 | ||
878 | if (learning && learning_sync) { | |
879 | info.addr = mac; | |
880 | info.vid = vid; | |
881 | notifier_type = adding ? SWITCHDEV_FDB_ADD : SWITCHDEV_FDB_DEL; | |
882 | call_switchdev_notifiers(notifier_type, dev, &info.info); | |
883 | } | |
884 | } | |
885 | ||
56ade8fe JP |
886 | static void mlxsw_sp_fdb_notify_mac_process(struct mlxsw_sp *mlxsw_sp, |
887 | char *sfn_pl, int rec_index, | |
888 | bool adding) | |
889 | { | |
890 | struct mlxsw_sp_port *mlxsw_sp_port; | |
891 | char mac[ETH_ALEN]; | |
892 | u8 local_port; | |
9de6a80e | 893 | u16 vid, fid; |
56ade8fe JP |
894 | int err; |
895 | ||
9de6a80e | 896 | mlxsw_reg_sfn_mac_unpack(sfn_pl, rec_index, mac, &fid, &local_port); |
56ade8fe JP |
897 | mlxsw_sp_port = mlxsw_sp->ports[local_port]; |
898 | if (!mlxsw_sp_port) { | |
899 | dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Incorrect local port in FDB notification\n"); | |
900 | return; | |
901 | } | |
902 | ||
9de6a80e | 903 | err = mlxsw_sp_port_fdb_uc_op(mlxsw_sp_port, mac, fid, |
8a1ab5d7 | 904 | adding && mlxsw_sp_port->learning, true); |
56ade8fe JP |
905 | if (err) { |
906 | if (net_ratelimit()) | |
907 | netdev_err(mlxsw_sp_port->dev, "Failed to set FDB entry\n"); | |
908 | return; | |
909 | } | |
910 | ||
9de6a80e IS |
911 | vid = fid; |
912 | ||
8a1ab5d7 JP |
913 | mlxsw_sp_fdb_call_notifiers(mlxsw_sp_port->learning, |
914 | mlxsw_sp_port->learning_sync, | |
915 | adding, mac, vid, mlxsw_sp_port->dev); | |
916 | } | |
56ade8fe | 917 | |
8a1ab5d7 JP |
918 | static void mlxsw_sp_fdb_notify_mac_lag_process(struct mlxsw_sp *mlxsw_sp, |
919 | char *sfn_pl, int rec_index, | |
920 | bool adding) | |
921 | { | |
922 | struct mlxsw_sp_port *mlxsw_sp_port; | |
923 | char mac[ETH_ALEN]; | |
924 | u16 lag_id; | |
9de6a80e | 925 | u16 vid, fid; |
8a1ab5d7 JP |
926 | int err; |
927 | ||
9de6a80e | 928 | mlxsw_reg_sfn_mac_lag_unpack(sfn_pl, rec_index, mac, &fid, &lag_id); |
8a1ab5d7 JP |
929 | mlxsw_sp_port = mlxsw_sp_lag_rep_port(mlxsw_sp, lag_id); |
930 | if (!mlxsw_sp_port) { | |
931 | dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Cannot find port representor for LAG\n"); | |
932 | return; | |
56ade8fe | 933 | } |
8a1ab5d7 | 934 | |
9de6a80e | 935 | err = mlxsw_sp_port_fdb_uc_lag_op(mlxsw_sp, lag_id, mac, fid, |
8a1ab5d7 JP |
936 | adding && mlxsw_sp_port->learning, |
937 | true); | |
938 | if (err) { | |
939 | if (net_ratelimit()) | |
940 | netdev_err(mlxsw_sp_port->dev, "Failed to set FDB entry\n"); | |
941 | return; | |
942 | } | |
943 | ||
9de6a80e IS |
944 | vid = fid; |
945 | ||
8a1ab5d7 JP |
946 | mlxsw_sp_fdb_call_notifiers(mlxsw_sp_port->learning, |
947 | mlxsw_sp_port->learning_sync, | |
948 | adding, mac, vid, | |
949 | mlxsw_sp_lag_get(mlxsw_sp, lag_id)->dev); | |
56ade8fe JP |
950 | } |
951 | ||
952 | static void mlxsw_sp_fdb_notify_rec_process(struct mlxsw_sp *mlxsw_sp, | |
953 | char *sfn_pl, int rec_index) | |
954 | { | |
955 | switch (mlxsw_reg_sfn_rec_type_get(sfn_pl, rec_index)) { | |
956 | case MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC: | |
957 | mlxsw_sp_fdb_notify_mac_process(mlxsw_sp, sfn_pl, | |
958 | rec_index, true); | |
959 | break; | |
960 | case MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC: | |
961 | mlxsw_sp_fdb_notify_mac_process(mlxsw_sp, sfn_pl, | |
962 | rec_index, false); | |
963 | break; | |
8a1ab5d7 JP |
964 | case MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG: |
965 | mlxsw_sp_fdb_notify_mac_lag_process(mlxsw_sp, sfn_pl, | |
966 | rec_index, true); | |
967 | break; | |
968 | case MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG: | |
969 | mlxsw_sp_fdb_notify_mac_lag_process(mlxsw_sp, sfn_pl, | |
970 | rec_index, false); | |
971 | break; | |
56ade8fe JP |
972 | } |
973 | } | |
974 | ||
975 | static void mlxsw_sp_fdb_notify_work_schedule(struct mlxsw_sp *mlxsw_sp) | |
976 | { | |
977 | schedule_delayed_work(&mlxsw_sp->fdb_notify.dw, | |
978 | msecs_to_jiffies(mlxsw_sp->fdb_notify.interval)); | |
979 | } | |
980 | ||
981 | static void mlxsw_sp_fdb_notify_work(struct work_struct *work) | |
982 | { | |
983 | struct mlxsw_sp *mlxsw_sp; | |
984 | char *sfn_pl; | |
985 | u8 num_rec; | |
986 | int i; | |
987 | int err; | |
988 | ||
989 | sfn_pl = kmalloc(MLXSW_REG_SFN_LEN, GFP_KERNEL); | |
990 | if (!sfn_pl) | |
991 | return; | |
992 | ||
993 | mlxsw_sp = container_of(work, struct mlxsw_sp, fdb_notify.dw.work); | |
994 | ||
995 | do { | |
996 | mlxsw_reg_sfn_pack(sfn_pl); | |
997 | err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(sfn), sfn_pl); | |
998 | if (err) { | |
999 | dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Failed to get FDB notifications\n"); | |
1000 | break; | |
1001 | } | |
1002 | num_rec = mlxsw_reg_sfn_num_rec_get(sfn_pl); | |
1003 | for (i = 0; i < num_rec; i++) | |
1004 | mlxsw_sp_fdb_notify_rec_process(mlxsw_sp, sfn_pl, i); | |
1005 | ||
1006 | } while (num_rec); | |
1007 | ||
1008 | kfree(sfn_pl); | |
1009 | mlxsw_sp_fdb_notify_work_schedule(mlxsw_sp); | |
1010 | } | |
1011 | ||
1012 | static int mlxsw_sp_fdb_init(struct mlxsw_sp *mlxsw_sp) | |
1013 | { | |
1014 | int err; | |
1015 | ||
1016 | err = mlxsw_sp_ageing_set(mlxsw_sp, MLXSW_SP_DEFAULT_AGEING_TIME); | |
1017 | if (err) { | |
1018 | dev_err(mlxsw_sp->bus_info->dev, "Failed to set default ageing time\n"); | |
1019 | return err; | |
1020 | } | |
1021 | INIT_DELAYED_WORK(&mlxsw_sp->fdb_notify.dw, mlxsw_sp_fdb_notify_work); | |
1022 | mlxsw_sp->fdb_notify.interval = MLXSW_SP_DEFAULT_LEARNING_INTERVAL; | |
1023 | mlxsw_sp_fdb_notify_work_schedule(mlxsw_sp); | |
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | static void mlxsw_sp_fdb_fini(struct mlxsw_sp *mlxsw_sp) | |
1028 | { | |
1029 | cancel_delayed_work_sync(&mlxsw_sp->fdb_notify.dw); | |
1030 | } | |
1031 | ||
1032 | static void mlxsw_sp_fids_fini(struct mlxsw_sp *mlxsw_sp) | |
1033 | { | |
1034 | u16 fid; | |
1035 | ||
1036 | for_each_set_bit(fid, mlxsw_sp->active_fids, VLAN_N_VID) | |
1037 | mlxsw_sp_fid_destroy(mlxsw_sp, fid); | |
1038 | } | |
1039 | ||
1040 | int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp) | |
1041 | { | |
1042 | return mlxsw_sp_fdb_init(mlxsw_sp); | |
1043 | } | |
1044 | ||
1045 | void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp) | |
1046 | { | |
1047 | mlxsw_sp_fdb_fini(mlxsw_sp); | |
1048 | mlxsw_sp_fids_fini(mlxsw_sp); | |
1049 | } | |
1050 | ||
1051 | int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port) | |
1052 | { | |
1053 | struct net_device *dev = mlxsw_sp_port->dev; | |
1054 | int err; | |
1055 | ||
1056 | /* Allow only untagged packets to ingress and tag them internally | |
1057 | * with VID 1. | |
1058 | */ | |
1059 | mlxsw_sp_port->pvid = 1; | |
1060 | err = __mlxsw_sp_port_vlans_del(mlxsw_sp_port, 0, VLAN_N_VID, true); | |
1061 | if (err) { | |
1062 | netdev_err(dev, "Unable to init VLANs\n"); | |
1063 | return err; | |
1064 | } | |
1065 | ||
1066 | /* Add implicit VLAN interface in the device, so that untagged | |
1067 | * packets will be classified to the default vFID. | |
1068 | */ | |
1069 | err = mlxsw_sp_port_add_vid(dev, 0, 1); | |
1070 | if (err) | |
1071 | netdev_err(dev, "Failed to configure default vFID\n"); | |
1072 | ||
1073 | return err; | |
1074 | } | |
1075 | ||
1076 | void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port) | |
1077 | { | |
1078 | mlxsw_sp_port->dev->switchdev_ops = &mlxsw_sp_port_switchdev_ops; | |
1079 | } | |
1080 | ||
1081 | void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port) | |
1082 | { | |
1083 | } |