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a556c76a AB |
1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
2 | /* | |
3 | * Microsemi Ocelot Switch driver | |
4 | * | |
5 | * Copyright (c) 2017 Microsemi Corporation | |
6 | */ | |
7 | ||
8 | #ifndef _MSCC_OCELOT_SYS_H_ | |
9 | #define _MSCC_OCELOT_SYS_H_ | |
10 | ||
11 | #define SYS_COUNT_RX_OCTETS_RSZ 0x4 | |
12 | ||
13 | #define SYS_COUNT_TX_OCTETS_RSZ 0x4 | |
14 | ||
15 | #define SYS_PORT_MODE_RSZ 0x4 | |
16 | ||
17 | #define SYS_PORT_MODE_DATA_WO_TS(x) (((x) << 5) & GENMASK(6, 5)) | |
18 | #define SYS_PORT_MODE_DATA_WO_TS_M GENMASK(6, 5) | |
19 | #define SYS_PORT_MODE_DATA_WO_TS_X(x) (((x) & GENMASK(6, 5)) >> 5) | |
20 | #define SYS_PORT_MODE_INCL_INJ_HDR(x) (((x) << 3) & GENMASK(4, 3)) | |
21 | #define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3) | |
22 | #define SYS_PORT_MODE_INCL_INJ_HDR_X(x) (((x) & GENMASK(4, 3)) >> 3) | |
23 | #define SYS_PORT_MODE_INCL_XTR_HDR(x) (((x) << 1) & GENMASK(2, 1)) | |
24 | #define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1) | |
25 | #define SYS_PORT_MODE_INCL_XTR_HDR_X(x) (((x) & GENMASK(2, 1)) >> 1) | |
26 | #define SYS_PORT_MODE_INJ_HDR_ERR BIT(0) | |
27 | ||
28 | #define SYS_FRONT_PORT_MODE_RSZ 0x4 | |
29 | ||
30 | #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0) | |
31 | ||
32 | #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) | |
33 | #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0)) | |
34 | #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0) | |
35 | ||
36 | #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10)) | |
37 | #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10) | |
38 | #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10) | |
39 | #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0)) | |
40 | #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0) | |
41 | ||
42 | #define SYS_SW_STATUS_RSZ 0x4 | |
43 | ||
44 | #define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0) | |
45 | ||
46 | #define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1) | |
47 | #define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0) | |
48 | ||
49 | #define SYS_REW_MAC_HIGH_CFG_RSZ 0x4 | |
50 | ||
51 | #define SYS_REW_MAC_LOW_CFG_RSZ 0x4 | |
52 | ||
53 | #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6)) | |
54 | #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6) | |
55 | #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6) | |
56 | #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0)) | |
57 | #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0) | |
58 | ||
59 | #define SYS_PAUSE_CFG_RSZ 0x4 | |
60 | ||
61 | #define SYS_PAUSE_CFG_PAUSE_START(x) (((x) << 10) & GENMASK(18, 10)) | |
62 | #define SYS_PAUSE_CFG_PAUSE_START_M GENMASK(18, 10) | |
63 | #define SYS_PAUSE_CFG_PAUSE_START_X(x) (((x) & GENMASK(18, 10)) >> 10) | |
64 | #define SYS_PAUSE_CFG_PAUSE_STOP(x) (((x) << 1) & GENMASK(9, 1)) | |
65 | #define SYS_PAUSE_CFG_PAUSE_STOP_M GENMASK(9, 1) | |
66 | #define SYS_PAUSE_CFG_PAUSE_STOP_X(x) (((x) & GENMASK(9, 1)) >> 1) | |
67 | #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) | |
68 | ||
69 | #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9)) | |
70 | #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9) | |
71 | #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9) | |
72 | #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0)) | |
73 | #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0) | |
74 | ||
75 | #define SYS_ATOP_RSZ 0x4 | |
76 | ||
77 | #define SYS_MAC_FC_CFG_RSZ 0x4 | |
78 | ||
79 | #define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26)) | |
80 | #define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26) | |
81 | #define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26) | |
82 | #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20)) | |
83 | #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20) | |
84 | #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20) | |
85 | #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) | |
86 | #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) | |
87 | #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) | |
88 | #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0)) | |
89 | #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0) | |
90 | ||
91 | #define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16)) | |
92 | #define SYS_MMGT_RELCNT_M GENMASK(31, 16) | |
93 | #define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16) | |
94 | #define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0)) | |
95 | #define SYS_MMGT_FREECNT_M GENMASK(15, 0) | |
96 | ||
97 | #define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4)) | |
98 | #define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4) | |
99 | #define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4) | |
100 | #define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0)) | |
101 | #define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0) | |
102 | ||
103 | #define SYS_EVENTS_DIF_RSZ 0x4 | |
104 | ||
105 | #define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6)) | |
106 | #define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6) | |
107 | #define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6) | |
108 | #define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0)) | |
109 | #define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0) | |
110 | ||
111 | #define SYS_EVENTS_CORE_EV_FWR BIT(2) | |
112 | #define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0)) | |
113 | #define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0) | |
114 | ||
115 | #define SYS_CNT_GSZ 0x4 | |
116 | ||
117 | #define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29) | |
118 | #define SYS_PTP_STATUS_PTP_OVFL BIT(28) | |
119 | #define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27) | |
120 | #define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21)) | |
121 | #define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21) | |
122 | #define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21) | |
123 | #define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16)) | |
124 | #define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16) | |
125 | #define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16) | |
126 | #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0)) | |
127 | #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0) | |
128 | ||
129 | #define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0)) | |
130 | #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0) | |
131 | #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31) | |
132 | ||
133 | #define SYS_PTP_NXT_PTP_NXT BIT(0) | |
134 | ||
135 | #define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2)) | |
136 | #define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2) | |
137 | #define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2) | |
138 | #define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0)) | |
139 | #define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0) | |
140 | ||
141 | #define SYS_RAM_INIT_RAM_INIT BIT(1) | |
142 | #define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0) | |
143 | ||
144 | #endif |