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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / myricom / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
3bea1237 4 * Copyright (C) 2005 - 2011 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
981813d8 53#include <linux/dca.h>
0da34b6d
BG		 54#include <linux/ip.h>
55#include <linux/inet.h>
56#include <linux/in.h>
57#include <linux/ethtool.h>
58#include <linux/firmware.h>
59#include <linux/delay.h>
0da34b6d
BG		 60#include <linux/timer.h>
61#include <linux/vmalloc.h>
62#include <linux/crc32.h>
63#include <linux/moduleparam.h>
64#include <linux/io.h>
199126a2 65#include <linux/log2.h>
5a0e3ad6 66#include <linux/slab.h>
70c71606 67#include <linux/prefetch.h>
0da34b6d 68#include <net/checksum.h>
1e6e9342
AG		 69#include <net/ip.h>
70#include <net/tcp.h>
0da34b6d
BG		 71#include <asm/byteorder.h>
72#include <asm/io.h>
0da34b6d
BG		 73#include <asm/processor.h>
74#ifdef CONFIG_MTRR
75#include <asm/mtrr.h>
76#endif
0dde8026 77#include <net/busy_poll.h>
0da34b6d
BG		 78
79#include "myri10ge_mcp.h"
80#include "myri10ge_mcp_gen_header.h"
81
3bea1237 82#define MYRI10GE_VERSION_STR "1.5.3-1.534"
0da34b6d
BG		 83
84MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
85MODULE_AUTHOR("Maintainer: help@myri.com");
86MODULE_VERSION(MYRI10GE_VERSION_STR);
87MODULE_LICENSE("Dual BSD/GPL");
88
89#define MYRI10GE_MAX_ETHER_MTU 9014
90
91#define MYRI10GE_ETH_STOPPED 0
92#define MYRI10GE_ETH_STOPPING 1
93#define MYRI10GE_ETH_STARTING 2
94#define MYRI10GE_ETH_RUNNING 3
95#define MYRI10GE_ETH_OPEN_FAILED 4
96
97#define MYRI10GE_EEPROM_STRINGS_SIZE 256
98#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
99
40f6cff5 100#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 101#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
102
dd50f336
BG		 103#define MYRI10GE_ALLOC_ORDER 0
104#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
105#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
106
236bb5e6
BG		 107#define MYRI10GE_MAX_SLICES 32
108
0da34b6d 109struct myri10ge_rx_buffer_state {
dd50f336
BG		 110 struct page *page;
111 int page_offset;
c755b4b6
FT		 112 DEFINE_DMA_UNMAP_ADDR(bus);
113 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 114};
115
116struct myri10ge_tx_buffer_state {
117 struct sk_buff *skb;
118 int last;
c755b4b6
FT		 119 DEFINE_DMA_UNMAP_ADDR(bus);
120 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 121};
122
123struct myri10ge_cmd {
124 u32 data0;
125 u32 data1;
126 u32 data2;
127};
128
129struct myri10ge_rx_buf {
130 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 131 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
132 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 133 struct page *page;
134 dma_addr_t bus;
135 int page_offset;
0da34b6d 136 int cnt;
dd50f336 137 int fill_cnt;
0da34b6d
BG		 138 int alloc_fail;
139 int mask; /* number of rx slots -1 */
dd50f336 140 int watchdog_needed;
0da34b6d
BG		 141};
142
143struct myri10ge_tx_buf {
144 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 145 __be32 __iomem *send_go; /* "go" doorbell ptr */
146 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 147 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
148 char *req_bytes;
149 struct myri10ge_tx_buffer_state *info;
150 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 151 int req ____cacheline_aligned; /* transmit slots submitted */
152 int pkt_start; /* packets started */
b53bef84
BG		 153 int stop_queue;
154 int linearized;
0da34b6d
BG		 155 int done ____cacheline_aligned; /* transmit slots completed */
156 int pkt_done; /* packets completed */
b53bef84 157 int wake_queue;
236bb5e6 158 int queue_active;
0da34b6d
BG		 159};
160
161struct myri10ge_rx_done {
162 struct mcp_slot *entry;
163 dma_addr_t bus;
164 int cnt;
165 int idx;
166};
167
b53bef84
BG		 168struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175};
176
177struct myri10ge_slice_state {
0da34b6d
BG		 178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
b53bef84
BG		 182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
d0234215 191 int watchdog_rx_done;
c689b81b 192 int stuck;
5dd2d332 193#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 194 int cached_dca_tag;
195 int cpu;
196 __be32 __iomem *dca_tag;
197#endif
0dde8026
HYK		 198#ifdef CONFIG_NET_RX_BUSY_POLL
199 unsigned int state;
200#define SLICE_STATE_IDLE 0
201#define SLICE_STATE_NAPI 1 /* NAPI owns this slice */
202#define SLICE_STATE_POLL 2 /* poll owns this slice */
203#define SLICE_LOCKED (SLICE_STATE_NAPI | SLICE_STATE_POLL)
204#define SLICE_STATE_NAPI_YIELD 4 /* NAPI yielded this slice */
205#define SLICE_STATE_POLL_YIELD 8 /* poll yielded this slice */
206#define SLICE_USER_PEND (SLICE_STATE_POLL | SLICE_STATE_POLL_YIELD)
207 spinlock_t lock;
208 unsigned long lock_napi_yield;
209 unsigned long lock_poll_yield;
210 unsigned long busy_poll_miss;
211 unsigned long busy_poll_cnt;
212#endif /* CONFIG_NET_RX_BUSY_POLL */
0dcffac1 213 char irq_desc[32];
b53bef84
BG		 214};
215
216struct myri10ge_priv {
0dcffac1 217 struct myri10ge_slice_state *ss;
b53bef84 218 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 219 int num_slices;
b53bef84 220 int running; /* running? */
0da34b6d 221 int small_bytes;
dd50f336 222 int big_bytes;
fa0a90d9 223 int max_intr_slots;
0da34b6d 224 struct net_device *dev;
0da34b6d
BG		 225 u8 __iomem *sram;
226 int sram_size;
227 unsigned long board_span;
228 unsigned long iomem_base;
40f6cff5 229 __be32 __iomem *irq_deassert;
0da34b6d
BG		 230 char *mac_addr_string;
231 struct mcp_cmd_response *cmd;
232 dma_addr_t cmd_bus;
0da34b6d
BG		 233 struct pci_dev *pdev;
234 int msi_enabled;
0dcffac1
BG		 235 int msix_enabled;
236 struct msix_entry *msix_vectors;
5dd2d332 237#ifdef CONFIG_MYRI10GE_DCA
981813d8 238 int dca_enabled;
ef09aadf 239 int relaxed_order;
981813d8 240#endif
66341fff 241 u32 link_state;
0da34b6d
BG		 242 unsigned int rdma_tags_available;
243 int intr_coal_delay;
40f6cff5 244 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 245 int mtrr;
276e26c3 246 int wc_enabled;
0da34b6d
BG		 247 int down_cnt;
248 wait_queue_head_t down_wq;
249 struct work_struct watchdog_work;
250 struct timer_list watchdog_timer;
0da34b6d 251 int watchdog_resets;
b53bef84 252 int watchdog_pause;
0da34b6d 253 int pause;
7d351035 254 bool fw_name_allocated;
0da34b6d
BG		 255 char *fw_name;
256 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 257 char *product_code_string;
0da34b6d 258 char fw_version[128];
9dc6f0e7
BG		 259 int fw_ver_major;
260 int fw_ver_minor;
261 int fw_ver_tiny;
262 int adopted_rx_filter_bug;
1409a932 263 u8 mac_addr[ETH_ALEN]; /* eeprom mac address */
0da34b6d
BG		 264 unsigned long serial_number;
265 int vendor_specific_offset;
85a7ea1b 266 int fw_multicast_support;
04ed3e74 267 u32 features;
4f93fde0 268 u32 max_tso6;
0da34b6d
BG		 269 u32 read_dma;
270 u32 write_dma;
271 u32 read_write_dma;
c58ac5ca
BG		 272 u32 link_changes;
273 u32 msg_enable;
2d90b0aa 274 unsigned int board_number;
d0234215 275 int rebooted;
0da34b6d
BG		 276};
277
278static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
279static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 280static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
281static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 282MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
283MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
284MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
285MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d 286
7d351035 287/* Careful: must be accessed under kparam_block_sysfs_write */
0da34b6d
BG		 288static char *myri10ge_fw_name = NULL;
289module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 290MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 291
2d90b0aa
BG		 292#define MYRI10GE_MAX_BOARDS 8
293static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 294 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 295module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
296 0444);
297MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
298
0da34b6d
BG		 299static int myri10ge_ecrc_enable = 1;
300module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 301MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 302
0da34b6d
BG		 303static int myri10ge_small_bytes = -1; /* -1 == auto */
304module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 305MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 306
307static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 308module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 309MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 310
f761fae1 311static int myri10ge_intr_coal_delay = 75;
0da34b6d 312module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 313MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 314
315static int myri10ge_flow_control = 1;
316module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 317MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 318
319static int myri10ge_deassert_wait = 1;
320module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
321MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 322 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 323
324static int myri10ge_force_firmware = 0;
325module_param(myri10ge_force_firmware, int, S_IRUGO);
326MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 327 "Force firmware to assume aligned completions");
0da34b6d 328
0da34b6d
BG		 329static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
330module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 331MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 332
333static int myri10ge_napi_weight = 64;
334module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 335MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 336
337static int myri10ge_watchdog_timeout = 1;
338module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 339MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 340
341static int myri10ge_max_irq_loops = 1048576;
342module_param(myri10ge_max_irq_loops, int, S_IRUGO);
343MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 344 "Set stuck legacy IRQ detection threshold");
0da34b6d 345
c58ac5ca
BG		 346#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
347
348static int myri10ge_debug = -1; /* defaults above */
349module_param(myri10ge_debug, int, 0);
350MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
351
dd50f336
BG		 352static int myri10ge_fill_thresh = 256;
353module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 354MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 355
f181137f
BG		 356static int myri10ge_reset_recover = 1;
357
0dcffac1
BG		 358static int myri10ge_max_slices = 1;
359module_param(myri10ge_max_slices, int, S_IRUGO);
360MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
361
4b860abf 362static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 363module_param(myri10ge_rss_hash, int, S_IRUGO);
364MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
365
981813d8
BG		 366static int myri10ge_dca = 1;
367module_param(myri10ge_dca, int, S_IRUGO);
368MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
369
0da34b6d
BG		 370#define MYRI10GE_FW_OFFSET 1024*1024
371#define MYRI10GE_HIGHPART_TO_U32(X) \
372(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
373#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
374
375#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
376
2f76216f 377static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 378static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
379 struct net_device *dev);
2f76216f 380
6250223e 381static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 382{
6250223e 383 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 384}
385
c5f7ef72 386static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
387 struct rtnl_link_stats64 *stats);
59081825 388
7d351035
RR		 389static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
390{
391 if (mgp->fw_name_allocated)
392 kfree(mgp->fw_name);
393 mgp->fw_name = name;
394 mgp->fw_name_allocated = allocated;
395}
396
0da34b6d
BG		 397static int
398myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
399 struct myri10ge_cmd *data, int atomic)
400{
401 struct mcp_cmd *buf;
402 char buf_bytes[sizeof(*buf) + 8];
403 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 404 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 405 u32 dma_low, dma_high, result, value;
406 int sleep_total = 0;
407
408 /* ensure buf is aligned to 8 bytes */
409 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
410
411 buf->data0 = htonl(data->data0);
412 buf->data1 = htonl(data->data1);
413 buf->data2 = htonl(data->data2);
414 buf->cmd = htonl(cmd);
415 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
416 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
417
418 buf->response_addr.low = htonl(dma_low);
419 buf->response_addr.high = htonl(dma_high);
40f6cff5 420 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 421 mb();
422 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
423
424 /* wait up to 15ms. Longest command is the DMA benchmark,
425 * which is capped at 5ms, but runs from a timeout handler
426 * that runs every 7.8ms. So a 15ms timeout leaves us with
427 * a 2.2ms margin
428 */
429 if (atomic) {
430 /* if atomic is set, do not sleep,
431 * and try to get the completion quickly
432 * (1ms will be enough for those commands) */
433 for (sleep_total = 0;
8e95a202
JP		 434 sleep_total < 1000 &&
435 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 436 sleep_total += 10) {
0da34b6d 437 udelay(10);
bd2db0cf
BG		 438 mb();
439 }
0da34b6d
BG		 440 } else {
441 /* use msleep for most command */
442 for (sleep_total = 0;
8e95a202
JP		 443 sleep_total < 15 &&
444 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 445 sleep_total++)
446 msleep(1);
447 }
448
449 result = ntohl(response->result);
450 value = ntohl(response->data);
451 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
452 if (result == 0) {
453 data->data0 = value;
454 return 0;
85a7ea1b
BG		 455 } else if (result == MXGEFW_CMD_UNKNOWN) {
456 return -ENOSYS;
5443e9ea
BG		 457 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
458 return -E2BIG;
236bb5e6
BG		 459 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
460 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
461 (data->
462 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
463 0) {
464 return -ERANGE;
0da34b6d
BG		 465 } else {
466 dev_err(&mgp->pdev->dev,
467 "command %d failed, result = %d\n",
468 cmd, result);
469 return -ENXIO;
470 }
471 }
472
473 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
474 cmd, result);
475 return -EAGAIN;
476}
477
478/*
479 * The eeprom strings on the lanaiX have the format
480 * SN=x\0
481 * MAC=x:x:x:x:x:x\0
482 * PT:ddd mmm xx xx:xx:xx xx\0
483 * PV:ddd mmm xx xx:xx:xx xx\0
484 */
485static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
486{
487 char *ptr, *limit;
488 int i;
489
490 ptr = mgp->eeprom_strings;
491 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
492
493 while (*ptr != '\0' && ptr < limit) {
494 if (memcmp(ptr, "MAC=", 4) == 0) {
495 ptr += 4;
496 mgp->mac_addr_string = ptr;
497 for (i = 0; i < 6; i++) {
498 if ((ptr + 2) > limit)
499 goto abort;
500 mgp->mac_addr[i] =
501 simple_strtoul(ptr, &ptr, 16);
502 ptr += 1;
503 }
504 }
c0bf8801
BG		 505 if (memcmp(ptr, "PC=", 3) == 0) {
506 ptr += 3;
507 mgp->product_code_string = ptr;
508 }
0da34b6d
BG		 509 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
510 ptr += 3;
511 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
512 }
513 while (ptr < limit && *ptr++) ;
514 }
515
516 return 0;
517
518abort:
519 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
520 return -ENXIO;
521}
522
523/*
524 * Enable or disable periodic RDMAs from the host to make certain
525 * chipsets resend dropped PCIe messages
526 */
527
528static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
529{
530 char __iomem *submit;
f8fd57c1 531 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 532 u32 dma_low, dma_high;
533 int i;
534
535 /* clear confirmation addr */
536 mgp->cmd->data = 0;
537 mb();
538
539 /* send a rdma command to the PCIe engine, and wait for the
540 * response in the confirmation address. The firmware should
541 * write a -1 there to indicate it is alive and well
542 */
543 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
544 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
545
546 buf[0] = htonl(dma_high); /* confirm addr MSW */
547 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 548 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 549 buf[3] = htonl(dma_high); /* dummy addr MSW */
550 buf[4] = htonl(dma_low); /* dummy addr LSW */
551 buf[5] = htonl(enable); /* enable? */
552
e700f9f4 553 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 554
555 myri10ge_pio_copy(submit, &buf, sizeof(buf));
556 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
557 msleep(1);
558 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
559 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
560 (enable ? "enable" : "disable"));
561}
562
563static int
564myri10ge_validate_firmware(struct myri10ge_priv *mgp,
565 struct mcp_gen_header *hdr)
566{
567 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 568
569 /* check firmware type */
570 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
571 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
572 return -EINVAL;
573 }
574
575 /* save firmware version for ethtool */
576 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
8dff81e8 577 mgp->fw_version[sizeof(mgp->fw_version) - 1] = '\0';
0da34b6d 578
9dc6f0e7
BG		 579 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
580 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 581
8e95a202
JP		 582 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
583 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 584 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
585 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
586 MXGEFW_VERSION_MINOR);
587 return -EINVAL;
588 }
589 return 0;
590}
591
592static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
593{
594 unsigned crc, reread_crc;
595 const struct firmware *fw;
596 struct device *dev = &mgp->pdev->dev;
b0d31d6b 597 unsigned char *fw_readback;
0da34b6d
BG		 598 struct mcp_gen_header *hdr;
599 size_t hdr_offset;
600 int status;
e454358a 601 unsigned i;
0da34b6d
BG		 602
603 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
604 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
605 mgp->fw_name);
606 status = -EINVAL;
607 goto abort_with_nothing;
608 }
609
610 /* check size */
611
612 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
613 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
614 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
615 status = -EINVAL;
616 goto abort_with_fw;
617 }
618
619 /* check id */
40f6cff5 620 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 621 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
622 dev_err(dev, "Bad firmware file\n");
623 status = -EINVAL;
624 goto abort_with_fw;
625 }
626 hdr = (void *)(fw->data + hdr_offset);
627
628 status = myri10ge_validate_firmware(mgp, hdr);
629 if (status != 0)
630 goto abort_with_fw;
631
632 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 633 for (i = 0; i < fw->size; i += 256) {
634 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
635 fw->data + i,
636 min(256U, (unsigned)(fw->size - i)));
637 mb();
638 readb(mgp->sram);
b10c0668 639 }
b0d31d6b
DW		 640 fw_readback = vmalloc(fw->size);
641 if (!fw_readback) {
642 status = -ENOMEM;
643 goto abort_with_fw;
644 }
0da34b6d 645 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 646 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
647 reread_crc = crc32(~0, fw_readback, fw->size);
648 vfree(fw_readback);
0da34b6d
BG		 649 if (crc != reread_crc) {
650 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
651 (unsigned)fw->size, reread_crc, crc);
652 status = -EIO;
653 goto abort_with_fw;
654 }
655 *size = (u32) fw->size;
656
657abort_with_fw:
658 release_firmware(fw);
659
660abort_with_nothing:
661 return status;
662}
663
664static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
665{
666 struct mcp_gen_header *hdr;
667 struct device *dev = &mgp->pdev->dev;
668 const size_t bytes = sizeof(struct mcp_gen_header);
669 size_t hdr_offset;
670 int status;
671
672 /* find running firmware header */
66341fff 673 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 674
675 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
676 dev_err(dev, "Running firmware has bad header offset (%d)\n",
677 (int)hdr_offset);
678 return -EIO;
679 }
680
681 /* copy header of running firmware from SRAM to host memory to
682 * validate firmware */
683 hdr = kmalloc(bytes, GFP_KERNEL);
b2adaca9 684 if (hdr == NULL)
0da34b6d 685 return -ENOMEM;
b2adaca9 686
0da34b6d
BG		 687 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
688 status = myri10ge_validate_firmware(mgp, hdr);
689 kfree(hdr);
9dc6f0e7
BG		 690
691 /* check to see if adopted firmware has bug where adopting
692 * it will cause broadcasts to be filtered unless the NIC
693 * is kept in ALLMULTI mode */
694 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
695 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
696 mgp->adopted_rx_filter_bug = 1;
697 dev_warn(dev, "Adopting fw %d.%d.%d: "
698 "working around rx filter bug\n",
699 mgp->fw_ver_major, mgp->fw_ver_minor,
700 mgp->fw_ver_tiny);
701 }
0da34b6d
BG		 702 return status;
703}
704
0178ec3d 705static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 706{
707 struct myri10ge_cmd cmd;
708 int status;
709
710 /* probe for IPv6 TSO support */
711 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
712 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
713 &cmd, 0);
714 if (status == 0) {
715 mgp->max_tso6 = cmd.data0;
716 mgp->features |= NETIF_F_TSO6;
717 }
718
719 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
720 if (status != 0) {
721 dev_err(&mgp->pdev->dev,
722 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
723 return -ENXIO;
724 }
725
726 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
727
728 return 0;
729}
730
0dcffac1 731static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 732{
733 char __iomem *submit;
f8fd57c1 734 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 735 u32 dma_low, dma_high, size;
736 int status, i;
737
b10c0668 738 size = 0;
0da34b6d
BG		 739 status = myri10ge_load_hotplug_firmware(mgp, &size);
740 if (status) {
0dcffac1
BG		 741 if (!adopt)
742 return status;
0da34b6d
BG		 743 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
744
745 /* Do not attempt to adopt firmware if there
746 * was a bad crc */
747 if (status == -EIO)
748 return status;
749
750 status = myri10ge_adopt_running_firmware(mgp);
751 if (status != 0) {
752 dev_err(&mgp->pdev->dev,
753 "failed to adopt running firmware\n");
754 return status;
755 }
756 dev_info(&mgp->pdev->dev,
757 "Successfully adopted running firmware\n");
b53bef84 758 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 759 dev_warn(&mgp->pdev->dev,
760 "Using firmware currently running on NIC"
761 ". For optimal\n");
762 dev_warn(&mgp->pdev->dev,
763 "performance consider loading optimized "
764 "firmware\n");
765 dev_warn(&mgp->pdev->dev, "via hotplug\n");
766 }
767
7d351035 768 set_fw_name(mgp, "adopted", false);
b53bef84 769 mgp->tx_boundary = 2048;
fa0a90d9
BG		 770 myri10ge_dummy_rdma(mgp, 1);
771 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 772 return status;
773 }
774
775 /* clear confirmation addr */
776 mgp->cmd->data = 0;
777 mb();
778
779 /* send a reload command to the bootstrap MCP, and wait for the
780 * response in the confirmation address. The firmware should
781 * write a -1 there to indicate it is alive and well
782 */
783 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
784 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
785
786 buf[0] = htonl(dma_high); /* confirm addr MSW */
787 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 788 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 789
790 /* FIX: All newest firmware should un-protect the bottom of
791 * the sram before handoff. However, the very first interfaces
792 * do not. Therefore the handoff copy must skip the first 8 bytes
793 */
794 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
795 buf[4] = htonl(size - 8); /* length of code */
796 buf[5] = htonl(8); /* where to copy to */
797 buf[6] = htonl(0); /* where to jump to */
798
e700f9f4 799 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 800
801 myri10ge_pio_copy(submit, &buf, sizeof(buf));
802 mb();
803 msleep(1);
804 mb();
805 i = 0;
d93ca2a4
BG		 806 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
807 msleep(1 << i);
0da34b6d
BG		 808 i++;
809 }
810 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
811 dev_err(&mgp->pdev->dev, "handoff failed\n");
812 return -ENXIO;
813 }
9a71db72 814 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 815 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 816
fa0a90d9 817 return status;
0da34b6d
BG		 818}
819
820static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
821{
822 struct myri10ge_cmd cmd;
823 int status;
824
825 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
826 | (addr[2] << 8) | addr[3]);
827
828 cmd.data1 = ((addr[4] << 8) | (addr[5]));
829
830 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
831 return status;
832}
833
834static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
835{
836 struct myri10ge_cmd cmd;
837 int status, ctl;
838
839 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
840 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
841
842 if (status) {
78ca90ea 843 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 844 return status;
845 }
846 mgp->pause = pause;
847 return 0;
848}
849
850static void
851myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
852{
853 struct myri10ge_cmd cmd;
854 int status, ctl;
855
856 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
857 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
858 if (status)
78ca90ea 859 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 860}
861
0d6ac257 862static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 863{
864 struct myri10ge_cmd cmd;
865 int status;
0da34b6d 866 u32 len;
34fdccea
BG		 867 struct page *dmatest_page;
868 dma_addr_t dmatest_bus;
0d6ac257
BG		 869 char *test = " ";
870
871 dmatest_page = alloc_page(GFP_KERNEL);
872 if (!dmatest_page)
873 return -ENOMEM;
874 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
875 DMA_BIDIRECTIONAL);
876
877 /* Run a small DMA test.
878 * The magic multipliers to the length tell the firmware
879 * to do DMA read, write, or read+write tests. The
880 * results are returned in cmd.data0. The upper 16
881 * bits or the return is the number of transfers completed.
882 * The lower 16 bits is the time in 0.5us ticks that the
883 * transfers took to complete.
884 */
885
b53bef84 886 len = mgp->tx_boundary;
0d6ac257
BG		 887
888 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
889 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
890 cmd.data2 = len * 0x10000;
891 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
892 if (status != 0) {
893 test = "read";
894 goto abort;
895 }
896 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
897 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
898 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
899 cmd.data2 = len * 0x1;
900 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
901 if (status != 0) {
902 test = "write";
903 goto abort;
904 }
905 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
906
907 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
908 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
909 cmd.data2 = len * 0x10001;
910 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
911 if (status != 0) {
912 test = "read/write";
913 goto abort;
914 }
915 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
916 (cmd.data0 & 0xffff);
917
918abort:
919 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
920 put_page(dmatest_page);
921
922 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
923 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
924 test, status);
925
926 return status;
927}
928
0dde8026
HYK		 929#ifdef CONFIG_NET_RX_BUSY_POLL
930static inline void myri10ge_ss_init_lock(struct myri10ge_slice_state *ss)
931{
932 spin_lock_init(&ss->lock);
933 ss->state = SLICE_STATE_IDLE;
934}
935
936static inline bool myri10ge_ss_lock_napi(struct myri10ge_slice_state *ss)
937{
de36cef3 938 bool rc = true;
0dde8026
HYK		 939 spin_lock(&ss->lock);
940 if ((ss->state & SLICE_LOCKED)) {
941 WARN_ON((ss->state & SLICE_STATE_NAPI));
942 ss->state |= SLICE_STATE_NAPI_YIELD;
943 rc = false;
944 ss->lock_napi_yield++;
945 } else
946 ss->state = SLICE_STATE_NAPI;
947 spin_unlock(&ss->lock);
948 return rc;
949}
950
951static inline void myri10ge_ss_unlock_napi(struct myri10ge_slice_state *ss)
952{
953 spin_lock(&ss->lock);
954 WARN_ON((ss->state & (SLICE_STATE_POLL | SLICE_STATE_NAPI_YIELD)));
955 ss->state = SLICE_STATE_IDLE;
956 spin_unlock(&ss->lock);
957}
958
959static inline bool myri10ge_ss_lock_poll(struct myri10ge_slice_state *ss)
960{
de36cef3 961 bool rc = true;
0dde8026
HYK		 962 spin_lock_bh(&ss->lock);
963 if ((ss->state & SLICE_LOCKED)) {
964 ss->state |= SLICE_STATE_POLL_YIELD;
965 rc = false;
966 ss->lock_poll_yield++;
967 } else
968 ss->state |= SLICE_STATE_POLL;
969 spin_unlock_bh(&ss->lock);
970 return rc;
971}
972
973static inline void myri10ge_ss_unlock_poll(struct myri10ge_slice_state *ss)
974{
975 spin_lock_bh(&ss->lock);
976 WARN_ON((ss->state & SLICE_STATE_NAPI));
977 ss->state = SLICE_STATE_IDLE;
978 spin_unlock_bh(&ss->lock);
979}
980
981static inline bool myri10ge_ss_busy_polling(struct myri10ge_slice_state *ss)
982{
983 WARN_ON(!(ss->state & SLICE_LOCKED));
984 return (ss->state & SLICE_USER_PEND);
985}
986#else /* CONFIG_NET_RX_BUSY_POLL */
987static inline void myri10ge_ss_init_lock(struct myri10ge_slice_state *ss)
988{
989}
990
991static inline bool myri10ge_ss_lock_napi(struct myri10ge_slice_state *ss)
992{
993 return false;
994}
995
996static inline void myri10ge_ss_unlock_napi(struct myri10ge_slice_state *ss)
997{
998}
999
1000static inline bool myri10ge_ss_lock_poll(struct myri10ge_slice_state *ss)
1001{
1002 return false;
1003}
1004
1005static inline void myri10ge_ss_unlock_poll(struct myri10ge_slice_state *ss)
1006{
1007}
1008
1009static inline bool myri10ge_ss_busy_polling(struct myri10ge_slice_state *ss)
1010{
1011 return false;
1012}
1013#endif
1014
0d6ac257
BG		 1015static int myri10ge_reset(struct myri10ge_priv *mgp)
1016{
1017 struct myri10ge_cmd cmd;
0dcffac1
BG		 1018 struct myri10ge_slice_state *ss;
1019 int i, status;
0d6ac257 1020 size_t bytes;
5dd2d332 1021#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1022 unsigned long dca_tag_off;
1023#endif
0da34b6d
BG		 1024
1025 /* try to send a reset command to the card to see if it
1026 * is alive */
1027 memset(&cmd, 0, sizeof(cmd));
1028 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
1029 if (status != 0) {
1030 dev_err(&mgp->pdev->dev, "failed reset\n");
1031 return -ENXIO;
1032 }
0d6ac257
BG		 1033
1034 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 1035 /*
1036 * Use non-ndis mcp_slot (eg, 4 bytes total,
1037 * no toeplitz hash value returned. Older firmware will
1038 * not understand this command, but will use the correct
1039 * sized mcp_slot, so we ignore error returns
1040 */
1041 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
1042 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 1043
1044 /* Now exchange information about interrupts */
1045
0dcffac1 1046 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 1047 cmd.data0 = (u32) bytes;
1048 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 1049
1050 /*
1051 * Even though we already know how many slices are supported
1052 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
1053 * has magic side effects, and must be called after a reset.
1054 * It must be called prior to calling any RSS related cmds,
1055 * including assigning an interrupt queue for anything but
1056 * slice 0. It must also be called *after*
1057 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
1058 * the firmware to compute offsets.
1059 */
1060
1061 if (mgp->num_slices > 1) {
1062
1063 /* ask the maximum number of slices it supports */
1064 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
1065 &cmd, 0);
1066 if (status != 0) {
1067 dev_err(&mgp->pdev->dev,
1068 "failed to get number of slices\n");
1069 }
1070
1071 /*
1072 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
1073 * to setting up the interrupt queue DMA
1074 */
1075
1076 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 1077 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1078 if (mgp->dev->real_num_tx_queues > 1)
1079 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 1080 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
1081 &cmd, 0);
236bb5e6
BG		 1082
1083 /* Firmware older than 1.4.32 only supports multiple
1084 * RX queues, so if we get an error, first retry using a
1085 * single TX queue before giving up */
1086 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
c9920268 1087 netif_set_real_num_tx_queues(mgp->dev, 1);
236bb5e6
BG		 1088 cmd.data0 = mgp->num_slices;
1089 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1090 status = myri10ge_send_cmd(mgp,
1091 MXGEFW_CMD_ENABLE_RSS_QUEUES,
1092 &cmd, 0);
1093 }
1094
0dcffac1
BG		 1095 if (status != 0) {
1096 dev_err(&mgp->pdev->dev,
1097 "failed to set number of slices\n");
1098
1099 return status;
1100 }
1101 }
1102 for (i = 0; i < mgp->num_slices; i++) {
1103 ss = &mgp->ss[i];
1104 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1105 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1106 cmd.data2 = i;
1107 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1108 &cmd, 0);
6403eab1 1109 }
0da34b6d
BG		 1110
1111 status |=
1112 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1113 for (i = 0; i < mgp->num_slices; i++) {
1114 ss = &mgp->ss[i];
1115 ss->irq_claim =
1116 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1117 }
df30a740
BG		 1118 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1119 &cmd, 0);
1120 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1121
0da34b6d
BG		 1122 status |= myri10ge_send_cmd
1123 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1124 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1125 if (status != 0) {
1126 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1127 return status;
1128 }
40f6cff5 1129 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1130
5dd2d332 1131#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1132 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1133 dca_tag_off = cmd.data0;
1134 for (i = 0; i < mgp->num_slices; i++) {
1135 ss = &mgp->ss[i];
1136 if (status == 0) {
1137 ss->dca_tag = (__iomem __be32 *)
1138 (mgp->sram + dca_tag_off + 4 * i);
1139 } else {
1140 ss->dca_tag = NULL;
1141 }
1142 }
4ee2ac51 1143#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1144
0da34b6d 1145 /* reset mcp/driver shared state back to 0 */
0dcffac1 1146
c58ac5ca 1147 mgp->link_changes = 0;
0dcffac1
BG		 1148 for (i = 0; i < mgp->num_slices; i++) {
1149 ss = &mgp->ss[i];
1150
1151 memset(ss->rx_done.entry, 0, bytes);
1152 ss->tx.req = 0;
1153 ss->tx.done = 0;
1154 ss->tx.pkt_start = 0;
1155 ss->tx.pkt_done = 0;
1156 ss->rx_big.cnt = 0;
1157 ss->rx_small.cnt = 0;
1158 ss->rx_done.idx = 0;
1159 ss->rx_done.cnt = 0;
1160 ss->tx.wake_queue = 0;
1161 ss->tx.stop_queue = 0;
1162 }
1163
0da34b6d 1164 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1165 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1166 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1167 return status;
1168}
1169
5dd2d332 1170#ifdef CONFIG_MYRI10GE_DCA
ef09aadf
AG		 1171static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1172{
9503e255 1173 int ret;
ef09aadf
AG		 1174 u16 ctl;
1175
9503e255 1176 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &ctl);
b3b6ae2c 1177
ef09aadf
AG		 1178 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1179 if (ret != on) {
1180 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1181 ctl |= (on << 4);
9503e255 1182 pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, ctl);
ef09aadf
AG		 1183 }
1184 return ret;
1185}
1186
981813d8
BG		 1187static void
1188myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1189{
981813d8
BG		 1190 ss->cached_dca_tag = tag;
1191 put_be32(htonl(tag), ss->dca_tag);
1192}
1193
1194static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1195{
1196 int cpu = get_cpu();
1197 int tag;
1198
1199 if (cpu != ss->cpu) {
ef09aadf 1200 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
981813d8
BG		 1201 if (ss->cached_dca_tag != tag)
1202 myri10ge_write_dca(ss, cpu, tag);
ef09aadf 1203 ss->cpu = cpu;
981813d8
BG		 1204 }
1205 put_cpu();
1206}
1207
1208static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1209{
1210 int err, i;
1211 struct pci_dev *pdev = mgp->pdev;
1212
1213 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1214 return;
1215 if (!myri10ge_dca) {
1216 dev_err(&pdev->dev, "dca disabled by administrator\n");
1217 return;
1218 }
1219 err = dca_add_requester(&pdev->dev);
1220 if (err) {
330554cb
BG		 1221 if (err != -ENODEV)
1222 dev_err(&pdev->dev,
1223 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1224 return;
1225 }
ef09aadf 1226 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
981813d8 1227 mgp->dca_enabled = 1;
ef09aadf
AG		 1228 for (i = 0; i < mgp->num_slices; i++) {
1229 mgp->ss[i].cpu = -1;
1230 mgp->ss[i].cached_dca_tag = -1;
1231 myri10ge_update_dca(&mgp->ss[i]);
b3b6ae2c 1232 }
981813d8
BG		 1233}
1234
1235static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1236{
1237 struct pci_dev *pdev = mgp->pdev;
981813d8
BG		 1238
1239 if (!mgp->dca_enabled)
1240 return;
1241 mgp->dca_enabled = 0;
ef09aadf
AG		 1242 if (mgp->relaxed_order)
1243 myri10ge_toggle_relaxed(pdev, 1);
b3b6ae2c 1244 dca_remove_requester(&pdev->dev);
981813d8
BG		 1245}
1246
1247static int myri10ge_notify_dca_device(struct device *dev, void *data)
1248{
1249 struct myri10ge_priv *mgp;
1250 unsigned long event;
1251
1252 mgp = dev_get_drvdata(dev);
1253 event = *(unsigned long *)data;
1254
1255 if (event == DCA_PROVIDER_ADD)
1256 myri10ge_setup_dca(mgp);
1257 else if (event == DCA_PROVIDER_REMOVE)
1258 myri10ge_teardown_dca(mgp);
1259 return 0;
1260}
4ee2ac51 1261#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1262
0da34b6d
BG		 1263static inline void
1264myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1265 struct mcp_kreq_ether_recv *src)
1266{
40f6cff5 1267 __be32 low;
0da34b6d
BG		 1268
1269 low = src->addr_low;
284901a9 1270 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1271 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1272 mb();
1273 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1274 mb();
1275 src->addr_low = low;
40f6cff5 1276 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1277 mb();
1278}
1279
40f6cff5 1280static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1281{
1282 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1283
40f6cff5 1284 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1285 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1286 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1287 skb->csum = hw_csum;
84fa7933 1288 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1289 }
1290}
1291
dd50f336
BG		 1292static void
1293myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1294 int bytes, int watchdog)
1295{
1296 struct page *page;
1297 int idx;
2a3f2790
BG		 1298#if MYRI10GE_ALLOC_SIZE > 4096
1299 int end_offset;
1300#endif
dd50f336
BG		 1301
1302 if (unlikely(rx->watchdog_needed && !watchdog))
1303 return;
1304
1305 /* try to refill entire ring */
1306 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1307 idx = rx->fill_cnt & rx->mask;
ae8509b1 1308 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1309 /* we can use part of previous page */
1310 get_page(rx->page);
1311 } else {
1312 /* we need a new page */
1313 page =
1314 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1315 MYRI10GE_ALLOC_ORDER);
1316 if (unlikely(page == NULL)) {
1317 if (rx->fill_cnt - rx->cnt < 16)
1318 rx->watchdog_needed = 1;
1319 return;
1320 }
1321 rx->page = page;
1322 rx->page_offset = 0;
1323 rx->bus = pci_map_page(mgp->pdev, page, 0,
1324 MYRI10GE_ALLOC_SIZE,
1325 PCI_DMA_FROMDEVICE);
1326 }
1327 rx->info[idx].page = rx->page;
1328 rx->info[idx].page_offset = rx->page_offset;
1329 /* note that this is the address of the start of the
1330 * page */
c755b4b6 1331 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
dd50f336
BG		 1332 rx->shadow[idx].addr_low =
1333 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1334 rx->shadow[idx].addr_high =
1335 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1336
1337 /* start next packet on a cacheline boundary */
1338 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1339
1340#if MYRI10GE_ALLOC_SIZE > 4096
1341 /* don't cross a 4KB boundary */
2a3f2790
BG		 1342 end_offset = rx->page_offset + bytes - 1;
1343 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1344 rx->page_offset = end_offset & ~4095;
ae8509b1 1345#endif
dd50f336
BG		 1346 rx->fill_cnt++;
1347
1348 /* copy 8 descriptors to the firmware at a time */
1349 if ((idx & 7) == 7) {
e454e7e2
BG		 1350 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1351 &rx->shadow[idx - 7]);
dd50f336
BG		 1352 }
1353 }
1354}
1355
1356static inline void
1357myri10ge_unmap_rx_page(struct pci_dev *pdev,
1358 struct myri10ge_rx_buffer_state *info, int bytes)
1359{
1360 /* unmap the recvd page if we're the only or last user of it */
1361 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1362 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
c755b4b6 1363 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
dd50f336
BG		 1364 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1365 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1366 }
1367}
1368
1b4c44e6
AG		 1369/*
1370 * GRO does not support acceleration of tagged vlan frames, and
1371 * this NIC does not support vlan tag offload, so we must pop
1372 * the tag ourselves to be able to achieve GRO performance that
1373 * is comparable to LRO.
1374 */
1375
1376static inline void
1377myri10ge_vlan_rx(struct net_device *dev, void *addr, struct sk_buff *skb)
1378{
1379 u8 *va;
1380 struct vlan_ethhdr *veh;
1381 struct skb_frag_struct *frag;
1382 __wsum vsum;
1383
1384 va = addr;
1385 va += MXGEFW_PAD;
1386 veh = (struct vlan_ethhdr *)va;
f646968f
PM		 1387 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
1388 NETIF_F_HW_VLAN_CTAG_RX &&
30828d2b 1389 veh->h_vlan_proto == htons(ETH_P_8021Q)) {
1b4c44e6
AG		 1390 /* fixup csum if needed */
1391 if (skb->ip_summed == CHECKSUM_COMPLETE) {
1392 vsum = csum_partial(va + ETH_HLEN, VLAN_HLEN, 0);
1393 skb->csum = csum_sub(skb->csum, vsum);
1394 }
1395 /* pop tag */
86a9bad3 1396 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(veh->h_vlan_TCI));
1b4c44e6
AG		 1397 memmove(va + VLAN_HLEN, va, 2 * ETH_ALEN);
1398 skb->len -= VLAN_HLEN;
1399 skb->data_len -= VLAN_HLEN;
1400 frag = skb_shinfo(skb)->frags;
1401 frag->page_offset += VLAN_HLEN;
1402 skb_frag_size_set(frag, skb_frag_size(frag) - VLAN_HLEN);
1403 }
1404}
1405
0dde8026
HYK		 1406#define MYRI10GE_HLEN 64 /* Bytes to copy from page to skb linear memory */
1407
dd50f336 1408static inline int
4ca3221f 1409myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum)
dd50f336 1410{
b53bef84 1411 struct myri10ge_priv *mgp = ss->mgp;
dd50f336 1412 struct sk_buff *skb;
4ca3221f 1413 struct skb_frag_struct *rx_frags;
b3cd9657 1414 struct myri10ge_rx_buf *rx;
4ca3221f 1415 int i, idx, remainder, bytes;
dd50f336
BG		 1416 struct pci_dev *pdev = mgp->pdev;
1417 struct net_device *dev = mgp->dev;
1418 u8 *va;
0dde8026 1419 bool polling;
dd50f336 1420
b3cd9657
SG		 1421 if (len <= mgp->small_bytes) {
1422 rx = &ss->rx_small;
1423 bytes = mgp->small_bytes;
1424 } else {
1425 rx = &ss->rx_big;
1426 bytes = mgp->big_bytes;
1427 }
1428
dd50f336
BG		 1429 len += MXGEFW_PAD;
1430 idx = rx->cnt & rx->mask;
1431 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1432 prefetch(va);
4ca3221f 1433
0dde8026
HYK		 1434 /* When busy polling in user context, allocate skb and copy headers to
1435 * skb's linear memory ourselves. When not busy polling, use the napi
1436 * gro api.
1437 */
1438 polling = myri10ge_ss_busy_polling(ss);
1439 if (polling)
1440 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1441 else
1442 skb = napi_get_frags(&ss->napi);
4ca3221f
AG		 1443 if (unlikely(skb == NULL)) {
1444 ss->stats.rx_dropped++;
1445 for (i = 0, remainder = len; remainder > 0; i++) {
1446 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1447 put_page(rx->info[idx].page);
1448 rx->cnt++;
1449 idx = rx->cnt & rx->mask;
1450 remainder -= MYRI10GE_ALLOC_SIZE;
1451 }
1452 return 0;
1453 }
1454 rx_frags = skb_shinfo(skb)->frags;
dd50f336
BG		 1455 /* Fill skb_frag_struct(s) with data from our receive */
1456 for (i = 0, remainder = len; remainder > 0; i++) {
1457 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
4ca3221f
AG		 1458 skb_fill_page_desc(skb, i, rx->info[idx].page,
1459 rx->info[idx].page_offset,
1460 remainder < MYRI10GE_ALLOC_SIZE ?
1461 remainder : MYRI10GE_ALLOC_SIZE);
dd50f336
BG		 1462 rx->cnt++;
1463 idx = rx->cnt & rx->mask;
1464 remainder -= MYRI10GE_ALLOC_SIZE;
1465 }
1466
4ca3221f
AG		 1467 /* remove padding */
1468 rx_frags[0].page_offset += MXGEFW_PAD;
1469 rx_frags[0].size -= MXGEFW_PAD;
1470 len -= MXGEFW_PAD;
dd50f336 1471
4ca3221f
AG		 1472 skb->len = len;
1473 skb->data_len = len;
1474 skb->truesize += len;
1475 if (dev->features & NETIF_F_RXCSUM) {
1476 skb->ip_summed = CHECKSUM_COMPLETE;
1477 skb->csum = csum;
dd50f336 1478 }
1b4c44e6 1479 myri10ge_vlan_rx(mgp->dev, va, skb);
0c8dfc83 1480 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
0dde8026
HYK		 1481 skb_mark_napi_id(skb, &ss->napi);
1482
1483 if (polling) {
1484 int hlen;
1485
1486 /* myri10ge_vlan_rx might have moved the header, so compute
1487 * length and address again.
1488 */
1489 hlen = MYRI10GE_HLEN > skb->len ? skb->len : MYRI10GE_HLEN;
1490 va = page_address(skb_frag_page(&rx_frags[0])) +
1491 rx_frags[0].page_offset;
1492 /* Copy header into the skb linear memory */
1493 skb_copy_to_linear_data(skb, va, hlen);
1494 rx_frags[0].page_offset += hlen;
1495 rx_frags[0].size -= hlen;
1496 skb->data_len -= hlen;
1497 skb->tail += hlen;
1498 skb->protocol = eth_type_trans(skb, dev);
1499 netif_receive_skb(skb);
1500 }
1501 else
1502 napi_gro_frags(&ss->napi);
dd50f336 1503
dd50f336
BG		 1504 return 1;
1505}
1506
b53bef84
BG		 1507static inline void
1508myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1509{
b53bef84
BG		 1510 struct pci_dev *pdev = ss->mgp->pdev;
1511 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1512 struct netdev_queue *dev_queue;
0da34b6d
BG		 1513 struct sk_buff *skb;
1514 int idx, len;
0da34b6d
BG		 1515
1516 while (tx->pkt_done != mcp_index) {
1517 idx = tx->done & tx->mask;
1518 skb = tx->info[idx].skb;
1519
1520 /* Mark as free */
1521 tx->info[idx].skb = NULL;
1522 if (tx->info[idx].last) {
1523 tx->pkt_done++;
1524 tx->info[idx].last = 0;
1525 }
1526 tx->done++;
c755b4b6
FT		 1527 len = dma_unmap_len(&tx->info[idx], len);
1528 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 1529 if (skb) {
b53bef84
BG		 1530 ss->stats.tx_bytes += skb->len;
1531 ss->stats.tx_packets++;
0da34b6d
BG		 1532 dev_kfree_skb_irq(skb);
1533 if (len)
1534 pci_unmap_single(pdev,
c755b4b6 1535 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1536 bus), len,
1537 PCI_DMA_TODEVICE);
1538 } else {
1539 if (len)
1540 pci_unmap_page(pdev,
c755b4b6 1541 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1542 bus), len,
1543 PCI_DMA_TODEVICE);
1544 }
0da34b6d 1545 }
236bb5e6
BG		 1546
1547 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1548 /*
1549 * Make a minimal effort to prevent the NIC from polling an
1550 * idle tx queue. If we can't get the lock we leave the queue
1551 * active. In this case, either a thread was about to start
1552 * using the queue anyway, or we lost a race and the NIC will
1553 * waste some of its resources polling an inactive queue for a
1554 * while.
1555 */
1556
1557 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1558 __netif_tx_trylock(dev_queue)) {
1559 if (tx->req == tx->done) {
1560 tx->queue_active = 0;
1561 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1562 mb();
6824a105 1563 mmiowb();
236bb5e6
BG		 1564 }
1565 __netif_tx_unlock(dev_queue);
1566 }
1567
0da34b6d 1568 /* start the queue if we've stopped it */
8e95a202 1569 if (netif_tx_queue_stopped(dev_queue) &&
3b20b2dc
JM		 1570 tx->req - tx->done < (tx->mask >> 1) &&
1571 ss->mgp->running == MYRI10GE_ETH_RUNNING) {
b53bef84 1572 tx->wake_queue++;
236bb5e6 1573 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1574 }
1575}
1576
b53bef84
BG		 1577static inline int
1578myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1579{
b53bef84
BG		 1580 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1581 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1582 unsigned long rx_bytes = 0;
1583 unsigned long rx_packets = 0;
1584 unsigned long rx_ok;
0da34b6d
BG		 1585 int idx = rx_done->idx;
1586 int cnt = rx_done->cnt;
bea3348e 1587 int work_done = 0;
0da34b6d 1588 u16 length;
40f6cff5 1589 __wsum checksum;
0da34b6d 1590
c956a240 1591 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1592 length = ntohs(rx_done->entry[idx].length);
1593 rx_done->entry[idx].length = 0;
40f6cff5 1594 checksum = csum_unfold(rx_done->entry[idx].checksum);
4ca3221f 1595 rx_ok = myri10ge_rx_done(ss, length, checksum);
0da34b6d
BG		 1596 rx_packets += rx_ok;
1597 rx_bytes += rx_ok * (unsigned long)length;
1598 cnt++;
014377a1 1599 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1600 work_done++;
0da34b6d
BG		 1601 }
1602 rx_done->idx = idx;
1603 rx_done->cnt = cnt;
b53bef84
BG		 1604 ss->stats.rx_packets += rx_packets;
1605 ss->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1606
1607 /* restock receive rings if needed */
b53bef84
BG		 1608 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1609 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1610 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1611 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1612 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1613
bea3348e 1614 return work_done;
0da34b6d
BG		 1615}
1616
1617static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1618{
0dcffac1 1619 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1620
1621 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1622 unsigned link_up = ntohl(stats->link_up);
1623 if (mgp->link_state != link_up) {
1624 mgp->link_state = link_up;
1625
1626 if (mgp->link_state == MXGEFW_LINK_UP) {
b3b6ae2c 1627 netif_info(mgp, link, mgp->dev, "link up\n");
0da34b6d 1628 netif_carrier_on(mgp->dev);
c58ac5ca 1629 mgp->link_changes++;
0da34b6d 1630 } else {
b3b6ae2c
JM		 1631 netif_info(mgp, link, mgp->dev, "link %s\n",
1632 (link_up == MXGEFW_LINK_MYRINET ?
78ca90ea 1633 "mismatch (Myrinet detected)" :
b3b6ae2c 1634 "down"));
0da34b6d 1635 netif_carrier_off(mgp->dev);
c58ac5ca 1636 mgp->link_changes++;
0da34b6d
BG		 1637 }
1638 }
1639 if (mgp->rdma_tags_available !=
b53bef84 1640 ntohl(stats->rdma_tags_available)) {
0da34b6d 1641 mgp->rdma_tags_available =
b53bef84 1642 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1643 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1644 mgp->rdma_tags_available);
0da34b6d
BG		 1645 }
1646 mgp->down_cnt += stats->link_down;
1647 if (stats->link_down)
1648 wake_up(&mgp->down_wq);
1649 }
1650}
1651
bea3348e 1652static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1653{
b53bef84
BG		 1654 struct myri10ge_slice_state *ss =
1655 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1656 int work_done;
0da34b6d 1657
5dd2d332 1658#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1659 if (ss->mgp->dca_enabled)
1660 myri10ge_update_dca(ss);
1661#endif
0dde8026
HYK		 1662 /* Try later if the busy_poll handler is running. */
1663 if (!myri10ge_ss_lock_napi(ss))
1664 return budget;
981813d8 1665
0da34b6d 1666 /* process as many rx events as NAPI will allow */
b53bef84 1667 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1668
0dde8026 1669 myri10ge_ss_unlock_napi(ss);
4ec24119 1670 if (work_done < budget) {
288379f0 1671 napi_complete(napi);
b53bef84 1672 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1673 }
bea3348e 1674 return work_done;
0da34b6d
BG		 1675}
1676
0dde8026
HYK		 1677#ifdef CONFIG_NET_RX_BUSY_POLL
1678static int myri10ge_busy_poll(struct napi_struct *napi)
1679{
1680 struct myri10ge_slice_state *ss =
1681 container_of(napi, struct myri10ge_slice_state, napi);
1682 struct myri10ge_priv *mgp = ss->mgp;
1683 int work_done;
1684
1685 /* Poll only when the link is up */
1686 if (mgp->link_state != MXGEFW_LINK_UP)
1687 return LL_FLUSH_FAILED;
1688
1689 if (!myri10ge_ss_lock_poll(ss))
1690 return LL_FLUSH_BUSY;
1691
1692 /* Process a small number of packets */
1693 work_done = myri10ge_clean_rx_done(ss, 4);
1694 if (work_done)
1695 ss->busy_poll_cnt += work_done;
1696 else
1697 ss->busy_poll_miss++;
1698
1699 myri10ge_ss_unlock_poll(ss);
1700
1701 return work_done;
1702}
1703#endif /* CONFIG_NET_RX_BUSY_POLL */
1704
7d12e780 1705static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1706{
b53bef84
BG		 1707 struct myri10ge_slice_state *ss = arg;
1708 struct myri10ge_priv *mgp = ss->mgp;
1709 struct mcp_irq_data *stats = ss->fw_stats;
1710 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1711 u32 send_done_count;
1712 int i;
1713
236bb5e6
BG		 1714 /* an interrupt on a non-zero receive-only slice is implicitly
1715 * valid since MSI-X irqs are not shared */
1716 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1717 napi_schedule(&ss->napi);
807540ba 1718 return IRQ_HANDLED;
0dcffac1
BG		 1719 }
1720
0da34b6d
BG		 1721 /* make sure it is our IRQ, and that the DMA has finished */
1722 if (unlikely(!stats->valid))
807540ba 1723 return IRQ_NONE;
0da34b6d
BG		 1724
1725 /* low bit indicates receives are present, so schedule
1726 * napi poll handler */
1727 if (stats->valid & 1)
288379f0 1728 napi_schedule(&ss->napi);
0da34b6d 1729
0dcffac1 1730 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1731 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1732 if (!myri10ge_deassert_wait)
1733 stats->valid = 0;
1734 mb();
1735 } else
1736 stats->valid = 0;
1737
1738 /* Wait for IRQ line to go low, if using INTx */
1739 i = 0;
1740 while (1) {
1741 i++;
1742 /* check for transmit completes and receives */
1743 send_done_count = ntohl(stats->send_done_count);
1744 if (send_done_count != tx->pkt_done)
b53bef84 1745 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1746 if (unlikely(i > myri10ge_max_irq_loops)) {
b3b6ae2c 1747 netdev_warn(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1748 stats->valid = 0;
1749 schedule_work(&mgp->watchdog_work);
1750 }
1751 if (likely(stats->valid == 0))
1752 break;
1753 cpu_relax();
1754 barrier();
1755 }
1756
236bb5e6
BG		 1757 /* Only slice 0 updates stats */
1758 if (ss == mgp->ss)
1759 myri10ge_check_statblock(mgp);
0da34b6d 1760
b53bef84 1761 put_be32(htonl(3), ss->irq_claim + 1);
807540ba 1762 return IRQ_HANDLED;
0da34b6d
BG		 1763}
1764
1765static int
1766myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1767{
c0bf8801
BG		 1768 struct myri10ge_priv *mgp = netdev_priv(netdev);
1769 char *ptr;
1770 int i;
1771
0da34b6d 1772 cmd->autoneg = AUTONEG_DISABLE;
70739497 1773 ethtool_cmd_speed_set(cmd, SPEED_10000);
0da34b6d 1774 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1775
1776 /*
1777 * parse the product code to deterimine the interface type
1778 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1779 * after the 3rd dash in the driver's cached copy of the
1780 * EEPROM's product code string.
1781 */
1782 ptr = mgp->product_code_string;
1783 if (ptr == NULL) {
78ca90ea 1784 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1785 return 0;
1786 }
1787 for (i = 0; i < 3; i++, ptr++) {
1788 ptr = strchr(ptr, '-');
1789 if (ptr == NULL) {
78ca90ea
JP		 1790 netdev_err(netdev, "Invalid product code %s\n",
1791 mgp->product_code_string);
c0bf8801
BG		 1792 return 0;
1793 }
1794 }
196f17eb
BG		 1795 if (*ptr == '2')
1796 ptr++;
1797 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1798 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1799 cmd->port = PORT_FIBRE;
196f17eb
BG		 1800 cmd->supported |= SUPPORTED_FIBRE;
1801 cmd->advertising |= ADVERTISED_FIBRE;
1802 } else {
1803 cmd->port = PORT_OTHER;
c0bf8801 1804 }
196f17eb
BG		 1805 if (*ptr == 'R' || *ptr == 'S')
1806 cmd->transceiver = XCVR_EXTERNAL;
1807 else
1808 cmd->transceiver = XCVR_INTERNAL;
1809
0da34b6d
BG		 1810 return 0;
1811}
1812
1813static void
1814myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1815{
1816 struct myri10ge_priv *mgp = netdev_priv(netdev);
1817
1818 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1819 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1820 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1821 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1822}
1823
1824static int
1825myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1826{
1827 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1828
0da34b6d
BG		 1829 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1830 return 0;
1831}
1832
1833static int
1834myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1835{
1836 struct myri10ge_priv *mgp = netdev_priv(netdev);
1837
1838 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1839 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1840 return 0;
1841}
1842
1843static void
1844myri10ge_get_pauseparam(struct net_device *netdev,
1845 struct ethtool_pauseparam *pause)
1846{
1847 struct myri10ge_priv *mgp = netdev_priv(netdev);
1848
1849 pause->autoneg = 0;
1850 pause->rx_pause = mgp->pause;
1851 pause->tx_pause = mgp->pause;
1852}
1853
1854static int
1855myri10ge_set_pauseparam(struct net_device *netdev,
1856 struct ethtool_pauseparam *pause)
1857{
1858 struct myri10ge_priv *mgp = netdev_priv(netdev);
1859
1860 if (pause->tx_pause != mgp->pause)
1861 return myri10ge_change_pause(mgp, pause->tx_pause);
1862 if (pause->rx_pause != mgp->pause)
2488f56d 1863 return myri10ge_change_pause(mgp, pause->rx_pause);
0da34b6d
BG		 1864 if (pause->autoneg != 0)
1865 return -EINVAL;
1866 return 0;
1867}
1868
1869static void
1870myri10ge_get_ringparam(struct net_device *netdev,
1871 struct ethtool_ringparam *ring)
1872{
1873 struct myri10ge_priv *mgp = netdev_priv(netdev);
1874
0dcffac1
BG		 1875 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1876 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1877 ring->rx_jumbo_max_pending = 0;
6498be3f 1878 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1879 ring->rx_mini_pending = ring->rx_mini_max_pending;
1880 ring->rx_pending = ring->rx_max_pending;
1881 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1882 ring->tx_pending = ring->tx_max_pending;
1883}
1884
b53bef84 1885static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1886 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1887 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1888 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1889 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1890 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1891 "tx_heartbeat_errors", "tx_window_errors",
1892 /* device-specific stats */
0dcffac1 1893 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1894 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1895 "serial_number", "watchdog_resets",
5dd2d332 1896#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1897 "dca_capable_firmware", "dca_device_present",
981813d8 1898#endif
c58ac5ca 1899 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1900 "dropped_link_error_or_filtered",
1901 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1902 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1903 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1904 "dropped_no_big_buffer"
1905};
1906
1907static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1908 "----------- slice ---------",
1909 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1910 "rx_small_cnt", "rx_big_cnt",
b3b6ae2c 1911 "wake_queue", "stop_queue", "tx_linearized",
0dde8026
HYK		 1912#ifdef CONFIG_NET_RX_BUSY_POLL
1913 "rx_lock_napi_yield", "rx_lock_poll_yield", "rx_busy_poll_miss",
1914 "rx_busy_poll_cnt",
1915#endif
0da34b6d
BG		 1916};
1917
1918#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1919#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1920#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1921
1922static void
1923myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1924{
0dcffac1
BG		 1925 struct myri10ge_priv *mgp = netdev_priv(netdev);
1926 int i;
1927
0da34b6d
BG		 1928 switch (stringset) {
1929 case ETH_SS_STATS:
b53bef84
BG		 1930 memcpy(data, *myri10ge_gstrings_main_stats,
1931 sizeof(myri10ge_gstrings_main_stats));
1932 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1933 for (i = 0; i < mgp->num_slices; i++) {
1934 memcpy(data, *myri10ge_gstrings_slice_stats,
1935 sizeof(myri10ge_gstrings_slice_stats));
1936 data += sizeof(myri10ge_gstrings_slice_stats);
1937 }
0da34b6d
BG		 1938 break;
1939 }
1940}
1941
b9f2c044 1942static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1943{
0dcffac1
BG		 1944 struct myri10ge_priv *mgp = netdev_priv(netdev);
1945
b9f2c044
JG		 1946 switch (sset) {
1947 case ETH_SS_STATS:
0dcffac1
BG		 1948 return MYRI10GE_MAIN_STATS_LEN +
1949 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1950 default:
1951 return -EOPNOTSUPP;
1952 }
0da34b6d
BG		 1953}
1954
1955static void
1956myri10ge_get_ethtool_stats(struct net_device *netdev,
1957 struct ethtool_stats *stats, u64 * data)
1958{
1959 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1960 struct myri10ge_slice_state *ss;
c5f7ef72 1961 struct rtnl_link_stats64 link_stats;
0dcffac1 1962 int slice;
0da34b6d
BG		 1963 int i;
1964
59081825 1965 /* force stats update */
306ff6eb 1966 memset(&link_stats, 0, sizeof(link_stats));
c5f7ef72 1967 (void)myri10ge_get_stats(netdev, &link_stats);
0da34b6d 1968 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
c5f7ef72 1969 data[i] = ((u64 *)&link_stats)[i];
0da34b6d 1970
b53bef84 1971 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1972 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1973 data[i++] = (unsigned int)mgp->pdev->irq;
1974 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1975 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1976 data[i++] = (unsigned int)mgp->read_dma;
1977 data[i++] = (unsigned int)mgp->write_dma;
1978 data[i++] = (unsigned int)mgp->read_write_dma;
1979 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1980 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1981#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1982 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1983 data[i++] = (unsigned int)(mgp->dca_enabled);
1984#endif
c58ac5ca 1985 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1986
1987 /* firmware stats are useful only in the first slice */
0dcffac1 1988 ss = &mgp->ss[0];
b53bef84
BG		 1989 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1990 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1991 data[i++] =
b53bef84
BG		 1992 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1993 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1994 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1995 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1996 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1997 data[i++] =
b53bef84
BG		 1998 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1999 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
2000 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
2001 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
2002 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
2003
0dcffac1
BG		 2004 for (slice = 0; slice < mgp->num_slices; slice++) {
2005 ss = &mgp->ss[slice];
2006 data[i++] = slice;
2007 data[i++] = (unsigned int)ss->tx.pkt_start;
2008 data[i++] = (unsigned int)ss->tx.pkt_done;
2009 data[i++] = (unsigned int)ss->tx.req;
2010 data[i++] = (unsigned int)ss->tx.done;
2011 data[i++] = (unsigned int)ss->rx_small.cnt;
2012 data[i++] = (unsigned int)ss->rx_big.cnt;
2013 data[i++] = (unsigned int)ss->tx.wake_queue;
2014 data[i++] = (unsigned int)ss->tx.stop_queue;
2015 data[i++] = (unsigned int)ss->tx.linearized;
0dde8026
HYK		 2016#ifdef CONFIG_NET_RX_BUSY_POLL
2017 data[i++] = ss->lock_napi_yield;
2018 data[i++] = ss->lock_poll_yield;
2019 data[i++] = ss->busy_poll_miss;
2020 data[i++] = ss->busy_poll_cnt;
2021#endif
0dcffac1 2022 }
0da34b6d
BG		 2023}
2024
c58ac5ca
BG		 2025static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
2026{
2027 struct myri10ge_priv *mgp = netdev_priv(netdev);
2028 mgp->msg_enable = value;
2029}
2030
2031static u32 myri10ge_get_msglevel(struct net_device *netdev)
2032{
2033 struct myri10ge_priv *mgp = netdev_priv(netdev);
2034 return mgp->msg_enable;
2035}
2036
5dcd8467
JM		 2037/*
2038 * Use a low-level command to change the LED behavior. Rather than
2039 * blinking (which is the normal case), when identify is used, the
2040 * yellow LED turns solid.
2041 */
2042static int myri10ge_led(struct myri10ge_priv *mgp, int on)
2043{
2044 struct mcp_gen_header *hdr;
2045 struct device *dev = &mgp->pdev->dev;
2046 size_t hdr_off, pattern_off, hdr_len;
2047 u32 pattern = 0xfffffffe;
2048
2049 /* find running firmware header */
2050 hdr_off = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
2051 if ((hdr_off & 3) || hdr_off + sizeof(*hdr) > mgp->sram_size) {
2052 dev_err(dev, "Running firmware has bad header offset (%d)\n",
2053 (int)hdr_off);
2054 return -EIO;
2055 }
2056 hdr_len = swab32(readl(mgp->sram + hdr_off +
2057 offsetof(struct mcp_gen_header, header_length)));
2058 pattern_off = hdr_off + offsetof(struct mcp_gen_header, led_pattern);
2059 if (pattern_off >= (hdr_len + hdr_off)) {
2060 dev_info(dev, "Firmware does not support LED identification\n");
2061 return -EINVAL;
2062 }
2063 if (!on)
2064 pattern = swab32(readl(mgp->sram + pattern_off + 4));
59e955ed 2065 writel(swab32(pattern), mgp->sram + pattern_off);
5dcd8467
JM		 2066 return 0;
2067}
2068
2069static int
2070myri10ge_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
2071{
2072 struct myri10ge_priv *mgp = netdev_priv(netdev);
2073 int rc;
2074
2075 switch (state) {
2076 case ETHTOOL_ID_ACTIVE:
2077 rc = myri10ge_led(mgp, 1);
2078 break;
2079
2080 case ETHTOOL_ID_INACTIVE:
2081 rc = myri10ge_led(mgp, 0);
2082 break;
2083
2084 default:
2085 rc = -EINVAL;
2086 }
2087
2088 return rc;
2089}
2090
7282d491 2091static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 2092 .get_settings = myri10ge_get_settings,
2093 .get_drvinfo = myri10ge_get_drvinfo,
2094 .get_coalesce = myri10ge_get_coalesce,
2095 .set_coalesce = myri10ge_set_coalesce,
2096 .get_pauseparam = myri10ge_get_pauseparam,
2097 .set_pauseparam = myri10ge_set_pauseparam,
2098 .get_ringparam = myri10ge_get_ringparam,
6ffdd071 2099 .get_link = ethtool_op_get_link,
0da34b6d 2100 .get_strings = myri10ge_get_strings,
b9f2c044 2101 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 2102 .get_ethtool_stats = myri10ge_get_ethtool_stats,
2103 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d 2104 .get_msglevel = myri10ge_get_msglevel,
5dcd8467 2105 .set_phys_id = myri10ge_phys_id,
0da34b6d
BG		 2106};
2107
b53bef84 2108static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 2109{
b53bef84 2110 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 2111 struct myri10ge_cmd cmd;
b53bef84 2112 struct net_device *dev = mgp->dev;
0da34b6d
BG		 2113 int tx_ring_size, rx_ring_size;
2114 int tx_ring_entries, rx_ring_entries;
0dcffac1 2115 int i, slice, status;
0da34b6d
BG		 2116 size_t bytes;
2117
0da34b6d 2118 /* get ring sizes */
0dcffac1
BG		 2119 slice = ss - mgp->ss;
2120 cmd.data0 = slice;
0da34b6d
BG		 2121 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
2122 tx_ring_size = cmd.data0;
0dcffac1 2123 cmd.data0 = slice;
0da34b6d 2124 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 2125 if (status != 0)
2126 return status;
0da34b6d
BG		 2127 rx_ring_size = cmd.data0;
2128
2129 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
2130 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 2131 ss->tx.mask = tx_ring_entries - 1;
2132 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 2133
355c7265
BG		 2134 status = -ENOMEM;
2135
0da34b6d
BG		 2136 /* allocate the host shadow rings */
2137
2138 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 2139 * sizeof(*ss->tx.req_list);
2140 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
2141 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 2142 goto abort_with_nothing;
2143
2144 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 2145 ss->tx.req_list = (struct mcp_kreq_ether_send *)
2146 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 2147 ss->tx.queue_active = 0;
0da34b6d 2148
b53bef84
BG		 2149 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
2150 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
2151 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 2152 goto abort_with_tx_req_bytes;
2153
b53bef84
BG		 2154 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
2155 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
2156 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 2157 goto abort_with_rx_small_shadow;
2158
2159 /* allocate the host info rings */
2160
b53bef84
BG		 2161 bytes = tx_ring_entries * sizeof(*ss->tx.info);
2162 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
2163 if (ss->tx.info == NULL)
0da34b6d
BG		 2164 goto abort_with_rx_big_shadow;
2165
b53bef84
BG		 2166 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
2167 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
2168 if (ss->rx_small.info == NULL)
0da34b6d
BG		 2169 goto abort_with_tx_info;
2170
b53bef84
BG		 2171 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
2172 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
2173 if (ss->rx_big.info == NULL)
0da34b6d
BG		 2174 goto abort_with_rx_small_info;
2175
2176 /* Fill the receive rings */
b53bef84
BG		 2177 ss->rx_big.cnt = 0;
2178 ss->rx_small.cnt = 0;
2179 ss->rx_big.fill_cnt = 0;
2180 ss->rx_small.fill_cnt = 0;
2181 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2182 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2183 ss->rx_small.watchdog_needed = 0;
2184 ss->rx_big.watchdog_needed = 0;
4b47638a
JM		 2185 if (mgp->small_bytes == 0) {
2186 ss->rx_small.fill_cnt = ss->rx_small.mask + 1;
2187 } else {
2188 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2189 mgp->small_bytes + MXGEFW_PAD, 0);
2190 }
0da34b6d 2191
b53bef84 2192 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 2193 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2194 slice, ss->rx_small.fill_cnt);
c7dab99b 2195 goto abort_with_rx_small_ring;
0da34b6d
BG		 2196 }
2197
b53bef84
BG		 2198 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2199 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 2200 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2201 slice, ss->rx_big.fill_cnt);
c7dab99b 2202 goto abort_with_rx_big_ring;
0da34b6d
BG		 2203 }
2204
2205 return 0;
2206
2207abort_with_rx_big_ring:
b53bef84
BG		 2208 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2209 int idx = i & ss->rx_big.mask;
2210 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2211 mgp->big_bytes);
b53bef84 2212 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2213 }
2214
2215abort_with_rx_small_ring:
4b47638a
JM		 2216 if (mgp->small_bytes == 0)
2217 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2218 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2219 int idx = i & ss->rx_small.mask;
2220 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2221 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2222 put_page(ss->rx_small.info[idx].page);
0da34b6d 2223 }
c7dab99b 2224
b53bef84 2225 kfree(ss->rx_big.info);
0da34b6d
BG		 2226
2227abort_with_rx_small_info:
b53bef84 2228 kfree(ss->rx_small.info);
0da34b6d
BG		 2229
2230abort_with_tx_info:
b53bef84 2231 kfree(ss->tx.info);
0da34b6d
BG		 2232
2233abort_with_rx_big_shadow:
b53bef84 2234 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2235
2236abort_with_rx_small_shadow:
b53bef84 2237 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2238
2239abort_with_tx_req_bytes:
b53bef84
BG		 2240 kfree(ss->tx.req_bytes);
2241 ss->tx.req_bytes = NULL;
2242 ss->tx.req_list = NULL;
0da34b6d
BG		 2243
2244abort_with_nothing:
2245 return status;
2246}
2247
b53bef84 2248static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2249{
b53bef84 2250 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2251 struct sk_buff *skb;
2252 struct myri10ge_tx_buf *tx;
2253 int i, len, idx;
2254
0dcffac1
BG		 2255 /* If not allocated, skip it */
2256 if (ss->tx.req_list == NULL)
2257 return;
2258
b53bef84
BG		 2259 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2260 idx = i & ss->rx_big.mask;
2261 if (i == ss->rx_big.fill_cnt - 1)
2262 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2263 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2264 mgp->big_bytes);
b53bef84 2265 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2266 }
2267
4b47638a
JM		 2268 if (mgp->small_bytes == 0)
2269 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2270 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2271 idx = i & ss->rx_small.mask;
2272 if (i == ss->rx_small.fill_cnt - 1)
2273 ss->rx_small.info[idx].page_offset =
c7dab99b 2274 MYRI10GE_ALLOC_SIZE;
b53bef84 2275 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2276 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2277 put_page(ss->rx_small.info[idx].page);
c7dab99b 2278 }
b53bef84 2279 tx = &ss->tx;
0da34b6d
BG		 2280 while (tx->done != tx->req) {
2281 idx = tx->done & tx->mask;
2282 skb = tx->info[idx].skb;
2283
2284 /* Mark as free */
2285 tx->info[idx].skb = NULL;
2286 tx->done++;
c755b4b6
FT		 2287 len = dma_unmap_len(&tx->info[idx], len);
2288 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 2289 if (skb) {
b53bef84 2290 ss->stats.tx_dropped++;
0da34b6d
BG		 2291 dev_kfree_skb_any(skb);
2292 if (len)
2293 pci_unmap_single(mgp->pdev,
c755b4b6 2294 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2295 bus), len,
2296 PCI_DMA_TODEVICE);
2297 } else {
2298 if (len)
2299 pci_unmap_page(mgp->pdev,
c755b4b6 2300 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2301 bus), len,
2302 PCI_DMA_TODEVICE);
2303 }
2304 }
b53bef84 2305 kfree(ss->rx_big.info);
0da34b6d 2306
b53bef84 2307 kfree(ss->rx_small.info);
0da34b6d 2308
b53bef84 2309 kfree(ss->tx.info);
0da34b6d 2310
b53bef84 2311 kfree(ss->rx_big.shadow);
0da34b6d 2312
b53bef84 2313 kfree(ss->rx_small.shadow);
0da34b6d 2314
b53bef84
BG		 2315 kfree(ss->tx.req_bytes);
2316 ss->tx.req_bytes = NULL;
2317 ss->tx.req_list = NULL;
0da34b6d
BG		 2318}
2319
df30a740
BG		 2320static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2321{
2322 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2323 struct myri10ge_slice_state *ss;
2324 struct net_device *netdev = mgp->dev;
2325 int i;
df30a740
BG		 2326 int status;
2327
0dcffac1
BG		 2328 mgp->msi_enabled = 0;
2329 mgp->msix_enabled = 0;
2330 status = 0;
df30a740 2331 if (myri10ge_msi) {
0dcffac1 2332 if (mgp->num_slices > 1) {
0729cc0c
AG		 2333 status = pci_enable_msix_range(pdev, mgp->msix_vectors,
2334 mgp->num_slices, mgp->num_slices);
2335 if (status < 0) {
0dcffac1
BG		 2336 dev_err(&pdev->dev,
2337 "Error %d setting up MSI-X\n", status);
2338 return status;
2339 }
0729cc0c 2340 mgp->msix_enabled = 1;
0dcffac1
BG		 2341 }
2342 if (mgp->msix_enabled == 0) {
2343 status = pci_enable_msi(pdev);
2344 if (status != 0) {
2345 dev_err(&pdev->dev,
2346 "Error %d setting up MSI; falling back to xPIC\n",
2347 status);
2348 } else {
2349 mgp->msi_enabled = 1;
2350 }
2351 }
df30a740 2352 }
0dcffac1
BG		 2353 if (mgp->msix_enabled) {
2354 for (i = 0; i < mgp->num_slices; i++) {
2355 ss = &mgp->ss[i];
2356 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2357 "%s:slice-%d", netdev->name, i);
2358 status = request_irq(mgp->msix_vectors[i].vector,
2359 myri10ge_intr, 0, ss->irq_desc,
2360 ss);
2361 if (status != 0) {
2362 dev_err(&pdev->dev,
2363 "slice %d failed to allocate IRQ\n", i);
2364 i--;
2365 while (i >= 0) {
2366 free_irq(mgp->msix_vectors[i].vector,
2367 &mgp->ss[i]);
2368 i--;
2369 }
2370 pci_disable_msix(pdev);
2371 return status;
2372 }
2373 }
2374 } else {
2375 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2376 mgp->dev->name, &mgp->ss[0]);
2377 if (status != 0) {
2378 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2379 if (mgp->msi_enabled)
2380 pci_disable_msi(pdev);
2381 }
df30a740
BG		 2382 }
2383 return status;
2384}
2385
2386static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2387{
2388 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2389 int i;
df30a740 2390
0dcffac1
BG		 2391 if (mgp->msix_enabled) {
2392 for (i = 0; i < mgp->num_slices; i++)
2393 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2394 } else {
2395 free_irq(pdev->irq, &mgp->ss[0]);
2396 }
df30a740
BG		 2397 if (mgp->msi_enabled)
2398 pci_disable_msi(pdev);
0dcffac1
BG		 2399 if (mgp->msix_enabled)
2400 pci_disable_msix(pdev);
df30a740
BG		 2401}
2402
77929732
BG		 2403static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2404{
2405 struct myri10ge_cmd cmd;
2406 struct myri10ge_slice_state *ss;
2407 int status;
2408
2409 ss = &mgp->ss[slice];
236bb5e6
BG		 2410 status = 0;
2411 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2412 cmd.data0 = slice;
2413 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2414 &cmd, 0);
2415 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2416 (mgp->sram + cmd.data0);
2417 }
77929732
BG		 2418 cmd.data0 = slice;
2419 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2420 &cmd, 0);
2421 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2422 (mgp->sram + cmd.data0);
2423
2424 cmd.data0 = slice;
2425 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2426 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2427 (mgp->sram + cmd.data0);
2428
236bb5e6
BG		 2429 ss->tx.send_go = (__iomem __be32 *)
2430 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2431 ss->tx.send_stop = (__iomem __be32 *)
2432 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2433 return status;
2434
2435}
2436
2437static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2438{
2439 struct myri10ge_cmd cmd;
2440 struct myri10ge_slice_state *ss;
2441 int status;
2442
2443 ss = &mgp->ss[slice];
2444 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2445 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2446 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2447 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2448 if (status == -ENOSYS) {
2449 dma_addr_t bus = ss->fw_stats_bus;
2450 if (slice != 0)
2451 return -EINVAL;
2452 bus += offsetof(struct mcp_irq_data, send_done_count);
2453 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2454 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2455 status = myri10ge_send_cmd(mgp,
2456 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2457 &cmd, 0);
2458 /* Firmware cannot support multicast without STATS_DMA_V2 */
2459 mgp->fw_multicast_support = 0;
2460 } else {
2461 mgp->fw_multicast_support = 1;
2462 }
2463 return 0;
2464}
77929732 2465
0da34b6d
BG		 2466static int myri10ge_open(struct net_device *dev)
2467{
0dcffac1 2468 struct myri10ge_slice_state *ss;
b53bef84 2469 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2470 struct myri10ge_cmd cmd;
0dcffac1 2471 int i, status, big_pow2, slice;
59e955ed 2472 u8 __iomem *itable;
0da34b6d 2473
0da34b6d
BG		 2474 if (mgp->running != MYRI10GE_ETH_STOPPED)
2475 return -EBUSY;
2476
2477 mgp->running = MYRI10GE_ETH_STARTING;
2478 status = myri10ge_reset(mgp);
2479 if (status != 0) {
78ca90ea 2480 netdev_err(dev, "failed reset\n");
df30a740 2481 goto abort_with_nothing;
0da34b6d
BG		 2482 }
2483
0dcffac1
BG		 2484 if (mgp->num_slices > 1) {
2485 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2486 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2487 if (mgp->dev->real_num_tx_queues > 1)
2488 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2489 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2490 &cmd, 0);
2491 if (status != 0) {
78ca90ea 2492 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2493 goto abort_with_nothing;
2494 }
2495 /* setup the indirection table */
2496 cmd.data0 = mgp->num_slices;
2497 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2498 &cmd, 0);
2499
2500 status |= myri10ge_send_cmd(mgp,
2501 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2502 &cmd, 0);
2503 if (status != 0) {
78ca90ea 2504 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2505 goto abort_with_nothing;
0dcffac1
BG		 2506 }
2507
2508 /* just enable an identity mapping */
2509 itable = mgp->sram + cmd.data0;
2510 for (i = 0; i < mgp->num_slices; i++)
2511 __raw_writeb(i, &itable[i]);
2512
2513 cmd.data0 = 1;
2514 cmd.data1 = myri10ge_rss_hash;
2515 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2516 &cmd, 0);
2517 if (status != 0) {
78ca90ea 2518 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2519 goto abort_with_nothing;
2520 }
2521 }
2522
df30a740
BG		 2523 status = myri10ge_request_irq(mgp);
2524 if (status != 0)
2525 goto abort_with_nothing;
2526
0da34b6d
BG		 2527 /* decide what small buffer size to use. For good TCP rx
2528 * performance, it is important to not receive 1514 byte
2529 * frames into jumbo buffers, as it confuses the socket buffer
2530 * accounting code, leading to drops and erratic performance.
2531 */
2532
2533 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2534 /* enough for a TCP header */
2535 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2536 ? (128 - MXGEFW_PAD)
2537 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2538 else
de3c4507
BG		 2539 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2540 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2541
2542 /* Override the small buffer size? */
4b47638a 2543 if (myri10ge_small_bytes >= 0)
0da34b6d
BG		 2544 mgp->small_bytes = myri10ge_small_bytes;
2545
0da34b6d
BG		 2546 /* Firmware needs the big buff size as a power of 2. Lie and
2547 * tell him the buffer is larger, because we only use 1
2548 * buffer/pkt, and the mtu will prevent overruns.
2549 */
13348bee 2550 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2551 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2552 while (!is_power_of_2(big_pow2))
c7dab99b 2553 big_pow2++;
13348bee 2554 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2555 } else {
2556 big_pow2 = MYRI10GE_ALLOC_SIZE;
2557 mgp->big_bytes = big_pow2;
2558 }
2559
0dcffac1
BG		 2560 /* setup the per-slice data structures */
2561 for (slice = 0; slice < mgp->num_slices; slice++) {
2562 ss = &mgp->ss[slice];
2563
2564 status = myri10ge_get_txrx(mgp, slice);
2565 if (status != 0) {
78ca90ea 2566 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2567 goto abort_with_rings;
2568 }
2569 status = myri10ge_allocate_rings(ss);
2570 if (status != 0)
2571 goto abort_with_rings;
236bb5e6
BG		 2572
2573 /* only firmware which supports multiple TX queues
2574 * supports setting up the tx stats on non-zero
2575 * slices */
2576 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2577 status = myri10ge_set_stats(mgp, slice);
2578 if (status) {
78ca90ea 2579 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2580 goto abort_with_rings;
2581 }
2582
0dde8026
HYK		 2583 /* Initialize the slice spinlock and state used for polling */
2584 myri10ge_ss_init_lock(ss);
2585
0dcffac1
BG		 2586 /* must happen prior to any irq */
2587 napi_enable(&(ss)->napi);
2588 }
0da34b6d
BG		 2589
2590 /* now give firmware buffers sizes, and MTU */
2591 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2592 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2593 cmd.data0 = mgp->small_bytes;
2594 status |=
2595 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2596 cmd.data0 = big_pow2;
2597 status |=
2598 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2599 if (status) {
78ca90ea 2600 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2601 goto abort_with_rings;
2602 }
2603
0dcffac1
BG		 2604 /*
2605 * Set Linux style TSO mode; this is needed only on newer
2606 * firmware versions. Older versions default to Linux
2607 * style TSO
2608 */
2609 cmd.data0 = 0;
2610 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2611 if (status && status != -ENOSYS) {
78ca90ea 2612 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2613 goto abort_with_rings;
2614 }
2615
66341fff 2616 mgp->link_state = ~0U;
0da34b6d
BG		 2617 mgp->rdma_tags_available = 15;
2618
0da34b6d
BG		 2619 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2620 if (status) {
78ca90ea 2621 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2622 goto abort_with_rings;
2623 }
2624
0da34b6d
BG		 2625 mgp->running = MYRI10GE_ETH_RUNNING;
2626 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2627 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2628 netif_tx_wake_all_queues(dev);
2629
0da34b6d
BG		 2630 return 0;
2631
2632abort_with_rings:
051d36f3
BG		 2633 while (slice) {
2634 slice--;
2635 napi_disable(&mgp->ss[slice].napi);
2636 }
0dcffac1
BG		 2637 for (i = 0; i < mgp->num_slices; i++)
2638 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2639
df30a740
BG		 2640 myri10ge_free_irq(mgp);
2641
0da34b6d
BG		 2642abort_with_nothing:
2643 mgp->running = MYRI10GE_ETH_STOPPED;
2644 return -ENOMEM;
2645}
2646
2647static int myri10ge_close(struct net_device *dev)
2648{
b53bef84 2649 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2650 struct myri10ge_cmd cmd;
2651 int status, old_down_cnt;
0dcffac1 2652 int i;
0da34b6d 2653
0da34b6d
BG		 2654 if (mgp->running != MYRI10GE_ETH_RUNNING)
2655 return 0;
2656
0dcffac1 2657 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2658 return 0;
2659
2660 del_timer_sync(&mgp->watchdog_timer);
2661 mgp->running = MYRI10GE_ETH_STOPPING;
0dde8026 2662 local_bh_disable(); /* myri10ge_ss_lock_napi needs bh disabled */
0dcffac1
BG		 2663 for (i = 0; i < mgp->num_slices; i++) {
2664 napi_disable(&mgp->ss[i].napi);
0dde8026
HYK		 2665 /* Lock the slice to prevent the busy_poll handler from
2666 * accessing it. Later when we bring the NIC up, myri10ge_open
2667 * resets the slice including this lock.
2668 */
2669 while (!myri10ge_ss_lock_napi(&mgp->ss[i])) {
2670 pr_info("Slice %d locked\n", i);
2671 mdelay(1);
2672 }
0dcffac1 2673 }
0dde8026 2674 local_bh_enable();
0da34b6d 2675 netif_carrier_off(dev);
236bb5e6
BG		 2676
2677 netif_tx_stop_all_queues(dev);
d0234215
BG		 2678 if (mgp->rebooted == 0) {
2679 old_down_cnt = mgp->down_cnt;
2680 mb();
2681 status =
2682 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2683 if (status)
78ca90ea 2684 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2685
d0234215
BG		 2686 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2687 HZ);
2688 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2689 netdev_err(dev, "never got down irq\n");
d0234215 2690 }
0da34b6d 2691 netif_tx_disable(dev);
df30a740 2692 myri10ge_free_irq(mgp);
0dcffac1
BG		 2693 for (i = 0; i < mgp->num_slices; i++)
2694 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2695
2696 mgp->running = MYRI10GE_ETH_STOPPED;
2697 return 0;
2698}
2699
2700/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2701 * backwards one at a time and handle ring wraps */
2702
2703static inline void
2704myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2705 struct mcp_kreq_ether_send *src, int cnt)
2706{
2707 int idx, starting_slot;
2708 starting_slot = tx->req;
2709 while (cnt > 1) {
2710 cnt--;
2711 idx = (starting_slot + cnt) & tx->mask;
2712 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2713 mb();
2714 }
2715}
2716
2717/*
2718 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2719 * at most 32 bytes at a time, so as to avoid involving the software
2720 * pio handler in the nic. We re-write the first segment's flags
2721 * to mark them valid only after writing the entire chain.
2722 */
2723
2724static inline void
2725myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2726 int cnt)
2727{
2728 int idx, i;
2729 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2730 struct mcp_kreq_ether_send *srcp;
2731 u8 last_flags;
2732
2733 idx = tx->req & tx->mask;
2734
2735 last_flags = src->flags;
2736 src->flags = 0;
2737 mb();
2738 dst = dstp = &tx->lanai[idx];
2739 srcp = src;
2740
2741 if ((idx + cnt) < tx->mask) {
2742 for (i = 0; i < (cnt - 1); i += 2) {
2743 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2744 mb(); /* force write every 32 bytes */
2745 srcp += 2;
2746 dstp += 2;
2747 }
2748 } else {
2749 /* submit all but the first request, and ensure
2750 * that it is submitted below */
2751 myri10ge_submit_req_backwards(tx, src, cnt);
2752 i = 0;
2753 }
2754 if (i < cnt) {
2755 /* submit the first request */
2756 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2757 mb(); /* barrier before setting valid flag */
2758 }
2759
2760 /* re-write the last 32-bits with the valid flags */
2761 src->flags = last_flags;
40f6cff5 2762 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2763 tx->req += cnt;
2764 mb();
2765}
2766
0da34b6d
BG		 2767/*
2768 * Transmit a packet. We need to split the packet so that a single
b53bef84 2769 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2770 * counting tricky. So rather than try to count segments up front, we
2771 * just give up if there are too few segments to hold a reasonably
2772 * fragmented packet currently available. If we run
2773 * out of segments while preparing a packet for DMA, we just linearize
2774 * it and try again.
2775 */
2776
61357325
SH		 2777static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2778 struct net_device *dev)
0da34b6d
BG		 2779{
2780 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2781 struct myri10ge_slice_state *ss;
0da34b6d 2782 struct mcp_kreq_ether_send *req;
b53bef84 2783 struct myri10ge_tx_buf *tx;
0da34b6d 2784 struct skb_frag_struct *frag;
236bb5e6 2785 struct netdev_queue *netdev_queue;
0da34b6d 2786 dma_addr_t bus;
40f6cff5
AV		 2787 u32 low;
2788 __be32 high_swapped;
0da34b6d
BG		 2789 unsigned int len;
2790 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2791 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2792 int cum_len, seglen, boundary, rdma_count;
2793 u8 flags, odd_flag;
2794
236bb5e6 2795 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2796 ss = &mgp->ss[queue];
2797 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2798 tx = &ss->tx;
236bb5e6 2799
0da34b6d
BG		 2800again:
2801 req = tx->req_list;
2802 avail = tx->mask - 1 - (tx->req - tx->done);
2803
2804 mss = 0;
2805 max_segments = MXGEFW_MAX_SEND_DESC;
2806
917690cd 2807 if (skb_is_gso(skb)) {
7967168c 2808 mss = skb_shinfo(skb)->gso_size;
917690cd 2809 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2810 }
0da34b6d
BG		 2811
2812 if ((unlikely(avail < max_segments))) {
2813 /* we are out of transmit resources */
b53bef84 2814 tx->stop_queue++;
236bb5e6 2815 netif_tx_stop_queue(netdev_queue);
5b548140 2816 return NETDEV_TX_BUSY;
0da34b6d
BG		 2817 }
2818
2819 /* Setup checksum offloading, if needed */
2820 cksum_offset = 0;
2821 pseudo_hdr_offset = 0;
2822 odd_flag = 0;
2823 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2824 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0d0b1672 2825 cksum_offset = skb_checksum_start_offset(skb);
ff1dcadb 2826 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2827 /* If the headers are excessively large, then we must
2828 * fall back to a software checksum */
4f93fde0
BG		 2829 if (unlikely(!mss && (cksum_offset > 255 ||
2830 pseudo_hdr_offset > 127))) {
84fa7933 2831 if (skb_checksum_help(skb))
0da34b6d
BG		 2832 goto drop;
2833 cksum_offset = 0;
2834 pseudo_hdr_offset = 0;
2835 } else {
0da34b6d
BG		 2836 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2837 flags |= MXGEFW_FLAGS_CKSUM;
2838 }
2839 }
2840
2841 cum_len = 0;
2842
0da34b6d
BG		 2843 if (mss) { /* TSO */
2844 /* this removes any CKSUM flag from before */
2845 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2846
2847 /* negative cum_len signifies to the
2848 * send loop that we are still in the
2849 * header portion of the TSO packet.
4f93fde0 2850 * TSO header can be at most 1KB long */
ab6a5bb6 2851 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2852
4f93fde0
BG		 2853 /* for IPv6 TSO, the checksum offset stores the
2854 * TCP header length, to save the firmware from
2855 * the need to parse the headers */
2856 if (skb_is_gso_v6(skb)) {
2857 cksum_offset = tcp_hdrlen(skb);
2858 /* Can only handle headers <= max_tso6 long */
2859 if (unlikely(-cum_len > mgp->max_tso6))
2860 return myri10ge_sw_tso(skb, dev);
2861 }
0da34b6d
BG		 2862 /* for TSO, pseudo_hdr_offset holds mss.
2863 * The firmware figures out where to put
2864 * the checksum by parsing the header. */
40f6cff5 2865 pseudo_hdr_offset = mss;
0da34b6d 2866 } else
0da34b6d
BG		 2867 /* Mark small packets, and pad out tiny packets */
2868 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2869 flags |= MXGEFW_FLAGS_SMALL;
2870
2871 /* pad frames to at least ETH_ZLEN bytes */
2872 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2873 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2874 /* The packet is gone, so we must
2875 * return 0 */
b53bef84 2876 ss->stats.tx_dropped += 1;
6ed10654 2877 return NETDEV_TX_OK;
0da34b6d
BG		 2878 }
2879 /* adjust the len to account for the zero pad
2880 * so that the nic can know how long it is */
2881 skb->len = ETH_ZLEN;
2882 }
2883 }
2884
2885 /* map the skb for DMA */
e743d313 2886 len = skb_headlen(skb);
0da34b6d
BG		 2887 idx = tx->req & tx->mask;
2888 tx->info[idx].skb = skb;
2889 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2890 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2891 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2892
2893 frag_cnt = skb_shinfo(skb)->nr_frags;
2894 frag_idx = 0;
2895 count = 0;
2896 rdma_count = 0;
2897
2898 /* "rdma_count" is the number of RDMAs belonging to the
2899 * current packet BEFORE the current send request. For
2900 * non-TSO packets, this is equal to "count".
2901 * For TSO packets, rdma_count needs to be reset
2902 * to 0 after a segment cut.
2903 *
2904 * The rdma_count field of the send request is
2905 * the number of RDMAs of the packet starting at
2906 * that request. For TSO send requests with one ore more cuts
2907 * in the middle, this is the number of RDMAs starting
2908 * after the last cut in the request. All previous
2909 * segments before the last cut implicitly have 1 RDMA.
2910 *
2911 * Since the number of RDMAs is not known beforehand,
2912 * it must be filled-in retroactively - after each
2913 * segmentation cut or at the end of the entire packet.
2914 */
2915
2916 while (1) {
2917 /* Break the SKB or Fragment up into pieces which
b53bef84 2918 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2919 low = MYRI10GE_LOWPART_TO_U32(bus);
2920 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2921 while (len) {
2922 u8 flags_next;
2923 int cum_len_next;
2924
2925 if (unlikely(count == max_segments))
2926 goto abort_linearize;
2927
b53bef84
BG		 2928 boundary =
2929 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2930 seglen = boundary - low;
2931 if (seglen > len)
2932 seglen = len;
2933 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2934 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2935 if (mss) { /* TSO */
2936 (req - rdma_count)->rdma_count = rdma_count + 1;
2937
2938 if (likely(cum_len >= 0)) { /* payload */
2939 int next_is_first, chop;
2940
2941 chop = (cum_len_next > mss);
2942 cum_len_next = cum_len_next % mss;
2943 next_is_first = (cum_len_next == 0);
2944 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2945 flags_next |= next_is_first *
2946 MXGEFW_FLAGS_FIRST;
2947 rdma_count |= -(chop | next_is_first);
59e955ed 2948 rdma_count += chop & ~next_is_first;
0da34b6d
BG		 2949 } else if (likely(cum_len_next >= 0)) { /* header ends */
2950 int small;
2951
2952 rdma_count = -1;
2953 cum_len_next = 0;
2954 seglen = -cum_len;
2955 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2956 flags_next = MXGEFW_FLAGS_TSO_PLD |
2957 MXGEFW_FLAGS_FIRST |
2958 (small * MXGEFW_FLAGS_SMALL);
2959 }
2960 }
0da34b6d
BG		 2961 req->addr_high = high_swapped;
2962 req->addr_low = htonl(low);
40f6cff5 2963 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2964 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2965 req->rdma_count = 1;
2966 req->length = htons(seglen);
2967 req->cksum_offset = cksum_offset;
2968 req->flags = flags | ((cum_len & 1) * odd_flag);
2969
2970 low += seglen;
2971 len -= seglen;
2972 cum_len = cum_len_next;
2973 flags = flags_next;
2974 req++;
2975 count++;
2976 rdma_count++;
4f93fde0
BG		 2977 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2978 if (unlikely(cksum_offset > seglen))
2979 cksum_offset -= seglen;
2980 else
2981 cksum_offset = 0;
2982 }
0da34b6d
BG		 2983 }
2984 if (frag_idx == frag_cnt)
2985 break;
2986
2987 /* map next fragment for DMA */
2988 idx = (count + tx->req) & tx->mask;
2989 frag = &skb_shinfo(skb)->frags[frag_idx];
2990 frag_idx++;
9e903e08 2991 len = skb_frag_size(frag);
5dc3e196 2992 bus = skb_frag_dma_map(&mgp->pdev->dev, frag, 0, len,
5d6bcdfe 2993 DMA_TO_DEVICE);
c755b4b6
FT		 2994 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2995 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2996 }
2997
2998 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2999 if (mss)
3000 do {
3001 req--;
3002 req->flags |= MXGEFW_FLAGS_TSO_LAST;
3003 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
3004 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 3005 idx = ((count - 1) + tx->req) & tx->mask;
3006 tx->info[idx].last = 1;
e454e7e2 3007 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 3008 /* if using multiple tx queues, make sure NIC polls the
3009 * current slice */
3010 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
3011 tx->queue_active = 1;
3012 put_be32(htonl(1), tx->send_go);
8c2f5fa5 3013 mb();
6824a105 3014 mmiowb();
236bb5e6 3015 }
0da34b6d
BG		 3016 tx->pkt_start++;
3017 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 3018 tx->stop_queue++;
236bb5e6 3019 netif_tx_stop_queue(netdev_queue);
0da34b6d 3020 }
6ed10654 3021 return NETDEV_TX_OK;
0da34b6d
BG		 3022
3023abort_linearize:
3024 /* Free any DMA resources we've alloced and clear out the skb
3025 * slot so as to not trip up assertions, and to avoid a
3026 * double-free if linearizing fails */
3027
3028 last_idx = (idx + 1) & tx->mask;
3029 idx = tx->req & tx->mask;
3030 tx->info[idx].skb = NULL;
3031 do {
c755b4b6 3032 len = dma_unmap_len(&tx->info[idx], len);
0da34b6d
BG		 3033 if (len) {
3034 if (tx->info[idx].skb != NULL)
3035 pci_unmap_single(mgp->pdev,
c755b4b6 3036 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 3037 bus), len,
3038 PCI_DMA_TODEVICE);
3039 else
3040 pci_unmap_page(mgp->pdev,
c755b4b6 3041 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 3042 bus), len,
3043 PCI_DMA_TODEVICE);
c755b4b6 3044 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d
BG		 3045 tx->info[idx].skb = NULL;
3046 }
3047 idx = (idx + 1) & tx->mask;
3048 } while (idx != last_idx);
89114afd 3049 if (skb_is_gso(skb)) {
78ca90ea 3050 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 3051 goto drop;
3052 }
3053
bec0e859 3054 if (skb_linearize(skb))
0da34b6d
BG		 3055 goto drop;
3056
b53bef84 3057 tx->linearized++;
0da34b6d
BG		 3058 goto again;
3059
3060drop:
3061 dev_kfree_skb_any(skb);
b53bef84 3062 ss->stats.tx_dropped += 1;
6ed10654 3063 return NETDEV_TX_OK;
0da34b6d
BG		 3064
3065}
3066
61357325
SH		 3067static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
3068 struct net_device *dev)
4f93fde0
BG		 3069{
3070 struct sk_buff *segs, *curr;
b53bef84 3071 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 3072 struct myri10ge_slice_state *ss;
61357325 3073 netdev_tx_t status;
4f93fde0
BG		 3074
3075 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 3076 if (IS_ERR(segs))
4f93fde0
BG		 3077 goto drop;
3078
3079 while (segs) {
3080 curr = segs;
3081 segs = segs->next;
3082 curr->next = NULL;
3083 status = myri10ge_xmit(curr, dev);
3084 if (status != 0) {
3085 dev_kfree_skb_any(curr);
3086 if (segs != NULL) {
3087 curr = segs;
3088 segs = segs->next;
3089 curr->next = NULL;
3090 dev_kfree_skb_any(segs);
3091 }
3092 goto drop;
3093 }
3094 }
3095 dev_kfree_skb_any(skb);
ec634fe3 3096 return NETDEV_TX_OK;
4f93fde0
BG		 3097
3098drop:
d6279c88 3099 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 3100 dev_kfree_skb_any(skb);
d6279c88 3101 ss->stats.tx_dropped += 1;
ec634fe3 3102 return NETDEV_TX_OK;
4f93fde0
BG		 3103}
3104
c5f7ef72 3105static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
3106 struct rtnl_link_stats64 *stats)
0da34b6d 3107{
306ff6eb
ED		 3108 const struct myri10ge_priv *mgp = netdev_priv(dev);
3109 const struct myri10ge_slice_netstats *slice_stats;
0dcffac1
BG		 3110 int i;
3111
0dcffac1
BG		 3112 for (i = 0; i < mgp->num_slices; i++) {
3113 slice_stats = &mgp->ss[i].stats;
3114 stats->rx_packets += slice_stats->rx_packets;
3115 stats->tx_packets += slice_stats->tx_packets;
3116 stats->rx_bytes += slice_stats->rx_bytes;
3117 stats->tx_bytes += slice_stats->tx_bytes;
3118 stats->rx_dropped += slice_stats->rx_dropped;
3119 stats->tx_dropped += slice_stats->tx_dropped;
3120 }
3121 return stats;
0da34b6d
BG		 3122}
3123
3124static void myri10ge_set_multicast_list(struct net_device *dev)
3125{
b53bef84 3126 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3127 struct myri10ge_cmd cmd;
22bedad3 3128 struct netdev_hw_addr *ha;
6250223e 3129 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3130 int err;
3131
0da34b6d
BG		 3132 /* can be called from atomic contexts,
3133 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3134 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3135
3136 /* This firmware is known to not support multicast */
2f76216f 3137 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3138 return;
3139
3140 /* Disable multicast filtering */
3141
3142 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3143 if (err != 0) {
78ca90ea
JP		 3144 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3145 err);
85a7ea1b
BG		 3146 goto abort;
3147 }
3148
2f76216f 3149 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3150 /* request to disable multicast filtering, so quit here */
3151 return;
3152 }
3153
3154 /* Flush the filters */
3155
3156 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3157 &cmd, 1);
3158 if (err != 0) {
78ca90ea
JP		 3159 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3160 err);
85a7ea1b
BG		 3161 goto abort;
3162 }
3163
3164 /* Walk the multicast list, and add each address */
22bedad3 3165 netdev_for_each_mc_addr(ha, dev) {
d458cdf7 3166 memcpy(data, &ha->addr, ETH_ALEN);
40f6cff5
AV		 3167 cmd.data0 = ntohl(data[0]);
3168 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3169 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3170 &cmd, 1);
3171
3172 if (err != 0) {
78ca90ea 3173 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 3174 err, ha->addr);
85a7ea1b
BG		 3175 goto abort;
3176 }
3177 }
3178 /* Enable multicast filtering */
3179 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3180 if (err != 0) {
78ca90ea
JP		 3181 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3182 err);
85a7ea1b
BG		 3183 goto abort;
3184 }
3185
3186 return;
3187
3188abort:
3189 return;
0da34b6d
BG		 3190}
3191
3192static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3193{
3194 struct sockaddr *sa = addr;
3195 struct myri10ge_priv *mgp = netdev_priv(dev);
3196 int status;
3197
3198 if (!is_valid_ether_addr(sa->sa_data))
3199 return -EADDRNOTAVAIL;
3200
3201 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3202 if (status != 0) {
78ca90ea
JP		 3203 netdev_err(dev, "changing mac address failed with %d\n",
3204 status);
0da34b6d
BG		 3205 return status;
3206 }
3207
3208 /* change the dev structure */
d458cdf7 3209 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
0da34b6d
BG		 3210 return 0;
3211}
3212
3213static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3214{
3215 struct myri10ge_priv *mgp = netdev_priv(dev);
3216 int error = 0;
3217
3218 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
78ca90ea 3219 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
0da34b6d
BG		 3220 return -EINVAL;
3221 }
78ca90ea 3222 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 3223 if (mgp->running) {
3224 /* if we change the mtu on an active device, we must
3225 * reset the device so the firmware sees the change */
3226 myri10ge_close(dev);
3227 dev->mtu = new_mtu;
3228 myri10ge_open(dev);
3229 } else
3230 dev->mtu = new_mtu;
3231
3232 return error;
3233}
3234
3235/*
3236 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3237 * Only do it if the bridge is a root port since we don't want to disturb
3238 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3239 */
3240
0da34b6d
BG		 3241static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3242{
3243 struct pci_dev *bridge = mgp->pdev->bus->self;
3244 struct device *dev = &mgp->pdev->dev;
effd1eda 3245 int cap;
0da34b6d 3246 unsigned err_cap;
0da34b6d
BG		 3247 int ret;
3248
3249 if (!myri10ge_ecrc_enable || !bridge)
3250 return;
3251
3252 /* check that the bridge is a root port */
9503e255 3253 if (pci_pcie_type(bridge) != PCI_EXP_TYPE_ROOT_PORT) {
0da34b6d 3254 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3255 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3256
3257 /* Walk the hierarchy up to the root port
3258 * where ECRC has to be enabled */
3259 do {
eca3fd83 3260 prev_bridge = bridge;
0da34b6d 3261 bridge = bridge->bus->self;
eca3fd83 3262 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3263 dev_err(dev,
3264 "Failed to find root port"
3265 " to force ECRC\n");
3266 return;
3267 }
9503e255
JL		 3268 } while (pci_pcie_type(bridge) !=
3269 PCI_EXP_TYPE_ROOT_PORT);
0da34b6d
BG		 3270
3271 dev_info(dev,
3272 "Forcing ECRC on non-root port %s"
3273 " (enabling on root port %s)\n",
3274 pci_name(old_bridge), pci_name(bridge));
3275 } else {
3276 dev_err(dev,
3277 "Not enabling ECRC on non-root port %s\n",
3278 pci_name(bridge));
3279 return;
3280 }
3281 }
3282
3283 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3284 if (!cap)
3285 return;
3286
3287 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3288 if (ret) {
3289 dev_err(dev, "failed reading ext-conf-space of %s\n",
3290 pci_name(bridge));
3291 dev_err(dev, "\t pci=nommconf in use? "
3292 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3293 return;
3294 }
3295 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3296 return;
3297
3298 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3299 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3300 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3301}
3302
3303/*
3304 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3305 * when the PCI-E Completion packets are aligned on an 8-byte
3306 * boundary. Some PCI-E chip sets always align Completion packets; on
3307 * the ones that do not, the alignment can be enforced by enabling
3308 * ECRC generation (if supported).
3309 *
3310 * When PCI-E Completion packets are not aligned, it is actually more
3311 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3312 *
3313 * If the driver can neither enable ECRC nor verify that it has
3314 * already been enabled, then it must use a firmware image which works
0dcffac1 3315 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3316 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3317 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3318 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3319 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3320 */
3321
5443e9ea 3322static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3323{
5443e9ea
BG		 3324 struct pci_dev *pdev = mgp->pdev;
3325 struct device *dev = &pdev->dev;
302d242c 3326 int status;
0da34b6d 3327
b53bef84 3328 mgp->tx_boundary = 4096;
5443e9ea
BG		 3329 /*
3330 * Verify the max read request size was set to 4KB
3331 * before trying the test with 4KB.
3332 */
302d242c
BG		 3333 status = pcie_get_readrq(pdev);
3334 if (status < 0) {
5443e9ea
BG		 3335 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3336 goto abort;
3337 }
302d242c
BG		 3338 if (status != 4096) {
3339 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3340 mgp->tx_boundary = 2048;
5443e9ea
BG		 3341 }
3342 /*
3343 * load the optimized firmware (which assumes aligned PCIe
3344 * completions) in order to see if it works on this host.
3345 */
7d351035 3346 set_fw_name(mgp, myri10ge_fw_aligned, false);
0dcffac1 3347 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3348 if (status != 0) {
3349 goto abort;
3350 }
3351
3352 /*
3353 * Enable ECRC if possible
3354 */
3355 myri10ge_enable_ecrc(mgp);
3356
3357 /*
3358 * Run a DMA test which watches for unaligned completions and
3359 * aborts on the first one seen.
3360 */
3361
3362 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3363 if (status == 0)
3364 return; /* keep the aligned firmware */
3365
3366 if (status != -E2BIG)
3367 dev_warn(dev, "DMA test failed: %d\n", status);
3368 if (status == -ENOSYS)
3369 dev_warn(dev, "Falling back to ethp! "
3370 "Please install up to date fw\n");
3371abort:
3372 /* fall back to using the unaligned firmware */
b53bef84 3373 mgp->tx_boundary = 2048;
7d351035 3374 set_fw_name(mgp, myri10ge_fw_unaligned, false);
5443e9ea
BG		 3375}
3376
3377static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3378{
2d90b0aa
BG		 3379 int overridden = 0;
3380
0da34b6d 3381 if (myri10ge_force_firmware == 0) {
9503e255 3382 int link_width;
ce7f9368
BG		 3383 u16 lnk;
3384
9503e255 3385 pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
ce7f9368
BG		 3386 link_width = (lnk >> 4) & 0x3f;
3387
ce7f9368
BG		 3388 /* Check to see if Link is less than 8 or if the
3389 * upstream bridge is known to provide aligned
3390 * completions */
3391 if (link_width < 8) {
3392 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3393 link_width);
b53bef84 3394 mgp->tx_boundary = 4096;
7d351035 3395 set_fw_name(mgp, myri10ge_fw_aligned, false);
5443e9ea
BG		 3396 } else {
3397 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3398 }
3399 } else {
3400 if (myri10ge_force_firmware == 1) {
3401 dev_info(&mgp->pdev->dev,
3402 "Assuming aligned completions (forced)\n");
b53bef84 3403 mgp->tx_boundary = 4096;
7d351035 3404 set_fw_name(mgp, myri10ge_fw_aligned, false);
0da34b6d
BG		 3405 } else {
3406 dev_info(&mgp->pdev->dev,
3407 "Assuming unaligned completions (forced)\n");
b53bef84 3408 mgp->tx_boundary = 2048;
7d351035 3409 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d
BG		 3410 }
3411 }
7d351035
RR		 3412
3413 kparam_block_sysfs_write(myri10ge_fw_name);
0da34b6d 3414 if (myri10ge_fw_name != NULL) {
7d351035
RR		 3415 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3416 if (fw_name) {
3417 overridden = 1;
3418 set_fw_name(mgp, fw_name, true);
3419 }
0da34b6d 3420 }
7d351035
RR		 3421 kparam_unblock_sysfs_write(myri10ge_fw_name);
3422
2d90b0aa
BG		 3423 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3424 myri10ge_fw_names[mgp->board_number] != NULL &&
3425 strlen(myri10ge_fw_names[mgp->board_number])) {
7d351035 3426 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
2d90b0aa
BG		 3427 overridden = 1;
3428 }
3429 if (overridden)
3430 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3431 mgp->fw_name);
0da34b6d
BG		 3432}
3433
7539a613
JM		 3434static void myri10ge_mask_surprise_down(struct pci_dev *pdev)
3435{
3436 struct pci_dev *bridge = pdev->bus->self;
3437 int cap;
3438 u32 mask;
3439
3440 if (bridge == NULL)
3441 return;
3442
3443 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3444 if (cap) {
3445 /* a sram parity error can cause a surprise link
3446 * down; since we expect and can recover from sram
3447 * parity errors, mask surprise link down events */
3448 pci_read_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, &mask);
3449 mask |= 0x20;
3450 pci_write_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, mask);
3451 }
3452}
3453
0da34b6d 3454#ifdef CONFIG_PM
0da34b6d
BG		 3455static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3456{
3457 struct myri10ge_priv *mgp;
3458 struct net_device *netdev;
3459
3460 mgp = pci_get_drvdata(pdev);
3461 if (mgp == NULL)
3462 return -EINVAL;
3463 netdev = mgp->dev;
3464
3465 netif_device_detach(netdev);
3466 if (netif_running(netdev)) {
78ca90ea 3467 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3468 rtnl_lock();
3469 myri10ge_close(netdev);
3470 rtnl_unlock();
3471 }
3472 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3473 pci_save_state(pdev);
0da34b6d 3474 pci_disable_device(pdev);
1a63e846
BG		 3475
3476 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3477}
3478
3479static int myri10ge_resume(struct pci_dev *pdev)
3480{
3481 struct myri10ge_priv *mgp;
3482 struct net_device *netdev;
3483 int status;
3484 u16 vendor;
3485
3486 mgp = pci_get_drvdata(pdev);
3487 if (mgp == NULL)
3488 return -EINVAL;
3489 netdev = mgp->dev;
1ca01512 3490 pci_set_power_state(pdev, PCI_D0); /* zeros conf space as a side effect */
0da34b6d
BG		 3491 msleep(5); /* give card time to respond */
3492 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3493 if (vendor == 0xffff) {
78ca90ea 3494 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3495 return -EIO;
3496 }
83f6e152 3497
1d3c16a8 3498 pci_restore_state(pdev);
4c2248cc
BG		 3499
3500 status = pci_enable_device(pdev);
1a63e846 3501 if (status) {
4c2248cc 3502 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3503 return status;
4c2248cc
BG		 3504 }
3505
0da34b6d
BG		 3506 pci_set_master(pdev);
3507
0da34b6d 3508 myri10ge_reset(mgp);
013b68bf 3509 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3510
3511 /* Save configuration space to be restored if the
3512 * nic resets due to a parity error */
83f6e152 3513 pci_save_state(pdev);
0da34b6d
BG		 3514
3515 if (netif_running(netdev)) {
3516 rtnl_lock();
df30a740 3517 status = myri10ge_open(netdev);
0da34b6d 3518 rtnl_unlock();
df30a740
BG		 3519 if (status != 0)
3520 goto abort_with_enabled;
3521
0da34b6d
BG		 3522 }
3523 netif_device_attach(netdev);
3524
3525 return 0;
3526
4c2248cc
BG		 3527abort_with_enabled:
3528 pci_disable_device(pdev);
0da34b6d
BG		 3529 return -EIO;
3530
3531}
0da34b6d
BG		 3532#endif /* CONFIG_PM */
3533
3534static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3535{
3536 struct pci_dev *pdev = mgp->pdev;
3537 int vs = mgp->vendor_specific_offset;
3538 u32 reboot;
3539
3540 /*enter read32 mode */
3541 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3542
3543 /*read REBOOT_STATUS (0xfffffff0) */
3544 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3545 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3546 return reboot;
3547}
3548
c689b81b
JM		 3549static void
3550myri10ge_check_slice(struct myri10ge_slice_state *ss, int *reset_needed,
3551 int *busy_slice_cnt, u32 rx_pause_cnt)
3552{
3553 struct myri10ge_priv *mgp = ss->mgp;
3554 int slice = ss - mgp->ss;
3555
3556 if (ss->tx.req != ss->tx.done &&
3557 ss->tx.done == ss->watchdog_tx_done &&
3558 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3559 /* nic seems like it might be stuck.. */
3560 if (rx_pause_cnt != mgp->watchdog_pause) {
3561 if (net_ratelimit())
3562 netdev_warn(mgp->dev, "slice %d: TX paused, "
3563 "check link partner\n", slice);
3564 } else {
3565 netdev_warn(mgp->dev,
3566 "slice %d: TX stuck %d %d %d %d %d %d\n",
3567 slice, ss->tx.queue_active, ss->tx.req,
3568 ss->tx.done, ss->tx.pkt_start,
3569 ss->tx.pkt_done,
3570 (int)ntohl(mgp->ss[slice].fw_stats->
3571 send_done_count));
3572 *reset_needed = 1;
3573 ss->stuck = 1;
3574 }
3575 }
3576 if (ss->watchdog_tx_done != ss->tx.done ||
3577 ss->watchdog_rx_done != ss->rx_done.cnt) {
3578 *busy_slice_cnt += 1;
3579 }
3580 ss->watchdog_tx_done = ss->tx.done;
3581 ss->watchdog_tx_req = ss->tx.req;
3582 ss->watchdog_rx_done = ss->rx_done.cnt;
3583}
3584
0da34b6d
BG		 3585/*
3586 * This watchdog is used to check whether the board has suffered
3587 * from a parity error and needs to be recovered.
3588 */
c4028958 3589static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3590{
c4028958 3591 struct myri10ge_priv *mgp =
6250223e 3592 container_of(work, struct myri10ge_priv, watchdog_work);
c689b81b
JM		 3593 struct myri10ge_slice_state *ss;
3594 u32 reboot, rx_pause_cnt;
d0234215 3595 int status, rebooted;
0dcffac1 3596 int i;
c689b81b
JM		 3597 int reset_needed = 0;
3598 int busy_slice_cnt = 0;
0da34b6d
BG		 3599 u16 cmd, vendor;
3600
3601 mgp->watchdog_resets++;
3602 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3603 rebooted = 0;
0da34b6d
BG		 3604 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3605 /* Bus master DMA disabled? Check to see
3606 * if the card rebooted due to a parity error
3607 * For now, just report it */
3608 reboot = myri10ge_read_reboot(mgp);
78ca90ea 3609 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
c689b81b 3610 reboot, myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3611 if (myri10ge_reset_recover == 0)
3612 return;
d0234215
BG		 3613 rtnl_lock();
3614 mgp->rebooted = 1;
3615 rebooted = 1;
3616 myri10ge_close(mgp->dev);
f181137f 3617 myri10ge_reset_recover--;
d0234215 3618 mgp->rebooted = 0;
0da34b6d
BG		 3619 /*
3620 * A rebooted nic will come back with config space as
3621 * it was after power was applied to PCIe bus.
3622 * Attempt to restore config space which was saved
3623 * when the driver was loaded, or the last time the
3624 * nic was resumed from power saving mode.
3625 */
83f6e152 3626 pci_restore_state(mgp->pdev);
7adda30c
BG		 3627
3628 /* save state again for accounting reasons */
83f6e152 3629 pci_save_state(mgp->pdev);
7adda30c 3630
0da34b6d
BG		 3631 } else {
3632 /* if we get back -1's from our slot, perhaps somebody
3633 * powered off our card. Don't try to reset it in
3634 * this case */
3635 if (cmd == 0xffff) {
3636 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3637 if (vendor == 0xffff) {
78ca90ea 3638 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3639 return;
3640 }
3641 }
c689b81b
JM		 3642 /* Perhaps it is a software error. See if stuck slice
3643 * has recovered, reset if not */
3644 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
0dcffac1 3645 for (i = 0; i < mgp->num_slices; i++) {
c689b81b
JM		 3646 ss = mgp->ss;
3647 if (ss->stuck) {
3648 myri10ge_check_slice(ss, &reset_needed,
3649 &busy_slice_cnt,
3650 rx_pause_cnt);
3651 ss->stuck = 0;
3652 }
0dcffac1 3653 }
c689b81b
JM		 3654 if (!reset_needed) {
3655 netdev_dbg(mgp->dev, "not resetting\n");
3656 return;
3657 }
3658
3659 netdev_err(mgp->dev, "device timeout, resetting\n");
0da34b6d 3660 }
236bb5e6 3661
d0234215
BG		 3662 if (!rebooted) {
3663 rtnl_lock();
3664 myri10ge_close(mgp->dev);
3665 }
0dcffac1 3666 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3667 if (status != 0)
78ca90ea 3668 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3669 else
3670 myri10ge_open(mgp->dev);
3671 rtnl_unlock();
3672}
3673
3674/*
3675 * We use our own timer routine rather than relying upon
3676 * netdev->tx_timeout because we have a very large hardware transmit
3677 * queue. Due to the large queue, the netdev->tx_timeout function
3678 * cannot detect a NIC with a parity error in a timely fashion if the
3679 * NIC is lightly loaded.
3680 */
3681static void myri10ge_watchdog_timer(unsigned long arg)
3682{
3683 struct myri10ge_priv *mgp;
b53bef84 3684 struct myri10ge_slice_state *ss;
d0234215 3685 int i, reset_needed, busy_slice_cnt;
626fda94 3686 u32 rx_pause_cnt;
d0234215 3687 u16 cmd;
0da34b6d
BG		 3688
3689 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3690
0dcffac1 3691 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3692 busy_slice_cnt = 0;
0dcffac1
BG		 3693 for (i = 0, reset_needed = 0;
3694 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3695
0dcffac1
BG		 3696 ss = &mgp->ss[i];
3697 if (ss->rx_small.watchdog_needed) {
3698 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3699 mgp->small_bytes + MXGEFW_PAD,
3700 1);
3701 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3702 myri10ge_fill_thresh)
3703 ss->rx_small.watchdog_needed = 0;
3704 }
3705 if (ss->rx_big.watchdog_needed) {
3706 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3707 mgp->big_bytes, 1);
3708 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3709 myri10ge_fill_thresh)
3710 ss->rx_big.watchdog_needed = 0;
3711 }
c689b81b
JM		 3712 myri10ge_check_slice(ss, &reset_needed, &busy_slice_cnt,
3713 rx_pause_cnt);
d0234215
BG		 3714 }
3715 /* if we've sent or received no traffic, poll the NIC to
3716 * ensure it is still there. Otherwise, we risk not noticing
3717 * an error in a timely fashion */
3718 if (busy_slice_cnt == 0) {
3719 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3720 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3721 reset_needed = 1;
3722 }
626fda94 3723 }
626fda94 3724 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3725
3726 if (reset_needed) {
3727 schedule_work(&mgp->watchdog_work);
3728 } else {
3729 /* rearm timer */
3730 mod_timer(&mgp->watchdog_timer,
3731 jiffies + myri10ge_watchdog_timeout * HZ);
3732 }
0da34b6d
BG		 3733}
3734
77929732
BG		 3735static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3736{
3737 struct myri10ge_slice_state *ss;
3738 struct pci_dev *pdev = mgp->pdev;
3739 size_t bytes;
3740 int i;
3741
3742 if (mgp->ss == NULL)
3743 return;
3744
3745 for (i = 0; i < mgp->num_slices; i++) {
3746 ss = &mgp->ss[i];
3747 if (ss->rx_done.entry != NULL) {
3748 bytes = mgp->max_intr_slots *
3749 sizeof(*ss->rx_done.entry);
3750 dma_free_coherent(&pdev->dev, bytes,
3751 ss->rx_done.entry, ss->rx_done.bus);
3752 ss->rx_done.entry = NULL;
3753 }
3754 if (ss->fw_stats != NULL) {
3755 bytes = sizeof(*ss->fw_stats);
3756 dma_free_coherent(&pdev->dev, bytes,
3757 ss->fw_stats, ss->fw_stats_bus);
3758 ss->fw_stats = NULL;
3759 }
0dde8026 3760 napi_hash_del(&ss->napi);
b3b6ae2c 3761 netif_napi_del(&ss->napi);
77929732 3762 }
0dde8026
HYK		 3763 /* Wait till napi structs are no longer used, and then free ss. */
3764 synchronize_rcu();
77929732
BG		 3765 kfree(mgp->ss);
3766 mgp->ss = NULL;
3767}
3768
3769static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3770{
3771 struct myri10ge_slice_state *ss;
3772 struct pci_dev *pdev = mgp->pdev;
3773 size_t bytes;
3774 int i;
3775
3776 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3777 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3778 if (mgp->ss == NULL) {
3779 return -ENOMEM;
3780 }
3781
3782 for (i = 0; i < mgp->num_slices; i++) {
3783 ss = &mgp->ss[i];
3784 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
ede23fa8
JP		 3785 ss->rx_done.entry = dma_zalloc_coherent(&pdev->dev, bytes,
3786 &ss->rx_done.bus,
3787 GFP_KERNEL);
77929732
BG		 3788 if (ss->rx_done.entry == NULL)
3789 goto abort;
77929732
BG		 3790 bytes = sizeof(*ss->fw_stats);
3791 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3792 &ss->fw_stats_bus,
3793 GFP_KERNEL);
3794 if (ss->fw_stats == NULL)
3795 goto abort;
3796 ss->mgp = mgp;
3797 ss->dev = mgp->dev;
3798 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3799 myri10ge_napi_weight);
0dde8026 3800 napi_hash_add(&ss->napi);
77929732
BG		 3801 }
3802 return 0;
3803abort:
3804 myri10ge_free_slices(mgp);
3805 return -ENOMEM;
3806}
3807
3808/*
3809 * This function determines the number of slices supported.
25985edc 3810 * The number slices is the minimum of the number of CPUS,
77929732
BG		 3811 * the number of MSI-X irqs supported, the number of slices
3812 * supported by the firmware
3813 */
3814static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3815{
3816 struct myri10ge_cmd cmd;
3817 struct pci_dev *pdev = mgp->pdev;
3818 char *old_fw;
7d351035 3819 bool old_allocated;
40b29562 3820 int i, status, ncpus;
77929732
BG		 3821
3822 mgp->num_slices = 1;
98f2d21f 3823 ncpus = netif_get_num_default_rss_queues();
77929732 3824
40b29562 3825 if (myri10ge_max_slices == 1 || !pdev->msix_cap ||
77929732
BG		 3826 (myri10ge_max_slices == -1 && ncpus < 2))
3827 return;
3828
3829 /* try to load the slice aware rss firmware */
3830 old_fw = mgp->fw_name;
7d351035
RR		 3831 old_allocated = mgp->fw_name_allocated;
3832 /* don't free old_fw if we override it. */
3833 mgp->fw_name_allocated = false;
3834
13b2738c
BG		 3835 if (myri10ge_fw_name != NULL) {
3836 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3837 myri10ge_fw_name);
7d351035 3838 set_fw_name(mgp, myri10ge_fw_name, false);
13b2738c 3839 } else if (old_fw == myri10ge_fw_aligned)
7d351035 3840 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
77929732 3841 else
7d351035 3842 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
77929732
BG		 3843 status = myri10ge_load_firmware(mgp, 0);
3844 if (status != 0) {
3845 dev_info(&pdev->dev, "Rss firmware not found\n");
7d351035
RR		 3846 if (old_allocated)
3847 kfree(old_fw);
77929732
BG		 3848 return;
3849 }
3850
3851 /* hit the board with a reset to ensure it is alive */
3852 memset(&cmd, 0, sizeof(cmd));
3853 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3854 if (status != 0) {
3855 dev_err(&mgp->pdev->dev, "failed reset\n");
3856 goto abort_with_fw;
77929732
BG		 3857 }
3858
3859 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3860
3861 /* tell it the size of the interrupt queues */
3862 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3863 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3864 if (status != 0) {
3865 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3866 goto abort_with_fw;
3867 }
3868
3869 /* ask the maximum number of slices it supports */
3870 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3871 if (status != 0)
3872 goto abort_with_fw;
3873 else
3874 mgp->num_slices = cmd.data0;
3875
3876 /* Only allow multiple slices if MSI-X is usable */
3877 if (!myri10ge_msi) {
3878 goto abort_with_fw;
3879 }
3880
3881 /* if the admin did not specify a limit to how many
3882 * slices we should use, cap it automatically to the
3883 * number of CPUs currently online */
3884 if (myri10ge_max_slices == -1)
3885 myri10ge_max_slices = ncpus;
3886
3887 if (mgp->num_slices > myri10ge_max_slices)
3888 mgp->num_slices = myri10ge_max_slices;
3889
3890 /* Now try to allocate as many MSI-X vectors as we have
3891 * slices. We give up on MSI-X if we can only get a single
3892 * vector. */
3893
baeb2ffa
JP		 3894 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3895 GFP_KERNEL);
77929732 3896 if (mgp->msix_vectors == NULL)
0729cc0c 3897 goto no_msix;
77929732
BG		 3898 for (i = 0; i < mgp->num_slices; i++) {
3899 mgp->msix_vectors[i].entry = i;
3900 }
3901
3902 while (mgp->num_slices > 1) {
0729cc0c 3903 mgp->num_slices = rounddown_pow_of_two(mgp->num_slices);
77929732 3904 if (mgp->num_slices == 1)
0729cc0c
AG		 3905 goto no_msix;
3906 status = pci_enable_msix_range(pdev,
3907 mgp->msix_vectors,
3908 mgp->num_slices,
3909 mgp->num_slices);
3910 if (status < 0)
3911 goto no_msix;
3912
3913 pci_disable_msix(pdev);
3914
3915 if (status == mgp->num_slices) {
7d351035
RR		 3916 if (old_allocated)
3917 kfree(old_fw);
77929732 3918 return;
0729cc0c 3919 } else {
77929732 3920 mgp->num_slices = status;
0729cc0c 3921 }
77929732
BG		 3922 }
3923
0729cc0c 3924no_msix:
77929732
BG		 3925 if (mgp->msix_vectors != NULL) {
3926 kfree(mgp->msix_vectors);
3927 mgp->msix_vectors = NULL;
3928 }
3929
3930abort_with_fw:
3931 mgp->num_slices = 1;
7d351035 3932 set_fw_name(mgp, old_fw, old_allocated);
77929732
BG		 3933 myri10ge_load_firmware(mgp, 0);
3934}
77929732 3935
8126089f
SH		 3936static const struct net_device_ops myri10ge_netdev_ops = {
3937 .ndo_open = myri10ge_open,
3938 .ndo_stop = myri10ge_close,
3939 .ndo_start_xmit = myri10ge_xmit,
c5f7ef72 3940 .ndo_get_stats64 = myri10ge_get_stats,
8126089f
SH		 3941 .ndo_validate_addr = eth_validate_addr,
3942 .ndo_change_mtu = myri10ge_change_mtu,
afc4b13d 3943 .ndo_set_rx_mode = myri10ge_set_multicast_list,
8126089f 3944 .ndo_set_mac_address = myri10ge_set_mac_address,
0dde8026
HYK		 3945#ifdef CONFIG_NET_RX_BUSY_POLL
3946 .ndo_busy_poll = myri10ge_busy_poll,
3947#endif
8126089f
SH		 3948};
3949
0da34b6d
BG		 3950static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3951{
3952 struct net_device *netdev;
3953 struct myri10ge_priv *mgp;
3954 struct device *dev = &pdev->dev;
0da34b6d
BG		 3955 int i;
3956 int status = -ENXIO;
0da34b6d 3957 int dac_enabled;
00b5e505 3958 unsigned hdr_offset, ss_offset;
2d90b0aa 3959 static int board_number;
0da34b6d 3960
236bb5e6 3961 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
41de8d4c 3962 if (netdev == NULL)
0da34b6d 3963 return -ENOMEM;
0da34b6d 3964
b245fb67
MH		 3965 SET_NETDEV_DEV(netdev, &pdev->dev);
3966
0da34b6d 3967 mgp = netdev_priv(netdev);
0da34b6d
BG		 3968 mgp->dev = netdev;
3969 mgp->pdev = pdev;
0da34b6d
BG		 3970 mgp->pause = myri10ge_flow_control;
3971 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3972 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3973 mgp->board_number = board_number;
0da34b6d
BG		 3974 init_waitqueue_head(&mgp->down_wq);
3975
3976 if (pci_enable_device(pdev)) {
3977 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3978 status = -ENODEV;
3979 goto abort_with_netdev;
3980 }
0da34b6d
BG		 3981
3982 /* Find the vendor-specific cap so we can check
3983 * the reboot register later on */
3984 mgp->vendor_specific_offset
3985 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3986
3987 /* Set our max read request to 4KB */
302d242c 3988 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3989 if (status != 0) {
3990 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3991 status);
e3fd5534 3992 goto abort_with_enabled;
0da34b6d
BG		 3993 }
3994
7539a613 3995 myri10ge_mask_surprise_down(pdev);
0da34b6d
BG		 3996 pci_set_master(pdev);
3997 dac_enabled = 1;
6a35528a 3998 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3999 if (status != 0) {
4000 dac_enabled = 0;
4001 dev_err(&pdev->dev,
898eb71c
JP		 4002 "64-bit pci address mask was refused, "
4003 "trying 32-bit\n");
284901a9 4004 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 4005 }
4006 if (status != 0) {
4007 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 4008 goto abort_with_enabled;
0da34b6d 4009 }
6a35528a 4010 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 4011 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
4012 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 4013 if (mgp->cmd == NULL)
e3fd5534 4014 goto abort_with_enabled;
0da34b6d 4015
0da34b6d
BG		 4016 mgp->board_span = pci_resource_len(pdev, 0);
4017 mgp->iomem_base = pci_resource_start(pdev, 0);
4018 mgp->mtrr = -1;
276e26c3 4019 mgp->wc_enabled = 0;
0da34b6d
BG		 4020#ifdef CONFIG_MTRR
4021 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
4022 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 4023 if (mgp->mtrr >= 0)
4024 mgp->wc_enabled = 1;
0da34b6d 4025#endif
c7f80993 4026 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 4027 if (mgp->sram == NULL) {
4028 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
4029 mgp->board_span, mgp->iomem_base);
4030 status = -ENXIO;
c7f80993 4031 goto abort_with_mtrr;
0da34b6d 4032 }
00b5e505 4033 hdr_offset =
59e955ed 4034 swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
00b5e505 4035 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
59e955ed 4036 mgp->sram_size = swab32(readl(mgp->sram + ss_offset));
00b5e505
BG		 4037 if (mgp->sram_size > mgp->board_span ||
4038 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
4039 dev_err(&pdev->dev,
4040 "invalid sram_size %dB or board span %ldB\n",
4041 mgp->sram_size, mgp->board_span);
4042 goto abort_with_ioremap;
4043 }
0da34b6d 4044 memcpy_fromio(mgp->eeprom_strings,
00b5e505 4045 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 4046 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
4047 status = myri10ge_read_mac_addr(mgp);
4048 if (status)
4049 goto abort_with_ioremap;
4050
4051 for (i = 0; i < ETH_ALEN; i++)
4052 netdev->dev_addr[i] = mgp->mac_addr[i];
4053
5443e9ea
BG		 4054 myri10ge_select_firmware(mgp);
4055
0dcffac1 4056 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 4057 if (status != 0) {
4058 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 4059 goto abort_with_ioremap;
4060 }
4061 myri10ge_probe_slices(mgp);
4062 status = myri10ge_alloc_slices(mgp);
4063 if (status != 0) {
4064 dev_err(&pdev->dev, "failed to alloc slice state\n");
4065 goto abort_with_firmware;
0da34b6d 4066 }
c9920268
BH		 4067 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
4068 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
0da34b6d
BG		 4069 status = myri10ge_reset(mgp);
4070 if (status != 0) {
4071 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 4072 goto abort_with_slices;
0da34b6d 4073 }
5dd2d332 4074#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4075 myri10ge_setup_dca(mgp);
4076#endif
0da34b6d
BG		 4077 pci_set_drvdata(pdev, mgp);
4078 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
4079 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
4080 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
4081 myri10ge_initial_mtu = 68;
8126089f
SH		 4082
4083 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 4084 netdev->mtu = myri10ge_initial_mtu;
4ca3221f 4085 netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
1b4c44e6 4086
f646968f
PM		 4087 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
4088 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1b4c44e6 4089
47c2cdf5 4090 netdev->features = netdev->hw_features;
236bb5e6 4091
0da34b6d
BG		 4092 if (dac_enabled)
4093 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 4094
dddc045e
BG		 4095 netdev->vlan_features |= mgp->features;
4096 if (mgp->fw_ver_tiny < 37)
4097 netdev->vlan_features &= ~NETIF_F_TSO6;
4098 if (mgp->fw_ver_tiny < 32)
4099 netdev->vlan_features &= ~NETIF_F_TSO;
4100
21d05db1 4101 /* make sure we can get an irq, and that MSI can be
a7425458 4102 * setup (if available). */
21d05db1
BG		 4103 status = myri10ge_request_irq(mgp);
4104 if (status != 0)
4105 goto abort_with_firmware;
21d05db1
BG		 4106 myri10ge_free_irq(mgp);
4107
0da34b6d
BG		 4108 /* Save configuration space to be restored if the
4109 * nic resets due to a parity error */
83f6e152 4110 pci_save_state(pdev);
0da34b6d
BG		 4111
4112 /* Setup the watchdog timer */
4113 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
4114 (unsigned long)mgp);
4115
7ad24ea4 4116 netdev->ethtool_ops = &myri10ge_ethtool_ops;
c4028958 4117 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 4118 status = register_netdev(netdev);
4119 if (status != 0) {
4120 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 4121 goto abort_with_state;
0da34b6d 4122 }
0dcffac1
BG		 4123 if (mgp->msix_enabled)
4124 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
4125 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
4126 (mgp->wc_enabled ? "Enabled" : "Disabled"));
4127 else
4128 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
4129 mgp->msi_enabled ? "MSI" : "xPIC",
a7425458 4130 pdev->irq, mgp->tx_boundary, mgp->fw_name,
0dcffac1 4131 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 4132
2d90b0aa 4133 board_number++;
0da34b6d
BG		 4134 return 0;
4135
7adda30c 4136abort_with_state:
83f6e152 4137 pci_restore_state(pdev);
0da34b6d 4138
0dcffac1
BG		 4139abort_with_slices:
4140 myri10ge_free_slices(mgp);
4141
0da34b6d
BG		 4142abort_with_firmware:
4143 myri10ge_dummy_rdma(mgp, 0);
4144
0da34b6d 4145abort_with_ioremap:
0f840011
BG		 4146 if (mgp->mac_addr_string != NULL)
4147 dev_err(&pdev->dev,
4148 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4149 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 4150 iounmap(mgp->sram);
4151
c7f80993 4152abort_with_mtrr:
0da34b6d
BG		 4153#ifdef CONFIG_MTRR
4154 if (mgp->mtrr >= 0)
4155 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4156#endif
b10c0668
BG		 4157 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4158 mgp->cmd, mgp->cmd_bus);
0da34b6d 4159
e3fd5534
BG		 4160abort_with_enabled:
4161 pci_disable_device(pdev);
0da34b6d 4162
e3fd5534 4163abort_with_netdev:
7d351035 4164 set_fw_name(mgp, NULL, false);
0da34b6d
BG		 4165 free_netdev(netdev);
4166 return status;
4167}
4168
4169/*
4170 * myri10ge_remove
4171 *
4172 * Does what is necessary to shutdown one Myrinet device. Called
4173 * once for each Myrinet card by the kernel when a module is
4174 * unloaded.
4175 */
4176static void myri10ge_remove(struct pci_dev *pdev)
4177{
4178 struct myri10ge_priv *mgp;
4179 struct net_device *netdev;
0da34b6d
BG		 4180
4181 mgp = pci_get_drvdata(pdev);
4182 if (mgp == NULL)
4183 return;
4184
23f333a2 4185 cancel_work_sync(&mgp->watchdog_work);
0da34b6d
BG		 4186 netdev = mgp->dev;
4187 unregister_netdev(netdev);
0da34b6d 4188
5dd2d332 4189#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4190 myri10ge_teardown_dca(mgp);
4191#endif
0da34b6d
BG		 4192 myri10ge_dummy_rdma(mgp, 0);
4193
7adda30c 4194 /* avoid a memory leak */
83f6e152 4195 pci_restore_state(pdev);
7adda30c 4196
0da34b6d
BG		 4197 iounmap(mgp->sram);
4198
4199#ifdef CONFIG_MTRR
4200 if (mgp->mtrr >= 0)
4201 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4202#endif
0dcffac1
BG		 4203 myri10ge_free_slices(mgp);
4204 if (mgp->msix_vectors != NULL)
4205 kfree(mgp->msix_vectors);
b10c0668
BG		 4206 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4207 mgp->cmd, mgp->cmd_bus);
0da34b6d 4208
7d351035 4209 set_fw_name(mgp, NULL, false);
0da34b6d 4210 free_netdev(netdev);
e3fd5534 4211 pci_disable_device(pdev);
0da34b6d
BG		 4212}
4213
b10c0668 4214#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4215#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 4216
a3aa1884 4217static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
b10c0668 4218 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4219 {PCI_DEVICE
4220 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4221 {0},
4222};
4223
97131079
BG		 4224MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4225
0da34b6d
BG		 4226static struct pci_driver myri10ge_driver = {
4227 .name = "myri10ge",
4228 .probe = myri10ge_probe,
4229 .remove = myri10ge_remove,
4230 .id_table = myri10ge_pci_tbl,
4231#ifdef CONFIG_PM
4232 .suspend = myri10ge_suspend,
4233 .resume = myri10ge_resume,
4234#endif
4235};
4236
5dd2d332 4237#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4238static int
4239myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4240{
4241 int err = driver_for_each_device(&myri10ge_driver.driver,
4242 NULL, &event,
4243 myri10ge_notify_dca_device);
4244
4245 if (err)
4246 return NOTIFY_BAD;
4247 return NOTIFY_DONE;
4248}
4249
4250static struct notifier_block myri10ge_dca_notifier = {
4251 .notifier_call = myri10ge_notify_dca,
4252 .next = NULL,
4253 .priority = 0,
4254};
4ee2ac51 4255#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4256
0da34b6d
BG		 4257static __init int myri10ge_init_module(void)
4258{
78ca90ea 4259 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4260
236bb5e6 4261 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4262 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4263 myri10ge_rss_hash);
0dcffac1
BG		 4264 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4265 }
5dd2d332 4266#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4267 dca_register_notify(&myri10ge_dca_notifier);
4268#endif
236bb5e6
BG		 4269 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4270 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4271
0da34b6d
BG		 4272 return pci_register_driver(&myri10ge_driver);
4273}
4274
4275module_init(myri10ge_init_module);
4276
4277static __exit void myri10ge_cleanup_module(void)
4278{
5dd2d332 4279#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4280 dca_unregister_notify(&myri10ge_dca_notifier);
4281#endif
0da34b6d
BG		 4282 pci_unregister_driver(&myri10ge_driver);
4283}
4284
4285module_exit(myri10ge_cleanup_module);
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