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10096974 1#define VERSION "0.23"
1da177e4
LT
2/* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
0ab75ae8 25 * along with this program; if not, see <http://www.gnu.org/licenses/>.
1da177e4
LT
26 *
27 *
28 * ChangeLog
29 * =========
30 * 20010414 0.1 - created
31 * 20010622 0.2 - basic rx and tx.
32 * 20010711 0.3 - added duplex and link state detection support.
33 * 20010713 0.4 - zero copy, no hangs.
34 * 0.5 - 64 bit dma support (davem will hate me for this)
35 * - disable jumbo frames to avoid tx hangs
36 * - work around tx deadlocks on my 1.02 card via
37 * fiddling with TXCFG
38 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
39 * 20010816 0.7 - misc cleanups
40 * 20010826 0.8 - fix critical zero copy bugs
41 * 0.9 - internal experiment
42 * 20010827 0.10 - fix ia64 unaligned access.
43 * 20010906 0.11 - accept all packets with checksum errors as
44 * otherwise fragments get lost
45 * - fix >> 32 bugs
46 * 0.12 - add statistics counters
47 * - add allmulti/promisc support
48 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
49 * 20011204 0.13a - optical transceiver support added
50 * by Michael Clark <michael@metaparadigm.com>
51 * 20011205 0.13b - call register_netdev earlier in initialization
52 * suppress duplicate link status messages
53 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
54 * 20011204 0.15 get ppc (big endian) working
55 * 20011218 0.16 various cleanups
56 * 20020310 0.17 speedups
57 * 20020610 0.18 - actually use the pci dma api for highmem
58 * - remove pci latency register fiddling
59 * 0.19 - better bist support
60 * - add ihr and reset_phy parameters
61 * - gmii bus probing
62 * - fix missed txok introduced during performance
63 * tuning
64 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
1da177e4
LT
65 * 20040828 0.21 - add hardware vlan accleration
66 * by Neil Horman <nhorman@redhat.com>
6aa20a22 67 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
c16ef1ce
BL
68 * - removal of dead code from Adrian Bunk
69 * - fix half duplex collision behaviour
1da177e4
LT
70 * Driver Overview
71 * ===============
72 *
73 * This driver was originally written for the National Semiconductor
74 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
75 * this code will turn out to be a) clean, b) correct, and c) fast.
76 * With that in mind, I'm aiming to split the code up as much as
77 * reasonably possible. At present there are X major sections that
78 * break down into a) packet receive, b) packet transmit, c) link
79 * management, d) initialization and configuration. Where possible,
80 * these code paths are designed to run in parallel.
81 *
82 * This driver has been tested and found to work with the following
83 * cards (in no particular order):
84 *
85 * Cameo SOHO-GA2000T SOHO-GA2500T
86 * D-Link DGE-500T
87 * PureData PDP8023Z-TG
88 * SMC SMC9452TX SMC9462TX
89 * Netgear GA621
90 *
91 * Special thanks to SMC for providing hardware to test this driver on.
92 *
93 * Reports of success or failure would be greatly appreciated.
94 */
95//#define dprintk printk
96#define dprintk(x...) do { } while (0)
97
1da177e4
LT
98#include <linux/module.h>
99#include <linux/moduleparam.h>
100#include <linux/types.h>
101#include <linux/pci.h>
1e7f0bd8 102#include <linux/dma-mapping.h>
1da177e4
LT
103#include <linux/netdevice.h>
104#include <linux/etherdevice.h>
105#include <linux/delay.h>
1da177e4
LT
106#include <linux/workqueue.h>
107#include <linux/init.h>
a6b7a407 108#include <linux/interrupt.h>
1da177e4
LT
109#include <linux/ip.h> /* for iph */
110#include <linux/in.h> /* for IPPROTO_... */
1da177e4
LT
111#include <linux/compiler.h>
112#include <linux/prefetch.h>
113#include <linux/ethtool.h>
d43c36dc 114#include <linux/sched.h>
1da177e4
LT
115#include <linux/timer.h>
116#include <linux/if_vlan.h>
14c85021 117#include <linux/rtnetlink.h>
ff5688ae 118#include <linux/jiffies.h>
5a0e3ad6 119#include <linux/slab.h>
1da177e4
LT
120
121#include <asm/io.h>
122#include <asm/uaccess.h>
1da177e4
LT
123
124#define DRV_NAME "ns83820"
125
126/* Global parameters. See module_param near the bottom. */
127static int ihr = 2;
128static int reset_phy = 0;
129static int lnksts = 0; /* CFG_LNKSTS bit polarity */
130
131/* Dprintk is used for more interesting debug events */
132#undef Dprintk
133#define Dprintk dprintk
134
1da177e4
LT
135/* tunables */
136#define RX_BUF_SIZE 1500 /* 8192 */
137#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
138#define NS83820_VLAN_ACCEL_SUPPORT
139#endif
140
141/* Must not exceed ~65000. */
142#define NR_RX_DESC 64
143#define NR_TX_DESC 128
144
145/* not tunable */
146#define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
147
148#define MIN_TX_DESC_FREE 8
149
150/* register defines */
151#define CFGCS 0x04
152
153#define CR_TXE 0x00000001
154#define CR_TXD 0x00000002
155/* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
156 * The Receive engine skips one descriptor and moves
157 * onto the next one!! */
158#define CR_RXE 0x00000004
159#define CR_RXD 0x00000008
160#define CR_TXR 0x00000010
161#define CR_RXR 0x00000020
162#define CR_SWI 0x00000080
163#define CR_RST 0x00000100
164
165#define PTSCR_EEBIST_FAIL 0x00000001
166#define PTSCR_EEBIST_EN 0x00000002
167#define PTSCR_EELOAD_EN 0x00000004
168#define PTSCR_RBIST_FAIL 0x000001b8
169#define PTSCR_RBIST_DONE 0x00000200
170#define PTSCR_RBIST_EN 0x00000400
171#define PTSCR_RBIST_RST 0x00002000
172
173#define MEAR_EEDI 0x00000001
174#define MEAR_EEDO 0x00000002
175#define MEAR_EECLK 0x00000004
176#define MEAR_EESEL 0x00000008
177#define MEAR_MDIO 0x00000010
178#define MEAR_MDDIR 0x00000020
179#define MEAR_MDC 0x00000040
180
181#define ISR_TXDESC3 0x40000000
182#define ISR_TXDESC2 0x20000000
183#define ISR_TXDESC1 0x10000000
184#define ISR_TXDESC0 0x08000000
185#define ISR_RXDESC3 0x04000000
186#define ISR_RXDESC2 0x02000000
187#define ISR_RXDESC1 0x01000000
188#define ISR_RXDESC0 0x00800000
189#define ISR_TXRCMP 0x00400000
190#define ISR_RXRCMP 0x00200000
191#define ISR_DPERR 0x00100000
192#define ISR_SSERR 0x00080000
193#define ISR_RMABT 0x00040000
194#define ISR_RTABT 0x00020000
195#define ISR_RXSOVR 0x00010000
196#define ISR_HIBINT 0x00008000
197#define ISR_PHY 0x00004000
198#define ISR_PME 0x00002000
199#define ISR_SWI 0x00001000
200#define ISR_MIB 0x00000800
201#define ISR_TXURN 0x00000400
202#define ISR_TXIDLE 0x00000200
203#define ISR_TXERR 0x00000100
204#define ISR_TXDESC 0x00000080
205#define ISR_TXOK 0x00000040
206#define ISR_RXORN 0x00000020
207#define ISR_RXIDLE 0x00000010
208#define ISR_RXEARLY 0x00000008
209#define ISR_RXERR 0x00000004
210#define ISR_RXDESC 0x00000002
211#define ISR_RXOK 0x00000001
212
213#define TXCFG_CSI 0x80000000
214#define TXCFG_HBI 0x40000000
215#define TXCFG_MLB 0x20000000
216#define TXCFG_ATP 0x10000000
217#define TXCFG_ECRETRY 0x00800000
218#define TXCFG_BRST_DIS 0x00080000
219#define TXCFG_MXDMA1024 0x00000000
220#define TXCFG_MXDMA512 0x00700000
221#define TXCFG_MXDMA256 0x00600000
222#define TXCFG_MXDMA128 0x00500000
223#define TXCFG_MXDMA64 0x00400000
224#define TXCFG_MXDMA32 0x00300000
225#define TXCFG_MXDMA16 0x00200000
226#define TXCFG_MXDMA8 0x00100000
227
228#define CFG_LNKSTS 0x80000000
229#define CFG_SPDSTS 0x60000000
230#define CFG_SPDSTS1 0x40000000
231#define CFG_SPDSTS0 0x20000000
232#define CFG_DUPSTS 0x10000000
233#define CFG_TBI_EN 0x01000000
234#define CFG_MODE_1000 0x00400000
235/* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
236 * Read the Phy response and then configure the MAC accordingly */
237#define CFG_AUTO_1000 0x00200000
238#define CFG_PINT_CTL 0x001c0000
239#define CFG_PINT_DUPSTS 0x00100000
240#define CFG_PINT_LNKSTS 0x00080000
241#define CFG_PINT_SPDSTS 0x00040000
242#define CFG_TMRTEST 0x00020000
243#define CFG_MRM_DIS 0x00010000
244#define CFG_MWI_DIS 0x00008000
245#define CFG_T64ADDR 0x00004000
246#define CFG_PCI64_DET 0x00002000
247#define CFG_DATA64_EN 0x00001000
248#define CFG_M64ADDR 0x00000800
249#define CFG_PHY_RST 0x00000400
250#define CFG_PHY_DIS 0x00000200
251#define CFG_EXTSTS_EN 0x00000100
252#define CFG_REQALG 0x00000080
253#define CFG_SB 0x00000040
254#define CFG_POW 0x00000020
255#define CFG_EXD 0x00000010
256#define CFG_PESEL 0x00000008
257#define CFG_BROM_DIS 0x00000004
258#define CFG_EXT_125 0x00000002
259#define CFG_BEM 0x00000001
260
261#define EXTSTS_UDPPKT 0x00200000
262#define EXTSTS_TCPPKT 0x00080000
263#define EXTSTS_IPPKT 0x00020000
264#define EXTSTS_VPKT 0x00010000
265#define EXTSTS_VTG_MASK 0x0000ffff
266
267#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
268
269#define MIBC_MIBS 0x00000008
270#define MIBC_ACLR 0x00000004
271#define MIBC_FRZ 0x00000002
272#define MIBC_WRN 0x00000001
273
274#define PCR_PSEN (1 << 31)
275#define PCR_PS_MCAST (1 << 30)
276#define PCR_PS_DA (1 << 29)
277#define PCR_STHI_8 (3 << 23)
278#define PCR_STLO_4 (1 << 23)
279#define PCR_FFHI_8K (3 << 21)
280#define PCR_FFLO_4K (1 << 21)
281#define PCR_PAUSE_CNT 0xFFFE
282
283#define RXCFG_AEP 0x80000000
284#define RXCFG_ARP 0x40000000
285#define RXCFG_STRIPCRC 0x20000000
286#define RXCFG_RX_FD 0x10000000
287#define RXCFG_ALP 0x08000000
288#define RXCFG_AIRL 0x04000000
289#define RXCFG_MXDMA512 0x00700000
290#define RXCFG_DRTH 0x0000003e
291#define RXCFG_DRTH0 0x00000002
292
293#define RFCR_RFEN 0x80000000
294#define RFCR_AAB 0x40000000
295#define RFCR_AAM 0x20000000
296#define RFCR_AAU 0x10000000
297#define RFCR_APM 0x08000000
298#define RFCR_APAT 0x07800000
299#define RFCR_APAT3 0x04000000
300#define RFCR_APAT2 0x02000000
301#define RFCR_APAT1 0x01000000
302#define RFCR_APAT0 0x00800000
303#define RFCR_AARP 0x00400000
304#define RFCR_MHEN 0x00200000
305#define RFCR_UHEN 0x00100000
306#define RFCR_ULM 0x00080000
307
308#define VRCR_RUDPE 0x00000080
309#define VRCR_RTCPE 0x00000040
310#define VRCR_RIPE 0x00000020
311#define VRCR_IPEN 0x00000010
312#define VRCR_DUTF 0x00000008
313#define VRCR_DVTF 0x00000004
314#define VRCR_VTREN 0x00000002
315#define VRCR_VTDEN 0x00000001
316
317#define VTCR_PPCHK 0x00000008
318#define VTCR_GCHK 0x00000004
319#define VTCR_VPPTI 0x00000002
320#define VTCR_VGTI 0x00000001
321
322#define CR 0x00
323#define CFG 0x04
324#define MEAR 0x08
325#define PTSCR 0x0c
326#define ISR 0x10
327#define IMR 0x14
328#define IER 0x18
329#define IHR 0x1c
330#define TXDP 0x20
331#define TXDP_HI 0x24
332#define TXCFG 0x28
333#define GPIOR 0x2c
334#define RXDP 0x30
335#define RXDP_HI 0x34
336#define RXCFG 0x38
337#define PQCR 0x3c
338#define WCSR 0x40
339#define PCR 0x44
340#define RFCR 0x48
341#define RFDR 0x4c
342
343#define SRR 0x58
344
345#define VRCR 0xbc
346#define VTCR 0xc0
347#define VDR 0xc4
348#define CCSR 0xcc
349
350#define TBICR 0xe0
351#define TBISR 0xe4
352#define TANAR 0xe8
353#define TANLPAR 0xec
354#define TANER 0xf0
355#define TESR 0xf4
356
357#define TBICR_MR_AN_ENABLE 0x00001000
358#define TBICR_MR_RESTART_AN 0x00000200
359
360#define TBISR_MR_LINK_STATUS 0x00000020
361#define TBISR_MR_AN_COMPLETE 0x00000004
362
363#define TANAR_PS2 0x00000100
364#define TANAR_PS1 0x00000080
365#define TANAR_HALF_DUP 0x00000040
366#define TANAR_FULL_DUP 0x00000020
367
368#define GPIOR_GP5_OE 0x00000200
369#define GPIOR_GP4_OE 0x00000100
370#define GPIOR_GP3_OE 0x00000080
371#define GPIOR_GP2_OE 0x00000040
372#define GPIOR_GP1_OE 0x00000020
373#define GPIOR_GP3_OUT 0x00000004
374#define GPIOR_GP1_OUT 0x00000001
375
376#define LINK_AUTONEGOTIATE 0x01
377#define LINK_DOWN 0x02
378#define LINK_UP 0x04
379
6aa20a22 380#define HW_ADDR_LEN sizeof(dma_addr_t)
1da177e4
LT
381#define desc_addr_set(desc, addr) \
382 do { \
c16ef1ce
BL
383 ((desc)[0] = cpu_to_le32(addr)); \
384 if (HW_ADDR_LEN == 8) \
385 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
1da177e4
LT
386 } while(0)
387#define desc_addr_get(desc) \
c16ef1ce
BL
388 (le32_to_cpu((desc)[0]) | \
389 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
1da177e4
LT
390
391#define DESC_LINK 0
392#define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
393#define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
394#define DESC_EXTSTS (DESC_CMDSTS + 4/4)
395
396#define CMDSTS_OWN 0x80000000
397#define CMDSTS_MORE 0x40000000
398#define CMDSTS_INTR 0x20000000
399#define CMDSTS_ERR 0x10000000
400#define CMDSTS_OK 0x08000000
401#define CMDSTS_RUNT 0x00200000
402#define CMDSTS_LEN_MASK 0x0000ffff
403
404#define CMDSTS_DEST_MASK 0x01800000
405#define CMDSTS_DEST_SELF 0x00800000
406#define CMDSTS_DEST_MULTI 0x01000000
407
408#define DESC_SIZE 8 /* Should be cache line sized */
409
410struct rx_info {
411 spinlock_t lock;
412 int up;
5d7dce76 413 unsigned long idle;
1da177e4
LT
414
415 struct sk_buff *skbs[NR_RX_DESC];
416
c69fda4e 417 __le32 *next_rx_desc;
1da177e4
LT
418 u16 next_rx, next_empty;
419
c69fda4e 420 __le32 *descs;
1da177e4
LT
421 dma_addr_t phy_descs;
422};
423
424
425struct ns83820 {
1da177e4
LT
426 u8 __iomem *base;
427
428 struct pci_dev *pci_dev;
c4028958 429 struct net_device *ndev;
1da177e4 430
1da177e4
LT
431 struct rx_info rx_info;
432 struct tasklet_struct rx_tasklet;
433
434 unsigned ihr;
435 struct work_struct tq_refill;
436
437 /* protects everything below. irqsave when using. */
438 spinlock_t misc_lock;
439
440 u32 CFG_cache;
441
442 u32 MEAR_cache;
443 u32 IMR_cache;
1da177e4
LT
444
445 unsigned linkstate;
446
447 spinlock_t tx_lock;
448
449 u16 tx_done_idx;
450 u16 tx_idx;
451 volatile u16 tx_free_idx; /* idx of free desc chain */
452 u16 tx_intr_idx;
453
454 atomic_t nr_tx_skbs;
455 struct sk_buff *tx_skbs[NR_TX_DESC];
456
457 char pad[16] __attribute__((aligned(16)));
c69fda4e 458 __le32 *tx_descs;
1da177e4
LT
459 dma_addr_t tx_phy_descs;
460
461 struct timer_list tx_watchdog;
462};
463
464static inline struct ns83820 *PRIV(struct net_device *dev)
465{
466 return netdev_priv(dev);
467}
468
469#define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
470
471static inline void kick_rx(struct net_device *ndev)
472{
473 struct ns83820 *dev = PRIV(ndev);
474 dprintk("kick_rx: maybe kicking\n");
475 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
476 dprintk("actually kicking\n");
477 writel(dev->rx_info.phy_descs +
478 (4 * DESC_SIZE * dev->rx_info.next_rx),
479 dev->base + RXDP);
480 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
481 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
482 ndev->name);
483 __kick_rx(dev);
484 }
485}
486
487//free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
488#define start_tx_okay(dev) \
489 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
490
1da177e4
LT
491/* Packet Receiver
492 *
493 * The hardware supports linked lists of receive descriptors for
25985edc 494 * which ownership is transferred back and forth by means of an
1da177e4
LT
495 * ownership bit. While the hardware does support the use of a
496 * ring for receive descriptors, we only make use of a chain in
497 * an attempt to reduce bus traffic under heavy load scenarios.
498 * This will also make bugs a bit more obvious. The current code
499 * only makes use of a single rx chain; I hope to implement
500 * priority based rx for version 1.0. Goal: even under overload
501 * conditions, still route realtime traffic with as low jitter as
502 * possible.
503 */
c69fda4e 504static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
1da177e4
LT
505{
506 desc_addr_set(desc + DESC_LINK, link);
507 desc_addr_set(desc + DESC_BUFPTR, buf);
508 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
509 mb();
510 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
511}
512
513#define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
514static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
515{
516 unsigned next_empty;
517 u32 cmdsts;
c69fda4e 518 __le32 *sg;
1da177e4
LT
519 dma_addr_t buf;
520
521 next_empty = dev->rx_info.next_empty;
522
523 /* don't overrun last rx marker */
524 if (unlikely(nr_rx_empty(dev) <= 2)) {
525 kfree_skb(skb);
526 return 1;
527 }
528
529#if 0
530 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
531 dev->rx_info.next_empty,
532 dev->rx_info.nr_used,
533 dev->rx_info.next_rx
534 );
535#endif
536
537 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
5d9428de 538 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
1da177e4
LT
539 dev->rx_info.skbs[next_empty] = skb;
540
541 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
542 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
689be439 543 buf = pci_map_single(dev->pci_dev, skb->data,
1da177e4
LT
544 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
545 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
546 /* update link of previous rx */
547 if (likely(next_empty != dev->rx_info.next_rx))
548 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
549
550 return 0;
551}
552
dd0fc66f 553static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
1da177e4
LT
554{
555 struct ns83820 *dev = PRIV(ndev);
556 unsigned i;
557 unsigned long flags = 0;
558
559 if (unlikely(nr_rx_empty(dev) <= 2))
560 return 0;
561
562 dprintk("rx_refill(%p)\n", ndev);
563 if (gfp == GFP_ATOMIC)
564 spin_lock_irqsave(&dev->rx_info.lock, flags);
565 for (i=0; i<NR_RX_DESC; i++) {
566 struct sk_buff *skb;
567 long res;
e83728c7 568
1da177e4 569 /* extra 16 bytes for alignment */
e83728c7 570 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
1da177e4
LT
571 if (unlikely(!skb))
572 break;
573
e83728c7 574 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
1da177e4
LT
575 if (gfp != GFP_ATOMIC)
576 spin_lock_irqsave(&dev->rx_info.lock, flags);
577 res = ns83820_add_rx_skb(dev, skb);
578 if (gfp != GFP_ATOMIC)
579 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
580 if (res) {
581 i = 1;
582 break;
583 }
584 }
585 if (gfp == GFP_ATOMIC)
586 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
587
588 return i ? 0 : -ENOMEM;
589}
590
7eefb04e 591static void rx_refill_atomic(struct net_device *ndev)
1da177e4
LT
592{
593 rx_refill(ndev, GFP_ATOMIC);
594}
595
596/* REFILL */
c4028958 597static inline void queue_refill(struct work_struct *work)
1da177e4 598{
c4028958
DH
599 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
600 struct net_device *ndev = dev->ndev;
1da177e4
LT
601
602 rx_refill(ndev, GFP_KERNEL);
603 if (dev->rx_info.up)
604 kick_rx(ndev);
605}
606
607static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
608{
609 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
610}
611
7eefb04e 612static void phy_intr(struct net_device *ndev)
1da177e4
LT
613{
614 struct ns83820 *dev = PRIV(ndev);
f71e1309 615 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
1da177e4
LT
616 u32 cfg, new_cfg;
617 u32 tbisr, tanar, tanlpar;
618 int speed, fullduplex, newlinkstate;
619
620 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
621
622 if (dev->CFG_cache & CFG_TBI_EN) {
623 /* we have an optical transceiver */
624 tbisr = readl(dev->base + TBISR);
625 tanar = readl(dev->base + TANAR);
626 tanlpar = readl(dev->base + TANLPAR);
627 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
628 tbisr, tanar, tanlpar);
629
8e95a202
JP
630 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
631 (tanar & TANAR_FULL_DUP)) ) {
1da177e4
LT
632
633 /* both of us are full duplex */
634 writel(readl(dev->base + TXCFG)
635 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
636 dev->base + TXCFG);
637 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
638 dev->base + RXCFG);
639 /* Light up full duplex LED */
640 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
641 dev->base + GPIOR);
642
8e95a202
JP
643 } else if (((tanlpar & TANAR_HALF_DUP) &&
644 (tanar & TANAR_HALF_DUP)) ||
645 ((tanlpar & TANAR_FULL_DUP) &&
646 (tanar & TANAR_HALF_DUP)) ||
647 ((tanlpar & TANAR_HALF_DUP) &&
648 (tanar & TANAR_FULL_DUP))) {
1da177e4
LT
649
650 /* one or both of us are half duplex */
651 writel((readl(dev->base + TXCFG)
652 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
653 dev->base + TXCFG);
654 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
655 dev->base + RXCFG);
656 /* Turn off full duplex LED */
657 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
658 dev->base + GPIOR);
659 }
660
661 speed = 4; /* 1000F */
662
663 } else {
664 /* we have a copper transceiver */
665 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
666
667 if (cfg & CFG_SPDSTS1)
668 new_cfg |= CFG_MODE_1000;
669 else
670 new_cfg &= ~CFG_MODE_1000;
671
672 speed = ((cfg / CFG_SPDSTS0) & 3);
673 fullduplex = (cfg & CFG_DUPSTS);
674
c16ef1ce 675 if (fullduplex) {
1da177e4 676 new_cfg |= CFG_SB;
c16ef1ce
BL
677 writel(readl(dev->base + TXCFG)
678 | TXCFG_CSI | TXCFG_HBI,
679 dev->base + TXCFG);
680 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
681 dev->base + RXCFG);
682 } else {
683 writel(readl(dev->base + TXCFG)
684 & ~(TXCFG_CSI | TXCFG_HBI),
685 dev->base + TXCFG);
686 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
687 dev->base + RXCFG);
688 }
1da177e4
LT
689
690 if ((cfg & CFG_LNKSTS) &&
c16ef1ce 691 ((new_cfg ^ dev->CFG_cache) != 0)) {
1da177e4
LT
692 writel(new_cfg, dev->base + CFG);
693 dev->CFG_cache = new_cfg;
694 }
695
696 dev->CFG_cache &= ~CFG_SPDSTS;
697 dev->CFG_cache |= cfg & CFG_SPDSTS;
698 }
699
700 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
701
8e95a202
JP
702 if (newlinkstate & LINK_UP &&
703 dev->linkstate != newlinkstate) {
1da177e4
LT
704 netif_start_queue(ndev);
705 netif_wake_queue(ndev);
706 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
707 ndev->name,
708 speeds[speed],
709 fullduplex ? "full" : "half");
8e95a202
JP
710 } else if (newlinkstate & LINK_DOWN &&
711 dev->linkstate != newlinkstate) {
1da177e4
LT
712 netif_stop_queue(ndev);
713 printk(KERN_INFO "%s: link now down.\n", ndev->name);
714 }
715
716 dev->linkstate = newlinkstate;
717}
718
719static int ns83820_setup_rx(struct net_device *ndev)
720{
721 struct ns83820 *dev = PRIV(ndev);
722 unsigned i;
723 int ret;
724
725 dprintk("ns83820_setup_rx(%p)\n", ndev);
726
727 dev->rx_info.idle = 1;
728 dev->rx_info.next_rx = 0;
729 dev->rx_info.next_rx_desc = dev->rx_info.descs;
730 dev->rx_info.next_empty = 0;
731
732 for (i=0; i<NR_RX_DESC; i++)
733 clear_rx_desc(dev, i);
734
735 writel(0, dev->base + RXDP_HI);
736 writel(dev->rx_info.phy_descs, dev->base + RXDP);
737
738 ret = rx_refill(ndev, GFP_KERNEL);
739 if (!ret) {
740 dprintk("starting receiver\n");
741 /* prevent the interrupt handler from stomping on us */
742 spin_lock_irq(&dev->rx_info.lock);
743
744 writel(0x0001, dev->base + CCSR);
745 writel(0, dev->base + RFCR);
746 writel(0x7fc00000, dev->base + RFCR);
747 writel(0xffc00000, dev->base + RFCR);
748
749 dev->rx_info.up = 1;
750
751 phy_intr(ndev);
752
753 /* Okay, let it rip */
cdd861d6 754 spin_lock(&dev->misc_lock);
1da177e4
LT
755 dev->IMR_cache |= ISR_PHY;
756 dev->IMR_cache |= ISR_RXRCMP;
757 //dev->IMR_cache |= ISR_RXERR;
758 //dev->IMR_cache |= ISR_RXOK;
759 dev->IMR_cache |= ISR_RXORN;
760 dev->IMR_cache |= ISR_RXSOVR;
761 dev->IMR_cache |= ISR_RXDESC;
762 dev->IMR_cache |= ISR_RXIDLE;
763 dev->IMR_cache |= ISR_TXDESC;
764 dev->IMR_cache |= ISR_TXIDLE;
765
766 writel(dev->IMR_cache, dev->base + IMR);
767 writel(1, dev->base + IER);
3a10cceb 768 spin_unlock(&dev->misc_lock);
1da177e4
LT
769
770 kick_rx(ndev);
771
772 spin_unlock_irq(&dev->rx_info.lock);
773 }
774 return ret;
775}
776
777static void ns83820_cleanup_rx(struct ns83820 *dev)
778{
779 unsigned i;
780 unsigned long flags;
781
782 dprintk("ns83820_cleanup_rx(%p)\n", dev);
783
784 /* disable receive interrupts */
785 spin_lock_irqsave(&dev->misc_lock, flags);
786 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
787 writel(dev->IMR_cache, dev->base + IMR);
788 spin_unlock_irqrestore(&dev->misc_lock, flags);
789
790 /* synchronize with the interrupt handler and kill it */
791 dev->rx_info.up = 0;
792 synchronize_irq(dev->pci_dev->irq);
793
794 /* touch the pci bus... */
795 readl(dev->base + IMR);
796
797 /* assumes the transmitter is already disabled and reset */
798 writel(0, dev->base + RXDP_HI);
799 writel(0, dev->base + RXDP);
800
801 for (i=0; i<NR_RX_DESC; i++) {
802 struct sk_buff *skb = dev->rx_info.skbs[i];
803 dev->rx_info.skbs[i] = NULL;
804 clear_rx_desc(dev, i);
893d7de7 805 kfree_skb(skb);
1da177e4
LT
806 }
807}
808
7eefb04e 809static void ns83820_rx_kick(struct net_device *ndev)
1da177e4
LT
810{
811 struct ns83820 *dev = PRIV(ndev);
812 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
813 if (dev->rx_info.up) {
814 rx_refill_atomic(ndev);
815 kick_rx(ndev);
816 }
817 }
818
819 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
820 schedule_work(&dev->tq_refill);
821 else
822 kick_rx(ndev);
823 if (dev->rx_info.idle)
824 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
825}
826
827/* rx_irq
6aa20a22 828 *
1da177e4 829 */
7eefb04e 830static void rx_irq(struct net_device *ndev)
1da177e4
LT
831{
832 struct ns83820 *dev = PRIV(ndev);
833 struct rx_info *info = &dev->rx_info;
834 unsigned next_rx;
835 int rx_rc, len;
c69fda4e
AV
836 u32 cmdsts;
837 __le32 *desc;
1da177e4
LT
838 unsigned long flags;
839 int nr = 0;
840
841 dprintk("rx_irq(%p)\n", ndev);
842 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
843 readl(dev->base + RXDP),
844 (long)(dev->rx_info.phy_descs),
845 (int)dev->rx_info.next_rx,
846 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
847 (int)dev->rx_info.next_empty,
848 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
849 );
850
851 spin_lock_irqsave(&info->lock, flags);
852 if (!info->up)
853 goto out;
854
855 dprintk("walking descs\n");
856 next_rx = info->next_rx;
857 desc = info->next_rx_desc;
858 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
859 (cmdsts != CMDSTS_OWN)) {
860 struct sk_buff *skb;
861 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
862 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
863
864 dprintk("cmdsts: %08x\n", cmdsts);
865 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
866 dprintk("extsts: %08x\n", extsts);
867
868 skb = info->skbs[next_rx];
869 info->skbs[next_rx] = NULL;
870 info->next_rx = (next_rx + 1) % NR_RX_DESC;
871
872 mb();
873 clear_rx_desc(dev, next_rx);
874
875 pci_unmap_single(dev->pci_dev, bufptr,
876 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
877 len = cmdsts & CMDSTS_LEN_MASK;
878#ifdef NS83820_VLAN_ACCEL_SUPPORT
879 /* NH: As was mentioned below, this chip is kinda
880 * brain dead about vlan tag stripping. Frames
881 * that are 64 bytes with a vlan header appended
882 * like arp frames, or pings, are flagged as Runts
883 * when the tag is stripped and hardware. This
6aa20a22 884 * also means that the OK bit in the descriptor
1da177e4
LT
885 * is cleared when the frame comes in so we have
886 * to do a specific length check here to make sure
887 * the frame would have been ok, had we not stripped
888 * the tag.
6aa20a22 889 */
1da177e4 890 if (likely((CMDSTS_OK & cmdsts) ||
6aa20a22 891 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
1da177e4
LT
892#else
893 if (likely(CMDSTS_OK & cmdsts)) {
894#endif
895 skb_put(skb, len);
896 if (unlikely(!skb))
897 goto netdev_mangle_me_harder_failed;
898 if (cmdsts & CMDSTS_DEST_MULTI)
e929bc33
KV
899 ndev->stats.multicast++;
900 ndev->stats.rx_packets++;
901 ndev->stats.rx_bytes += len;
1da177e4
LT
902 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
903 skb->ip_summed = CHECKSUM_UNNECESSARY;
904 } else {
bc8acf2c 905 skb_checksum_none_assert(skb);
1da177e4
LT
906 }
907 skb->protocol = eth_type_trans(skb, ndev);
6aa20a22 908#ifdef NS83820_VLAN_ACCEL_SUPPORT
1da177e4
LT
909 if(extsts & EXTSTS_VPKT) {
910 unsigned short tag;
a4f676b8 911
1da177e4 912 tag = ntohs(extsts & EXTSTS_VTG_MASK);
86a9bad3 913 __vlan_hwaccel_put_tag(skb, htons(ETH_P_IPV6), tag);
1da177e4 914 }
1da177e4 915#endif
a4f676b8 916 rx_rc = netif_rx(skb);
1da177e4
LT
917 if (NET_RX_DROP == rx_rc) {
918netdev_mangle_me_harder_failed:
e929bc33 919 ndev->stats.rx_dropped++;
1da177e4
LT
920 }
921 } else {
922 kfree_skb(skb);
923 }
924
925 nr++;
926 next_rx = info->next_rx;
927 desc = info->descs + (DESC_SIZE * next_rx);
928 }
929 info->next_rx = next_rx;
930 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
931
932out:
933 if (0 && !nr) {
934 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
935 }
936
937 spin_unlock_irqrestore(&info->lock, flags);
938}
939
940static void rx_action(unsigned long _dev)
941{
942 struct net_device *ndev = (void *)_dev;
943 struct ns83820 *dev = PRIV(ndev);
944 rx_irq(ndev);
945 writel(ihr, dev->base + IHR);
946
947 spin_lock_irq(&dev->misc_lock);
948 dev->IMR_cache |= ISR_RXDESC;
949 writel(dev->IMR_cache, dev->base + IMR);
950 spin_unlock_irq(&dev->misc_lock);
951
952 rx_irq(ndev);
953 ns83820_rx_kick(ndev);
954}
955
956/* Packet Transmit code
957 */
958static inline void kick_tx(struct ns83820 *dev)
959{
960 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
961 dev, dev->tx_idx, dev->tx_free_idx);
962 writel(CR_TXE, dev->base + CR);
963}
964
965/* No spinlock needed on the transmit irq path as the interrupt handler is
966 * serialized.
967 */
968static void do_tx_done(struct net_device *ndev)
969{
970 struct ns83820 *dev = PRIV(ndev);
c69fda4e
AV
971 u32 cmdsts, tx_done_idx;
972 __le32 *desc;
1da177e4 973
1da177e4
LT
974 dprintk("do_tx_done(%p)\n", ndev);
975 tx_done_idx = dev->tx_done_idx;
976 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
977
978 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
979 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
980 while ((tx_done_idx != dev->tx_free_idx) &&
981 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
982 struct sk_buff *skb;
983 unsigned len;
984 dma_addr_t addr;
985
986 if (cmdsts & CMDSTS_ERR)
e929bc33 987 ndev->stats.tx_errors++;
1da177e4 988 if (cmdsts & CMDSTS_OK)
e929bc33 989 ndev->stats.tx_packets++;
1da177e4 990 if (cmdsts & CMDSTS_OK)
e929bc33 991 ndev->stats.tx_bytes += cmdsts & 0xffff;
1da177e4
LT
992
993 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
994 tx_done_idx, dev->tx_free_idx, cmdsts);
995 skb = dev->tx_skbs[tx_done_idx];
996 dev->tx_skbs[tx_done_idx] = NULL;
997 dprintk("done(%p)\n", skb);
998
999 len = cmdsts & CMDSTS_LEN_MASK;
1000 addr = desc_addr_get(desc + DESC_BUFPTR);
1001 if (skb) {
1002 pci_unmap_single(dev->pci_dev,
1003 addr,
1004 len,
1005 PCI_DMA_TODEVICE);
1006 dev_kfree_skb_irq(skb);
1007 atomic_dec(&dev->nr_tx_skbs);
1008 } else
6aa20a22 1009 pci_unmap_page(dev->pci_dev,
1da177e4
LT
1010 addr,
1011 len,
1012 PCI_DMA_TODEVICE);
1013
1014 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1015 dev->tx_done_idx = tx_done_idx;
1016 desc[DESC_CMDSTS] = cpu_to_le32(0);
1017 mb();
1018 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1019 }
1020
1021 /* Allow network stack to resume queueing packets after we've
1022 * finished transmitting at least 1/4 of the packets in the queue.
1023 */
1024 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1025 dprintk("start_queue(%p)\n", ndev);
1026 netif_start_queue(ndev);
1027 netif_wake_queue(ndev);
1028 }
1da177e4
LT
1029}
1030
1031static void ns83820_cleanup_tx(struct ns83820 *dev)
1032{
1033 unsigned i;
1034
1035 for (i=0; i<NR_TX_DESC; i++) {
1036 struct sk_buff *skb = dev->tx_skbs[i];
1037 dev->tx_skbs[i] = NULL;
1038 if (skb) {
c69fda4e 1039 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1da177e4
LT
1040 pci_unmap_single(dev->pci_dev,
1041 desc_addr_get(desc + DESC_BUFPTR),
1042 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1043 PCI_DMA_TODEVICE);
1044 dev_kfree_skb_irq(skb);
1045 atomic_dec(&dev->nr_tx_skbs);
1046 }
1047 }
1048
1049 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1050}
1051
1052/* transmit routine. This code relies on the network layer serializing
1053 * its calls in, but will run happily in parallel with the interrupt
1054 * handler. This code currently has provisions for fragmenting tx buffers
1055 * while trying to track down a bug in either the zero copy code or
1056 * the tx fifo (hence the MAX_FRAG_LEN).
1057 */
61357325
SH
1058static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
1059 struct net_device *ndev)
1da177e4
LT
1060{
1061 struct ns83820 *dev = PRIV(ndev);
1062 u32 free_idx, cmdsts, extsts;
1063 int nr_free, nr_frags;
1064 unsigned tx_done_idx, last_idx;
1065 dma_addr_t buf;
1066 unsigned len;
1067 skb_frag_t *frag;
1068 int stopped = 0;
1069 int do_intr = 0;
c69fda4e 1070 volatile __le32 *first_desc;
1da177e4
LT
1071
1072 dprintk("ns83820_hard_start_xmit\n");
1073
1074 nr_frags = skb_shinfo(skb)->nr_frags;
1075again:
1076 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1077 netif_stop_queue(ndev);
1078 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
5b548140 1079 return NETDEV_TX_BUSY;
1da177e4
LT
1080 netif_start_queue(ndev);
1081 }
1082
1083 last_idx = free_idx = dev->tx_free_idx;
1084 tx_done_idx = dev->tx_done_idx;
1085 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1086 nr_free -= 1;
1087 if (nr_free <= nr_frags) {
1088 dprintk("stop_queue - not enough(%p)\n", ndev);
1089 netif_stop_queue(ndev);
1090
1091 /* Check again: we may have raced with a tx done irq */
1092 if (dev->tx_done_idx != tx_done_idx) {
1093 dprintk("restart queue(%p)\n", ndev);
1094 netif_start_queue(ndev);
1095 goto again;
1096 }
5b548140 1097 return NETDEV_TX_BUSY;
1da177e4
LT
1098 }
1099
1100 if (free_idx == dev->tx_intr_idx) {
1101 do_intr = 1;
1102 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1103 }
1104
1105 nr_free -= nr_frags;
1106 if (nr_free < MIN_TX_DESC_FREE) {
1107 dprintk("stop_queue - last entry(%p)\n", ndev);
1108 netif_stop_queue(ndev);
1109 stopped = 1;
1110 }
1111
1112 frag = skb_shinfo(skb)->frags;
1113 if (!nr_frags)
1114 frag = NULL;
1115 extsts = 0;
84fa7933 1116 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 1117 extsts |= EXTSTS_IPPKT;
eddc9ec5 1118 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1da177e4 1119 extsts |= EXTSTS_TCPPKT;
eddc9ec5 1120 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1da177e4
LT
1121 extsts |= EXTSTS_UDPPKT;
1122 }
1123
1124#ifdef NS83820_VLAN_ACCEL_SUPPORT
1125 if(vlan_tx_tag_present(skb)) {
1126 /* fetch the vlan tag info out of the
25985edc 1127 * ancillary data if the vlan code
1da177e4
LT
1128 * is using hw vlan acceleration
1129 */
1130 short tag = vlan_tx_tag_get(skb);
1131 extsts |= (EXTSTS_VPKT | htons(tag));
1132 }
1133#endif
1134
1135 len = skb->len;
1136 if (nr_frags)
1137 len -= skb->data_len;
1138 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1139
1140 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1141
1142 for (;;) {
c69fda4e 1143 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1da177e4
LT
1144
1145 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1146 (unsigned long long)buf);
1147 last_idx = free_idx;
1148 free_idx = (free_idx + 1) % NR_TX_DESC;
1149 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1150 desc_addr_set(desc + DESC_BUFPTR, buf);
1151 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1152
c16ef1ce 1153 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1da177e4
LT
1154 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1155 cmdsts |= len;
1156 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1157
1da177e4
LT
1158 if (!nr_frags)
1159 break;
1160
bc516c8f 1161 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
9e903e08 1162 skb_frag_size(frag), DMA_TO_DEVICE);
1da177e4
LT
1163 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1164 (long long)buf, (long) page_to_pfn(frag->page),
1165 frag->page_offset);
9e903e08 1166 len = skb_frag_size(frag);
1da177e4
LT
1167 frag++;
1168 nr_frags--;
1169 }
1170 dprintk("done pkt\n");
1171
1172 spin_lock_irq(&dev->tx_lock);
1173 dev->tx_skbs[last_idx] = skb;
1174 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1175 dev->tx_free_idx = free_idx;
1176 atomic_inc(&dev->nr_tx_skbs);
1177 spin_unlock_irq(&dev->tx_lock);
1178
1179 kick_tx(dev);
1180
1181 /* Check again: we may have raced with a tx done irq */
1182 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1183 netif_start_queue(ndev);
1184
cdd0db05 1185 return NETDEV_TX_OK;
1da177e4
LT
1186}
1187
1188static void ns83820_update_stats(struct ns83820 *dev)
1189{
e929bc33 1190 struct net_device *ndev = dev->ndev;
1da177e4
LT
1191 u8 __iomem *base = dev->base;
1192
1193 /* the DP83820 will freeze counters, so we need to read all of them */
e929bc33
KV
1194 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1195 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1196 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1197 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1198 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1199 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1200 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1201 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1202 /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
1203 /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
1204 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1da177e4
LT
1205}
1206
1207static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1208{
1209 struct ns83820 *dev = PRIV(ndev);
1210
1211 /* somewhat overkill */
1212 spin_lock_irq(&dev->misc_lock);
1213 ns83820_update_stats(dev);
1214 spin_unlock_irq(&dev->misc_lock);
1215
e929bc33 1216 return &ndev->stats;
1da177e4
LT
1217}
1218
10096974
JG
1219/* Let ethtool retrieve info */
1220static int ns83820_get_settings(struct net_device *ndev,
1221 struct ethtool_cmd *cmd)
1222{
1223 struct ns83820 *dev = PRIV(ndev);
1224 u32 cfg, tanar, tbicr;
10096974
JG
1225 int fullduplex = 0;
1226
1227 /*
1228 * Here's the list of available ethtool commands from other drivers:
1229 * cmd->advertising =
70739497 1230 * ethtool_cmd_speed_set(cmd, ...)
10096974
JG
1231 * cmd->duplex =
1232 * cmd->port = 0;
1233 * cmd->phy_address =
1234 * cmd->transceiver = 0;
1235 * cmd->autoneg =
1236 * cmd->maxtxpkt = 0;
1237 * cmd->maxrxpkt = 0;
1238 */
1239
1240 /* read current configuration */
1241 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1242 tanar = readl(dev->base + TANAR);
1243 tbicr = readl(dev->base + TBICR);
1244
7457e911 1245 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
10096974
JG
1246
1247 cmd->supported = SUPPORTED_Autoneg;
1248
10096974 1249 if (dev->CFG_cache & CFG_TBI_EN) {
3c083edc 1250 /* we have optical interface */
10096974
JG
1251 cmd->supported |= SUPPORTED_1000baseT_Half |
1252 SUPPORTED_1000baseT_Full |
1253 SUPPORTED_FIBRE;
1254 cmd->port = PORT_FIBRE;
3c083edc
DK
1255 } else {
1256 /* we have copper */
1257 cmd->supported |= SUPPORTED_10baseT_Half |
1258 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
1259 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
1260 SUPPORTED_1000baseT_Full |
1261 SUPPORTED_MII;
1262 cmd->port = PORT_MII;
1263 }
10096974
JG
1264
1265 cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1266 switch (cfg / CFG_SPDSTS0 & 3) {
1267 case 2:
70739497 1268 ethtool_cmd_speed_set(cmd, SPEED_1000);
10096974
JG
1269 break;
1270 case 1:
70739497 1271 ethtool_cmd_speed_set(cmd, SPEED_100);
10096974
JG
1272 break;
1273 default:
70739497 1274 ethtool_cmd_speed_set(cmd, SPEED_10);
10096974
JG
1275 break;
1276 }
a5d31e0f
DK
1277 cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1278 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
10096974
JG
1279 return 0;
1280}
1281
1282/* Let ethool change settings*/
1283static int ns83820_set_settings(struct net_device *ndev,
1284 struct ethtool_cmd *cmd)
1285{
1286 struct ns83820 *dev = PRIV(ndev);
1287 u32 cfg, tanar;
1288 int have_optical = 0;
1289 int fullduplex = 0;
1290
1291 /* read current configuration */
1292 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1293 tanar = readl(dev->base + TANAR);
1294
1295 if (dev->CFG_cache & CFG_TBI_EN) {
1296 /* we have optical */
1297 have_optical = 1;
1298 fullduplex = (tanar & TANAR_FULL_DUP);
1299
1300 } else {
1301 /* we have copper */
1302 fullduplex = cfg & CFG_DUPSTS;
1303 }
1304
1305 spin_lock_irq(&dev->misc_lock);
1306 spin_lock(&dev->tx_lock);
1307
1308 /* Set duplex */
1309 if (cmd->duplex != fullduplex) {
1310 if (have_optical) {
1311 /*set full duplex*/
1312 if (cmd->duplex == DUPLEX_FULL) {
1313 /* force full duplex */
1314 writel(readl(dev->base + TXCFG)
1315 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1316 dev->base + TXCFG);
1317 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1318 dev->base + RXCFG);
1319 /* Light up full duplex LED */
1320 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1321 dev->base + GPIOR);
1322 } else {
1323 /*TODO: set half duplex */
1324 }
1325
1326 } else {
1327 /*we have copper*/
1328 /* TODO: Set duplex for copper cards */
1329 }
1330 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1331 ndev->name);
1332 }
1333
1334 /* Set autonegotiation */
1335 if (1) {
1336 if (cmd->autoneg == AUTONEG_ENABLE) {
1337 /* restart auto negotiation */
1338 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1339 dev->base + TBICR);
1340 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1341 dev->linkstate = LINK_AUTONEGOTIATE;
1342
1343 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1344 ndev->name);
1345 } else {
1346 /* disable auto negotiation */
1347 writel(0x00000000, dev->base + TBICR);
1348 }
1349
1350 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1351 cmd->autoneg ? "ENABLED" : "DISABLED");
1352 }
1353
1354 phy_intr(ndev);
1355 spin_unlock(&dev->tx_lock);
1356 spin_unlock_irq(&dev->misc_lock);
1357
1358 return 0;
1359}
1360/* end ethtool get/set support -df */
1361
1da177e4
LT
1362static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1363{
1364 struct ns83820 *dev = PRIV(ndev);
68aad78c
RJ
1365 strlcpy(info->driver, "ns83820", sizeof(info->driver));
1366 strlcpy(info->version, VERSION, sizeof(info->version));
1367 strlcpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1da177e4
LT
1368}
1369
1370static u32 ns83820_get_link(struct net_device *ndev)
1371{
1372 struct ns83820 *dev = PRIV(ndev);
1373 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1374 return cfg & CFG_LNKSTS ? 1 : 0;
1375}
1376
7282d491 1377static const struct ethtool_ops ops = {
10096974
JG
1378 .get_settings = ns83820_get_settings,
1379 .set_settings = ns83820_set_settings,
1380 .get_drvinfo = ns83820_get_drvinfo,
1381 .get_link = ns83820_get_link
1da177e4
LT
1382};
1383
1a9f28c8
DK
1384static inline void ns83820_disable_interrupts(struct ns83820 *dev)
1385{
1386 writel(0, dev->base + IMR);
1387 writel(0, dev->base + IER);
1388 readl(dev->base + IER);
1389}
1390
3a10cceb 1391/* this function is called in irq context from the ISR */
1da177e4
LT
1392static void ns83820_mib_isr(struct ns83820 *dev)
1393{
3a10cceb
IM
1394 unsigned long flags;
1395 spin_lock_irqsave(&dev->misc_lock, flags);
1da177e4 1396 ns83820_update_stats(dev);
3a10cceb 1397 spin_unlock_irqrestore(&dev->misc_lock, flags);
1da177e4
LT
1398}
1399
1400static void ns83820_do_isr(struct net_device *ndev, u32 isr);
7d12e780 1401static irqreturn_t ns83820_irq(int foo, void *data)
1da177e4
LT
1402{
1403 struct net_device *ndev = data;
1404 struct ns83820 *dev = PRIV(ndev);
1405 u32 isr;
1406 dprintk("ns83820_irq(%p)\n", ndev);
1407
1408 dev->ihr = 0;
1409
1410 isr = readl(dev->base + ISR);
1411 dprintk("irq: %08x\n", isr);
1412 ns83820_do_isr(ndev, isr);
1413 return IRQ_HANDLED;
1414}
1415
1416static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1417{
1418 struct ns83820 *dev = PRIV(ndev);
3a10cceb
IM
1419 unsigned long flags;
1420
1da177e4
LT
1421#ifdef DEBUG
1422 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1423 Dprintk("odd isr? 0x%08x\n", isr);
1424#endif
1425
1426 if (ISR_RXIDLE & isr) {
1427 dev->rx_info.idle = 1;
1428 Dprintk("oh dear, we are idle\n");
1429 ns83820_rx_kick(ndev);
1430 }
1431
1432 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1433 prefetch(dev->rx_info.next_rx_desc);
1434
3a10cceb 1435 spin_lock_irqsave(&dev->misc_lock, flags);
1da177e4
LT
1436 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1437 writel(dev->IMR_cache, dev->base + IMR);
3a10cceb 1438 spin_unlock_irqrestore(&dev->misc_lock, flags);
1da177e4
LT
1439
1440 tasklet_schedule(&dev->rx_tasklet);
1441 //rx_irq(ndev);
1442 //writel(4, dev->base + IHR);
1443 }
1444
1445 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1446 ns83820_rx_kick(ndev);
1447
1448 if (unlikely(ISR_RXSOVR & isr)) {
1449 //printk("overrun: rxsovr\n");
e929bc33 1450 ndev->stats.rx_fifo_errors++;
1da177e4
LT
1451 }
1452
1453 if (unlikely(ISR_RXORN & isr)) {
1454 //printk("overrun: rxorn\n");
e929bc33 1455 ndev->stats.rx_fifo_errors++;
1da177e4
LT
1456 }
1457
1458 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1459 writel(CR_RXE, dev->base + CR);
1460
1461 if (ISR_TXIDLE & isr) {
1462 u32 txdp;
1463 txdp = readl(dev->base + TXDP);
1464 dprintk("txdp: %08x\n", txdp);
1465 txdp -= dev->tx_phy_descs;
1466 dev->tx_idx = txdp / (DESC_SIZE * 4);
1467 if (dev->tx_idx >= NR_TX_DESC) {
1468 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1469 dev->tx_idx = 0;
1470 }
1471 /* The may have been a race between a pci originated read
6aa20a22
JG
1472 * and the descriptor update from the cpu. Just in case,
1473 * kick the transmitter if the hardware thinks it is on a
1da177e4
LT
1474 * different descriptor than we are.
1475 */
1476 if (dev->tx_idx != dev->tx_free_idx)
1477 kick_tx(dev);
1478 }
1479
1480 /* Defer tx ring processing until more than a minimum amount of
1481 * work has accumulated
1482 */
1483 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
3a10cceb 1484 spin_lock_irqsave(&dev->tx_lock, flags);
1da177e4 1485 do_tx_done(ndev);
3a10cceb 1486 spin_unlock_irqrestore(&dev->tx_lock, flags);
1da177e4
LT
1487
1488 /* Disable TxOk if there are no outstanding tx packets.
1489 */
1490 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1491 (dev->IMR_cache & ISR_TXOK)) {
3a10cceb 1492 spin_lock_irqsave(&dev->misc_lock, flags);
1da177e4
LT
1493 dev->IMR_cache &= ~ISR_TXOK;
1494 writel(dev->IMR_cache, dev->base + IMR);
3a10cceb 1495 spin_unlock_irqrestore(&dev->misc_lock, flags);
1da177e4
LT
1496 }
1497 }
1498
1499 /* The TxIdle interrupt can come in before the transmit has
1500 * completed. Normally we reap packets off of the combination
6aa20a22
JG
1501 * of TxDesc and TxIdle and leave TxOk disabled (since it
1502 * occurs on every packet), but when no further irqs of this
1da177e4
LT
1503 * nature are expected, we must enable TxOk.
1504 */
1505 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
3a10cceb 1506 spin_lock_irqsave(&dev->misc_lock, flags);
1da177e4
LT
1507 dev->IMR_cache |= ISR_TXOK;
1508 writel(dev->IMR_cache, dev->base + IMR);
3a10cceb 1509 spin_unlock_irqrestore(&dev->misc_lock, flags);
1da177e4
LT
1510 }
1511
1512 /* MIB interrupt: one of the statistics counters is about to overflow */
1513 if (unlikely(ISR_MIB & isr))
1514 ns83820_mib_isr(dev);
1515
1516 /* PHY: Link up/down/negotiation state change */
1517 if (unlikely(ISR_PHY & isr))
1518 phy_intr(ndev);
1519
1520#if 0 /* Still working on the interrupt mitigation strategy */
1521 if (dev->ihr)
1522 writel(dev->ihr, dev->base + IHR);
1523#endif
1524}
1525
1526static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1527{
1528 Dprintk("resetting chip...\n");
1529 writel(which, dev->base + CR);
1530 do {
1531 schedule();
1532 } while (readl(dev->base + CR) & which);
1533 Dprintk("okay!\n");
1534}
1535
1536static int ns83820_stop(struct net_device *ndev)
1537{
1538 struct ns83820 *dev = PRIV(ndev);
1539
1540 /* FIXME: protect against interrupt handler? */
1541 del_timer_sync(&dev->tx_watchdog);
1542
1a9f28c8 1543 ns83820_disable_interrupts(dev);
1da177e4
LT
1544
1545 dev->rx_info.up = 0;
1546 synchronize_irq(dev->pci_dev->irq);
1547
1548 ns83820_do_reset(dev, CR_RST);
1549
1550 synchronize_irq(dev->pci_dev->irq);
1551
1552 spin_lock_irq(&dev->misc_lock);
1553 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1554 spin_unlock_irq(&dev->misc_lock);
1555
1556 ns83820_cleanup_rx(dev);
1557 ns83820_cleanup_tx(dev);
1558
1559 return 0;
1560}
1561
1562static void ns83820_tx_timeout(struct net_device *ndev)
1563{
1564 struct ns83820 *dev = PRIV(ndev);
c69fda4e
AV
1565 u32 tx_done_idx;
1566 __le32 *desc;
1da177e4
LT
1567 unsigned long flags;
1568
3a10cceb 1569 spin_lock_irqsave(&dev->tx_lock, flags);
1da177e4
LT
1570
1571 tx_done_idx = dev->tx_done_idx;
1572 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1573
1574 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1575 ndev->name,
1576 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1577
1578#if defined(DEBUG)
1579 {
1580 u32 isr;
1581 isr = readl(dev->base + ISR);
1582 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1583 ns83820_do_isr(ndev, isr);
1584 }
1585#endif
1586
1587 do_tx_done(ndev);
1588
1589 tx_done_idx = dev->tx_done_idx;
1590 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1591
1592 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1593 ndev->name,
1594 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1595
3a10cceb 1596 spin_unlock_irqrestore(&dev->tx_lock, flags);
1da177e4
LT
1597}
1598
1599static void ns83820_tx_watch(unsigned long data)
1600{
1601 struct net_device *ndev = (void *)data;
1602 struct ns83820 *dev = PRIV(ndev);
1603
1604#if defined(DEBUG)
1605 printk("ns83820_tx_watch: %u %u %d\n",
1606 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1607 );
1608#endif
1609
cdd0db05 1610 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1da177e4
LT
1611 dev->tx_done_idx != dev->tx_free_idx) {
1612 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1613 ndev->name,
1614 dev->tx_done_idx, dev->tx_free_idx,
1615 atomic_read(&dev->nr_tx_skbs));
1616 ns83820_tx_timeout(ndev);
1617 }
1618
1619 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1620}
1621
1622static int ns83820_open(struct net_device *ndev)
1623{
1624 struct ns83820 *dev = PRIV(ndev);
1625 unsigned i;
1626 u32 desc;
1627 int ret;
1628
1629 dprintk("ns83820_open\n");
1630
1631 writel(0, dev->base + PQCR);
1632
1633 ret = ns83820_setup_rx(ndev);
1634 if (ret)
1635 goto failed;
1636
1637 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1638 for (i=0; i<NR_TX_DESC; i++) {
1639 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1640 = cpu_to_le32(
1641 dev->tx_phy_descs
1642 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1643 }
1644
1645 dev->tx_idx = 0;
1646 dev->tx_done_idx = 0;
1647 desc = dev->tx_phy_descs;
1648 writel(0, dev->base + TXDP_HI);
1649 writel(desc, dev->base + TXDP);
1650
1651 init_timer(&dev->tx_watchdog);
1652 dev->tx_watchdog.data = (unsigned long)ndev;
1653 dev->tx_watchdog.function = ns83820_tx_watch;
1654 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1655
1656 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1657
1658 return 0;
1659
1660failed:
1661 ns83820_stop(ndev);
1662 return ret;
1663}
1664
1665static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1666{
1667 unsigned i;
1668 for (i=0; i<3; i++) {
1669 u32 data;
48888cc6 1670
1da177e4
LT
1671 /* Read from the perfect match memory: this is loaded by
1672 * the chip from the EEPROM via the EELOAD self test.
1673 */
1674 writel(i*2, dev->base + RFCR);
1675 data = readl(dev->base + RFDR);
48888cc6 1676
1da177e4
LT
1677 *mac++ = data;
1678 *mac++ = data >> 8;
1679 }
1680}
1681
1682static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1683{
1684 if (new_mtu > RX_BUF_SIZE)
1685 return -EINVAL;
1686 ndev->mtu = new_mtu;
1687 return 0;
1688}
1689
1690static void ns83820_set_multicast(struct net_device *ndev)
1691{
1692 struct ns83820 *dev = PRIV(ndev);
1693 u8 __iomem *rfcr = dev->base + RFCR;
1694 u32 and_mask = 0xffffffff;
1695 u32 or_mask = 0;
1696 u32 val;
1697
1698 if (ndev->flags & IFF_PROMISC)
1699 or_mask |= RFCR_AAU | RFCR_AAM;
1700 else
1701 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1702
4cd24eaf 1703 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1da177e4
LT
1704 or_mask |= RFCR_AAM;
1705 else
1706 and_mask &= ~RFCR_AAM;
1707
1708 spin_lock_irq(&dev->misc_lock);
1709 val = (readl(rfcr) & and_mask) | or_mask;
1710 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1711 writel(val & ~RFCR_RFEN, rfcr);
1712 writel(val, rfcr);
1713 spin_unlock_irq(&dev->misc_lock);
1714}
1715
1716static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1717{
1718 struct ns83820 *dev = PRIV(ndev);
1719 int timed_out = 0;
ff5688ae 1720 unsigned long start;
1da177e4
LT
1721 u32 status;
1722 int loops = 0;
1723
1724 dprintk("%s: start %s\n", ndev->name, name);
1725
1726 start = jiffies;
1727
1728 writel(enable, dev->base + PTSCR);
1729 for (;;) {
1730 loops++;
1731 status = readl(dev->base + PTSCR);
1732 if (!(status & enable))
1733 break;
1734 if (status & done)
1735 break;
1736 if (status & fail)
1737 break;
ff5688ae 1738 if (time_after_eq(jiffies, start + HZ)) {
1da177e4
LT
1739 timed_out = 1;
1740 break;
1741 }
3173c890 1742 schedule_timeout_uninterruptible(1);
1da177e4
LT
1743 }
1744
1745 if (status & fail)
1746 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1747 ndev->name, name, status, fail);
1748 else if (timed_out)
1749 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1750 ndev->name, name, status);
1751
1752 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1753}
1754
1755#ifdef PHY_CODE_IS_FINISHED
1756static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1757{
1758 /* drive MDC low */
1759 dev->MEAR_cache &= ~MEAR_MDC;
1760 writel(dev->MEAR_cache, dev->base + MEAR);
1761 readl(dev->base + MEAR);
1762
1763 /* enable output, set bit */
1764 dev->MEAR_cache |= MEAR_MDDIR;
1765 if (bit)
1766 dev->MEAR_cache |= MEAR_MDIO;
1767 else
1768 dev->MEAR_cache &= ~MEAR_MDIO;
1769
1770 /* set the output bit */
1771 writel(dev->MEAR_cache, dev->base + MEAR);
1772 readl(dev->base + MEAR);
1773
1774 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1775 udelay(1);
1776
1777 /* drive MDC high causing the data bit to be latched */
1778 dev->MEAR_cache |= MEAR_MDC;
1779 writel(dev->MEAR_cache, dev->base + MEAR);
1780 readl(dev->base + MEAR);
1781
1782 /* Wait again... */
1783 udelay(1);
1784}
1785
1786static int ns83820_mii_read_bit(struct ns83820 *dev)
1787{
1788 int bit;
1789
1790 /* drive MDC low, disable output */
1791 dev->MEAR_cache &= ~MEAR_MDC;
1792 dev->MEAR_cache &= ~MEAR_MDDIR;
1793 writel(dev->MEAR_cache, dev->base + MEAR);
1794 readl(dev->base + MEAR);
1795
1796 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1797 udelay(1);
1798
1799 /* drive MDC high causing the data bit to be latched */
1800 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1801 dev->MEAR_cache |= MEAR_MDC;
1802 writel(dev->MEAR_cache, dev->base + MEAR);
1803
1804 /* Wait again... */
1805 udelay(1);
1806
1807 return bit;
1808}
1809
1810static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1811{
1812 unsigned data = 0;
1813 int i;
1814
1815 /* read some garbage so that we eventually sync up */
1816 for (i=0; i<64; i++)
1817 ns83820_mii_read_bit(dev);
1818
1819 ns83820_mii_write_bit(dev, 0); /* start */
1820 ns83820_mii_write_bit(dev, 1);
1821 ns83820_mii_write_bit(dev, 1); /* opcode read */
1822 ns83820_mii_write_bit(dev, 0);
1823
1824 /* write out the phy address: 5 bits, msb first */
1825 for (i=0; i<5; i++)
1826 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1827
1828 /* write out the register address, 5 bits, msb first */
1829 for (i=0; i<5; i++)
1830 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1831
1832 ns83820_mii_read_bit(dev); /* turn around cycles */
1833 ns83820_mii_read_bit(dev);
1834
1835 /* read in the register data, 16 bits msb first */
1836 for (i=0; i<16; i++) {
1837 data <<= 1;
1838 data |= ns83820_mii_read_bit(dev);
1839 }
1840
1841 return data;
1842}
1843
1844static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1845{
1846 int i;
1847
1848 /* read some garbage so that we eventually sync up */
1849 for (i=0; i<64; i++)
1850 ns83820_mii_read_bit(dev);
1851
1852 ns83820_mii_write_bit(dev, 0); /* start */
1853 ns83820_mii_write_bit(dev, 1);
1854 ns83820_mii_write_bit(dev, 0); /* opcode read */
1855 ns83820_mii_write_bit(dev, 1);
1856
1857 /* write out the phy address: 5 bits, msb first */
1858 for (i=0; i<5; i++)
1859 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1860
1861 /* write out the register address, 5 bits, msb first */
1862 for (i=0; i<5; i++)
1863 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1864
1865 ns83820_mii_read_bit(dev); /* turn around cycles */
1866 ns83820_mii_read_bit(dev);
1867
1868 /* read in the register data, 16 bits msb first */
1869 for (i=0; i<16; i++)
1870 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1871
1872 return data;
1873}
1874
1875static void ns83820_probe_phy(struct net_device *ndev)
1876{
1877 struct ns83820 *dev = PRIV(ndev);
1878 static int first;
1879 int i;
1880#define MII_PHYIDR1 0x02
1881#define MII_PHYIDR2 0x03
1882
1883#if 0
1884 if (!first) {
1885 unsigned tmp;
1886 ns83820_mii_read_reg(dev, 1, 0x09);
1887 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1888
1889 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1890 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1891 udelay(1300);
1892 ns83820_mii_read_reg(dev, 1, 0x09);
1893 }
1894#endif
1895 first = 1;
1896
1897 for (i=1; i<2; i++) {
1898 int j;
1899 unsigned a, b;
1900 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1901 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1902
1903 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1904 // ndev->name, i, a, b);
1905
1906 for (j=0; j<0x16; j+=4) {
1907 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1908 ndev->name, j,
1909 ns83820_mii_read_reg(dev, i, 0 + j),
1910 ns83820_mii_read_reg(dev, i, 1 + j),
1911 ns83820_mii_read_reg(dev, i, 2 + j),
1912 ns83820_mii_read_reg(dev, i, 3 + j)
1913 );
1914 }
1915 }
1916 {
1917 unsigned a, b;
1918 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1919 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1920 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1921 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1922
1923 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1924 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1925 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1926 dprintk("version: 0x%04x 0x%04x\n", a, b);
1927 }
1928}
1929#endif
1930
6557d7b8
SH
1931static const struct net_device_ops netdev_ops = {
1932 .ndo_open = ns83820_open,
1933 .ndo_stop = ns83820_stop,
1934 .ndo_start_xmit = ns83820_hard_start_xmit,
1935 .ndo_get_stats = ns83820_get_stats,
1936 .ndo_change_mtu = ns83820_change_mtu,
afc4b13d 1937 .ndo_set_rx_mode = ns83820_set_multicast,
6557d7b8 1938 .ndo_validate_addr = eth_validate_addr,
a4f676b8 1939 .ndo_set_mac_address = eth_mac_addr,
6557d7b8
SH
1940 .ndo_tx_timeout = ns83820_tx_timeout,
1941};
1942
6980cbe4 1943static int ns83820_init_one(struct pci_dev *pci_dev,
1dd06ae8 1944 const struct pci_device_id *id)
1da177e4
LT
1945{
1946 struct net_device *ndev;
1947 struct ns83820 *dev;
1948 long addr;
1949 int err;
1950 int using_dac = 0;
1951
1952 /* See if we can set the dma mask early on; failure is fatal. */
910638ae 1953 if (sizeof(dma_addr_t) == 8 &&
6a35528a 1954 !pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
1da177e4 1955 using_dac = 1;
284901a9 1956 } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
1da177e4
LT
1957 using_dac = 0;
1958 } else {
9b91cf9d 1959 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1da177e4
LT
1960 return -ENODEV;
1961 }
1962
1963 ndev = alloc_etherdev(sizeof(struct ns83820));
1da177e4 1964 err = -ENOMEM;
1956cc52 1965 if (!ndev)
1da177e4
LT
1966 goto out;
1967
1956cc52 1968 dev = PRIV(ndev);
d14e37e1
AB
1969 dev->ndev = ndev;
1970
1da177e4
LT
1971 spin_lock_init(&dev->rx_info.lock);
1972 spin_lock_init(&dev->tx_lock);
1973 spin_lock_init(&dev->misc_lock);
1974 dev->pci_dev = pci_dev;
1975
1da177e4
LT
1976 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1977
c4028958 1978 INIT_WORK(&dev->tq_refill, queue_refill);
1da177e4
LT
1979 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1980
1981 err = pci_enable_device(pci_dev);
1982 if (err) {
9b91cf9d 1983 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1da177e4
LT
1984 goto out_free;
1985 }
1986
1987 pci_set_master(pci_dev);
1988 addr = pci_resource_start(pci_dev, 1);
1989 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1990 dev->tx_descs = pci_alloc_consistent(pci_dev,
1991 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1992 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1993 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1994 err = -ENOMEM;
1995 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1996 goto out_disable;
1997
1998 dprintk("%p: %08lx %p: %08lx\n",
1999 dev->tx_descs, (long)dev->tx_phy_descs,
2000 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
2001
1a9f28c8 2002 ns83820_disable_interrupts(dev);
1da177e4
LT
2003
2004 dev->IMR_cache = 0;
2005
1fb9df5d 2006 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1da177e4
LT
2007 DRV_NAME, ndev);
2008 if (err) {
9b91cf9d 2009 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
2e8a538d 2010 pci_dev->irq, err);
1da177e4
LT
2011 goto out_disable;
2012 }
2013
2014 /*
2015 * FIXME: we are holding rtnl_lock() over obscenely long area only
2016 * because some of the setup code uses dev->name. It's Wrong(tm) -
2017 * we should be using driver-specific names for all that stuff.
2018 * For now that will do, but we really need to come back and kill
2019 * most of the dev_alloc_name() users later.
2020 */
2021 rtnl_lock();
2022 err = dev_alloc_name(ndev, ndev->name);
2023 if (err < 0) {
9b91cf9d 2024 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1da177e4
LT
2025 goto out_free_irq;
2026 }
2027
2028 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2029 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2030 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
2031
6557d7b8 2032 ndev->netdev_ops = &netdev_ops;
7ad24ea4 2033 ndev->ethtool_ops = &ops;
1da177e4
LT
2034 ndev->watchdog_timeo = 5 * HZ;
2035 pci_set_drvdata(pci_dev, ndev);
2036
2037 ns83820_do_reset(dev, CR_RST);
2038
2039 /* Must reset the ram bist before running it */
2040 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2041 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
2042 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
2043 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
2044 PTSCR_EEBIST_FAIL);
2045 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2046
2047 /* I love config registers */
2048 dev->CFG_cache = readl(dev->base + CFG);
2049
2050 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2051 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2052 ndev->name);
2053 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2054 if (!(dev->CFG_cache & CFG_DATA64_EN))
2055 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2056 ndev->name);
2057 } else
2058 dev->CFG_cache &= ~(CFG_DATA64_EN);
2059
2060 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2061 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2062 CFG_M64ADDR);
2063 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2064 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2065 dev->CFG_cache |= CFG_REQALG;
2066 dev->CFG_cache |= CFG_POW;
2067 dev->CFG_cache |= CFG_TMRTEST;
2068
2069 /* When compiled with 64 bit addressing, we must always enable
2070 * the 64 bit descriptor format.
2071 */
6aa20a22 2072 if (sizeof(dma_addr_t) == 8)
c16ef1ce 2073 dev->CFG_cache |= CFG_M64ADDR;
1da177e4
LT
2074 if (using_dac)
2075 dev->CFG_cache |= CFG_T64ADDR;
2076
2077 /* Big endian mode does not seem to do what the docs suggest */
2078 dev->CFG_cache &= ~CFG_BEM;
2079
2080 /* setup optical transceiver if we have one */
2081 if (dev->CFG_cache & CFG_TBI_EN) {
2082 printk(KERN_INFO "%s: enabling optical transceiver\n",
2083 ndev->name);
2084 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2085
2086 /* setup auto negotiation feature advertisement */
2087 writel(readl(dev->base + TANAR)
2088 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2089 dev->base + TANAR);
2090
2091 /* start auto negotiation */
2092 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2093 dev->base + TBICR);
2094 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2095 dev->linkstate = LINK_AUTONEGOTIATE;
2096
2097 dev->CFG_cache |= CFG_MODE_1000;
2098 }
2099
2100 writel(dev->CFG_cache, dev->base + CFG);
2101 dprintk("CFG: %08x\n", dev->CFG_cache);
2102
2103 if (reset_phy) {
2104 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2105 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2106 msleep(10);
2107 writel(dev->CFG_cache, dev->base + CFG);
2108 }
2109
6aa20a22 2110#if 0 /* Huh? This sets the PCI latency register. Should be done via
1da177e4
LT
2111 * the PCI layer. FIXME.
2112 */
2113 if (readl(dev->base + SRR))
2114 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2115#endif
2116
2117 /* Note! The DMA burst size interacts with packet
2118 * transmission, such that the largest packet that
2119 * can be transmitted is 8192 - FLTH - burst size.
2120 * If only the transmit fifo was larger...
2121 */
6aa20a22 2122 /* Ramit : 1024 DMA is not a good idea, it ends up banging
1da177e4
LT
2123 * some DELL and COMPAQ SMP systems */
2124 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2125 | ((1600 / 32) * 0x100),
2126 dev->base + TXCFG);
2127
2128 /* Flush the interrupt holdoff timer */
2129 writel(0x000, dev->base + IHR);
2130 writel(0x100, dev->base + IHR);
2131 writel(0x000, dev->base + IHR);
2132
2133 /* Set Rx to full duplex, don't accept runt, errored, long or length
2134 * range errored packets. Use 512 byte DMA.
2135 */
6aa20a22
JG
2136 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2137 * some DELL and COMPAQ SMP systems
1da177e4
LT
2138 * Turn on ALP, only we are accpeting Jumbo Packets */
2139 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2140 | RXCFG_STRIPCRC
2141 //| RXCFG_ALP
2142 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2143
2144 /* Disable priority queueing */
2145 writel(0, dev->base + PQCR);
2146
2147 /* Enable IP checksum validation and detetion of VLAN headers.
2148 * Note: do not set the reject options as at least the 0x102
2149 * revision of the chip does not properly accept IP fragments
2150 * at least for UDP.
2151 */
2152 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2153 * the MAC it calculates the packetsize AFTER stripping the VLAN
2154 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2155 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2156 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2157 * it discrards it!. These guys......
2158 * also turn on tag stripping if hardware acceleration is enabled
2159 */
2160#ifdef NS83820_VLAN_ACCEL_SUPPORT
6aa20a22 2161#define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
1da177e4
LT
2162#else
2163#define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2164#endif
2165 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2166
2167 /* Enable per-packet TCP/UDP/IP checksumming
2168 * and per packet vlan tag insertion if
2169 * vlan hardware acceleration is enabled
2170 */
2171#ifdef NS83820_VLAN_ACCEL_SUPPORT
2172#define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2173#else
2174#define VTCR_INIT_VALUE VTCR_PPCHK
2175#endif
2176 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2177
2178 /* Ramit : Enable async and sync pause frames */
2179 /* writel(0, dev->base + PCR); */
2180 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2181 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2182 dev->base + PCR);
2183
2184 /* Disable Wake On Lan */
2185 writel(0, dev->base + WCSR);
2186
2187 ns83820_getmac(dev, ndev->dev_addr);
2188
2189 /* Yes, we support dumb IP checksum on transmit */
2190 ndev->features |= NETIF_F_SG;
2191 ndev->features |= NETIF_F_IP_CSUM;
2192
2193#ifdef NS83820_VLAN_ACCEL_SUPPORT
2194 /* We also support hardware vlan acceleration */
f646968f 2195 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1da177e4
LT
2196#endif
2197
2198 if (using_dac) {
2199 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2200 ndev->name);
2201 ndev->features |= NETIF_F_HIGHDMA;
2202 }
2203
e174961c 2204 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
1da177e4
LT
2205 ndev->name,
2206 (unsigned)readl(dev->base + SRR) >> 8,
2207 (unsigned)readl(dev->base + SRR) & 0xff,
e174961c 2208 ndev->dev_addr, addr, pci_dev->irq,
1da177e4
LT
2209 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2210 );
2211
2212#ifdef PHY_CODE_IS_FINISHED
2213 ns83820_probe_phy(ndev);
2214#endif
2215
2216 err = register_netdevice(ndev);
2217 if (err) {
2218 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2219 goto out_cleanup;
2220 }
2221 rtnl_unlock();
2222
2223 return 0;
2224
2225out_cleanup:
1a9f28c8 2226 ns83820_disable_interrupts(dev); /* paranoia */
1da177e4
LT
2227out_free_irq:
2228 rtnl_unlock();
2229 free_irq(pci_dev->irq, ndev);
2230out_disable:
2231 if (dev->base)
2232 iounmap(dev->base);
2233 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2234 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2235 pci_disable_device(pci_dev);
2236out_free:
2237 free_netdev(ndev);
1da177e4
LT
2238out:
2239 return err;
2240}
2241
6980cbe4 2242static void ns83820_remove_one(struct pci_dev *pci_dev)
1da177e4
LT
2243{
2244 struct net_device *ndev = pci_get_drvdata(pci_dev);
2245 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2246
2247 if (!ndev) /* paranoia */
2248 return;
2249
1a9f28c8 2250 ns83820_disable_interrupts(dev); /* paranoia */
1da177e4
LT
2251
2252 unregister_netdev(ndev);
2253 free_irq(dev->pci_dev->irq, ndev);
2254 iounmap(dev->base);
2255 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2256 dev->tx_descs, dev->tx_phy_descs);
2257 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2258 dev->rx_info.descs, dev->rx_info.phy_descs);
2259 pci_disable_device(dev->pci_dev);
2260 free_netdev(ndev);
1da177e4
LT
2261}
2262
9baa3c34 2263static const struct pci_device_id ns83820_pci_tbl[] = {
1da177e4
LT
2264 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2265 { 0, },
2266};
2267
2268static struct pci_driver driver = {
2269 .name = "ns83820",
2270 .id_table = ns83820_pci_tbl,
2271 .probe = ns83820_init_one,
6980cbe4 2272 .remove = ns83820_remove_one,
1da177e4
LT
2273#if 0 /* FIXME: implement */
2274 .suspend = ,
2275 .resume = ,
2276#endif
2277};
2278
2279
2280static int __init ns83820_init(void)
2281{
2282 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
29917620 2283 return pci_register_driver(&driver);
1da177e4
LT
2284}
2285
2286static void __exit ns83820_exit(void)
2287{
2288 pci_unregister_driver(&driver);
2289}
2290
2291MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2292MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2293MODULE_LICENSE("GPL");
2294
2295MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2296
2297module_param(lnksts, int, 0);
2298MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2299
2300module_param(ihr, int, 0);
2301MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2302
2303module_param(reset_phy, int, 0);
2304MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2305
2306module_init(ns83820_init);
2307module_exit(ns83820_exit);