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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
f1405d32 | 16 | * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 29 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 | 30 | * |
1da177e4 LT |
31 | * Known bugs: |
32 | * We suspect that on some hardware no TX done interrupts are generated. | |
33 | * This means recovery from netif_stop_queue only happens if the hw timer | |
34 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
35 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
36 | * If your hardware reliably generates tx done interrupts, then you can remove | |
37 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
38 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
39 | * superfluous timer interrupts from the nic. | |
40 | */ | |
294a554e JP |
41 | |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
43 | ||
3e1a3ce2 | 44 | #define FORCEDETH_VERSION "0.64" |
1da177e4 LT |
45 | #define DRV_NAME "forcedeth" |
46 | ||
47 | #include <linux/module.h> | |
48 | #include <linux/types.h> | |
49 | #include <linux/pci.h> | |
50 | #include <linux/interrupt.h> | |
51 | #include <linux/netdevice.h> | |
52 | #include <linux/etherdevice.h> | |
53 | #include <linux/delay.h> | |
d43c36dc | 54 | #include <linux/sched.h> |
1da177e4 LT |
55 | #include <linux/spinlock.h> |
56 | #include <linux/ethtool.h> | |
57 | #include <linux/timer.h> | |
58 | #include <linux/skbuff.h> | |
59 | #include <linux/mii.h> | |
60 | #include <linux/random.h> | |
22c6d143 | 61 | #include <linux/if_vlan.h> |
910638ae | 62 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 63 | #include <linux/slab.h> |
5504e139 | 64 | #include <linux/uaccess.h> |
70c71606 | 65 | #include <linux/prefetch.h> |
f5d827ae | 66 | #include <linux/u64_stats_sync.h> |
67 | #include <linux/io.h> | |
1da177e4 LT |
68 | |
69 | #include <asm/irq.h> | |
1da177e4 | 70 | |
bea3348e SH |
71 | #define TX_WORK_PER_LOOP 64 |
72 | #define RX_WORK_PER_LOOP 64 | |
1da177e4 LT |
73 | |
74 | /* | |
75 | * Hardware access: | |
76 | */ | |
77 | ||
3c2e1c11 AA |
78 | #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */ |
79 | #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */ | |
80 | #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */ | |
81 | #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */ | |
82 | #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */ | |
83 | #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */ | |
84 | #define DEV_HAS_MSI 0x0000040 /* device supports MSI */ | |
85 | #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */ | |
86 | #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */ | |
87 | #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */ | |
7b5e078c MD |
88 | #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */ |
89 | #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */ | |
90 | #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */ | |
91 | #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */ | |
3c2e1c11 AA |
92 | #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */ |
93 | #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */ | |
94 | #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */ | |
95 | #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */ | |
96 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */ | |
97 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */ | |
98 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */ | |
99 | #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */ | |
100 | #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */ | |
101 | #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */ | |
102 | #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */ | |
103 | #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */ | |
104 | #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */ | |
1da177e4 LT |
105 | |
106 | enum { | |
107 | NvRegIrqStatus = 0x000, | |
108 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
daa91a9d | 109 | #define NVREG_IRQSTAT_MASK 0x83ff |
1da177e4 LT |
110 | NvRegIrqMask = 0x004, |
111 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
112 | #define NVREG_IRQ_RX 0x0002 | |
113 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
114 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 115 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
116 | #define NVREG_IRQ_TIMER 0x0020 |
117 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
118 | #define NVREG_IRQ_RX_FORCED 0x0080 |
119 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
daa91a9d | 120 | #define NVREG_IRQ_RECOVER_ERROR 0x8200 |
a971c324 | 121 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
096a458c | 122 | #define NVREG_IRQMASK_CPU 0x0060 |
d33a73c8 AA |
123 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
124 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 125 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d | 126 | |
1da177e4 LT |
127 | NvRegUnknownSetupReg6 = 0x008, |
128 | #define NVREG_UNKSETUP6_VAL 3 | |
129 | ||
130 | /* | |
131 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
132 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
133 | */ | |
134 | NvRegPollingInterval = 0x00c, | |
6cef67a0 | 135 | #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */ |
a971c324 | 136 | #define NVREG_POLL_DEFAULT_CPU 13 |
d33a73c8 AA |
137 | NvRegMSIMap0 = 0x020, |
138 | NvRegMSIMap1 = 0x024, | |
139 | NvRegMSIIrqMask = 0x030, | |
140 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 141 | NvRegMisc1 = 0x080, |
eb91f61b | 142 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
143 | #define NVREG_MISC1_HD 0x02 |
144 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
145 | ||
0a62677b | 146 | NvRegMacReset = 0x34, |
86a0f043 | 147 | #define NVREG_MAC_RESET_ASSERT 0x0F3 |
1da177e4 LT |
148 | NvRegTransmitterControl = 0x084, |
149 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
150 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
151 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
152 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
153 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
154 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
155 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
156 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
157 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
158 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 159 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
cac1c52c AA |
160 | #define NVREG_XMITCTL_DATA_START 0x00100000 |
161 | #define NVREG_XMITCTL_DATA_READY 0x00010000 | |
162 | #define NVREG_XMITCTL_DATA_ERROR 0x00020000 | |
1da177e4 LT |
163 | NvRegTransmitterStatus = 0x088, |
164 | #define NVREG_XMITSTAT_BUSY 0x01 | |
165 | ||
166 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
167 | #define NVREG_PFF_PAUSE_RX 0x08 |
168 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
169 | #define NVREG_PFF_PROMISC 0x80 |
170 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 171 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
172 | |
173 | NvRegOffloadConfig = 0x90, | |
174 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
175 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
176 | NvRegReceiverControl = 0x094, | |
177 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 178 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
179 | NvRegReceiverStatus = 0x98, |
180 | #define NVREG_RCVSTAT_BUSY 0x01 | |
181 | ||
a433686c AA |
182 | NvRegSlotTime = 0x9c, |
183 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | |
184 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | |
78aea4fc | 185 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 |
a433686c | 186 | #define NVREG_SLOTTIME_HALF 0x0000ff00 |
78aea4fc | 187 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 |
a433686c | 188 | #define NVREG_SLOTTIME_MASK 0x000000ff |
1da177e4 | 189 | |
9744e218 | 190 | NvRegTxDeferral = 0xA0, |
fd9b558c AA |
191 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
192 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
193 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
194 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f | |
195 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f | |
196 | #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 | |
9744e218 AA |
197 | NvRegRxDeferral = 0xA4, |
198 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
199 | NvRegMacAddrA = 0xA8, |
200 | NvRegMacAddrB = 0xAC, | |
201 | NvRegMulticastAddrA = 0xB0, | |
202 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
203 | NvRegMulticastAddrB = 0xB4, | |
204 | NvRegMulticastMaskA = 0xB8, | |
bb9a4fd1 | 205 | #define NVREG_MCASTMASKA_NONE 0xffffffff |
1da177e4 | 206 | NvRegMulticastMaskB = 0xBC, |
bb9a4fd1 | 207 | #define NVREG_MCASTMASKB_NONE 0xffff |
1da177e4 LT |
208 | |
209 | NvRegPhyInterface = 0xC0, | |
210 | #define PHY_RGMII 0x10000000 | |
a433686c AA |
211 | NvRegBackOffControl = 0xC4, |
212 | #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 | |
213 | #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff | |
214 | #define NVREG_BKOFFCTRL_SELECT 24 | |
215 | #define NVREG_BKOFFCTRL_GEAR 12 | |
1da177e4 LT |
216 | |
217 | NvRegTxRingPhysAddr = 0x100, | |
218 | NvRegRxRingPhysAddr = 0x104, | |
219 | NvRegRingSizes = 0x108, | |
220 | #define NVREG_RINGSZ_TXSHIFT 0 | |
221 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
222 | NvRegTransmitPoll = 0x10c, |
223 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
224 | NvRegLinkSpeed = 0x110, |
225 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
226 | #define NVREG_LINKSPEED_10 1000 | |
227 | #define NVREG_LINKSPEED_100 100 | |
228 | #define NVREG_LINKSPEED_1000 50 | |
229 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
230 | NvRegUnknownSetupReg5 = 0x130, | |
231 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
232 | NvRegTxWatermark = 0x13c, |
233 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
234 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
235 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
236 | NvRegTxRxControl = 0x144, |
237 | #define NVREG_TXRXCTL_KICK 0x0001 | |
238 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
239 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
240 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
241 | #define NVREG_TXRXCTL_RESET 0x0010 | |
242 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 243 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
244 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
245 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
246 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
247 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
248 | NvRegTxRingPhysAddrHigh = 0x148, |
249 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b | 250 | NvRegTxPauseFrame = 0x170, |
5289b4c4 AA |
251 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 |
252 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | |
253 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | |
254 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | |
9a33e883 AA |
255 | NvRegTxPauseFrameLimit = 0x174, |
256 | #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 | |
1da177e4 LT |
257 | NvRegMIIStatus = 0x180, |
258 | #define NVREG_MIISTAT_ERROR 0x0001 | |
259 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
eb798428 AA |
260 | #define NVREG_MIISTAT_MASK_RW 0x0007 |
261 | #define NVREG_MIISTAT_MASK_ALL 0x000f | |
7e680c22 AA |
262 | NvRegMIIMask = 0x184, |
263 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
264 | |
265 | NvRegAdapterControl = 0x188, | |
266 | #define NVREG_ADAPTCTL_START 0x02 | |
267 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
268 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
269 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
270 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
271 | NvRegMIISpeed = 0x18c, | |
272 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
273 | #define NVREG_MIIDELAY 5 | |
274 | NvRegMIIControl = 0x190, | |
275 | #define NVREG_MIICTL_INUSE 0x08000 | |
276 | #define NVREG_MIICTL_WRITE 0x00400 | |
277 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
278 | NvRegMIIData = 0x194, | |
9c662435 AA |
279 | NvRegTxUnicast = 0x1a0, |
280 | NvRegTxMulticast = 0x1a4, | |
281 | NvRegTxBroadcast = 0x1a8, | |
1da177e4 LT |
282 | NvRegWakeUpFlags = 0x200, |
283 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
284 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
285 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
286 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
287 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
288 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
289 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
290 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
291 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
292 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
293 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
294 | ||
cac1c52c | 295 | NvRegMgmtUnitGetVersion = 0x204, |
78aea4fc | 296 | #define NVREG_MGMTUNITGETVERSION 0x01 |
cac1c52c AA |
297 | NvRegMgmtUnitVersion = 0x208, |
298 | #define NVREG_MGMTUNITVERSION 0x08 | |
1da177e4 LT |
299 | NvRegPowerCap = 0x268, |
300 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
301 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
302 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
303 | NvRegPowerState = 0x26c, | |
304 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
305 | #define NVREG_POWERSTATE_VALID 0x0100 | |
306 | #define NVREG_POWERSTATE_MASK 0x0003 | |
307 | #define NVREG_POWERSTATE_D0 0x0000 | |
308 | #define NVREG_POWERSTATE_D1 0x0001 | |
309 | #define NVREG_POWERSTATE_D2 0x0002 | |
310 | #define NVREG_POWERSTATE_D3 0x0003 | |
cac1c52c AA |
311 | NvRegMgmtUnitControl = 0x278, |
312 | #define NVREG_MGMTUNITCONTROL_INUSE 0x20000 | |
52da3578 AA |
313 | NvRegTxCnt = 0x280, |
314 | NvRegTxZeroReXmt = 0x284, | |
315 | NvRegTxOneReXmt = 0x288, | |
316 | NvRegTxManyReXmt = 0x28c, | |
317 | NvRegTxLateCol = 0x290, | |
318 | NvRegTxUnderflow = 0x294, | |
319 | NvRegTxLossCarrier = 0x298, | |
320 | NvRegTxExcessDef = 0x29c, | |
321 | NvRegTxRetryErr = 0x2a0, | |
322 | NvRegRxFrameErr = 0x2a4, | |
323 | NvRegRxExtraByte = 0x2a8, | |
324 | NvRegRxLateCol = 0x2ac, | |
325 | NvRegRxRunt = 0x2b0, | |
326 | NvRegRxFrameTooLong = 0x2b4, | |
327 | NvRegRxOverflow = 0x2b8, | |
328 | NvRegRxFCSErr = 0x2bc, | |
329 | NvRegRxFrameAlignErr = 0x2c0, | |
330 | NvRegRxLenErr = 0x2c4, | |
331 | NvRegRxUnicast = 0x2c8, | |
332 | NvRegRxMulticast = 0x2cc, | |
333 | NvRegRxBroadcast = 0x2d0, | |
334 | NvRegTxDef = 0x2d4, | |
335 | NvRegTxFrame = 0x2d8, | |
336 | NvRegRxCnt = 0x2dc, | |
337 | NvRegTxPause = 0x2e0, | |
338 | NvRegRxPause = 0x2e4, | |
339 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
340 | NvRegVlanControl = 0x300, |
341 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
342 | NvRegMSIXMap0 = 0x3e0, |
343 | NvRegMSIXMap1 = 0x3e4, | |
344 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
345 | |
346 | NvRegPowerState2 = 0x600, | |
1545e205 | 347 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 |
86a0f043 | 348 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
22ae03a1 | 349 | #define NVREG_POWERSTATE2_PHY_RESET 0x0004 |
88d7d8b0 | 350 | #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00 |
1da177e4 LT |
351 | }; |
352 | ||
353 | /* Big endian: should work, but is untested */ | |
354 | struct ring_desc { | |
a8bed49e SH |
355 | __le32 buf; |
356 | __le32 flaglen; | |
1da177e4 LT |
357 | }; |
358 | ||
ee73362c | 359 | struct ring_desc_ex { |
a8bed49e SH |
360 | __le32 bufhigh; |
361 | __le32 buflow; | |
362 | __le32 txvlan; | |
363 | __le32 flaglen; | |
ee73362c MS |
364 | }; |
365 | ||
f82a9352 | 366 | union ring_type { |
78aea4fc SJ |
367 | struct ring_desc *orig; |
368 | struct ring_desc_ex *ex; | |
f82a9352 | 369 | }; |
ee73362c | 370 | |
1da177e4 LT |
371 | #define FLAG_MASK_V1 0xffff0000 |
372 | #define FLAG_MASK_V2 0xffffc000 | |
373 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
374 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
375 | ||
376 | #define NV_TX_LASTPACKET (1<<16) | |
377 | #define NV_TX_RETRYERROR (1<<19) | |
a433686c | 378 | #define NV_TX_RETRYCOUNT_MASK (0xF<<20) |
c2dba06d | 379 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
380 | #define NV_TX_DEFERRED (1<<26) |
381 | #define NV_TX_CARRIERLOST (1<<27) | |
382 | #define NV_TX_LATECOLLISION (1<<28) | |
383 | #define NV_TX_UNDERFLOW (1<<29) | |
384 | #define NV_TX_ERROR (1<<30) | |
385 | #define NV_TX_VALID (1<<31) | |
386 | ||
387 | #define NV_TX2_LASTPACKET (1<<29) | |
388 | #define NV_TX2_RETRYERROR (1<<18) | |
a433686c | 389 | #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) |
c2dba06d | 390 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
391 | #define NV_TX2_DEFERRED (1<<25) |
392 | #define NV_TX2_CARRIERLOST (1<<26) | |
393 | #define NV_TX2_LATECOLLISION (1<<27) | |
394 | #define NV_TX2_UNDERFLOW (1<<28) | |
395 | /* error and valid are the same for both */ | |
396 | #define NV_TX2_ERROR (1<<30) | |
397 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
398 | #define NV_TX2_TSO (1<<28) |
399 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
400 | #define NV_TX2_TSO_MAX_SHIFT 14 |
401 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
402 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
403 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 404 | |
ee407b02 AA |
405 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
406 | ||
1da177e4 LT |
407 | #define NV_RX_DESCRIPTORVALID (1<<16) |
408 | #define NV_RX_MISSEDFRAME (1<<17) | |
cef33c81 | 409 | #define NV_RX_SUBTRACT1 (1<<18) |
1da177e4 LT |
410 | #define NV_RX_ERROR1 (1<<23) |
411 | #define NV_RX_ERROR2 (1<<24) | |
412 | #define NV_RX_ERROR3 (1<<25) | |
413 | #define NV_RX_ERROR4 (1<<26) | |
414 | #define NV_RX_CRCERR (1<<27) | |
415 | #define NV_RX_OVERFLOW (1<<28) | |
416 | #define NV_RX_FRAMINGERR (1<<29) | |
417 | #define NV_RX_ERROR (1<<30) | |
418 | #define NV_RX_AVAIL (1<<31) | |
1ef6841b | 419 | #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) |
1da177e4 LT |
420 | |
421 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
bfaffe8f AA |
422 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
423 | #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) | |
424 | #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) | |
1da177e4 | 425 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
cef33c81 | 426 | #define NV_RX2_SUBTRACT1 (1<<25) |
1da177e4 LT |
427 | #define NV_RX2_ERROR1 (1<<18) |
428 | #define NV_RX2_ERROR2 (1<<19) | |
429 | #define NV_RX2_ERROR3 (1<<20) | |
430 | #define NV_RX2_ERROR4 (1<<21) | |
431 | #define NV_RX2_CRCERR (1<<22) | |
432 | #define NV_RX2_OVERFLOW (1<<23) | |
433 | #define NV_RX2_FRAMINGERR (1<<24) | |
434 | /* error and avail are the same for both */ | |
435 | #define NV_RX2_ERROR (1<<30) | |
436 | #define NV_RX2_AVAIL (1<<31) | |
1ef6841b | 437 | #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) |
1da177e4 | 438 | |
ee407b02 AA |
439 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
440 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
441 | ||
25985edc | 442 | /* Miscellaneous hardware related defines: */ |
78aea4fc SJ |
443 | #define NV_PCI_REGSZ_VER1 0x270 |
444 | #define NV_PCI_REGSZ_VER2 0x2d4 | |
445 | #define NV_PCI_REGSZ_VER3 0x604 | |
446 | #define NV_PCI_REGSZ_MAX 0x604 | |
1da177e4 LT |
447 | |
448 | /* various timeout delays: all in usec */ | |
449 | #define NV_TXRX_RESET_DELAY 4 | |
450 | #define NV_TXSTOP_DELAY1 10 | |
451 | #define NV_TXSTOP_DELAY1MAX 500000 | |
452 | #define NV_TXSTOP_DELAY2 100 | |
453 | #define NV_RXSTOP_DELAY1 10 | |
454 | #define NV_RXSTOP_DELAY1MAX 500000 | |
455 | #define NV_RXSTOP_DELAY2 100 | |
456 | #define NV_SETUP5_DELAY 5 | |
457 | #define NV_SETUP5_DELAYMAX 50000 | |
458 | #define NV_POWERUP_DELAY 5 | |
459 | #define NV_POWERUP_DELAYMAX 5000 | |
460 | #define NV_MIIBUSY_DELAY 50 | |
461 | #define NV_MIIPHY_DELAY 10 | |
462 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 463 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
464 | |
465 | #define NV_WAKEUPPATTERNS 5 | |
466 | #define NV_WAKEUPMASKENTRIES 4 | |
467 | ||
468 | /* General driver defaults */ | |
469 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
470 | ||
6cef67a0 | 471 | #define RX_RING_DEFAULT 512 |
eafa59f6 AA |
472 | #define TX_RING_DEFAULT 256 |
473 | #define RX_RING_MIN 128 | |
474 | #define TX_RING_MIN 64 | |
475 | #define RING_MAX_DESC_VER_1 1024 | |
476 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
477 | |
478 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
479 | #define NV_RX_HEADERS (64) |
480 | /* even more slack. */ | |
481 | #define NV_RX_ALLOC_PAD (64) | |
482 | ||
483 | /* maximum mtu size */ | |
484 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
485 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
486 | |
487 | #define OOM_REFILL (1+HZ/20) | |
488 | #define POLL_WAIT (1+HZ/100) | |
489 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 490 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 491 | |
f3b197ac | 492 | /* |
1da177e4 | 493 | * desc_ver values: |
8a4ae7f2 MS |
494 | * The nic supports three different descriptor types: |
495 | * - DESC_VER_1: Original | |
496 | * - DESC_VER_2: support for jumbo frames. | |
497 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 498 | */ |
8a4ae7f2 MS |
499 | #define DESC_VER_1 1 |
500 | #define DESC_VER_2 2 | |
501 | #define DESC_VER_3 3 | |
1da177e4 LT |
502 | |
503 | /* PHY defines */ | |
9f3f7910 AA |
504 | #define PHY_OUI_MARVELL 0x5043 |
505 | #define PHY_OUI_CICADA 0x03f1 | |
506 | #define PHY_OUI_VITESSE 0x01c1 | |
507 | #define PHY_OUI_REALTEK 0x0732 | |
508 | #define PHY_OUI_REALTEK2 0x0020 | |
1da177e4 LT |
509 | #define PHYID1_OUI_MASK 0x03ff |
510 | #define PHYID1_OUI_SHFT 6 | |
511 | #define PHYID2_OUI_MASK 0xfc00 | |
512 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec | 513 | #define PHYID2_MODEL_MASK 0x03f0 |
9f3f7910 AA |
514 | #define PHY_MODEL_REALTEK_8211 0x0110 |
515 | #define PHY_REV_MASK 0x0001 | |
516 | #define PHY_REV_REALTEK_8211B 0x0000 | |
517 | #define PHY_REV_REALTEK_8211C 0x0001 | |
518 | #define PHY_MODEL_REALTEK_8201 0x0200 | |
519 | #define PHY_MODEL_MARVELL_E3016 0x0220 | |
edf7e5ec | 520 | #define PHY_MARVELL_E3016_INITMASK 0x0300 |
14a67f3c AA |
521 | #define PHY_CICADA_INIT1 0x0f000 |
522 | #define PHY_CICADA_INIT2 0x0e00 | |
523 | #define PHY_CICADA_INIT3 0x01000 | |
524 | #define PHY_CICADA_INIT4 0x0200 | |
525 | #define PHY_CICADA_INIT5 0x0004 | |
526 | #define PHY_CICADA_INIT6 0x02000 | |
d215d8a2 AA |
527 | #define PHY_VITESSE_INIT_REG1 0x1f |
528 | #define PHY_VITESSE_INIT_REG2 0x10 | |
529 | #define PHY_VITESSE_INIT_REG3 0x11 | |
530 | #define PHY_VITESSE_INIT_REG4 0x12 | |
531 | #define PHY_VITESSE_INIT_MSK1 0xc | |
532 | #define PHY_VITESSE_INIT_MSK2 0x0180 | |
533 | #define PHY_VITESSE_INIT1 0x52b5 | |
534 | #define PHY_VITESSE_INIT2 0xaf8a | |
535 | #define PHY_VITESSE_INIT3 0x8 | |
536 | #define PHY_VITESSE_INIT4 0x8f8a | |
537 | #define PHY_VITESSE_INIT5 0xaf86 | |
538 | #define PHY_VITESSE_INIT6 0x8f86 | |
539 | #define PHY_VITESSE_INIT7 0xaf82 | |
540 | #define PHY_VITESSE_INIT8 0x0100 | |
541 | #define PHY_VITESSE_INIT9 0x8f82 | |
542 | #define PHY_VITESSE_INIT10 0x0 | |
c5e3ae88 AA |
543 | #define PHY_REALTEK_INIT_REG1 0x1f |
544 | #define PHY_REALTEK_INIT_REG2 0x19 | |
545 | #define PHY_REALTEK_INIT_REG3 0x13 | |
9f3f7910 AA |
546 | #define PHY_REALTEK_INIT_REG4 0x14 |
547 | #define PHY_REALTEK_INIT_REG5 0x18 | |
548 | #define PHY_REALTEK_INIT_REG6 0x11 | |
22ae03a1 | 549 | #define PHY_REALTEK_INIT_REG7 0x01 |
c5e3ae88 AA |
550 | #define PHY_REALTEK_INIT1 0x0000 |
551 | #define PHY_REALTEK_INIT2 0x8e00 | |
552 | #define PHY_REALTEK_INIT3 0x0001 | |
553 | #define PHY_REALTEK_INIT4 0xad17 | |
9f3f7910 AA |
554 | #define PHY_REALTEK_INIT5 0xfb54 |
555 | #define PHY_REALTEK_INIT6 0xf5c7 | |
556 | #define PHY_REALTEK_INIT7 0x1000 | |
557 | #define PHY_REALTEK_INIT8 0x0003 | |
22ae03a1 AA |
558 | #define PHY_REALTEK_INIT9 0x0008 |
559 | #define PHY_REALTEK_INIT10 0x0005 | |
560 | #define PHY_REALTEK_INIT11 0x0200 | |
9f3f7910 | 561 | #define PHY_REALTEK_INIT_MSK1 0x0003 |
d215d8a2 | 562 | |
1da177e4 LT |
563 | #define PHY_GIGABIT 0x0100 |
564 | ||
565 | #define PHY_TIMEOUT 0x1 | |
566 | #define PHY_ERROR 0x2 | |
567 | ||
568 | #define PHY_100 0x1 | |
569 | #define PHY_1000 0x2 | |
570 | #define PHY_HALF 0x100 | |
571 | ||
eb91f61b AA |
572 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
573 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
574 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
575 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
576 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
577 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
578 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 579 | |
d33a73c8 AA |
580 | /* MSI/MSI-X defines */ |
581 | #define NV_MSI_X_MAX_VECTORS 8 | |
582 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
583 | #define NV_MSI_CAPABLE 0x0010 | |
584 | #define NV_MSI_X_CAPABLE 0x0020 | |
585 | #define NV_MSI_ENABLED 0x0040 | |
586 | #define NV_MSI_X_ENABLED 0x0080 | |
587 | ||
588 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
589 | #define NV_MSI_X_VECTOR_RX 0x0 | |
590 | #define NV_MSI_X_VECTOR_TX 0x1 | |
591 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 592 | |
b6e4405b AA |
593 | #define NV_MSI_PRIV_OFFSET 0x68 |
594 | #define NV_MSI_PRIV_VALUE 0xffffffff | |
595 | ||
b2976d23 AA |
596 | #define NV_RESTART_TX 0x1 |
597 | #define NV_RESTART_RX 0x2 | |
598 | ||
3b446c3e AA |
599 | #define NV_TX_LIMIT_COUNT 16 |
600 | ||
4145ade2 AA |
601 | #define NV_DYNAMIC_THRESHOLD 4 |
602 | #define NV_DYNAMIC_MAX_QUIET_COUNT 2048 | |
603 | ||
52da3578 AA |
604 | /* statistics */ |
605 | struct nv_ethtool_str { | |
606 | char name[ETH_GSTRING_LEN]; | |
607 | }; | |
608 | ||
609 | static const struct nv_ethtool_str nv_estats_str[] = { | |
674aee3b | 610 | { "tx_bytes" }, /* includes Ethernet FCS CRC */ |
52da3578 AA |
611 | { "tx_zero_rexmt" }, |
612 | { "tx_one_rexmt" }, | |
613 | { "tx_many_rexmt" }, | |
614 | { "tx_late_collision" }, | |
615 | { "tx_fifo_errors" }, | |
616 | { "tx_carrier_errors" }, | |
617 | { "tx_excess_deferral" }, | |
618 | { "tx_retry_error" }, | |
52da3578 AA |
619 | { "rx_frame_error" }, |
620 | { "rx_extra_byte" }, | |
621 | { "rx_late_collision" }, | |
622 | { "rx_runt" }, | |
623 | { "rx_frame_too_long" }, | |
624 | { "rx_over_errors" }, | |
625 | { "rx_crc_errors" }, | |
626 | { "rx_frame_align_error" }, | |
627 | { "rx_length_error" }, | |
628 | { "rx_unicast" }, | |
629 | { "rx_multicast" }, | |
630 | { "rx_broadcast" }, | |
57fff698 AA |
631 | { "rx_packets" }, |
632 | { "rx_errors_total" }, | |
633 | { "tx_errors_total" }, | |
634 | ||
635 | /* version 2 stats */ | |
636 | { "tx_deferral" }, | |
637 | { "tx_packets" }, | |
674aee3b | 638 | { "rx_bytes" }, /* includes Ethernet FCS CRC */ |
57fff698 | 639 | { "tx_pause" }, |
52da3578 | 640 | { "rx_pause" }, |
9c662435 AA |
641 | { "rx_drop_frame" }, |
642 | ||
643 | /* version 3 stats */ | |
644 | { "tx_unicast" }, | |
645 | { "tx_multicast" }, | |
646 | { "tx_broadcast" } | |
52da3578 AA |
647 | }; |
648 | ||
649 | struct nv_ethtool_stats { | |
674aee3b | 650 | u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */ |
52da3578 AA |
651 | u64 tx_zero_rexmt; |
652 | u64 tx_one_rexmt; | |
653 | u64 tx_many_rexmt; | |
654 | u64 tx_late_collision; | |
655 | u64 tx_fifo_errors; | |
656 | u64 tx_carrier_errors; | |
657 | u64 tx_excess_deferral; | |
658 | u64 tx_retry_error; | |
52da3578 AA |
659 | u64 rx_frame_error; |
660 | u64 rx_extra_byte; | |
661 | u64 rx_late_collision; | |
662 | u64 rx_runt; | |
663 | u64 rx_frame_too_long; | |
664 | u64 rx_over_errors; | |
665 | u64 rx_crc_errors; | |
666 | u64 rx_frame_align_error; | |
667 | u64 rx_length_error; | |
668 | u64 rx_unicast; | |
669 | u64 rx_multicast; | |
670 | u64 rx_broadcast; | |
674aee3b | 671 | u64 rx_packets; /* should be ifconfig->rx_packets */ |
57fff698 AA |
672 | u64 rx_errors_total; |
673 | u64 tx_errors_total; | |
674 | ||
675 | /* version 2 stats */ | |
676 | u64 tx_deferral; | |
674aee3b | 677 | u64 tx_packets; /* should be ifconfig->tx_packets */ |
678 | u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */ | |
57fff698 | 679 | u64 tx_pause; |
52da3578 AA |
680 | u64 rx_pause; |
681 | u64 rx_drop_frame; | |
9c662435 AA |
682 | |
683 | /* version 3 stats */ | |
684 | u64 tx_unicast; | |
685 | u64 tx_multicast; | |
686 | u64 tx_broadcast; | |
52da3578 AA |
687 | }; |
688 | ||
9c662435 AA |
689 | #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
690 | #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3) | |
57fff698 AA |
691 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) |
692 | ||
9589c77a AA |
693 | /* diagnostics */ |
694 | #define NV_TEST_COUNT_BASE 3 | |
695 | #define NV_TEST_COUNT_EXTENDED 4 | |
696 | ||
697 | static const struct nv_ethtool_str nv_etests_str[] = { | |
698 | { "link (online/offline)" }, | |
699 | { "register (offline) " }, | |
700 | { "interrupt (offline) " }, | |
701 | { "loopback (offline) " } | |
702 | }; | |
703 | ||
704 | struct register_test { | |
5bb7ea26 AV |
705 | __u32 reg; |
706 | __u32 mask; | |
9589c77a AA |
707 | }; |
708 | ||
709 | static const struct register_test nv_registers_test[] = { | |
710 | { NvRegUnknownSetupReg6, 0x01 }, | |
711 | { NvRegMisc1, 0x03c }, | |
712 | { NvRegOffloadConfig, 0x03ff }, | |
713 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 714 | { NvRegTxWatermark, 0x0ff }, |
9589c77a | 715 | { NvRegWakeUpFlags, 0x07777 }, |
78aea4fc | 716 | { 0, 0 } |
9589c77a AA |
717 | }; |
718 | ||
761fcd9e AA |
719 | struct nv_skb_map { |
720 | struct sk_buff *skb; | |
721 | dma_addr_t dma; | |
73a37079 ED |
722 | unsigned int dma_len:31; |
723 | unsigned int dma_single:1; | |
3b446c3e AA |
724 | struct ring_desc_ex *first_tx_desc; |
725 | struct nv_skb_map *next_tx_ctx; | |
761fcd9e AA |
726 | }; |
727 | ||
1da177e4 LT |
728 | /* |
729 | * SMP locking: | |
b74ca3a8 | 730 | * All hardware access under netdev_priv(dev)->lock, except the performance |
1da177e4 LT |
731 | * critical parts: |
732 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
733 | * by the arch code for interrupts. | |
932ff279 | 734 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
b74ca3a8 | 735 | * needs netdev_priv(dev)->lock :-( |
932ff279 | 736 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
f5d827ae | 737 | * |
738 | * Hardware stats updates are protected by hwstats_lock: | |
739 | * - updated by nv_do_stats_poll (timer). This is meant to avoid | |
740 | * integer wraparound in the NIC stats registers, at low frequency | |
741 | * (0.1 Hz) | |
742 | * - updated by nv_get_ethtool_stats + nv_get_stats64 | |
743 | * | |
744 | * Software stats are accessed only through 64b synchronization points | |
745 | * and are not subject to other synchronization techniques (single | |
746 | * update thread on the TX or RX paths). | |
1da177e4 LT |
747 | */ |
748 | ||
749 | /* in dev: base, irq */ | |
750 | struct fe_priv { | |
751 | spinlock_t lock; | |
752 | ||
bea3348e SH |
753 | struct net_device *dev; |
754 | struct napi_struct napi; | |
755 | ||
f5d827ae | 756 | /* hardware stats are updated in syscall and timer */ |
757 | spinlock_t hwstats_lock; | |
52da3578 | 758 | struct nv_ethtool_stats estats; |
f5d827ae | 759 | |
1da177e4 LT |
760 | int in_shutdown; |
761 | u32 linkspeed; | |
762 | int duplex; | |
763 | int autoneg; | |
764 | int fixed_mode; | |
765 | int phyaddr; | |
766 | int wolenabled; | |
767 | unsigned int phy_oui; | |
edf7e5ec | 768 | unsigned int phy_model; |
9f3f7910 | 769 | unsigned int phy_rev; |
1da177e4 | 770 | u16 gigabit; |
9589c77a | 771 | int intr_test; |
c5cf9101 | 772 | int recover_error; |
4145ade2 | 773 | int quiet_count; |
1da177e4 LT |
774 | |
775 | /* General data: RO fields */ | |
776 | dma_addr_t ring_addr; | |
777 | struct pci_dev *pci_dev; | |
778 | u32 orig_mac[2]; | |
582806be | 779 | u32 events; |
1da177e4 LT |
780 | u32 irqmask; |
781 | u32 desc_ver; | |
8a4ae7f2 | 782 | u32 txrxctl_bits; |
ee407b02 | 783 | u32 vlanctl_bits; |
86a0f043 | 784 | u32 driver_data; |
9f3f7910 | 785 | u32 device_id; |
86a0f043 | 786 | u32 register_size; |
7e680c22 | 787 | u32 mac_in_use; |
cac1c52c AA |
788 | int mgmt_version; |
789 | int mgmt_sema; | |
1da177e4 LT |
790 | |
791 | void __iomem *base; | |
792 | ||
793 | /* rx specific fields. | |
794 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
795 | */ | |
761fcd9e AA |
796 | union ring_type get_rx, put_rx, first_rx, last_rx; |
797 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; | |
798 | struct nv_skb_map *first_rx_ctx, *last_rx_ctx; | |
799 | struct nv_skb_map *rx_skb; | |
800 | ||
f82a9352 | 801 | union ring_type rx_ring; |
1da177e4 | 802 | unsigned int rx_buf_sz; |
d81c0983 | 803 | unsigned int pkt_limit; |
1da177e4 LT |
804 | struct timer_list oom_kick; |
805 | struct timer_list nic_poll; | |
52da3578 | 806 | struct timer_list stats_poll; |
d33a73c8 | 807 | u32 nic_poll_irq; |
eafa59f6 | 808 | int rx_ring_size; |
1da177e4 | 809 | |
f5d827ae | 810 | /* RX software stats */ |
811 | struct u64_stats_sync swstats_rx_syncp; | |
812 | u64 stat_rx_packets; | |
813 | u64 stat_rx_bytes; /* not always available in HW */ | |
814 | u64 stat_rx_missed_errors; | |
0a1f222d | 815 | u64 stat_rx_dropped; |
f5d827ae | 816 | |
1da177e4 LT |
817 | /* media detection workaround. |
818 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
819 | */ | |
820 | int need_linktimer; | |
821 | unsigned long link_timeout; | |
822 | /* | |
823 | * tx specific fields. | |
824 | */ | |
761fcd9e AA |
825 | union ring_type get_tx, put_tx, first_tx, last_tx; |
826 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; | |
827 | struct nv_skb_map *first_tx_ctx, *last_tx_ctx; | |
828 | struct nv_skb_map *tx_skb; | |
829 | ||
f82a9352 | 830 | union ring_type tx_ring; |
1da177e4 | 831 | u32 tx_flags; |
eafa59f6 | 832 | int tx_ring_size; |
3b446c3e AA |
833 | int tx_limit; |
834 | u32 tx_pkts_in_progress; | |
835 | struct nv_skb_map *tx_change_owner; | |
836 | struct nv_skb_map *tx_end_flip; | |
aaa37d2d | 837 | int tx_stop; |
ee407b02 | 838 | |
f5d827ae | 839 | /* TX software stats */ |
840 | struct u64_stats_sync swstats_tx_syncp; | |
841 | u64 stat_tx_packets; /* not always available in HW */ | |
842 | u64 stat_tx_bytes; | |
843 | u64 stat_tx_dropped; | |
844 | ||
d33a73c8 AA |
845 | /* msi/msi-x fields */ |
846 | u32 msi_flags; | |
847 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
848 | |
849 | /* flow control */ | |
850 | u32 pause_flags; | |
1a1ca861 TD |
851 | |
852 | /* power saved state */ | |
853 | u32 saved_config_space[NV_PCI_REGSZ_MAX/4]; | |
ddb213f0 YL |
854 | |
855 | /* for different msi-x irq type */ | |
856 | char name_rx[IFNAMSIZ + 3]; /* -rx */ | |
857 | char name_tx[IFNAMSIZ + 3]; /* -tx */ | |
858 | char name_other[IFNAMSIZ + 6]; /* -other */ | |
1da177e4 LT |
859 | }; |
860 | ||
861 | /* | |
862 | * Maximum number of loops until we assume that a bit in the irq mask | |
863 | * is stuck. Overridable with module param. | |
864 | */ | |
4145ade2 | 865 | static int max_interrupt_work = 4; |
1da177e4 | 866 | |
a971c324 AA |
867 | /* |
868 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 869 | * |
a971c324 AA |
870 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
871 | * CPU Mode: Interrupts are controlled by a timer. | |
872 | */ | |
69fe3fd7 AA |
873 | enum { |
874 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
9e184767 AA |
875 | NV_OPTIMIZATION_MODE_CPU, |
876 | NV_OPTIMIZATION_MODE_DYNAMIC | |
69fe3fd7 | 877 | }; |
9e184767 | 878 | static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC; |
a971c324 AA |
879 | |
880 | /* | |
881 | * Poll interval for timer irq | |
882 | * | |
883 | * This interval determines how frequent an interrupt is generated. | |
884 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
885 | * Min = 0, and Max = 65535 | |
886 | */ | |
887 | static int poll_interval = -1; | |
888 | ||
d33a73c8 | 889 | /* |
69fe3fd7 | 890 | * MSI interrupts |
d33a73c8 | 891 | */ |
69fe3fd7 AA |
892 | enum { |
893 | NV_MSI_INT_DISABLED, | |
894 | NV_MSI_INT_ENABLED | |
895 | }; | |
896 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
897 | |
898 | /* | |
69fe3fd7 | 899 | * MSIX interrupts |
d33a73c8 | 900 | */ |
69fe3fd7 AA |
901 | enum { |
902 | NV_MSIX_INT_DISABLED, | |
903 | NV_MSIX_INT_ENABLED | |
904 | }; | |
39482791 | 905 | static int msix = NV_MSIX_INT_ENABLED; |
69fe3fd7 AA |
906 | |
907 | /* | |
908 | * DMA 64bit | |
909 | */ | |
910 | enum { | |
911 | NV_DMA_64BIT_DISABLED, | |
912 | NV_DMA_64BIT_ENABLED | |
913 | }; | |
914 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 915 | |
1ec4f2d3 SN |
916 | /* |
917 | * Debug output control for tx_timeout | |
918 | */ | |
919 | static bool debug_tx_timeout = false; | |
920 | ||
9f3f7910 AA |
921 | /* |
922 | * Crossover Detection | |
923 | * Realtek 8201 phy + some OEM boards do not work properly. | |
924 | */ | |
925 | enum { | |
926 | NV_CROSSOVER_DETECTION_DISABLED, | |
927 | NV_CROSSOVER_DETECTION_ENABLED | |
928 | }; | |
929 | static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; | |
930 | ||
5a9a8e32 ES |
931 | /* |
932 | * Power down phy when interface is down (persists through reboot; | |
933 | * older Linux and other OSes may not power it up again) | |
934 | */ | |
78aea4fc | 935 | static int phy_power_down; |
5a9a8e32 | 936 | |
1da177e4 LT |
937 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
938 | { | |
939 | return netdev_priv(dev); | |
940 | } | |
941 | ||
942 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
943 | { | |
ac9c1897 | 944 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
945 | } |
946 | ||
947 | static inline void pci_push(u8 __iomem *base) | |
948 | { | |
949 | /* force out pending posted writes */ | |
950 | readl(base); | |
951 | } | |
952 | ||
953 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
954 | { | |
f82a9352 | 955 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
956 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
957 | } | |
958 | ||
ee73362c MS |
959 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
960 | { | |
f82a9352 | 961 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
962 | } |
963 | ||
36b30ea9 JG |
964 | static bool nv_optimized(struct fe_priv *np) |
965 | { | |
966 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
967 | return false; | |
968 | return true; | |
969 | } | |
970 | ||
1da177e4 | 971 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
344d0dce | 972 | int delay, int delaymax) |
1da177e4 LT |
973 | { |
974 | u8 __iomem *base = get_hwbase(dev); | |
975 | ||
976 | pci_push(base); | |
977 | do { | |
978 | udelay(delay); | |
979 | delaymax -= delay; | |
344d0dce | 980 | if (delaymax < 0) |
1da177e4 | 981 | return 1; |
1da177e4 LT |
982 | } while ((readl(base + offset) & mask) != target); |
983 | return 0; | |
984 | } | |
985 | ||
0832b25a AA |
986 | #define NV_SETUP_RX_RING 0x01 |
987 | #define NV_SETUP_TX_RING 0x02 | |
988 | ||
5bb7ea26 AV |
989 | static inline u32 dma_low(dma_addr_t addr) |
990 | { | |
991 | return addr; | |
992 | } | |
993 | ||
994 | static inline u32 dma_high(dma_addr_t addr) | |
995 | { | |
996 | return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ | |
997 | } | |
998 | ||
0832b25a AA |
999 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
1000 | { | |
1001 | struct fe_priv *np = get_nvpriv(dev); | |
1002 | u8 __iomem *base = get_hwbase(dev); | |
1003 | ||
36b30ea9 | 1004 | if (!nv_optimized(np)) { |
78aea4fc | 1005 | if (rxtx_flags & NV_SETUP_RX_RING) |
5bb7ea26 | 1006 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
78aea4fc | 1007 | if (rxtx_flags & NV_SETUP_TX_RING) |
5bb7ea26 | 1008 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
1009 | } else { |
1010 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
5bb7ea26 AV |
1011 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
1012 | writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); | |
0832b25a AA |
1013 | } |
1014 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 AV |
1015 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
1016 | writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
1017 | } |
1018 | } | |
1019 | } | |
1020 | ||
eafa59f6 AA |
1021 | static void free_rings(struct net_device *dev) |
1022 | { | |
1023 | struct fe_priv *np = get_nvpriv(dev); | |
1024 | ||
36b30ea9 | 1025 | if (!nv_optimized(np)) { |
f82a9352 | 1026 | if (np->rx_ring.orig) |
eafa59f6 AA |
1027 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
1028 | np->rx_ring.orig, np->ring_addr); | |
1029 | } else { | |
1030 | if (np->rx_ring.ex) | |
1031 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | |
1032 | np->rx_ring.ex, np->ring_addr); | |
1033 | } | |
9b03b06b SJ |
1034 | kfree(np->rx_skb); |
1035 | kfree(np->tx_skb); | |
eafa59f6 AA |
1036 | } |
1037 | ||
84b3932b AA |
1038 | static int using_multi_irqs(struct net_device *dev) |
1039 | { | |
1040 | struct fe_priv *np = get_nvpriv(dev); | |
1041 | ||
1042 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
1043 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1044 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
1045 | return 0; | |
1046 | else | |
1047 | return 1; | |
1048 | } | |
1049 | ||
88d7d8b0 AA |
1050 | static void nv_txrx_gate(struct net_device *dev, bool gate) |
1051 | { | |
1052 | struct fe_priv *np = get_nvpriv(dev); | |
1053 | u8 __iomem *base = get_hwbase(dev); | |
1054 | u32 powerstate; | |
1055 | ||
1056 | if (!np->mac_in_use && | |
1057 | (np->driver_data & DEV_HAS_POWER_CNTRL)) { | |
1058 | powerstate = readl(base + NvRegPowerState2); | |
1059 | if (gate) | |
1060 | powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS; | |
1061 | else | |
1062 | powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS; | |
1063 | writel(powerstate, base + NvRegPowerState2); | |
1064 | } | |
1065 | } | |
1066 | ||
84b3932b AA |
1067 | static void nv_enable_irq(struct net_device *dev) |
1068 | { | |
1069 | struct fe_priv *np = get_nvpriv(dev); | |
1070 | ||
1071 | if (!using_multi_irqs(dev)) { | |
1072 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1073 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1074 | else | |
a7475906 | 1075 | enable_irq(np->pci_dev->irq); |
84b3932b AA |
1076 | } else { |
1077 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1078 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1079 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | static void nv_disable_irq(struct net_device *dev) | |
1084 | { | |
1085 | struct fe_priv *np = get_nvpriv(dev); | |
1086 | ||
1087 | if (!using_multi_irqs(dev)) { | |
1088 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1089 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1090 | else | |
a7475906 | 1091 | disable_irq(np->pci_dev->irq); |
84b3932b AA |
1092 | } else { |
1093 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1094 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1095 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
1100 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
1101 | { | |
1102 | u8 __iomem *base = get_hwbase(dev); | |
1103 | ||
1104 | writel(mask, base + NvRegIrqMask); | |
1105 | } | |
1106 | ||
1107 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
1108 | { | |
1109 | struct fe_priv *np = get_nvpriv(dev); | |
1110 | u8 __iomem *base = get_hwbase(dev); | |
1111 | ||
1112 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
1113 | writel(mask, base + NvRegIrqMask); | |
1114 | } else { | |
1115 | if (np->msi_flags & NV_MSI_ENABLED) | |
1116 | writel(0, base + NvRegMSIIrqMask); | |
1117 | writel(0, base + NvRegIrqMask); | |
1118 | } | |
1119 | } | |
1120 | ||
08d93575 AA |
1121 | static void nv_napi_enable(struct net_device *dev) |
1122 | { | |
08d93575 AA |
1123 | struct fe_priv *np = get_nvpriv(dev); |
1124 | ||
1125 | napi_enable(&np->napi); | |
08d93575 AA |
1126 | } |
1127 | ||
1128 | static void nv_napi_disable(struct net_device *dev) | |
1129 | { | |
08d93575 AA |
1130 | struct fe_priv *np = get_nvpriv(dev); |
1131 | ||
1132 | napi_disable(&np->napi); | |
08d93575 AA |
1133 | } |
1134 | ||
1da177e4 LT |
1135 | #define MII_READ (-1) |
1136 | /* mii_rw: read/write a register on the PHY. | |
1137 | * | |
1138 | * Caller must guarantee serialization | |
1139 | */ | |
1140 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1141 | { | |
1142 | u8 __iomem *base = get_hwbase(dev); | |
1143 | u32 reg; | |
1144 | int retval; | |
1145 | ||
eb798428 | 1146 | writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); |
1da177e4 LT |
1147 | |
1148 | reg = readl(base + NvRegMIIControl); | |
1149 | if (reg & NVREG_MIICTL_INUSE) { | |
1150 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1151 | udelay(NV_MIIBUSY_DELAY); | |
1152 | } | |
1153 | ||
1154 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1155 | if (value != MII_READ) { | |
1156 | writel(value, base + NvRegMIIData); | |
1157 | reg |= NVREG_MIICTL_WRITE; | |
1158 | } | |
1159 | writel(reg, base + NvRegMIIControl); | |
1160 | ||
1161 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
344d0dce | 1162 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) { |
1da177e4 LT |
1163 | retval = -1; |
1164 | } else if (value != MII_READ) { | |
1165 | /* it was a write operation - fewer failures are detectable */ | |
1da177e4 LT |
1166 | retval = 0; |
1167 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
1da177e4 LT |
1168 | retval = -1; |
1169 | } else { | |
1170 | retval = readl(base + NvRegMIIData); | |
1da177e4 LT |
1171 | } |
1172 | ||
1173 | return retval; | |
1174 | } | |
1175 | ||
edf7e5ec | 1176 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1177 | { |
ac9c1897 | 1178 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1179 | u32 miicontrol; |
1180 | unsigned int tries = 0; | |
1181 | ||
edf7e5ec | 1182 | miicontrol = BMCR_RESET | bmcr_setup; |
78aea4fc | 1183 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) |
1da177e4 | 1184 | return -1; |
1da177e4 LT |
1185 | |
1186 | /* wait for 500ms */ | |
1187 | msleep(500); | |
1188 | ||
1189 | /* must wait till reset is deasserted */ | |
1190 | while (miicontrol & BMCR_RESET) { | |
de855b99 | 1191 | usleep_range(10000, 20000); |
1da177e4 LT |
1192 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1193 | /* FIXME: 100 tries seem excessive */ | |
1194 | if (tries++ > 100) | |
1195 | return -1; | |
1196 | } | |
1197 | return 0; | |
1198 | } | |
1199 | ||
c41d41e1 JP |
1200 | static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np) |
1201 | { | |
1202 | static const struct { | |
1203 | int reg; | |
1204 | int init; | |
1205 | } ri[] = { | |
1206 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1207 | { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 }, | |
1208 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 }, | |
1209 | { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 }, | |
1210 | { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 }, | |
1211 | { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 }, | |
1212 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1213 | }; | |
1214 | int i; | |
1215 | ||
1216 | for (i = 0; i < ARRAY_SIZE(ri); i++) { | |
cd66328b JP |
1217 | if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) |
1218 | return PHY_ERROR; | |
1219 | } | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np) | |
1225 | { | |
1226 | u32 reg; | |
1227 | u8 __iomem *base = get_hwbase(dev); | |
1228 | u32 powerstate = readl(base + NvRegPowerState2); | |
1229 | ||
1230 | /* need to perform hw phy reset */ | |
1231 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | |
1232 | writel(powerstate, base + NvRegPowerState2); | |
1233 | msleep(25); | |
1234 | ||
1235 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | |
1236 | writel(powerstate, base + NvRegPowerState2); | |
1237 | msleep(25); | |
1238 | ||
1239 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1240 | reg |= PHY_REALTEK_INIT9; | |
1241 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) | |
1242 | return PHY_ERROR; | |
1243 | if (mii_rw(dev, np->phyaddr, | |
1244 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) | |
1245 | return PHY_ERROR; | |
1246 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | |
1247 | if (!(reg & PHY_REALTEK_INIT11)) { | |
1248 | reg |= PHY_REALTEK_INIT11; | |
1249 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) | |
1250 | return PHY_ERROR; | |
1251 | } | |
1252 | if (mii_rw(dev, np->phyaddr, | |
1253 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | |
1254 | return PHY_ERROR; | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | static int init_realtek_8201(struct net_device *dev, struct fe_priv *np) | |
1260 | { | |
1261 | u32 phy_reserved; | |
1262 | ||
1263 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { | |
1264 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1265 | PHY_REALTEK_INIT_REG6, MII_READ); | |
1266 | phy_reserved |= PHY_REALTEK_INIT7; | |
1267 | if (mii_rw(dev, np->phyaddr, | |
1268 | PHY_REALTEK_INIT_REG6, phy_reserved)) | |
1269 | return PHY_ERROR; | |
1270 | } | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np) | |
1276 | { | |
1277 | u32 phy_reserved; | |
1278 | ||
1279 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
1280 | if (mii_rw(dev, np->phyaddr, | |
1281 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) | |
1282 | return PHY_ERROR; | |
1283 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1284 | PHY_REALTEK_INIT_REG2, MII_READ); | |
1285 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
1286 | phy_reserved |= PHY_REALTEK_INIT3; | |
1287 | if (mii_rw(dev, np->phyaddr, | |
1288 | PHY_REALTEK_INIT_REG2, phy_reserved)) | |
1289 | return PHY_ERROR; | |
1290 | if (mii_rw(dev, np->phyaddr, | |
1291 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | |
c41d41e1 | 1292 | return PHY_ERROR; |
c41d41e1 JP |
1293 | } |
1294 | ||
1295 | return 0; | |
1296 | } | |
1297 | ||
cd66328b JP |
1298 | static int init_cicada(struct net_device *dev, struct fe_priv *np, |
1299 | u32 phyinterface) | |
1300 | { | |
1301 | u32 phy_reserved; | |
1302 | ||
1303 | if (phyinterface & PHY_RGMII) { | |
1304 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | |
1305 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); | |
1306 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | |
1307 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) | |
1308 | return PHY_ERROR; | |
1309 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1310 | phy_reserved |= PHY_CICADA_INIT5; | |
1311 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) | |
1312 | return PHY_ERROR; | |
1313 | } | |
1314 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
1315 | phy_reserved |= PHY_CICADA_INIT6; | |
1316 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) | |
1317 | return PHY_ERROR; | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | static int init_vitesse(struct net_device *dev, struct fe_priv *np) | |
1323 | { | |
1324 | u32 phy_reserved; | |
1325 | ||
1326 | if (mii_rw(dev, np->phyaddr, | |
1327 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) | |
1328 | return PHY_ERROR; | |
1329 | if (mii_rw(dev, np->phyaddr, | |
1330 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) | |
1331 | return PHY_ERROR; | |
1332 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1333 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1334 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1335 | return PHY_ERROR; | |
1336 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1337 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1338 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1339 | phy_reserved |= PHY_VITESSE_INIT3; | |
1340 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1341 | return PHY_ERROR; | |
1342 | if (mii_rw(dev, np->phyaddr, | |
1343 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) | |
1344 | return PHY_ERROR; | |
1345 | if (mii_rw(dev, np->phyaddr, | |
1346 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) | |
1347 | return PHY_ERROR; | |
1348 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1349 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1350 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1351 | phy_reserved |= PHY_VITESSE_INIT3; | |
1352 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1353 | return PHY_ERROR; | |
1354 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1355 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1356 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1357 | return PHY_ERROR; | |
1358 | if (mii_rw(dev, np->phyaddr, | |
1359 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) | |
1360 | return PHY_ERROR; | |
1361 | if (mii_rw(dev, np->phyaddr, | |
1362 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) | |
1363 | return PHY_ERROR; | |
1364 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1365 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1366 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1367 | return PHY_ERROR; | |
1368 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1369 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1370 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | |
1371 | phy_reserved |= PHY_VITESSE_INIT8; | |
1372 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1373 | return PHY_ERROR; | |
1374 | if (mii_rw(dev, np->phyaddr, | |
1375 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) | |
1376 | return PHY_ERROR; | |
1377 | if (mii_rw(dev, np->phyaddr, | |
1378 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) | |
1379 | return PHY_ERROR; | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
1da177e4 LT |
1384 | static int phy_init(struct net_device *dev) |
1385 | { | |
1386 | struct fe_priv *np = get_nvpriv(dev); | |
1387 | u8 __iomem *base = get_hwbase(dev); | |
cd66328b JP |
1388 | u32 phyinterface; |
1389 | u32 mii_status, mii_control, mii_control_1000, reg; | |
1da177e4 | 1390 | |
edf7e5ec AA |
1391 | /* phy errata for E3016 phy */ |
1392 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1393 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1394 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1395 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1d397f36 JP |
1396 | netdev_info(dev, "%s: phy write to errata reg failed\n", |
1397 | pci_name(np->pci_dev)); | |
edf7e5ec AA |
1398 | return PHY_ERROR; |
1399 | } | |
1400 | } | |
c5e3ae88 | 1401 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1402 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1403 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
cd66328b | 1404 | if (init_realtek_8211b(dev, np)) { |
1d397f36 JP |
1405 | netdev_info(dev, "%s: phy init failed\n", |
1406 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1407 | return PHY_ERROR; |
1408 | } | |
cd66328b JP |
1409 | } else if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1410 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1411 | if (init_realtek_8211c(dev, np)) { | |
1d397f36 JP |
1412 | netdev_info(dev, "%s: phy init failed\n", |
1413 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1414 | return PHY_ERROR; |
1415 | } | |
cd66328b JP |
1416 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1417 | if (init_realtek_8201(dev, np)) { | |
1d397f36 JP |
1418 | netdev_info(dev, "%s: phy init failed\n", |
1419 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1420 | return PHY_ERROR; |
1421 | } | |
1422 | } | |
c5e3ae88 | 1423 | } |
edf7e5ec | 1424 | |
1da177e4 LT |
1425 | /* set advertise register */ |
1426 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
cd66328b JP |
1427 | reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
1428 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
1429 | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); | |
1da177e4 | 1430 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1d397f36 JP |
1431 | netdev_info(dev, "%s: phy write to advertise failed\n", |
1432 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1433 | return PHY_ERROR; |
1434 | } | |
1435 | ||
1436 | /* get phy interface type */ | |
1437 | phyinterface = readl(base + NvRegPhyInterface); | |
1438 | ||
1439 | /* see if gigabit phy */ | |
1440 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1441 | if (mii_status & PHY_GIGABIT) { | |
1442 | np->gigabit = PHY_GIGABIT; | |
cd66328b JP |
1443 | mii_control_1000 = mii_rw(dev, np->phyaddr, |
1444 | MII_CTRL1000, MII_READ); | |
1da177e4 LT |
1445 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1446 | if (phyinterface & PHY_RGMII) | |
1447 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1448 | else | |
1449 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1450 | ||
eb91f61b | 1451 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1d397f36 JP |
1452 | netdev_info(dev, "%s: phy init failed\n", |
1453 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1454 | return PHY_ERROR; |
1455 | } | |
78aea4fc | 1456 | } else |
1da177e4 LT |
1457 | np->gigabit = 0; |
1458 | ||
edf7e5ec AA |
1459 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1460 | mii_control |= BMCR_ANENABLE; | |
1461 | ||
22ae03a1 AA |
1462 | if (np->phy_oui == PHY_OUI_REALTEK && |
1463 | np->phy_model == PHY_MODEL_REALTEK_8211 && | |
1464 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1465 | /* start autoneg since we already performed hw reset above */ | |
1466 | mii_control |= BMCR_ANRESTART; | |
1467 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1d397f36 JP |
1468 | netdev_info(dev, "%s: phy init failed\n", |
1469 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1470 | return PHY_ERROR; |
1471 | } | |
1472 | } else { | |
1473 | /* reset the phy | |
1474 | * (certain phys need bmcr to be setup with reset) | |
1475 | */ | |
1476 | if (phy_reset(dev, mii_control)) { | |
1d397f36 JP |
1477 | netdev_info(dev, "%s: phy reset failed\n", |
1478 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1479 | return PHY_ERROR; |
1480 | } | |
1da177e4 LT |
1481 | } |
1482 | ||
1483 | /* phy vendor specific configuration */ | |
d46781bc | 1484 | if (np->phy_oui == PHY_OUI_CICADA) { |
cd66328b | 1485 | if (init_cicada(dev, np, phyinterface)) { |
1d397f36 JP |
1486 | netdev_info(dev, "%s: phy init failed\n", |
1487 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1488 | return PHY_ERROR; |
1489 | } | |
cd66328b JP |
1490 | } else if (np->phy_oui == PHY_OUI_VITESSE) { |
1491 | if (init_vitesse(dev, np)) { | |
1d397f36 JP |
1492 | netdev_info(dev, "%s: phy init failed\n", |
1493 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1494 | return PHY_ERROR; |
1495 | } | |
cd66328b | 1496 | } else if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1497 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1498 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1499 | /* reset could have cleared these out, set them back */ | |
cd66328b JP |
1500 | if (init_realtek_8211b(dev, np)) { |
1501 | netdev_info(dev, "%s: phy init failed\n", | |
1502 | pci_name(np->pci_dev)); | |
9f3f7910 | 1503 | return PHY_ERROR; |
9f3f7910 | 1504 | } |
cd66328b JP |
1505 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1506 | if (init_realtek_8201(dev, np) || | |
1507 | init_realtek_8201_cross(dev, np)) { | |
1508 | netdev_info(dev, "%s: phy init failed\n", | |
1509 | pci_name(np->pci_dev)); | |
1510 | return PHY_ERROR; | |
9f3f7910 | 1511 | } |
c5e3ae88 AA |
1512 | } |
1513 | } | |
1514 | ||
25985edc | 1515 | /* some phys clear out pause advertisement on reset, set it back */ |
eb91f61b | 1516 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); |
1da177e4 | 1517 | |
cb52deba | 1518 | /* restart auto negotiation, power down phy */ |
1da177e4 | 1519 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
5a9a8e32 | 1520 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
78aea4fc | 1521 | if (phy_power_down) |
5a9a8e32 | 1522 | mii_control |= BMCR_PDOWN; |
78aea4fc | 1523 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) |
1da177e4 | 1524 | return PHY_ERROR; |
1da177e4 LT |
1525 | |
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | static void nv_start_rx(struct net_device *dev) | |
1530 | { | |
ac9c1897 | 1531 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1532 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1533 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1534 | |
1da177e4 | 1535 | /* Already running? Stop it. */ |
f35723ec AA |
1536 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1537 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1538 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1539 | pci_push(base); |
1540 | } | |
1541 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1542 | pci_push(base); | |
78aea4fc SJ |
1543 | rx_ctrl |= NVREG_RCVCTL_START; |
1544 | if (np->mac_in_use) | |
f35723ec AA |
1545 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; |
1546 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1547 | pci_push(base); |
1548 | } | |
1549 | ||
1550 | static void nv_stop_rx(struct net_device *dev) | |
1551 | { | |
f35723ec | 1552 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1553 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1554 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1555 | |
f35723ec AA |
1556 | if (!np->mac_in_use) |
1557 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1558 | else | |
1559 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1560 | writel(rx_ctrl, base + NvRegReceiverControl); | |
344d0dce JP |
1561 | if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1562 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1563 | netdev_info(dev, "%s: ReceiverStatus remained busy\n", |
1564 | __func__); | |
1da177e4 LT |
1565 | |
1566 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1567 | if (!np->mac_in_use) |
1568 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1569 | } |
1570 | ||
1571 | static void nv_start_tx(struct net_device *dev) | |
1572 | { | |
f35723ec | 1573 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1574 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1575 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1576 | |
f35723ec AA |
1577 | tx_ctrl |= NVREG_XMITCTL_START; |
1578 | if (np->mac_in_use) | |
1579 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1580 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1581 | pci_push(base); |
1582 | } | |
1583 | ||
1584 | static void nv_stop_tx(struct net_device *dev) | |
1585 | { | |
f35723ec | 1586 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1587 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1588 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1589 | |
f35723ec AA |
1590 | if (!np->mac_in_use) |
1591 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1592 | else | |
1593 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1594 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
344d0dce JP |
1595 | if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1596 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1597 | netdev_info(dev, "%s: TransmitterStatus remained busy\n", |
1598 | __func__); | |
1da177e4 LT |
1599 | |
1600 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1601 | if (!np->mac_in_use) |
1602 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1603 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1604 | } |
1605 | ||
36b30ea9 JG |
1606 | static void nv_start_rxtx(struct net_device *dev) |
1607 | { | |
1608 | nv_start_rx(dev); | |
1609 | nv_start_tx(dev); | |
1610 | } | |
1611 | ||
1612 | static void nv_stop_rxtx(struct net_device *dev) | |
1613 | { | |
1614 | nv_stop_rx(dev); | |
1615 | nv_stop_tx(dev); | |
1616 | } | |
1617 | ||
1da177e4 LT |
1618 | static void nv_txrx_reset(struct net_device *dev) |
1619 | { | |
ac9c1897 | 1620 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1621 | u8 __iomem *base = get_hwbase(dev); |
1622 | ||
8a4ae7f2 | 1623 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1624 | pci_push(base); |
1625 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1626 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1627 | pci_push(base); |
1628 | } | |
1629 | ||
86a0f043 AA |
1630 | static void nv_mac_reset(struct net_device *dev) |
1631 | { | |
1632 | struct fe_priv *np = netdev_priv(dev); | |
1633 | u8 __iomem *base = get_hwbase(dev); | |
4e84f9b1 | 1634 | u32 temp1, temp2, temp3; |
86a0f043 | 1635 | |
86a0f043 AA |
1636 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1637 | pci_push(base); | |
4e84f9b1 AA |
1638 | |
1639 | /* save registers since they will be cleared on reset */ | |
1640 | temp1 = readl(base + NvRegMacAddrA); | |
1641 | temp2 = readl(base + NvRegMacAddrB); | |
1642 | temp3 = readl(base + NvRegTransmitPoll); | |
1643 | ||
86a0f043 AA |
1644 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
1645 | pci_push(base); | |
1646 | udelay(NV_MAC_RESET_DELAY); | |
1647 | writel(0, base + NvRegMacReset); | |
1648 | pci_push(base); | |
1649 | udelay(NV_MAC_RESET_DELAY); | |
4e84f9b1 AA |
1650 | |
1651 | /* restore saved registers */ | |
1652 | writel(temp1, base + NvRegMacAddrA); | |
1653 | writel(temp2, base + NvRegMacAddrB); | |
1654 | writel(temp3, base + NvRegTransmitPoll); | |
1655 | ||
86a0f043 AA |
1656 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1657 | pci_push(base); | |
1658 | } | |
1659 | ||
f5d827ae | 1660 | /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */ |
1661 | static void nv_update_stats(struct net_device *dev) | |
57fff698 AA |
1662 | { |
1663 | struct fe_priv *np = netdev_priv(dev); | |
1664 | u8 __iomem *base = get_hwbase(dev); | |
1665 | ||
f5d827ae | 1666 | /* If it happens that this is run in top-half context, then |
1667 | * replace the spin_lock of hwstats_lock with | |
1668 | * spin_lock_irqsave() in calling functions. */ | |
1669 | WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half"); | |
1670 | assert_spin_locked(&np->hwstats_lock); | |
1671 | ||
1672 | /* query hardware */ | |
57fff698 AA |
1673 | np->estats.tx_bytes += readl(base + NvRegTxCnt); |
1674 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
1675 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
1676 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
1677 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
1678 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
1679 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
1680 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
1681 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
1682 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
1683 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
1684 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
1685 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
1686 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
1687 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
1688 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
1689 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
1690 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
1691 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
1692 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
1693 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
1694 | np->estats.rx_packets = | |
1695 | np->estats.rx_unicast + | |
1696 | np->estats.rx_multicast + | |
1697 | np->estats.rx_broadcast; | |
1698 | np->estats.rx_errors_total = | |
1699 | np->estats.rx_crc_errors + | |
1700 | np->estats.rx_over_errors + | |
1701 | np->estats.rx_frame_error + | |
1702 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
1703 | np->estats.rx_late_collision + | |
1704 | np->estats.rx_runt + | |
1705 | np->estats.rx_frame_too_long; | |
1706 | np->estats.tx_errors_total = | |
1707 | np->estats.tx_late_collision + | |
1708 | np->estats.tx_fifo_errors + | |
1709 | np->estats.tx_carrier_errors + | |
1710 | np->estats.tx_excess_deferral + | |
1711 | np->estats.tx_retry_error; | |
1712 | ||
1713 | if (np->driver_data & DEV_HAS_STATISTICS_V2) { | |
1714 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
1715 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
1716 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
1717 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
1718 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
1719 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
0bdfea8b | 1720 | np->estats.rx_errors_total += np->estats.rx_drop_frame; |
57fff698 | 1721 | } |
9c662435 AA |
1722 | |
1723 | if (np->driver_data & DEV_HAS_STATISTICS_V3) { | |
1724 | np->estats.tx_unicast += readl(base + NvRegTxUnicast); | |
1725 | np->estats.tx_multicast += readl(base + NvRegTxMulticast); | |
1726 | np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); | |
1727 | } | |
57fff698 AA |
1728 | } |
1729 | ||
1da177e4 | 1730 | /* |
f5d827ae | 1731 | * nv_get_stats64: dev->ndo_get_stats64 function |
1da177e4 LT |
1732 | * Get latest stats value from the nic. |
1733 | * Called with read_lock(&dev_base_lock) held for read - | |
1734 | * only synchronized against unregister_netdevice. | |
1735 | */ | |
bc1f4470 | 1736 | static void |
f5d827ae | 1737 | nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage) |
1738 | __acquires(&netdev_priv(dev)->hwstats_lock) | |
1739 | __releases(&netdev_priv(dev)->hwstats_lock) | |
1da177e4 | 1740 | { |
ac9c1897 | 1741 | struct fe_priv *np = netdev_priv(dev); |
f5d827ae | 1742 | unsigned int syncp_start; |
1743 | ||
1744 | /* | |
1745 | * Note: because HW stats are not always available and for | |
1746 | * consistency reasons, the following ifconfig stats are | |
1747 | * managed by software: rx_bytes, tx_bytes, rx_packets and | |
1748 | * tx_packets. The related hardware stats reported by ethtool | |
1749 | * should be equivalent to these ifconfig stats, with 4 | |
1750 | * additional bytes per packet (Ethernet FCS CRC), except for | |
1751 | * tx_packets when TSO kicks in. | |
1752 | */ | |
1753 | ||
1754 | /* software stats */ | |
1755 | do { | |
57a7744e | 1756 | syncp_start = u64_stats_fetch_begin_irq(&np->swstats_rx_syncp); |
f5d827ae | 1757 | storage->rx_packets = np->stat_rx_packets; |
1758 | storage->rx_bytes = np->stat_rx_bytes; | |
0a1f222d | 1759 | storage->rx_dropped = np->stat_rx_dropped; |
f5d827ae | 1760 | storage->rx_missed_errors = np->stat_rx_missed_errors; |
57a7744e | 1761 | } while (u64_stats_fetch_retry_irq(&np->swstats_rx_syncp, syncp_start)); |
f5d827ae | 1762 | |
1763 | do { | |
57a7744e | 1764 | syncp_start = u64_stats_fetch_begin_irq(&np->swstats_tx_syncp); |
f5d827ae | 1765 | storage->tx_packets = np->stat_tx_packets; |
1766 | storage->tx_bytes = np->stat_tx_bytes; | |
1767 | storage->tx_dropped = np->stat_tx_dropped; | |
57a7744e | 1768 | } while (u64_stats_fetch_retry_irq(&np->swstats_tx_syncp, syncp_start)); |
1da177e4 | 1769 | |
21828163 | 1770 | /* If the nic supports hw counters then retrieve latest values */ |
f5d827ae | 1771 | if (np->driver_data & DEV_HAS_STATISTICS_V123) { |
1772 | spin_lock_bh(&np->hwstats_lock); | |
21828163 | 1773 | |
f5d827ae | 1774 | nv_update_stats(dev); |
1775 | ||
1776 | /* generic stats */ | |
1777 | storage->rx_errors = np->estats.rx_errors_total; | |
1778 | storage->tx_errors = np->estats.tx_errors_total; | |
1779 | ||
1780 | /* meaningful only when NIC supports stats v3 */ | |
1781 | storage->multicast = np->estats.rx_multicast; | |
1782 | ||
1783 | /* detailed rx_errors */ | |
1784 | storage->rx_length_errors = np->estats.rx_length_error; | |
1785 | storage->rx_over_errors = np->estats.rx_over_errors; | |
1786 | storage->rx_crc_errors = np->estats.rx_crc_errors; | |
1787 | storage->rx_frame_errors = np->estats.rx_frame_align_error; | |
1788 | storage->rx_fifo_errors = np->estats.rx_drop_frame; | |
674aee3b | 1789 | |
f5d827ae | 1790 | /* detailed tx_errors */ |
1791 | storage->tx_carrier_errors = np->estats.tx_carrier_errors; | |
1792 | storage->tx_fifo_errors = np->estats.tx_fifo_errors; | |
1793 | ||
1794 | spin_unlock_bh(&np->hwstats_lock); | |
21828163 | 1795 | } |
1da177e4 LT |
1796 | } |
1797 | ||
1798 | /* | |
1799 | * nv_alloc_rx: fill rx ring entries. | |
1800 | * Return 1 if the allocations for the skbs failed and the | |
1801 | * rx engine is without Available descriptors | |
1802 | */ | |
1803 | static int nv_alloc_rx(struct net_device *dev) | |
1804 | { | |
ac9c1897 | 1805 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 1806 | struct ring_desc *less_rx; |
1da177e4 | 1807 | |
86b22b0d AA |
1808 | less_rx = np->get_rx.orig; |
1809 | if (less_rx-- == np->first_rx.orig) | |
1810 | less_rx = np->last_rx.orig; | |
761fcd9e | 1811 | |
86b22b0d | 1812 | while (np->put_rx.orig != less_rx) { |
dae2e9f4 | 1813 | struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); |
86b22b0d | 1814 | if (skb) { |
86b22b0d | 1815 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1816 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1817 | skb->data, | |
8b5be268 | 1818 | skb_tailroom(skb), |
4305b541 | 1819 | PCI_DMA_FROMDEVICE); |
612a7c4e LF |
1820 | if (pci_dma_mapping_error(np->pci_dev, |
1821 | np->put_rx_ctx->dma)) { | |
1822 | kfree_skb(skb); | |
1823 | goto packet_dropped; | |
1824 | } | |
8b5be268 | 1825 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
86b22b0d AA |
1826 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); |
1827 | wmb(); | |
1828 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1829 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 1830 | np->put_rx.orig = np->first_rx.orig; |
b01867cb | 1831 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 1832 | np->put_rx_ctx = np->first_rx_ctx; |
0a1f222d | 1833 | } else { |
612a7c4e | 1834 | packet_dropped: |
0a1f222d | 1835 | u64_stats_update_begin(&np->swstats_rx_syncp); |
1836 | np->stat_rx_dropped++; | |
1837 | u64_stats_update_end(&np->swstats_rx_syncp); | |
86b22b0d | 1838 | return 1; |
0a1f222d | 1839 | } |
86b22b0d AA |
1840 | } |
1841 | return 0; | |
1842 | } | |
1843 | ||
1844 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1845 | { | |
1846 | struct fe_priv *np = netdev_priv(dev); | |
78aea4fc | 1847 | struct ring_desc_ex *less_rx; |
86b22b0d AA |
1848 | |
1849 | less_rx = np->get_rx.ex; | |
1850 | if (less_rx-- == np->first_rx.ex) | |
1851 | less_rx = np->last_rx.ex; | |
761fcd9e | 1852 | |
86b22b0d | 1853 | while (np->put_rx.ex != less_rx) { |
dae2e9f4 | 1854 | struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); |
0d63fb32 | 1855 | if (skb) { |
761fcd9e | 1856 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1857 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1858 | skb->data, | |
8b5be268 | 1859 | skb_tailroom(skb), |
4305b541 | 1860 | PCI_DMA_FROMDEVICE); |
612a7c4e LF |
1861 | if (pci_dma_mapping_error(np->pci_dev, |
1862 | np->put_rx_ctx->dma)) { | |
1863 | kfree_skb(skb); | |
1864 | goto packet_dropped; | |
1865 | } | |
8b5be268 | 1866 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
5bb7ea26 AV |
1867 | np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); |
1868 | np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); | |
86b22b0d AA |
1869 | wmb(); |
1870 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1871 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 1872 | np->put_rx.ex = np->first_rx.ex; |
b01867cb | 1873 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
0d63fb32 | 1874 | np->put_rx_ctx = np->first_rx_ctx; |
0a1f222d | 1875 | } else { |
612a7c4e | 1876 | packet_dropped: |
0a1f222d | 1877 | u64_stats_update_begin(&np->swstats_rx_syncp); |
1878 | np->stat_rx_dropped++; | |
1879 | u64_stats_update_end(&np->swstats_rx_syncp); | |
0d63fb32 | 1880 | return 1; |
0a1f222d | 1881 | } |
1da177e4 | 1882 | } |
1da177e4 LT |
1883 | return 0; |
1884 | } | |
1885 | ||
e27cdba5 | 1886 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
e27cdba5 SH |
1887 | static void nv_do_rx_refill(unsigned long data) |
1888 | { | |
1889 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 1890 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
1891 | |
1892 | /* Just reschedule NAPI rx processing */ | |
288379f0 | 1893 | napi_schedule(&np->napi); |
e27cdba5 | 1894 | } |
1da177e4 | 1895 | |
f3b197ac | 1896 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1897 | { |
ac9c1897 | 1898 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1899 | int i; |
36b30ea9 | 1900 | |
761fcd9e | 1901 | np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
36b30ea9 JG |
1902 | |
1903 | if (!nv_optimized(np)) | |
761fcd9e AA |
1904 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
1905 | else | |
1906 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
1907 | np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; | |
1908 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; | |
1da177e4 | 1909 | |
761fcd9e | 1910 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1911 | if (!nv_optimized(np)) { |
f82a9352 | 1912 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1913 | np->rx_ring.orig[i].buf = 0; |
1914 | } else { | |
f82a9352 | 1915 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1916 | np->rx_ring.ex[i].txvlan = 0; |
1917 | np->rx_ring.ex[i].bufhigh = 0; | |
1918 | np->rx_ring.ex[i].buflow = 0; | |
1919 | } | |
1920 | np->rx_skb[i].skb = NULL; | |
1921 | np->rx_skb[i].dma = 0; | |
1922 | } | |
d81c0983 MS |
1923 | } |
1924 | ||
1925 | static void nv_init_tx(struct net_device *dev) | |
1926 | { | |
ac9c1897 | 1927 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1928 | int i; |
36b30ea9 | 1929 | |
761fcd9e | 1930 | np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
36b30ea9 JG |
1931 | |
1932 | if (!nv_optimized(np)) | |
761fcd9e AA |
1933 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
1934 | else | |
1935 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
1936 | np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; | |
1937 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; | |
b8bfca94 | 1938 | netdev_reset_queue(np->dev); |
3b446c3e AA |
1939 | np->tx_pkts_in_progress = 0; |
1940 | np->tx_change_owner = NULL; | |
1941 | np->tx_end_flip = NULL; | |
8f955d7f | 1942 | np->tx_stop = 0; |
d81c0983 | 1943 | |
eafa59f6 | 1944 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1945 | if (!nv_optimized(np)) { |
f82a9352 | 1946 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1947 | np->tx_ring.orig[i].buf = 0; |
1948 | } else { | |
f82a9352 | 1949 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1950 | np->tx_ring.ex[i].txvlan = 0; |
1951 | np->tx_ring.ex[i].bufhigh = 0; | |
1952 | np->tx_ring.ex[i].buflow = 0; | |
1953 | } | |
1954 | np->tx_skb[i].skb = NULL; | |
1955 | np->tx_skb[i].dma = 0; | |
3b446c3e | 1956 | np->tx_skb[i].dma_len = 0; |
73a37079 | 1957 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1958 | np->tx_skb[i].first_tx_desc = NULL; |
1959 | np->tx_skb[i].next_tx_ctx = NULL; | |
ac9c1897 | 1960 | } |
d81c0983 MS |
1961 | } |
1962 | ||
1963 | static int nv_init_ring(struct net_device *dev) | |
1964 | { | |
86b22b0d AA |
1965 | struct fe_priv *np = netdev_priv(dev); |
1966 | ||
d81c0983 MS |
1967 | nv_init_tx(dev); |
1968 | nv_init_rx(dev); | |
36b30ea9 JG |
1969 | |
1970 | if (!nv_optimized(np)) | |
86b22b0d AA |
1971 | return nv_alloc_rx(dev); |
1972 | else | |
1973 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1974 | } |
1975 | ||
73a37079 | 1976 | static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) |
ac9c1897 | 1977 | { |
761fcd9e | 1978 | if (tx_skb->dma) { |
73a37079 ED |
1979 | if (tx_skb->dma_single) |
1980 | pci_unmap_single(np->pci_dev, tx_skb->dma, | |
1981 | tx_skb->dma_len, | |
1982 | PCI_DMA_TODEVICE); | |
1983 | else | |
1984 | pci_unmap_page(np->pci_dev, tx_skb->dma, | |
1985 | tx_skb->dma_len, | |
1986 | PCI_DMA_TODEVICE); | |
761fcd9e | 1987 | tx_skb->dma = 0; |
fa45459e | 1988 | } |
73a37079 ED |
1989 | } |
1990 | ||
1991 | static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) | |
1992 | { | |
1993 | nv_unmap_txskb(np, tx_skb); | |
761fcd9e AA |
1994 | if (tx_skb->skb) { |
1995 | dev_kfree_skb_any(tx_skb->skb); | |
1996 | tx_skb->skb = NULL; | |
fa45459e | 1997 | return 1; |
ac9c1897 | 1998 | } |
73a37079 | 1999 | return 0; |
ac9c1897 AA |
2000 | } |
2001 | ||
1da177e4 LT |
2002 | static void nv_drain_tx(struct net_device *dev) |
2003 | { | |
ac9c1897 AA |
2004 | struct fe_priv *np = netdev_priv(dev); |
2005 | unsigned int i; | |
f3b197ac | 2006 | |
eafa59f6 | 2007 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 2008 | if (!nv_optimized(np)) { |
f82a9352 | 2009 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
2010 | np->tx_ring.orig[i].buf = 0; |
2011 | } else { | |
f82a9352 | 2012 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
2013 | np->tx_ring.ex[i].txvlan = 0; |
2014 | np->tx_ring.ex[i].bufhigh = 0; | |
2015 | np->tx_ring.ex[i].buflow = 0; | |
2016 | } | |
f5d827ae | 2017 | if (nv_release_txskb(np, &np->tx_skb[i])) { |
2018 | u64_stats_update_begin(&np->swstats_tx_syncp); | |
2019 | np->stat_tx_dropped++; | |
2020 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2021 | } | |
3b446c3e AA |
2022 | np->tx_skb[i].dma = 0; |
2023 | np->tx_skb[i].dma_len = 0; | |
73a37079 | 2024 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
2025 | np->tx_skb[i].first_tx_desc = NULL; |
2026 | np->tx_skb[i].next_tx_ctx = NULL; | |
1da177e4 | 2027 | } |
3b446c3e AA |
2028 | np->tx_pkts_in_progress = 0; |
2029 | np->tx_change_owner = NULL; | |
2030 | np->tx_end_flip = NULL; | |
1da177e4 LT |
2031 | } |
2032 | ||
2033 | static void nv_drain_rx(struct net_device *dev) | |
2034 | { | |
ac9c1897 | 2035 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2036 | int i; |
761fcd9e | 2037 | |
eafa59f6 | 2038 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 2039 | if (!nv_optimized(np)) { |
f82a9352 | 2040 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
2041 | np->rx_ring.orig[i].buf = 0; |
2042 | } else { | |
f82a9352 | 2043 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
2044 | np->rx_ring.ex[i].txvlan = 0; |
2045 | np->rx_ring.ex[i].bufhigh = 0; | |
2046 | np->rx_ring.ex[i].buflow = 0; | |
2047 | } | |
1da177e4 | 2048 | wmb(); |
761fcd9e AA |
2049 | if (np->rx_skb[i].skb) { |
2050 | pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, | |
4305b541 ACM |
2051 | (skb_end_pointer(np->rx_skb[i].skb) - |
2052 | np->rx_skb[i].skb->data), | |
2053 | PCI_DMA_FROMDEVICE); | |
761fcd9e AA |
2054 | dev_kfree_skb(np->rx_skb[i].skb); |
2055 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
2056 | } |
2057 | } | |
2058 | } | |
2059 | ||
36b30ea9 | 2060 | static void nv_drain_rxtx(struct net_device *dev) |
1da177e4 LT |
2061 | { |
2062 | nv_drain_tx(dev); | |
2063 | nv_drain_rx(dev); | |
2064 | } | |
2065 | ||
761fcd9e AA |
2066 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
2067 | { | |
2068 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
2069 | } | |
2070 | ||
a433686c AA |
2071 | static void nv_legacybackoff_reseed(struct net_device *dev) |
2072 | { | |
2073 | u8 __iomem *base = get_hwbase(dev); | |
2074 | u32 reg; | |
2075 | u32 low; | |
2076 | int tx_status = 0; | |
2077 | ||
2078 | reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; | |
2079 | get_random_bytes(&low, sizeof(low)); | |
2080 | reg |= low & NVREG_SLOTTIME_MASK; | |
2081 | ||
2082 | /* Need to stop tx before change takes effect. | |
2083 | * Caller has already gained np->lock. | |
2084 | */ | |
2085 | tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; | |
2086 | if (tx_status) | |
2087 | nv_stop_tx(dev); | |
2088 | nv_stop_rx(dev); | |
2089 | writel(reg, base + NvRegSlotTime); | |
2090 | if (tx_status) | |
2091 | nv_start_tx(dev); | |
2092 | nv_start_rx(dev); | |
2093 | } | |
2094 | ||
2095 | /* Gear Backoff Seeds */ | |
2096 | #define BACKOFF_SEEDSET_ROWS 8 | |
2097 | #define BACKOFF_SEEDSET_LFSRS 15 | |
2098 | ||
2099 | /* Known Good seed sets */ | |
2100 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2101 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, |
2102 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | |
2103 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
2104 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | |
2105 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | |
2106 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | |
2107 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | |
2108 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} }; | |
a433686c AA |
2109 | |
2110 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2111 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2112 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2113 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | |
2114 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2115 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2116 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2117 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2118 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} }; | |
a433686c AA |
2119 | |
2120 | static void nv_gear_backoff_reseed(struct net_device *dev) | |
2121 | { | |
2122 | u8 __iomem *base = get_hwbase(dev); | |
2123 | u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed; | |
2124 | u32 temp, seedset, combinedSeed; | |
2125 | int i; | |
2126 | ||
2127 | /* Setup seed for free running LFSR */ | |
2128 | /* We are going to read the time stamp counter 3 times | |
2129 | and swizzle bits around to increase randomness */ | |
2130 | get_random_bytes(&miniseed1, sizeof(miniseed1)); | |
2131 | miniseed1 &= 0x0fff; | |
2132 | if (miniseed1 == 0) | |
2133 | miniseed1 = 0xabc; | |
2134 | ||
2135 | get_random_bytes(&miniseed2, sizeof(miniseed2)); | |
2136 | miniseed2 &= 0x0fff; | |
2137 | if (miniseed2 == 0) | |
2138 | miniseed2 = 0xabc; | |
2139 | miniseed2_reversed = | |
2140 | ((miniseed2 & 0xF00) >> 8) | | |
2141 | (miniseed2 & 0x0F0) | | |
2142 | ((miniseed2 & 0x00F) << 8); | |
2143 | ||
2144 | get_random_bytes(&miniseed3, sizeof(miniseed3)); | |
2145 | miniseed3 &= 0x0fff; | |
2146 | if (miniseed3 == 0) | |
2147 | miniseed3 = 0xabc; | |
2148 | miniseed3_reversed = | |
2149 | ((miniseed3 & 0xF00) >> 8) | | |
2150 | (miniseed3 & 0x0F0) | | |
2151 | ((miniseed3 & 0x00F) << 8); | |
2152 | ||
2153 | combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) | | |
2154 | (miniseed2 ^ miniseed3_reversed); | |
2155 | ||
2156 | /* Seeds can not be zero */ | |
2157 | if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) | |
2158 | combinedSeed |= 0x08; | |
2159 | if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) | |
2160 | combinedSeed |= 0x8000; | |
2161 | ||
2162 | /* No need to disable tx here */ | |
2163 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | |
2164 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | |
2165 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | |
78aea4fc | 2166 | writel(temp, base + NvRegBackOffControl); |
a433686c | 2167 | |
78aea4fc | 2168 | /* Setup seeds for all gear LFSRs. */ |
a433686c AA |
2169 | get_random_bytes(&seedset, sizeof(seedset)); |
2170 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | |
78aea4fc | 2171 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) { |
a433686c AA |
2172 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); |
2173 | temp |= main_seedset[seedset][i-1] & 0x3ff; | |
2174 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | |
2175 | writel(temp, base + NvRegBackOffControl); | |
2176 | } | |
2177 | } | |
2178 | ||
1da177e4 LT |
2179 | /* |
2180 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 2181 | * Called with netif_tx_lock held. |
1da177e4 | 2182 | */ |
61357325 | 2183 | static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 2184 | { |
ac9c1897 | 2185 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 2186 | u32 tx_flags = 0; |
ac9c1897 AA |
2187 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
2188 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 2189 | unsigned int i; |
fa45459e AA |
2190 | u32 offset = 0; |
2191 | u32 bcnt; | |
e743d313 | 2192 | u32 size = skb_headlen(skb); |
fa45459e | 2193 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
761fcd9e | 2194 | u32 empty_slots; |
78aea4fc SJ |
2195 | struct ring_desc *put_tx; |
2196 | struct ring_desc *start_tx; | |
2197 | struct ring_desc *prev_tx; | |
2198 | struct nv_skb_map *prev_tx_ctx; | |
f7f22874 | 2199 | struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL; |
bd6ca637 | 2200 | unsigned long flags; |
fa45459e AA |
2201 | |
2202 | /* add fragments to entries count */ | |
2203 | for (i = 0; i < fragments; i++) { | |
e45a6187 | 2204 | u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]); |
9e903e08 | 2205 | |
e45a6187 | 2206 | entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) + |
2207 | ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
fa45459e | 2208 | } |
ac9c1897 | 2209 | |
001eb84b | 2210 | spin_lock_irqsave(&np->lock, flags); |
761fcd9e | 2211 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2212 | if (unlikely(empty_slots <= entries)) { |
ac9c1897 | 2213 | netif_stop_queue(dev); |
aaa37d2d | 2214 | np->tx_stop = 1; |
bd6ca637 | 2215 | spin_unlock_irqrestore(&np->lock, flags); |
ac9c1897 AA |
2216 | return NETDEV_TX_BUSY; |
2217 | } | |
001eb84b | 2218 | spin_unlock_irqrestore(&np->lock, flags); |
1da177e4 | 2219 | |
86b22b0d | 2220 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 2221 | |
fa45459e AA |
2222 | /* setup the header buffer */ |
2223 | do { | |
761fcd9e AA |
2224 | prev_tx = put_tx; |
2225 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2226 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e | 2227 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
fa45459e | 2228 | PCI_DMA_TODEVICE); |
612a7c4e LF |
2229 | if (pci_dma_mapping_error(np->pci_dev, |
2230 | np->put_tx_ctx->dma)) { | |
2231 | /* on DMA mapping error - drop the packet */ | |
1616566c | 2232 | dev_kfree_skb_any(skb); |
612a7c4e LF |
2233 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2234 | np->stat_tx_dropped++; | |
2235 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2236 | return NETDEV_TX_OK; | |
2237 | } | |
761fcd9e | 2238 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2239 | np->put_tx_ctx->dma_single = 1; |
86b22b0d AA |
2240 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2241 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2242 | |
fa45459e AA |
2243 | tx_flags = np->tx_flags; |
2244 | offset += bcnt; | |
2245 | size -= bcnt; | |
445583b8 | 2246 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2247 | put_tx = np->first_tx.orig; |
445583b8 | 2248 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2249 | np->put_tx_ctx = np->first_tx_ctx; |
f82a9352 | 2250 | } while (size); |
fa45459e AA |
2251 | |
2252 | /* setup the fragments */ | |
2253 | for (i = 0; i < fragments; i++) { | |
9e903e08 | 2254 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
e45a6187 | 2255 | u32 frag_size = skb_frag_size(frag); |
fa45459e AA |
2256 | offset = 0; |
2257 | ||
2258 | do { | |
761fcd9e AA |
2259 | prev_tx = put_tx; |
2260 | prev_tx_ctx = np->put_tx_ctx; | |
f7f22874 NH |
2261 | if (!start_tx_ctx) |
2262 | start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; | |
2263 | ||
e45a6187 | 2264 | bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size; |
671173c3 IC |
2265 | np->put_tx_ctx->dma = skb_frag_dma_map( |
2266 | &np->pci_dev->dev, | |
2267 | frag, offset, | |
2268 | bcnt, | |
5d6bcdfe | 2269 | DMA_TO_DEVICE); |
f7f22874 NH |
2270 | if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) { |
2271 | ||
2272 | /* Unwind the mapped fragments */ | |
2273 | do { | |
2274 | nv_unmap_txskb(np, start_tx_ctx); | |
2275 | if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) | |
2276 | tmp_tx_ctx = np->first_tx_ctx; | |
2277 | } while (tmp_tx_ctx != np->put_tx_ctx); | |
1616566c | 2278 | dev_kfree_skb_any(skb); |
f7f22874 NH |
2279 | np->put_tx_ctx = start_tx_ctx; |
2280 | u64_stats_update_begin(&np->swstats_tx_syncp); | |
2281 | np->stat_tx_dropped++; | |
2282 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2283 | return NETDEV_TX_OK; | |
2284 | } | |
2285 | ||
761fcd9e | 2286 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2287 | np->put_tx_ctx->dma_single = 0; |
86b22b0d AA |
2288 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2289 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2290 | |
fa45459e | 2291 | offset += bcnt; |
e45a6187 | 2292 | frag_size -= bcnt; |
445583b8 | 2293 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2294 | put_tx = np->first_tx.orig; |
445583b8 | 2295 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2296 | np->put_tx_ctx = np->first_tx_ctx; |
e45a6187 | 2297 | } while (frag_size); |
fa45459e | 2298 | } |
ac9c1897 | 2299 | |
fa45459e | 2300 | /* set last fragment flag */ |
86b22b0d | 2301 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 2302 | |
761fcd9e AA |
2303 | /* save skb in this slot's context area */ |
2304 | prev_tx_ctx->skb = skb; | |
fa45459e | 2305 | |
89114afd | 2306 | if (skb_is_gso(skb)) |
7967168c | 2307 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 2308 | else |
1d39ed56 | 2309 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 2310 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 2311 | |
bd6ca637 | 2312 | spin_lock_irqsave(&np->lock, flags); |
164a86e4 | 2313 | |
fa45459e | 2314 | /* set tx flags */ |
86b22b0d | 2315 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
b8bfca94 TH |
2316 | |
2317 | netdev_sent_queue(np->dev, skb->len); | |
2318 | ||
49cbb1c1 WB |
2319 | skb_tx_timestamp(skb); |
2320 | ||
86b22b0d | 2321 | np->put_tx.orig = put_tx; |
1da177e4 | 2322 | |
bd6ca637 | 2323 | spin_unlock_irqrestore(&np->lock, flags); |
761fcd9e | 2324 | |
8a4ae7f2 | 2325 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 2326 | return NETDEV_TX_OK; |
1da177e4 LT |
2327 | } |
2328 | ||
61357325 SH |
2329 | static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb, |
2330 | struct net_device *dev) | |
86b22b0d AA |
2331 | { |
2332 | struct fe_priv *np = netdev_priv(dev); | |
2333 | u32 tx_flags = 0; | |
445583b8 | 2334 | u32 tx_flags_extra; |
86b22b0d AA |
2335 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2336 | unsigned int i; | |
2337 | u32 offset = 0; | |
2338 | u32 bcnt; | |
e743d313 | 2339 | u32 size = skb_headlen(skb); |
86b22b0d AA |
2340 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2341 | u32 empty_slots; | |
78aea4fc SJ |
2342 | struct ring_desc_ex *put_tx; |
2343 | struct ring_desc_ex *start_tx; | |
2344 | struct ring_desc_ex *prev_tx; | |
2345 | struct nv_skb_map *prev_tx_ctx; | |
f7f22874 NH |
2346 | struct nv_skb_map *start_tx_ctx = NULL; |
2347 | struct nv_skb_map *tmp_tx_ctx = NULL; | |
bd6ca637 | 2348 | unsigned long flags; |
86b22b0d AA |
2349 | |
2350 | /* add fragments to entries count */ | |
2351 | for (i = 0; i < fragments; i++) { | |
e45a6187 | 2352 | u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]); |
9e903e08 | 2353 | |
e45a6187 | 2354 | entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) + |
2355 | ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
86b22b0d AA |
2356 | } |
2357 | ||
001eb84b | 2358 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2359 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2360 | if (unlikely(empty_slots <= entries)) { |
86b22b0d | 2361 | netif_stop_queue(dev); |
aaa37d2d | 2362 | np->tx_stop = 1; |
bd6ca637 | 2363 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2364 | return NETDEV_TX_BUSY; |
2365 | } | |
001eb84b | 2366 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2367 | |
2368 | start_tx = put_tx = np->put_tx.ex; | |
3b446c3e | 2369 | start_tx_ctx = np->put_tx_ctx; |
86b22b0d AA |
2370 | |
2371 | /* setup the header buffer */ | |
2372 | do { | |
2373 | prev_tx = put_tx; | |
2374 | prev_tx_ctx = np->put_tx_ctx; | |
2375 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2376 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
2377 | PCI_DMA_TODEVICE); | |
612a7c4e LF |
2378 | if (pci_dma_mapping_error(np->pci_dev, |
2379 | np->put_tx_ctx->dma)) { | |
2380 | /* on DMA mapping error - drop the packet */ | |
1616566c | 2381 | dev_kfree_skb_any(skb); |
612a7c4e LF |
2382 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2383 | np->stat_tx_dropped++; | |
2384 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2385 | return NETDEV_TX_OK; | |
2386 | } | |
86b22b0d | 2387 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2388 | np->put_tx_ctx->dma_single = 1; |
5bb7ea26 AV |
2389 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2390 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2391 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 AA |
2392 | |
2393 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
2394 | offset += bcnt; |
2395 | size -= bcnt; | |
445583b8 | 2396 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2397 | put_tx = np->first_tx.ex; |
445583b8 | 2398 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2399 | np->put_tx_ctx = np->first_tx_ctx; |
2400 | } while (size); | |
2401 | ||
2402 | /* setup the fragments */ | |
2403 | for (i = 0; i < fragments; i++) { | |
2404 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
e45a6187 | 2405 | u32 frag_size = skb_frag_size(frag); |
86b22b0d AA |
2406 | offset = 0; |
2407 | ||
2408 | do { | |
2409 | prev_tx = put_tx; | |
2410 | prev_tx_ctx = np->put_tx_ctx; | |
e45a6187 | 2411 | bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size; |
f7f22874 NH |
2412 | if (!start_tx_ctx) |
2413 | start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; | |
671173c3 IC |
2414 | np->put_tx_ctx->dma = skb_frag_dma_map( |
2415 | &np->pci_dev->dev, | |
2416 | frag, offset, | |
2417 | bcnt, | |
5d6bcdfe | 2418 | DMA_TO_DEVICE); |
f7f22874 NH |
2419 | |
2420 | if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) { | |
2421 | ||
2422 | /* Unwind the mapped fragments */ | |
2423 | do { | |
2424 | nv_unmap_txskb(np, start_tx_ctx); | |
2425 | if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) | |
2426 | tmp_tx_ctx = np->first_tx_ctx; | |
2427 | } while (tmp_tx_ctx != np->put_tx_ctx); | |
1616566c | 2428 | dev_kfree_skb_any(skb); |
f7f22874 NH |
2429 | np->put_tx_ctx = start_tx_ctx; |
2430 | u64_stats_update_begin(&np->swstats_tx_syncp); | |
2431 | np->stat_tx_dropped++; | |
2432 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2433 | return NETDEV_TX_OK; | |
2434 | } | |
86b22b0d | 2435 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2436 | np->put_tx_ctx->dma_single = 0; |
5bb7ea26 AV |
2437 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2438 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2439 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 | 2440 | |
86b22b0d | 2441 | offset += bcnt; |
e45a6187 | 2442 | frag_size -= bcnt; |
445583b8 | 2443 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2444 | put_tx = np->first_tx.ex; |
445583b8 | 2445 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d | 2446 | np->put_tx_ctx = np->first_tx_ctx; |
e45a6187 | 2447 | } while (frag_size); |
86b22b0d AA |
2448 | } |
2449 | ||
2450 | /* set last fragment flag */ | |
445583b8 | 2451 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
2452 | |
2453 | /* save skb in this slot's context area */ | |
2454 | prev_tx_ctx->skb = skb; | |
2455 | ||
2456 | if (skb_is_gso(skb)) | |
2457 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
2458 | else | |
2459 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
2460 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
2461 | ||
2462 | /* vlan tag */ | |
df8a39de | 2463 | if (skb_vlan_tag_present(skb)) |
eab6d18d | 2464 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | |
df8a39de | 2465 | skb_vlan_tag_get(skb)); |
eab6d18d | 2466 | else |
445583b8 | 2467 | start_tx->txvlan = 0; |
86b22b0d | 2468 | |
bd6ca637 | 2469 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2470 | |
3b446c3e AA |
2471 | if (np->tx_limit) { |
2472 | /* Limit the number of outstanding tx. Setup all fragments, but | |
2473 | * do not set the VALID bit on the first descriptor. Save a pointer | |
2474 | * to that descriptor and also for next skb_map element. | |
2475 | */ | |
2476 | ||
2477 | if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { | |
2478 | if (!np->tx_change_owner) | |
2479 | np->tx_change_owner = start_tx_ctx; | |
2480 | ||
2481 | /* remove VALID bit */ | |
2482 | tx_flags &= ~NV_TX2_VALID; | |
2483 | start_tx_ctx->first_tx_desc = start_tx; | |
2484 | start_tx_ctx->next_tx_ctx = np->put_tx_ctx; | |
2485 | np->tx_end_flip = np->put_tx_ctx; | |
2486 | } else { | |
2487 | np->tx_pkts_in_progress++; | |
2488 | } | |
2489 | } | |
2490 | ||
86b22b0d | 2491 | /* set tx flags */ |
86b22b0d | 2492 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
b8bfca94 TH |
2493 | |
2494 | netdev_sent_queue(np->dev, skb->len); | |
2495 | ||
49cbb1c1 WB |
2496 | skb_tx_timestamp(skb); |
2497 | ||
86b22b0d AA |
2498 | np->put_tx.ex = put_tx; |
2499 | ||
bd6ca637 | 2500 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d | 2501 | |
86b22b0d | 2502 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
86b22b0d AA |
2503 | return NETDEV_TX_OK; |
2504 | } | |
2505 | ||
3b446c3e AA |
2506 | static inline void nv_tx_flip_ownership(struct net_device *dev) |
2507 | { | |
2508 | struct fe_priv *np = netdev_priv(dev); | |
2509 | ||
2510 | np->tx_pkts_in_progress--; | |
2511 | if (np->tx_change_owner) { | |
30ecce90 AV |
2512 | np->tx_change_owner->first_tx_desc->flaglen |= |
2513 | cpu_to_le32(NV_TX2_VALID); | |
3b446c3e AA |
2514 | np->tx_pkts_in_progress++; |
2515 | ||
2516 | np->tx_change_owner = np->tx_change_owner->next_tx_ctx; | |
2517 | if (np->tx_change_owner == np->tx_end_flip) | |
2518 | np->tx_change_owner = NULL; | |
2519 | ||
2520 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2521 | } | |
2522 | } | |
2523 | ||
1da177e4 LT |
2524 | /* |
2525 | * nv_tx_done: check for completed packets, release the skbs. | |
2526 | * | |
2527 | * Caller must own np->lock. | |
2528 | */ | |
33912e72 | 2529 | static int nv_tx_done(struct net_device *dev, int limit) |
1da177e4 | 2530 | { |
ac9c1897 | 2531 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2532 | u32 flags; |
33912e72 | 2533 | int tx_work = 0; |
78aea4fc | 2534 | struct ring_desc *orig_get_tx = np->get_tx.orig; |
b8bfca94 | 2535 | unsigned int bytes_compl = 0; |
1da177e4 | 2536 | |
445583b8 | 2537 | while ((np->get_tx.orig != np->put_tx.orig) && |
33912e72 AA |
2538 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && |
2539 | (tx_work < limit)) { | |
1da177e4 | 2540 | |
73a37079 | 2541 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2542 | |
1da177e4 | 2543 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 2544 | if (flags & NV_TX_LASTPACKET) { |
445583b8 | 2545 | if (flags & NV_TX_ERROR) { |
f5d827ae | 2546 | if ((flags & NV_TX_RETRYERROR) |
2547 | && !(flags & NV_TX_RETRYCOUNT_MASK)) | |
a433686c | 2548 | nv_legacybackoff_reseed(dev); |
674aee3b | 2549 | } else { |
f5d827ae | 2550 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2551 | np->stat_tx_packets++; | |
2552 | np->stat_tx_bytes += np->get_tx_ctx->skb->len; | |
2553 | u64_stats_update_end(&np->swstats_tx_syncp); | |
ac9c1897 | 2554 | } |
b8bfca94 | 2555 | bytes_compl += np->get_tx_ctx->skb->len; |
445583b8 AA |
2556 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2557 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2558 | tx_work++; |
1da177e4 LT |
2559 | } |
2560 | } else { | |
f82a9352 | 2561 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 2562 | if (flags & NV_TX2_ERROR) { |
f5d827ae | 2563 | if ((flags & NV_TX2_RETRYERROR) |
2564 | && !(flags & NV_TX2_RETRYCOUNT_MASK)) | |
a433686c | 2565 | nv_legacybackoff_reseed(dev); |
674aee3b | 2566 | } else { |
f5d827ae | 2567 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2568 | np->stat_tx_packets++; | |
2569 | np->stat_tx_bytes += np->get_tx_ctx->skb->len; | |
2570 | u64_stats_update_end(&np->swstats_tx_syncp); | |
f3b197ac | 2571 | } |
b8bfca94 | 2572 | bytes_compl += np->get_tx_ctx->skb->len; |
445583b8 AA |
2573 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2574 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2575 | tx_work++; |
1da177e4 LT |
2576 | } |
2577 | } | |
445583b8 | 2578 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
86b22b0d | 2579 | np->get_tx.orig = np->first_tx.orig; |
445583b8 | 2580 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2581 | np->get_tx_ctx = np->first_tx_ctx; |
2582 | } | |
b8bfca94 TH |
2583 | |
2584 | netdev_completed_queue(np->dev, tx_work, bytes_compl); | |
2585 | ||
445583b8 | 2586 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 2587 | np->tx_stop = 0; |
86b22b0d | 2588 | netif_wake_queue(dev); |
aaa37d2d | 2589 | } |
33912e72 | 2590 | return tx_work; |
86b22b0d AA |
2591 | } |
2592 | ||
33912e72 | 2593 | static int nv_tx_done_optimized(struct net_device *dev, int limit) |
86b22b0d AA |
2594 | { |
2595 | struct fe_priv *np = netdev_priv(dev); | |
2596 | u32 flags; | |
33912e72 | 2597 | int tx_work = 0; |
78aea4fc | 2598 | struct ring_desc_ex *orig_get_tx = np->get_tx.ex; |
b8bfca94 | 2599 | unsigned long bytes_cleaned = 0; |
86b22b0d | 2600 | |
445583b8 | 2601 | while ((np->get_tx.ex != np->put_tx.ex) && |
217d32dc | 2602 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && |
33912e72 | 2603 | (tx_work < limit)) { |
86b22b0d | 2604 | |
73a37079 | 2605 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2606 | |
86b22b0d | 2607 | if (flags & NV_TX2_LASTPACKET) { |
4687f3f3 | 2608 | if (flags & NV_TX2_ERROR) { |
f5d827ae | 2609 | if ((flags & NV_TX2_RETRYERROR) |
2610 | && !(flags & NV_TX2_RETRYCOUNT_MASK)) { | |
a433686c AA |
2611 | if (np->driver_data & DEV_HAS_GEAR_MODE) |
2612 | nv_gear_backoff_reseed(dev); | |
2613 | else | |
2614 | nv_legacybackoff_reseed(dev); | |
2615 | } | |
674aee3b | 2616 | } else { |
efd0bf97 DM |
2617 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2618 | np->stat_tx_packets++; | |
2619 | np->stat_tx_bytes += np->get_tx_ctx->skb->len; | |
2620 | u64_stats_update_end(&np->swstats_tx_syncp); | |
a433686c AA |
2621 | } |
2622 | ||
b8bfca94 | 2623 | bytes_cleaned += np->get_tx_ctx->skb->len; |
445583b8 AA |
2624 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2625 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2626 | tx_work++; |
3b446c3e | 2627 | |
78aea4fc | 2628 | if (np->tx_limit) |
3b446c3e | 2629 | nv_tx_flip_ownership(dev); |
761fcd9e | 2630 | } |
b8bfca94 | 2631 | |
445583b8 | 2632 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
86b22b0d | 2633 | np->get_tx.ex = np->first_tx.ex; |
445583b8 | 2634 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2635 | np->get_tx_ctx = np->first_tx_ctx; |
1da177e4 | 2636 | } |
7505afe2 IM |
2637 | |
2638 | netdev_completed_queue(np->dev, tx_work, bytes_cleaned); | |
2639 | ||
445583b8 | 2640 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 2641 | np->tx_stop = 0; |
1da177e4 | 2642 | netif_wake_queue(dev); |
aaa37d2d | 2643 | } |
33912e72 | 2644 | return tx_work; |
1da177e4 LT |
2645 | } |
2646 | ||
2647 | /* | |
2648 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 2649 | * Called with netif_tx_lock held. |
1da177e4 LT |
2650 | */ |
2651 | static void nv_tx_timeout(struct net_device *dev) | |
2652 | { | |
ac9c1897 | 2653 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2654 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 2655 | u32 status; |
8f955d7f AA |
2656 | union ring_type put_tx; |
2657 | int saved_tx_limit; | |
d33a73c8 AA |
2658 | |
2659 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2660 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2661 | else | |
2662 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 2663 | |
1ec4f2d3 | 2664 | netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status); |
1da177e4 | 2665 | |
1ec4f2d3 SN |
2666 | if (unlikely(debug_tx_timeout)) { |
2667 | int i; | |
2668 | ||
2669 | netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); | |
2670 | netdev_info(dev, "Dumping tx registers\n"); | |
2671 | for (i = 0; i <= np->register_size; i += 32) { | |
1d397f36 | 2672 | netdev_info(dev, |
1ec4f2d3 SN |
2673 | "%3x: %08x %08x %08x %08x " |
2674 | "%08x %08x %08x %08x\n", | |
1d397f36 | 2675 | i, |
1ec4f2d3 SN |
2676 | readl(base + i + 0), readl(base + i + 4), |
2677 | readl(base + i + 8), readl(base + i + 12), | |
2678 | readl(base + i + 16), readl(base + i + 20), | |
2679 | readl(base + i + 24), readl(base + i + 28)); | |
2680 | } | |
2681 | netdev_info(dev, "Dumping tx ring\n"); | |
2682 | for (i = 0; i < np->tx_ring_size; i += 4) { | |
2683 | if (!nv_optimized(np)) { | |
2684 | netdev_info(dev, | |
2685 | "%03x: %08x %08x // %08x %08x " | |
2686 | "// %08x %08x // %08x %08x\n", | |
2687 | i, | |
2688 | le32_to_cpu(np->tx_ring.orig[i].buf), | |
2689 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
2690 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
2691 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
2692 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
2693 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
2694 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
2695 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
2696 | } else { | |
2697 | netdev_info(dev, | |
2698 | "%03x: %08x %08x %08x " | |
2699 | "// %08x %08x %08x " | |
2700 | "// %08x %08x %08x " | |
2701 | "// %08x %08x %08x\n", | |
2702 | i, | |
2703 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), | |
2704 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
2705 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
2706 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
2707 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
2708 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
2709 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
2710 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
2711 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
2712 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
2713 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
2714 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
2715 | } | |
c2dba06d MS |
2716 | } |
2717 | } | |
2718 | ||
1da177e4 LT |
2719 | spin_lock_irq(&np->lock); |
2720 | ||
2721 | /* 1) stop tx engine */ | |
2722 | nv_stop_tx(dev); | |
2723 | ||
8f955d7f AA |
2724 | /* 2) complete any outstanding tx and do not give HW any limited tx pkts */ |
2725 | saved_tx_limit = np->tx_limit; | |
2726 | np->tx_limit = 0; /* prevent giving HW any limited pkts */ | |
2727 | np->tx_stop = 0; /* prevent waking tx queue */ | |
36b30ea9 | 2728 | if (!nv_optimized(np)) |
33912e72 | 2729 | nv_tx_done(dev, np->tx_ring_size); |
86b22b0d | 2730 | else |
4e16ed1b | 2731 | nv_tx_done_optimized(dev, np->tx_ring_size); |
1da177e4 | 2732 | |
25985edc | 2733 | /* save current HW position */ |
8f955d7f AA |
2734 | if (np->tx_change_owner) |
2735 | put_tx.ex = np->tx_change_owner->first_tx_desc; | |
2736 | else | |
2737 | put_tx = np->put_tx; | |
1da177e4 | 2738 | |
8f955d7f AA |
2739 | /* 3) clear all tx state */ |
2740 | nv_drain_tx(dev); | |
2741 | nv_init_tx(dev); | |
2742 | ||
2743 | /* 4) restore state to current HW position */ | |
2744 | np->get_tx = np->put_tx = put_tx; | |
2745 | np->tx_limit = saved_tx_limit; | |
3ba4d093 | 2746 | |
8f955d7f | 2747 | /* 5) restart tx engine */ |
1da177e4 | 2748 | nv_start_tx(dev); |
8f955d7f | 2749 | netif_wake_queue(dev); |
1da177e4 LT |
2750 | spin_unlock_irq(&np->lock); |
2751 | } | |
2752 | ||
22c6d143 MS |
2753 | /* |
2754 | * Called when the nic notices a mismatch between the actual data len on the | |
2755 | * wire and the len indicated in the 802 header | |
2756 | */ | |
2757 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
2758 | { | |
2759 | int hdrlen; /* length of the 802 header */ | |
2760 | int protolen; /* length as stored in the proto field */ | |
2761 | ||
2762 | /* 1) calculate len according to header */ | |
78aea4fc SJ |
2763 | if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
2764 | protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto); | |
22c6d143 MS |
2765 | hdrlen = VLAN_HLEN; |
2766 | } else { | |
78aea4fc | 2767 | protolen = ntohs(((struct ethhdr *)packet)->h_proto); |
22c6d143 MS |
2768 | hdrlen = ETH_HLEN; |
2769 | } | |
22c6d143 MS |
2770 | if (protolen > ETH_DATA_LEN) |
2771 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2772 | ||
2773 | protolen += hdrlen; | |
2774 | /* consistency checks: */ | |
2775 | if (datalen > ETH_ZLEN) { | |
2776 | if (datalen >= protolen) { | |
2777 | /* more data on wire than in 802 header, trim of | |
2778 | * additional data. | |
2779 | */ | |
22c6d143 MS |
2780 | return protolen; |
2781 | } else { | |
2782 | /* less data on wire than mentioned in header. | |
2783 | * Discard the packet. | |
2784 | */ | |
22c6d143 MS |
2785 | return -1; |
2786 | } | |
2787 | } else { | |
2788 | /* short packet. Accept only if 802 values are also short */ | |
2789 | if (protolen > ETH_ZLEN) { | |
22c6d143 MS |
2790 | return -1; |
2791 | } | |
22c6d143 MS |
2792 | return datalen; |
2793 | } | |
2794 | } | |
2795 | ||
e27cdba5 | 2796 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2797 | { |
ac9c1897 | 2798 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2799 | u32 flags; |
bcb5febb | 2800 | int rx_work = 0; |
b01867cb AA |
2801 | struct sk_buff *skb; |
2802 | int len; | |
1da177e4 | 2803 | |
78aea4fc | 2804 | while ((np->get_rx.orig != np->put_rx.orig) && |
b01867cb | 2805 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && |
bcb5febb | 2806 | (rx_work < limit)) { |
1da177e4 | 2807 | |
1da177e4 LT |
2808 | /* |
2809 | * the packet is for us - immediately tear down the pci mapping. | |
2810 | * TODO: check if a prefetch of the first cacheline improves | |
2811 | * the performance. | |
2812 | */ | |
761fcd9e AA |
2813 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2814 | np->get_rx_ctx->dma_len, | |
1da177e4 | 2815 | PCI_DMA_FROMDEVICE); |
0d63fb32 AA |
2816 | skb = np->get_rx_ctx->skb; |
2817 | np->get_rx_ctx->skb = NULL; | |
1da177e4 | 2818 | |
1da177e4 LT |
2819 | /* look at what we actually got: */ |
2820 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2821 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2822 | len = flags & LEN_MASK_V1; | |
2823 | if (unlikely(flags & NV_RX_ERROR)) { | |
1ef6841b | 2824 | if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) { |
b01867cb AA |
2825 | len = nv_getlen(dev, skb->data, len); |
2826 | if (len < 0) { | |
b01867cb AA |
2827 | dev_kfree_skb(skb); |
2828 | goto next_pkt; | |
2829 | } | |
2830 | } | |
2831 | /* framing errors are soft errors */ | |
1ef6841b | 2832 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
cef33c81 | 2833 | if (flags & NV_RX_SUBTRACT1) |
b01867cb | 2834 | len--; |
b01867cb AA |
2835 | } |
2836 | /* the rest are hard errors */ | |
2837 | else { | |
f5d827ae | 2838 | if (flags & NV_RX_MISSEDFRAME) { |
2839 | u64_stats_update_begin(&np->swstats_rx_syncp); | |
2840 | np->stat_rx_missed_errors++; | |
2841 | u64_stats_update_end(&np->swstats_rx_syncp); | |
2842 | } | |
0d63fb32 | 2843 | dev_kfree_skb(skb); |
a971c324 AA |
2844 | goto next_pkt; |
2845 | } | |
2846 | } | |
b01867cb | 2847 | } else { |
0d63fb32 | 2848 | dev_kfree_skb(skb); |
1da177e4 | 2849 | goto next_pkt; |
0d63fb32 | 2850 | } |
b01867cb AA |
2851 | } else { |
2852 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2853 | len = flags & LEN_MASK_V2; | |
2854 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2855 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2856 | len = nv_getlen(dev, skb->data, len); |
2857 | if (len < 0) { | |
b01867cb AA |
2858 | dev_kfree_skb(skb); |
2859 | goto next_pkt; | |
2860 | } | |
2861 | } | |
2862 | /* framing errors are soft errors */ | |
1ef6841b | 2863 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
cef33c81 | 2864 | if (flags & NV_RX2_SUBTRACT1) |
b01867cb | 2865 | len--; |
b01867cb AA |
2866 | } |
2867 | /* the rest are hard errors */ | |
2868 | else { | |
0d63fb32 | 2869 | dev_kfree_skb(skb); |
a971c324 AA |
2870 | goto next_pkt; |
2871 | } | |
2872 | } | |
bfaffe8f AA |
2873 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2874 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
0d63fb32 | 2875 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2876 | } else { |
2877 | dev_kfree_skb(skb); | |
2878 | goto next_pkt; | |
1da177e4 LT |
2879 | } |
2880 | } | |
2881 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2882 | skb_put(skb, len); |
2883 | skb->protocol = eth_type_trans(skb, dev); | |
53f224cc | 2884 | napi_gro_receive(&np->napi, skb); |
f5d827ae | 2885 | u64_stats_update_begin(&np->swstats_rx_syncp); |
2886 | np->stat_rx_packets++; | |
2887 | np->stat_rx_bytes += len; | |
2888 | u64_stats_update_end(&np->swstats_rx_syncp); | |
1da177e4 | 2889 | next_pkt: |
b01867cb | 2890 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 2891 | np->get_rx.orig = np->first_rx.orig; |
b01867cb | 2892 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 2893 | np->get_rx_ctx = np->first_rx_ctx; |
bcb5febb IM |
2894 | |
2895 | rx_work++; | |
86b22b0d AA |
2896 | } |
2897 | ||
bcb5febb | 2898 | return rx_work; |
86b22b0d AA |
2899 | } |
2900 | ||
2901 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2902 | { | |
2903 | struct fe_priv *np = netdev_priv(dev); | |
2904 | u32 flags; | |
2905 | u32 vlanflags = 0; | |
c1b7151a | 2906 | int rx_work = 0; |
b01867cb AA |
2907 | struct sk_buff *skb; |
2908 | int len; | |
86b22b0d | 2909 | |
78aea4fc | 2910 | while ((np->get_rx.ex != np->put_rx.ex) && |
b01867cb | 2911 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && |
c1b7151a | 2912 | (rx_work < limit)) { |
86b22b0d | 2913 | |
86b22b0d AA |
2914 | /* |
2915 | * the packet is for us - immediately tear down the pci mapping. | |
2916 | * TODO: check if a prefetch of the first cacheline improves | |
2917 | * the performance. | |
2918 | */ | |
2919 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, | |
2920 | np->get_rx_ctx->dma_len, | |
2921 | PCI_DMA_FROMDEVICE); | |
2922 | skb = np->get_rx_ctx->skb; | |
2923 | np->get_rx_ctx->skb = NULL; | |
2924 | ||
86b22b0d | 2925 | /* look at what we actually got: */ |
b01867cb AA |
2926 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2927 | len = flags & LEN_MASK_V2; | |
2928 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2929 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2930 | len = nv_getlen(dev, skb->data, len); |
2931 | if (len < 0) { | |
b01867cb AA |
2932 | dev_kfree_skb(skb); |
2933 | goto next_pkt; | |
2934 | } | |
2935 | } | |
2936 | /* framing errors are soft errors */ | |
1ef6841b | 2937 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
cef33c81 | 2938 | if (flags & NV_RX2_SUBTRACT1) |
b01867cb | 2939 | len--; |
b01867cb AA |
2940 | } |
2941 | /* the rest are hard errors */ | |
2942 | else { | |
86b22b0d AA |
2943 | dev_kfree_skb(skb); |
2944 | goto next_pkt; | |
2945 | } | |
2946 | } | |
b01867cb | 2947 | |
bfaffe8f AA |
2948 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2949 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
86b22b0d | 2950 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2951 | |
2952 | /* got a valid packet - forward it to the network core */ | |
2953 | skb_put(skb, len); | |
2954 | skb->protocol = eth_type_trans(skb, dev); | |
2955 | prefetch(skb->data); | |
2956 | ||
3326c784 | 2957 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); |
0891b0e0 JP |
2958 | |
2959 | /* | |
f646968f PM |
2960 | * There's need to check for NETIF_F_HW_VLAN_CTAG_RX |
2961 | * here. Even if vlan rx accel is disabled, | |
0891b0e0 JP |
2962 | * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set. |
2963 | */ | |
f646968f | 2964 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && |
0891b0e0 | 2965 | vlanflags & NV_RX3_VLAN_TAG_PRESENT) { |
3326c784 JP |
2966 | u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK; |
2967 | ||
86a9bad3 | 2968 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
b01867cb | 2969 | } |
3326c784 | 2970 | napi_gro_receive(&np->napi, skb); |
f5d827ae | 2971 | u64_stats_update_begin(&np->swstats_rx_syncp); |
2972 | np->stat_rx_packets++; | |
2973 | np->stat_rx_bytes += len; | |
2974 | u64_stats_update_end(&np->swstats_rx_syncp); | |
b01867cb AA |
2975 | } else { |
2976 | dev_kfree_skb(skb); | |
2977 | } | |
86b22b0d | 2978 | next_pkt: |
b01867cb | 2979 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 2980 | np->get_rx.ex = np->first_rx.ex; |
b01867cb | 2981 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
761fcd9e | 2982 | np->get_rx_ctx = np->first_rx_ctx; |
c1b7151a IM |
2983 | |
2984 | rx_work++; | |
1da177e4 | 2985 | } |
e27cdba5 | 2986 | |
c1b7151a | 2987 | return rx_work; |
1da177e4 LT |
2988 | } |
2989 | ||
d81c0983 MS |
2990 | static void set_bufsize(struct net_device *dev) |
2991 | { | |
2992 | struct fe_priv *np = netdev_priv(dev); | |
2993 | ||
2994 | if (dev->mtu <= ETH_DATA_LEN) | |
2995 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
2996 | else | |
2997 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
2998 | } | |
2999 | ||
1da177e4 LT |
3000 | /* |
3001 | * nv_change_mtu: dev->change_mtu function | |
3002 | * Called with dev_base_lock held for read. | |
3003 | */ | |
3004 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
3005 | { | |
ac9c1897 | 3006 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
3007 | int old_mtu; |
3008 | ||
d81c0983 | 3009 | old_mtu = dev->mtu; |
1da177e4 | 3010 | dev->mtu = new_mtu; |
d81c0983 MS |
3011 | |
3012 | /* return early if the buffer sizes will not change */ | |
3013 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
3014 | return 0; | |
d81c0983 MS |
3015 | |
3016 | /* synchronized against open : rtnl_lock() held by caller */ | |
3017 | if (netif_running(dev)) { | |
25097d4b | 3018 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
3019 | /* |
3020 | * It seems that the nic preloads valid ring entries into an | |
3021 | * internal buffer. The procedure for flushing everything is | |
3022 | * guessed, there is probably a simpler approach. | |
3023 | * Changing the MTU is a rare event, it shouldn't matter. | |
3024 | */ | |
84b3932b | 3025 | nv_disable_irq(dev); |
08d93575 | 3026 | nv_napi_disable(dev); |
932ff279 | 3027 | netif_tx_lock_bh(dev); |
e308a5d8 | 3028 | netif_addr_lock(dev); |
d81c0983 MS |
3029 | spin_lock(&np->lock); |
3030 | /* stop engines */ | |
36b30ea9 | 3031 | nv_stop_rxtx(dev); |
d81c0983 MS |
3032 | nv_txrx_reset(dev); |
3033 | /* drain rx queue */ | |
36b30ea9 | 3034 | nv_drain_rxtx(dev); |
d81c0983 | 3035 | /* reinit driver view of the rx queue */ |
d81c0983 | 3036 | set_bufsize(dev); |
eafa59f6 | 3037 | if (nv_init_ring(dev)) { |
d81c0983 MS |
3038 | if (!np->in_shutdown) |
3039 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3040 | } | |
3041 | /* reinit nic view of the rx queue */ | |
3042 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 3043 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 3044 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
3045 | base + NvRegRingSizes); |
3046 | pci_push(base); | |
8a4ae7f2 | 3047 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
3048 | pci_push(base); |
3049 | ||
3050 | /* restart rx engine */ | |
36b30ea9 | 3051 | nv_start_rxtx(dev); |
d81c0983 | 3052 | spin_unlock(&np->lock); |
e308a5d8 | 3053 | netif_addr_unlock(dev); |
932ff279 | 3054 | netif_tx_unlock_bh(dev); |
08d93575 | 3055 | nv_napi_enable(dev); |
84b3932b | 3056 | nv_enable_irq(dev); |
d81c0983 | 3057 | } |
1da177e4 LT |
3058 | return 0; |
3059 | } | |
3060 | ||
72b31782 MS |
3061 | static void nv_copy_mac_to_hw(struct net_device *dev) |
3062 | { | |
25097d4b | 3063 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
3064 | u32 mac[2]; |
3065 | ||
3066 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
3067 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
3068 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
3069 | ||
3070 | writel(mac[0], base + NvRegMacAddrA); | |
3071 | writel(mac[1], base + NvRegMacAddrB); | |
3072 | } | |
3073 | ||
3074 | /* | |
3075 | * nv_set_mac_address: dev->set_mac_address function | |
3076 | * Called with rtnl_lock() held. | |
3077 | */ | |
3078 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
3079 | { | |
ac9c1897 | 3080 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 3081 | struct sockaddr *macaddr = (struct sockaddr *)addr; |
72b31782 | 3082 | |
f82a9352 | 3083 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
3084 | return -EADDRNOTAVAIL; |
3085 | ||
3086 | /* synchronized against open : rtnl_lock() held by caller */ | |
3087 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
3088 | ||
3089 | if (netif_running(dev)) { | |
932ff279 | 3090 | netif_tx_lock_bh(dev); |
e308a5d8 | 3091 | netif_addr_lock(dev); |
72b31782 MS |
3092 | spin_lock_irq(&np->lock); |
3093 | ||
3094 | /* stop rx engine */ | |
3095 | nv_stop_rx(dev); | |
3096 | ||
3097 | /* set mac address */ | |
3098 | nv_copy_mac_to_hw(dev); | |
3099 | ||
3100 | /* restart rx engine */ | |
3101 | nv_start_rx(dev); | |
3102 | spin_unlock_irq(&np->lock); | |
e308a5d8 | 3103 | netif_addr_unlock(dev); |
932ff279 | 3104 | netif_tx_unlock_bh(dev); |
72b31782 MS |
3105 | } else { |
3106 | nv_copy_mac_to_hw(dev); | |
3107 | } | |
3108 | return 0; | |
3109 | } | |
3110 | ||
1da177e4 LT |
3111 | /* |
3112 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 3113 | * Called with netif_tx_lock held. |
1da177e4 LT |
3114 | */ |
3115 | static void nv_set_multicast(struct net_device *dev) | |
3116 | { | |
ac9c1897 | 3117 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3118 | u8 __iomem *base = get_hwbase(dev); |
3119 | u32 addr[2]; | |
3120 | u32 mask[2]; | |
b6d0773f | 3121 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
3122 | |
3123 | memset(addr, 0, sizeof(addr)); | |
3124 | memset(mask, 0, sizeof(mask)); | |
3125 | ||
3126 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 3127 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 3128 | } else { |
b6d0773f | 3129 | pff |= NVREG_PFF_MYADDR; |
1da177e4 | 3130 | |
48e2f183 | 3131 | if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) { |
1da177e4 LT |
3132 | u32 alwaysOff[2]; |
3133 | u32 alwaysOn[2]; | |
3134 | ||
3135 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
3136 | if (dev->flags & IFF_ALLMULTI) { | |
3137 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
3138 | } else { | |
22bedad3 | 3139 | struct netdev_hw_addr *ha; |
1da177e4 | 3140 | |
22bedad3 | 3141 | netdev_for_each_mc_addr(ha, dev) { |
e45a6187 | 3142 | unsigned char *hw_addr = ha->addr; |
1da177e4 | 3143 | u32 a, b; |
22bedad3 | 3144 | |
e45a6187 | 3145 | a = le32_to_cpu(*(__le32 *) hw_addr); |
3146 | b = le16_to_cpu(*(__le16 *) (&hw_addr[4])); | |
1da177e4 LT |
3147 | alwaysOn[0] &= a; |
3148 | alwaysOff[0] &= ~a; | |
3149 | alwaysOn[1] &= b; | |
3150 | alwaysOff[1] &= ~b; | |
1da177e4 LT |
3151 | } |
3152 | } | |
3153 | addr[0] = alwaysOn[0]; | |
3154 | addr[1] = alwaysOn[1]; | |
3155 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
3156 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
bb9a4fd1 AA |
3157 | } else { |
3158 | mask[0] = NVREG_MCASTMASKA_NONE; | |
3159 | mask[1] = NVREG_MCASTMASKB_NONE; | |
1da177e4 LT |
3160 | } |
3161 | } | |
3162 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
3163 | pff |= NVREG_PFF_ALWAYS; | |
3164 | spin_lock_irq(&np->lock); | |
3165 | nv_stop_rx(dev); | |
3166 | writel(addr[0], base + NvRegMulticastAddrA); | |
3167 | writel(addr[1], base + NvRegMulticastAddrB); | |
3168 | writel(mask[0], base + NvRegMulticastMaskA); | |
3169 | writel(mask[1], base + NvRegMulticastMaskB); | |
3170 | writel(pff, base + NvRegPacketFilterFlags); | |
1da177e4 LT |
3171 | nv_start_rx(dev); |
3172 | spin_unlock_irq(&np->lock); | |
3173 | } | |
3174 | ||
c7985051 | 3175 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
3176 | { |
3177 | struct fe_priv *np = netdev_priv(dev); | |
3178 | u8 __iomem *base = get_hwbase(dev); | |
3179 | ||
3180 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
3181 | ||
3182 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
3183 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
3184 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
3185 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
3186 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3187 | } else { | |
3188 | writel(pff, base + NvRegPacketFilterFlags); | |
3189 | } | |
3190 | } | |
3191 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
3192 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
3193 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
5289b4c4 AA |
3194 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
3195 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | |
3196 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | |
9a33e883 | 3197 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { |
5289b4c4 | 3198 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; |
9a33e883 AA |
3199 | /* limit the number of tx pause frames to a default of 8 */ |
3200 | writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); | |
3201 | } | |
5289b4c4 | 3202 | writel(pause_enable, base + NvRegTxPauseFrame); |
b6d0773f AA |
3203 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
3204 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3205 | } else { | |
3206 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
3207 | writel(regmisc, base + NvRegMisc1); | |
3208 | } | |
3209 | } | |
3210 | } | |
3211 | ||
e19df76a SH |
3212 | static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex) |
3213 | { | |
3214 | struct fe_priv *np = netdev_priv(dev); | |
3215 | u8 __iomem *base = get_hwbase(dev); | |
3216 | u32 phyreg, txreg; | |
3217 | int mii_status; | |
3218 | ||
3219 | np->linkspeed = NVREG_LINKSPEED_FORCE|speed; | |
3220 | np->duplex = duplex; | |
3221 | ||
3222 | /* see if gigabit phy */ | |
3223 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3224 | if (mii_status & PHY_GIGABIT) { | |
3225 | np->gigabit = PHY_GIGABIT; | |
3226 | phyreg = readl(base + NvRegSlotTime); | |
3227 | phyreg &= ~(0x3FF00); | |
3228 | if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) | |
3229 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
3230 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) | |
3231 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
3232 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) | |
3233 | phyreg |= NVREG_SLOTTIME_1000_FULL; | |
3234 | writel(phyreg, base + NvRegSlotTime); | |
3235 | } | |
3236 | ||
3237 | phyreg = readl(base + NvRegPhyInterface); | |
3238 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3239 | if (np->duplex == 0) | |
3240 | phyreg |= PHY_HALF; | |
3241 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3242 | phyreg |= PHY_100; | |
3243 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == | |
3244 | NVREG_LINKSPEED_1000) | |
3245 | phyreg |= PHY_1000; | |
3246 | writel(phyreg, base + NvRegPhyInterface); | |
3247 | ||
3248 | if (phyreg & PHY_RGMII) { | |
3249 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == | |
3250 | NVREG_LINKSPEED_1000) | |
3251 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; | |
3252 | else | |
3253 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3254 | } else { | |
3255 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
3256 | } | |
3257 | writel(txreg, base + NvRegTxDeferral); | |
3258 | ||
3259 | if (np->desc_ver == DESC_VER_1) { | |
3260 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3261 | } else { | |
3262 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == | |
3263 | NVREG_LINKSPEED_1000) | |
3264 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3265 | else | |
3266 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3267 | } | |
3268 | writel(txreg, base + NvRegTxWatermark); | |
3269 | ||
3270 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), | |
3271 | base + NvRegMisc1); | |
3272 | pci_push(base); | |
3273 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3274 | pci_push(base); | |
e19df76a SH |
3275 | } |
3276 | ||
4ea7f299 | 3277 | /** |
49ce9c2c | 3278 | * nv_update_linkspeed - Setup the MAC according to the link partner |
4ea7f299 AA |
3279 | * @dev: Network device to be configured |
3280 | * | |
3281 | * The function queries the PHY and checks if there is a link partner. | |
3282 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
3283 | * set to 10 MBit HD. | |
3284 | * | |
3285 | * The function returns 0 if there is no link partner and 1 if there is | |
3286 | * a good link partner. | |
3287 | */ | |
1da177e4 LT |
3288 | static int nv_update_linkspeed(struct net_device *dev) |
3289 | { | |
ac9c1897 | 3290 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3291 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
3292 | int adv = 0; |
3293 | int lpa = 0; | |
3294 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
3295 | int newls = np->linkspeed; |
3296 | int newdup = np->duplex; | |
3297 | int mii_status; | |
e19df76a | 3298 | u32 bmcr; |
1da177e4 | 3299 | int retval = 0; |
9744e218 | 3300 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
b2976d23 | 3301 | u32 txrxFlags = 0; |
fd9b558c | 3302 | u32 phy_exp; |
1da177e4 | 3303 | |
e19df76a SH |
3304 | /* If device loopback is enabled, set carrier on and enable max link |
3305 | * speed. | |
3306 | */ | |
3307 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
3308 | if (bmcr & BMCR_LOOPBACK) { | |
3309 | if (netif_running(dev)) { | |
3310 | nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1); | |
3311 | if (!netif_carrier_ok(dev)) | |
3312 | netif_carrier_on(dev); | |
3313 | } | |
3314 | return 1; | |
3315 | } | |
3316 | ||
1da177e4 LT |
3317 | /* BMSR_LSTATUS is latched, read it twice: |
3318 | * we want the current value. | |
3319 | */ | |
3320 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3321 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3322 | ||
3323 | if (!(mii_status & BMSR_LSTATUS)) { | |
1da177e4 LT |
3324 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3325 | newdup = 0; | |
3326 | retval = 0; | |
3327 | goto set_speed; | |
3328 | } | |
3329 | ||
3330 | if (np->autoneg == 0) { | |
1da177e4 LT |
3331 | if (np->fixed_mode & LPA_100FULL) { |
3332 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3333 | newdup = 1; | |
3334 | } else if (np->fixed_mode & LPA_100HALF) { | |
3335 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3336 | newdup = 0; | |
3337 | } else if (np->fixed_mode & LPA_10FULL) { | |
3338 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3339 | newdup = 1; | |
3340 | } else { | |
3341 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3342 | newdup = 0; | |
3343 | } | |
3344 | retval = 1; | |
3345 | goto set_speed; | |
3346 | } | |
3347 | /* check auto negotiation is complete */ | |
3348 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
3349 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
3350 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3351 | newdup = 0; | |
3352 | retval = 0; | |
1da177e4 LT |
3353 | goto set_speed; |
3354 | } | |
3355 | ||
b6d0773f AA |
3356 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
3357 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
b6d0773f | 3358 | |
1da177e4 LT |
3359 | retval = 1; |
3360 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
3361 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
3362 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
3363 | |
3364 | if ((control_1000 & ADVERTISE_1000FULL) && | |
3365 | (status_1000 & LPA_1000FULL)) { | |
1da177e4 LT |
3366 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
3367 | newdup = 1; | |
3368 | goto set_speed; | |
3369 | } | |
3370 | } | |
3371 | ||
1da177e4 | 3372 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
3373 | adv_lpa = lpa & adv; |
3374 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
3375 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3376 | newdup = 1; | |
eb91f61b | 3377 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
3378 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3379 | newdup = 0; | |
eb91f61b | 3380 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
3381 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3382 | newdup = 1; | |
eb91f61b | 3383 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
3384 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3385 | newdup = 0; | |
3386 | } else { | |
1da177e4 LT |
3387 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3388 | newdup = 0; | |
3389 | } | |
3390 | ||
3391 | set_speed: | |
3392 | if (np->duplex == newdup && np->linkspeed == newls) | |
3393 | return retval; | |
3394 | ||
1da177e4 LT |
3395 | np->duplex = newdup; |
3396 | np->linkspeed = newls; | |
3397 | ||
b2976d23 AA |
3398 | /* The transmitter and receiver must be restarted for safe update */ |
3399 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { | |
3400 | txrxFlags |= NV_RESTART_TX; | |
3401 | nv_stop_tx(dev); | |
3402 | } | |
3403 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
3404 | txrxFlags |= NV_RESTART_RX; | |
3405 | nv_stop_rx(dev); | |
3406 | } | |
3407 | ||
1da177e4 | 3408 | if (np->gigabit == PHY_GIGABIT) { |
a433686c | 3409 | phyreg = readl(base + NvRegSlotTime); |
1da177e4 | 3410 | phyreg &= ~(0x3FF00); |
a433686c AA |
3411 | if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || |
3412 | ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) | |
3413 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
1da177e4 | 3414 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
a433686c AA |
3415 | phyreg |= NVREG_SLOTTIME_1000_FULL; |
3416 | writel(phyreg, base + NvRegSlotTime); | |
1da177e4 LT |
3417 | } |
3418 | ||
3419 | phyreg = readl(base + NvRegPhyInterface); | |
3420 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3421 | if (np->duplex == 0) | |
3422 | phyreg |= PHY_HALF; | |
3423 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3424 | phyreg |= PHY_100; | |
3425 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3426 | phyreg |= PHY_1000; | |
3427 | writel(phyreg, base + NvRegPhyInterface); | |
3428 | ||
fd9b558c | 3429 | phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ |
9744e218 | 3430 | if (phyreg & PHY_RGMII) { |
fd9b558c | 3431 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { |
9744e218 | 3432 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
fd9b558c AA |
3433 | } else { |
3434 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { | |
3435 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) | |
3436 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; | |
3437 | else | |
3438 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; | |
3439 | } else { | |
3440 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3441 | } | |
3442 | } | |
9744e218 | 3443 | } else { |
fd9b558c AA |
3444 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) |
3445 | txreg = NVREG_TX_DEFERRAL_MII_STRETCH; | |
3446 | else | |
3447 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
9744e218 AA |
3448 | } |
3449 | writel(txreg, base + NvRegTxDeferral); | |
3450 | ||
95d161cb AA |
3451 | if (np->desc_ver == DESC_VER_1) { |
3452 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3453 | } else { | |
3454 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3455 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3456 | else | |
3457 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3458 | } | |
3459 | writel(txreg, base + NvRegTxWatermark); | |
3460 | ||
78aea4fc | 3461 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), |
1da177e4 LT |
3462 | base + NvRegMisc1); |
3463 | pci_push(base); | |
3464 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3465 | pci_push(base); | |
3466 | ||
b6d0773f AA |
3467 | pause_flags = 0; |
3468 | /* setup pause frame */ | |
1ff39eb6 | 3469 | if (netif_running(dev) && (np->duplex != 0)) { |
b6d0773f | 3470 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
78aea4fc SJ |
3471 | adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
3472 | lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM); | |
b6d0773f AA |
3473 | |
3474 | switch (adv_pause) { | |
f82a9352 | 3475 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
3476 | if (lpa_pause & LPA_PAUSE_CAP) { |
3477 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3478 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3479 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3480 | } | |
3481 | break; | |
f82a9352 | 3482 | case ADVERTISE_PAUSE_ASYM: |
78aea4fc | 3483 | if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM)) |
b6d0773f | 3484 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
b6d0773f | 3485 | break; |
78aea4fc SJ |
3486 | case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM: |
3487 | if (lpa_pause & LPA_PAUSE_CAP) { | |
b6d0773f AA |
3488 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3489 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3490 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3491 | } | |
3492 | if (lpa_pause == LPA_PAUSE_ASYM) | |
b6d0773f | 3493 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
b6d0773f | 3494 | break; |
f3b197ac | 3495 | } |
eb91f61b | 3496 | } else { |
b6d0773f | 3497 | pause_flags = np->pause_flags; |
eb91f61b AA |
3498 | } |
3499 | } | |
b6d0773f | 3500 | nv_update_pause(dev, pause_flags); |
eb91f61b | 3501 | |
b2976d23 AA |
3502 | if (txrxFlags & NV_RESTART_TX) |
3503 | nv_start_tx(dev); | |
3504 | if (txrxFlags & NV_RESTART_RX) | |
3505 | nv_start_rx(dev); | |
3506 | ||
1da177e4 LT |
3507 | return retval; |
3508 | } | |
3509 | ||
3510 | static void nv_linkchange(struct net_device *dev) | |
3511 | { | |
3512 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 3513 | if (!netif_carrier_ok(dev)) { |
1da177e4 | 3514 | netif_carrier_on(dev); |
1d397f36 | 3515 | netdev_info(dev, "link up\n"); |
88d7d8b0 | 3516 | nv_txrx_gate(dev, false); |
4ea7f299 | 3517 | nv_start_rx(dev); |
1da177e4 | 3518 | } |
1da177e4 LT |
3519 | } else { |
3520 | if (netif_carrier_ok(dev)) { | |
3521 | netif_carrier_off(dev); | |
1d397f36 | 3522 | netdev_info(dev, "link down\n"); |
88d7d8b0 | 3523 | nv_txrx_gate(dev, true); |
1da177e4 LT |
3524 | nv_stop_rx(dev); |
3525 | } | |
3526 | } | |
3527 | } | |
3528 | ||
3529 | static void nv_link_irq(struct net_device *dev) | |
3530 | { | |
3531 | u8 __iomem *base = get_hwbase(dev); | |
3532 | u32 miistat; | |
3533 | ||
3534 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 3535 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
1da177e4 LT |
3536 | |
3537 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
3538 | nv_linkchange(dev); | |
1da177e4 LT |
3539 | } |
3540 | ||
4db0ee17 AA |
3541 | static void nv_msi_workaround(struct fe_priv *np) |
3542 | { | |
3543 | ||
3544 | /* Need to toggle the msi irq mask within the ethernet device, | |
3545 | * otherwise, future interrupts will not be detected. | |
3546 | */ | |
3547 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3548 | u8 __iomem *base = np->base; | |
3549 | ||
3550 | writel(0, base + NvRegMSIIrqMask); | |
3551 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3552 | } | |
3553 | } | |
3554 | ||
4145ade2 AA |
3555 | static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work) |
3556 | { | |
3557 | struct fe_priv *np = netdev_priv(dev); | |
3558 | ||
3559 | if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) { | |
3560 | if (total_work > NV_DYNAMIC_THRESHOLD) { | |
3561 | /* transition to poll based interrupts */ | |
3562 | np->quiet_count = 0; | |
3563 | if (np->irqmask != NVREG_IRQMASK_CPU) { | |
3564 | np->irqmask = NVREG_IRQMASK_CPU; | |
3565 | return 1; | |
3566 | } | |
3567 | } else { | |
3568 | if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) { | |
3569 | np->quiet_count++; | |
3570 | } else { | |
3571 | /* reached a period of low activity, switch | |
3572 | to per tx/rx packet interrupts */ | |
3573 | if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { | |
3574 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
3575 | return 1; | |
3576 | } | |
3577 | } | |
3578 | } | |
3579 | } | |
3580 | return 0; | |
3581 | } | |
3582 | ||
7d12e780 | 3583 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
3584 | { |
3585 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3586 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3587 | u8 __iomem *base = get_hwbase(dev); |
1da177e4 | 3588 | |
b67874ac AA |
3589 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3590 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3591 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3592 | } else { |
3593 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3594 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3595 | } |
b67874ac AA |
3596 | if (!(np->events & np->irqmask)) |
3597 | return IRQ_NONE; | |
1da177e4 | 3598 | |
b67874ac | 3599 | nv_msi_workaround(np); |
4db0ee17 | 3600 | |
78c29bd9 ED |
3601 | if (napi_schedule_prep(&np->napi)) { |
3602 | /* | |
3603 | * Disable further irq's (msix not enabled with napi) | |
3604 | */ | |
3605 | writel(0, base + NvRegIrqMask); | |
3606 | __napi_schedule(&np->napi); | |
3607 | } | |
f0734ab6 | 3608 | |
b67874ac | 3609 | return IRQ_HANDLED; |
1da177e4 LT |
3610 | } |
3611 | ||
1aa8b471 | 3612 | /* All _optimized functions are used to help increase performance |
f0734ab6 AA |
3613 | * (reduce CPU and increase throughput). They use descripter version 3, |
3614 | * compiler directives, and reduce memory accesses. | |
3615 | */ | |
86b22b0d AA |
3616 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
3617 | { | |
3618 | struct net_device *dev = (struct net_device *) data; | |
3619 | struct fe_priv *np = netdev_priv(dev); | |
3620 | u8 __iomem *base = get_hwbase(dev); | |
86b22b0d | 3621 | |
b67874ac AA |
3622 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3623 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3624 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3625 | } else { |
3626 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3627 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3628 | } |
b67874ac AA |
3629 | if (!(np->events & np->irqmask)) |
3630 | return IRQ_NONE; | |
86b22b0d | 3631 | |
b67874ac | 3632 | nv_msi_workaround(np); |
4db0ee17 | 3633 | |
78c29bd9 ED |
3634 | if (napi_schedule_prep(&np->napi)) { |
3635 | /* | |
3636 | * Disable further irq's (msix not enabled with napi) | |
3637 | */ | |
3638 | writel(0, base + NvRegIrqMask); | |
3639 | __napi_schedule(&np->napi); | |
3640 | } | |
86b22b0d | 3641 | |
b67874ac | 3642 | return IRQ_HANDLED; |
86b22b0d AA |
3643 | } |
3644 | ||
7d12e780 | 3645 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
3646 | { |
3647 | struct net_device *dev = (struct net_device *) data; | |
3648 | struct fe_priv *np = netdev_priv(dev); | |
3649 | u8 __iomem *base = get_hwbase(dev); | |
3650 | u32 events; | |
3651 | int i; | |
0a07bc64 | 3652 | unsigned long flags; |
d33a73c8 | 3653 | |
78aea4fc | 3654 | for (i = 0;; i++) { |
d33a73c8 | 3655 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
2a4e7a08 MD |
3656 | writel(events, base + NvRegMSIXIrqStatus); |
3657 | netdev_dbg(dev, "tx irq events: %08x\n", events); | |
d33a73c8 AA |
3658 | if (!(events & np->irqmask)) |
3659 | break; | |
3660 | ||
0a07bc64 | 3661 | spin_lock_irqsave(&np->lock, flags); |
4e16ed1b | 3662 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
0a07bc64 | 3663 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3664 | |
f0734ab6 | 3665 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3666 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3667 | /* disable interrupts on the nic */ |
3668 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3669 | pci_push(base); | |
3670 | ||
3671 | if (!np->in_shutdown) { | |
3672 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3673 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3674 | } | |
0a07bc64 | 3675 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3676 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3677 | __func__, i); | |
d33a73c8 AA |
3678 | break; |
3679 | } | |
3680 | ||
3681 | } | |
d33a73c8 AA |
3682 | |
3683 | return IRQ_RETVAL(i); | |
3684 | } | |
3685 | ||
bea3348e | 3686 | static int nv_napi_poll(struct napi_struct *napi, int budget) |
e27cdba5 | 3687 | { |
bea3348e SH |
3688 | struct fe_priv *np = container_of(napi, struct fe_priv, napi); |
3689 | struct net_device *dev = np->dev; | |
e27cdba5 | 3690 | u8 __iomem *base = get_hwbase(dev); |
d15e9c4d | 3691 | unsigned long flags; |
4145ade2 | 3692 | int retcode; |
78aea4fc | 3693 | int rx_count, tx_work = 0, rx_work = 0; |
e27cdba5 | 3694 | |
81a2e36d | 3695 | do { |
3696 | if (!nv_optimized(np)) { | |
3697 | spin_lock_irqsave(&np->lock, flags); | |
3698 | tx_work += nv_tx_done(dev, np->tx_ring_size); | |
3699 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3700 | |
d951f725 | 3701 | rx_count = nv_rx_process(dev, budget - rx_work); |
81a2e36d | 3702 | retcode = nv_alloc_rx(dev); |
3703 | } else { | |
3704 | spin_lock_irqsave(&np->lock, flags); | |
3705 | tx_work += nv_tx_done_optimized(dev, np->tx_ring_size); | |
3706 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3707 | |
d951f725 TH |
3708 | rx_count = nv_rx_process_optimized(dev, |
3709 | budget - rx_work); | |
81a2e36d | 3710 | retcode = nv_alloc_rx_optimized(dev); |
3711 | } | |
3712 | } while (retcode == 0 && | |
3713 | rx_count > 0 && (rx_work += rx_count) < budget); | |
e27cdba5 | 3714 | |
e0379a14 | 3715 | if (retcode) { |
d15e9c4d | 3716 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3717 | if (!np->in_shutdown) |
3718 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3719 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3720 | } |
3721 | ||
4145ade2 AA |
3722 | nv_change_interrupt_mode(dev, tx_work + rx_work); |
3723 | ||
f27e6f39 AA |
3724 | if (unlikely(np->events & NVREG_IRQ_LINK)) { |
3725 | spin_lock_irqsave(&np->lock, flags); | |
3726 | nv_link_irq(dev); | |
3727 | spin_unlock_irqrestore(&np->lock, flags); | |
3728 | } | |
3729 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { | |
3730 | spin_lock_irqsave(&np->lock, flags); | |
3731 | nv_linkchange(dev); | |
3732 | spin_unlock_irqrestore(&np->lock, flags); | |
3733 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3734 | } | |
3735 | if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) { | |
3736 | spin_lock_irqsave(&np->lock, flags); | |
3737 | if (!np->in_shutdown) { | |
3738 | np->nic_poll_irq = np->irqmask; | |
3739 | np->recover_error = 1; | |
3740 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3741 | } | |
3742 | spin_unlock_irqrestore(&np->lock, flags); | |
6c2da9c2 | 3743 | napi_complete(napi); |
4145ade2 | 3744 | return rx_work; |
f27e6f39 AA |
3745 | } |
3746 | ||
4145ade2 | 3747 | if (rx_work < budget) { |
f27e6f39 AA |
3748 | /* re-enable interrupts |
3749 | (msix not enabled in napi) */ | |
6ad20165 | 3750 | napi_complete_done(napi, rx_work); |
bea3348e | 3751 | |
f27e6f39 | 3752 | writel(np->irqmask, base + NvRegIrqMask); |
e27cdba5 | 3753 | } |
4145ade2 | 3754 | return rx_work; |
e27cdba5 | 3755 | } |
e27cdba5 | 3756 | |
7d12e780 | 3757 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3758 | { |
3759 | struct net_device *dev = (struct net_device *) data; | |
3760 | struct fe_priv *np = netdev_priv(dev); | |
3761 | u8 __iomem *base = get_hwbase(dev); | |
3762 | u32 events; | |
3763 | int i; | |
0a07bc64 | 3764 | unsigned long flags; |
d33a73c8 | 3765 | |
78aea4fc | 3766 | for (i = 0;; i++) { |
d33a73c8 | 3767 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
2a4e7a08 MD |
3768 | writel(events, base + NvRegMSIXIrqStatus); |
3769 | netdev_dbg(dev, "rx irq events: %08x\n", events); | |
d33a73c8 AA |
3770 | if (!(events & np->irqmask)) |
3771 | break; | |
f3b197ac | 3772 | |
bea3348e | 3773 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3774 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3775 | spin_lock_irqsave(&np->lock, flags); | |
3776 | if (!np->in_shutdown) | |
3777 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3778 | spin_unlock_irqrestore(&np->lock, flags); | |
3779 | } | |
d33a73c8 | 3780 | } |
f3b197ac | 3781 | |
f0734ab6 | 3782 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3783 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3784 | /* disable interrupts on the nic */ |
3785 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3786 | pci_push(base); | |
3787 | ||
3788 | if (!np->in_shutdown) { | |
3789 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3790 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3791 | } | |
0a07bc64 | 3792 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3793 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3794 | __func__, i); | |
d33a73c8 AA |
3795 | break; |
3796 | } | |
d33a73c8 | 3797 | } |
d33a73c8 AA |
3798 | |
3799 | return IRQ_RETVAL(i); | |
3800 | } | |
3801 | ||
7d12e780 | 3802 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3803 | { |
3804 | struct net_device *dev = (struct net_device *) data; | |
3805 | struct fe_priv *np = netdev_priv(dev); | |
3806 | u8 __iomem *base = get_hwbase(dev); | |
3807 | u32 events; | |
3808 | int i; | |
0a07bc64 | 3809 | unsigned long flags; |
d33a73c8 | 3810 | |
78aea4fc | 3811 | for (i = 0;; i++) { |
d33a73c8 | 3812 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
2a4e7a08 MD |
3813 | writel(events, base + NvRegMSIXIrqStatus); |
3814 | netdev_dbg(dev, "irq events: %08x\n", events); | |
d33a73c8 AA |
3815 | if (!(events & np->irqmask)) |
3816 | break; | |
f3b197ac | 3817 | |
4e16ed1b AA |
3818 | /* check tx in case we reached max loop limit in tx isr */ |
3819 | spin_lock_irqsave(&np->lock, flags); | |
3820 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); | |
3821 | spin_unlock_irqrestore(&np->lock, flags); | |
3822 | ||
d33a73c8 | 3823 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3824 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3825 | nv_link_irq(dev); |
0a07bc64 | 3826 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3827 | } |
3828 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3829 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3830 | nv_linkchange(dev); |
0a07bc64 | 3831 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3832 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3833 | } | |
c5cf9101 | 3834 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
186e8687 | 3835 | spin_lock_irqsave(&np->lock, flags); |
c5cf9101 AA |
3836 | /* disable interrupts on the nic */ |
3837 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3838 | pci_push(base); | |
3839 | ||
3840 | if (!np->in_shutdown) { | |
3841 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3842 | np->recover_error = 1; | |
3843 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3844 | } | |
186e8687 | 3845 | spin_unlock_irqrestore(&np->lock, flags); |
c5cf9101 AA |
3846 | break; |
3847 | } | |
f0734ab6 | 3848 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3849 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3850 | /* disable interrupts on the nic */ |
3851 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3852 | pci_push(base); | |
3853 | ||
3854 | if (!np->in_shutdown) { | |
3855 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3856 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3857 | } | |
0a07bc64 | 3858 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3859 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3860 | __func__, i); | |
d33a73c8 AA |
3861 | break; |
3862 | } | |
3863 | ||
3864 | } | |
d33a73c8 AA |
3865 | |
3866 | return IRQ_RETVAL(i); | |
3867 | } | |
3868 | ||
7d12e780 | 3869 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3870 | { |
3871 | struct net_device *dev = (struct net_device *) data; | |
3872 | struct fe_priv *np = netdev_priv(dev); | |
3873 | u8 __iomem *base = get_hwbase(dev); | |
3874 | u32 events; | |
3875 | ||
9589c77a AA |
3876 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3877 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
2a4e7a08 | 3878 | writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus); |
9589c77a AA |
3879 | } else { |
3880 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2a4e7a08 | 3881 | writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); |
9589c77a AA |
3882 | } |
3883 | pci_push(base); | |
9589c77a AA |
3884 | if (!(events & NVREG_IRQ_TIMER)) |
3885 | return IRQ_RETVAL(0); | |
3886 | ||
4db0ee17 AA |
3887 | nv_msi_workaround(np); |
3888 | ||
9589c77a AA |
3889 | spin_lock(&np->lock); |
3890 | np->intr_test = 1; | |
3891 | spin_unlock(&np->lock); | |
3892 | ||
9589c77a AA |
3893 | return IRQ_RETVAL(1); |
3894 | } | |
3895 | ||
7a1854b7 AA |
3896 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3897 | { | |
3898 | u8 __iomem *base = get_hwbase(dev); | |
3899 | int i; | |
3900 | u32 msixmap = 0; | |
3901 | ||
3902 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3903 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3904 | * the remaining 8 interrupts. | |
3905 | */ | |
3906 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3907 | if ((irqmask >> i) & 0x1) |
7a1854b7 | 3908 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3909 | } |
3910 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3911 | ||
3912 | msixmap = 0; | |
3913 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3914 | if ((irqmask >> (i + 8)) & 0x1) |
7a1854b7 | 3915 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3916 | } |
3917 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3918 | } | |
3919 | ||
9589c77a | 3920 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3921 | { |
3922 | struct fe_priv *np = get_nvpriv(dev); | |
3923 | u8 __iomem *base = get_hwbase(dev); | |
d9bd00a1 | 3924 | int ret; |
7a1854b7 | 3925 | int i; |
86b22b0d AA |
3926 | irqreturn_t (*handler)(int foo, void *data); |
3927 | ||
3928 | if (intr_test) { | |
3929 | handler = nv_nic_irq_test; | |
3930 | } else { | |
36b30ea9 | 3931 | if (nv_optimized(np)) |
86b22b0d AA |
3932 | handler = nv_nic_irq_optimized; |
3933 | else | |
3934 | handler = nv_nic_irq; | |
3935 | } | |
7a1854b7 AA |
3936 | |
3937 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
78aea4fc | 3938 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3939 | np->msi_x_entry[i].entry = i; |
04698ef3 AG |
3940 | ret = pci_enable_msix_range(np->pci_dev, |
3941 | np->msi_x_entry, | |
3942 | np->msi_flags & NV_MSI_X_VECTORS_MASK, | |
3943 | np->msi_flags & NV_MSI_X_VECTORS_MASK); | |
3944 | if (ret > 0) { | |
7a1854b7 | 3945 | np->msi_flags |= NV_MSI_X_ENABLED; |
9589c77a | 3946 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3947 | /* Request irq for rx handling */ |
ddb213f0 | 3948 | sprintf(np->name_rx, "%s-rx", dev->name); |
61c9471e AG |
3949 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, |
3950 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev); | |
3951 | if (ret) { | |
1d397f36 JP |
3952 | netdev_info(dev, |
3953 | "request_irq failed for rx %d\n", | |
3954 | ret); | |
7a1854b7 AA |
3955 | pci_disable_msix(np->pci_dev); |
3956 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3957 | goto out_err; | |
3958 | } | |
3959 | /* Request irq for tx handling */ | |
ddb213f0 | 3960 | sprintf(np->name_tx, "%s-tx", dev->name); |
61c9471e AG |
3961 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, |
3962 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev); | |
3963 | if (ret) { | |
1d397f36 JP |
3964 | netdev_info(dev, |
3965 | "request_irq failed for tx %d\n", | |
3966 | ret); | |
7a1854b7 AA |
3967 | pci_disable_msix(np->pci_dev); |
3968 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3969 | goto out_free_rx; | |
3970 | } | |
3971 | /* Request irq for link and timer handling */ | |
ddb213f0 | 3972 | sprintf(np->name_other, "%s-other", dev->name); |
61c9471e AG |
3973 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, |
3974 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev); | |
3975 | if (ret) { | |
1d397f36 JP |
3976 | netdev_info(dev, |
3977 | "request_irq failed for link %d\n", | |
3978 | ret); | |
7a1854b7 AA |
3979 | pci_disable_msix(np->pci_dev); |
3980 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3981 | goto out_free_tx; | |
3982 | } | |
3983 | /* map interrupts to their respective vector */ | |
3984 | writel(0, base + NvRegMSIXMap0); | |
3985 | writel(0, base + NvRegMSIXMap1); | |
3986 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
3987 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
3988 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
3989 | } else { | |
3990 | /* Request irq for all interrupts */ | |
61c9471e AG |
3991 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, |
3992 | handler, IRQF_SHARED, dev->name, dev); | |
3993 | if (ret) { | |
1d397f36 JP |
3994 | netdev_info(dev, |
3995 | "request_irq failed %d\n", | |
3996 | ret); | |
7a1854b7 AA |
3997 | pci_disable_msix(np->pci_dev); |
3998 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3999 | goto out_err; | |
4000 | } | |
4001 | ||
4002 | /* map interrupts to vector 0 */ | |
4003 | writel(0, base + NvRegMSIXMap0); | |
4004 | writel(0, base + NvRegMSIXMap1); | |
4005 | } | |
89328783 | 4006 | netdev_info(dev, "MSI-X enabled\n"); |
d9bd00a1 | 4007 | return 0; |
7a1854b7 AA |
4008 | } |
4009 | } | |
d9bd00a1 | 4010 | if (np->msi_flags & NV_MSI_CAPABLE) { |
34cf97eb SJ |
4011 | ret = pci_enable_msi(np->pci_dev); |
4012 | if (ret == 0) { | |
7a1854b7 | 4013 | np->msi_flags |= NV_MSI_ENABLED; |
61c9471e AG |
4014 | ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev); |
4015 | if (ret) { | |
1d397f36 JP |
4016 | netdev_info(dev, "request_irq failed %d\n", |
4017 | ret); | |
7a1854b7 AA |
4018 | pci_disable_msi(np->pci_dev); |
4019 | np->msi_flags &= ~NV_MSI_ENABLED; | |
4020 | goto out_err; | |
4021 | } | |
4022 | ||
4023 | /* map interrupts to vector 0 */ | |
4024 | writel(0, base + NvRegMSIMap0); | |
4025 | writel(0, base + NvRegMSIMap1); | |
4026 | /* enable msi vector 0 */ | |
4027 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
89328783 | 4028 | netdev_info(dev, "MSI enabled\n"); |
d9bd00a1 | 4029 | return 0; |
7a1854b7 AA |
4030 | } |
4031 | } | |
9589c77a | 4032 | |
d9bd00a1 AG |
4033 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
4034 | goto out_err; | |
7a1854b7 AA |
4035 | |
4036 | return 0; | |
4037 | out_free_tx: | |
4038 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
4039 | out_free_rx: | |
4040 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
4041 | out_err: | |
4042 | return 1; | |
4043 | } | |
4044 | ||
4045 | static void nv_free_irq(struct net_device *dev) | |
4046 | { | |
4047 | struct fe_priv *np = get_nvpriv(dev); | |
4048 | int i; | |
4049 | ||
4050 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
78aea4fc | 4051 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 4052 | free_irq(np->msi_x_entry[i].vector, dev); |
7a1854b7 AA |
4053 | pci_disable_msix(np->pci_dev); |
4054 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
4055 | } else { | |
4056 | free_irq(np->pci_dev->irq, dev); | |
4057 | if (np->msi_flags & NV_MSI_ENABLED) { | |
4058 | pci_disable_msi(np->pci_dev); | |
4059 | np->msi_flags &= ~NV_MSI_ENABLED; | |
4060 | } | |
4061 | } | |
4062 | } | |
4063 | ||
1da177e4 LT |
4064 | static void nv_do_nic_poll(unsigned long data) |
4065 | { | |
4066 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 4067 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4068 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 4069 | u32 mask = 0; |
0b7c8743 NH |
4070 | unsigned long flags; |
4071 | unsigned int irq = 0; | |
1da177e4 | 4072 | |
1da177e4 | 4073 | /* |
d33a73c8 | 4074 | * First disable irq(s) and then |
1da177e4 LT |
4075 | * reenable interrupts on the nic, we have to do this before calling |
4076 | * nv_nic_irq because that may decide to do otherwise | |
4077 | */ | |
d33a73c8 | 4078 | |
84b3932b AA |
4079 | if (!using_multi_irqs(dev)) { |
4080 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
0b7c8743 | 4081 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector; |
84b3932b | 4082 | else |
0b7c8743 | 4083 | irq = np->pci_dev->irq; |
d33a73c8 AA |
4084 | mask = np->irqmask; |
4085 | } else { | |
4086 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
0b7c8743 | 4087 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector; |
d33a73c8 AA |
4088 | mask |= NVREG_IRQ_RX_ALL; |
4089 | } | |
4090 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
0b7c8743 | 4091 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector; |
d33a73c8 AA |
4092 | mask |= NVREG_IRQ_TX_ALL; |
4093 | } | |
4094 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
0b7c8743 | 4095 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector; |
d33a73c8 AA |
4096 | mask |= NVREG_IRQ_OTHER; |
4097 | } | |
4098 | } | |
0b7c8743 NH |
4099 | |
4100 | disable_irq_nosync_lockdep_irqsave(irq, &flags); | |
4101 | synchronize_irq(irq); | |
a7475906 | 4102 | |
c5cf9101 AA |
4103 | if (np->recover_error) { |
4104 | np->recover_error = 0; | |
1d397f36 | 4105 | netdev_info(dev, "MAC in recoverable error state\n"); |
c5cf9101 AA |
4106 | if (netif_running(dev)) { |
4107 | netif_tx_lock_bh(dev); | |
e308a5d8 | 4108 | netif_addr_lock(dev); |
c5cf9101 AA |
4109 | spin_lock(&np->lock); |
4110 | /* stop engines */ | |
36b30ea9 | 4111 | nv_stop_rxtx(dev); |
daa91a9d AA |
4112 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
4113 | nv_mac_reset(dev); | |
c5cf9101 AA |
4114 | nv_txrx_reset(dev); |
4115 | /* drain rx queue */ | |
36b30ea9 | 4116 | nv_drain_rxtx(dev); |
c5cf9101 AA |
4117 | /* reinit driver view of the rx queue */ |
4118 | set_bufsize(dev); | |
4119 | if (nv_init_ring(dev)) { | |
4120 | if (!np->in_shutdown) | |
4121 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4122 | } | |
4123 | /* reinit nic view of the rx queue */ | |
4124 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4125 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4126 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
c5cf9101 AA |
4127 | base + NvRegRingSizes); |
4128 | pci_push(base); | |
4129 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4130 | pci_push(base); | |
daa91a9d AA |
4131 | /* clear interrupts */ |
4132 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4133 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4134 | else | |
4135 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
c5cf9101 AA |
4136 | |
4137 | /* restart rx engine */ | |
36b30ea9 | 4138 | nv_start_rxtx(dev); |
c5cf9101 | 4139 | spin_unlock(&np->lock); |
e308a5d8 | 4140 | netif_addr_unlock(dev); |
c5cf9101 AA |
4141 | netif_tx_unlock_bh(dev); |
4142 | } | |
4143 | } | |
4144 | ||
d33a73c8 | 4145 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 4146 | pci_push(base); |
d33a73c8 | 4147 | |
84b3932b | 4148 | if (!using_multi_irqs(dev)) { |
79d30a58 | 4149 | np->nic_poll_irq = 0; |
36b30ea9 | 4150 | if (nv_optimized(np)) |
fcc5f266 AA |
4151 | nv_nic_irq_optimized(0, dev); |
4152 | else | |
4153 | nv_nic_irq(0, dev); | |
d33a73c8 AA |
4154 | } else { |
4155 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
79d30a58 | 4156 | np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; |
7d12e780 | 4157 | nv_nic_irq_rx(0, dev); |
d33a73c8 AA |
4158 | } |
4159 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
79d30a58 | 4160 | np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; |
7d12e780 | 4161 | nv_nic_irq_tx(0, dev); |
d33a73c8 AA |
4162 | } |
4163 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
79d30a58 | 4164 | np->nic_poll_irq &= ~NVREG_IRQ_OTHER; |
7d12e780 | 4165 | nv_nic_irq_other(0, dev); |
d33a73c8 AA |
4166 | } |
4167 | } | |
79d30a58 | 4168 | |
0b7c8743 | 4169 | enable_irq_lockdep_irqrestore(irq, &flags); |
1da177e4 LT |
4170 | } |
4171 | ||
2918c35d MS |
4172 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4173 | static void nv_poll_controller(struct net_device *dev) | |
4174 | { | |
4175 | nv_do_nic_poll((unsigned long) dev); | |
4176 | } | |
4177 | #endif | |
4178 | ||
52da3578 | 4179 | static void nv_do_stats_poll(unsigned long data) |
f5d827ae | 4180 | __acquires(&netdev_priv(dev)->hwstats_lock) |
4181 | __releases(&netdev_priv(dev)->hwstats_lock) | |
52da3578 AA |
4182 | { |
4183 | struct net_device *dev = (struct net_device *) data; | |
4184 | struct fe_priv *np = netdev_priv(dev); | |
52da3578 | 4185 | |
f5d827ae | 4186 | /* If lock is currently taken, the stats are being refreshed |
4187 | * and hence fresh enough */ | |
4188 | if (spin_trylock(&np->hwstats_lock)) { | |
4189 | nv_update_stats(dev); | |
4190 | spin_unlock(&np->hwstats_lock); | |
4191 | } | |
52da3578 AA |
4192 | |
4193 | if (!np->in_shutdown) | |
bfebbb88 DD |
4194 | mod_timer(&np->stats_poll, |
4195 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 AA |
4196 | } |
4197 | ||
1da177e4 LT |
4198 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
4199 | { | |
ac9c1897 | 4200 | struct fe_priv *np = netdev_priv(dev); |
68aad78c RJ |
4201 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
4202 | strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version)); | |
4203 | strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); | |
1da177e4 LT |
4204 | } |
4205 | ||
4206 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4207 | { | |
ac9c1897 | 4208 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
4209 | wolinfo->supported = WAKE_MAGIC; |
4210 | ||
4211 | spin_lock_irq(&np->lock); | |
4212 | if (np->wolenabled) | |
4213 | wolinfo->wolopts = WAKE_MAGIC; | |
4214 | spin_unlock_irq(&np->lock); | |
4215 | } | |
4216 | ||
4217 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4218 | { | |
ac9c1897 | 4219 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4220 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 4221 | u32 flags = 0; |
1da177e4 | 4222 | |
1da177e4 | 4223 | if (wolinfo->wolopts == 0) { |
1da177e4 | 4224 | np->wolenabled = 0; |
c42d9df9 | 4225 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 4226 | np->wolenabled = 1; |
c42d9df9 AA |
4227 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
4228 | } | |
4229 | if (netif_running(dev)) { | |
4230 | spin_lock_irq(&np->lock); | |
4231 | writel(flags, base + NvRegWakeUpFlags); | |
4232 | spin_unlock_irq(&np->lock); | |
1da177e4 | 4233 | } |
dba5a68a | 4234 | device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled); |
1da177e4 LT |
4235 | return 0; |
4236 | } | |
4237 | ||
0fa9e289 PR |
4238 | static int nv_get_link_ksettings(struct net_device *dev, |
4239 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
4240 | { |
4241 | struct fe_priv *np = netdev_priv(dev); | |
0fa9e289 | 4242 | u32 speed, supported, advertising; |
1da177e4 LT |
4243 | int adv; |
4244 | ||
4245 | spin_lock_irq(&np->lock); | |
0fa9e289 | 4246 | cmd->base.port = PORT_MII; |
1da177e4 LT |
4247 | if (!netif_running(dev)) { |
4248 | /* We do not track link speed / duplex setting if the | |
4249 | * interface is disabled. Force a link check */ | |
f9430a01 | 4250 | if (nv_update_linkspeed(dev)) { |
5d826b7b | 4251 | netif_carrier_on(dev); |
f9430a01 | 4252 | } else { |
5d826b7b | 4253 | netif_carrier_off(dev); |
f9430a01 | 4254 | } |
1da177e4 | 4255 | } |
f9430a01 AA |
4256 | |
4257 | if (netif_carrier_ok(dev)) { | |
78aea4fc | 4258 | switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
1da177e4 | 4259 | case NVREG_LINKSPEED_10: |
70739497 | 4260 | speed = SPEED_10; |
1da177e4 LT |
4261 | break; |
4262 | case NVREG_LINKSPEED_100: | |
70739497 | 4263 | speed = SPEED_100; |
1da177e4 LT |
4264 | break; |
4265 | case NVREG_LINKSPEED_1000: | |
70739497 DD |
4266 | speed = SPEED_1000; |
4267 | break; | |
4268 | default: | |
4269 | speed = -1; | |
1da177e4 | 4270 | break; |
f9430a01 | 4271 | } |
0fa9e289 | 4272 | cmd->base.duplex = DUPLEX_HALF; |
f9430a01 | 4273 | if (np->duplex) |
0fa9e289 | 4274 | cmd->base.duplex = DUPLEX_FULL; |
f9430a01 | 4275 | } else { |
537fae01 | 4276 | speed = SPEED_UNKNOWN; |
0fa9e289 | 4277 | cmd->base.duplex = DUPLEX_UNKNOWN; |
1da177e4 | 4278 | } |
0fa9e289 PR |
4279 | cmd->base.speed = speed; |
4280 | cmd->base.autoneg = np->autoneg; | |
1da177e4 | 4281 | |
0fa9e289 | 4282 | advertising = ADVERTISED_MII; |
1da177e4 | 4283 | if (np->autoneg) { |
0fa9e289 | 4284 | advertising |= ADVERTISED_Autoneg; |
1da177e4 | 4285 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
f9430a01 | 4286 | if (adv & ADVERTISE_10HALF) |
0fa9e289 | 4287 | advertising |= ADVERTISED_10baseT_Half; |
f9430a01 | 4288 | if (adv & ADVERTISE_10FULL) |
0fa9e289 | 4289 | advertising |= ADVERTISED_10baseT_Full; |
f9430a01 | 4290 | if (adv & ADVERTISE_100HALF) |
0fa9e289 | 4291 | advertising |= ADVERTISED_100baseT_Half; |
f9430a01 | 4292 | if (adv & ADVERTISE_100FULL) |
0fa9e289 | 4293 | advertising |= ADVERTISED_100baseT_Full; |
f9430a01 AA |
4294 | if (np->gigabit == PHY_GIGABIT) { |
4295 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
4296 | if (adv & ADVERTISE_1000FULL) | |
0fa9e289 | 4297 | advertising |= ADVERTISED_1000baseT_Full; |
f9430a01 | 4298 | } |
1da177e4 | 4299 | } |
0fa9e289 | 4300 | supported = (SUPPORTED_Autoneg | |
1da177e4 LT |
4301 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | |
4302 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
4303 | SUPPORTED_MII); | |
4304 | if (np->gigabit == PHY_GIGABIT) | |
0fa9e289 | 4305 | supported |= SUPPORTED_1000baseT_Full; |
1da177e4 | 4306 | |
0fa9e289 PR |
4307 | cmd->base.phy_address = np->phyaddr; |
4308 | ||
4309 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, | |
4310 | supported); | |
4311 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, | |
4312 | advertising); | |
1da177e4 LT |
4313 | |
4314 | /* ignore maxtxpkt, maxrxpkt for now */ | |
4315 | spin_unlock_irq(&np->lock); | |
4316 | return 0; | |
4317 | } | |
4318 | ||
0fa9e289 PR |
4319 | static int nv_set_link_ksettings(struct net_device *dev, |
4320 | const struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
4321 | { |
4322 | struct fe_priv *np = netdev_priv(dev); | |
0fa9e289 PR |
4323 | u32 speed = cmd->base.speed; |
4324 | u32 advertising; | |
1da177e4 | 4325 | |
0fa9e289 PR |
4326 | ethtool_convert_link_mode_to_legacy_u32(&advertising, |
4327 | cmd->link_modes.advertising); | |
4328 | ||
4329 | if (cmd->base.port != PORT_MII) | |
1da177e4 | 4330 | return -EINVAL; |
0fa9e289 | 4331 | if (cmd->base.phy_address != np->phyaddr) { |
1da177e4 LT |
4332 | /* TODO: support switching between multiple phys. Should be |
4333 | * trivial, but not enabled due to lack of test hardware. */ | |
4334 | return -EINVAL; | |
4335 | } | |
0fa9e289 | 4336 | if (cmd->base.autoneg == AUTONEG_ENABLE) { |
1da177e4 LT |
4337 | u32 mask; |
4338 | ||
4339 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4340 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4341 | if (np->gigabit == PHY_GIGABIT) | |
4342 | mask |= ADVERTISED_1000baseT_Full; | |
4343 | ||
0fa9e289 | 4344 | if ((advertising & mask) == 0) |
1da177e4 LT |
4345 | return -EINVAL; |
4346 | ||
0fa9e289 | 4347 | } else if (cmd->base.autoneg == AUTONEG_DISABLE) { |
1da177e4 | 4348 | /* Note: autonegotiation disable, speed 1000 intentionally |
25985edc | 4349 | * forbidden - no one should need that. */ |
1da177e4 | 4350 | |
25db0338 | 4351 | if (speed != SPEED_10 && speed != SPEED_100) |
1da177e4 | 4352 | return -EINVAL; |
0fa9e289 PR |
4353 | if (cmd->base.duplex != DUPLEX_HALF && |
4354 | cmd->base.duplex != DUPLEX_FULL) | |
1da177e4 LT |
4355 | return -EINVAL; |
4356 | } else { | |
4357 | return -EINVAL; | |
4358 | } | |
4359 | ||
f9430a01 AA |
4360 | netif_carrier_off(dev); |
4361 | if (netif_running(dev)) { | |
97bff095 TD |
4362 | unsigned long flags; |
4363 | ||
f9430a01 | 4364 | nv_disable_irq(dev); |
58dfd9c1 | 4365 | netif_tx_lock_bh(dev); |
e308a5d8 | 4366 | netif_addr_lock(dev); |
97bff095 TD |
4367 | /* with plain spinlock lockdep complains */ |
4368 | spin_lock_irqsave(&np->lock, flags); | |
f9430a01 | 4369 | /* stop engines */ |
97bff095 TD |
4370 | /* FIXME: |
4371 | * this can take some time, and interrupts are disabled | |
4372 | * due to spin_lock_irqsave, but let's hope no daemon | |
4373 | * is going to change the settings very often... | |
4374 | * Worst case: | |
4375 | * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX | |
4376 | * + some minor delays, which is up to a second approximately | |
4377 | */ | |
36b30ea9 | 4378 | nv_stop_rxtx(dev); |
97bff095 | 4379 | spin_unlock_irqrestore(&np->lock, flags); |
e308a5d8 | 4380 | netif_addr_unlock(dev); |
58dfd9c1 | 4381 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4382 | } |
4383 | ||
0fa9e289 | 4384 | if (cmd->base.autoneg == AUTONEG_ENABLE) { |
1da177e4 LT |
4385 | int adv, bmcr; |
4386 | ||
4387 | np->autoneg = 1; | |
4388 | ||
4389 | /* advertise only what has been requested */ | |
4390 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4391 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
0fa9e289 | 4392 | if (advertising & ADVERTISED_10baseT_Half) |
1da177e4 | 4393 | adv |= ADVERTISE_10HALF; |
0fa9e289 | 4394 | if (advertising & ADVERTISED_10baseT_Full) |
b6d0773f | 4395 | adv |= ADVERTISE_10FULL; |
0fa9e289 | 4396 | if (advertising & ADVERTISED_100baseT_Half) |
1da177e4 | 4397 | adv |= ADVERTISE_100HALF; |
0fa9e289 | 4398 | if (advertising & ADVERTISED_100baseT_Full) |
b6d0773f | 4399 | adv |= ADVERTISE_100FULL; |
25985edc | 4400 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4401 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4402 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4403 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
4404 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4405 | ||
4406 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4407 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4408 | adv &= ~ADVERTISE_1000FULL; |
0fa9e289 | 4409 | if (advertising & ADVERTISED_1000baseT_Full) |
1da177e4 | 4410 | adv |= ADVERTISE_1000FULL; |
eb91f61b | 4411 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4412 | } |
4413 | ||
f9430a01 | 4414 | if (netif_running(dev)) |
1d397f36 | 4415 | netdev_info(dev, "link down\n"); |
1da177e4 | 4416 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4417 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4418 | bmcr |= BMCR_ANENABLE; | |
4419 | /* reset the phy in order for settings to stick, | |
4420 | * and cause autoneg to start */ | |
4421 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4422 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4423 | return -EINVAL; |
4424 | } | |
4425 | } else { | |
4426 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4427 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4428 | } | |
1da177e4 LT |
4429 | } else { |
4430 | int adv, bmcr; | |
4431 | ||
4432 | np->autoneg = 0; | |
4433 | ||
4434 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4435 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
0fa9e289 | 4436 | if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF) |
1da177e4 | 4437 | adv |= ADVERTISE_10HALF; |
0fa9e289 | 4438 | if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL) |
b6d0773f | 4439 | adv |= ADVERTISE_10FULL; |
0fa9e289 | 4440 | if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF) |
1da177e4 | 4441 | adv |= ADVERTISE_100HALF; |
0fa9e289 | 4442 | if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL) |
b6d0773f AA |
4443 | adv |= ADVERTISE_100FULL; |
4444 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
25985edc | 4445 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4446 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4447 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4448 | } | |
4449 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
4450 | adv |= ADVERTISE_PAUSE_ASYM; | |
4451 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4452 | } | |
1da177e4 LT |
4453 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4454 | np->fixed_mode = adv; | |
4455 | ||
4456 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4457 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4458 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 4459 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4460 | } |
4461 | ||
4462 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
4463 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
4464 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 4465 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 4466 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 4467 | bmcr |= BMCR_SPEED100; |
f9430a01 | 4468 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
4469 | /* reset the phy in order for forced mode settings to stick */ |
4470 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4471 | netdev_info(dev, "phy reset failed\n"); |
f9430a01 AA |
4472 | return -EINVAL; |
4473 | } | |
edf7e5ec AA |
4474 | } else { |
4475 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4476 | if (netif_running(dev)) { | |
4477 | /* Wait a bit and then reconfigure the nic. */ | |
4478 | udelay(10); | |
4479 | nv_linkchange(dev); | |
4480 | } | |
1da177e4 LT |
4481 | } |
4482 | } | |
f9430a01 AA |
4483 | |
4484 | if (netif_running(dev)) { | |
36b30ea9 | 4485 | nv_start_rxtx(dev); |
f9430a01 AA |
4486 | nv_enable_irq(dev); |
4487 | } | |
1da177e4 LT |
4488 | |
4489 | return 0; | |
4490 | } | |
4491 | ||
dc8216c1 | 4492 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
4493 | |
4494 | static int nv_get_regs_len(struct net_device *dev) | |
4495 | { | |
86a0f043 AA |
4496 | struct fe_priv *np = netdev_priv(dev); |
4497 | return np->register_size; | |
dc8216c1 MS |
4498 | } |
4499 | ||
4500 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
4501 | { | |
ac9c1897 | 4502 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4503 | u8 __iomem *base = get_hwbase(dev); |
4504 | u32 *rbuf = buf; | |
4505 | int i; | |
4506 | ||
4507 | regs->version = FORCEDETH_REGS_VER; | |
4508 | spin_lock_irq(&np->lock); | |
ba9aa134 | 4509 | for (i = 0; i < np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
4510 | rbuf[i] = readl(base + i*sizeof(u32)); |
4511 | spin_unlock_irq(&np->lock); | |
4512 | } | |
4513 | ||
4514 | static int nv_nway_reset(struct net_device *dev) | |
4515 | { | |
ac9c1897 | 4516 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4517 | int ret; |
4518 | ||
dc8216c1 MS |
4519 | if (np->autoneg) { |
4520 | int bmcr; | |
4521 | ||
f9430a01 AA |
4522 | netif_carrier_off(dev); |
4523 | if (netif_running(dev)) { | |
4524 | nv_disable_irq(dev); | |
58dfd9c1 | 4525 | netif_tx_lock_bh(dev); |
e308a5d8 | 4526 | netif_addr_lock(dev); |
f9430a01 AA |
4527 | spin_lock(&np->lock); |
4528 | /* stop engines */ | |
36b30ea9 | 4529 | nv_stop_rxtx(dev); |
f9430a01 | 4530 | spin_unlock(&np->lock); |
e308a5d8 | 4531 | netif_addr_unlock(dev); |
58dfd9c1 | 4532 | netif_tx_unlock_bh(dev); |
1d397f36 | 4533 | netdev_info(dev, "link down\n"); |
f9430a01 AA |
4534 | } |
4535 | ||
dc8216c1 | 4536 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4537 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4538 | bmcr |= BMCR_ANENABLE; | |
4539 | /* reset the phy in order for settings to stick*/ | |
4540 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4541 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4542 | return -EINVAL; |
4543 | } | |
4544 | } else { | |
4545 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4546 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4547 | } | |
dc8216c1 | 4548 | |
f9430a01 | 4549 | if (netif_running(dev)) { |
36b30ea9 | 4550 | nv_start_rxtx(dev); |
f9430a01 AA |
4551 | nv_enable_irq(dev); |
4552 | } | |
dc8216c1 MS |
4553 | ret = 0; |
4554 | } else { | |
4555 | ret = -EINVAL; | |
4556 | } | |
dc8216c1 MS |
4557 | |
4558 | return ret; | |
4559 | } | |
4560 | ||
eafa59f6 AA |
4561 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4562 | { | |
4563 | struct fe_priv *np = netdev_priv(dev); | |
4564 | ||
4565 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
eafa59f6 AA |
4566 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; |
4567 | ||
4568 | ring->rx_pending = np->rx_ring_size; | |
eafa59f6 AA |
4569 | ring->tx_pending = np->tx_ring_size; |
4570 | } | |
4571 | ||
4572 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
4573 | { | |
4574 | struct fe_priv *np = netdev_priv(dev); | |
4575 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 4576 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
4577 | dma_addr_t ring_addr; |
4578 | ||
4579 | if (ring->rx_pending < RX_RING_MIN || | |
4580 | ring->tx_pending < TX_RING_MIN || | |
4581 | ring->rx_mini_pending != 0 || | |
4582 | ring->rx_jumbo_pending != 0 || | |
4583 | (np->desc_ver == DESC_VER_1 && | |
4584 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
4585 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
4586 | (np->desc_ver != DESC_VER_1 && | |
4587 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
4588 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
4589 | return -EINVAL; | |
4590 | } | |
4591 | ||
4592 | /* allocate new rings */ | |
36b30ea9 | 4593 | if (!nv_optimized(np)) { |
eafa59f6 AA |
4594 | rxtx_ring = pci_alloc_consistent(np->pci_dev, |
4595 | sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), | |
4596 | &ring_addr); | |
4597 | } else { | |
4598 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
4599 | sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4600 | &ring_addr); | |
4601 | } | |
761fcd9e AA |
4602 | rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
4603 | tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); | |
4604 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { | |
eafa59f6 | 4605 | /* fall back to old rings */ |
36b30ea9 | 4606 | if (!nv_optimized(np)) { |
f82a9352 | 4607 | if (rxtx_ring) |
eafa59f6 AA |
4608 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
4609 | rxtx_ring, ring_addr); | |
4610 | } else { | |
4611 | if (rxtx_ring) | |
4612 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4613 | rxtx_ring, ring_addr); | |
4614 | } | |
9b03b06b SJ |
4615 | |
4616 | kfree(rx_skbuff); | |
4617 | kfree(tx_skbuff); | |
eafa59f6 AA |
4618 | goto exit; |
4619 | } | |
4620 | ||
4621 | if (netif_running(dev)) { | |
4622 | nv_disable_irq(dev); | |
08d93575 | 4623 | nv_napi_disable(dev); |
58dfd9c1 | 4624 | netif_tx_lock_bh(dev); |
e308a5d8 | 4625 | netif_addr_lock(dev); |
eafa59f6 AA |
4626 | spin_lock(&np->lock); |
4627 | /* stop engines */ | |
36b30ea9 | 4628 | nv_stop_rxtx(dev); |
eafa59f6 AA |
4629 | nv_txrx_reset(dev); |
4630 | /* drain queues */ | |
36b30ea9 | 4631 | nv_drain_rxtx(dev); |
eafa59f6 AA |
4632 | /* delete queues */ |
4633 | free_rings(dev); | |
4634 | } | |
4635 | ||
4636 | /* set new values */ | |
4637 | np->rx_ring_size = ring->rx_pending; | |
4638 | np->tx_ring_size = ring->tx_pending; | |
36b30ea9 JG |
4639 | |
4640 | if (!nv_optimized(np)) { | |
78aea4fc | 4641 | np->rx_ring.orig = (struct ring_desc *)rxtx_ring; |
eafa59f6 AA |
4642 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
4643 | } else { | |
78aea4fc | 4644 | np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; |
eafa59f6 AA |
4645 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4646 | } | |
78aea4fc SJ |
4647 | np->rx_skb = (struct nv_skb_map *)rx_skbuff; |
4648 | np->tx_skb = (struct nv_skb_map *)tx_skbuff; | |
eafa59f6 AA |
4649 | np->ring_addr = ring_addr; |
4650 | ||
761fcd9e AA |
4651 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4652 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
4653 | |
4654 | if (netif_running(dev)) { | |
4655 | /* reinit driver view of the queues */ | |
4656 | set_bufsize(dev); | |
4657 | if (nv_init_ring(dev)) { | |
4658 | if (!np->in_shutdown) | |
4659 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4660 | } | |
4661 | ||
4662 | /* reinit nic view of the queues */ | |
4663 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4664 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4665 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
eafa59f6 AA |
4666 | base + NvRegRingSizes); |
4667 | pci_push(base); | |
4668 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4669 | pci_push(base); | |
4670 | ||
4671 | /* restart engines */ | |
36b30ea9 | 4672 | nv_start_rxtx(dev); |
eafa59f6 | 4673 | spin_unlock(&np->lock); |
e308a5d8 | 4674 | netif_addr_unlock(dev); |
58dfd9c1 | 4675 | netif_tx_unlock_bh(dev); |
08d93575 | 4676 | nv_napi_enable(dev); |
eafa59f6 AA |
4677 | nv_enable_irq(dev); |
4678 | } | |
4679 | return 0; | |
4680 | exit: | |
4681 | return -ENOMEM; | |
4682 | } | |
4683 | ||
b6d0773f AA |
4684 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4685 | { | |
4686 | struct fe_priv *np = netdev_priv(dev); | |
4687 | ||
4688 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4689 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4690 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4691 | } | |
4692 | ||
4693 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4694 | { | |
4695 | struct fe_priv *np = netdev_priv(dev); | |
4696 | int adv, bmcr; | |
4697 | ||
4698 | if ((!np->autoneg && np->duplex == 0) || | |
4699 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
1d397f36 | 4700 | netdev_info(dev, "can not set pause settings when forced link is in half duplex\n"); |
b6d0773f AA |
4701 | return -EINVAL; |
4702 | } | |
4703 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
1d397f36 | 4704 | netdev_info(dev, "hardware does not support tx pause frames\n"); |
b6d0773f AA |
4705 | return -EINVAL; |
4706 | } | |
4707 | ||
4708 | netif_carrier_off(dev); | |
4709 | if (netif_running(dev)) { | |
4710 | nv_disable_irq(dev); | |
58dfd9c1 | 4711 | netif_tx_lock_bh(dev); |
e308a5d8 | 4712 | netif_addr_lock(dev); |
b6d0773f AA |
4713 | spin_lock(&np->lock); |
4714 | /* stop engines */ | |
36b30ea9 | 4715 | nv_stop_rxtx(dev); |
b6d0773f | 4716 | spin_unlock(&np->lock); |
e308a5d8 | 4717 | netif_addr_unlock(dev); |
58dfd9c1 | 4718 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4719 | } |
4720 | ||
4721 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4722 | if (pause->rx_pause) | |
4723 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4724 | if (pause->tx_pause) | |
4725 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4726 | ||
4727 | if (np->autoneg && pause->autoneg) { | |
4728 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4729 | ||
4730 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4731 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
25985edc | 4732 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4733 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4734 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4735 | adv |= ADVERTISE_PAUSE_ASYM; | |
4736 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4737 | ||
4738 | if (netif_running(dev)) | |
1d397f36 | 4739 | netdev_info(dev, "link down\n"); |
b6d0773f AA |
4740 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4741 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4742 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4743 | } else { | |
4744 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4745 | if (pause->rx_pause) | |
4746 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4747 | if (pause->tx_pause) | |
4748 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4749 | ||
4750 | if (!netif_running(dev)) | |
4751 | nv_update_linkspeed(dev); | |
4752 | else | |
4753 | nv_update_pause(dev, np->pause_flags); | |
4754 | } | |
4755 | ||
4756 | if (netif_running(dev)) { | |
36b30ea9 | 4757 | nv_start_rxtx(dev); |
b6d0773f AA |
4758 | nv_enable_irq(dev); |
4759 | } | |
4760 | return 0; | |
4761 | } | |
4762 | ||
c8f44aff | 4763 | static int nv_set_loopback(struct net_device *dev, netdev_features_t features) |
e19df76a SH |
4764 | { |
4765 | struct fe_priv *np = netdev_priv(dev); | |
4766 | unsigned long flags; | |
4767 | u32 miicontrol; | |
4768 | int err, retval = 0; | |
4769 | ||
4770 | spin_lock_irqsave(&np->lock, flags); | |
4771 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
4772 | if (features & NETIF_F_LOOPBACK) { | |
4773 | if (miicontrol & BMCR_LOOPBACK) { | |
4774 | spin_unlock_irqrestore(&np->lock, flags); | |
4775 | netdev_info(dev, "Loopback already enabled\n"); | |
4776 | return 0; | |
4777 | } | |
4778 | nv_disable_irq(dev); | |
4779 | /* Turn on loopback mode */ | |
4780 | miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
4781 | err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); | |
4782 | if (err) { | |
4783 | retval = PHY_ERROR; | |
4784 | spin_unlock_irqrestore(&np->lock, flags); | |
4785 | phy_init(dev); | |
4786 | } else { | |
4787 | if (netif_running(dev)) { | |
4788 | /* Force 1000 Mbps full-duplex */ | |
4789 | nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, | |
4790 | 1); | |
4791 | /* Force link up */ | |
4792 | netif_carrier_on(dev); | |
4793 | } | |
4794 | spin_unlock_irqrestore(&np->lock, flags); | |
4795 | netdev_info(dev, | |
4796 | "Internal PHY loopback mode enabled.\n"); | |
4797 | } | |
4798 | } else { | |
4799 | if (!(miicontrol & BMCR_LOOPBACK)) { | |
4800 | spin_unlock_irqrestore(&np->lock, flags); | |
4801 | netdev_info(dev, "Loopback already disabled\n"); | |
4802 | return 0; | |
4803 | } | |
4804 | nv_disable_irq(dev); | |
4805 | /* Turn off loopback */ | |
4806 | spin_unlock_irqrestore(&np->lock, flags); | |
4807 | netdev_info(dev, "Internal PHY loopback mode disabled.\n"); | |
4808 | phy_init(dev); | |
4809 | } | |
4810 | msleep(500); | |
4811 | spin_lock_irqsave(&np->lock, flags); | |
4812 | nv_enable_irq(dev); | |
4813 | spin_unlock_irqrestore(&np->lock, flags); | |
4814 | ||
4815 | return retval; | |
4816 | } | |
4817 | ||
c8f44aff MM |
4818 | static netdev_features_t nv_fix_features(struct net_device *dev, |
4819 | netdev_features_t features) | |
5ed2616f | 4820 | { |
569e1463 | 4821 | /* vlan is dependent on rx checksum offload */ |
f646968f | 4822 | if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) |
569e1463 MM |
4823 | features |= NETIF_F_RXCSUM; |
4824 | ||
4825 | return features; | |
5ed2616f AA |
4826 | } |
4827 | ||
c8f44aff | 4828 | static void nv_vlan_mode(struct net_device *dev, netdev_features_t features) |
3326c784 JP |
4829 | { |
4830 | struct fe_priv *np = get_nvpriv(dev); | |
4831 | ||
4832 | spin_lock_irq(&np->lock); | |
4833 | ||
f646968f | 4834 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
3326c784 JP |
4835 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP; |
4836 | else | |
4837 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
4838 | ||
f646968f | 4839 | if (features & NETIF_F_HW_VLAN_CTAG_TX) |
3326c784 JP |
4840 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS; |
4841 | else | |
4842 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
4843 | ||
4844 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4845 | ||
4846 | spin_unlock_irq(&np->lock); | |
4847 | } | |
4848 | ||
c8f44aff | 4849 | static int nv_set_features(struct net_device *dev, netdev_features_t features) |
5ed2616f AA |
4850 | { |
4851 | struct fe_priv *np = netdev_priv(dev); | |
4852 | u8 __iomem *base = get_hwbase(dev); | |
c8f44aff | 4853 | netdev_features_t changed = dev->features ^ features; |
e19df76a SH |
4854 | int retval; |
4855 | ||
4856 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) { | |
4857 | retval = nv_set_loopback(dev, features); | |
4858 | if (retval != 0) | |
4859 | return retval; | |
4860 | } | |
5ed2616f | 4861 | |
569e1463 MM |
4862 | if (changed & NETIF_F_RXCSUM) { |
4863 | spin_lock_irq(&np->lock); | |
5ed2616f | 4864 | |
569e1463 MM |
4865 | if (features & NETIF_F_RXCSUM) |
4866 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | |
4867 | else | |
4868 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4869 | |
569e1463 MM |
4870 | if (netif_running(dev)) |
4871 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
5ed2616f | 4872 | |
569e1463 MM |
4873 | spin_unlock_irq(&np->lock); |
4874 | } | |
5ed2616f | 4875 | |
f646968f | 4876 | if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX)) |
3326c784 JP |
4877 | nv_vlan_mode(dev, features); |
4878 | ||
569e1463 | 4879 | return 0; |
5ed2616f AA |
4880 | } |
4881 | ||
b9f2c044 | 4882 | static int nv_get_sset_count(struct net_device *dev, int sset) |
52da3578 AA |
4883 | { |
4884 | struct fe_priv *np = netdev_priv(dev); | |
4885 | ||
b9f2c044 JG |
4886 | switch (sset) { |
4887 | case ETH_SS_TEST: | |
4888 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4889 | return NV_TEST_COUNT_EXTENDED; | |
4890 | else | |
4891 | return NV_TEST_COUNT_BASE; | |
4892 | case ETH_SS_STATS: | |
8ed1454a AA |
4893 | if (np->driver_data & DEV_HAS_STATISTICS_V3) |
4894 | return NV_DEV_STATISTICS_V3_COUNT; | |
b9f2c044 JG |
4895 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) |
4896 | return NV_DEV_STATISTICS_V2_COUNT; | |
8ed1454a AA |
4897 | else if (np->driver_data & DEV_HAS_STATISTICS_V1) |
4898 | return NV_DEV_STATISTICS_V1_COUNT; | |
b9f2c044 JG |
4899 | else |
4900 | return 0; | |
4901 | default: | |
4902 | return -EOPNOTSUPP; | |
4903 | } | |
52da3578 AA |
4904 | } |
4905 | ||
f5d827ae | 4906 | static void nv_get_ethtool_stats(struct net_device *dev, |
4907 | struct ethtool_stats *estats, u64 *buffer) | |
4908 | __acquires(&netdev_priv(dev)->hwstats_lock) | |
4909 | __releases(&netdev_priv(dev)->hwstats_lock) | |
52da3578 AA |
4910 | { |
4911 | struct fe_priv *np = netdev_priv(dev); | |
4912 | ||
f5d827ae | 4913 | spin_lock_bh(&np->hwstats_lock); |
4914 | nv_update_stats(dev); | |
4915 | memcpy(buffer, &np->estats, | |
4916 | nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64)); | |
4917 | spin_unlock_bh(&np->hwstats_lock); | |
9589c77a AA |
4918 | } |
4919 | ||
4920 | static int nv_link_test(struct net_device *dev) | |
4921 | { | |
4922 | struct fe_priv *np = netdev_priv(dev); | |
4923 | int mii_status; | |
4924 | ||
4925 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4926 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4927 | ||
4928 | /* check phy link status */ | |
4929 | if (!(mii_status & BMSR_LSTATUS)) | |
4930 | return 0; | |
4931 | else | |
4932 | return 1; | |
4933 | } | |
4934 | ||
4935 | static int nv_register_test(struct net_device *dev) | |
4936 | { | |
4937 | u8 __iomem *base = get_hwbase(dev); | |
4938 | int i = 0; | |
4939 | u32 orig_read, new_read; | |
4940 | ||
4941 | do { | |
4942 | orig_read = readl(base + nv_registers_test[i].reg); | |
4943 | ||
4944 | /* xor with mask to toggle bits */ | |
4945 | orig_read ^= nv_registers_test[i].mask; | |
4946 | ||
4947 | writel(orig_read, base + nv_registers_test[i].reg); | |
4948 | ||
4949 | new_read = readl(base + nv_registers_test[i].reg); | |
4950 | ||
4951 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4952 | return 0; | |
4953 | ||
4954 | /* restore original value */ | |
4955 | orig_read ^= nv_registers_test[i].mask; | |
4956 | writel(orig_read, base + nv_registers_test[i].reg); | |
4957 | ||
4958 | } while (nv_registers_test[++i].reg != 0); | |
4959 | ||
4960 | return 1; | |
4961 | } | |
4962 | ||
4963 | static int nv_interrupt_test(struct net_device *dev) | |
4964 | { | |
4965 | struct fe_priv *np = netdev_priv(dev); | |
4966 | u8 __iomem *base = get_hwbase(dev); | |
4967 | int ret = 1; | |
4968 | int testcnt; | |
4969 | u32 save_msi_flags, save_poll_interval = 0; | |
4970 | ||
4971 | if (netif_running(dev)) { | |
4972 | /* free current irq */ | |
4973 | nv_free_irq(dev); | |
4974 | save_poll_interval = readl(base+NvRegPollingInterval); | |
4975 | } | |
4976 | ||
4977 | /* flag to test interrupt handler */ | |
4978 | np->intr_test = 0; | |
4979 | ||
4980 | /* setup test irq */ | |
4981 | save_msi_flags = np->msi_flags; | |
4982 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
4983 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
4984 | if (nv_request_irq(dev, 1)) | |
4985 | return 0; | |
4986 | ||
4987 | /* setup timer interrupt */ | |
4988 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4989 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4990 | ||
4991 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4992 | ||
4993 | /* wait for at least one interrupt */ | |
4994 | msleep(100); | |
4995 | ||
4996 | spin_lock_irq(&np->lock); | |
4997 | ||
4998 | /* flag should be set within ISR */ | |
4999 | testcnt = np->intr_test; | |
5000 | if (!testcnt) | |
5001 | ret = 2; | |
5002 | ||
5003 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
5004 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
5005 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
5006 | else | |
5007 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
5008 | ||
5009 | spin_unlock_irq(&np->lock); | |
5010 | ||
5011 | nv_free_irq(dev); | |
5012 | ||
5013 | np->msi_flags = save_msi_flags; | |
5014 | ||
5015 | if (netif_running(dev)) { | |
5016 | writel(save_poll_interval, base + NvRegPollingInterval); | |
5017 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
5018 | /* restore original irq */ | |
5019 | if (nv_request_irq(dev, 0)) | |
5020 | return 0; | |
5021 | } | |
5022 | ||
5023 | return ret; | |
5024 | } | |
5025 | ||
5026 | static int nv_loopback_test(struct net_device *dev) | |
5027 | { | |
5028 | struct fe_priv *np = netdev_priv(dev); | |
5029 | u8 __iomem *base = get_hwbase(dev); | |
5030 | struct sk_buff *tx_skb, *rx_skb; | |
5031 | dma_addr_t test_dma_addr; | |
5032 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 5033 | u32 flags; |
9589c77a AA |
5034 | int len, i, pkt_len; |
5035 | u8 *pkt_data; | |
5036 | u32 filter_flags = 0; | |
5037 | u32 misc1_flags = 0; | |
5038 | int ret = 1; | |
5039 | ||
5040 | if (netif_running(dev)) { | |
5041 | nv_disable_irq(dev); | |
5042 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
5043 | misc1_flags = readl(base + NvRegMisc1); | |
5044 | } else { | |
5045 | nv_txrx_reset(dev); | |
5046 | } | |
5047 | ||
5048 | /* reinit driver view of the rx queue */ | |
5049 | set_bufsize(dev); | |
5050 | nv_init_ring(dev); | |
5051 | ||
5052 | /* setup hardware for loopback */ | |
5053 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
5054 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
5055 | ||
5056 | /* reinit nic view of the rx queue */ | |
5057 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
5058 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 5059 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
5060 | base + NvRegRingSizes); |
5061 | pci_push(base); | |
5062 | ||
5063 | /* restart rx engine */ | |
36b30ea9 | 5064 | nv_start_rxtx(dev); |
9589c77a AA |
5065 | |
5066 | /* setup packet for tx */ | |
5067 | pkt_len = ETH_DATA_LEN; | |
dae2e9f4 | 5068 | tx_skb = netdev_alloc_skb(dev, pkt_len); |
46798c89 | 5069 | if (!tx_skb) { |
46798c89 JJ |
5070 | ret = 0; |
5071 | goto out; | |
5072 | } | |
8b5be268 ACM |
5073 | test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, |
5074 | skb_tailroom(tx_skb), | |
5075 | PCI_DMA_FROMDEVICE); | |
612a7c4e LF |
5076 | if (pci_dma_mapping_error(np->pci_dev, |
5077 | test_dma_addr)) { | |
5078 | dev_kfree_skb_any(tx_skb); | |
5079 | goto out; | |
5080 | } | |
9589c77a AA |
5081 | pkt_data = skb_put(tx_skb, pkt_len); |
5082 | for (i = 0; i < pkt_len; i++) | |
5083 | pkt_data[i] = (u8)(i & 0xff); | |
9589c77a | 5084 | |
36b30ea9 | 5085 | if (!nv_optimized(np)) { |
f82a9352 SH |
5086 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
5087 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 5088 | } else { |
5bb7ea26 AV |
5089 | np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); |
5090 | np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); | |
f82a9352 | 5091 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
9589c77a AA |
5092 | } |
5093 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5094 | pci_push(get_hwbase(dev)); | |
5095 | ||
5096 | msleep(500); | |
5097 | ||
5098 | /* check for rx of the packet */ | |
36b30ea9 | 5099 | if (!nv_optimized(np)) { |
f82a9352 | 5100 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
5101 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
5102 | ||
5103 | } else { | |
f82a9352 | 5104 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
5105 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
5106 | } | |
5107 | ||
f82a9352 | 5108 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
5109 | ret = 0; |
5110 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 5111 | if (flags & NV_RX_ERROR) |
9589c77a AA |
5112 | ret = 0; |
5113 | } else { | |
78aea4fc | 5114 | if (flags & NV_RX2_ERROR) |
9589c77a | 5115 | ret = 0; |
9589c77a AA |
5116 | } |
5117 | ||
5118 | if (ret) { | |
5119 | if (len != pkt_len) { | |
5120 | ret = 0; | |
9589c77a | 5121 | } else { |
761fcd9e | 5122 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
5123 | for (i = 0; i < pkt_len; i++) { |
5124 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
5125 | ret = 0; | |
9589c77a AA |
5126 | break; |
5127 | } | |
5128 | } | |
5129 | } | |
9589c77a AA |
5130 | } |
5131 | ||
73a37079 | 5132 | pci_unmap_single(np->pci_dev, test_dma_addr, |
4305b541 | 5133 | (skb_end_pointer(tx_skb) - tx_skb->data), |
9589c77a AA |
5134 | PCI_DMA_TODEVICE); |
5135 | dev_kfree_skb_any(tx_skb); | |
46798c89 | 5136 | out: |
9589c77a | 5137 | /* stop engines */ |
36b30ea9 | 5138 | nv_stop_rxtx(dev); |
9589c77a AA |
5139 | nv_txrx_reset(dev); |
5140 | /* drain rx queue */ | |
36b30ea9 | 5141 | nv_drain_rxtx(dev); |
9589c77a AA |
5142 | |
5143 | if (netif_running(dev)) { | |
5144 | writel(misc1_flags, base + NvRegMisc1); | |
5145 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
5146 | nv_enable_irq(dev); | |
5147 | } | |
5148 | ||
5149 | return ret; | |
5150 | } | |
5151 | ||
5152 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
5153 | { | |
5154 | struct fe_priv *np = netdev_priv(dev); | |
5155 | u8 __iomem *base = get_hwbase(dev); | |
86d9be26 IV |
5156 | int result, count; |
5157 | ||
5158 | count = nv_get_sset_count(dev, ETH_SS_TEST); | |
5159 | memset(buffer, 0, count * sizeof(u64)); | |
9589c77a AA |
5160 | |
5161 | if (!nv_link_test(dev)) { | |
5162 | test->flags |= ETH_TEST_FL_FAILED; | |
5163 | buffer[0] = 1; | |
5164 | } | |
5165 | ||
5166 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
5167 | if (netif_running(dev)) { | |
5168 | netif_stop_queue(dev); | |
08d93575 | 5169 | nv_napi_disable(dev); |
58dfd9c1 | 5170 | netif_tx_lock_bh(dev); |
e308a5d8 | 5171 | netif_addr_lock(dev); |
9589c77a AA |
5172 | spin_lock_irq(&np->lock); |
5173 | nv_disable_hw_interrupts(dev, np->irqmask); | |
78aea4fc | 5174 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
9589c77a | 5175 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
78aea4fc | 5176 | else |
9589c77a | 5177 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
9589c77a | 5178 | /* stop engines */ |
36b30ea9 | 5179 | nv_stop_rxtx(dev); |
9589c77a AA |
5180 | nv_txrx_reset(dev); |
5181 | /* drain rx queue */ | |
36b30ea9 | 5182 | nv_drain_rxtx(dev); |
9589c77a | 5183 | spin_unlock_irq(&np->lock); |
e308a5d8 | 5184 | netif_addr_unlock(dev); |
58dfd9c1 | 5185 | netif_tx_unlock_bh(dev); |
9589c77a AA |
5186 | } |
5187 | ||
5188 | if (!nv_register_test(dev)) { | |
5189 | test->flags |= ETH_TEST_FL_FAILED; | |
5190 | buffer[1] = 1; | |
5191 | } | |
5192 | ||
5193 | result = nv_interrupt_test(dev); | |
5194 | if (result != 1) { | |
5195 | test->flags |= ETH_TEST_FL_FAILED; | |
5196 | buffer[2] = 1; | |
5197 | } | |
5198 | if (result == 0) { | |
5199 | /* bail out */ | |
5200 | return; | |
5201 | } | |
5202 | ||
86d9be26 | 5203 | if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) { |
9589c77a AA |
5204 | test->flags |= ETH_TEST_FL_FAILED; |
5205 | buffer[3] = 1; | |
5206 | } | |
5207 | ||
5208 | if (netif_running(dev)) { | |
5209 | /* reinit driver view of the rx queue */ | |
5210 | set_bufsize(dev); | |
5211 | if (nv_init_ring(dev)) { | |
5212 | if (!np->in_shutdown) | |
5213 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
5214 | } | |
5215 | /* reinit nic view of the rx queue */ | |
5216 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
5217 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 5218 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
5219 | base + NvRegRingSizes); |
5220 | pci_push(base); | |
5221 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5222 | pci_push(base); | |
5223 | /* restart rx engine */ | |
36b30ea9 | 5224 | nv_start_rxtx(dev); |
9589c77a | 5225 | netif_start_queue(dev); |
08d93575 | 5226 | nv_napi_enable(dev); |
9589c77a AA |
5227 | nv_enable_hw_interrupts(dev, np->irqmask); |
5228 | } | |
5229 | } | |
5230 | } | |
5231 | ||
52da3578 AA |
5232 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
5233 | { | |
5234 | switch (stringset) { | |
5235 | case ETH_SS_STATS: | |
b9f2c044 | 5236 | memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str)); |
52da3578 | 5237 | break; |
9589c77a | 5238 | case ETH_SS_TEST: |
b9f2c044 | 5239 | memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str)); |
9589c77a | 5240 | break; |
52da3578 AA |
5241 | } |
5242 | } | |
5243 | ||
7282d491 | 5244 | static const struct ethtool_ops ops = { |
1da177e4 LT |
5245 | .get_drvinfo = nv_get_drvinfo, |
5246 | .get_link = ethtool_op_get_link, | |
5247 | .get_wol = nv_get_wol, | |
5248 | .set_wol = nv_set_wol, | |
dc8216c1 MS |
5249 | .get_regs_len = nv_get_regs_len, |
5250 | .get_regs = nv_get_regs, | |
5251 | .nway_reset = nv_nway_reset, | |
eafa59f6 AA |
5252 | .get_ringparam = nv_get_ringparam, |
5253 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
5254 | .get_pauseparam = nv_get_pauseparam, |
5255 | .set_pauseparam = nv_set_pauseparam, | |
52da3578 | 5256 | .get_strings = nv_get_strings, |
52da3578 | 5257 | .get_ethtool_stats = nv_get_ethtool_stats, |
b9f2c044 | 5258 | .get_sset_count = nv_get_sset_count, |
9589c77a | 5259 | .self_test = nv_self_test, |
7491302d | 5260 | .get_ts_info = ethtool_op_get_ts_info, |
0fa9e289 PR |
5261 | .get_link_ksettings = nv_get_link_ksettings, |
5262 | .set_link_ksettings = nv_set_link_ksettings, | |
1da177e4 LT |
5263 | }; |
5264 | ||
7e680c22 AA |
5265 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
5266 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
5267 | { | |
cac1c52c | 5268 | struct fe_priv *np = netdev_priv(dev); |
7e680c22 AA |
5269 | u8 __iomem *base = get_hwbase(dev); |
5270 | int i; | |
5271 | u32 tx_ctrl, mgmt_sema; | |
5272 | ||
5273 | for (i = 0; i < 10; i++) { | |
5274 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
5275 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5276 | break; | |
5277 | msleep(500); | |
5278 | } | |
5279 | ||
5280 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5281 | return 0; | |
5282 | ||
5283 | for (i = 0; i < 2; i++) { | |
5284 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5285 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5286 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5287 | ||
5288 | /* verify that semaphore was acquired */ | |
5289 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5290 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
cac1c52c AA |
5291 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
5292 | np->mgmt_sema = 1; | |
7e680c22 | 5293 | return 1; |
78aea4fc | 5294 | } else |
7e680c22 AA |
5295 | udelay(50); |
5296 | } | |
5297 | ||
5298 | return 0; | |
5299 | } | |
5300 | ||
cac1c52c AA |
5301 | static void nv_mgmt_release_sema(struct net_device *dev) |
5302 | { | |
5303 | struct fe_priv *np = netdev_priv(dev); | |
5304 | u8 __iomem *base = get_hwbase(dev); | |
5305 | u32 tx_ctrl; | |
5306 | ||
5307 | if (np->driver_data & DEV_HAS_MGMT_UNIT) { | |
5308 | if (np->mgmt_sema) { | |
5309 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5310 | tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5311 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5312 | } | |
5313 | } | |
5314 | } | |
5315 | ||
5316 | ||
5317 | static int nv_mgmt_get_version(struct net_device *dev) | |
5318 | { | |
5319 | struct fe_priv *np = netdev_priv(dev); | |
5320 | u8 __iomem *base = get_hwbase(dev); | |
5321 | u32 data_ready = readl(base + NvRegTransmitterControl); | |
5322 | u32 data_ready2 = 0; | |
5323 | unsigned long start; | |
5324 | int ready = 0; | |
5325 | ||
5326 | writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion); | |
5327 | writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl); | |
5328 | start = jiffies; | |
5329 | while (time_before(jiffies, start + 5*HZ)) { | |
5330 | data_ready2 = readl(base + NvRegTransmitterControl); | |
5331 | if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) { | |
5332 | ready = 1; | |
5333 | break; | |
5334 | } | |
5335 | schedule_timeout_uninterruptible(1); | |
5336 | } | |
5337 | ||
5338 | if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR)) | |
5339 | return 0; | |
5340 | ||
5341 | np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; | |
5342 | ||
5343 | return 1; | |
5344 | } | |
5345 | ||
1da177e4 LT |
5346 | static int nv_open(struct net_device *dev) |
5347 | { | |
ac9c1897 | 5348 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 5349 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
5350 | int ret = 1; |
5351 | int oom, i; | |
a433686c | 5352 | u32 low; |
1da177e4 | 5353 | |
cb52deba ES |
5354 | /* power up phy */ |
5355 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5356 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); | |
5357 | ||
88d7d8b0 | 5358 | nv_txrx_gate(dev, false); |
f1489653 | 5359 | /* erase previous misconfiguration */ |
86a0f043 AA |
5360 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
5361 | nv_mac_reset(dev); | |
1da177e4 LT |
5362 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
5363 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5364 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5365 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5366 | writel(0, base + NvRegPacketFilterFlags); |
5367 | ||
5368 | writel(0, base + NvRegTransmitterControl); | |
5369 | writel(0, base + NvRegReceiverControl); | |
5370 | ||
5371 | writel(0, base + NvRegAdapterControl); | |
5372 | ||
eb91f61b AA |
5373 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
5374 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
5375 | ||
f1489653 | 5376 | /* initialize descriptor rings */ |
d81c0983 | 5377 | set_bufsize(dev); |
1da177e4 LT |
5378 | oom = nv_init_ring(dev); |
5379 | ||
5380 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 5381 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
5382 | nv_txrx_reset(dev); |
5383 | writel(0, base + NvRegUnknownSetupReg6); | |
5384 | ||
5385 | np->in_shutdown = 0; | |
5386 | ||
f1489653 | 5387 | /* give hw rings */ |
0832b25a | 5388 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 5389 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
5390 | base + NvRegRingSizes); |
5391 | ||
1da177e4 | 5392 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
5393 | if (np->desc_ver == DESC_VER_1) |
5394 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
5395 | else | |
5396 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 5397 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 5398 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 5399 | pci_push(base); |
8a4ae7f2 | 5400 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
344d0dce JP |
5401 | if (reg_delay(dev, NvRegUnknownSetupReg5, |
5402 | NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, | |
5403 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) | |
1d397f36 JP |
5404 | netdev_info(dev, |
5405 | "%s: SetupReg5, Bit 31 remained off\n", __func__); | |
1da177e4 | 5406 | |
7e680c22 | 5407 | writel(0, base + NvRegMIIMask); |
1da177e4 | 5408 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
eb798428 | 5409 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5410 | |
1da177e4 LT |
5411 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5412 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
5413 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 5414 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
5415 | |
5416 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
a433686c AA |
5417 | |
5418 | get_random_bytes(&low, sizeof(low)); | |
5419 | low &= NVREG_SLOTTIME_MASK; | |
5420 | if (np->desc_ver == DESC_VER_1) { | |
5421 | writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); | |
5422 | } else { | |
5423 | if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { | |
5424 | /* setup legacy backoff */ | |
5425 | writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); | |
5426 | } else { | |
5427 | writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); | |
5428 | nv_gear_backoff_reseed(dev); | |
5429 | } | |
5430 | } | |
9744e218 AA |
5431 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
5432 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
5433 | if (poll_interval == -1) { |
5434 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
5435 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
5436 | else | |
5437 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
78aea4fc | 5438 | } else |
a971c324 | 5439 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
1da177e4 LT |
5440 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5441 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
5442 | base + NvRegAdapterControl); | |
5443 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 5444 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
5445 | if (np->wolenabled) |
5446 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
5447 | |
5448 | i = readl(base + NvRegPowerState); | |
78aea4fc | 5449 | if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) |
1da177e4 LT |
5450 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
5451 | ||
5452 | pci_push(base); | |
5453 | udelay(10); | |
5454 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
5455 | ||
84b3932b | 5456 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5457 | pci_push(base); |
eb798428 | 5458 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5459 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5460 | pci_push(base); | |
5461 | ||
78aea4fc | 5462 | if (nv_request_irq(dev, 0)) |
84b3932b | 5463 | goto out_drain; |
1da177e4 LT |
5464 | |
5465 | /* ask for interrupts */ | |
84b3932b | 5466 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5467 | |
5468 | spin_lock_irq(&np->lock); | |
5469 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
5470 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5471 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5472 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5473 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
5474 | /* One manual link speed update: Interrupts are enabled, future link | |
5475 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
5476 | */ | |
5477 | { | |
5478 | u32 miistat; | |
5479 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 5480 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5481 | } |
1b1b3c9b MS |
5482 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5483 | * to init hw */ | |
5484 | np->linkspeed = 0; | |
1da177e4 | 5485 | ret = nv_update_linkspeed(dev); |
36b30ea9 | 5486 | nv_start_rxtx(dev); |
1da177e4 | 5487 | netif_start_queue(dev); |
08d93575 | 5488 | nv_napi_enable(dev); |
e27cdba5 | 5489 | |
1da177e4 LT |
5490 | if (ret) { |
5491 | netif_carrier_on(dev); | |
5492 | } else { | |
1d397f36 | 5493 | netdev_info(dev, "no link during initialization\n"); |
1da177e4 LT |
5494 | netif_carrier_off(dev); |
5495 | } | |
5496 | if (oom) | |
5497 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
5498 | |
5499 | /* start statistics timer */ | |
9c662435 | 5500 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
bfebbb88 DD |
5501 | mod_timer(&np->stats_poll, |
5502 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 | 5503 | |
1da177e4 LT |
5504 | spin_unlock_irq(&np->lock); |
5505 | ||
e19df76a SH |
5506 | /* If the loopback feature was set while the device was down, make sure |
5507 | * that it's set correctly now. | |
5508 | */ | |
5509 | if (dev->features & NETIF_F_LOOPBACK) | |
5510 | nv_set_loopback(dev, dev->features); | |
5511 | ||
1da177e4 LT |
5512 | return 0; |
5513 | out_drain: | |
36b30ea9 | 5514 | nv_drain_rxtx(dev); |
1da177e4 LT |
5515 | return ret; |
5516 | } | |
5517 | ||
5518 | static int nv_close(struct net_device *dev) | |
5519 | { | |
ac9c1897 | 5520 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
5521 | u8 __iomem *base; |
5522 | ||
5523 | spin_lock_irq(&np->lock); | |
5524 | np->in_shutdown = 1; | |
5525 | spin_unlock_irq(&np->lock); | |
08d93575 | 5526 | nv_napi_disable(dev); |
a7475906 | 5527 | synchronize_irq(np->pci_dev->irq); |
1da177e4 LT |
5528 | |
5529 | del_timer_sync(&np->oom_kick); | |
5530 | del_timer_sync(&np->nic_poll); | |
52da3578 | 5531 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
5532 | |
5533 | netif_stop_queue(dev); | |
5534 | spin_lock_irq(&np->lock); | |
1ff39eb6 | 5535 | nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */ |
36b30ea9 | 5536 | nv_stop_rxtx(dev); |
1da177e4 LT |
5537 | nv_txrx_reset(dev); |
5538 | ||
5539 | /* disable interrupts on the nic or we will lock up */ | |
5540 | base = get_hwbase(dev); | |
84b3932b | 5541 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5542 | pci_push(base); |
1da177e4 LT |
5543 | |
5544 | spin_unlock_irq(&np->lock); | |
5545 | ||
84b3932b | 5546 | nv_free_irq(dev); |
1da177e4 | 5547 | |
36b30ea9 | 5548 | nv_drain_rxtx(dev); |
1da177e4 | 5549 | |
5a9a8e32 | 5550 | if (np->wolenabled || !phy_power_down) { |
88d7d8b0 | 5551 | nv_txrx_gate(dev, false); |
2cc49a5c | 5552 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
1da177e4 | 5553 | nv_start_rx(dev); |
cb52deba ES |
5554 | } else { |
5555 | /* power down phy */ | |
5556 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5557 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); | |
88d7d8b0 | 5558 | nv_txrx_gate(dev, true); |
2cc49a5c | 5559 | } |
1da177e4 LT |
5560 | |
5561 | /* FIXME: power down nic */ | |
5562 | ||
5563 | return 0; | |
5564 | } | |
5565 | ||
b94426bd SH |
5566 | static const struct net_device_ops nv_netdev_ops = { |
5567 | .ndo_open = nv_open, | |
5568 | .ndo_stop = nv_close, | |
f5d827ae | 5569 | .ndo_get_stats64 = nv_get_stats64, |
00829823 SH |
5570 | .ndo_start_xmit = nv_start_xmit, |
5571 | .ndo_tx_timeout = nv_tx_timeout, | |
5572 | .ndo_change_mtu = nv_change_mtu, | |
569e1463 MM |
5573 | .ndo_fix_features = nv_fix_features, |
5574 | .ndo_set_features = nv_set_features, | |
00829823 SH |
5575 | .ndo_validate_addr = eth_validate_addr, |
5576 | .ndo_set_mac_address = nv_set_mac_address, | |
afc4b13d | 5577 | .ndo_set_rx_mode = nv_set_multicast, |
00829823 SH |
5578 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5579 | .ndo_poll_controller = nv_poll_controller, | |
5580 | #endif | |
5581 | }; | |
5582 | ||
5583 | static const struct net_device_ops nv_netdev_ops_optimized = { | |
5584 | .ndo_open = nv_open, | |
5585 | .ndo_stop = nv_close, | |
f5d827ae | 5586 | .ndo_get_stats64 = nv_get_stats64, |
00829823 | 5587 | .ndo_start_xmit = nv_start_xmit_optimized, |
b94426bd SH |
5588 | .ndo_tx_timeout = nv_tx_timeout, |
5589 | .ndo_change_mtu = nv_change_mtu, | |
569e1463 MM |
5590 | .ndo_fix_features = nv_fix_features, |
5591 | .ndo_set_features = nv_set_features, | |
b94426bd SH |
5592 | .ndo_validate_addr = eth_validate_addr, |
5593 | .ndo_set_mac_address = nv_set_mac_address, | |
afc4b13d | 5594 | .ndo_set_rx_mode = nv_set_multicast, |
b94426bd SH |
5595 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5596 | .ndo_poll_controller = nv_poll_controller, | |
5597 | #endif | |
5598 | }; | |
5599 | ||
d05919a1 | 5600 | static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
1da177e4 LT |
5601 | { |
5602 | struct net_device *dev; | |
5603 | struct fe_priv *np; | |
5604 | unsigned long addr; | |
5605 | u8 __iomem *base; | |
5606 | int err, i; | |
5070d340 | 5607 | u32 powerstate, txreg; |
7e680c22 AA |
5608 | u32 phystate_orig = 0, phystate; |
5609 | int phyinitialized = 0; | |
3f88ce49 JG |
5610 | static int printed_version; |
5611 | ||
5612 | if (!printed_version++) | |
294a554e JP |
5613 | pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n", |
5614 | FORCEDETH_VERSION); | |
1da177e4 LT |
5615 | |
5616 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
5617 | err = -ENOMEM; | |
5618 | if (!dev) | |
5619 | goto out; | |
5620 | ||
ac9c1897 | 5621 | np = netdev_priv(dev); |
bea3348e | 5622 | np->dev = dev; |
1da177e4 LT |
5623 | np->pci_dev = pci_dev; |
5624 | spin_lock_init(&np->lock); | |
f5d827ae | 5625 | spin_lock_init(&np->hwstats_lock); |
1da177e4 | 5626 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
827da44c JS |
5627 | u64_stats_init(&np->swstats_rx_syncp); |
5628 | u64_stats_init(&np->swstats_tx_syncp); | |
1da177e4 | 5629 | |
de55558d AKC |
5630 | setup_timer(&np->oom_kick, nv_do_rx_refill, (unsigned long)dev); |
5631 | setup_timer(&np->nic_poll, nv_do_nic_poll, (unsigned long)dev); | |
8f5f6982 | 5632 | init_timer_deferrable(&np->stats_poll); |
52da3578 | 5633 | np->stats_poll.data = (unsigned long) dev; |
c061b18d | 5634 | np->stats_poll.function = nv_do_stats_poll; /* timer handler */ |
1da177e4 LT |
5635 | |
5636 | err = pci_enable_device(pci_dev); | |
3f88ce49 | 5637 | if (err) |
1da177e4 | 5638 | goto out_free; |
1da177e4 LT |
5639 | |
5640 | pci_set_master(pci_dev); | |
5641 | ||
5642 | err = pci_request_regions(pci_dev, DRV_NAME); | |
5643 | if (err < 0) | |
5644 | goto out_disable; | |
5645 | ||
9c662435 | 5646 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
57fff698 AA |
5647 | np->register_size = NV_PCI_REGSZ_VER3; |
5648 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | |
86a0f043 AA |
5649 | np->register_size = NV_PCI_REGSZ_VER2; |
5650 | else | |
5651 | np->register_size = NV_PCI_REGSZ_VER1; | |
5652 | ||
1da177e4 LT |
5653 | err = -EINVAL; |
5654 | addr = 0; | |
5655 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1da177e4 | 5656 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
86a0f043 | 5657 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
5658 | addr = pci_resource_start(pci_dev, i); |
5659 | break; | |
5660 | } | |
5661 | } | |
5662 | if (i == DEVICE_COUNT_RESOURCE) { | |
b2ba08e6 | 5663 | dev_info(&pci_dev->dev, "Couldn't find register window\n"); |
1da177e4 LT |
5664 | goto out_relreg; |
5665 | } | |
5666 | ||
86a0f043 AA |
5667 | /* copy of driver data */ |
5668 | np->driver_data = id->driver_data; | |
9f3f7910 AA |
5669 | /* copy of device id */ |
5670 | np->device_id = id->device; | |
86a0f043 | 5671 | |
1da177e4 | 5672 | /* handle different descriptor versions */ |
ee73362c MS |
5673 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
5674 | /* packet format 3: supports 40-bit addressing */ | |
5675 | np->desc_ver = DESC_VER_3; | |
84b3932b | 5676 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 | 5677 | if (dma_64bit) { |
6afd142f | 5678 | if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) |
b2ba08e6 JP |
5679 | dev_info(&pci_dev->dev, |
5680 | "64-bit DMA failed, using 32-bit addressing\n"); | |
3f88ce49 | 5681 | else |
69fe3fd7 | 5682 | dev->features |= NETIF_F_HIGHDMA; |
6afd142f | 5683 | if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { |
b2ba08e6 JP |
5684 | dev_info(&pci_dev->dev, |
5685 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | |
69fe3fd7 | 5686 | } |
ee73362c MS |
5687 | } |
5688 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
5689 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 5690 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 5691 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
5692 | } else { |
5693 | /* original packet format */ | |
5694 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 5695 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 5696 | } |
ee73362c MS |
5697 | |
5698 | np->pkt_limit = NV_PKTLIMIT_1; | |
5699 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
5700 | np->pkt_limit = NV_PKTLIMIT_2; | |
5701 | ||
8a4ae7f2 MS |
5702 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
5703 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | |
569e1463 MM |
5704 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
5705 | NETIF_F_TSO | NETIF_F_RXCSUM; | |
21828163 | 5706 | } |
8a4ae7f2 | 5707 | |
ee407b02 AA |
5708 | np->vlanctl_bits = 0; |
5709 | if (id->driver_data & DEV_HAS_VLAN) { | |
5710 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
f646968f PM |
5711 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | |
5712 | NETIF_F_HW_VLAN_CTAG_TX; | |
ee407b02 AA |
5713 | } |
5714 | ||
0891b0e0 JP |
5715 | dev->features |= dev->hw_features; |
5716 | ||
e19df76a SH |
5717 | /* Add loopback capability to the device. */ |
5718 | dev->hw_features |= NETIF_F_LOOPBACK; | |
5719 | ||
44770e11 JW |
5720 | /* MTU range: 64 - 1500 or 9100 */ |
5721 | dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN; | |
5722 | dev->max_mtu = np->pkt_limit; | |
5723 | ||
b6d0773f | 5724 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5289b4c4 AA |
5725 | if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || |
5726 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || | |
5727 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { | |
b6d0773f | 5728 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 5729 | } |
f3b197ac | 5730 | |
1da177e4 | 5731 | err = -ENOMEM; |
86a0f043 | 5732 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
5733 | if (!np->base) |
5734 | goto out_relreg; | |
ee73362c | 5735 | |
eafa59f6 AA |
5736 | np->rx_ring_size = RX_RING_DEFAULT; |
5737 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 5738 | |
36b30ea9 | 5739 | if (!nv_optimized(np)) { |
ee73362c | 5740 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
eafa59f6 | 5741 | sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5742 | &np->ring_addr); |
5743 | if (!np->rx_ring.orig) | |
5744 | goto out_unmap; | |
eafa59f6 | 5745 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c MS |
5746 | } else { |
5747 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 5748 | sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5749 | &np->ring_addr); |
5750 | if (!np->rx_ring.ex) | |
5751 | goto out_unmap; | |
eafa59f6 AA |
5752 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5753 | } | |
dd00cc48 YP |
5754 | np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); |
5755 | np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); | |
761fcd9e | 5756 | if (!np->rx_skb || !np->tx_skb) |
eafa59f6 | 5757 | goto out_freering; |
1da177e4 | 5758 | |
36b30ea9 | 5759 | if (!nv_optimized(np)) |
00829823 | 5760 | dev->netdev_ops = &nv_netdev_ops; |
86b22b0d | 5761 | else |
00829823 | 5762 | dev->netdev_ops = &nv_netdev_ops_optimized; |
b94426bd | 5763 | |
bea3348e | 5764 | netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); |
7ad24ea4 | 5765 | dev->ethtool_ops = &ops; |
1da177e4 LT |
5766 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
5767 | ||
5768 | pci_set_drvdata(pci_dev, dev); | |
5769 | ||
5770 | /* read the mac address */ | |
5771 | base = get_hwbase(dev); | |
5772 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
5773 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
5774 | ||
5070d340 AA |
5775 | /* check the workaround bit for correct mac address order */ |
5776 | txreg = readl(base + NvRegTransmitPoll); | |
a376e79c | 5777 | if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { |
5070d340 AA |
5778 | /* mac address is already in correct order */ |
5779 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5780 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5781 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5782 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5783 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5784 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
a376e79c AA |
5785 | } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5786 | /* mac address is already in correct order */ | |
5787 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5788 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5789 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5790 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5791 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5792 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5793 | /* | |
5794 | * Set orig mac address back to the reversed version. | |
5795 | * This flag will be cleared during low power transition. | |
5796 | * Therefore, we should always put back the reversed address. | |
5797 | */ | |
5798 | np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + | |
5799 | (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24); | |
5800 | np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); | |
5070d340 AA |
5801 | } else { |
5802 | /* need to reverse mac address to correct order */ | |
5803 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5804 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5805 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5806 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5807 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5808 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5070d340 | 5809 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
c20ec761 JP |
5810 | dev_dbg(&pci_dev->dev, |
5811 | "%s: set workaround bit for reversed mac addr\n", | |
5812 | __func__); | |
5070d340 | 5813 | } |
1da177e4 | 5814 | |
aaeb6cdf | 5815 | if (!is_valid_ether_addr(dev->dev_addr)) { |
1da177e4 LT |
5816 | /* |
5817 | * Bad mac address. At least one bios sets the mac address | |
5818 | * to 01:23:45:67:89:ab | |
5819 | */ | |
b2ba08e6 | 5820 | dev_err(&pci_dev->dev, |
c20ec761 | 5821 | "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n", |
78aea4fc | 5822 | dev->dev_addr); |
7ce5d222 | 5823 | eth_hw_addr_random(dev); |
c20ec761 JP |
5824 | dev_err(&pci_dev->dev, |
5825 | "Using random MAC address: %pM\n", dev->dev_addr); | |
1da177e4 LT |
5826 | } |
5827 | ||
f1489653 AA |
5828 | /* set mac address */ |
5829 | nv_copy_mac_to_hw(dev); | |
5830 | ||
1da177e4 LT |
5831 | /* disable WOL */ |
5832 | writel(0, base + NvRegWakeUpFlags); | |
5833 | np->wolenabled = 0; | |
dba5a68a | 5834 | device_set_wakeup_enable(&pci_dev->dev, false); |
1da177e4 | 5835 | |
86a0f043 | 5836 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
86a0f043 AA |
5837 | |
5838 | /* take phy and nic out of low power mode */ | |
5839 | powerstate = readl(base + NvRegPowerState2); | |
5840 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
3c2e1c11 | 5841 | if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) && |
44c10138 | 5842 | pci_dev->revision >= 0xA3) |
86a0f043 AA |
5843 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
5844 | writel(powerstate, base + NvRegPowerState2); | |
5845 | } | |
5846 | ||
78aea4fc | 5847 | if (np->desc_ver == DESC_VER_1) |
ac9c1897 | 5848 | np->tx_flags = NV_TX_VALID; |
78aea4fc | 5849 | else |
ac9c1897 | 5850 | np->tx_flags = NV_TX2_VALID; |
9e184767 AA |
5851 | |
5852 | np->msi_flags = 0; | |
78aea4fc | 5853 | if ((id->driver_data & DEV_HAS_MSI) && msi) |
9e184767 | 5854 | np->msi_flags |= NV_MSI_CAPABLE; |
78aea4fc | 5855 | |
9e184767 AA |
5856 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
5857 | /* msix has had reported issues when modifying irqmask | |
5858 | as in the case of napi, therefore, disable for now | |
5859 | */ | |
0a12761b | 5860 | #if 0 |
9e184767 AA |
5861 | np->msi_flags |= NV_MSI_X_CAPABLE; |
5862 | #endif | |
5863 | } | |
5864 | ||
5865 | if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) { | |
a971c324 | 5866 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5867 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5868 | np->msi_flags |= 0x0001; | |
9e184767 AA |
5869 | } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC && |
5870 | !(id->driver_data & DEV_NEED_TIMERIRQ)) { | |
5871 | /* start off in throughput mode */ | |
5872 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5873 | /* remove support for msix mode */ | |
5874 | np->msi_flags &= ~NV_MSI_X_CAPABLE; | |
5875 | } else { | |
5876 | optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; | |
5877 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5878 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ | |
5879 | np->msi_flags |= 0x0003; | |
d33a73c8 | 5880 | } |
a971c324 | 5881 | |
1da177e4 LT |
5882 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5883 | np->irqmask |= NVREG_IRQ_TIMER; | |
5884 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
1da177e4 LT |
5885 | np->need_linktimer = 1; |
5886 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5887 | } else { | |
1da177e4 LT |
5888 | np->need_linktimer = 0; |
5889 | } | |
5890 | ||
3b446c3e AA |
5891 | /* Limit the number of tx's outstanding for hw bug */ |
5892 | if (id->driver_data & DEV_NEED_TX_LIMIT) { | |
5893 | np->tx_limit = 1; | |
5c659322 | 5894 | if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) && |
3b446c3e AA |
5895 | pci_dev->revision >= 0xA2) |
5896 | np->tx_limit = 0; | |
5897 | } | |
5898 | ||
7e680c22 AA |
5899 | /* clear phy state and temporarily halt phy interrupts */ |
5900 | writel(0, base + NvRegMIIMask); | |
5901 | phystate = readl(base + NvRegAdapterControl); | |
5902 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5903 | phystate_orig = 1; | |
5904 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5905 | writel(phystate, base + NvRegAdapterControl); | |
5906 | } | |
eb798428 | 5907 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
7e680c22 AA |
5908 | |
5909 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5910 | /* management unit running on the mac? */ |
cac1c52c AA |
5911 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) && |
5912 | (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) && | |
5913 | nv_mgmt_acquire_sema(dev) && | |
5914 | nv_mgmt_get_version(dev)) { | |
5915 | np->mac_in_use = 1; | |
78aea4fc | 5916 | if (np->mgmt_version > 0) |
cac1c52c | 5917 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; |
cac1c52c AA |
5918 | /* management unit setup the phy already? */ |
5919 | if (np->mac_in_use && | |
5920 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5921 | NVREG_XMITCTL_SYNC_PHY_INIT)) { | |
5922 | /* phy is inited by mgmt unit */ | |
5923 | phyinitialized = 1; | |
cac1c52c AA |
5924 | } else { |
5925 | /* we need to init the phy */ | |
7e680c22 AA |
5926 | } |
5927 | } | |
5928 | } | |
5929 | ||
1da177e4 | 5930 | /* find a suitable phy */ |
7a33e45a | 5931 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5932 | int id1, id2; |
7a33e45a | 5933 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5934 | |
5935 | spin_lock_irq(&np->lock); | |
7a33e45a | 5936 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5937 | spin_unlock_irq(&np->lock); |
5938 | if (id1 < 0 || id1 == 0xffff) | |
5939 | continue; | |
5940 | spin_lock_irq(&np->lock); | |
7a33e45a | 5941 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5942 | spin_unlock_irq(&np->lock); |
5943 | if (id2 < 0 || id2 == 0xffff) | |
5944 | continue; | |
5945 | ||
edf7e5ec | 5946 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5947 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5948 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
7a33e45a | 5949 | np->phyaddr = phyaddr; |
1da177e4 | 5950 | np->phy_oui = id1 | id2; |
9f3f7910 AA |
5951 | |
5952 | /* Realtek hardcoded phy id1 to all zero's on certain phys */ | |
5953 | if (np->phy_oui == PHY_OUI_REALTEK2) | |
5954 | np->phy_oui = PHY_OUI_REALTEK; | |
5955 | /* Setup phy revision for Realtek */ | |
5956 | if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) | |
5957 | np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; | |
5958 | ||
1da177e4 LT |
5959 | break; |
5960 | } | |
7a33e45a | 5961 | if (i == 33) { |
b2ba08e6 | 5962 | dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n"); |
eafa59f6 | 5963 | goto out_error; |
1da177e4 | 5964 | } |
f3b197ac | 5965 | |
7e680c22 AA |
5966 | if (!phyinitialized) { |
5967 | /* reset it */ | |
5968 | phy_init(dev); | |
f35723ec AA |
5969 | } else { |
5970 | /* see if it is a gigabit phy */ | |
5971 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
78aea4fc | 5972 | if (mii_status & PHY_GIGABIT) |
f35723ec | 5973 | np->gigabit = PHY_GIGABIT; |
7e680c22 | 5974 | } |
1da177e4 LT |
5975 | |
5976 | /* set default link speed settings */ | |
5977 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
5978 | np->duplex = 0; | |
5979 | np->autoneg = 1; | |
5980 | ||
5981 | err = register_netdev(dev); | |
5982 | if (err) { | |
b2ba08e6 | 5983 | dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err); |
eafa59f6 | 5984 | goto out_error; |
1da177e4 | 5985 | } |
3f88ce49 | 5986 | |
3f0a1b58 | 5987 | netif_carrier_off(dev); |
5988 | ||
5989 | /* Some NICs freeze when TX pause is enabled while NIC is | |
5990 | * down, and this stays across warm reboots. The sequence | |
5991 | * below should be enough to recover from that state. | |
5992 | */ | |
5993 | nv_update_pause(dev, 0); | |
5994 | nv_start_tx(dev); | |
5995 | nv_stop_tx(dev); | |
5996 | ||
9331db4f JP |
5997 | if (id->driver_data & DEV_HAS_VLAN) |
5998 | nv_vlan_mode(dev, dev->features); | |
0891b0e0 | 5999 | |
b2ba08e6 JP |
6000 | dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n", |
6001 | dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); | |
6002 | ||
e19df76a | 6003 | dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", |
b2ba08e6 JP |
6004 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", |
6005 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? | |
78aea4fc | 6006 | "csum " : "", |
f646968f PM |
6007 | dev->features & (NETIF_F_HW_VLAN_CTAG_RX | |
6008 | NETIF_F_HW_VLAN_CTAG_TX) ? | |
78aea4fc | 6009 | "vlan " : "", |
e19df76a SH |
6010 | dev->features & (NETIF_F_LOOPBACK) ? |
6011 | "loopback " : "", | |
b2ba08e6 JP |
6012 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", |
6013 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | |
6014 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
6015 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | |
6016 | np->need_linktimer ? "lnktim " : "", | |
6017 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | |
6018 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | |
6019 | np->desc_ver); | |
1da177e4 LT |
6020 | |
6021 | return 0; | |
6022 | ||
eafa59f6 | 6023 | out_error: |
7e680c22 AA |
6024 | if (phystate_orig) |
6025 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
eafa59f6 AA |
6026 | out_freering: |
6027 | free_rings(dev); | |
1da177e4 LT |
6028 | out_unmap: |
6029 | iounmap(get_hwbase(dev)); | |
6030 | out_relreg: | |
6031 | pci_release_regions(pci_dev); | |
6032 | out_disable: | |
6033 | pci_disable_device(pci_dev); | |
6034 | out_free: | |
6035 | free_netdev(dev); | |
6036 | out: | |
6037 | return err; | |
6038 | } | |
6039 | ||
9f3f7910 AA |
6040 | static void nv_restore_phy(struct net_device *dev) |
6041 | { | |
6042 | struct fe_priv *np = netdev_priv(dev); | |
6043 | u16 phy_reserved, mii_control; | |
6044 | ||
6045 | if (np->phy_oui == PHY_OUI_REALTEK && | |
6046 | np->phy_model == PHY_MODEL_REALTEK_8201 && | |
6047 | phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
6048 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); | |
6049 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
6050 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
6051 | phy_reserved |= PHY_REALTEK_INIT8; | |
6052 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); | |
6053 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); | |
6054 | ||
6055 | /* restart auto negotiation */ | |
6056 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
6057 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
6058 | mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); | |
6059 | } | |
6060 | } | |
6061 | ||
f55c21fd | 6062 | static void nv_restore_mac_addr(struct pci_dev *pci_dev) |
1da177e4 LT |
6063 | { |
6064 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
6065 | struct fe_priv *np = netdev_priv(dev); |
6066 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 | 6067 | |
f1489653 AA |
6068 | /* special op: write back the misordered MAC address - otherwise |
6069 | * the next nv_probe would see a wrong address. | |
6070 | */ | |
6071 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
6072 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |
2e3884b5 BS |
6073 | writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV, |
6074 | base + NvRegTransmitPoll); | |
f55c21fd YL |
6075 | } |
6076 | ||
d05919a1 | 6077 | static void nv_remove(struct pci_dev *pci_dev) |
f55c21fd YL |
6078 | { |
6079 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
6080 | ||
6081 | unregister_netdev(dev); | |
6082 | ||
6083 | nv_restore_mac_addr(pci_dev); | |
f1489653 | 6084 | |
9f3f7910 AA |
6085 | /* restore any phy related changes */ |
6086 | nv_restore_phy(dev); | |
6087 | ||
cac1c52c AA |
6088 | nv_mgmt_release_sema(dev); |
6089 | ||
1da177e4 | 6090 | /* free all structures */ |
eafa59f6 | 6091 | free_rings(dev); |
1da177e4 LT |
6092 | iounmap(get_hwbase(dev)); |
6093 | pci_release_regions(pci_dev); | |
6094 | pci_disable_device(pci_dev); | |
6095 | free_netdev(dev); | |
1da177e4 LT |
6096 | } |
6097 | ||
94252763 | 6098 | #ifdef CONFIG_PM_SLEEP |
dba5a68a | 6099 | static int nv_suspend(struct device *device) |
a189317f | 6100 | { |
dba5a68a | 6101 | struct pci_dev *pdev = to_pci_dev(device); |
a189317f FR |
6102 | struct net_device *dev = pci_get_drvdata(pdev); |
6103 | struct fe_priv *np = netdev_priv(dev); | |
1a1ca861 TD |
6104 | u8 __iomem *base = get_hwbase(dev); |
6105 | int i; | |
a189317f | 6106 | |
25d90810 | 6107 | if (netif_running(dev)) { |
78aea4fc | 6108 | /* Gross. */ |
25d90810 TD |
6109 | nv_close(dev); |
6110 | } | |
a189317f FR |
6111 | netif_device_detach(dev); |
6112 | ||
1a1ca861 | 6113 | /* save non-pci configuration space */ |
78aea4fc | 6114 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
1a1ca861 TD |
6115 | np->saved_config_space[i] = readl(base + i*sizeof(u32)); |
6116 | ||
a189317f FR |
6117 | return 0; |
6118 | } | |
6119 | ||
dba5a68a | 6120 | static int nv_resume(struct device *device) |
a189317f | 6121 | { |
dba5a68a | 6122 | struct pci_dev *pdev = to_pci_dev(device); |
a189317f | 6123 | struct net_device *dev = pci_get_drvdata(pdev); |
1a1ca861 | 6124 | struct fe_priv *np = netdev_priv(dev); |
a376e79c | 6125 | u8 __iomem *base = get_hwbase(dev); |
1a1ca861 | 6126 | int i, rc = 0; |
a189317f | 6127 | |
1a1ca861 | 6128 | /* restore non-pci configuration space */ |
78aea4fc | 6129 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
1a1ca861 | 6130 | writel(np->saved_config_space[i], base+i*sizeof(u32)); |
a376e79c | 6131 | |
3c2e1c11 AA |
6132 | if (np->driver_data & DEV_NEED_MSI_FIX) |
6133 | pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE); | |
b6e4405b | 6134 | |
35a7433c ES |
6135 | /* restore phy state, including autoneg */ |
6136 | phy_init(dev); | |
6137 | ||
25d90810 TD |
6138 | netif_device_attach(dev); |
6139 | if (netif_running(dev)) { | |
6140 | rc = nv_open(dev); | |
6141 | nv_set_multicast(dev); | |
6142 | } | |
a189317f FR |
6143 | return rc; |
6144 | } | |
f735a2a1 | 6145 | |
dba5a68a RW |
6146 | static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume); |
6147 | #define NV_PM_OPS (&nv_pm_ops) | |
6148 | ||
94252763 ML |
6149 | #else |
6150 | #define NV_PM_OPS NULL | |
6151 | #endif /* CONFIG_PM_SLEEP */ | |
6152 | ||
6153 | #ifdef CONFIG_PM | |
f735a2a1 TD |
6154 | static void nv_shutdown(struct pci_dev *pdev) |
6155 | { | |
6156 | struct net_device *dev = pci_get_drvdata(pdev); | |
6157 | struct fe_priv *np = netdev_priv(dev); | |
6158 | ||
6159 | if (netif_running(dev)) | |
6160 | nv_close(dev); | |
6161 | ||
34edaa88 TD |
6162 | /* |
6163 | * Restore the MAC so a kernel started by kexec won't get confused. | |
6164 | * If we really go for poweroff, we must not restore the MAC, | |
6165 | * otherwise the MAC for WOL will be reversed at least on some boards. | |
6166 | */ | |
78aea4fc | 6167 | if (system_state != SYSTEM_POWER_OFF) |
34edaa88 | 6168 | nv_restore_mac_addr(pdev); |
f55c21fd | 6169 | |
f735a2a1 | 6170 | pci_disable_device(pdev); |
34edaa88 TD |
6171 | /* |
6172 | * Apparently it is not possible to reinitialise from D3 hot, | |
6173 | * only put the device into D3 if we really go for poweroff. | |
6174 | */ | |
3cb5599a | 6175 | if (system_state == SYSTEM_POWER_OFF) { |
dba5a68a | 6176 | pci_wake_from_d3(pdev, np->wolenabled); |
3cb5599a RW |
6177 | pci_set_power_state(pdev, PCI_D3hot); |
6178 | } | |
f735a2a1 | 6179 | } |
a189317f | 6180 | #else |
f735a2a1 | 6181 | #define nv_shutdown NULL |
a189317f FR |
6182 | #endif /* CONFIG_PM */ |
6183 | ||
9baa3c34 | 6184 | static const struct pci_device_id pci_tbl[] = { |
1da177e4 | 6185 | { /* nForce Ethernet Controller */ |
3c2e1c11 | 6186 | PCI_DEVICE(0x10DE, 0x01C3), |
c2dba06d | 6187 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
6188 | }, |
6189 | { /* nForce2 Ethernet Controller */ | |
3c2e1c11 | 6190 | PCI_DEVICE(0x10DE, 0x0066), |
c2dba06d | 6191 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
6192 | }, |
6193 | { /* nForce3 Ethernet Controller */ | |
3c2e1c11 | 6194 | PCI_DEVICE(0x10DE, 0x00D6), |
c2dba06d | 6195 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
6196 | }, |
6197 | { /* nForce3 Ethernet Controller */ | |
3c2e1c11 | 6198 | PCI_DEVICE(0x10DE, 0x0086), |
8a4ae7f2 | 6199 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6200 | }, |
6201 | { /* nForce3 Ethernet Controller */ | |
3c2e1c11 | 6202 | PCI_DEVICE(0x10DE, 0x008C), |
8a4ae7f2 | 6203 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6204 | }, |
6205 | { /* nForce3 Ethernet Controller */ | |
3c2e1c11 | 6206 | PCI_DEVICE(0x10DE, 0x00E6), |
8a4ae7f2 | 6207 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6208 | }, |
6209 | { /* nForce3 Ethernet Controller */ | |
3c2e1c11 | 6210 | PCI_DEVICE(0x10DE, 0x00DF), |
8a4ae7f2 | 6211 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6212 | }, |
6213 | { /* CK804 Ethernet Controller */ | |
3c2e1c11 | 6214 | PCI_DEVICE(0x10DE, 0x0056), |
033e97b2 | 6215 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
6216 | }, |
6217 | { /* CK804 Ethernet Controller */ | |
3c2e1c11 | 6218 | PCI_DEVICE(0x10DE, 0x0057), |
033e97b2 | 6219 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
6220 | }, |
6221 | { /* MCP04 Ethernet Controller */ | |
3c2e1c11 | 6222 | PCI_DEVICE(0x10DE, 0x0037), |
9e184767 | 6223 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
6224 | }, |
6225 | { /* MCP04 Ethernet Controller */ | |
3c2e1c11 | 6226 | PCI_DEVICE(0x10DE, 0x0038), |
9e184767 | 6227 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 | 6228 | }, |
9992d4aa | 6229 | { /* MCP51 Ethernet Controller */ |
3c2e1c11 AA |
6230 | PCI_DEVICE(0x10DE, 0x0268), |
6231 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX, | |
9992d4aa MS |
6232 | }, |
6233 | { /* MCP51 Ethernet Controller */ | |
3c2e1c11 AA |
6234 | PCI_DEVICE(0x10DE, 0x0269), |
6235 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX, | |
9992d4aa | 6236 | }, |
f49d16ef | 6237 | { /* MCP55 Ethernet Controller */ |
3c2e1c11 | 6238 | PCI_DEVICE(0x10DE, 0x0372), |
7b5e078c | 6239 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX, |
f49d16ef MS |
6240 | }, |
6241 | { /* MCP55 Ethernet Controller */ | |
3c2e1c11 | 6242 | PCI_DEVICE(0x10DE, 0x0373), |
7b5e078c | 6243 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX, |
f49d16ef | 6244 | }, |
c99ce7ee | 6245 | { /* MCP61 Ethernet Controller */ |
3c2e1c11 | 6246 | PCI_DEVICE(0x10DE, 0x03E5), |
7b5e078c | 6247 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX, |
c99ce7ee AA |
6248 | }, |
6249 | { /* MCP61 Ethernet Controller */ | |
3c2e1c11 | 6250 | PCI_DEVICE(0x10DE, 0x03E6), |
7b5e078c | 6251 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX, |
c99ce7ee AA |
6252 | }, |
6253 | { /* MCP61 Ethernet Controller */ | |
3c2e1c11 | 6254 | PCI_DEVICE(0x10DE, 0x03EE), |
7b5e078c | 6255 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX, |
c99ce7ee AA |
6256 | }, |
6257 | { /* MCP61 Ethernet Controller */ | |
3c2e1c11 | 6258 | PCI_DEVICE(0x10DE, 0x03EF), |
7b5e078c | 6259 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX, |
c99ce7ee AA |
6260 | }, |
6261 | { /* MCP65 Ethernet Controller */ | |
3c2e1c11 | 6262 | PCI_DEVICE(0x10DE, 0x0450), |
7b5e078c | 6263 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
c99ce7ee AA |
6264 | }, |
6265 | { /* MCP65 Ethernet Controller */ | |
3c2e1c11 | 6266 | PCI_DEVICE(0x10DE, 0x0451), |
7b5e078c | 6267 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
c99ce7ee AA |
6268 | }, |
6269 | { /* MCP65 Ethernet Controller */ | |
3c2e1c11 | 6270 | PCI_DEVICE(0x10DE, 0x0452), |
7b5e078c | 6271 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
c99ce7ee AA |
6272 | }, |
6273 | { /* MCP65 Ethernet Controller */ | |
3c2e1c11 | 6274 | PCI_DEVICE(0x10DE, 0x0453), |
7b5e078c | 6275 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
c99ce7ee | 6276 | }, |
f4344848 | 6277 | { /* MCP67 Ethernet Controller */ |
3c2e1c11 | 6278 | PCI_DEVICE(0x10DE, 0x054C), |
7b5e078c | 6279 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
f4344848 AA |
6280 | }, |
6281 | { /* MCP67 Ethernet Controller */ | |
3c2e1c11 | 6282 | PCI_DEVICE(0x10DE, 0x054D), |
7b5e078c | 6283 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
f4344848 AA |
6284 | }, |
6285 | { /* MCP67 Ethernet Controller */ | |
3c2e1c11 | 6286 | PCI_DEVICE(0x10DE, 0x054E), |
7b5e078c | 6287 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
f4344848 AA |
6288 | }, |
6289 | { /* MCP67 Ethernet Controller */ | |
3c2e1c11 | 6290 | PCI_DEVICE(0x10DE, 0x054F), |
7b5e078c | 6291 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
f4344848 | 6292 | }, |
1398661b | 6293 | { /* MCP73 Ethernet Controller */ |
3c2e1c11 | 6294 | PCI_DEVICE(0x10DE, 0x07DC), |
7b5e078c | 6295 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
1398661b AA |
6296 | }, |
6297 | { /* MCP73 Ethernet Controller */ | |
3c2e1c11 | 6298 | PCI_DEVICE(0x10DE, 0x07DD), |
7b5e078c | 6299 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
1398661b AA |
6300 | }, |
6301 | { /* MCP73 Ethernet Controller */ | |
3c2e1c11 | 6302 | PCI_DEVICE(0x10DE, 0x07DE), |
7b5e078c | 6303 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
1398661b AA |
6304 | }, |
6305 | { /* MCP73 Ethernet Controller */ | |
3c2e1c11 | 6306 | PCI_DEVICE(0x10DE, 0x07DF), |
7b5e078c | 6307 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX, |
1398661b | 6308 | }, |
96fd4cd3 | 6309 | { /* MCP77 Ethernet Controller */ |
3c2e1c11 | 6310 | PCI_DEVICE(0x10DE, 0x0760), |
7b5e078c | 6311 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
96fd4cd3 AA |
6312 | }, |
6313 | { /* MCP77 Ethernet Controller */ | |
3c2e1c11 | 6314 | PCI_DEVICE(0x10DE, 0x0761), |
7b5e078c | 6315 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
96fd4cd3 AA |
6316 | }, |
6317 | { /* MCP77 Ethernet Controller */ | |
3c2e1c11 | 6318 | PCI_DEVICE(0x10DE, 0x0762), |
7b5e078c | 6319 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
96fd4cd3 AA |
6320 | }, |
6321 | { /* MCP77 Ethernet Controller */ | |
3c2e1c11 | 6322 | PCI_DEVICE(0x10DE, 0x0763), |
7b5e078c | 6323 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
96fd4cd3 | 6324 | }, |
490dde89 | 6325 | { /* MCP79 Ethernet Controller */ |
3c2e1c11 | 6326 | PCI_DEVICE(0x10DE, 0x0AB0), |
7b5e078c | 6327 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
490dde89 AA |
6328 | }, |
6329 | { /* MCP79 Ethernet Controller */ | |
3c2e1c11 | 6330 | PCI_DEVICE(0x10DE, 0x0AB1), |
7b5e078c | 6331 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
490dde89 AA |
6332 | }, |
6333 | { /* MCP79 Ethernet Controller */ | |
3c2e1c11 | 6334 | PCI_DEVICE(0x10DE, 0x0AB2), |
7b5e078c | 6335 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
490dde89 AA |
6336 | }, |
6337 | { /* MCP79 Ethernet Controller */ | |
3c2e1c11 | 6338 | PCI_DEVICE(0x10DE, 0x0AB3), |
7b5e078c | 6339 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX, |
490dde89 | 6340 | }, |
3df81c4e AA |
6341 | { /* MCP89 Ethernet Controller */ |
6342 | PCI_DEVICE(0x10DE, 0x0D7D), | |
7b5e078c | 6343 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX, |
3df81c4e | 6344 | }, |
1da177e4 LT |
6345 | {0,}, |
6346 | }; | |
6347 | ||
4f45c40f | 6348 | static struct pci_driver forcedeth_pci_driver = { |
3f88ce49 JG |
6349 | .name = DRV_NAME, |
6350 | .id_table = pci_tbl, | |
6351 | .probe = nv_probe, | |
d05919a1 | 6352 | .remove = nv_remove, |
f735a2a1 | 6353 | .shutdown = nv_shutdown, |
dba5a68a | 6354 | .driver.pm = NV_PM_OPS, |
1da177e4 LT |
6355 | }; |
6356 | ||
1da177e4 LT |
6357 | module_param(max_interrupt_work, int, 0); |
6358 | MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); | |
a971c324 | 6359 | module_param(optimization_mode, int, 0); |
9e184767 | 6360 | MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load."); |
a971c324 AA |
6361 | module_param(poll_interval, int, 0); |
6362 | MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); | |
69fe3fd7 AA |
6363 | module_param(msi, int, 0); |
6364 | MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
6365 | module_param(msix, int, 0); | |
6366 | MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
6367 | module_param(dma_64bit, int, 0); | |
6368 | MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); | |
9f3f7910 AA |
6369 | module_param(phy_cross, int, 0); |
6370 | MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0."); | |
5a9a8e32 ES |
6371 | module_param(phy_power_down, int, 0); |
6372 | MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0)."); | |
1ec4f2d3 SN |
6373 | module_param(debug_tx_timeout, bool, 0); |
6374 | MODULE_PARM_DESC(debug_tx_timeout, | |
6375 | "Dump tx related registers and ring when tx_timeout happens"); | |
1da177e4 | 6376 | |
4f45c40f | 6377 | module_pci_driver(forcedeth_pci_driver); |
1da177e4 LT |
6378 | MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); |
6379 | MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); | |
6380 | MODULE_LICENSE("GPL"); | |
1da177e4 | 6381 | MODULE_DEVICE_TABLE(pci, pci_tbl); |