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[mirror_ubuntu-kernels.git] / drivers / net / ethernet / oki-semi / pch_gbe / pch_gbe_main.c
CommitLineData
77555ee7
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
1a0bdadb 3 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
77555ee7
MO		 4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
0ab75ae8 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
77555ee7
MO		 18 */
19
20#include "pch_gbe.h"
c63ebdf0 21#include "pch_gbe_phy.h"
9d9779e7 22#include <linux/module.h>
1a0bdadb
TS		 23#include <linux/net_tstamp.h>
24#include <linux/ptp_classify.h>
f1a26fdf 25#include <linux/gpio.h>
77555ee7 26
f2c31662 27#define DRV_VERSION "1.01"
77555ee7
MO		 28const char pch_driver_version[] = DRV_VERSION;
29
77555ee7
MO		 30#define PCH_GBE_MAR_ENTRIES 16
31#define PCH_GBE_SHORT_PKT 64
32#define DSC_INIT16 0xC000
33#define PCH_GBE_DMA_ALIGN 0
ac096642 34#define PCH_GBE_DMA_PADDING 2
913f53e4 35#define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */
77555ee7 36#define PCH_GBE_PCI_BAR 1
124d770a 37#define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
77555ee7 38
0ce26a1c 39#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802
b0e6baf5 40
0ce26a1c 41#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
7756332f
TO		 42#define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
43
77555ee7
MO		 44#define PCH_GBE_TX_WEIGHT 64
45#define PCH_GBE_RX_WEIGHT 64
46#define PCH_GBE_RX_BUFFER_WRITE 16
47
48/* Initialize the wake-on-LAN settings */
49#define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
50
51#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
52 PCH_GBE_CHIP_TYPE_INTERNAL | \
ce3dad0f 53 PCH_GBE_RGMII_MODE_RGMII \
77555ee7
MO		 54 )
55
56/* Ethertype field values */
124d770a 57#define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
77555ee7
MO		 58#define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
59#define PCH_GBE_FRAME_SIZE_2048 2048
60#define PCH_GBE_FRAME_SIZE_4096 4096
61#define PCH_GBE_FRAME_SIZE_8192 8192
62
63#define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
64#define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
65#define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
66#define PCH_GBE_DESC_UNUSED(R) \
67 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
68 (R)->next_to_clean - (R)->next_to_use - 1)
69
70/* Pause packet value */
71#define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
72#define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
73#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
74#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
75
77555ee7
MO		 76
77/* This defines the bits that are set in the Interrupt Mask
78 * Set/Read Register. Each bit is documented below:
79 * o RXT0 = Receiver Timer Interrupt (ring 0)
80 * o TXDW = Transmit Descriptor Written Back
81 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
82 * o RXSEQ = Receive Sequence Error
83 * o LSC = Link Status Change
84 */
85#define PCH_GBE_INT_ENABLE_MASK ( \
86 PCH_GBE_INT_RX_DMA_CMPLT | \
87 PCH_GBE_INT_RX_DSC_EMP | \
124d770a 88 PCH_GBE_INT_RX_FIFO_ERR | \
77555ee7
MO		 89 PCH_GBE_INT_WOL_DET | \
90 PCH_GBE_INT_TX_CMPLT \
91 )
92
124d770a 93#define PCH_GBE_INT_DISABLE_ALL 0
77555ee7 94
1a0bdadb 95/* Macros for ieee1588 */
1a0bdadb
TS		 96/* 0x40 Time Synchronization Channel Control Register Bits */
97#define MASTER_MODE (1<<0)
93c8acb5 98#define SLAVE_MODE (0)
1a0bdadb 99#define V2_MODE (1<<31)
93c8acb5 100#define CAP_MODE0 (0)
1a0bdadb
TS		 101#define CAP_MODE2 (1<<17)
102
103/* 0x44 Time Synchronization Channel Event Register Bits */
104#define TX_SNAPSHOT_LOCKED (1<<0)
105#define RX_SNAPSHOT_LOCKED (1<<1)
358dfb6d
TS		 106
107#define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
108#define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
1a0bdadb 109
f1a26fdf
DH		 110#define MINNOW_PHY_RESET_GPIO 13
111
191cc687 112static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
113static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
114 int data);
d344c4f3 115static void pch_gbe_set_multi(struct net_device *netdev);
98200ec2 116
1a0bdadb
TS		 117static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
118{
119 u8 *data = skb->data;
120 unsigned int offset;
121 u16 *hi, *id;
122 u32 lo;
123
164d8c66 124 if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
1a0bdadb 125 return 0;
1a0bdadb
TS		 126
127 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
128
129 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
130 return 0;
131
132 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
133 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
134
135 memcpy(&lo, &hi[1], sizeof(lo));
136
137 return (uid_hi == *hi &&
138 uid_lo == lo &&
139 seqid == *id);
140}
141
93c8acb5
TS		 142static void
143pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
1a0bdadb
TS		 144{
145 struct skb_shared_hwtstamps *shhwtstamps;
146 struct pci_dev *pdev;
147 u64 ns;
148 u32 hi, lo, val;
149 u16 uid, seq;
150
151 if (!adapter->hwts_rx_en)
152 return;
153
154 /* Get ieee1588's dev information */
155 pdev = adapter->ptp_pdev;
156
157 val = pch_ch_event_read(pdev);
158
159 if (!(val & RX_SNAPSHOT_LOCKED))
160 return;
161
162 lo = pch_src_uuid_lo_read(pdev);
163 hi = pch_src_uuid_hi_read(pdev);
164
165 uid = hi & 0xffff;
166 seq = (hi >> 16) & 0xffff;
167
168 if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
169 goto out;
170
171 ns = pch_rx_snap_read(pdev);
1a0bdadb
TS		 172
173 shhwtstamps = skb_hwtstamps(skb);
174 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
175 shhwtstamps->hwtstamp = ns_to_ktime(ns);
176out:
177 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
178}
179
93c8acb5
TS		 180static void
181pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
1a0bdadb
TS		 182{
183 struct skb_shared_hwtstamps shhwtstamps;
184 struct pci_dev *pdev;
185 struct skb_shared_info *shtx;
186 u64 ns;
187 u32 cnt, val;
188
189 shtx = skb_shinfo(skb);
5481c8cd 190 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
1a0bdadb
TS		 191 return;
192
5481c8cd
TS		 193 shtx->tx_flags |= SKBTX_IN_PROGRESS;
194
1a0bdadb
TS		 195 /* Get ieee1588's dev information */
196 pdev = adapter->ptp_pdev;
197
198 /*
199 * This really stinks, but we have to poll for the Tx time stamp.
1a0bdadb
TS		 200 */
201 for (cnt = 0; cnt < 100; cnt++) {
202 val = pch_ch_event_read(pdev);
203 if (val & TX_SNAPSHOT_LOCKED)
204 break;
205 udelay(1);
206 }
207 if (!(val & TX_SNAPSHOT_LOCKED)) {
208 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
209 return;
210 }
211
212 ns = pch_tx_snap_read(pdev);
1a0bdadb
TS		 213
214 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
215 shhwtstamps.hwtstamp = ns_to_ktime(ns);
216 skb_tstamp_tx(skb, &shhwtstamps);
217
218 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
219}
220
221static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
222{
223 struct hwtstamp_config cfg;
224 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
225 struct pci_dev *pdev;
358dfb6d 226 u8 station[20];
1a0bdadb
TS		 227
228 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
229 return -EFAULT;
230
231 if (cfg.flags) /* reserved for future extensions */
232 return -EINVAL;
233
234 /* Get ieee1588's dev information */
235 pdev = adapter->ptp_pdev;
236
810abe9b 237 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1a0bdadb 238 return -ERANGE;
1a0bdadb
TS		 239
240 switch (cfg.rx_filter) {
241 case HWTSTAMP_FILTER_NONE:
242 adapter->hwts_rx_en = 0;
243 break;
244 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
245 adapter->hwts_rx_en = 0;
93c8acb5 246 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
1a0bdadb
TS		 247 break;
248 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
249 adapter->hwts_rx_en = 1;
93c8acb5 250 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
1a0bdadb 251 break;
358dfb6d
TS		 252 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
253 adapter->hwts_rx_en = 1;
254 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
255 strcpy(station, PTP_L4_MULTICAST_SA);
256 pch_set_station_address(station, pdev);
257 break;
258 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1a0bdadb 259 adapter->hwts_rx_en = 1;
93c8acb5 260 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
358dfb6d
TS		 261 strcpy(station, PTP_L2_MULTICAST_SA);
262 pch_set_station_address(station, pdev);
1a0bdadb
TS		 263 break;
264 default:
265 return -ERANGE;
266 }
267
810abe9b
BH		 268 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
269
1a0bdadb
TS		 270 /* Clear out any old time stamps. */
271 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
272
273 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
274}
1a0bdadb 275
bd796809 276static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
98200ec2
TO		 277{
278 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
279}
280
77555ee7
MO		 281/**
282 * pch_gbe_mac_read_mac_addr - Read MAC address
283 * @hw: Pointer to the HW structure
49ce9c2c 284 * Returns:
77555ee7
MO		 285 * 0: Successful.
286 */
9c020d7b 287static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
77555ee7 288{
453ca931 289 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
77555ee7
MO		 290 u32 adr1a, adr1b;
291
292 adr1a = ioread32(&hw->reg->mac_adr[0].high);
293 adr1b = ioread32(&hw->reg->mac_adr[0].low);
294
295 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
296 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
297 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
298 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
299 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
300 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
301
453ca931 302 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
77555ee7
MO		 303 return 0;
304}
305
306/**
307 * pch_gbe_wait_clr_bit - Wait to clear a bit
308 * @reg: Pointer of register
309 * @busy: Busy bit
310 */
191cc687 311static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
77555ee7
MO		 312{
313 u32 tmp;
453ca931 314
77555ee7
MO		 315 /* wait busy */
316 tmp = 1000;
317 while ((ioread32(reg) & bit) && --tmp)
318 cpu_relax();
319 if (!tmp)
320 pr_err("Error: busy bit is not cleared\n");
321}
124d770a 322
77555ee7
MO		 323/**
324 * pch_gbe_mac_mar_set - Set MAC address register
325 * @hw: Pointer to the HW structure
326 * @addr: Pointer to the MAC address
327 * @index: MAC address array register
328 */
191cc687 329static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
77555ee7 330{
453ca931 331 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
77555ee7
MO		 332 u32 mar_low, mar_high, adrmask;
333
453ca931 334 netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
77555ee7
MO		 335
336 /*
337 * HW expects these in little endian so we reverse the byte order
338 * from network order (big endian) to little endian
339 */
340 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
341 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
342 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
343 /* Stop the MAC Address of index. */
344 adrmask = ioread32(&hw->reg->ADDR_MASK);
345 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
346 /* wait busy */
347 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
348 /* Set the MAC address to the MAC address 1A/1B register */
349 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
350 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
351 /* Start the MAC address of index */
352 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
353 /* wait busy */
354 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
355}
356
357/**
358 * pch_gbe_mac_reset_hw - Reset hardware
359 * @hw: Pointer to the HW structure
360 */
191cc687 361static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
77555ee7
MO		 362{
363 /* Read the MAC address. and store to the private data */
364 pch_gbe_mac_read_mac_addr(hw);
365 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
77555ee7 366 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
77555ee7 367 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
eefc48b0 368 /* Setup the receive addresses */
77555ee7
MO		 369 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
370 return;
371}
372
e408a9ff 373static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
124d770a 374{
e408a9ff
VF		 375 u32 rctl;
376 /* Disables Receive MAC */
377 rctl = ioread32(&hw->reg->MAC_RX_EN);
378 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
379}
380
381static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
382{
383 u32 rctl;
384 /* Enables Receive MAC */
385 rctl = ioread32(&hw->reg->MAC_RX_EN);
386 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
124d770a
TO		 387}
388
77555ee7
MO		 389/**
390 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
391 * @hw: Pointer to the HW structure
392 * @mar_count: Receive address registers
393 */
191cc687 394static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
77555ee7
MO		 395{
396 u32 i;
397
398 /* Setup the receive address */
399 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
400
401 /* Zero out the other receive addresses */
402 for (i = 1; i < mar_count; i++) {
403 iowrite32(0, &hw->reg->mac_adr[i].high);
404 iowrite32(0, &hw->reg->mac_adr[i].low);
405 }
406 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
407 /* wait busy */
408 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
409}
410
77555ee7
MO		 411/**
412 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
413 * @hw: Pointer to the HW structure
49ce9c2c 414 * Returns:
77555ee7
MO		 415 * 0: Successful.
416 * Negative value: Failed.
417 */
418s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
419{
453ca931 420 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
77555ee7
MO		 421 struct pch_gbe_mac_info *mac = &hw->mac;
422 u32 rx_fctrl;
423
453ca931 424 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
77555ee7
MO		 425
426 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
427
428 switch (mac->fc) {
429 case PCH_GBE_FC_NONE:
430 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
431 mac->tx_fc_enable = false;
432 break;
433 case PCH_GBE_FC_RX_PAUSE:
434 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
435 mac->tx_fc_enable = false;
436 break;
437 case PCH_GBE_FC_TX_PAUSE:
438 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
439 mac->tx_fc_enable = true;
440 break;
441 case PCH_GBE_FC_FULL:
442 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
443 mac->tx_fc_enable = true;
444 break;
445 default:
453ca931
AS		 446 netdev_err(adapter->netdev,
447 "Flow control param set incorrectly\n");
77555ee7
MO		 448 return -EINVAL;
449 }
450 if (mac->link_duplex == DUPLEX_HALF)
451 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
452 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
453ca931
AS		 453 netdev_dbg(adapter->netdev,
454 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
455 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
77555ee7
MO		 456 return 0;
457}
458
459/**
460 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
461 * @hw: Pointer to the HW structure
462 * @wu_evt: Wake up event
463 */
191cc687 464static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
77555ee7 465{
453ca931 466 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
77555ee7
MO		 467 u32 addr_mask;
468
453ca931
AS		 469 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
470 wu_evt, ioread32(&hw->reg->ADDR_MASK));
77555ee7
MO		 471
472 if (wu_evt) {
473 /* Set Wake-On-Lan address mask */
474 addr_mask = ioread32(&hw->reg->ADDR_MASK);
475 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
476 /* wait busy */
477 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
478 iowrite32(0, &hw->reg->WOL_ST);
479 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
480 iowrite32(0x02, &hw->reg->TCPIP_ACC);
481 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
482 } else {
483 iowrite32(0, &hw->reg->WOL_CTRL);
484 iowrite32(0, &hw->reg->WOL_ST);
485 }
486 return;
487}
488
489/**
490 * pch_gbe_mac_ctrl_miim - Control MIIM interface
491 * @hw: Pointer to the HW structure
492 * @addr: Address of PHY
493 * @dir: Operetion. (Write or Read)
494 * @reg: Access register of PHY
495 * @data: Write data.
496 *
497 * Returns: Read date.
498 */
499u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
500 u16 data)
501{
453ca931 502 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
77555ee7
MO		 503 u32 data_out = 0;
504 unsigned int i;
505 unsigned long flags;
506
507 spin_lock_irqsave(&hw->miim_lock, flags);
508
509 for (i = 100; i; --i) {
510 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
511 break;
512 udelay(20);
513 }
514 if (i == 0) {
453ca931 515 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
77555ee7
MO		 516 spin_unlock_irqrestore(&hw->miim_lock, flags);
517 return 0; /* No way to indicate timeout error */
518 }
519 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
520 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
521 dir | data), &hw->reg->MIIM);
522 for (i = 0; i < 100; i++) {
523 udelay(20);
524 data_out = ioread32(&hw->reg->MIIM);
525 if ((data_out & PCH_GBE_MIIM_OPER_READY))
526 break;
527 }
528 spin_unlock_irqrestore(&hw->miim_lock, flags);
529
453ca931
AS		 530 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
531 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
532 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
77555ee7
MO		 533 return (u16) data_out;
534}
535
536/**
537 * pch_gbe_mac_set_pause_packet - Set pause packet
538 * @hw: Pointer to the HW structure
539 */
191cc687 540static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
77555ee7 541{
453ca931 542 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
77555ee7
MO		 543 unsigned long tmp2, tmp3;
544
545 /* Set Pause packet */
546 tmp2 = hw->mac.addr[1];
547 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
548 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
549
550 tmp3 = hw->mac.addr[5];
551 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
552 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
553 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
554
555 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
556 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
557 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
558 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
559 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
560
561 /* Transmit Pause Packet */
562 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
563
453ca931
AS		 564 netdev_dbg(adapter->netdev,
565 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
566 ioread32(&hw->reg->PAUSE_PKT1),
567 ioread32(&hw->reg->PAUSE_PKT2),
568 ioread32(&hw->reg->PAUSE_PKT3),
569 ioread32(&hw->reg->PAUSE_PKT4),
570 ioread32(&hw->reg->PAUSE_PKT5));
77555ee7
MO		 571
572 return;
573}
574
575
576/**
577 * pch_gbe_alloc_queues - Allocate memory for all rings
578 * @adapter: Board private structure to initialize
49ce9c2c 579 * Returns:
77555ee7
MO		 580 * 0: Successfully
581 * Negative value: Failed
582 */
583static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
584{
29cc436c
AS		 585 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
586 sizeof(*adapter->tx_ring), GFP_KERNEL);
77555ee7
MO		 587 if (!adapter->tx_ring)
588 return -ENOMEM;
3ab77bf2 589
29cc436c
AS		 590 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
591 sizeof(*adapter->rx_ring), GFP_KERNEL);
592 if (!adapter->rx_ring)
77555ee7 593 return -ENOMEM;
77555ee7
MO		 594 return 0;
595}
596
597/**
598 * pch_gbe_init_stats - Initialize status
599 * @adapter: Board private structure to initialize
600 */
601static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
602{
603 memset(&adapter->stats, 0, sizeof(adapter->stats));
604 return;
605}
606
607/**
608 * pch_gbe_init_phy - Initialize PHY
609 * @adapter: Board private structure to initialize
49ce9c2c 610 * Returns:
77555ee7
MO		 611 * 0: Successfully
612 * Negative value: Failed
613 */
614static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
615{
616 struct net_device *netdev = adapter->netdev;
617 u32 addr;
618 u16 bmcr, stat;
619
620 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
621 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
622 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
623 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
624 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
625 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
626 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
627 break;
628 }
629 adapter->hw.phy.addr = adapter->mii.phy_id;
453ca931 630 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
b04d68eb 631 if (addr == PCH_GBE_PHY_REGS_LEN)
77555ee7
MO		 632 return -EAGAIN;
633 /* Selected the phy and isolate the rest */
634 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
635 if (addr != adapter->mii.phy_id) {
636 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
637 BMCR_ISOLATE);
638 } else {
639 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
640 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
641 bmcr & ~BMCR_ISOLATE);
642 }
643 }
644
645 /* MII setup */
646 adapter->mii.phy_id_mask = 0x1F;
647 adapter->mii.reg_num_mask = 0x1F;
648 adapter->mii.dev = adapter->netdev;
649 adapter->mii.mdio_read = pch_gbe_mdio_read;
650 adapter->mii.mdio_write = pch_gbe_mdio_write;
651 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
652 return 0;
653}
654
655/**
656 * pch_gbe_mdio_read - The read function for mii
657 * @netdev: Network interface device structure
658 * @addr: Phy ID
659 * @reg: Access location
49ce9c2c 660 * Returns:
77555ee7
MO		 661 * 0: Successfully
662 * Negative value: Failed
663 */
191cc687 664static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
77555ee7
MO		 665{
666 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
667 struct pch_gbe_hw *hw = &adapter->hw;
668
669 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
670 (u16) 0);
671}
672
673/**
674 * pch_gbe_mdio_write - The write function for mii
675 * @netdev: Network interface device structure
676 * @addr: Phy ID (not used)
677 * @reg: Access location
678 * @data: Write data
679 */
191cc687 680static void pch_gbe_mdio_write(struct net_device *netdev,
681 int addr, int reg, int data)
77555ee7
MO		 682{
683 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
684 struct pch_gbe_hw *hw = &adapter->hw;
685
686 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
687}
688
689/**
690 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
691 * @work: Pointer of board private structure
692 */
693static void pch_gbe_reset_task(struct work_struct *work)
694{
695 struct pch_gbe_adapter *adapter;
696 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
697
75d1a752 698 rtnl_lock();
77555ee7 699 pch_gbe_reinit_locked(adapter);
75d1a752 700 rtnl_unlock();
77555ee7
MO		 701}
702
703/**
704 * pch_gbe_reinit_locked- Re-initialization
705 * @adapter: Board private structure
706 */
707void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
708{
75d1a752
TO		 709 pch_gbe_down(adapter);
710 pch_gbe_up(adapter);
77555ee7
MO		 711}
712
713/**
714 * pch_gbe_reset - Reset GbE
715 * @adapter: Board private structure
716 */
717void pch_gbe_reset(struct pch_gbe_adapter *adapter)
718{
453ca931 719 struct net_device *netdev = adapter->netdev;
3ef594b0
PB		 720 struct pch_gbe_hw *hw = &adapter->hw;
721 s32 ret_val;
453ca931 722
3ef594b0 723 pch_gbe_mac_reset_hw(hw);
d344c4f3 724 /* reprogram multicast address register after reset */
453ca931 725 pch_gbe_set_multi(netdev);
77555ee7 726 /* Setup the receive address. */
3ef594b0
PB		 727 pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
728
729 ret_val = pch_gbe_phy_get_id(hw);
730 if (ret_val) {
731 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
732 return;
733 }
734 pch_gbe_phy_init_setting(hw);
735 /* Setup Mac interface option RGMII */
3ef594b0 736 pch_gbe_phy_set_rgmii(hw);
77555ee7
MO		 737}
738
739/**
740 * pch_gbe_free_irq - Free an interrupt
741 * @adapter: Board private structure
742 */
743static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
744{
745 struct net_device *netdev = adapter->netdev;
746
2a600d97
AS		 747 free_irq(adapter->irq, netdev);
748 pci_free_irq_vectors(adapter->pdev);
77555ee7
MO		 749}
750
751/**
752 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
753 * @adapter: Board private structure
754 */
755static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
756{
757 struct pch_gbe_hw *hw = &adapter->hw;
758
759 atomic_inc(&adapter->irq_sem);
760 iowrite32(0, &hw->reg->INT_EN);
761 ioread32(&hw->reg->INT_ST);
2a600d97 762 synchronize_irq(adapter->irq);
77555ee7 763
453ca931
AS		 764 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
765 ioread32(&hw->reg->INT_EN));
77555ee7
MO		 766}
767
768/**
769 * pch_gbe_irq_enable - Enable default interrupt generation settings
770 * @adapter: Board private structure
771 */
772static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
773{
774 struct pch_gbe_hw *hw = &adapter->hw;
775
776 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
777 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
778 ioread32(&hw->reg->INT_ST);
453ca931
AS		 779 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
780 ioread32(&hw->reg->INT_EN));
77555ee7
MO		 781}
782
783
784
785/**
786 * pch_gbe_setup_tctl - configure the Transmit control registers
787 * @adapter: Board private structure
788 */
789static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
790{
791 struct pch_gbe_hw *hw = &adapter->hw;
792 u32 tx_mode, tcpip;
793
794 tx_mode = PCH_GBE_TM_LONG_PKT |
795 PCH_GBE_TM_ST_AND_FD |
796 PCH_GBE_TM_SHORT_PKT |
797 PCH_GBE_TM_TH_TX_STRT_8 |
798 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
799
800 iowrite32(tx_mode, &hw->reg->TX_MODE);
801
802 tcpip = ioread32(&hw->reg->TCPIP_ACC);
803 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
804 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
805 return;
806}
807
808/**
809 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
810 * @adapter: Board private structure
811 */
812static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
813{
814 struct pch_gbe_hw *hw = &adapter->hw;
815 u32 tdba, tdlen, dctrl;
816
453ca931
AS		 817 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n",
818 (unsigned long long)adapter->tx_ring->dma,
819 adapter->tx_ring->size);
77555ee7
MO		 820
821 /* Setup the HW Tx Head and Tail descriptor pointers */
822 tdba = adapter->tx_ring->dma;
823 tdlen = adapter->tx_ring->size - 0x10;
824 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
825 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
826 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
827
828 /* Enables Transmission DMA */
829 dctrl = ioread32(&hw->reg->DMA_CTRL);
830 dctrl |= PCH_GBE_TX_DMA_EN;
831 iowrite32(dctrl, &hw->reg->DMA_CTRL);
832}
833
834/**
835 * pch_gbe_setup_rctl - Configure the receive control registers
836 * @adapter: Board private structure
837 */
838static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
839{
840 struct pch_gbe_hw *hw = &adapter->hw;
841 u32 rx_mode, tcpip;
842
843 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
844 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
845
846 iowrite32(rx_mode, &hw->reg->RX_MODE);
847
848 tcpip = ioread32(&hw->reg->TCPIP_ACC);
849
124d770a
TO		 850 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
851 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
77555ee7
MO		 852 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
853 return;
854}
855
856/**
857 * pch_gbe_configure_rx - Configure Receive Unit after Reset
858 * @adapter: Board private structure
859 */
860static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
861{
862 struct pch_gbe_hw *hw = &adapter->hw;
e408a9ff 863 u32 rdba, rdlen, rxdma;
77555ee7 864
453ca931
AS		 865 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n",
866 (unsigned long long)adapter->rx_ring->dma,
867 adapter->rx_ring->size);
77555ee7
MO		 868
869 pch_gbe_mac_force_mac_fc(hw);
870
e408a9ff 871 pch_gbe_disable_mac_rx(hw);
77555ee7
MO		 872
873 /* Disables Receive DMA */
874 rxdma = ioread32(&hw->reg->DMA_CTRL);
875 rxdma &= ~PCH_GBE_RX_DMA_EN;
876 iowrite32(rxdma, &hw->reg->DMA_CTRL);
877
453ca931
AS		 878 netdev_dbg(adapter->netdev,
879 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
880 ioread32(&hw->reg->MAC_RX_EN),
881 ioread32(&hw->reg->DMA_CTRL));
77555ee7
MO		 882
883 /* Setup the HW Rx Head and Tail Descriptor Pointers and
884 * the Base and Length of the Rx Descriptor Ring */
885 rdba = adapter->rx_ring->dma;
886 rdlen = adapter->rx_ring->size - 0x10;
887 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
888 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
889 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
77555ee7
MO		 890}
891
892/**
893 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
894 * @adapter: Board private structure
895 * @buffer_info: Buffer information structure
896 */
897static void pch_gbe_unmap_and_free_tx_resource(
898 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
899{
900 if (buffer_info->mapped) {
901 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
902 buffer_info->length, DMA_TO_DEVICE);
903 buffer_info->mapped = false;
904 }
905 if (buffer_info->skb) {
906 dev_kfree_skb_any(buffer_info->skb);
907 buffer_info->skb = NULL;
908 }
909}
910
911/**
912 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
913 * @adapter: Board private structure
914 * @buffer_info: Buffer information structure
915 */
916static void pch_gbe_unmap_and_free_rx_resource(
917 struct pch_gbe_adapter *adapter,
918 struct pch_gbe_buffer *buffer_info)
919{
920 if (buffer_info->mapped) {
921 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
922 buffer_info->length, DMA_FROM_DEVICE);
923 buffer_info->mapped = false;
924 }
925 if (buffer_info->skb) {
926 dev_kfree_skb_any(buffer_info->skb);
927 buffer_info->skb = NULL;
928 }
929}
930
931/**
932 * pch_gbe_clean_tx_ring - Free Tx Buffers
933 * @adapter: Board private structure
934 * @tx_ring: Ring to be cleaned
935 */
936static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
937 struct pch_gbe_tx_ring *tx_ring)
938{
939 struct pch_gbe_hw *hw = &adapter->hw;
940 struct pch_gbe_buffer *buffer_info;
941 unsigned long size;
942 unsigned int i;
943
944 /* Free all the Tx ring sk_buffs */
945 for (i = 0; i < tx_ring->count; i++) {
946 buffer_info = &tx_ring->buffer_info[i];
947 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
948 }
453ca931
AS		 949 netdev_dbg(adapter->netdev,
950 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
77555ee7
MO		 951
952 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
953 memset(tx_ring->buffer_info, 0, size);
954
955 /* Zero out the descriptor ring */
956 memset(tx_ring->desc, 0, tx_ring->size);
957 tx_ring->next_to_use = 0;
958 tx_ring->next_to_clean = 0;
959 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
960 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
961}
962
963/**
964 * pch_gbe_clean_rx_ring - Free Rx Buffers
965 * @adapter: Board private structure
966 * @rx_ring: Ring to free buffers from
967 */
968static void
969pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
970 struct pch_gbe_rx_ring *rx_ring)
971{
972 struct pch_gbe_hw *hw = &adapter->hw;
973 struct pch_gbe_buffer *buffer_info;
974 unsigned long size;
975 unsigned int i;
976
977 /* Free all the Rx ring sk_buffs */
978 for (i = 0; i < rx_ring->count; i++) {
979 buffer_info = &rx_ring->buffer_info[i];
980 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
981 }
453ca931
AS		 982 netdev_dbg(adapter->netdev,
983 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
77555ee7
MO		 984 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
985 memset(rx_ring->buffer_info, 0, size);
986
987 /* Zero out the descriptor ring */
988 memset(rx_ring->desc, 0, rx_ring->size);
989 rx_ring->next_to_clean = 0;
990 rx_ring->next_to_use = 0;
991 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
992 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
993}
994
995static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
996 u16 duplex)
997{
998 struct pch_gbe_hw *hw = &adapter->hw;
999 unsigned long rgmii = 0;
1000
1001 /* Set the RGMII control. */
77555ee7
MO		 1002 switch (speed) {
1003 case SPEED_10:
1004 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1005 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1006 break;
1007 case SPEED_100:
1008 rgmii = (PCH_GBE_RGMII_RATE_25M |
1009 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1010 break;
1011 case SPEED_1000:
1012 rgmii = (PCH_GBE_RGMII_RATE_125M |
1013 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1014 break;
1015 }
1016 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
77555ee7
MO		 1017}
1018static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1019 u16 duplex)
1020{
1021 struct net_device *netdev = adapter->netdev;
1022 struct pch_gbe_hw *hw = &adapter->hw;
1023 unsigned long mode = 0;
1024
1025 /* Set the communication mode */
1026 switch (speed) {
1027 case SPEED_10:
1028 mode = PCH_GBE_MODE_MII_ETHER;
1029 netdev->tx_queue_len = 10;
1030 break;
1031 case SPEED_100:
1032 mode = PCH_GBE_MODE_MII_ETHER;
1033 netdev->tx_queue_len = 100;
1034 break;
1035 case SPEED_1000:
1036 mode = PCH_GBE_MODE_GMII_ETHER;
1037 break;
1038 }
1039 if (duplex == DUPLEX_FULL)
1040 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1041 else
1042 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1043 iowrite32(mode, &hw->reg->MODE);
1044}
1045
1046/**
1047 * pch_gbe_watchdog - Watchdog process
1048 * @data: Board private structure
1049 */
e99e88a9 1050static void pch_gbe_watchdog(struct timer_list *t)
77555ee7 1051{
e99e88a9
KC		 1052 struct pch_gbe_adapter *adapter = from_timer(adapter, t,
1053 watchdog_timer);
77555ee7
MO		 1054 struct net_device *netdev = adapter->netdev;
1055 struct pch_gbe_hw *hw = &adapter->hw;
77555ee7 1056
453ca931 1057 netdev_dbg(netdev, "right now = %ld\n", jiffies);
77555ee7
MO		 1058
1059 pch_gbe_update_stats(adapter);
1060 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
8ae6daca 1061 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
77555ee7
MO		 1062 netdev->tx_queue_len = adapter->tx_queue_len;
1063 /* mii library handles link maintenance tasks */
1064 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
453ca931 1065 netdev_err(netdev, "ethtool get setting Error\n");
77555ee7
MO		 1066 mod_timer(&adapter->watchdog_timer,
1067 round_jiffies(jiffies +
1068 PCH_GBE_WATCHDOG_PERIOD));
1069 return;
1070 }
8ae6daca 1071 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
77555ee7
MO		 1072 hw->mac.link_duplex = cmd.duplex;
1073 /* Set the RGMII control. */
1074 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1075 hw->mac.link_duplex);
1076 /* Set the communication mode */
1077 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1078 hw->mac.link_duplex);
1079 netdev_dbg(netdev,
1080 "Link is Up %d Mbps %s-Duplex\n",
8ae6daca 1081 hw->mac.link_speed,
77555ee7
MO		 1082 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1083 netif_carrier_on(netdev);
1084 netif_wake_queue(netdev);
1085 } else if ((!mii_link_ok(&adapter->mii)) &&
1086 (netif_carrier_ok(netdev))) {
1087 netdev_dbg(netdev, "NIC Link is Down\n");
1088 hw->mac.link_speed = SPEED_10;
1089 hw->mac.link_duplex = DUPLEX_HALF;
1090 netif_carrier_off(netdev);
1091 netif_stop_queue(netdev);
1092 }
1093 mod_timer(&adapter->watchdog_timer,
1094 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1095}
1096
1097/**
1098 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1099 * @adapter: Board private structure
1100 * @tx_ring: Tx descriptor ring structure
1101 * @skb: Sockt buffer structure
1102 */
1103static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1104 struct pch_gbe_tx_ring *tx_ring,
1105 struct sk_buff *skb)
1106{
1107 struct pch_gbe_hw *hw = &adapter->hw;
1108 struct pch_gbe_tx_desc *tx_desc;
1109 struct pch_gbe_buffer *buffer_info;
1110 struct sk_buff *tmp_skb;
1111 unsigned int frame_ctrl;
1112 unsigned int ring_num;
77555ee7
MO		 1113
1114 /*-- Set frame control --*/
1115 frame_ctrl = 0;
1116 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1117 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
756a6b03 1118 if (skb->ip_summed == CHECKSUM_NONE)
77555ee7
MO		 1119 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1120
1121 /* Performs checksum processing */
1122 /*
1123 * It is because the hardware accelerator does not support a checksum,
1124 * when the received data size is less than 64 bytes.
1125 */
756a6b03 1126 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
77555ee7
MO		 1127 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1128 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1129 if (skb->protocol == htons(ETH_P_IP)) {
1130 struct iphdr *iph = ip_hdr(skb);
1131 unsigned int offset;
77555ee7
MO		 1132 offset = skb_transport_offset(skb);
1133 if (iph->protocol == IPPROTO_TCP) {
1134 skb->csum = 0;
1135 tcp_hdr(skb)->check = 0;
1136 skb->csum = skb_checksum(skb, offset,
1137 skb->len - offset, 0);
1138 tcp_hdr(skb)->check =
1139 csum_tcpudp_magic(iph->saddr,
1140 iph->daddr,
1141 skb->len - offset,
1142 IPPROTO_TCP,
1143 skb->csum);
1144 } else if (iph->protocol == IPPROTO_UDP) {
1145 skb->csum = 0;
1146 udp_hdr(skb)->check = 0;
1147 skb->csum =
1148 skb_checksum(skb, offset,
1149 skb->len - offset, 0);
1150 udp_hdr(skb)->check =
1151 csum_tcpudp_magic(iph->saddr,
1152 iph->daddr,
1153 skb->len - offset,
1154 IPPROTO_UDP,
1155 skb->csum);
1156 }
1157 }
1158 }
3ab77bf2 1159
77555ee7
MO		 1160 ring_num = tx_ring->next_to_use;
1161 if (unlikely((ring_num + 1) == tx_ring->count))
1162 tx_ring->next_to_use = 0;
1163 else
1164 tx_ring->next_to_use = ring_num + 1;
1165
3ab77bf2 1166
77555ee7
MO		 1167 buffer_info = &tx_ring->buffer_info[ring_num];
1168 tmp_skb = buffer_info->skb;
1169
1170 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1171 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1172 tmp_skb->data[ETH_HLEN] = 0x00;
1173 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1174 tmp_skb->len = skb->len;
1175 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1176 (skb->len - ETH_HLEN));
25985edc 1177 /*-- Set Buffer information --*/
77555ee7
MO		 1178 buffer_info->length = tmp_skb->len;
1179 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1180 buffer_info->length,
1181 DMA_TO_DEVICE);
1182 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
453ca931 1183 netdev_err(adapter->netdev, "TX DMA map failed\n");
77555ee7
MO		 1184 buffer_info->dma = 0;
1185 buffer_info->time_stamp = 0;
1186 tx_ring->next_to_use = ring_num;
1187 return;
1188 }
1189 buffer_info->mapped = true;
1190 buffer_info->time_stamp = jiffies;
1191
1192 /*-- Set Tx descriptor --*/
1193 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1194 tx_desc->buffer_addr = (buffer_info->dma);
1195 tx_desc->length = (tmp_skb->len);
1196 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1197 tx_desc->tx_frame_ctrl = (frame_ctrl);
1198 tx_desc->gbec_status = (DSC_INIT16);
1199
1200 if (unlikely(++ring_num == tx_ring->count))
1201 ring_num = 0;
1202
1203 /* Update software pointer of TX descriptor */
1204 iowrite32(tx_ring->dma +
1205 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1206 &hw->reg->TX_DSC_SW_P);
1a0bdadb 1207
1a0bdadb 1208 pch_tx_timestamp(adapter, skb);
1a0bdadb 1209
77555ee7
MO		 1210 dev_kfree_skb_any(skb);
1211}
1212
1213/**
1214 * pch_gbe_update_stats - Update the board statistics counters
1215 * @adapter: Board private structure
1216 */
1217void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1218{
1219 struct net_device *netdev = adapter->netdev;
1220 struct pci_dev *pdev = adapter->pdev;
1221 struct pch_gbe_hw_stats *stats = &adapter->stats;
1222 unsigned long flags;
1223
1224 /*
1225 * Prevent stats update while adapter is being reset, or if the pci
1226 * connection is down.
1227 */
1228 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1229 return;
1230
1231 spin_lock_irqsave(&adapter->stats_lock, flags);
1232
1233 /* Update device status "adapter->stats" */
1234 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1235 stats->tx_errors = stats->tx_length_errors +
1236 stats->tx_aborted_errors +
1237 stats->tx_carrier_errors + stats->tx_timeout_count;
1238
1239 /* Update network device status "adapter->net_stats" */
1240 netdev->stats.rx_packets = stats->rx_packets;
1241 netdev->stats.rx_bytes = stats->rx_bytes;
1242 netdev->stats.rx_dropped = stats->rx_dropped;
1243 netdev->stats.tx_packets = stats->tx_packets;
1244 netdev->stats.tx_bytes = stats->tx_bytes;
1245 netdev->stats.tx_dropped = stats->tx_dropped;
1246 /* Fill out the OS statistics structure */
1247 netdev->stats.multicast = stats->multicast;
1248 netdev->stats.collisions = stats->collisions;
1249 /* Rx Errors */
1250 netdev->stats.rx_errors = stats->rx_errors;
1251 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1252 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1253 /* Tx Errors */
1254 netdev->stats.tx_errors = stats->tx_errors;
1255 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1256 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1257
1258 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1259}
1260
a35279f0 1261static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
124d770a 1262{
124d770a 1263 u32 rxdma;
124d770a
TO		 1264
1265 /* Disable Receive DMA */
1266 rxdma = ioread32(&hw->reg->DMA_CTRL);
1267 rxdma &= ~PCH_GBE_RX_DMA_EN;
1268 iowrite32(rxdma, &hw->reg->DMA_CTRL);
124d770a
TO		 1269}
1270
a35279f0 1271static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
5229d87e
TO		 1272{
1273 u32 rxdma;
1274
1275 /* Enables Receive DMA */
1276 rxdma = ioread32(&hw->reg->DMA_CTRL);
1277 rxdma |= PCH_GBE_RX_DMA_EN;
1278 iowrite32(rxdma, &hw->reg->DMA_CTRL);
5229d87e
TO		 1279}
1280
77555ee7
MO		 1281/**
1282 * pch_gbe_intr - Interrupt Handler
1283 * @irq: Interrupt number
1284 * @data: Pointer to a network interface device structure
49ce9c2c 1285 * Returns:
77555ee7
MO		 1286 * - IRQ_HANDLED: Our interrupt
1287 * - IRQ_NONE: Not our interrupt
1288 */
1289static irqreturn_t pch_gbe_intr(int irq, void *data)
1290{
1291 struct net_device *netdev = data;
1292 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1293 struct pch_gbe_hw *hw = &adapter->hw;
1294 u32 int_st;
1295 u32 int_en;
1296
1297 /* Check request status */
1298 int_st = ioread32(&hw->reg->INT_ST);
1299 int_st = int_st & ioread32(&hw->reg->INT_EN);
1300 /* When request status is no interruption factor */
1301 if (unlikely(!int_st))
1302 return IRQ_NONE; /* Not our interrupt. End processing. */
453ca931 1303 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
77555ee7
MO		 1304 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1305 adapter->stats.intr_rx_frame_err_count++;
1306 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
124d770a
TO		 1307 if (!adapter->rx_stop_flag) {
1308 adapter->stats.intr_rx_fifo_err_count++;
453ca931 1309 netdev_dbg(netdev, "Rx fifo over run\n");
124d770a
TO		 1310 adapter->rx_stop_flag = true;
1311 int_en = ioread32(&hw->reg->INT_EN);
1312 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1313 &hw->reg->INT_EN);
a35279f0 1314 pch_gbe_disable_dma_rx(&adapter->hw);
805e969f
TO		 1315 int_st |= ioread32(&hw->reg->INT_ST);
1316 int_st = int_st & ioread32(&hw->reg->INT_EN);
124d770a 1317 }
77555ee7
MO		 1318 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1319 adapter->stats.intr_rx_dma_err_count++;
1320 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1321 adapter->stats.intr_tx_fifo_err_count++;
1322 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1323 adapter->stats.intr_tx_dma_err_count++;
1324 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1325 adapter->stats.intr_tcpip_err_count++;
1326 /* When Rx descriptor is empty */
1327 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1328 adapter->stats.intr_rx_dsc_empty_count++;
453ca931 1329 netdev_dbg(netdev, "Rx descriptor is empty\n");
77555ee7
MO		 1330 int_en = ioread32(&hw->reg->INT_EN);
1331 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1332 if (hw->mac.tx_fc_enable) {
1333 /* Set Pause packet */
1334 pch_gbe_mac_set_pause_packet(hw);
1335 }
77555ee7
MO		 1336 }
1337
1338 /* When request status is Receive interruption */
805e969f 1339 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
23677ce3 1340 (adapter->rx_stop_flag)) {
77555ee7
MO		 1341 if (likely(napi_schedule_prep(&adapter->napi))) {
1342 /* Enable only Rx Descriptor empty */
1343 atomic_inc(&adapter->irq_sem);
1344 int_en = ioread32(&hw->reg->INT_EN);
1345 int_en &=
1346 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1347 iowrite32(int_en, &hw->reg->INT_EN);
1348 /* Start polling for NAPI */
1349 __napi_schedule(&adapter->napi);
1350 }
1351 }
453ca931
AS		 1352 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n",
1353 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
77555ee7
MO		 1354 return IRQ_HANDLED;
1355}
1356
1357/**
1358 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1359 * @adapter: Board private structure
1360 * @rx_ring: Rx descriptor ring
1361 * @cleaned_count: Cleaned count
1362 */
1363static void
1364pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1365 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1366{
1367 struct net_device *netdev = adapter->netdev;
1368 struct pci_dev *pdev = adapter->pdev;
1369 struct pch_gbe_hw *hw = &adapter->hw;
1370 struct pch_gbe_rx_desc *rx_desc;
1371 struct pch_gbe_buffer *buffer_info;
1372 struct sk_buff *skb;
1373 unsigned int i;
1374 unsigned int bufsz;
1375
124d770a 1376 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
77555ee7
MO		 1377 i = rx_ring->next_to_use;
1378
1379 while ((cleaned_count--)) {
1380 buffer_info = &rx_ring->buffer_info[i];
124d770a
TO		 1381 skb = netdev_alloc_skb(netdev, bufsz);
1382 if (unlikely(!skb)) {
1383 /* Better luck next round */
1384 adapter->stats.rx_alloc_buff_failed++;
1385 break;
77555ee7 1386 }
124d770a
TO		 1387 /* align */
1388 skb_reserve(skb, NET_IP_ALIGN);
1389 buffer_info->skb = skb;
1390
77555ee7 1391 buffer_info->dma = dma_map_single(&pdev->dev,
124d770a 1392 buffer_info->rx_buffer,
77555ee7
MO		 1393 buffer_info->length,
1394 DMA_FROM_DEVICE);
1395 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1396 dev_kfree_skb(skb);
1397 buffer_info->skb = NULL;
1398 buffer_info->dma = 0;
1399 adapter->stats.rx_alloc_buff_failed++;
1400 break; /* while !buffer_info->skb */
1401 }
1402 buffer_info->mapped = true;
1403 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1404 rx_desc->buffer_addr = (buffer_info->dma);
1405 rx_desc->gbec_status = DSC_INIT16;
1406
453ca931
AS		 1407 netdev_dbg(netdev,
1408 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1409 i, (unsigned long long)buffer_info->dma,
1410 buffer_info->length);
77555ee7
MO		 1411
1412 if (unlikely(++i == rx_ring->count))
1413 i = 0;
1414 }
1415 if (likely(rx_ring->next_to_use != i)) {
1416 rx_ring->next_to_use = i;
1417 if (unlikely(i-- == 0))
1418 i = (rx_ring->count - 1);
1419 iowrite32(rx_ring->dma +
1420 (int)sizeof(struct pch_gbe_rx_desc) * i,
1421 &hw->reg->RX_DSC_SW_P);
1422 }
1423 return;
1424}
1425
124d770a
TO		 1426static int
1427pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1428 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1429{
1430 struct pci_dev *pdev = adapter->pdev;
1431 struct pch_gbe_buffer *buffer_info;
1432 unsigned int i;
1433 unsigned int bufsz;
1434 unsigned int size;
1435
1436 bufsz = adapter->rx_buffer_len;
1437
1438 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
ede23fa8 1439 rx_ring->rx_buff_pool =
750afb08
LC		 1440 dma_alloc_coherent(&pdev->dev, size,
1441 &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
d0320f75 1442 if (!rx_ring->rx_buff_pool)
124d770a 1443 return -ENOMEM;
d0320f75 1444
124d770a
TO		 1445 rx_ring->rx_buff_pool_size = size;
1446 for (i = 0; i < rx_ring->count; i++) {
1447 buffer_info = &rx_ring->buffer_info[i];
1448 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1449 buffer_info->length = bufsz;
1450 }
1451 return 0;
1452}
1453
77555ee7
MO		 1454/**
1455 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1456 * @adapter: Board private structure
1457 * @tx_ring: Tx descriptor ring
1458 */
1459static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1460 struct pch_gbe_tx_ring *tx_ring)
1461{
1462 struct pch_gbe_buffer *buffer_info;
1463 struct sk_buff *skb;
1464 unsigned int i;
1465 unsigned int bufsz;
1466 struct pch_gbe_tx_desc *tx_desc;
1467
1468 bufsz =
1469 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1470
1471 for (i = 0; i < tx_ring->count; i++) {
1472 buffer_info = &tx_ring->buffer_info[i];
1473 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1474 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1475 buffer_info->skb = skb;
1476 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1477 tx_desc->gbec_status = (DSC_INIT16);
1478 }
1479 return;
1480}
1481
1482/**
1483 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1484 * @adapter: Board private structure
1485 * @tx_ring: Tx descriptor ring
49ce9c2c 1486 * Returns:
77555ee7
MO		 1487 * true: Cleaned the descriptor
1488 * false: Not cleaned the descriptor
1489 */
1490static bool
1491pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1492 struct pch_gbe_tx_ring *tx_ring)
1493{
1494 struct pch_gbe_tx_desc *tx_desc;
1495 struct pch_gbe_buffer *buffer_info;
1496 struct sk_buff *skb;
1497 unsigned int i;
1498 unsigned int cleaned_count = 0;
f2c31662
AC		 1499 bool cleaned = false;
1500 int unused, thresh;
77555ee7 1501
453ca931
AS		 1502 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1503 tx_ring->next_to_clean);
77555ee7
MO		 1504
1505 i = tx_ring->next_to_clean;
1506 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
453ca931
AS		 1507 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n",
1508 tx_desc->gbec_status, tx_desc->dma_status);
77555ee7 1509
f2c31662
AC		 1510 unused = PCH_GBE_DESC_UNUSED(tx_ring);
1511 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1512 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1513 { /* current marked clean, tx queue filling up, do extra clean */
1514 int j, k;
1515 if (unused < 8) { /* tx queue nearly full */
453ca931
AS		 1516 netdev_dbg(adapter->netdev,
1517 "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1518 tx_ring->next_to_clean, tx_ring->next_to_use,
1519 unused);
f2c31662
AC		 1520 }
1521
1522 /* current marked clean, scan for more that need cleaning. */
1523 k = i;
1524 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1525 {
1526 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1527 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1528 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
1529 }
1530 if (j < PCH_GBE_TX_WEIGHT) {
453ca931
AS		 1531 netdev_dbg(adapter->netdev,
1532 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1533 unused, j, i, k, tx_ring->next_to_use,
1534 tx_desc->gbec_status);
f2c31662
AC		 1535 i = k; /*found one to clean, usu gbec_status==2000.*/
1536 }
1537 }
1538
77555ee7 1539 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
453ca931
AS		 1540 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1541 tx_desc->gbec_status);
77555ee7
MO		 1542 buffer_info = &tx_ring->buffer_info[i];
1543 skb = buffer_info->skb;
f2c31662 1544 cleaned = true;
77555ee7
MO		 1545
1546 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1547 adapter->stats.tx_aborted_errors++;
453ca931 1548 netdev_err(adapter->netdev, "Transfer Abort Error\n");
77555ee7
MO		 1549 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1550 ) {
1551 adapter->stats.tx_carrier_errors++;
453ca931
AS		 1552 netdev_err(adapter->netdev,
1553 "Transfer Carrier Sense Error\n");
77555ee7
MO		 1554 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1555 ) {
1556 adapter->stats.tx_aborted_errors++;
453ca931
AS		 1557 netdev_err(adapter->netdev,
1558 "Transfer Collision Abort Error\n");
77555ee7
MO		 1559 } else if ((tx_desc->gbec_status &
1560 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1561 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1562 adapter->stats.collisions++;
1563 adapter->stats.tx_packets++;
1564 adapter->stats.tx_bytes += skb->len;
453ca931 1565 netdev_dbg(adapter->netdev, "Transfer Collision\n");
77555ee7
MO		 1566 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1567 ) {
1568 adapter->stats.tx_packets++;
1569 adapter->stats.tx_bytes += skb->len;
1570 }
1571 if (buffer_info->mapped) {
453ca931
AS		 1572 netdev_dbg(adapter->netdev,
1573 "unmap buffer_info->dma : %d\n", i);
77555ee7
MO		 1574 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1575 buffer_info->length, DMA_TO_DEVICE);
1576 buffer_info->mapped = false;
1577 }
1578 if (buffer_info->skb) {
453ca931
AS		 1579 netdev_dbg(adapter->netdev,
1580 "trim buffer_info->skb : %d\n", i);
77555ee7
MO		 1581 skb_trim(buffer_info->skb, 0);
1582 }
1583 tx_desc->gbec_status = DSC_INIT16;
1584 if (unlikely(++i == tx_ring->count))
1585 i = 0;
1586 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1587
1588 /* weight of a sort for tx, to avoid endless transmit cleanup */
805e969f
TO		 1589 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1590 cleaned = false;
77555ee7 1591 break;
805e969f 1592 }
77555ee7 1593 }
453ca931
AS		 1594 netdev_dbg(adapter->netdev,
1595 "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1596 cleaned_count);
f2c31662
AC		 1597 if (cleaned_count > 0) { /*skip this if nothing cleaned*/
1598 /* Recover from running out of Tx resources in xmit_frame */
222e4d0b 1599 netif_tx_lock(adapter->netdev);
f2c31662
AC		 1600 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1601 {
1602 netif_wake_queue(adapter->netdev);
1603 adapter->stats.tx_restart_count++;
453ca931 1604 netdev_dbg(adapter->netdev, "Tx wake queue\n");
f2c31662 1605 }
3ab77bf2 1606
f2c31662 1607 tx_ring->next_to_clean = i;
3ab77bf2 1608
453ca931
AS		 1609 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1610 tx_ring->next_to_clean);
222e4d0b 1611 netif_tx_unlock(adapter->netdev);
f2c31662 1612 }
77555ee7
MO		 1613 return cleaned;
1614}
1615
1616/**
1617 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1618 * @adapter: Board private structure
1619 * @rx_ring: Rx descriptor ring
1620 * @work_done: Completed count
1621 * @work_to_do: Request count
49ce9c2c 1622 * Returns:
77555ee7
MO		 1623 * true: Cleaned the descriptor
1624 * false: Not cleaned the descriptor
1625 */
1626static bool
1627pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1628 struct pch_gbe_rx_ring *rx_ring,
1629 int *work_done, int work_to_do)
1630{
1631 struct net_device *netdev = adapter->netdev;
1632 struct pci_dev *pdev = adapter->pdev;
1633 struct pch_gbe_buffer *buffer_info;
1634 struct pch_gbe_rx_desc *rx_desc;
1635 u32 length;
77555ee7
MO		 1636 unsigned int i;
1637 unsigned int cleaned_count = 0;
1638 bool cleaned = false;
124d770a 1639 struct sk_buff *skb;
77555ee7
MO		 1640 u8 dma_status;
1641 u16 gbec_status;
1642 u32 tcp_ip_status;
77555ee7
MO		 1643
1644 i = rx_ring->next_to_clean;
1645
1646 while (*work_done < work_to_do) {
1647 /* Check Rx descriptor status */
1648 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1649 if (rx_desc->gbec_status == DSC_INIT16)
1650 break;
1651 cleaned = true;
1652 cleaned_count++;
1653
1654 dma_status = rx_desc->dma_status;
1655 gbec_status = rx_desc->gbec_status;
1656 tcp_ip_status = rx_desc->tcp_ip_status;
1657 rx_desc->gbec_status = DSC_INIT16;
1658 buffer_info = &rx_ring->buffer_info[i];
1659 skb = buffer_info->skb;
124d770a 1660 buffer_info->skb = NULL;
77555ee7
MO		 1661
1662 /* unmap dma */
1663 dma_unmap_single(&pdev->dev, buffer_info->dma,
1664 buffer_info->length, DMA_FROM_DEVICE);
1665 buffer_info->mapped = false;
77555ee7 1666
453ca931
AS		 1667 netdev_dbg(netdev,
1668 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n",
1669 i, dma_status, gbec_status, tcp_ip_status,
1670 buffer_info);
77555ee7
MO		 1671 /* Error check */
1672 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1673 adapter->stats.rx_frame_errors++;
453ca931 1674 netdev_err(netdev, "Receive Not Octal Error\n");
77555ee7
MO		 1675 } else if (unlikely(gbec_status &
1676 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1677 adapter->stats.rx_frame_errors++;
453ca931 1678 netdev_err(netdev, "Receive Nibble Error\n");
77555ee7
MO		 1679 } else if (unlikely(gbec_status &
1680 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1681 adapter->stats.rx_crc_errors++;
453ca931 1682 netdev_err(netdev, "Receive CRC Error\n");
77555ee7
MO		 1683 } else {
1684 /* get receive length */
124d770a
TO		 1685 /* length convert[-3], length includes FCS length */
1686 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1687 if (rx_desc->rx_words_eob & 0x02)
1688 length = length - 4;
1689 /*
1690 * buffer_info->rx_buffer: [Header:14][payload]
1691 * skb->data: [Reserve:2][Header:14][payload]
1692 */
1693 memcpy(skb->data, buffer_info->rx_buffer, length);
1694
77555ee7
MO		 1695 /* update status of driver */
1696 adapter->stats.rx_bytes += length;
1697 adapter->stats.rx_packets++;
1698 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1699 adapter->stats.multicast++;
1700 /* Write meta date of skb */
1701 skb_put(skb, length);
1a0bdadb 1702
1a0bdadb 1703 pch_rx_timestamp(adapter, skb);
1a0bdadb 1704
77555ee7 1705 skb->protocol = eth_type_trans(skb, netdev);
5d05a04d 1706 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
5d05a04d 1707 skb->ip_summed = CHECKSUM_UNNECESSARY;
76a0e681
VF		 1708 else
1709 skb->ip_summed = CHECKSUM_NONE;
5d05a04d 1710
77555ee7
MO		 1711 napi_gro_receive(&adapter->napi, skb);
1712 (*work_done)++;
453ca931
AS		 1713 netdev_dbg(netdev,
1714 "Receive skb->ip_summed: %d length: %d\n",
1715 skb->ip_summed, length);
77555ee7 1716 }
77555ee7
MO		 1717 /* return some buffers to hardware, one at a time is too slow */
1718 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1719 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1720 cleaned_count);
1721 cleaned_count = 0;
1722 }
1723 if (++i == rx_ring->count)
1724 i = 0;
1725 }
1726 rx_ring->next_to_clean = i;
1727 if (cleaned_count)
1728 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1729 return cleaned;
1730}
1731
1732/**
1733 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1734 * @adapter: Board private structure
1735 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
49ce9c2c 1736 * Returns:
77555ee7
MO		 1737 * 0: Successfully
1738 * Negative value: Failed
1739 */
1740int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1741 struct pch_gbe_tx_ring *tx_ring)
1742{
1743 struct pci_dev *pdev = adapter->pdev;
1744 struct pch_gbe_tx_desc *tx_desc;
1745 int size;
1746 int desNo;
1747
1748 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
89bf67f1 1749 tx_ring->buffer_info = vzalloc(size);
e404decb 1750 if (!tx_ring->buffer_info)
77555ee7 1751 return -ENOMEM;
77555ee7
MO		 1752
1753 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1754
750afb08
LC		 1755 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1756 &tx_ring->dma, GFP_KERNEL);
77555ee7
MO		 1757 if (!tx_ring->desc) {
1758 vfree(tx_ring->buffer_info);
77555ee7
MO		 1759 return -ENOMEM;
1760 }
77555ee7
MO		 1761
1762 tx_ring->next_to_use = 0;
1763 tx_ring->next_to_clean = 0;
77555ee7
MO		 1764
1765 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1766 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1767 tx_desc->gbec_status = DSC_INIT16;
1768 }
453ca931
AS		 1769 netdev_dbg(adapter->netdev,
1770 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1771 tx_ring->desc, (unsigned long long)tx_ring->dma,
1772 tx_ring->next_to_clean, tx_ring->next_to_use);
77555ee7
MO		 1773 return 0;
1774}
1775
1776/**
1777 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1778 * @adapter: Board private structure
1779 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
49ce9c2c 1780 * Returns:
77555ee7
MO		 1781 * 0: Successfully
1782 * Negative value: Failed
1783 */
1784int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1785 struct pch_gbe_rx_ring *rx_ring)
1786{
1787 struct pci_dev *pdev = adapter->pdev;
1788 struct pch_gbe_rx_desc *rx_desc;
1789 int size;
1790 int desNo;
1791
1792 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
89bf67f1 1793 rx_ring->buffer_info = vzalloc(size);
e404decb 1794 if (!rx_ring->buffer_info)
77555ee7 1795 return -ENOMEM;
e404decb 1796
77555ee7 1797 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
750afb08
LC		 1798 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1799 &rx_ring->dma, GFP_KERNEL);
77555ee7 1800 if (!rx_ring->desc) {
77555ee7
MO		 1801 vfree(rx_ring->buffer_info);
1802 return -ENOMEM;
1803 }
77555ee7
MO		 1804 rx_ring->next_to_clean = 0;
1805 rx_ring->next_to_use = 0;
1806 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1807 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1808 rx_desc->gbec_status = DSC_INIT16;
1809 }
453ca931
AS		 1810 netdev_dbg(adapter->netdev,
1811 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1812 rx_ring->desc, (unsigned long long)rx_ring->dma,
1813 rx_ring->next_to_clean, rx_ring->next_to_use);
77555ee7
MO		 1814 return 0;
1815}
1816
1817/**
1818 * pch_gbe_free_tx_resources - Free Tx Resources
1819 * @adapter: Board private structure
1820 * @tx_ring: Tx descriptor ring for a specific queue
1821 */
1822void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1823 struct pch_gbe_tx_ring *tx_ring)
1824{
1825 struct pci_dev *pdev = adapter->pdev;
1826
1827 pch_gbe_clean_tx_ring(adapter, tx_ring);
1828 vfree(tx_ring->buffer_info);
1829 tx_ring->buffer_info = NULL;
1830 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1831 tx_ring->desc = NULL;
1832}
1833
1834/**
1835 * pch_gbe_free_rx_resources - Free Rx Resources
1836 * @adapter: Board private structure
1837 * @rx_ring: Ring to clean the resources from
1838 */
1839void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1840 struct pch_gbe_rx_ring *rx_ring)
1841{
1842 struct pci_dev *pdev = adapter->pdev;
1843
1844 pch_gbe_clean_rx_ring(adapter, rx_ring);
1845 vfree(rx_ring->buffer_info);
1846 rx_ring->buffer_info = NULL;
1847 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1848 rx_ring->desc = NULL;
1849}
1850
1851/**
1852 * pch_gbe_request_irq - Allocate an interrupt line
1853 * @adapter: Board private structure
49ce9c2c 1854 * Returns:
77555ee7
MO		 1855 * 0: Successfully
1856 * Negative value: Failed
1857 */
1858static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1859{
1860 struct net_device *netdev = adapter->netdev;
1861 int err;
77555ee7 1862
2a600d97
AS		 1863 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1864 if (err < 0)
1865 return err;
1866
1867 adapter->irq = pci_irq_vector(adapter->pdev, 0);
1868
1869 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED,
1870 netdev->name, netdev);
77555ee7 1871 if (err)
453ca931
AS		 1872 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1873 err);
2a600d97
AS		 1874 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n",
1875 pci_dev_msi_enabled(adapter->pdev), err);
77555ee7
MO		 1876 return err;
1877}
1878
77555ee7
MO		 1879/**
1880 * pch_gbe_up - Up GbE network device
1881 * @adapter: Board private structure
49ce9c2c 1882 * Returns:
77555ee7
MO		 1883 * 0: Successfully
1884 * Negative value: Failed
1885 */
1886int pch_gbe_up(struct pch_gbe_adapter *adapter)
1887{
1888 struct net_device *netdev = adapter->netdev;
1889 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1890 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
a2fc66ce 1891 int err = -EINVAL;
77555ee7 1892
2b53d078
DH		 1893 /* Ensure we have a valid MAC */
1894 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
453ca931 1895 netdev_err(netdev, "Error: Invalid MAC address\n");
a2fc66ce 1896 goto out;
2b53d078
DH		 1897 }
1898
77555ee7
MO		 1899 /* hardware has been reset, we need to reload some things */
1900 pch_gbe_set_multi(netdev);
1901
1902 pch_gbe_setup_tctl(adapter);
1903 pch_gbe_configure_tx(adapter);
1904 pch_gbe_setup_rctl(adapter);
1905 pch_gbe_configure_rx(adapter);
1906
1907 err = pch_gbe_request_irq(adapter);
1908 if (err) {
453ca931
AS		 1909 netdev_err(netdev,
1910 "Error: can't bring device up - irq request failed\n");
a2fc66ce 1911 goto out;
77555ee7 1912 }
124d770a
TO		 1913 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1914 if (err) {
453ca931
AS		 1915 netdev_err(netdev,
1916 "Error: can't bring device up - alloc rx buffers pool failed\n");
a2fc66ce 1917 goto freeirq;
124d770a 1918 }
77555ee7
MO		 1919 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1920 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1921 adapter->tx_queue_len = netdev->tx_queue_len;
a35279f0
VF		 1922 pch_gbe_enable_dma_rx(&adapter->hw);
1923 pch_gbe_enable_mac_rx(&adapter->hw);
77555ee7
MO		 1924
1925 mod_timer(&adapter->watchdog_timer, jiffies);
1926
1927 napi_enable(&adapter->napi);
1928 pch_gbe_irq_enable(adapter);
1929 netif_start_queue(adapter->netdev);
1930
1931 return 0;
a2fc66ce
VF		 1932
1933freeirq:
1934 pch_gbe_free_irq(adapter);
1935out:
1936 return err;
77555ee7
MO		 1937}
1938
1939/**
1940 * pch_gbe_down - Down GbE network device
1941 * @adapter: Board private structure
1942 */
1943void pch_gbe_down(struct pch_gbe_adapter *adapter)
1944{
1945 struct net_device *netdev = adapter->netdev;
6d8d2dd8 1946 struct pci_dev *pdev = adapter->pdev;
124d770a 1947 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
77555ee7
MO		 1948
1949 /* signal that we're down so the interrupt handler does not
1950 * reschedule our watchdog timer */
1951 napi_disable(&adapter->napi);
1952 atomic_set(&adapter->irq_sem, 0);
1953
1954 pch_gbe_irq_disable(adapter);
1955 pch_gbe_free_irq(adapter);
1956
1957 del_timer_sync(&adapter->watchdog_timer);
1958
1959 netdev->tx_queue_len = adapter->tx_queue_len;
1960 netif_carrier_off(netdev);
1961 netif_stop_queue(netdev);
1962
6d8d2dd8
WY		 1963 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1964 pch_gbe_reset(adapter);
77555ee7
MO		 1965 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1966 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
124d770a
TO		 1967
1968 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
1969 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
1970 rx_ring->rx_buff_pool_logic = 0;
1971 rx_ring->rx_buff_pool_size = 0;
1972 rx_ring->rx_buff_pool = NULL;
77555ee7
MO		 1973}
1974
1975/**
1976 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1977 * @adapter: Board private structure to initialize
49ce9c2c 1978 * Returns:
77555ee7
MO		 1979 * 0: Successfully
1980 * Negative value: Failed
1981 */
1982static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1983{
1984 struct pch_gbe_hw *hw = &adapter->hw;
1985 struct net_device *netdev = adapter->netdev;
1986
1987 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1988 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1989 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
c63ebdf0 1990 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
77555ee7 1991
77555ee7 1992 if (pch_gbe_alloc_queues(adapter)) {
453ca931 1993 netdev_err(netdev, "Unable to allocate memory for queues\n");
77555ee7
MO		 1994 return -ENOMEM;
1995 }
1996 spin_lock_init(&adapter->hw.miim_lock);
77555ee7
MO		 1997 spin_lock_init(&adapter->stats_lock);
1998 spin_lock_init(&adapter->ethtool_lock);
1999 atomic_set(&adapter->irq_sem, 0);
2000 pch_gbe_irq_disable(adapter);
2001
2002 pch_gbe_init_stats(adapter);
2003
453ca931
AS		 2004 netdev_dbg(netdev,
2005 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
2006 (u32) adapter->rx_buffer_len,
2007 hw->mac.min_frame_size, hw->mac.max_frame_size);
77555ee7
MO		 2008 return 0;
2009}
2010
2011/**
2012 * pch_gbe_open - Called when a network interface is made active
2013 * @netdev: Network interface device structure
49ce9c2c 2014 * Returns:
77555ee7
MO		 2015 * 0: Successfully
2016 * Negative value: Failed
2017 */
2018static int pch_gbe_open(struct net_device *netdev)
2019{
2020 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2021 struct pch_gbe_hw *hw = &adapter->hw;
2022 int err;
2023
2024 /* allocate transmit descriptors */
2025 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2026 if (err)
2027 goto err_setup_tx;
2028 /* allocate receive descriptors */
2029 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2030 if (err)
2031 goto err_setup_rx;
ac6c0e0a 2032 pch_gbe_phy_power_up(hw);
77555ee7
MO		 2033 err = pch_gbe_up(adapter);
2034 if (err)
2035 goto err_up;
453ca931 2036 netdev_dbg(netdev, "Success End\n");
77555ee7
MO		 2037 return 0;
2038
2039err_up:
2040 if (!adapter->wake_up_evt)
ac6c0e0a 2041 pch_gbe_phy_power_down(hw);
77555ee7
MO		 2042 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2043err_setup_rx:
2044 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2045err_setup_tx:
2046 pch_gbe_reset(adapter);
453ca931 2047 netdev_err(netdev, "Error End\n");
77555ee7
MO		 2048 return err;
2049}
2050
2051/**
2052 * pch_gbe_stop - Disables a network interface
2053 * @netdev: Network interface device structure
49ce9c2c 2054 * Returns:
77555ee7
MO		 2055 * 0: Successfully
2056 */
2057static int pch_gbe_stop(struct net_device *netdev)
2058{
2059 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2060 struct pch_gbe_hw *hw = &adapter->hw;
2061
2062 pch_gbe_down(adapter);
2063 if (!adapter->wake_up_evt)
ac6c0e0a 2064 pch_gbe_phy_power_down(hw);
77555ee7
MO		 2065 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2066 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2067 return 0;
2068}
2069
2070/**
2071 * pch_gbe_xmit_frame - Packet transmitting start
2072 * @skb: Socket buffer structure
2073 * @netdev: Network interface device structure
49ce9c2c 2074 * Returns:
77555ee7
MO		 2075 * - NETDEV_TX_OK: Normal end
2076 * - NETDEV_TX_BUSY: Error end
2077 */
2078static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2079{
2080 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2081 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
a6086a89 2082
77555ee7
MO		 2083 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2084 netif_stop_queue(netdev);
453ca931
AS		 2085 netdev_dbg(netdev,
2086 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2087 tx_ring->next_to_use, tx_ring->next_to_clean);
77555ee7
MO		 2088 return NETDEV_TX_BUSY;
2089 }
77555ee7
MO		 2090
2091 /* CRC,ITAG no support */
2092 pch_gbe_tx_queue(adapter, tx_ring, skb);
2093 return NETDEV_TX_OK;
2094}
2095
77555ee7
MO		 2096/**
2097 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2098 * @netdev: Network interface device structure
2099 */
2100static void pch_gbe_set_multi(struct net_device *netdev)
2101{
2102 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2103 struct pch_gbe_hw *hw = &adapter->hw;
2104 struct netdev_hw_addr *ha;
6ab91e47
PB		 2105 u32 rctl, adrmask;
2106 int mc_count, i;
77555ee7 2107
453ca931 2108 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
77555ee7 2109
418e7dab 2110 /* By default enable address & multicast filtering */
77555ee7 2111 rctl = ioread32(&hw->reg->RX_MODE);
418e7dab
PB		 2112 rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN;
2113
2114 /* Promiscuous mode disables all hardware address filtering */
2115 if (netdev->flags & IFF_PROMISC)
2116 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2117
2118 /* If we want to monitor more multicast addresses than the hardware can
2119 * support then disable hardware multicast filtering.
2120 */
77555ee7 2121 mc_count = netdev_mc_count(netdev);
418e7dab 2122 if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES)
77555ee7 2123 rctl &= ~PCH_GBE_MLT_FIL_EN;
418e7dab 2124
77555ee7
MO		 2125 iowrite32(rctl, &hw->reg->RX_MODE);
2126
418e7dab
PB		 2127 /* If we're not using multicast filtering then there's no point
2128 * configuring the unused MAC address registers.
2129 */
2130 if (!(rctl & PCH_GBE_MLT_FIL_EN))
77555ee7 2131 return;
77555ee7 2132
6ab91e47
PB		 2133 /* Load the first set of multicast addresses into MAC address registers
2134 * for use by hardware filtering.
2135 */
2136 i = 1;
2137 netdev_for_each_mc_addr(ha, netdev)
2138 pch_gbe_mac_mar_set(hw, ha->addr, i++);
2139
2140 /* If there are spare MAC registers, mask & clear them */
2141 for (; i < PCH_GBE_MAR_ENTRIES; i++) {
2142 /* Clear MAC address mask */
2143 adrmask = ioread32(&hw->reg->ADDR_MASK);
2144 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK);
2145 /* wait busy */
2146 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
2147 /* Clear MAC address */
2148 iowrite32(0, &hw->reg->mac_adr[i].high);
2149 iowrite32(0, &hw->reg->mac_adr[i].low);
77555ee7 2150 }
77555ee7 2151
453ca931
AS		 2152 netdev_dbg(netdev,
2153 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
77555ee7
MO		 2154 ioread32(&hw->reg->RX_MODE), mc_count);
2155}
2156
2157/**
2158 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2159 * @netdev: Network interface device structure
2160 * @addr: Pointer to an address structure
49ce9c2c 2161 * Returns:
77555ee7
MO		 2162 * 0: Successfully
2163 * -EADDRNOTAVAIL: Failed
2164 */
2165static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2166{
2167 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2168 struct sockaddr *skaddr = addr;
2169 int ret_val;
2170
2171 if (!is_valid_ether_addr(skaddr->sa_data)) {
2172 ret_val = -EADDRNOTAVAIL;
2173 } else {
2174 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2175 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2176 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2177 ret_val = 0;
2178 }
453ca931
AS		 2179 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2180 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2181 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2182 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2183 ioread32(&adapter->hw.reg->mac_adr[0].high),
2184 ioread32(&adapter->hw.reg->mac_adr[0].low));
77555ee7
MO		 2185 return ret_val;
2186}
2187
2188/**
2189 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2190 * @netdev: Network interface device structure
2191 * @new_mtu: New value for maximum frame size
49ce9c2c 2192 * Returns:
77555ee7
MO		 2193 * 0: Successfully
2194 * -EINVAL: Failed
2195 */
2196static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2197{
2198 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
44770e11 2199 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
124d770a
TO		 2200 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2201 int err;
77555ee7 2202
77555ee7
MO		 2203 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2204 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2205 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2206 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2207 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2208 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2209 else
124d770a 2210 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
77555ee7 2211
124d770a
TO		 2212 if (netif_running(netdev)) {
2213 pch_gbe_down(adapter);
2214 err = pch_gbe_up(adapter);
2215 if (err) {
2216 adapter->rx_buffer_len = old_rx_buffer_len;
2217 pch_gbe_up(adapter);
474f315d 2218 return err;
124d770a
TO		 2219 } else {
2220 netdev->mtu = new_mtu;
2221 adapter->hw.mac.max_frame_size = max_frame;
2222 }
2223 } else {
77555ee7 2224 pch_gbe_reset(adapter);
124d770a
TO		 2225 netdev->mtu = new_mtu;
2226 adapter->hw.mac.max_frame_size = max_frame;
2227 }
77555ee7 2228
453ca931
AS		 2229 netdev_dbg(netdev,
2230 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2231 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2232 adapter->hw.mac.max_frame_size);
77555ee7
MO		 2233 return 0;
2234}
2235
756a6b03
MM		 2236/**
2237 * pch_gbe_set_features - Reset device after features changed
2238 * @netdev: Network interface device structure
2239 * @features: New features
49ce9c2c 2240 * Returns:
756a6b03
MM		 2241 * 0: HW state updated successfully
2242 */
c8f44aff
MM		 2243static int pch_gbe_set_features(struct net_device *netdev,
2244 netdev_features_t features)
756a6b03
MM		 2245{
2246 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
c8f44aff 2247 netdev_features_t changed = features ^ netdev->features;
756a6b03
MM		 2248
2249 if (!(changed & NETIF_F_RXCSUM))
2250 return 0;
2251
2252 if (netif_running(netdev))
2253 pch_gbe_reinit_locked(adapter);
2254 else
2255 pch_gbe_reset(adapter);
2256
2257 return 0;
2258}
2259
77555ee7
MO		 2260/**
2261 * pch_gbe_ioctl - Controls register through a MII interface
2262 * @netdev: Network interface device structure
2263 * @ifr: Pointer to ifr structure
2264 * @cmd: Control command
49ce9c2c 2265 * Returns:
77555ee7
MO		 2266 * 0: Successfully
2267 * Negative value: Failed
2268 */
2269static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2270{
2271 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2272
453ca931 2273 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
77555ee7 2274
1a0bdadb
TS		 2275 if (cmd == SIOCSHWTSTAMP)
2276 return hwtstamp_ioctl(netdev, ifr, cmd);
1a0bdadb 2277
77555ee7
MO		 2278 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2279}
2280
2281/**
2282 * pch_gbe_tx_timeout - Respond to a Tx Hang
2283 * @netdev: Network interface device structure
2284 */
2285static void pch_gbe_tx_timeout(struct net_device *netdev)
2286{
2287 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2288
2289 /* Do the reset outside of interrupt context */
2290 adapter->stats.tx_timeout_count++;
2291 schedule_work(&adapter->reset_task);
2292}
2293
2294/**
2295 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2296 * @napi: Pointer of polling device struct
2297 * @budget: The maximum number of a packet
49ce9c2c 2298 * Returns:
77555ee7
MO		 2299 * false: Exit the polling mode
2300 * true: Continue the polling mode
2301 */
2302static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2303{
2304 struct pch_gbe_adapter *adapter =
2305 container_of(napi, struct pch_gbe_adapter, napi);
77555ee7
MO		 2306 int work_done = 0;
2307 bool poll_end_flag = false;
2308 bool cleaned = false;
2309
453ca931 2310 netdev_dbg(adapter->netdev, "budget : %d\n", budget);
77555ee7 2311
805e969f
TO		 2312 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2313 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2314
f2c31662 2315 if (cleaned)
805e969f
TO		 2316 work_done = budget;
2317 /* If no Tx and not enough Rx work done,
2318 * exit the polling mode
2319 */
2320 if (work_done < budget)
77555ee7 2321 poll_end_flag = true;
805e969f
TO		 2322
2323 if (poll_end_flag) {
6ad20165 2324 napi_complete_done(napi, work_done);
805e969f 2325 pch_gbe_irq_enable(adapter);
9c0314e1
VF		 2326 }
2327
2328 if (adapter->rx_stop_flag) {
2329 adapter->rx_stop_flag = false;
a35279f0 2330 pch_gbe_enable_dma_rx(&adapter->hw);
9c0314e1 2331 }
77555ee7 2332
453ca931
AS		 2333 netdev_dbg(adapter->netdev,
2334 "poll_end_flag : %d work_done : %d budget : %d\n",
2335 poll_end_flag, work_done, budget);
77555ee7
MO		 2336
2337 return work_done;
2338}
2339
2340#ifdef CONFIG_NET_POLL_CONTROLLER
2341/**
2342 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2343 * @netdev: Network interface device structure
2344 */
2345static void pch_gbe_netpoll(struct net_device *netdev)
2346{
2347 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2348
2a600d97
AS		 2349 disable_irq(adapter->irq);
2350 pch_gbe_intr(adapter->irq, netdev);
2351 enable_irq(adapter->irq);
77555ee7
MO		 2352}
2353#endif
2354
2355static const struct net_device_ops pch_gbe_netdev_ops = {
2356 .ndo_open = pch_gbe_open,
2357 .ndo_stop = pch_gbe_stop,
2358 .ndo_start_xmit = pch_gbe_xmit_frame,
77555ee7
MO		 2359 .ndo_set_mac_address = pch_gbe_set_mac,
2360 .ndo_tx_timeout = pch_gbe_tx_timeout,
2361 .ndo_change_mtu = pch_gbe_change_mtu,
756a6b03 2362 .ndo_set_features = pch_gbe_set_features,
77555ee7 2363 .ndo_do_ioctl = pch_gbe_ioctl,
afc4b13d 2364 .ndo_set_rx_mode = pch_gbe_set_multi,
77555ee7
MO		 2365#ifdef CONFIG_NET_POLL_CONTROLLER
2366 .ndo_poll_controller = pch_gbe_netpoll,
2367#endif
2368};
2369
2370static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2371 pci_channel_state_t state)
2372{
2373 struct net_device *netdev = pci_get_drvdata(pdev);
2374 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2375
2376 netif_device_detach(netdev);
2377 if (netif_running(netdev))
2378 pch_gbe_down(adapter);
2379 pci_disable_device(pdev);
2380 /* Request a slot slot reset. */
2381 return PCI_ERS_RESULT_NEED_RESET;
2382}
2383
2384static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2385{
2386 struct net_device *netdev = pci_get_drvdata(pdev);
2387 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2388 struct pch_gbe_hw *hw = &adapter->hw;
2389
2390 if (pci_enable_device(pdev)) {
453ca931 2391 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
77555ee7
MO		 2392 return PCI_ERS_RESULT_DISCONNECT;
2393 }
2394 pci_set_master(pdev);
2395 pci_enable_wake(pdev, PCI_D0, 0);
ac6c0e0a 2396 pch_gbe_phy_power_up(hw);
77555ee7
MO		 2397 pch_gbe_reset(adapter);
2398 /* Clear wake up status */
2399 pch_gbe_mac_set_wol_event(hw, 0);
2400
2401 return PCI_ERS_RESULT_RECOVERED;
2402}
2403
2404static void pch_gbe_io_resume(struct pci_dev *pdev)
2405{
2406 struct net_device *netdev = pci_get_drvdata(pdev);
2407 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2408
2409 if (netif_running(netdev)) {
2410 if (pch_gbe_up(adapter)) {
453ca931
AS		 2411 netdev_dbg(netdev,
2412 "can't bring device back up after reset\n");
77555ee7
MO		 2413 return;
2414 }
2415 }
2416 netif_device_attach(netdev);
2417}
2418
2419static int __pch_gbe_suspend(struct pci_dev *pdev)
2420{
2421 struct net_device *netdev = pci_get_drvdata(pdev);
2422 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2423 struct pch_gbe_hw *hw = &adapter->hw;
2424 u32 wufc = adapter->wake_up_evt;
2425 int retval = 0;
2426
2427 netif_device_detach(netdev);
2428 if (netif_running(netdev))
2429 pch_gbe_down(adapter);
2430 if (wufc) {
2431 pch_gbe_set_multi(netdev);
2432 pch_gbe_setup_rctl(adapter);
2433 pch_gbe_configure_rx(adapter);
2434 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2435 hw->mac.link_duplex);
2436 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2437 hw->mac.link_duplex);
2438 pch_gbe_mac_set_wol_event(hw, wufc);
2439 pci_disable_device(pdev);
2440 } else {
ac6c0e0a 2441 pch_gbe_phy_power_down(hw);
77555ee7
MO		 2442 pch_gbe_mac_set_wol_event(hw, wufc);
2443 pci_disable_device(pdev);
2444 }
2445 return retval;
2446}
2447
2448#ifdef CONFIG_PM
2449static int pch_gbe_suspend(struct device *device)
2450{
2451 struct pci_dev *pdev = to_pci_dev(device);
2452
2453 return __pch_gbe_suspend(pdev);
2454}
2455
2456static int pch_gbe_resume(struct device *device)
2457{
2458 struct pci_dev *pdev = to_pci_dev(device);
2459 struct net_device *netdev = pci_get_drvdata(pdev);
2460 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2461 struct pch_gbe_hw *hw = &adapter->hw;
2462 u32 err;
2463
2464 err = pci_enable_device(pdev);
2465 if (err) {
453ca931 2466 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
77555ee7
MO		 2467 return err;
2468 }
2469 pci_set_master(pdev);
ac6c0e0a 2470 pch_gbe_phy_power_up(hw);
77555ee7
MO		 2471 pch_gbe_reset(adapter);
2472 /* Clear wake on lan control and status */
2473 pch_gbe_mac_set_wol_event(hw, 0);
2474
2475 if (netif_running(netdev))
2476 pch_gbe_up(adapter);
2477 netif_device_attach(netdev);
2478
2479 return 0;
2480}
2481#endif /* CONFIG_PM */
2482
2483static void pch_gbe_shutdown(struct pci_dev *pdev)
2484{
2485 __pch_gbe_suspend(pdev);
2486 if (system_state == SYSTEM_POWER_OFF) {
2487 pci_wake_from_d3(pdev, true);
2488 pci_set_power_state(pdev, PCI_D3hot);
2489 }
2490}
2491
2492static void pch_gbe_remove(struct pci_dev *pdev)
2493{
2494 struct net_device *netdev = pci_get_drvdata(pdev);
2495 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2496
2321f3b4 2497 cancel_work_sync(&adapter->reset_task);
77555ee7
MO		 2498 unregister_netdev(netdev);
2499
7dbe38ae 2500 pch_gbe_phy_hw_reset(&adapter->hw);
77555ee7 2501
77555ee7 2502 free_netdev(netdev);
77555ee7
MO		 2503}
2504
2505static int pch_gbe_probe(struct pci_dev *pdev,
2506 const struct pci_device_id *pci_id)
2507{
2508 struct net_device *netdev;
2509 struct pch_gbe_adapter *adapter;
2510 int ret;
2511
29cc436c 2512 ret = pcim_enable_device(pdev);
77555ee7
MO		 2513 if (ret)
2514 return ret;
2515
2516 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2517 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2518 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2519 if (ret) {
2520 ret = pci_set_consistent_dma_mask(pdev,
2521 DMA_BIT_MASK(32));
2522 if (ret) {
2523 dev_err(&pdev->dev, "ERR: No usable DMA "
2524 "configuration, aborting\n");
29cc436c 2525 return ret;
77555ee7
MO		 2526 }
2527 }
2528 }
2529
29cc436c 2530 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
77555ee7
MO		 2531 if (ret) {
2532 dev_err(&pdev->dev,
2533 "ERR: Can't reserve PCI I/O and memory resources\n");
29cc436c 2534 return ret;
77555ee7
MO		 2535 }
2536 pci_set_master(pdev);
2537
2538 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
29cc436c
AS		 2539 if (!netdev)
2540 return -ENOMEM;
77555ee7
MO		 2541 SET_NETDEV_DEV(netdev, &pdev->dev);
2542
2543 pci_set_drvdata(pdev, netdev);
2544 adapter = netdev_priv(netdev);
2545 adapter->netdev = netdev;
2546 adapter->pdev = pdev;
2547 adapter->hw.back = adapter;
29cc436c 2548 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
f1a26fdf
DH		 2549 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2550 if (adapter->pdata && adapter->pdata->platform_init)
2551 adapter->pdata->platform_init(pdev);
77555ee7 2552
2e1c8725
SK		 2553 adapter->ptp_pdev =
2554 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
2555 adapter->pdev->bus->number,
2556 PCI_DEVFN(12, 4));
1a0bdadb 2557
77555ee7
MO		 2558 netdev->netdev_ops = &pch_gbe_netdev_ops;
2559 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2560 netif_napi_add(netdev, &adapter->napi,
2561 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
756a6b03
MM		 2562 netdev->hw_features = NETIF_F_RXCSUM |
2563 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2564 netdev->features = netdev->hw_features;
77555ee7
MO		 2565 pch_gbe_set_ethtool_ops(netdev);
2566
44770e11
JW		 2567 /* MTU range: 46 - 10300 */
2568 netdev->min_mtu = ETH_ZLEN - ETH_HLEN;
2569 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE -
2570 (ETH_HLEN + ETH_FCS_LEN);
2571
98200ec2 2572 pch_gbe_mac_load_mac_addr(&adapter->hw);
77555ee7
MO		 2573 pch_gbe_mac_reset_hw(&adapter->hw);
2574
2575 /* setup the private structure */
2576 ret = pch_gbe_sw_init(adapter);
2577 if (ret)
29cc436c 2578 goto err_free_netdev;
77555ee7
MO		 2579
2580 /* Initialize PHY */
2581 ret = pch_gbe_init_phy(adapter);
2582 if (ret) {
2583 dev_err(&pdev->dev, "PHY initialize error\n");
2584 goto err_free_adapter;
2585 }
77555ee7
MO		 2586
2587 /* Read the MAC address. and store to the private data */
9c020d7b 2588 ret = pch_gbe_mac_read_mac_addr(&adapter->hw);
77555ee7
MO		 2589 if (ret) {
2590 dev_err(&pdev->dev, "MAC address Read Error\n");
2591 goto err_free_adapter;
2592 }
2593
2594 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2595 if (!is_valid_ether_addr(netdev->dev_addr)) {
2b53d078
DH		 2596 /*
2597 * If the MAC is invalid (or just missing), display a warning
2598 * but do not abort setting up the device. pch_gbe_up will
2599 * prevent the interface from being brought up until a valid MAC
2600 * is set.
2601 */
2602 dev_err(&pdev->dev, "Invalid MAC address, "
2603 "interface disabled.\n");
77555ee7 2604 }
e99e88a9 2605 timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0);
77555ee7
MO		 2606
2607 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2608
2609 pch_gbe_check_options(adapter);
2610
77555ee7
MO		 2611 /* initialize the wol settings based on the eeprom settings */
2612 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2613 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2614
2615 /* reset the hardware with the new settings */
2616 pch_gbe_reset(adapter);
2617
2618 ret = register_netdev(netdev);
2619 if (ret)
2620 goto err_free_adapter;
2621 /* tell the stack to leave us alone until pch_gbe_open() is called */
2622 netif_carrier_off(netdev);
2623 netif_stop_queue(netdev);
2624
1a0bdadb 2625 dev_dbg(&pdev->dev, "PCH Network Connection\n");
77555ee7 2626
f1a26fdf
DH		 2627 /* Disable hibernation on certain platforms */
2628 if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2629 pch_gbe_phy_disable_hibernate(&adapter->hw);
2630
77555ee7
MO		 2631 device_set_wakeup_enable(&pdev->dev, 1);
2632 return 0;
2633
2634err_free_adapter:
7dbe38ae 2635 pch_gbe_phy_hw_reset(&adapter->hw);
77555ee7
MO		 2636err_free_netdev:
2637 free_netdev(netdev);
77555ee7
MO		 2638 return ret;
2639}
2640
f1a26fdf
DH		 2641/* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2642 * ensure it is awake for probe and init. Request the line and reset the PHY.
2643 */
2644static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2645{
2646 unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2647 unsigned gpio = MINNOW_PHY_RESET_GPIO;
2648 int ret;
2649
2650 ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2651 "minnow_phy_reset");
2652 if (ret) {
2653 dev_err(&pdev->dev,
2654 "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2655 return ret;
2656 }
2657
2658 gpio_set_value(gpio, 0);
2659 usleep_range(1250, 1500);
2660 gpio_set_value(gpio, 1);
2661 usleep_range(1250, 1500);
2662
2663 return ret;
2664}
2665
2666static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2667 .phy_tx_clk_delay = true,
2668 .phy_disable_hibernate = true,
2669 .platform_init = pch_gbe_minnow_platform_init,
2670};
2671
9baa3c34 2672static const struct pci_device_id pch_gbe_pcidev_id[] = {
f1a26fdf
DH		 2673 {.vendor = PCI_VENDOR_ID_INTEL,
2674 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2675 .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2676 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2677 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2678 .class_mask = (0xFFFF00),
2679 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2680 },
77555ee7
MO		 2681 {.vendor = PCI_VENDOR_ID_INTEL,
2682 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2683 .subvendor = PCI_ANY_ID,
2684 .subdevice = PCI_ANY_ID,
2685 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2686 .class_mask = (0xFFFF00)
2687 },
b0e6baf5
T		 2688 {.vendor = PCI_VENDOR_ID_ROHM,
2689 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2690 .subvendor = PCI_ANY_ID,
2691 .subdevice = PCI_ANY_ID,
2692 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2693 .class_mask = (0xFFFF00)
2694 },
7756332f
TO		 2695 {.vendor = PCI_VENDOR_ID_ROHM,
2696 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2697 .subvendor = PCI_ANY_ID,
2698 .subdevice = PCI_ANY_ID,
2699 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2700 .class_mask = (0xFFFF00)
2701 },
77555ee7
MO		 2702 /* required last entry */
2703 {0}
2704};
2705
2706#ifdef CONFIG_PM
2707static const struct dev_pm_ops pch_gbe_pm_ops = {
2708 .suspend = pch_gbe_suspend,
2709 .resume = pch_gbe_resume,
2710 .freeze = pch_gbe_suspend,
2711 .thaw = pch_gbe_resume,
2712 .poweroff = pch_gbe_suspend,
2713 .restore = pch_gbe_resume,
2714};
2715#endif
2716
3646f0e5 2717static const struct pci_error_handlers pch_gbe_err_handler = {
77555ee7
MO		 2718 .error_detected = pch_gbe_io_error_detected,
2719 .slot_reset = pch_gbe_io_slot_reset,
2720 .resume = pch_gbe_io_resume
2721};
2722
f7594d42 2723static struct pci_driver pch_gbe_driver = {
77555ee7
MO		 2724 .name = KBUILD_MODNAME,
2725 .id_table = pch_gbe_pcidev_id,
2726 .probe = pch_gbe_probe,
2727 .remove = pch_gbe_remove,
aa338601 2728#ifdef CONFIG_PM
77555ee7
MO		 2729 .driver.pm = &pch_gbe_pm_ops,
2730#endif
2731 .shutdown = pch_gbe_shutdown,
2732 .err_handler = &pch_gbe_err_handler
2733};
99a9c288 2734module_pci_driver(pch_gbe_driver);
77555ee7 2735
a1dcfcb7 2736MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
1a0bdadb 2737MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
77555ee7
MO		 2738MODULE_LICENSE("GPL");
2739MODULE_VERSION(DRV_VERSION);
2740MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2741
77555ee7 2742/* pch_gbe_main.c */
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