]>
Commit | Line | Data |
---|---|---|
f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 16 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
f5cd7872 OJ |
17 | */ |
18 | ||
f5cd7872 OJ |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
f5cd7872 OJ |
22 | #include <linux/interrupt.h> |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/netdevice.h> | |
1dd2d06c | 26 | #include <linux/of_mdio.h> |
f5cd7872 OJ |
27 | #include <linux/etherdevice.h> |
28 | #include <asm/dma-mapping.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/skbuff.h> | |
31 | ||
32 | #include <linux/ip.h> | |
f5cd7872 | 33 | #include <net/checksum.h> |
70c71606 | 34 | #include <linux/prefetch.h> |
f5cd7872 | 35 | |
771f7404 | 36 | #include <asm/irq.h> |
af289e80 | 37 | #include <asm/firmware.h> |
40afa531 | 38 | #include <asm/pasemi_dma.h> |
771f7404 | 39 | |
f5cd7872 OJ |
40 | #include "pasemi_mac.h" |
41 | ||
8dc121a4 OJ |
42 | /* We have our own align, since ppc64 in general has it at 0 because |
43 | * of design flaws in some of the server bridge chips. However, for | |
44 | * PWRficient doing the unaligned copies is more expensive than doing | |
45 | * unaligned DMA, so make sure the data is aligned instead. | |
46 | */ | |
47 | #define LOCAL_SKB_ALIGN 2 | |
f5cd7872 OJ |
48 | |
49 | /* TODO list | |
50 | * | |
f5cd7872 OJ |
51 | * - Multicast support |
52 | * - Large MTU support | |
7ddeae2c | 53 | * - Multiqueue RX/TX |
f5cd7872 OJ |
54 | */ |
55 | ||
44770e11 | 56 | #define PE_MIN_MTU (ETH_ZLEN + ETH_HLEN) |
8d636d8b | 57 | #define PE_MAX_MTU 9000 |
ef1ea0b4 OJ |
58 | #define PE_DEF_MTU ETH_DATA_LEN |
59 | ||
ceb51361 OJ |
60 | #define DEFAULT_MSG_ENABLE \ |
61 | (NETIF_MSG_DRV | \ | |
62 | NETIF_MSG_PROBE | \ | |
63 | NETIF_MSG_LINK | \ | |
64 | NETIF_MSG_TIMER | \ | |
65 | NETIF_MSG_IFDOWN | \ | |
66 | NETIF_MSG_IFUP | \ | |
67 | NETIF_MSG_RX_ERR | \ | |
68 | NETIF_MSG_TX_ERR) | |
69 | ||
ceb51361 OJ |
70 | MODULE_LICENSE("GPL"); |
71 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
72 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
73 | ||
74 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
75 | module_param(debug, int, 0); | |
76 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 | 77 | |
e37c772e OJ |
78 | extern const struct ethtool_ops pasemi_mac_ethtool_ops; |
79 | ||
af289e80 OJ |
80 | static int translation_enabled(void) |
81 | { | |
82 | #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) | |
83 | return 1; | |
84 | #else | |
85 | return firmware_has_feature(FW_FEATURE_LPAR); | |
86 | #endif | |
87 | } | |
88 | ||
34c20624 | 89 | static void write_iob_reg(unsigned int reg, unsigned int val) |
a85b9422 | 90 | { |
34c20624 | 91 | pasemi_write_iob_reg(reg, val); |
a85b9422 OJ |
92 | } |
93 | ||
5c15332b | 94 | static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) |
a85b9422 | 95 | { |
34c20624 | 96 | return pasemi_read_mac_reg(mac->dma_if, reg); |
a85b9422 OJ |
97 | } |
98 | ||
5c15332b | 99 | static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, |
a85b9422 OJ |
100 | unsigned int val) |
101 | { | |
34c20624 | 102 | pasemi_write_mac_reg(mac->dma_if, reg, val); |
a85b9422 OJ |
103 | } |
104 | ||
34c20624 | 105 | static unsigned int read_dma_reg(unsigned int reg) |
a85b9422 | 106 | { |
34c20624 | 107 | return pasemi_read_dma_reg(reg); |
a85b9422 OJ |
108 | } |
109 | ||
34c20624 | 110 | static void write_dma_reg(unsigned int reg, unsigned int val) |
a85b9422 | 111 | { |
34c20624 | 112 | pasemi_write_dma_reg(reg, val); |
a85b9422 OJ |
113 | } |
114 | ||
5c15332b | 115 | static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
116 | { |
117 | return mac->rx; | |
118 | } | |
119 | ||
5c15332b | 120 | static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
121 | { |
122 | return mac->tx; | |
123 | } | |
124 | ||
5c15332b OJ |
125 | static inline void prefetch_skb(const struct sk_buff *skb) |
126 | { | |
127 | const void *d = skb; | |
128 | ||
129 | prefetch(d); | |
130 | prefetch(d+64); | |
131 | prefetch(d+128); | |
132 | prefetch(d+192); | |
133 | } | |
134 | ||
34c20624 OJ |
135 | static int mac_to_intf(struct pasemi_mac *mac) |
136 | { | |
137 | struct pci_dev *pdev = mac->pdev; | |
138 | u32 tmp; | |
139 | int nintf, off, i, j; | |
140 | int devfn = pdev->devfn; | |
141 | ||
142 | tmp = read_dma_reg(PAS_DMA_CAP_IFI); | |
143 | nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; | |
144 | off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; | |
145 | ||
146 | /* IOFF contains the offset to the registers containing the | |
147 | * DMA interface-to-MAC-pci-id mappings, and NIN contains number | |
148 | * of total interfaces. Each register contains 4 devfns. | |
149 | * Just do a linear search until we find the devfn of the MAC | |
150 | * we're trying to look up. | |
151 | */ | |
152 | ||
153 | for (i = 0; i < (nintf+3)/4; i++) { | |
154 | tmp = read_dma_reg(off+4*i); | |
155 | for (j = 0; j < 4; j++) { | |
156 | if (((tmp >> (8*j)) & 0xff) == devfn) | |
157 | return i*4 + j; | |
158 | } | |
159 | } | |
160 | return -1; | |
161 | } | |
162 | ||
ef1ea0b4 OJ |
163 | static void pasemi_mac_intf_disable(struct pasemi_mac *mac) |
164 | { | |
165 | unsigned int flags; | |
166 | ||
167 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
168 | flags &= ~PAS_MAC_CFG_PCFG_PE; | |
169 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
170 | } | |
171 | ||
172 | static void pasemi_mac_intf_enable(struct pasemi_mac *mac) | |
173 | { | |
174 | unsigned int flags; | |
175 | ||
176 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
177 | flags |= PAS_MAC_CFG_PCFG_PE; | |
178 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
179 | } | |
180 | ||
f5cd7872 OJ |
181 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
182 | { | |
183 | struct pci_dev *pdev = mac->pdev; | |
184 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
1af7f056 | 185 | int len; |
f5cd7872 | 186 | const u8 *maddr; |
1409a932 | 187 | u8 addr[ETH_ALEN]; |
f5cd7872 OJ |
188 | |
189 | if (!dn) { | |
190 | dev_dbg(&pdev->dev, | |
191 | "No device node for mac, not configuring\n"); | |
192 | return -ENOENT; | |
193 | } | |
194 | ||
1af7f056 | 195 | maddr = of_get_property(dn, "local-mac-address", &len); |
196 | ||
1409a932 JP |
197 | if (maddr && len == ETH_ALEN) { |
198 | memcpy(mac->mac_addr, maddr, ETH_ALEN); | |
1af7f056 | 199 | return 0; |
200 | } | |
201 | ||
202 | /* Some old versions of firmware mistakenly uses mac-address | |
203 | * (and as a string) instead of a byte array in local-mac-address. | |
204 | */ | |
a5fd22eb | 205 | |
a5fd22eb | 206 | if (maddr == NULL) |
9028780a | 207 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 208 | |
f5cd7872 OJ |
209 | if (maddr == NULL) { |
210 | dev_warn(&pdev->dev, | |
211 | "no mac address in device tree, not configuring\n"); | |
212 | return -ENOENT; | |
213 | } | |
214 | ||
1409a932 JP |
215 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", |
216 | &addr[0], &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) | |
217 | != ETH_ALEN) { | |
f5cd7872 OJ |
218 | dev_warn(&pdev->dev, |
219 | "can't parse mac address, not configuring\n"); | |
220 | return -EINVAL; | |
221 | } | |
222 | ||
1409a932 | 223 | memcpy(mac->mac_addr, addr, ETH_ALEN); |
1af7f056 | 224 | |
f5cd7872 OJ |
225 | return 0; |
226 | } | |
227 | ||
5cea73b0 OJ |
228 | static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p) |
229 | { | |
230 | struct pasemi_mac *mac = netdev_priv(dev); | |
231 | struct sockaddr *addr = p; | |
232 | unsigned int adr0, adr1; | |
233 | ||
234 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 235 | return -EADDRNOTAVAIL; |
5cea73b0 OJ |
236 | |
237 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
238 | ||
239 | adr0 = dev->dev_addr[2] << 24 | | |
240 | dev->dev_addr[3] << 16 | | |
241 | dev->dev_addr[4] << 8 | | |
242 | dev->dev_addr[5]; | |
243 | adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1); | |
244 | adr1 &= ~0xffff; | |
245 | adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1]; | |
246 | ||
247 | pasemi_mac_intf_disable(mac); | |
248 | write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0); | |
249 | write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1); | |
250 | pasemi_mac_intf_enable(mac); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
ad3c20d1 | 255 | static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, |
7e9916e9 | 256 | const int nfrags, |
ad3c20d1 | 257 | struct sk_buff *skb, |
5c15332b | 258 | const dma_addr_t *dmas) |
ad3c20d1 OJ |
259 | { |
260 | int f; | |
5c15332b | 261 | struct pci_dev *pdev = mac->dma_pdev; |
ad3c20d1 | 262 | |
5c15332b | 263 | pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
264 | |
265 | for (f = 0; f < nfrags; f++) { | |
9e903e08 | 266 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; |
ad3c20d1 | 267 | |
9e903e08 | 268 | pci_unmap_page(pdev, dmas[f+1], skb_frag_size(frag), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
269 | } |
270 | dev_kfree_skb_irq(skb); | |
271 | ||
272 | /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, | |
273 | * aligned up to a power of 2 | |
274 | */ | |
275 | return (nfrags + 3) & ~1; | |
276 | } | |
277 | ||
8d636d8b OJ |
278 | static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac) |
279 | { | |
280 | struct pasemi_mac_csring *ring; | |
281 | u32 val; | |
282 | unsigned int cfg; | |
283 | int chno; | |
284 | ||
285 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring), | |
286 | offsetof(struct pasemi_mac_csring, chan)); | |
287 | ||
288 | if (!ring) { | |
289 | dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n"); | |
290 | goto out_chan; | |
291 | } | |
292 | ||
293 | chno = ring->chan.chno; | |
294 | ||
295 | ring->size = CS_RING_SIZE; | |
296 | ring->next_to_fill = 0; | |
297 | ||
298 | /* Allocate descriptors */ | |
299 | if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE)) | |
300 | goto out_ring_desc; | |
301 | ||
302 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), | |
303 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
304 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
305 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3); | |
306 | ||
307 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); | |
308 | ||
309 | ring->events[0] = pasemi_dma_alloc_flag(); | |
310 | ring->events[1] = pasemi_dma_alloc_flag(); | |
311 | if (ring->events[0] < 0 || ring->events[1] < 0) | |
312 | goto out_flags; | |
313 | ||
314 | pasemi_dma_clear_flag(ring->events[0]); | |
315 | pasemi_dma_clear_flag(ring->events[1]); | |
316 | ||
317 | ring->fun = pasemi_dma_alloc_fun(); | |
318 | if (ring->fun < 0) | |
319 | goto out_fun; | |
320 | ||
321 | cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP | | |
322 | PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) | | |
323 | PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ; | |
324 | ||
325 | if (translation_enabled()) | |
326 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
327 | ||
328 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); | |
329 | ||
330 | /* enable channel */ | |
331 | pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | | |
332 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
333 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
334 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
335 | ||
336 | return ring; | |
337 | ||
338 | out_fun: | |
339 | out_flags: | |
340 | if (ring->events[0] >= 0) | |
341 | pasemi_dma_free_flag(ring->events[0]); | |
342 | if (ring->events[1] >= 0) | |
343 | pasemi_dma_free_flag(ring->events[1]); | |
344 | pasemi_dma_free_ring(&ring->chan); | |
345 | out_ring_desc: | |
346 | pasemi_dma_free_chan(&ring->chan); | |
347 | out_chan: | |
348 | ||
349 | return NULL; | |
350 | } | |
351 | ||
352 | static void pasemi_mac_setup_csrings(struct pasemi_mac *mac) | |
353 | { | |
354 | int i; | |
355 | mac->cs[0] = pasemi_mac_setup_csring(mac); | |
356 | if (mac->type == MAC_TYPE_XAUI) | |
357 | mac->cs[1] = pasemi_mac_setup_csring(mac); | |
358 | else | |
359 | mac->cs[1] = 0; | |
360 | ||
361 | for (i = 0; i < MAX_CS; i++) | |
362 | if (mac->cs[i]) | |
363 | mac->num_cs++; | |
364 | } | |
365 | ||
366 | static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring) | |
367 | { | |
368 | pasemi_dma_stop_chan(&csring->chan); | |
369 | pasemi_dma_free_flag(csring->events[0]); | |
370 | pasemi_dma_free_flag(csring->events[1]); | |
371 | pasemi_dma_free_ring(&csring->chan); | |
372 | pasemi_dma_free_chan(&csring->chan); | |
1724ac2e | 373 | pasemi_dma_free_fun(csring->fun); |
8d636d8b OJ |
374 | } |
375 | ||
5c15332b | 376 | static int pasemi_mac_setup_rx_resources(const struct net_device *dev) |
f5cd7872 OJ |
377 | { |
378 | struct pasemi_mac_rxring *ring; | |
379 | struct pasemi_mac *mac = netdev_priv(dev); | |
34c20624 | 380 | int chno; |
af289e80 | 381 | unsigned int cfg; |
f5cd7872 | 382 | |
34c20624 OJ |
383 | ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), |
384 | offsetof(struct pasemi_mac_rxring, chan)); | |
f5cd7872 | 385 | |
34c20624 OJ |
386 | if (!ring) { |
387 | dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); | |
388 | goto out_chan; | |
389 | } | |
390 | chno = ring->chan.chno; | |
f5cd7872 OJ |
391 | |
392 | spin_lock_init(&ring->lock); | |
393 | ||
021fa22e | 394 | ring->size = RX_RING_SIZE; |
fc9e4d2a | 395 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 OJ |
396 | RX_RING_SIZE, GFP_KERNEL); |
397 | ||
fc9e4d2a OJ |
398 | if (!ring->ring_info) |
399 | goto out_ring_info; | |
f5cd7872 OJ |
400 | |
401 | /* Allocate descriptors */ | |
34c20624 | 402 | if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) |
fc9e4d2a | 403 | goto out_ring_desc; |
f5cd7872 | 404 | |
ede23fa8 JP |
405 | ring->buffers = dma_zalloc_coherent(&mac->dma_pdev->dev, |
406 | RX_RING_SIZE * sizeof(u64), | |
407 | &ring->buf_dma, GFP_KERNEL); | |
f5cd7872 | 408 | if (!ring->buffers) |
34c20624 | 409 | goto out_ring_desc; |
f5cd7872 | 410 | |
34c20624 OJ |
411 | write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), |
412 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
f5cd7872 | 413 | |
34c20624 OJ |
414 | write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), |
415 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | | |
416 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 417 | |
5c15332b | 418 | cfg = PAS_DMA_RXCHAN_CFG_HBU(2); |
af289e80 OJ |
419 | |
420 | if (translation_enabled()) | |
421 | cfg |= PAS_DMA_RXCHAN_CFG_CTR; | |
422 | ||
34c20624 | 423 | write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); |
f5cd7872 | 424 | |
34c20624 OJ |
425 | write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), |
426 | PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); | |
f5cd7872 | 427 | |
34c20624 OJ |
428 | write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), |
429 | PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | | |
430 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 431 | |
5c15332b | 432 | cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | |
af289e80 OJ |
433 | PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | |
434 | PAS_DMA_RXINT_CFG_HEN; | |
435 | ||
436 | if (translation_enabled()) | |
437 | cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; | |
438 | ||
34c20624 | 439 | write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); |
c0efd52b | 440 | |
f5cd7872 OJ |
441 | ring->next_to_fill = 0; |
442 | ring->next_to_clean = 0; | |
72b05b99 | 443 | ring->mac = mac; |
f5cd7872 OJ |
444 | mac->rx = ring; |
445 | ||
446 | return 0; | |
447 | ||
fc9e4d2a OJ |
448 | out_ring_desc: |
449 | kfree(ring->ring_info); | |
450 | out_ring_info: | |
34c20624 OJ |
451 | pasemi_dma_free_chan(&ring->chan); |
452 | out_chan: | |
f5cd7872 OJ |
453 | return -ENOMEM; |
454 | } | |
455 | ||
72b05b99 | 456 | static struct pasemi_mac_txring * |
5c15332b | 457 | pasemi_mac_setup_tx_resources(const struct net_device *dev) |
f5cd7872 OJ |
458 | { |
459 | struct pasemi_mac *mac = netdev_priv(dev); | |
460 | u32 val; | |
f5cd7872 | 461 | struct pasemi_mac_txring *ring; |
af289e80 | 462 | unsigned int cfg; |
34c20624 | 463 | int chno; |
f5cd7872 | 464 | |
34c20624 OJ |
465 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), |
466 | offsetof(struct pasemi_mac_txring, chan)); | |
467 | ||
468 | if (!ring) { | |
469 | dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); | |
470 | goto out_chan; | |
471 | } | |
472 | ||
473 | chno = ring->chan.chno; | |
f5cd7872 OJ |
474 | |
475 | spin_lock_init(&ring->lock); | |
476 | ||
021fa22e | 477 | ring->size = TX_RING_SIZE; |
fc9e4d2a | 478 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 | 479 | TX_RING_SIZE, GFP_KERNEL); |
fc9e4d2a OJ |
480 | if (!ring->ring_info) |
481 | goto out_ring_info; | |
f5cd7872 OJ |
482 | |
483 | /* Allocate descriptors */ | |
34c20624 | 484 | if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) |
fc9e4d2a | 485 | goto out_ring_desc; |
f5cd7872 | 486 | |
34c20624 OJ |
487 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), |
488 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
489 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
fc9e4d2a | 490 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); |
f5cd7872 | 491 | |
34c20624 | 492 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); |
f5cd7872 | 493 | |
af289e80 OJ |
494 | cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | |
495 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
496 | PAS_DMA_TXCHAN_CFG_UP | | |
8d636d8b | 497 | PAS_DMA_TXCHAN_CFG_WT(4); |
af289e80 OJ |
498 | |
499 | if (translation_enabled()) | |
500 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
501 | ||
34c20624 | 502 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); |
f5cd7872 | 503 | |
021fa22e | 504 | ring->next_to_fill = 0; |
f5cd7872 | 505 | ring->next_to_clean = 0; |
72b05b99 | 506 | ring->mac = mac; |
f5cd7872 | 507 | |
72b05b99 | 508 | return ring; |
f5cd7872 | 509 | |
fc9e4d2a OJ |
510 | out_ring_desc: |
511 | kfree(ring->ring_info); | |
512 | out_ring_info: | |
34c20624 OJ |
513 | pasemi_dma_free_chan(&ring->chan); |
514 | out_chan: | |
72b05b99 | 515 | return NULL; |
f5cd7872 OJ |
516 | } |
517 | ||
72b05b99 | 518 | static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) |
f5cd7872 | 519 | { |
72b05b99 | 520 | struct pasemi_mac_txring *txring = tx_ring(mac); |
ad3c20d1 | 521 | unsigned int i, j; |
f5cd7872 | 522 | struct pasemi_mac_buffer *info; |
ad3c20d1 | 523 | dma_addr_t dmas[MAX_SKB_FRAGS+1]; |
7e9916e9 | 524 | int freed, nfrags; |
ad5da10a | 525 | int start, limit; |
fc9e4d2a | 526 | |
72b05b99 OJ |
527 | start = txring->next_to_clean; |
528 | limit = txring->next_to_fill; | |
ad5da10a OJ |
529 | |
530 | /* Compensate for when fill has wrapped and clean has not */ | |
531 | if (start > limit) | |
532 | limit += TX_RING_SIZE; | |
533 | ||
534 | for (i = start; i < limit; i += freed) { | |
72b05b99 | 535 | info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; |
fc9e4d2a | 536 | if (info->dma && info->skb) { |
7e9916e9 OJ |
537 | nfrags = skb_shinfo(info->skb)->nr_frags; |
538 | for (j = 0; j <= nfrags; j++) | |
72b05b99 OJ |
539 | dmas[j] = txring->ring_info[(i+1+j) & |
540 | (TX_RING_SIZE-1)].dma; | |
7e9916e9 OJ |
541 | freed = pasemi_mac_unmap_tx_skb(mac, nfrags, |
542 | info->skb, dmas); | |
ea5cdccc | 543 | } else { |
ad3c20d1 | 544 | freed = 2; |
ea5cdccc | 545 | } |
f5cd7872 OJ |
546 | } |
547 | ||
72b05b99 | 548 | kfree(txring->ring_info); |
34c20624 OJ |
549 | pasemi_dma_free_chan(&txring->chan); |
550 | ||
f5cd7872 OJ |
551 | } |
552 | ||
ef1ea0b4 | 553 | static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac) |
f5cd7872 | 554 | { |
72b05b99 | 555 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
f5cd7872 OJ |
556 | unsigned int i; |
557 | struct pasemi_mac_buffer *info; | |
f5cd7872 OJ |
558 | |
559 | for (i = 0; i < RX_RING_SIZE; i++) { | |
72b05b99 | 560 | info = &RX_DESC_INFO(rx, i); |
fc9e4d2a OJ |
561 | if (info->skb && info->dma) { |
562 | pci_unmap_single(mac->dma_pdev, | |
563 | info->dma, | |
564 | info->skb->len, | |
565 | PCI_DMA_FROMDEVICE); | |
566 | dev_kfree_skb_any(info->skb); | |
f5cd7872 | 567 | } |
fc9e4d2a OJ |
568 | info->dma = 0; |
569 | info->skb = NULL; | |
f5cd7872 OJ |
570 | } |
571 | ||
fc9e4d2a | 572 | for (i = 0; i < RX_RING_SIZE; i++) |
ef1ea0b4 OJ |
573 | RX_BUFF(rx, i) = 0; |
574 | } | |
575 | ||
576 | static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) | |
577 | { | |
578 | pasemi_mac_free_rx_buffers(mac); | |
fc9e4d2a | 579 | |
f5cd7872 | 580 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), |
72b05b99 | 581 | rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); |
f5cd7872 | 582 | |
72b05b99 | 583 | kfree(rx_ring(mac)->ring_info); |
34c20624 | 584 | pasemi_dma_free_chan(&rx_ring(mac)->chan); |
f5cd7872 OJ |
585 | mac->rx = NULL; |
586 | } | |
587 | ||
5c6239c8 | 588 | static void pasemi_mac_replenish_rx_ring(struct net_device *dev, |
5c15332b | 589 | const int limit) |
f5cd7872 | 590 | { |
5c15332b | 591 | const struct pasemi_mac *mac = netdev_priv(dev); |
72b05b99 | 592 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
b5254eee | 593 | int fill, count; |
f5cd7872 | 594 | |
cd4ceb24 | 595 | if (limit <= 0) |
f5cd7872 OJ |
596 | return; |
597 | ||
72b05b99 | 598 | fill = rx_ring(mac)->next_to_fill; |
928773c2 | 599 | for (count = 0; count < limit; count++) { |
72b05b99 OJ |
600 | struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); |
601 | u64 *buff = &RX_BUFF(rx, fill); | |
f5cd7872 OJ |
602 | struct sk_buff *skb; |
603 | dma_addr_t dma; | |
604 | ||
fc9e4d2a OJ |
605 | /* Entry in use? */ |
606 | WARN_ON(*buff); | |
607 | ||
dae2e9f4 | 608 | skb = netdev_alloc_skb(dev, mac->bufsz); |
5d894944 | 609 | skb_reserve(skb, LOCAL_SKB_ALIGN); |
f5cd7872 | 610 | |
9f05cfe2 | 611 | if (unlikely(!skb)) |
f5cd7872 | 612 | break; |
f5cd7872 | 613 | |
8dc121a4 | 614 | dma = pci_map_single(mac->dma_pdev, skb->data, |
ef1ea0b4 | 615 | mac->bufsz - LOCAL_SKB_ALIGN, |
f5cd7872 OJ |
616 | PCI_DMA_FROMDEVICE); |
617 | ||
8d8bb39b | 618 | if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) { |
f5cd7872 | 619 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
620 | break; |
621 | } | |
622 | ||
623 | info->skb = skb; | |
624 | info->dma = dma; | |
ef1ea0b4 | 625 | *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma); |
fc9e4d2a | 626 | fill++; |
f5cd7872 OJ |
627 | } |
628 | ||
629 | wmb(); | |
630 | ||
34c20624 | 631 | write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); |
f5cd7872 | 632 | |
72b05b99 | 633 | rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & |
b5254eee | 634 | (RX_RING_SIZE - 1); |
f5cd7872 OJ |
635 | } |
636 | ||
5c15332b | 637 | static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) |
1b0335ea | 638 | { |
906674ab | 639 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
52a94351 | 640 | unsigned int reg, pcnt; |
1b0335ea OJ |
641 | /* Re-enable packet count interrupts: finally |
642 | * ack the packet count interrupt we got in rx_intr. | |
643 | */ | |
644 | ||
906674ab | 645 | pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 646 | |
52a94351 | 647 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea | 648 | |
906674ab OJ |
649 | if (*rx->chan.status & PAS_STATUS_TIMER) |
650 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
651 | ||
34c20624 | 652 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); |
1b0335ea OJ |
653 | } |
654 | ||
5c15332b | 655 | static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) |
1b0335ea | 656 | { |
52a94351 | 657 | unsigned int reg, pcnt; |
1b0335ea OJ |
658 | |
659 | /* Re-enable packet count interrupts */ | |
34c20624 | 660 | pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 661 | |
52a94351 | 662 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea | 663 | |
34c20624 | 664 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); |
1b0335ea OJ |
665 | } |
666 | ||
667 | ||
5c15332b OJ |
668 | static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, |
669 | const u64 macrx) | |
69c29d89 OJ |
670 | { |
671 | unsigned int rcmdsta, ccmdsta; | |
34c20624 | 672 | struct pasemi_dmachan *chan = &rx_ring(mac)->chan; |
69c29d89 OJ |
673 | |
674 | if (!netif_msg_rx_err(mac)) | |
675 | return; | |
676 | ||
34c20624 OJ |
677 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
678 | ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); | |
69c29d89 | 679 | |
fe333321 | 680 | printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n", |
34c20624 | 681 | macrx, *chan->status); |
69c29d89 OJ |
682 | |
683 | printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", | |
684 | rcmdsta, ccmdsta); | |
685 | } | |
686 | ||
5c15332b OJ |
687 | static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, |
688 | const u64 mactx) | |
69c29d89 OJ |
689 | { |
690 | unsigned int cmdsta; | |
34c20624 | 691 | struct pasemi_dmachan *chan = &tx_ring(mac)->chan; |
69c29d89 OJ |
692 | |
693 | if (!netif_msg_tx_err(mac)) | |
694 | return; | |
695 | ||
34c20624 | 696 | cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); |
69c29d89 | 697 | |
fe333321 IM |
698 | printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\ |
699 | "tx status 0x%016llx\n", mactx, *chan->status); | |
69c29d89 OJ |
700 | |
701 | printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); | |
702 | } | |
703 | ||
5c15332b OJ |
704 | static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, |
705 | const int limit) | |
f5cd7872 | 706 | { |
5c15332b | 707 | const struct pasemi_dmachan *chan = &rx->chan; |
72b05b99 | 708 | struct pasemi_mac *mac = rx->mac; |
5c15332b | 709 | struct pci_dev *pdev = mac->dma_pdev; |
cd4ceb24 | 710 | unsigned int n; |
5c15332b | 711 | int count, buf_index, tot_bytes, packets; |
cd4ceb24 OJ |
712 | struct pasemi_mac_buffer *info; |
713 | struct sk_buff *skb; | |
b5254eee | 714 | unsigned int len; |
5c15332b | 715 | u64 macrx, eval; |
cd4ceb24 | 716 | dma_addr_t dma; |
5c15332b OJ |
717 | |
718 | tot_bytes = 0; | |
719 | packets = 0; | |
f5cd7872 | 720 | |
72b05b99 | 721 | spin_lock(&rx->lock); |
f5cd7872 | 722 | |
72b05b99 | 723 | n = rx->next_to_clean; |
f5cd7872 | 724 | |
72b05b99 | 725 | prefetch(&RX_DESC(rx, n)); |
b5254eee OJ |
726 | |
727 | for (count = 0; count < limit; count++) { | |
72b05b99 | 728 | macrx = RX_DESC(rx, n); |
5c15332b | 729 | prefetch(&RX_DESC(rx, n+4)); |
f5cd7872 | 730 | |
69c29d89 | 731 | if ((macrx & XCT_MACRX_E) || |
34c20624 | 732 | (*chan->status & PAS_STATUS_ERROR)) |
69c29d89 OJ |
733 | pasemi_mac_rx_error(mac, macrx); |
734 | ||
cd4ceb24 | 735 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
736 | break; |
737 | ||
f5cd7872 OJ |
738 | info = NULL; |
739 | ||
b5254eee | 740 | BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); |
f5cd7872 | 741 | |
72b05b99 | 742 | eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> |
b5254eee OJ |
743 | XCT_RXRES_8B_EVAL_S; |
744 | buf_index = eval-1; | |
745 | ||
72b05b99 OJ |
746 | dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); |
747 | info = &RX_DESC_INFO(rx, buf_index); | |
fc9e4d2a | 748 | |
9f05cfe2 | 749 | skb = info->skb; |
f5cd7872 | 750 | |
5c15332b | 751 | prefetch_skb(skb); |
f5cd7872 | 752 | |
cd4ceb24 | 753 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 754 | |
ef1ea0b4 | 755 | pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN, |
5c15332b | 756 | PCI_DMA_FROMDEVICE); |
32bee776 OJ |
757 | |
758 | if (macrx & XCT_MACRX_CRC) { | |
759 | /* CRC error flagged */ | |
760 | mac->netdev->stats.rx_errors++; | |
761 | mac->netdev->stats.rx_crc_errors++; | |
4352d826 | 762 | /* No need to free skb, it'll be reused */ |
32bee776 OJ |
763 | goto next; |
764 | } | |
765 | ||
5d894944 | 766 | info->skb = NULL; |
ad5da10a | 767 | info->dma = 0; |
fc9e4d2a | 768 | |
26fcfa95 | 769 | if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { |
38bf3184 | 770 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
cd4ceb24 | 771 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 | 772 | XCT_MACRX_CSUM_S; |
ea5cdccc | 773 | } else { |
bc8acf2c | 774 | skb_checksum_none_assert(skb); |
ea5cdccc | 775 | } |
f5cd7872 | 776 | |
5c15332b OJ |
777 | packets++; |
778 | tot_bytes += len; | |
779 | ||
780 | /* Don't include CRC */ | |
781 | skb_put(skb, len-4); | |
f5cd7872 | 782 | |
26fcfa95 | 783 | skb->protocol = eth_type_trans(skb, mac->netdev); |
a4f9cdb2 | 784 | napi_gro_receive(&mac->napi, skb); |
f5cd7872 | 785 | |
32bee776 | 786 | next: |
72b05b99 OJ |
787 | RX_DESC(rx, n) = 0; |
788 | RX_DESC(rx, n+1) = 0; | |
cd4ceb24 | 789 | |
ad5da10a OJ |
790 | /* Need to zero it out since hardware doesn't, since the |
791 | * replenish loop uses it to tell when it's done. | |
792 | */ | |
72b05b99 | 793 | RX_BUFF(rx, buf_index) = 0; |
ad5da10a | 794 | |
b5254eee | 795 | n += 4; |
f5cd7872 OJ |
796 | } |
797 | ||
9a50bebd OJ |
798 | if (n > RX_RING_SIZE) { |
799 | /* Errata 5971 workaround: L2 target of headers */ | |
34c20624 | 800 | write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); |
9a50bebd OJ |
801 | n &= (RX_RING_SIZE-1); |
802 | } | |
b5254eee | 803 | |
72b05b99 | 804 | rx_ring(mac)->next_to_clean = n; |
b5254eee OJ |
805 | |
806 | /* Increase is in number of 16-byte entries, and since each descriptor | |
807 | * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with | |
808 | * count*2. | |
809 | */ | |
34c20624 | 810 | write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); |
b5254eee OJ |
811 | |
812 | pasemi_mac_replenish_rx_ring(mac->netdev, count); | |
f5cd7872 | 813 | |
5c15332b OJ |
814 | mac->netdev->stats.rx_bytes += tot_bytes; |
815 | mac->netdev->stats.rx_packets += packets; | |
816 | ||
72b05b99 | 817 | spin_unlock(&rx_ring(mac)->lock); |
f5cd7872 OJ |
818 | |
819 | return count; | |
820 | } | |
821 | ||
ad3c20d1 OJ |
822 | /* Can't make this too large or we blow the kernel stack limits */ |
823 | #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) | |
824 | ||
72b05b99 | 825 | static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) |
f5cd7872 | 826 | { |
34c20624 | 827 | struct pasemi_dmachan *chan = &txring->chan; |
72b05b99 | 828 | struct pasemi_mac *mac = txring->mac; |
ad3c20d1 | 829 | int i, j; |
ad5da10a OJ |
830 | unsigned int start, descr_count, buf_count, batch_limit; |
831 | unsigned int ring_limit; | |
02df6cfa | 832 | unsigned int total_count; |
ca7e235f | 833 | unsigned long flags; |
ad3c20d1 OJ |
834 | struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; |
835 | dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; | |
7e9916e9 OJ |
836 | int nf[TX_CLEAN_BATCHSIZE]; |
837 | int nr_frags; | |
f5cd7872 | 838 | |
02df6cfa | 839 | total_count = 0; |
ad5da10a | 840 | batch_limit = TX_CLEAN_BATCHSIZE; |
02df6cfa | 841 | restart: |
72b05b99 | 842 | spin_lock_irqsave(&txring->lock, flags); |
f5cd7872 | 843 | |
72b05b99 OJ |
844 | start = txring->next_to_clean; |
845 | ring_limit = txring->next_to_fill; | |
ad5da10a | 846 | |
7e9916e9 OJ |
847 | prefetch(&TX_DESC_INFO(txring, start+1).skb); |
848 | ||
ad5da10a OJ |
849 | /* Compensate for when fill has wrapped but clean has not */ |
850 | if (start > ring_limit) | |
851 | ring_limit += TX_RING_SIZE; | |
02df6cfa | 852 | |
ad3c20d1 OJ |
853 | buf_count = 0; |
854 | descr_count = 0; | |
f5cd7872 | 855 | |
ad3c20d1 | 856 | for (i = start; |
ad5da10a | 857 | descr_count < batch_limit && i < ring_limit; |
ad3c20d1 | 858 | i += buf_count) { |
72b05b99 | 859 | u64 mactx = TX_DESC(txring, i); |
ad5da10a | 860 | struct sk_buff *skb; |
ad3c20d1 | 861 | |
fc9e4d2a | 862 | if ((mactx & XCT_MACTX_E) || |
34c20624 | 863 | (*chan->status & PAS_STATUS_ERROR)) |
fc9e4d2a | 864 | pasemi_mac_tx_error(mac, mactx); |
69c29d89 | 865 | |
8d636d8b OJ |
866 | /* Skip over control descriptors */ |
867 | if (!(mactx & XCT_MACTX_LLEN_M)) { | |
868 | TX_DESC(txring, i) = 0; | |
869 | TX_DESC(txring, i+1) = 0; | |
870 | buf_count = 2; | |
871 | continue; | |
872 | } | |
873 | ||
874 | skb = TX_DESC_INFO(txring, i+1).skb; | |
875 | nr_frags = TX_DESC_INFO(txring, i).dma; | |
876 | ||
fc9e4d2a | 877 | if (unlikely(mactx & XCT_MACTX_O)) |
02df6cfa | 878 | /* Not yet transmitted */ |
f5cd7872 OJ |
879 | break; |
880 | ||
7e9916e9 OJ |
881 | buf_count = 2 + nr_frags; |
882 | /* Since we always fill with an even number of entries, make | |
883 | * sure we skip any unused one at the end as well. | |
884 | */ | |
885 | if (buf_count & 1) | |
886 | buf_count++; | |
ad3c20d1 | 887 | |
7e9916e9 | 888 | for (j = 0; j <= nr_frags; j++) |
72b05b99 | 889 | dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; |
ad3c20d1 | 890 | |
7e9916e9 OJ |
891 | skbs[descr_count] = skb; |
892 | nf[descr_count] = nr_frags; | |
893 | ||
72b05b99 OJ |
894 | TX_DESC(txring, i) = 0; |
895 | TX_DESC(txring, i+1) = 0; | |
fc9e4d2a | 896 | |
ad3c20d1 | 897 | descr_count++; |
f5cd7872 | 898 | } |
72b05b99 | 899 | txring->next_to_clean = i & (TX_RING_SIZE-1); |
ad3c20d1 | 900 | |
72b05b99 | 901 | spin_unlock_irqrestore(&txring->lock, flags); |
0ce68c74 OJ |
902 | netif_wake_queue(mac->netdev); |
903 | ||
ad3c20d1 | 904 | for (i = 0; i < descr_count; i++) |
7e9916e9 | 905 | pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); |
02df6cfa | 906 | |
ad3c20d1 | 907 | total_count += descr_count; |
02df6cfa OJ |
908 | |
909 | /* If the batch was full, try to clean more */ | |
ad5da10a | 910 | if (descr_count == batch_limit) |
02df6cfa OJ |
911 | goto restart; |
912 | ||
913 | return total_count; | |
f5cd7872 OJ |
914 | } |
915 | ||
916 | ||
917 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
918 | { | |
5c15332b | 919 | const struct pasemi_mac_rxring *rxring = data; |
34c20624 | 920 | struct pasemi_mac *mac = rxring->mac; |
5c15332b | 921 | const struct pasemi_dmachan *chan = &rxring->chan; |
f5cd7872 OJ |
922 | unsigned int reg; |
923 | ||
34c20624 | 924 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
925 | return IRQ_NONE; |
926 | ||
6dfa7522 OJ |
927 | /* Don't reset packet count so it won't fire again but clear |
928 | * all others. | |
929 | */ | |
930 | ||
6dfa7522 | 931 | reg = 0; |
34c20624 | 932 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 933 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; |
34c20624 | 934 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 935 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; |
f5cd7872 | 936 | |
288379f0 | 937 | napi_schedule(&mac->napi); |
6dfa7522 | 938 | |
34c20624 | 939 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); |
f5cd7872 OJ |
940 | |
941 | return IRQ_HANDLED; | |
942 | } | |
943 | ||
61cec3bd OJ |
944 | #define TX_CLEAN_INTERVAL HZ |
945 | ||
946 | static void pasemi_mac_tx_timer(unsigned long data) | |
947 | { | |
948 | struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data; | |
949 | struct pasemi_mac *mac = txring->mac; | |
950 | ||
951 | pasemi_mac_clean_tx(txring); | |
952 | ||
953 | mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); | |
954 | ||
955 | pasemi_mac_restart_tx_intr(mac); | |
956 | } | |
957 | ||
f5cd7872 OJ |
958 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) |
959 | { | |
72b05b99 | 960 | struct pasemi_mac_txring *txring = data; |
5c15332b | 961 | const struct pasemi_dmachan *chan = &txring->chan; |
61cec3bd OJ |
962 | struct pasemi_mac *mac = txring->mac; |
963 | unsigned int reg; | |
f5cd7872 | 964 | |
34c20624 | 965 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
966 | return IRQ_NONE; |
967 | ||
61cec3bd | 968 | reg = 0; |
6dfa7522 | 969 | |
34c20624 | 970 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 971 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; |
34c20624 | 972 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 973 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; |
f5cd7872 | 974 | |
61cec3bd OJ |
975 | mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); |
976 | ||
288379f0 | 977 | napi_schedule(&mac->napi); |
61cec3bd OJ |
978 | |
979 | if (reg) | |
980 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); | |
f5cd7872 | 981 | |
f5cd7872 OJ |
982 | return IRQ_HANDLED; |
983 | } | |
984 | ||
bb6e9590 OJ |
985 | static void pasemi_adjust_link(struct net_device *dev) |
986 | { | |
987 | struct pasemi_mac *mac = netdev_priv(dev); | |
988 | int msg; | |
989 | unsigned int flags; | |
990 | unsigned int new_flags; | |
991 | ||
80721e7f | 992 | if (!dev->phydev->link) { |
bb6e9590 OJ |
993 | /* If no link, MAC speed settings don't matter. Just report |
994 | * link down and return. | |
995 | */ | |
996 | if (mac->link && netif_msg_link(mac)) | |
997 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
998 | ||
999 | netif_carrier_off(dev); | |
b0cd2f90 | 1000 | pasemi_mac_intf_disable(mac); |
bb6e9590 OJ |
1001 | mac->link = 0; |
1002 | ||
1003 | return; | |
b0cd2f90 OJ |
1004 | } else { |
1005 | pasemi_mac_intf_enable(mac); | |
bb6e9590 | 1006 | netif_carrier_on(dev); |
b0cd2f90 | 1007 | } |
bb6e9590 | 1008 | |
a85b9422 | 1009 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
bb6e9590 OJ |
1010 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
1011 | PAS_MAC_CFG_PCFG_TSR_M); | |
1012 | ||
80721e7f | 1013 | if (!dev->phydev->duplex) |
bb6e9590 OJ |
1014 | new_flags |= PAS_MAC_CFG_PCFG_HD; |
1015 | ||
80721e7f | 1016 | switch (dev->phydev->speed) { |
bb6e9590 OJ |
1017 | case 1000: |
1018 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
1019 | PAS_MAC_CFG_PCFG_TSR_1G; | |
1020 | break; | |
1021 | case 100: | |
1022 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
1023 | PAS_MAC_CFG_PCFG_TSR_100M; | |
1024 | break; | |
1025 | case 10: | |
1026 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
1027 | PAS_MAC_CFG_PCFG_TSR_10M; | |
1028 | break; | |
1029 | default: | |
80721e7f | 1030 | printk("Unsupported speed %d\n", dev->phydev->speed); |
bb6e9590 OJ |
1031 | } |
1032 | ||
1033 | /* Print on link or speed/duplex change */ | |
80721e7f | 1034 | msg = mac->link != dev->phydev->link || flags != new_flags; |
bb6e9590 | 1035 | |
80721e7f PR |
1036 | mac->duplex = dev->phydev->duplex; |
1037 | mac->speed = dev->phydev->speed; | |
1038 | mac->link = dev->phydev->link; | |
bb6e9590 OJ |
1039 | |
1040 | if (new_flags != flags) | |
a85b9422 | 1041 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
bb6e9590 OJ |
1042 | |
1043 | if (msg && netif_msg_link(mac)) | |
1044 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
1045 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
1046 | } | |
1047 | ||
1048 | static int pasemi_mac_phy_init(struct net_device *dev) | |
1049 | { | |
1050 | struct pasemi_mac *mac = netdev_priv(dev); | |
1051 | struct device_node *dn, *phy_dn; | |
1052 | struct phy_device *phydev; | |
bb6e9590 OJ |
1053 | |
1054 | dn = pci_device_to_OF_node(mac->pdev); | |
1dd2d06c | 1055 | phy_dn = of_parse_phandle(dn, "phy-handle", 0); |
bb6e9590 OJ |
1056 | of_node_put(phy_dn); |
1057 | ||
1058 | mac->link = 0; | |
1059 | mac->speed = 0; | |
1060 | mac->duplex = -1; | |
1061 | ||
1dd2d06c GL |
1062 | phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0, |
1063 | PHY_INTERFACE_MODE_SGMII); | |
bb6e9590 | 1064 | |
beb5ac20 | 1065 | if (!phydev) { |
bb6e9590 | 1066 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); |
beb5ac20 | 1067 | return -ENODEV; |
bb6e9590 OJ |
1068 | } |
1069 | ||
bb6e9590 | 1070 | return 0; |
bb6e9590 OJ |
1071 | } |
1072 | ||
1073 | ||
f5cd7872 OJ |
1074 | static int pasemi_mac_open(struct net_device *dev) |
1075 | { | |
1076 | struct pasemi_mac *mac = netdev_priv(dev); | |
1077 | unsigned int flags; | |
e37c772e | 1078 | int i, ret; |
f5cd7872 OJ |
1079 | |
1080 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | |
1081 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
1082 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
1083 | ||
a85b9422 | 1084 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
f5cd7872 | 1085 | |
f5cd7872 OJ |
1086 | ret = pasemi_mac_setup_rx_resources(dev); |
1087 | if (ret) | |
1088 | goto out_rx_resources; | |
1089 | ||
34c20624 | 1090 | mac->tx = pasemi_mac_setup_tx_resources(dev); |
72b05b99 OJ |
1091 | |
1092 | if (!mac->tx) | |
1093 | goto out_tx_ring; | |
f5cd7872 | 1094 | |
1724ac2e OJ |
1095 | /* We might already have allocated rings in case mtu was changed |
1096 | * before interface was brought up. | |
1097 | */ | |
1098 | if (dev->mtu > 1500 && !mac->num_cs) { | |
8d636d8b OJ |
1099 | pasemi_mac_setup_csrings(mac); |
1100 | if (!mac->num_cs) | |
1101 | goto out_tx_ring; | |
1102 | } | |
1103 | ||
e37c772e OJ |
1104 | /* Zero out rmon counters */ |
1105 | for (i = 0; i < 32; i++) | |
1106 | write_mac_reg(mac, PAS_MAC_RMON(i), 0); | |
1107 | ||
906674ab OJ |
1108 | /* 0x3ff with 33MHz clock is about 31us */ |
1109 | write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, | |
1110 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); | |
1111 | ||
34c20624 | 1112 | write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), |
28ae79f5 | 1113 | PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); |
34c20624 OJ |
1114 | |
1115 | write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), | |
61cec3bd | 1116 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); |
34c20624 | 1117 | |
a85b9422 | 1118 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
34c20624 OJ |
1119 | PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | |
1120 | PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); | |
f5cd7872 OJ |
1121 | |
1122 | /* enable rx if */ | |
34c20624 OJ |
1123 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
1124 | PAS_DMA_RXINT_RCMDSTA_EN | | |
1125 | PAS_DMA_RXINT_RCMDSTA_DROPS_M | | |
1126 | PAS_DMA_RXINT_RCMDSTA_BP | | |
1127 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1128 | PAS_DMA_RXINT_RCMDSTA_BT); | |
f5cd7872 OJ |
1129 | |
1130 | /* enable rx channel */ | |
34c20624 OJ |
1131 | pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | |
1132 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1133 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1134 | PAS_DMA_RXCHAN_CCMDSTA_DT); | |
f5cd7872 OJ |
1135 | |
1136 | /* enable tx channel */ | |
34c20624 OJ |
1137 | pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | |
1138 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
1139 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
1140 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
f5cd7872 | 1141 | |
928773c2 | 1142 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); |
f5cd7872 | 1143 | |
34c20624 OJ |
1144 | write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), |
1145 | RX_RING_SIZE>>1); | |
b5254eee | 1146 | |
72b05b99 OJ |
1147 | /* Clear out any residual packet count state from firmware */ |
1148 | pasemi_mac_restart_rx_intr(mac); | |
1149 | pasemi_mac_restart_tx_intr(mac); | |
1150 | ||
b0cd2f90 | 1151 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; |
36033766 OJ |
1152 | |
1153 | if (mac->type == MAC_TYPE_GMAC) | |
1154 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
1155 | else | |
1156 | flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; | |
1157 | ||
1158 | /* Enable interface in MAC */ | |
1159 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
1160 | ||
bb6e9590 | 1161 | ret = pasemi_mac_phy_init(dev); |
b0cd2f90 OJ |
1162 | if (ret) { |
1163 | /* Since we won't get link notification, just enable RX */ | |
1164 | pasemi_mac_intf_enable(mac); | |
1165 | if (mac->type == MAC_TYPE_GMAC) { | |
1166 | /* Warn for missing PHY on SGMII (1Gig) ports */ | |
1167 | dev_warn(&mac->pdev->dev, | |
1168 | "PHY init failed: %d.\n", ret); | |
1169 | dev_warn(&mac->pdev->dev, | |
1170 | "Defaulting to 1Gbit full duplex\n"); | |
1171 | } | |
8304b633 | 1172 | } |
bb6e9590 | 1173 | |
f5cd7872 | 1174 | netif_start_queue(dev); |
bea3348e | 1175 | napi_enable(&mac->napi); |
f5cd7872 | 1176 | |
72b05b99 OJ |
1177 | snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", |
1178 | dev->name); | |
771f7404 | 1179 | |
78874271 | 1180 | ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, 0, |
72b05b99 | 1181 | mac->tx_irq_name, mac->tx); |
f5cd7872 OJ |
1182 | if (ret) { |
1183 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1184 | mac->tx->chan.irq, ret); |
f5cd7872 OJ |
1185 | goto out_tx_int; |
1186 | } | |
1187 | ||
72b05b99 OJ |
1188 | snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", |
1189 | dev->name); | |
1190 | ||
78874271 | 1191 | ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, 0, |
34c20624 | 1192 | mac->rx_irq_name, mac->rx); |
f5cd7872 OJ |
1193 | if (ret) { |
1194 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1195 | mac->rx->chan.irq, ret); |
f5cd7872 OJ |
1196 | goto out_rx_int; |
1197 | } | |
1198 | ||
80721e7f PR |
1199 | if (dev->phydev) |
1200 | phy_start(dev->phydev); | |
bb6e9590 | 1201 | |
187d6785 VT |
1202 | setup_timer(&mac->tx->clean_timer, pasemi_mac_tx_timer, |
1203 | (unsigned long)mac->tx); | |
1204 | mod_timer(&mac->tx->clean_timer, jiffies + HZ); | |
61cec3bd | 1205 | |
f5cd7872 OJ |
1206 | return 0; |
1207 | ||
1208 | out_rx_int: | |
34c20624 | 1209 | free_irq(mac->tx->chan.irq, mac->tx); |
f5cd7872 | 1210 | out_tx_int: |
bea3348e | 1211 | napi_disable(&mac->napi); |
f5cd7872 | 1212 | netif_stop_queue(dev); |
72b05b99 OJ |
1213 | out_tx_ring: |
1214 | if (mac->tx) | |
1215 | pasemi_mac_free_tx_resources(mac); | |
1216 | pasemi_mac_free_rx_resources(mac); | |
f5cd7872 OJ |
1217 | out_rx_resources: |
1218 | ||
1219 | return ret; | |
1220 | } | |
1221 | ||
1222 | #define MAX_RETRIES 5000 | |
1223 | ||
ef1ea0b4 OJ |
1224 | static void pasemi_mac_pause_txchan(struct pasemi_mac *mac) |
1225 | { | |
1226 | unsigned int sta, retries; | |
1227 | int txch = tx_ring(mac)->chan.chno; | |
1228 | ||
1229 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), | |
1230 | PAS_DMA_TXCHAN_TCMDSTA_ST); | |
1231 | ||
1232 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1233 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); | |
1234 | if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) | |
1235 | break; | |
1236 | cond_resched(); | |
1237 | } | |
1238 | ||
1239 | if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) | |
1240 | dev_err(&mac->dma_pdev->dev, | |
1241 | "Failed to stop tx channel, tcmdsta %08x\n", sta); | |
1242 | ||
1243 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); | |
1244 | } | |
1245 | ||
1246 | static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac) | |
1247 | { | |
1248 | unsigned int sta, retries; | |
1249 | int rxch = rx_ring(mac)->chan.chno; | |
1250 | ||
1251 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), | |
1252 | PAS_DMA_RXCHAN_CCMDSTA_ST); | |
1253 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1254 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); | |
1255 | if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) | |
1256 | break; | |
1257 | cond_resched(); | |
1258 | } | |
1259 | ||
1260 | if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) | |
1261 | dev_err(&mac->dma_pdev->dev, | |
1262 | "Failed to stop rx channel, ccmdsta 08%x\n", sta); | |
1263 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); | |
1264 | } | |
1265 | ||
1266 | static void pasemi_mac_pause_rxint(struct pasemi_mac *mac) | |
1267 | { | |
1268 | unsigned int sta, retries; | |
1269 | ||
1270 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1271 | PAS_DMA_RXINT_RCMDSTA_ST); | |
1272 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1273 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1274 | if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) | |
1275 | break; | |
1276 | cond_resched(); | |
1277 | } | |
1278 | ||
1279 | if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) | |
1280 | dev_err(&mac->dma_pdev->dev, | |
1281 | "Failed to stop rx interface, rcmdsta %08x\n", sta); | |
1282 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
1283 | } | |
1284 | ||
f5cd7872 OJ |
1285 | static int pasemi_mac_close(struct net_device *dev) |
1286 | { | |
1287 | struct pasemi_mac *mac = netdev_priv(dev); | |
9e81d331 | 1288 | unsigned int sta; |
8d636d8b | 1289 | int rxch, txch, i; |
34c20624 OJ |
1290 | |
1291 | rxch = rx_ring(mac)->chan.chno; | |
1292 | txch = tx_ring(mac)->chan.chno; | |
f5cd7872 | 1293 | |
80721e7f PR |
1294 | if (dev->phydev) { |
1295 | phy_stop(dev->phydev); | |
1296 | phy_disconnect(dev->phydev); | |
bb6e9590 OJ |
1297 | } |
1298 | ||
61cec3bd OJ |
1299 | del_timer_sync(&mac->tx->clean_timer); |
1300 | ||
f5cd7872 | 1301 | netif_stop_queue(dev); |
bea3348e | 1302 | napi_disable(&mac->napi); |
f5cd7872 | 1303 | |
34c20624 | 1304 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 OJ |
1305 | if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | |
1306 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1307 | PAS_DMA_RXINT_RCMDSTA_BT)) | |
1308 | printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); | |
1309 | ||
34c20624 | 1310 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 OJ |
1311 | if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | |
1312 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1313 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1314 | PAS_DMA_RXCHAN_CCMDSTA_DT)) | |
1315 | printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); | |
1316 | ||
34c20624 | 1317 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); |
72b05b99 OJ |
1318 | if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | |
1319 | PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) | |
9e81d331 OJ |
1320 | printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); |
1321 | ||
f5cd7872 | 1322 | /* Clean out any pending buffers */ |
72b05b99 OJ |
1323 | pasemi_mac_clean_tx(tx_ring(mac)); |
1324 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
f5cd7872 | 1325 | |
ef1ea0b4 OJ |
1326 | pasemi_mac_pause_txchan(mac); |
1327 | pasemi_mac_pause_rxint(mac); | |
1328 | pasemi_mac_pause_rxchan(mac); | |
1145d954 | 1329 | pasemi_mac_intf_disable(mac); |
f5cd7872 | 1330 | |
34c20624 OJ |
1331 | free_irq(mac->tx->chan.irq, mac->tx); |
1332 | free_irq(mac->rx->chan.irq, mac->rx); | |
f5cd7872 | 1333 | |
1724ac2e | 1334 | for (i = 0; i < mac->num_cs; i++) { |
8d636d8b | 1335 | pasemi_mac_free_csring(mac->cs[i]); |
1724ac2e OJ |
1336 | mac->cs[i] = NULL; |
1337 | } | |
1338 | ||
1339 | mac->num_cs = 0; | |
8d636d8b | 1340 | |
f5cd7872 | 1341 | /* Free resources */ |
72b05b99 OJ |
1342 | pasemi_mac_free_rx_resources(mac); |
1343 | pasemi_mac_free_tx_resources(mac); | |
f5cd7872 OJ |
1344 | |
1345 | return 0; | |
1346 | } | |
1347 | ||
8d636d8b OJ |
1348 | static void pasemi_mac_queue_csdesc(const struct sk_buff *skb, |
1349 | const dma_addr_t *map, | |
1350 | const unsigned int *map_size, | |
1351 | struct pasemi_mac_txring *txring, | |
1352 | struct pasemi_mac_csring *csring) | |
1353 | { | |
1354 | u64 fund; | |
1355 | dma_addr_t cs_dest; | |
1356 | const int nh_off = skb_network_offset(skb); | |
1357 | const int nh_len = skb_network_header_len(skb); | |
1358 | const int nfrags = skb_shinfo(skb)->nr_frags; | |
1359 | int cs_size, i, fill, hdr, cpyhdr, evt; | |
1360 | dma_addr_t csdma; | |
1361 | ||
1362 | fund = XCT_FUN_ST | XCT_FUN_RR_8BRES | | |
1363 | XCT_FUN_O | XCT_FUN_FUN(csring->fun) | | |
1364 | XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) | | |
1365 | XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE; | |
1366 | ||
1367 | switch (ip_hdr(skb)->protocol) { | |
1368 | case IPPROTO_TCP: | |
1369 | fund |= XCT_FUN_SIG_TCP4; | |
1370 | /* TCP checksum is 16 bytes into the header */ | |
1371 | cs_dest = map[0] + skb_transport_offset(skb) + 16; | |
1372 | break; | |
1373 | case IPPROTO_UDP: | |
1374 | fund |= XCT_FUN_SIG_UDP4; | |
1375 | /* UDP checksum is 6 bytes into the header */ | |
1376 | cs_dest = map[0] + skb_transport_offset(skb) + 6; | |
1377 | break; | |
1378 | default: | |
1379 | BUG(); | |
1380 | } | |
1381 | ||
1382 | /* Do the checksum offloaded */ | |
1383 | fill = csring->next_to_fill; | |
1384 | hdr = fill; | |
1385 | ||
1386 | CS_DESC(csring, fill++) = fund; | |
1387 | /* Room for 8BRES. Checksum result is really 2 bytes into it */ | |
1388 | csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2; | |
1389 | CS_DESC(csring, fill++) = 0; | |
1390 | ||
1391 | CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off); | |
1392 | for (i = 1; i <= nfrags; i++) | |
1393 | CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); | |
1394 | ||
1395 | fill += i; | |
1396 | if (fill & 1) | |
1397 | fill++; | |
1398 | ||
1399 | /* Copy the result into the TCP packet */ | |
1400 | cpyhdr = fill; | |
1401 | CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) | | |
1402 | XCT_FUN_LLEN(2) | XCT_FUN_SE; | |
1403 | CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T; | |
1404 | CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma); | |
1405 | fill++; | |
1406 | ||
1407 | evt = !csring->last_event; | |
1408 | csring->last_event = evt; | |
1409 | ||
1410 | /* Event handshaking with MAC TX */ | |
1411 | CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1412 | CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]); | |
1413 | CS_DESC(csring, fill++) = 0; | |
1414 | CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1415 | CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]); | |
1416 | CS_DESC(csring, fill++) = 0; | |
1417 | csring->next_to_fill = fill & (CS_RING_SIZE-1); | |
1418 | ||
1419 | cs_size = fill - hdr; | |
1420 | write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1); | |
1421 | ||
1422 | /* TX-side event handshaking */ | |
1423 | fill = txring->next_to_fill; | |
1424 | TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1425 | CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]); | |
1426 | TX_DESC(txring, fill++) = 0; | |
1427 | TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1428 | CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]); | |
1429 | TX_DESC(txring, fill++) = 0; | |
1430 | txring->next_to_fill = fill; | |
1431 | ||
1432 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2); | |
8d636d8b OJ |
1433 | } |
1434 | ||
f5cd7872 OJ |
1435 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) |
1436 | { | |
8d636d8b OJ |
1437 | struct pasemi_mac * const mac = netdev_priv(dev); |
1438 | struct pasemi_mac_txring * const txring = tx_ring(mac); | |
1439 | struct pasemi_mac_csring *csring; | |
1440 | u64 dflags = 0; | |
1441 | u64 mactx; | |
ad3c20d1 OJ |
1442 | dma_addr_t map[MAX_SKB_FRAGS+1]; |
1443 | unsigned int map_size[MAX_SKB_FRAGS+1]; | |
ca7e235f | 1444 | unsigned long flags; |
ad3c20d1 | 1445 | int i, nfrags; |
5c15332b | 1446 | int fill; |
8d636d8b OJ |
1447 | const int nh_off = skb_network_offset(skb); |
1448 | const int nh_len = skb_network_header_len(skb); | |
f5cd7872 | 1449 | |
8d636d8b | 1450 | prefetch(&txring->ring_info); |
d56f90a7 | 1451 | |
8d636d8b | 1452 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; |
f5cd7872 | 1453 | |
ad3c20d1 OJ |
1454 | nfrags = skb_shinfo(skb)->nr_frags; |
1455 | ||
1456 | map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), | |
1457 | PCI_DMA_TODEVICE); | |
1458 | map_size[0] = skb_headlen(skb); | |
8d8bb39b | 1459 | if (pci_dma_mapping_error(mac->dma_pdev, map[0])) |
ad3c20d1 OJ |
1460 | goto out_err_nolock; |
1461 | ||
1462 | for (i = 0; i < nfrags; i++) { | |
1463 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
f5cd7872 | 1464 | |
4bb97cae | 1465 | map[i + 1] = skb_frag_dma_map(&mac->dma_pdev->dev, frag, 0, |
9e903e08 ED |
1466 | skb_frag_size(frag), DMA_TO_DEVICE); |
1467 | map_size[i+1] = skb_frag_size(frag); | |
5d6bcdfe | 1468 | if (dma_mapping_error(&mac->dma_pdev->dev, map[i + 1])) { |
ad3c20d1 OJ |
1469 | nfrags = i; |
1470 | goto out_err_nolock; | |
1471 | } | |
1472 | } | |
f5cd7872 | 1473 | |
8d636d8b OJ |
1474 | if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) { |
1475 | switch (ip_hdr(skb)->protocol) { | |
1476 | case IPPROTO_TCP: | |
1477 | dflags |= XCT_MACTX_CSUM_TCP; | |
1478 | dflags |= XCT_MACTX_IPH(nh_len >> 2); | |
1479 | dflags |= XCT_MACTX_IPO(nh_off); | |
1480 | break; | |
1481 | case IPPROTO_UDP: | |
1482 | dflags |= XCT_MACTX_CSUM_UDP; | |
1483 | dflags |= XCT_MACTX_IPH(nh_len >> 2); | |
1484 | dflags |= XCT_MACTX_IPO(nh_off); | |
1485 | break; | |
1486 | default: | |
1487 | WARN_ON(1); | |
1488 | } | |
1489 | } | |
26fcfa95 | 1490 | |
8d636d8b | 1491 | mactx = dflags | XCT_MACTX_LLEN(skb->len); |
f5cd7872 OJ |
1492 | |
1493 | spin_lock_irqsave(&txring->lock, flags); | |
1494 | ||
ad5da10a OJ |
1495 | /* Avoid stepping on the same cache line that the DMA controller |
1496 | * is currently about to send, so leave at least 8 words available. | |
1497 | * Total free space needed is mactx + fragments + 8 | |
1498 | */ | |
8d636d8b | 1499 | if (RING_AVAIL(txring) < nfrags + 14) { |
ad5da10a OJ |
1500 | /* no room -- stop the queue and wait for tx intr */ |
1501 | netif_stop_queue(dev); | |
1502 | goto out_err; | |
f5cd7872 OJ |
1503 | } |
1504 | ||
8d636d8b OJ |
1505 | /* Queue up checksum + event descriptors, if needed */ |
1506 | if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) { | |
1507 | csring = mac->cs[mac->last_cs]; | |
1508 | mac->last_cs = (mac->last_cs + 1) % mac->num_cs; | |
1509 | ||
1510 | pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring); | |
1511 | } | |
1512 | ||
1513 | fill = txring->next_to_fill; | |
5c15332b | 1514 | TX_DESC(txring, fill) = mactx; |
7e9916e9 | 1515 | TX_DESC_INFO(txring, fill).dma = nfrags; |
5c15332b OJ |
1516 | fill++; |
1517 | TX_DESC_INFO(txring, fill).skb = skb; | |
ad3c20d1 | 1518 | for (i = 0; i <= nfrags; i++) { |
5c15332b | 1519 | TX_DESC(txring, fill+i) = |
72b05b99 | 1520 | XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); |
5c15332b | 1521 | TX_DESC_INFO(txring, fill+i).dma = map[i]; |
ad3c20d1 OJ |
1522 | } |
1523 | ||
1524 | /* We have to add an even number of 8-byte entries to the ring | |
1525 | * even if the last one is unused. That means always an odd number | |
1526 | * of pointers + one mactx descriptor. | |
1527 | */ | |
1528 | if (nfrags & 1) | |
1529 | nfrags++; | |
fc9e4d2a | 1530 | |
5c15332b | 1531 | txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); |
f5cd7872 | 1532 | |
09f75cd7 JG |
1533 | dev->stats.tx_packets++; |
1534 | dev->stats.tx_bytes += skb->len; | |
f5cd7872 OJ |
1535 | |
1536 | spin_unlock_irqrestore(&txring->lock, flags); | |
1537 | ||
34c20624 | 1538 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); |
f5cd7872 OJ |
1539 | |
1540 | return NETDEV_TX_OK; | |
1541 | ||
1542 | out_err: | |
1543 | spin_unlock_irqrestore(&txring->lock, flags); | |
ad3c20d1 OJ |
1544 | out_err_nolock: |
1545 | while (nfrags--) | |
1546 | pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], | |
1547 | PCI_DMA_TODEVICE); | |
1548 | ||
f5cd7872 OJ |
1549 | return NETDEV_TX_BUSY; |
1550 | } | |
1551 | ||
f5cd7872 OJ |
1552 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1553 | { | |
5c15332b | 1554 | const struct pasemi_mac *mac = netdev_priv(dev); |
f5cd7872 OJ |
1555 | unsigned int flags; |
1556 | ||
a85b9422 | 1557 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
f5cd7872 OJ |
1558 | |
1559 | /* Set promiscuous */ | |
1560 | if (dev->flags & IFF_PROMISC) | |
1561 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1562 | else | |
1563 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1564 | ||
a85b9422 | 1565 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
f5cd7872 OJ |
1566 | } |
1567 | ||
1568 | ||
bea3348e | 1569 | static int pasemi_mac_poll(struct napi_struct *napi, int budget) |
f5cd7872 | 1570 | { |
bea3348e | 1571 | struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); |
bea3348e | 1572 | int pkts; |
f5cd7872 | 1573 | |
72b05b99 OJ |
1574 | pasemi_mac_clean_tx(tx_ring(mac)); |
1575 | pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); | |
bea3348e | 1576 | if (pkts < budget) { |
f5cd7872 | 1577 | /* all done, no more packets present */ |
288379f0 | 1578 | napi_complete(napi); |
f5cd7872 | 1579 | |
1b0335ea | 1580 | pasemi_mac_restart_rx_intr(mac); |
61cec3bd | 1581 | pasemi_mac_restart_tx_intr(mac); |
f5cd7872 | 1582 | } |
bea3348e | 1583 | return pkts; |
f5cd7872 OJ |
1584 | } |
1585 | ||
6e62040c NC |
1586 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1587 | /* | |
1588 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1589 | * without having to re-enable interrupts. It's not called while | |
1590 | * the interrupt routine is executing. | |
1591 | */ | |
1592 | static void pasemi_mac_netpoll(struct net_device *dev) | |
1593 | { | |
1594 | const struct pasemi_mac *mac = netdev_priv(dev); | |
1595 | ||
1596 | disable_irq(mac->tx->chan.irq); | |
1597 | pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx); | |
1598 | enable_irq(mac->tx->chan.irq); | |
1599 | ||
1600 | disable_irq(mac->rx->chan.irq); | |
1601 | pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx); | |
1602 | enable_irq(mac->rx->chan.irq); | |
1603 | } | |
1604 | #endif | |
1605 | ||
ef1ea0b4 OJ |
1606 | static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu) |
1607 | { | |
1608 | struct pasemi_mac *mac = netdev_priv(dev); | |
1609 | unsigned int reg; | |
8d636d8b | 1610 | unsigned int rcmdsta = 0; |
ef1ea0b4 | 1611 | int running; |
8d636d8b | 1612 | int ret = 0; |
ef1ea0b4 | 1613 | |
ef1ea0b4 OJ |
1614 | running = netif_running(dev); |
1615 | ||
1616 | if (running) { | |
1617 | /* Need to stop the interface, clean out all already | |
1618 | * received buffers, free all unused buffers on the RX | |
1619 | * interface ring, then finally re-fill the rx ring with | |
1620 | * the new-size buffers and restart. | |
1621 | */ | |
1622 | ||
1623 | napi_disable(&mac->napi); | |
1624 | netif_tx_disable(dev); | |
1625 | pasemi_mac_intf_disable(mac); | |
1626 | ||
1627 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1628 | pasemi_mac_pause_rxint(mac); | |
1629 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
1630 | pasemi_mac_free_rx_buffers(mac); | |
8d636d8b OJ |
1631 | |
1632 | } | |
1633 | ||
1634 | /* Setup checksum channels if large MTU and none already allocated */ | |
44770e11 | 1635 | if (new_mtu > PE_DEF_MTU && !mac->num_cs) { |
8d636d8b OJ |
1636 | pasemi_mac_setup_csrings(mac); |
1637 | if (!mac->num_cs) { | |
1638 | ret = -ENOMEM; | |
1639 | goto out; | |
1640 | } | |
ef1ea0b4 OJ |
1641 | } |
1642 | ||
1643 | /* Change maxf, i.e. what size frames are accepted. | |
1644 | * Need room for ethernet header and CRC word | |
1645 | */ | |
1646 | reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG); | |
1647 | reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M; | |
1648 | reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4); | |
1649 | write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg); | |
1650 | ||
1651 | dev->mtu = new_mtu; | |
1652 | /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
1653 | mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
1654 | ||
8d636d8b | 1655 | out: |
ef1ea0b4 OJ |
1656 | if (running) { |
1657 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1658 | rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN); | |
1659 | ||
1660 | rx_ring(mac)->next_to_fill = 0; | |
1661 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1); | |
1662 | ||
1663 | napi_enable(&mac->napi); | |
1664 | netif_start_queue(dev); | |
1665 | pasemi_mac_intf_enable(mac); | |
1666 | } | |
1667 | ||
8d636d8b | 1668 | return ret; |
ef1ea0b4 OJ |
1669 | } |
1670 | ||
9e0ac841 AB |
1671 | static const struct net_device_ops pasemi_netdev_ops = { |
1672 | .ndo_open = pasemi_mac_open, | |
1673 | .ndo_stop = pasemi_mac_close, | |
1674 | .ndo_start_xmit = pasemi_mac_start_tx, | |
afc4b13d | 1675 | .ndo_set_rx_mode = pasemi_mac_set_rx_mode, |
9e0ac841 AB |
1676 | .ndo_set_mac_address = pasemi_mac_set_mac_addr, |
1677 | .ndo_change_mtu = pasemi_mac_change_mtu, | |
1678 | .ndo_validate_addr = eth_validate_addr, | |
1679 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1680 | .ndo_poll_controller = pasemi_mac_netpoll, | |
1681 | #endif | |
1682 | }; | |
1683 | ||
03c4d832 | 1684 | static int |
f5cd7872 OJ |
1685 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1686 | { | |
f5cd7872 OJ |
1687 | struct net_device *dev; |
1688 | struct pasemi_mac *mac; | |
15b8e191 | 1689 | int err, ret; |
f5cd7872 OJ |
1690 | |
1691 | err = pci_enable_device(pdev); | |
1692 | if (err) | |
1693 | return err; | |
1694 | ||
1695 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1696 | if (dev == NULL) { | |
f5cd7872 OJ |
1697 | err = -ENOMEM; |
1698 | goto out_disable_device; | |
1699 | } | |
1700 | ||
f5cd7872 OJ |
1701 | pci_set_drvdata(pdev, dev); |
1702 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1703 | ||
1704 | mac = netdev_priv(dev); | |
1705 | ||
1706 | mac->pdev = pdev; | |
1707 | mac->netdev = dev; | |
f5cd7872 | 1708 | |
bea3348e SH |
1709 | netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); |
1710 | ||
5c15332b | 1711 | dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG | |
25156784 | 1712 | NETIF_F_HIGHDMA | NETIF_F_GSO; |
bea3348e | 1713 | |
34c20624 OJ |
1714 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); |
1715 | if (!mac->dma_pdev) { | |
1716 | dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); | |
1717 | err = -ENODEV; | |
1718 | goto out; | |
1719 | } | |
f5cd7872 | 1720 | |
34c20624 OJ |
1721 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); |
1722 | if (!mac->iob_pdev) { | |
1723 | dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); | |
1724 | err = -ENODEV; | |
1725 | goto out; | |
1726 | } | |
1727 | ||
1728 | /* get mac addr from device tree */ | |
1729 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1730 | err = -ENODEV; | |
1731 | goto out; | |
1732 | } | |
1733 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1734 | ||
15b8e191 | 1735 | ret = mac_to_intf(mac); |
1736 | if (ret < 0) { | |
34c20624 OJ |
1737 | dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); |
1738 | err = -ENODEV; | |
1739 | goto out; | |
1740 | } | |
15b8e191 | 1741 | mac->dma_if = ret; |
f5cd7872 OJ |
1742 | |
1743 | switch (pdev->device) { | |
1744 | case 0xa005: | |
1745 | mac->type = MAC_TYPE_GMAC; | |
1746 | break; | |
1747 | case 0xa006: | |
1748 | mac->type = MAC_TYPE_XAUI; | |
1749 | break; | |
1750 | default: | |
1751 | err = -ENODEV; | |
1752 | goto out; | |
1753 | } | |
1754 | ||
9e0ac841 | 1755 | dev->netdev_ops = &pasemi_netdev_ops; |
ef1ea0b4 | 1756 | dev->mtu = PE_DEF_MTU; |
44770e11 JW |
1757 | |
1758 | /* MTU range: 64 - 9000 */ | |
1759 | dev->min_mtu = PE_MIN_MTU; | |
1760 | dev->max_mtu = PE_MAX_MTU; | |
1761 | ||
ef1ea0b4 OJ |
1762 | /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ |
1763 | mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
1764 | ||
e37c772e | 1765 | dev->ethtool_ops = &pasemi_mac_ethtool_ops; |
f5cd7872 | 1766 | |
b6e05a1b OJ |
1767 | if (err) |
1768 | goto out; | |
f5cd7872 | 1769 | |
ceb51361 OJ |
1770 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1771 | ||
bb6e9590 OJ |
1772 | /* Enable most messages by default */ |
1773 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1774 | ||
f5cd7872 OJ |
1775 | err = register_netdev(dev); |
1776 | ||
1777 | if (err) { | |
1778 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1779 | err); | |
1780 | goto out; | |
ea5cdccc | 1781 | } else if (netif_msg_probe(mac)) { |
e174961c | 1782 | printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n", |
f5cd7872 | 1783 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", |
e174961c | 1784 | mac->dma_if, dev->dev_addr); |
ea5cdccc | 1785 | } |
f5cd7872 OJ |
1786 | |
1787 | return err; | |
1788 | ||
1789 | out: | |
6db16718 ME |
1790 | pci_dev_put(mac->iob_pdev); |
1791 | pci_dev_put(mac->dma_pdev); | |
b6e05a1b | 1792 | |
f5cd7872 OJ |
1793 | free_netdev(dev); |
1794 | out_disable_device: | |
1795 | pci_disable_device(pdev); | |
1796 | return err; | |
1797 | ||
1798 | } | |
1799 | ||
03c4d832 | 1800 | static void pasemi_mac_remove(struct pci_dev *pdev) |
f5cd7872 OJ |
1801 | { |
1802 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1803 | struct pasemi_mac *mac; | |
1804 | ||
1805 | if (!netdev) | |
1806 | return; | |
1807 | ||
1808 | mac = netdev_priv(netdev); | |
1809 | ||
1810 | unregister_netdev(netdev); | |
1811 | ||
1812 | pci_disable_device(pdev); | |
1813 | pci_dev_put(mac->dma_pdev); | |
1814 | pci_dev_put(mac->iob_pdev); | |
1815 | ||
34c20624 OJ |
1816 | pasemi_dma_free_chan(&mac->tx->chan); |
1817 | pasemi_dma_free_chan(&mac->rx->chan); | |
b6e05a1b | 1818 | |
f5cd7872 OJ |
1819 | free_netdev(netdev); |
1820 | } | |
1821 | ||
9baa3c34 | 1822 | static const struct pci_device_id pasemi_mac_pci_tbl[] = { |
f5cd7872 OJ |
1823 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, |
1824 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
fd178254 | 1825 | { }, |
f5cd7872 OJ |
1826 | }; |
1827 | ||
1828 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1829 | ||
1830 | static struct pci_driver pasemi_mac_driver = { | |
1831 | .name = "pasemi_mac", | |
1832 | .id_table = pasemi_mac_pci_tbl, | |
1833 | .probe = pasemi_mac_probe, | |
03c4d832 | 1834 | .remove = pasemi_mac_remove, |
f5cd7872 OJ |
1835 | }; |
1836 | ||
1837 | static void __exit pasemi_mac_cleanup_module(void) | |
1838 | { | |
1839 | pci_unregister_driver(&pasemi_mac_driver); | |
f5cd7872 OJ |
1840 | } |
1841 | ||
1842 | int pasemi_mac_init_module(void) | |
1843 | { | |
34c20624 OJ |
1844 | int err; |
1845 | ||
1846 | err = pasemi_dma_init(); | |
1847 | if (err) | |
1848 | return err; | |
1849 | ||
f5cd7872 OJ |
1850 | return pci_register_driver(&pasemi_mac_driver); |
1851 | } | |
1852 | ||
f5cd7872 OJ |
1853 | module_init(pasemi_mac_init_module); |
1854 | module_exit(pasemi_mac_cleanup_module); |