[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / pasemi / pasemi_mac.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2006 PA Semi, Inc
 *
 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
 * hardware register layouts.
 */

#ifndef PASEMI_MAC_H
#define PASEMI_MAC_H

#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/spinlock.h>
#include <linux/phy.h>

/* Must be a power of two */
#define RX_RING_SIZE 2048
#define TX_RING_SIZE 4096
#define CS_RING_SIZE (TX_RING_SIZE*2)


#define MAX_CS	2

struct pasemi_mac_txring {
	struct pasemi_dmachan chan; /* Must be first */
	spinlock_t	 lock;
	unsigned int	 size;
	unsigned int	 next_to_fill;
	unsigned int	 next_to_clean;
	struct pasemi_mac_buffer *ring_info;
	struct pasemi_mac *mac;	/* Needed in intr handler */
	struct timer_list clean_timer;
};

struct pasemi_mac_rxring {
	struct pasemi_dmachan chan; /* Must be first */
	spinlock_t	 lock;
	u64		*buffers;	/* RX interface buffer ring */
	dma_addr_t	 buf_dma;
	unsigned int	 size;
	unsigned int	 next_to_fill;
	unsigned int	 next_to_clean;
	struct pasemi_mac_buffer *ring_info;
	struct pasemi_mac *mac;	/* Needed in intr handler */
};

struct pasemi_mac_csring {
	struct pasemi_dmachan chan;
	unsigned int	size;
	unsigned int	next_to_fill;
	int		events[2];
	int		last_event;
	int		fun;
};

struct pasemi_mac {
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct pci_dev *dma_pdev;
	struct pci_dev *iob_pdev;
	struct napi_struct napi;

	int		bufsz; /* RX ring buffer size */
	int		last_cs;
	int		num_cs;
	u32		dma_if;
	u8		type;
#define MAC_TYPE_GMAC	1
#define MAC_TYPE_XAUI	2

	u8		mac_addr[ETH_ALEN];

	struct timer_list	rxtimer;

	struct pasemi_mac_txring *tx;
	struct pasemi_mac_rxring *rx;
	struct pasemi_mac_csring *cs[MAX_CS];
	char		tx_irq_name[10];		/* "eth%d tx" */
	char		rx_irq_name[10];		/* "eth%d rx" */
	int	link;
	int	speed;
	int	duplex;

	unsigned int	msg_enable;
};

/* Software status descriptor (ring_info) */
struct pasemi_mac_buffer {
	struct sk_buff *skb;
	dma_addr_t	dma;
};

#define TX_DESC(tx, num)	((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
#define TX_DESC_INFO(tx, num)	((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
#define RX_DESC(rx, num)	((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
#define RX_DESC_INFO(rx, num)	((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
#define RX_BUFF(rx, num)	((rx)->buffers[(num) & (RX_RING_SIZE-1)])
#define CS_DESC(cs, num)	((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)])

#define RING_USED(ring)	(((ring)->next_to_fill - (ring)->next_to_clean) \
				& ((ring)->size - 1))
#define RING_AVAIL(ring)	((ring->size) - RING_USED(ring))

/* PCI register offsets and formats */


/* MAC CFG register offsets */
enum {
	PAS_MAC_CFG_PCFG = 0x80,
	PAS_MAC_CFG_MACCFG = 0x84,
	PAS_MAC_CFG_ADR0 = 0x8c,
	PAS_MAC_CFG_ADR1 = 0x90,
	PAS_MAC_CFG_TXP = 0x98,
	PAS_MAC_CFG_RMON = 0x100,
	PAS_MAC_IPC_CHNL = 0x208,
};

/* MAC CFG register fields */
#define PAS_MAC_CFG_PCFG_PE		0x80000000
#define PAS_MAC_CFG_PCFG_CE		0x40000000
#define PAS_MAC_CFG_PCFG_BU		0x20000000
#define PAS_MAC_CFG_PCFG_TT		0x10000000
#define PAS_MAC_CFG_PCFG_TSR_M		0x0c000000
#define PAS_MAC_CFG_PCFG_TSR_10M	0x00000000
#define PAS_MAC_CFG_PCFG_TSR_100M	0x04000000
#define PAS_MAC_CFG_PCFG_TSR_1G		0x08000000
#define PAS_MAC_CFG_PCFG_TSR_10G	0x0c000000
#define PAS_MAC_CFG_PCFG_T24		0x02000000
#define PAS_MAC_CFG_PCFG_PR		0x01000000
#define PAS_MAC_CFG_PCFG_CRO_M		0x00ff0000
#define PAS_MAC_CFG_PCFG_CRO_S	16
#define PAS_MAC_CFG_PCFG_IPO_M		0x0000ff00
#define PAS_MAC_CFG_PCFG_IPO_S	8
#define PAS_MAC_CFG_PCFG_S1		0x00000080
#define PAS_MAC_CFG_PCFG_IO_M		0x00000060
#define PAS_MAC_CFG_PCFG_IO_MAC		0x00000000
#define PAS_MAC_CFG_PCFG_IO_OFF		0x00000020
#define PAS_MAC_CFG_PCFG_IO_IND_ETH	0x00000040
#define PAS_MAC_CFG_PCFG_IO_IND_IP	0x00000060
#define PAS_MAC_CFG_PCFG_LP		0x00000010
#define PAS_MAC_CFG_PCFG_TS		0x00000008
#define PAS_MAC_CFG_PCFG_HD		0x00000004
#define PAS_MAC_CFG_PCFG_SPD_M		0x00000003
#define PAS_MAC_CFG_PCFG_SPD_10M	0x00000000
#define PAS_MAC_CFG_PCFG_SPD_100M	0x00000001
#define PAS_MAC_CFG_PCFG_SPD_1G		0x00000002
#define PAS_MAC_CFG_PCFG_SPD_10G	0x00000003

#define PAS_MAC_CFG_MACCFG_TXT_M	0x70000000
#define PAS_MAC_CFG_MACCFG_TXT_S	28
#define PAS_MAC_CFG_MACCFG_PRES_M	0x0f000000
#define PAS_MAC_CFG_MACCFG_PRES_S	24
#define PAS_MAC_CFG_MACCFG_MAXF_M	0x00ffff00
#define PAS_MAC_CFG_MACCFG_MAXF_S	8
#define PAS_MAC_CFG_MACCFG_MAXF(x)	(((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \
					 PAS_MAC_CFG_MACCFG_MAXF_M)
#define PAS_MAC_CFG_MACCFG_MINF_M	0x000000ff
#define PAS_MAC_CFG_MACCFG_MINF_S	0

#define PAS_MAC_CFG_TXP_FCF		0x01000000
#define PAS_MAC_CFG_TXP_FCE		0x00800000
#define PAS_MAC_CFG_TXP_FC		0x00400000
#define PAS_MAC_CFG_TXP_FPC_M		0x00300000
#define PAS_MAC_CFG_TXP_FPC_S		20
#define PAS_MAC_CFG_TXP_FPC(x)		(((x) << PAS_MAC_CFG_TXP_FPC_S) & \
					 PAS_MAC_CFG_TXP_FPC_M)
#define PAS_MAC_CFG_TXP_RT		0x00080000
#define PAS_MAC_CFG_TXP_BL		0x00040000
#define PAS_MAC_CFG_TXP_SL_M		0x00030000
#define PAS_MAC_CFG_TXP_SL_S		16
#define PAS_MAC_CFG_TXP_SL(x)		(((x) << PAS_MAC_CFG_TXP_SL_S) & \
					 PAS_MAC_CFG_TXP_SL_M)
#define PAS_MAC_CFG_TXP_COB_M		0x0000f000
#define PAS_MAC_CFG_TXP_COB_S		12
#define PAS_MAC_CFG_TXP_COB(x)		(((x) << PAS_MAC_CFG_TXP_COB_S) & \
					 PAS_MAC_CFG_TXP_COB_M)
#define PAS_MAC_CFG_TXP_TIFT_M		0x00000f00
#define PAS_MAC_CFG_TXP_TIFT_S		8
#define PAS_MAC_CFG_TXP_TIFT(x)		(((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
					 PAS_MAC_CFG_TXP_TIFT_M)
#define PAS_MAC_CFG_TXP_TIFG_M		0x000000ff
#define PAS_MAC_CFG_TXP_TIFG_S		0
#define PAS_MAC_CFG_TXP_TIFG(x)		(((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
					 PAS_MAC_CFG_TXP_TIFG_M)

#define PAS_MAC_RMON(r)			(0x100+(r)*4)

#define PAS_MAC_IPC_CHNL_DCHNO_M	0x003f0000
#define PAS_MAC_IPC_CHNL_DCHNO_S	16
#define PAS_MAC_IPC_CHNL_DCHNO(x)	(((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
					 PAS_MAC_IPC_CHNL_DCHNO_M)
#define PAS_MAC_IPC_CHNL_BCH_M		0x0000003f
#define PAS_MAC_IPC_CHNL_BCH_S		0
#define PAS_MAC_IPC_CHNL_BCH(x)		(((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
					 PAS_MAC_IPC_CHNL_BCH_M)


#endif /* PASEMI_MAC_H */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
f5cd7872 OJ	2	/*
	3	* Copyright (C) 2006 PA Semi, Inc
	4	*
	5	* Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
	6	* hardware register layouts.
f5cd7872 OJ	7	*/
	8
	9	#ifndef PASEMI_MAC_H
	10	#define PASEMI_MAC_H
	11
	12	#include <linux/ethtool.h>
	13	#include <linux/netdevice.h>
	14	#include <linux/spinlock.h>
bb6e9590	15	#include <linux/phy.h>
f5cd7872	16
e37c772e OJ	17	/* Must be a power of two */
	18	#define RX_RING_SIZE 2048
	19	#define TX_RING_SIZE 4096
	20	#define CS_RING_SIZE (TX_RING_SIZE*2)
	21
	22
8d636d8b	23	#define MAX_CS 2
28ae79f5	24
f5cd7872	25	struct pasemi_mac_txring {
34c20624	26	struct pasemi_dmachan chan; /* Must be first */
f5cd7872	27	spinlock_t lock;
f5cd7872	28	unsigned int size;
021fa22e	29	unsigned int next_to_fill;
f5cd7872	30	unsigned int next_to_clean;
fc9e4d2a	31	struct pasemi_mac_buffer *ring_info;
72b05b99	32	struct pasemi_mac mac; / Needed in intr handler */
61cec3bd	33	struct timer_list clean_timer;
f5cd7872 OJ	34	};
	35
	36	struct pasemi_mac_rxring {
34c20624	37	struct pasemi_dmachan chan; /* Must be first */
f5cd7872	38	spinlock_t lock;
f5cd7872 OJ	39	u64 buffers; / RX interface buffer ring */
	40	dma_addr_t buf_dma;
	41	unsigned int size;
	42	unsigned int next_to_fill;
	43	unsigned int next_to_clean;
fc9e4d2a	44	struct pasemi_mac_buffer *ring_info;
72b05b99	45	struct pasemi_mac mac; / Needed in intr handler */
f5cd7872 OJ	46	};
f5cd7872 OJ	47
8d636d8b OJ	48	struct pasemi_mac_csring {
	49	struct pasemi_dmachan chan;
	50	unsigned int size;
	51	unsigned int next_to_fill;
	52	int events[2];
	53	int last_event;
	54	int fun;
	55	};
	56
f5cd7872 OJ	57	struct pasemi_mac {
	58	struct net_device *netdev;
	59	struct pci_dev *pdev;
	60	struct pci_dev *dma_pdev;
	61	struct pci_dev *iob_pdev;
bea3348e	62	struct napi_struct napi;
f5cd7872	63
ef1ea0b4	64	int bufsz; /* RX ring buffer size */
8d636d8b OJ	65	int last_cs;
	66	int num_cs;
	67	u32 dma_if;
f5cd7872 OJ	68	u8 type;
	69	#define MAC_TYPE_GMAC 1
	70	#define MAC_TYPE_XAUI 2
f5cd7872	71
1409a932	72	u8 mac_addr[ETH_ALEN];
f5cd7872 OJ	73
	74	struct timer_list rxtimer;
	75
	76	struct pasemi_mac_txring *tx;
	77	struct pasemi_mac_rxring *rx;
8d636d8b	78	struct pasemi_mac_csring *cs[MAX_CS];
72b05b99 OJ	79	char tx_irq_name[10]; /* "eth%d tx" */
72b05b99 OJ	80	char rx_irq_name[10]; /* "eth%d rx" */
bb6e9590 OJ	81	int link;
	82	int speed;
	83	int duplex;
ceb51361 OJ	84
ceb51361 OJ	85	unsigned int msg_enable;
f5cd7872 OJ	86	};
f5cd7872 OJ	87
fc9e4d2a	88	/* Software status descriptor (ring_info) */
f5cd7872 OJ	89	struct pasemi_mac_buffer {
	90	struct sk_buff *skb;
	91	dma_addr_t dma;
	92	};
	93
e37c772e OJ	94	#define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
	95	#define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
	96	#define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
	97	#define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
	98	#define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
	99	#define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)])
	100
	101	#define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
	102	& ((ring)->size - 1))
	103	#define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
f5cd7872	104
40afa531 OJ	105	/* PCI register offsets and formats */
40afa531 OJ	106
f5cd7872	107
f5cd7872	108	/* MAC CFG register offsets */
f5cd7872 OJ	109	enum {
f5cd7872 OJ	110	PAS_MAC_CFG_PCFG = 0x80,
ef1ea0b4	111	PAS_MAC_CFG_MACCFG = 0x84,
5cea73b0 OJ	112	PAS_MAC_CFG_ADR0 = 0x8c,
5cea73b0 OJ	113	PAS_MAC_CFG_ADR1 = 0x90,
f5cd7872	114	PAS_MAC_CFG_TXP = 0x98,
e37c772e	115	PAS_MAC_CFG_RMON = 0x100,
f5cd7872 OJ	116	PAS_MAC_IPC_CHNL = 0x208,
	117	};
	118
	119	/* MAC CFG register fields */
	120	#define PAS_MAC_CFG_PCFG_PE 0x80000000
	121	#define PAS_MAC_CFG_PCFG_CE 0x40000000
	122	#define PAS_MAC_CFG_PCFG_BU 0x20000000
	123	#define PAS_MAC_CFG_PCFG_TT 0x10000000
	124	#define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
	125	#define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
	126	#define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
	127	#define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
	128	#define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
	129	#define PAS_MAC_CFG_PCFG_T24 0x02000000
	130	#define PAS_MAC_CFG_PCFG_PR 0x01000000
	131	#define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
	132	#define PAS_MAC_CFG_PCFG_CRO_S 16
	133	#define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
	134	#define PAS_MAC_CFG_PCFG_IPO_S 8
	135	#define PAS_MAC_CFG_PCFG_S1 0x00000080
	136	#define PAS_MAC_CFG_PCFG_IO_M 0x00000060
	137	#define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
	138	#define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
	139	#define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
	140	#define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
	141	#define PAS_MAC_CFG_PCFG_LP 0x00000010
	142	#define PAS_MAC_CFG_PCFG_TS 0x00000008
	143	#define PAS_MAC_CFG_PCFG_HD 0x00000004
	144	#define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
	145	#define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
	146	#define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
	147	#define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
	148	#define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
ef1ea0b4 OJ	149
	150	#define PAS_MAC_CFG_MACCFG_TXT_M 0x70000000
	151	#define PAS_MAC_CFG_MACCFG_TXT_S 28
	152	#define PAS_MAC_CFG_MACCFG_PRES_M 0x0f000000
	153	#define PAS_MAC_CFG_MACCFG_PRES_S 24
	154	#define PAS_MAC_CFG_MACCFG_MAXF_M 0x00ffff00
	155	#define PAS_MAC_CFG_MACCFG_MAXF_S 8
	156	#define PAS_MAC_CFG_MACCFG_MAXF(x) (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \
	157	PAS_MAC_CFG_MACCFG_MAXF_M)
	158	#define PAS_MAC_CFG_MACCFG_MINF_M 0x000000ff
	159	#define PAS_MAC_CFG_MACCFG_MINF_S 0
	160
f5cd7872 OJ	161	#define PAS_MAC_CFG_TXP_FCF 0x01000000
	162	#define PAS_MAC_CFG_TXP_FCE 0x00800000
	163	#define PAS_MAC_CFG_TXP_FC 0x00400000
	164	#define PAS_MAC_CFG_TXP_FPC_M 0x00300000
	165	#define PAS_MAC_CFG_TXP_FPC_S 20
	166	#define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
	167	PAS_MAC_CFG_TXP_FPC_M)
	168	#define PAS_MAC_CFG_TXP_RT 0x00080000
	169	#define PAS_MAC_CFG_TXP_BL 0x00040000
	170	#define PAS_MAC_CFG_TXP_SL_M 0x00030000
	171	#define PAS_MAC_CFG_TXP_SL_S 16
	172	#define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
	173	PAS_MAC_CFG_TXP_SL_M)
	174	#define PAS_MAC_CFG_TXP_COB_M 0x0000f000
	175	#define PAS_MAC_CFG_TXP_COB_S 12
	176	#define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
	177	PAS_MAC_CFG_TXP_COB_M)
	178	#define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
	179	#define PAS_MAC_CFG_TXP_TIFT_S 8
	180	#define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
	181	PAS_MAC_CFG_TXP_TIFT_M)
	182	#define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
	183	#define PAS_MAC_CFG_TXP_TIFG_S 0
	184	#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
	185	PAS_MAC_CFG_TXP_TIFG_M)
	186
e37c772e OJ	187	#define PAS_MAC_RMON(r) (0x100+(r)*4)
e37c772e OJ	188
f5cd7872 OJ	189	#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
	190	#define PAS_MAC_IPC_CHNL_DCHNO_S 16
	191	#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
	192	PAS_MAC_IPC_CHNL_DCHNO_M)
	193	#define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
	194	#define PAS_MAC_IPC_CHNL_BCH_S 0
	195	#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
	196	PAS_MAC_IPC_CHNL_BCH_M)
	197
e37c772e	198
f5cd7872	199	#endif /* PASEMI_MAC_H */