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ionic: print firmware version on identify
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / pensando / ionic / ionic_lif.c
CommitLineData
1a58e196
SN		 1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3
cc69837f 4#include <linux/ethtool.h>
011c7289
AB		 5#include <linux/printk.h>
6#include <linux/dynamic_debug.h>
1a58e196
SN		 7#include <linux/netdevice.h>
8#include <linux/etherdevice.h>
4b03b273 9#include <linux/if_vlan.h>
8c15440b 10#include <linux/rtnetlink.h>
1a58e196
SN		 11#include <linux/interrupt.h>
12#include <linux/pci.h>
13#include <linux/cpumask.h>
c0b03e83 14#include <linux/crash_dump.h>
1a58e196
SN		 15
16#include "ionic.h"
17#include "ionic_bus.h"
18#include "ionic_lif.h"
0f3154e6 19#include "ionic_txrx.h"
4d03e00a 20#include "ionic_ethtool.h"
1a58e196
SN		 21#include "ionic_debugfs.h"
22
5b3f3f2a
SN		 23/* queuetype support level */
24static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = {
25 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */
26 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */
27 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */
28 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support
29 * 1 = ... with Tx SG version 1
30 */
31};
32
2a654540
SN		 33static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode);
34static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr);
35static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr);
8d61aad4 36static void ionic_link_status_check(struct ionic_lif *lif);
c672412f
SN		 37static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
38static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
39static void ionic_lif_set_netdev_info(struct ionic_lif *lif);
2a654540 40
f053e1f8
SN		 41static void ionic_txrx_deinit(struct ionic_lif *lif);
42static int ionic_txrx_init(struct ionic_lif *lif);
49d3b493
SN		 43static int ionic_start_queues(struct ionic_lif *lif);
44static void ionic_stop_queues(struct ionic_lif *lif);
5b3f3f2a 45static void ionic_lif_queue_identify(struct ionic_lif *lif);
49d3b493 46
04a83459
SN		 47static void ionic_dim_work(struct work_struct *work)
48{
49 struct dim *dim = container_of(work, struct dim, work);
50 struct dim_cq_moder cur_moder;
51 struct ionic_qcq *qcq;
52 u32 new_coal;
53
54 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
55 qcq = container_of(dim, struct ionic_qcq, dim);
56 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);
57 qcq->intr.dim_coal_hw = new_coal ? new_coal : 1;
58 dim->state = DIM_START_MEASURE;
59}
60
2a654540
SN		 61static void ionic_lif_deferred_work(struct work_struct *work)
62{
63 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
64 struct ionic_deferred *def = &lif->deferred;
65 struct ionic_deferred_work *w = NULL;
66
52733cff
SN		 67 do {
68 spin_lock_bh(&def->lock);
69 if (!list_empty(&def->list)) {
70 w = list_first_entry(&def->list,
71 struct ionic_deferred_work, list);
72 list_del(&w->list);
73 }
74 spin_unlock_bh(&def->lock);
75
76 if (!w)
77 break;
2a654540 78
2a654540
SN		 79 switch (w->type) {
80 case IONIC_DW_TYPE_RX_MODE:
81 ionic_lif_rx_mode(lif, w->rx_mode);
82 break;
83 case IONIC_DW_TYPE_RX_ADDR_ADD:
84 ionic_lif_addr_add(lif, w->addr);
85 break;
86 case IONIC_DW_TYPE_RX_ADDR_DEL:
87 ionic_lif_addr_del(lif, w->addr);
88 break;
8d61aad4
SN		 89 case IONIC_DW_TYPE_LINK_STATUS:
90 ionic_link_status_check(lif);
91 break;
c672412f
SN		 92 case IONIC_DW_TYPE_LIF_RESET:
93 if (w->fw_status)
94 ionic_lif_handle_fw_up(lif);
95 else
96 ionic_lif_handle_fw_down(lif);
97 break;
2a654540
SN		 98 default:
99 break;
100 }
101 kfree(w);
52733cff
SN		 102 w = NULL;
103 } while (true);
2a654540
SN		 104}
105
c672412f
SN		 106void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
107 struct ionic_deferred_work *work)
2a654540
SN		 108{
109 spin_lock_bh(&def->lock);
110 list_add_tail(&work->list, &def->list);
111 spin_unlock_bh(&def->lock);
112 schedule_work(&def->work);
113}
114
8d61aad4
SN		 115static void ionic_link_status_check(struct ionic_lif *lif)
116{
117 struct net_device *netdev = lif->netdev;
118 u16 link_status;
119 bool link_up;
120
0925e9db 121 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
49d3b493
SN		 122 return;
123
9e8eaf84
SN		 124 /* Don't put carrier back up if we're in a broken state */
125 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) {
126 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
127 return;
128 }
129
8d61aad4
SN		 130 link_status = le16_to_cpu(lif->info->status.link_status);
131 link_up = link_status == IONIC_PORT_OPER_STATUS_UP;
132
8d61aad4 133 if (link_up) {
9e8eaf84
SN		 134 int err = 0;
135
25cc5a5f 136 if (netdev->flags & IFF_UP && netif_running(netdev)) {
8f56bc4d 137 mutex_lock(&lif->queue_lock);
9e8eaf84 138 err = ionic_start_queues(lif);
99b5bea0 139 if (err && err != -EBUSY) {
9e8eaf84
SN		 140 netdev_err(lif->netdev,
141 "Failed to start queues: %d\n", err);
142 set_bit(IONIC_LIF_F_BROKEN, lif->state);
143 netif_carrier_off(lif->netdev);
144 }
8f56bc4d
SN		 145 mutex_unlock(&lif->queue_lock);
146 }
147
9e8eaf84 148 if (!err && !netif_carrier_ok(netdev)) {
aa47b540 149 ionic_port_identify(lif->ionic);
aa47b540 150 netdev_info(netdev, "Link up - %d Gbps\n",
25cc5a5f 151 le32_to_cpu(lif->info->status.link_speed) / 1000);
0f3154e6
SN		 152 netif_carrier_on(netdev);
153 }
8d61aad4 154 } else {
aa47b540
SN		 155 if (netif_carrier_ok(netdev)) {
156 netdev_info(netdev, "Link down\n");
157 netif_carrier_off(netdev);
158 }
8d61aad4 159
25cc5a5f 160 if (netdev->flags & IFF_UP && netif_running(netdev)) {
0925e9db 161 mutex_lock(&lif->queue_lock);
49d3b493 162 ionic_stop_queues(lif);
0925e9db
SN		 163 mutex_unlock(&lif->queue_lock);
164 }
8d61aad4
SN		 165 }
166
c6d3d73a 167 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
8d61aad4
SN		 168}
169
1800eee1 170void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep)
8d61aad4
SN		 171{
172 struct ionic_deferred_work *work;
173
174 /* we only need one request outstanding at a time */
c6d3d73a 175 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
8d61aad4
SN		 176 return;
177
1800eee1 178 if (!can_sleep) {
8d61aad4 179 work = kzalloc(sizeof(*work), GFP_ATOMIC);
2c580d77
SN		 180 if (!work) {
181 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
8d61aad4 182 return;
2c580d77 183 }
8d61aad4
SN		 184
185 work->type = IONIC_DW_TYPE_LINK_STATUS;
186 ionic_lif_deferred_enqueue(&lif->deferred, work);
187 } else {
188 ionic_link_status_check(lif);
189 }
190}
191
1d062b7b
SN		 192static irqreturn_t ionic_isr(int irq, void *data)
193{
194 struct napi_struct *napi = data;
195
196 napi_schedule_irqoff(napi);
197
198 return IRQ_HANDLED;
199}
200
201static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
202{
203 struct ionic_intr_info *intr = &qcq->intr;
204 struct device *dev = lif->ionic->dev;
205 struct ionic_queue *q = &qcq->q;
206 const char *name;
207
208 if (lif->registered)
209 name = lif->netdev->name;
210 else
211 name = dev_name(dev);
212
213 snprintf(intr->name, sizeof(intr->name),
214 "%s-%s-%s", IONIC_DRV_NAME, name, q->name);
215
216 return devm_request_irq(dev, intr->vector, ionic_isr,
217 0, intr->name, &qcq->napi);
218}
219
220static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
221{
222 struct ionic *ionic = lif->ionic;
223 int index;
224
225 index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
226 if (index == ionic->nintrs) {
227 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
228 __func__, index, ionic->nintrs);
229 return -ENOSPC;
230 }
231
232 set_bit(index, ionic->intrs);
233 ionic_intr_init(&ionic->idev, intr, index);
234
235 return 0;
236}
237
36ac2c50 238static void ionic_intr_free(struct ionic *ionic, int index)
1d062b7b 239{
c06107ca 240 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs)
36ac2c50 241 clear_bit(index, ionic->intrs);
1d062b7b
SN		 242}
243
0f3154e6
SN		 244static int ionic_qcq_enable(struct ionic_qcq *qcq)
245{
246 struct ionic_queue *q = &qcq->q;
247 struct ionic_lif *lif = q->lif;
248 struct ionic_dev *idev;
249 struct device *dev;
250
251 struct ionic_admin_ctx ctx = {
252 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
253 .cmd.q_control = {
254 .opcode = IONIC_CMD_Q_CONTROL,
255 .lif_index = cpu_to_le16(lif->index),
256 .type = q->type,
257 .index = cpu_to_le32(q->index),
258 .oper = IONIC_Q_ENABLE,
259 },
260 };
261
262 idev = &lif->ionic->idev;
263 dev = lif->ionic->dev;
264
265 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
266 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
267
268 if (qcq->flags & IONIC_QCQ_F_INTR) {
269 irq_set_affinity_hint(qcq->intr.vector,
270 &qcq->intr.affinity_mask);
271 napi_enable(&qcq->napi);
272 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
273 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
274 IONIC_INTR_MASK_CLEAR);
275 }
276
277 return ionic_adminq_post_wait(lif, &ctx);
278}
279
ba6ab8ac 280static int ionic_qcq_disable(struct ionic_qcq *qcq, bool send_to_hw)
0f3154e6 281{
7c737fc4
SN		 282 struct ionic_queue *q;
283 struct ionic_lif *lif;
ba6ab8ac 284 int err = 0;
0f3154e6
SN		 285
286 struct ionic_admin_ctx ctx = {
287 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
288 .cmd.q_control = {
289 .opcode = IONIC_CMD_Q_CONTROL,
0f3154e6
SN		 290 .oper = IONIC_Q_DISABLE,
291 },
292 };
293
7c737fc4
SN		 294 if (!qcq)
295 return -ENXIO;
0f3154e6 296
7c737fc4
SN		 297 q = &qcq->q;
298 lif = q->lif;
0f3154e6
SN		 299
300 if (qcq->flags & IONIC_QCQ_F_INTR) {
7c737fc4
SN		 301 struct ionic_dev *idev = &lif->ionic->idev;
302
04a83459 303 cancel_work_sync(&qcq->dim.work);
0f3154e6
SN		 304 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
305 IONIC_INTR_MASK_SET);
306 synchronize_irq(qcq->intr.vector);
307 irq_set_affinity_hint(qcq->intr.vector, NULL);
308 napi_disable(&qcq->napi);
309 }
310
ba6ab8ac
SN		 311 if (send_to_hw) {
312 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index);
313 ctx.cmd.q_control.type = q->type;
314 ctx.cmd.q_control.index = cpu_to_le32(q->index);
315 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n",
316 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
7c737fc4 317
ba6ab8ac
SN		 318 err = ionic_adminq_post_wait(lif, &ctx);
319 }
320
321 return err;
0f3154e6
SN		 322}
323
1d062b7b
SN		 324static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
325{
326 struct ionic_dev *idev = &lif->ionic->idev;
1d062b7b
SN		 327
328 if (!qcq)
329 return;
330
1d062b7b
SN		 331 if (!(qcq->flags & IONIC_QCQ_F_INITED))
332 return;
333
334 if (qcq->flags & IONIC_QCQ_F_INTR) {
335 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
336 IONIC_INTR_MASK_SET);
1d062b7b
SN		 337 netif_napi_del(&qcq->napi);
338 }
339
340 qcq->flags &= ~IONIC_QCQ_F_INITED;
341}
342
101b40a0
SN		 343static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
344{
345 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0)
346 return;
347
348 irq_set_affinity_hint(qcq->intr.vector, NULL);
349 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi);
350 qcq->intr.vector = 0;
351 ionic_intr_free(lif->ionic, qcq->intr.index);
352 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
353}
354
1d062b7b
SN		 355static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
356{
357 struct device *dev = lif->ionic->dev;
358
359 if (!qcq)
360 return;
361
2a8c2c1a
SN		 362 ionic_debugfs_del_qcq(qcq);
363
ea5a8b09
SN		 364 if (qcq->q_base) {
365 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa);
366 qcq->q_base = NULL;
367 qcq->q_base_pa = 0;
368 }
369
370 if (qcq->cq_base) {
371 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa);
372 qcq->cq_base = NULL;
373 qcq->cq_base_pa = 0;
374 }
375
376 if (qcq->sg_base) {
377 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa);
378 qcq->sg_base = NULL;
379 qcq->sg_base_pa = 0;
380 }
1d062b7b 381
101b40a0 382 ionic_qcq_intr_free(lif, qcq);
1d062b7b 383
a34e25ab
SN		 384 if (qcq->cq.info) {
385 devm_kfree(dev, qcq->cq.info);
386 qcq->cq.info = NULL;
387 }
388 if (qcq->q.info) {
389 devm_kfree(dev, qcq->q.info);
390 qcq->q.info = NULL;
391 }
1d062b7b
SN		 392}
393
394static void ionic_qcqs_free(struct ionic_lif *lif)
395{
0f3154e6 396 struct device *dev = lif->ionic->dev;
e768929d
SN		 397 struct ionic_qcq *adminqcq;
398 unsigned long irqflags;
0f3154e6 399
77ceb68e
SN		 400 if (lif->notifyqcq) {
401 ionic_qcq_free(lif, lif->notifyqcq);
101b40a0 402 devm_kfree(dev, lif->notifyqcq);
77ceb68e
SN		 403 lif->notifyqcq = NULL;
404 }
405
1d062b7b 406 if (lif->adminqcq) {
e768929d
SN		 407 spin_lock_irqsave(&lif->adminq_lock, irqflags);
408 adminqcq = READ_ONCE(lif->adminqcq);
1d062b7b 409 lif->adminqcq = NULL;
e768929d
SN		 410 spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
411 if (adminqcq) {
412 ionic_qcq_free(lif, adminqcq);
413 devm_kfree(dev, adminqcq);
414 }
1d062b7b 415 }
0f3154e6 416
a4674f34 417 if (lif->rxqcqs) {
34dec947
SN		 418 devm_kfree(dev, lif->rxqstats);
419 lif->rxqstats = NULL;
a4674f34
SN		 420 devm_kfree(dev, lif->rxqcqs);
421 lif->rxqcqs = NULL;
422 }
0f3154e6 423
a4674f34 424 if (lif->txqcqs) {
34dec947
SN		 425 devm_kfree(dev, lif->txqstats);
426 lif->txqstats = NULL;
a4674f34
SN		 427 devm_kfree(dev, lif->txqcqs);
428 lif->txqcqs = NULL;
429 }
1d062b7b
SN		 430}
431
77ceb68e
SN		 432static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
433 struct ionic_qcq *n_qcq)
434{
435 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) {
36ac2c50 436 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index);
77ceb68e
SN		 437 n_qcq->flags &= ~IONIC_QCQ_F_INTR;
438 }
439
440 n_qcq->intr.vector = src_qcq->intr.vector;
441 n_qcq->intr.index = src_qcq->intr.index;
442}
443
101b40a0
SN		 444static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
445{
446 int err;
447
448 if (!(qcq->flags & IONIC_QCQ_F_INTR)) {
449 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
450 return 0;
451 }
452
453 err = ionic_intr_alloc(lif, &qcq->intr);
454 if (err) {
455 netdev_warn(lif->netdev, "no intr for %s: %d\n",
456 qcq->q.name, err);
457 goto err_out;
458 }
459
460 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index);
461 if (err < 0) {
462 netdev_warn(lif->netdev, "no vector for %s: %d\n",
463 qcq->q.name, err);
464 goto err_out_free_intr;
465 }
466 qcq->intr.vector = err;
467 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index,
468 IONIC_INTR_MASK_SET);
469
470 err = ionic_request_irq(lif, qcq);
471 if (err) {
472 netdev_warn(lif->netdev, "irq request failed %d\n", err);
473 goto err_out_free_intr;
474 }
475
476 /* try to get the irq on the local numa node first */
477 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index,
478 dev_to_node(lif->ionic->dev));
479 if (qcq->intr.cpu != -1)
480 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask);
481
482 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
483 return 0;
484
485err_out_free_intr:
486 ionic_intr_free(lif->ionic, qcq->intr.index);
487err_out:
488 return err;
489}
490
1d062b7b
SN		 491static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
492 unsigned int index,
493 const char *name, unsigned int flags,
494 unsigned int num_descs, unsigned int desc_size,
495 unsigned int cq_desc_size,
496 unsigned int sg_desc_size,
497 unsigned int pid, struct ionic_qcq **qcq)
498{
499 struct ionic_dev *idev = &lif->ionic->idev;
1d062b7b
SN		 500 struct device *dev = lif->ionic->dev;
501 void *q_base, *cq_base, *sg_base;
502 dma_addr_t cq_base_pa = 0;
503 dma_addr_t sg_base_pa = 0;
504 dma_addr_t q_base_pa = 0;
505 struct ionic_qcq *new;
506 int err;
507
508 *qcq = NULL;
509
1d062b7b
SN		 510 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
511 if (!new) {
512 netdev_err(lif->netdev, "Cannot allocate queue structure\n");
513 err = -ENOMEM;
514 goto err_out;
515 }
516
f37bc346 517 new->q.dev = dev;
1d062b7b
SN		 518 new->flags = flags;
519
e7164200 520 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info),
1d062b7b
SN		 521 GFP_KERNEL);
522 if (!new->q.info) {
523 netdev_err(lif->netdev, "Cannot allocate queue info\n");
524 err = -ENOMEM;
ea5a8b09 525 goto err_out_free_qcq;
1d062b7b
SN		 526 }
527
528 new->q.type = type;
f37bc346 529 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems;
1d062b7b
SN		 530
531 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
532 desc_size, sg_desc_size, pid);
533 if (err) {
534 netdev_err(lif->netdev, "Cannot initialize queue\n");
ea5a8b09 535 goto err_out_free_q_info;
1d062b7b
SN		 536 }
537
101b40a0
SN		 538 err = ionic_alloc_qcq_interrupt(lif, new);
539 if (err)
540 goto err_out;
1d062b7b 541
e7164200 542 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info),
1d062b7b
SN		 543 GFP_KERNEL);
544 if (!new->cq.info) {
545 netdev_err(lif->netdev, "Cannot allocate completion queue info\n");
546 err = -ENOMEM;
0b064100 547 goto err_out_free_irq;
1d062b7b
SN		 548 }
549
550 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
551 if (err) {
552 netdev_err(lif->netdev, "Cannot initialize completion queue\n");
ea5a8b09 553 goto err_out_free_cq_info;
1d062b7b
SN		 554 }
555
9576a36c
SN		 556 if (flags & IONIC_QCQ_F_NOTIFYQ) {
557 int q_size, cq_size;
558
559 /* q & cq need to be contiguous in case of notifyq */
560 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE);
561 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE);
562
563 new->q_size = PAGE_SIZE + q_size + cq_size;
564 new->q_base = dma_alloc_coherent(dev, new->q_size,
565 &new->q_base_pa, GFP_KERNEL);
566 if (!new->q_base) {
567 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n");
568 err = -ENOMEM;
569 goto err_out_free_cq_info;
570 }
571 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
572 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
573 ionic_q_map(&new->q, q_base, q_base_pa);
574
575 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE);
576 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE);
577 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
578 ionic_cq_bind(&new->cq, &new->q);
579 } else {
580 new->q_size = PAGE_SIZE + (num_descs * desc_size);
581 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa,
582 GFP_KERNEL);
583 if (!new->q_base) {
584 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
585 err = -ENOMEM;
586 goto err_out_free_cq_info;
587 }
588 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
589 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
590 ionic_q_map(&new->q, q_base, q_base_pa);
591
592 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size);
593 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa,
594 GFP_KERNEL);
595 if (!new->cq_base) {
596 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n");
597 err = -ENOMEM;
598 goto err_out_free_q;
599 }
600 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE);
601 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE);
602 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
603 ionic_cq_bind(&new->cq, &new->q);
ea5a8b09 604 }
1d062b7b
SN		 605
606 if (flags & IONIC_QCQ_F_SG) {
ea5a8b09
SN		 607 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size);
608 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa,
609 GFP_KERNEL);
610 if (!new->sg_base) {
611 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n");
612 err = -ENOMEM;
613 goto err_out_free_cq;
614 }
615 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE);
616 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE);
1d062b7b
SN		 617 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
618 }
619
04a83459
SN		 620 INIT_WORK(&new->dim.work, ionic_dim_work);
621 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
622
1d062b7b
SN		 623 *qcq = new;
624
625 return 0;
626
ea5a8b09
SN		 627err_out_free_cq:
628 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa);
629err_out_free_q:
630 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa);
631err_out_free_cq_info:
632 devm_kfree(dev, new->cq.info);
0b064100 633err_out_free_irq:
101b40a0 634 if (flags & IONIC_QCQ_F_INTR) {
0b064100 635 devm_free_irq(dev, new->intr.vector, &new->napi);
36ac2c50 636 ionic_intr_free(lif->ionic, new->intr.index);
101b40a0 637 }
ea5a8b09
SN		 638err_out_free_q_info:
639 devm_kfree(dev, new->q.info);
640err_out_free_qcq:
641 devm_kfree(dev, new);
1d062b7b
SN		 642err_out:
643 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
644 return err;
645}
646
647static int ionic_qcqs_alloc(struct ionic_lif *lif)
648{
0f3154e6 649 struct device *dev = lif->ionic->dev;
1d062b7b
SN		 650 unsigned int flags;
651 int err;
652
653 flags = IONIC_QCQ_F_INTR;
654 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
655 IONIC_ADMINQ_LENGTH,
656 sizeof(struct ionic_admin_cmd),
657 sizeof(struct ionic_admin_comp),
658 0, lif->kern_pid, &lif->adminqcq);
659 if (err)
660 return err;
2a8c2c1a 661 ionic_debugfs_add_qcq(lif, lif->adminqcq);
1d062b7b 662
77ceb68e
SN		 663 if (lif->ionic->nnqs_per_lif) {
664 flags = IONIC_QCQ_F_NOTIFYQ;
665 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
666 flags, IONIC_NOTIFYQ_LENGTH,
667 sizeof(struct ionic_notifyq_cmd),
668 sizeof(union ionic_notifyq_comp),
669 0, lif->kern_pid, &lif->notifyqcq);
670 if (err)
34dec947 671 goto err_out;
2a8c2c1a 672 ionic_debugfs_add_qcq(lif, lif->notifyqcq);
77ceb68e
SN		 673
674 /* Let the notifyq ride on the adminq interrupt */
675 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
676 }
677
0f3154e6 678 err = -ENOMEM;
ee205626 679 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
230efff4 680 sizeof(*lif->txqcqs), GFP_KERNEL);
0f3154e6 681 if (!lif->txqcqs)
34dec947 682 goto err_out;
ee205626 683 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
230efff4 684 sizeof(*lif->rxqcqs), GFP_KERNEL);
0f3154e6 685 if (!lif->rxqcqs)
34dec947 686 goto err_out;
0f3154e6 687
f0790bcd 688 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1,
230efff4 689 sizeof(*lif->txqstats), GFP_KERNEL);
34dec947
SN		 690 if (!lif->txqstats)
691 goto err_out;
f0790bcd 692 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1,
230efff4 693 sizeof(*lif->rxqstats), GFP_KERNEL);
34dec947
SN		 694 if (!lif->rxqstats)
695 goto err_out;
77ceb68e 696
34dec947 697 return 0;
77ceb68e 698
34dec947
SN		 699err_out:
700 ionic_qcqs_free(lif);
77ceb68e
SN		 701 return err;
702}
703
f053e1f8
SN		 704static void ionic_qcq_sanitize(struct ionic_qcq *qcq)
705{
706 qcq->q.tail_idx = 0;
707 qcq->q.head_idx = 0;
708 qcq->cq.tail_idx = 0;
709 qcq->cq.done_color = 1;
710 memset(qcq->q_base, 0, qcq->q_size);
711 memset(qcq->cq_base, 0, qcq->cq_size);
712 memset(qcq->sg_base, 0, qcq->sg_size);
713}
714
0f3154e6
SN		 715static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
716{
717 struct device *dev = lif->ionic->dev;
718 struct ionic_queue *q = &qcq->q;
719 struct ionic_cq *cq = &qcq->cq;
720 struct ionic_admin_ctx ctx = {
721 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
722 .cmd.q_init = {
723 .opcode = IONIC_CMD_Q_INIT,
724 .lif_index = cpu_to_le16(lif->index),
725 .type = q->type,
5b3f3f2a 726 .ver = lif->qtype_info[q->type].version,
0f3154e6
SN		 727 .index = cpu_to_le32(q->index),
728 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
729 IONIC_QINIT_F_SG),
0f3154e6
SN		 730 .pid = cpu_to_le16(q->pid),
731 .ring_size = ilog2(q->num_descs),
732 .ring_base = cpu_to_le64(q->base_pa),
733 .cq_ring_base = cpu_to_le64(cq->base_pa),
734 .sg_ring_base = cpu_to_le64(q->sg_base_pa),
57a3a98d 735 .features = cpu_to_le64(q->features),
0f3154e6
SN		 736 },
737 };
fe8c30b5 738 unsigned int intr_index;
0f3154e6
SN		 739 int err;
740
2103ed2f
SN		 741 intr_index = qcq->intr.index;
742
fe8c30b5
SN		 743 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index);
744
0f3154e6
SN		 745 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
746 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
747 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
748 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
5b3f3f2a
SN		 749 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
750 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver);
fe8c30b5 751 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
0f3154e6 752
f053e1f8 753 ionic_qcq_sanitize(qcq);
49d3b493 754
0f3154e6
SN		 755 err = ionic_adminq_post_wait(lif, &ctx);
756 if (err)
757 return err;
758
759 q->hw_type = ctx.comp.q_init.hw_type;
760 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
761 q->dbval = IONIC_DBELL_QID(q->hw_index);
762
763 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
764 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
765
fe8c30b5
SN		 766 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
767 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi,
768 NAPI_POLL_WEIGHT);
769
0f3154e6
SN		 770 qcq->flags |= IONIC_QCQ_F_INITED;
771
0f3154e6
SN		 772 return 0;
773}
774
775static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
776{
777 struct device *dev = lif->ionic->dev;
778 struct ionic_queue *q = &qcq->q;
779 struct ionic_cq *cq = &qcq->cq;
780 struct ionic_admin_ctx ctx = {
781 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
782 .cmd.q_init = {
783 .opcode = IONIC_CMD_Q_INIT,
784 .lif_index = cpu_to_le16(lif->index),
785 .type = q->type,
5b3f3f2a 786 .ver = lif->qtype_info[q->type].version,
0f3154e6 787 .index = cpu_to_le32(q->index),
08f2e4b2
SN		 788 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
789 IONIC_QINIT_F_SG),
0f3154e6
SN		 790 .intr_index = cpu_to_le16(cq->bound_intr->index),
791 .pid = cpu_to_le16(q->pid),
792 .ring_size = ilog2(q->num_descs),
793 .ring_base = cpu_to_le64(q->base_pa),
794 .cq_ring_base = cpu_to_le64(cq->base_pa),
08f2e4b2 795 .sg_ring_base = cpu_to_le64(q->sg_base_pa),
57a3a98d 796 .features = cpu_to_le64(q->features),
0f3154e6
SN		 797 },
798 };
799 int err;
800
801 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
802 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
803 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
804 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
5b3f3f2a
SN		 805 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
806 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver);
fe8c30b5 807 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
0f3154e6 808
f053e1f8 809 ionic_qcq_sanitize(qcq);
49d3b493 810
0f3154e6
SN		 811 err = ionic_adminq_post_wait(lif, &ctx);
812 if (err)
813 return err;
814
815 q->hw_type = ctx.comp.q_init.hw_type;
816 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
817 q->dbval = IONIC_DBELL_QID(q->hw_index);
818
819 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
820 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
821
fe8c30b5
SN		 822 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
823 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
824 NAPI_POLL_WEIGHT);
825 else
826 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi,
827 NAPI_POLL_WEIGHT);
0f3154e6 828
0f3154e6
SN		 829 qcq->flags |= IONIC_QCQ_F_INITED;
830
0f3154e6
SN		 831 return 0;
832}
833
61db421d
SN		 834int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif)
835{
f0790bcd
SN		 836 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
837 unsigned int txq_i, flags;
838 struct ionic_qcq *txq;
839 u64 features;
840 int err;
841
842 mutex_lock(&lif->queue_lock);
843
844 if (lif->hwstamp_txq)
845 goto out;
846
847 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP;
848
849 num_desc = IONIC_MIN_TXRX_DESC;
850 desc_sz = sizeof(struct ionic_txq_desc);
851 comp_sz = 2 * sizeof(struct ionic_txq_comp);
852
853 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
854 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1))
855 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
856 else
857 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
858
859 txq_i = lif->ionic->ntxqs_per_lif;
860 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
861
862 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags,
863 num_desc, desc_sz, comp_sz, sg_desc_sz,
864 lif->kern_pid, &txq);
865 if (err)
866 goto err_qcq_alloc;
867
868 txq->q.features = features;
869
870 ionic_link_qcq_interrupts(lif->adminqcq, txq);
871 ionic_debugfs_add_qcq(lif, txq);
872
873 lif->hwstamp_txq = txq;
874
875 if (netif_running(lif->netdev)) {
876 err = ionic_lif_txq_init(lif, txq);
877 if (err)
878 goto err_qcq_init;
879
880 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
881 err = ionic_qcq_enable(txq);
882 if (err)
883 goto err_qcq_enable;
884 }
885 }
886
887out:
888 mutex_unlock(&lif->queue_lock);
889
61db421d 890 return 0;
f0790bcd
SN		 891
892err_qcq_enable:
893 ionic_lif_qcq_deinit(lif, txq);
894err_qcq_init:
895 lif->hwstamp_txq = NULL;
896 ionic_debugfs_del_qcq(txq);
897 ionic_qcq_free(lif, txq);
898 devm_kfree(lif->ionic->dev, txq);
899err_qcq_alloc:
900 mutex_unlock(&lif->queue_lock);
901 return err;
61db421d
SN		 902}
903
904int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif)
905{
f0790bcd
SN		 906 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
907 unsigned int rxq_i, flags;
908 struct ionic_qcq *rxq;
909 u64 features;
910 int err;
911
912 mutex_lock(&lif->queue_lock);
913
914 if (lif->hwstamp_rxq)
915 goto out;
916
917 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
918
919 num_desc = IONIC_MIN_TXRX_DESC;
920 desc_sz = sizeof(struct ionic_rxq_desc);
921 comp_sz = 2 * sizeof(struct ionic_rxq_comp);
922 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
923
924 rxq_i = lif->ionic->nrxqs_per_lif;
925 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG;
926
927 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags,
928 num_desc, desc_sz, comp_sz, sg_desc_sz,
929 lif->kern_pid, &rxq);
930 if (err)
931 goto err_qcq_alloc;
932
933 rxq->q.features = features;
934
935 ionic_link_qcq_interrupts(lif->adminqcq, rxq);
936 ionic_debugfs_add_qcq(lif, rxq);
937
938 lif->hwstamp_rxq = rxq;
939
940 if (netif_running(lif->netdev)) {
941 err = ionic_lif_rxq_init(lif, rxq);
942 if (err)
943 goto err_qcq_init;
944
945 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
946 ionic_rx_fill(&rxq->q);
947 err = ionic_qcq_enable(rxq);
948 if (err)
949 goto err_qcq_enable;
950 }
951 }
952
953out:
954 mutex_unlock(&lif->queue_lock);
955
61db421d 956 return 0;
f0790bcd
SN		 957
958err_qcq_enable:
959 ionic_lif_qcq_deinit(lif, rxq);
960err_qcq_init:
961 lif->hwstamp_rxq = NULL;
962 ionic_debugfs_del_qcq(rxq);
963 ionic_qcq_free(lif, rxq);
964 devm_kfree(lif->ionic->dev, rxq);
965err_qcq_alloc:
966 mutex_unlock(&lif->queue_lock);
967 return err;
61db421d
SN		 968}
969
970int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all)
971{
f0790bcd
SN		 972 struct ionic_queue_params qparam;
973
974 ionic_init_queue_params(lif, &qparam);
975
976 if (rx_all)
977 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
978 else
979 qparam.rxq_features = 0;
980
981 /* if we're not running, just set the values and return */
982 if (!netif_running(lif->netdev)) {
983 lif->rxq_features = qparam.rxq_features;
984 return 0;
985 }
986
987 return ionic_reconfigure_queues(lif, &qparam);
61db421d
SN		 988}
989
990int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode)
991{
f0790bcd
SN		 992 struct ionic_admin_ctx ctx = {
993 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
994 .cmd.lif_setattr = {
995 .opcode = IONIC_CMD_LIF_SETATTR,
996 .index = cpu_to_le16(lif->index),
997 .attr = IONIC_LIF_ATTR_TXSTAMP,
998 .txstamp_mode = cpu_to_le16(txstamp_mode),
999 },
1000 };
1001
1002 return ionic_adminq_post_wait(lif, &ctx);
1003}
1004
1005static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif)
1006{
1007 struct ionic_admin_ctx ctx = {
1008 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1009 .cmd.rx_filter_del = {
1010 .opcode = IONIC_CMD_RX_FILTER_DEL,
1011 .lif_index = cpu_to_le16(lif->index),
1012 },
1013 };
1014 struct ionic_rx_filter *f;
1015 u32 filter_id;
1016 int err;
1017
1018 spin_lock_bh(&lif->rx_filters.lock);
1019
1020 f = ionic_rx_filter_rxsteer(lif);
1021 if (!f) {
1022 spin_unlock_bh(&lif->rx_filters.lock);
1023 return;
1024 }
1025
1026 filter_id = f->filter_id;
1027 ionic_rx_filter_free(lif, f);
1028
1029 spin_unlock_bh(&lif->rx_filters.lock);
1030
1031 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id);
1032
1033 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id);
1034
1035 err = ionic_adminq_post_wait(lif, &ctx);
1036 if (err && err != -EEXIST)
1037 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id);
1038}
1039
1040static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1041{
1042 struct ionic_admin_ctx ctx = {
1043 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1044 .cmd.rx_filter_add = {
1045 .opcode = IONIC_CMD_RX_FILTER_ADD,
1046 .lif_index = cpu_to_le16(lif->index),
1047 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS),
1048 .pkt_class = cpu_to_le64(pkt_class),
1049 },
1050 };
1051 u8 qtype;
1052 u32 qid;
1053 int err;
1054
1055 if (!lif->hwstamp_rxq)
1056 return -EINVAL;
1057
1058 qtype = lif->hwstamp_rxq->q.type;
1059 ctx.cmd.rx_filter_add.qtype = qtype;
1060
1061 qid = lif->hwstamp_rxq->q.index;
1062 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid);
1063
1064 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n");
1065 err = ionic_adminq_post_wait(lif, &ctx);
1066 if (err && err != -EEXIST)
1067 return err;
1068
1069 return ionic_rx_filter_save(lif, 0, qid, 0, &ctx);
61db421d
SN		 1070}
1071
1072int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1073{
f0790bcd
SN		 1074 ionic_lif_del_hwstamp_rxfilt(lif);
1075
1076 if (!pkt_class)
1077 return 0;
1078
1079 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class);
61db421d
SN		 1080}
1081
77ceb68e
SN		 1082static bool ionic_notifyq_service(struct ionic_cq *cq,
1083 struct ionic_cq_info *cq_info)
1084{
1085 union ionic_notifyq_comp *comp = cq_info->cq_desc;
c672412f 1086 struct ionic_deferred_work *work;
77ceb68e
SN		 1087 struct net_device *netdev;
1088 struct ionic_queue *q;
1089 struct ionic_lif *lif;
1090 u64 eid;
1091
1092 q = cq->bound_q;
1093 lif = q->info[0].cb_arg;
1094 netdev = lif->netdev;
1095 eid = le64_to_cpu(comp->event.eid);
1096
1097 /* Have we run out of new completions to process? */
3fbc9bb6 1098 if ((s64)(eid - lif->last_eid) <= 0)
77ceb68e
SN		 1099 return false;
1100
1101 lif->last_eid = eid;
1102
1103 dev_dbg(lif->ionic->dev, "notifyq event:\n");
1104 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
1105 comp, sizeof(*comp), true);
1106
1107 switch (le16_to_cpu(comp->event.ecode)) {
1108 case IONIC_EVENT_LINK_CHANGE:
25cc5a5f 1109 ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
77ceb68e
SN		 1110 break;
1111 case IONIC_EVENT_RESET:
c672412f
SN		 1112 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1113 if (!work) {
c0c682ee 1114 netdev_err(lif->netdev, "Reset event dropped\n");
c672412f
SN		 1115 } else {
1116 work->type = IONIC_DW_TYPE_LIF_RESET;
1117 ionic_lif_deferred_enqueue(&lif->deferred, work);
1118 }
77ceb68e
SN		 1119 break;
1120 default:
5b3f3f2a 1121 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n",
77ceb68e
SN		 1122 comp->event.ecode, eid);
1123 break;
1124 }
1125
1126 return true;
1127}
1128
1d062b7b
SN		 1129static bool ionic_adminq_service(struct ionic_cq *cq,
1130 struct ionic_cq_info *cq_info)
1131{
1132 struct ionic_admin_comp *comp = cq_info->cq_desc;
1133
1134 if (!color_match(comp->color, cq->done_color))
1135 return false;
1136
1137 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index));
1138
1139 return true;
1140}
1141
1142static int ionic_adminq_napi(struct napi_struct *napi, int budget)
1143{
b4280948 1144 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr;
77ceb68e 1145 struct ionic_lif *lif = napi_to_cq(napi)->lif;
b4280948 1146 struct ionic_dev *idev = &lif->ionic->idev;
e768929d 1147 unsigned long irqflags;
b4280948 1148 unsigned int flags = 0;
a8771bfe
SN		 1149 int rx_work = 0;
1150 int tx_work = 0;
77ceb68e
SN		 1151 int n_work = 0;
1152 int a_work = 0;
b4280948 1153 int work_done;
a8771bfe 1154 int credits;
b4280948
SN		 1155
1156 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)
1157 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget,
1158 ionic_notifyq_service, NULL, NULL);
77ceb68e 1159
e768929d 1160 spin_lock_irqsave(&lif->adminq_lock, irqflags);
b4280948
SN		 1161 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED)
1162 a_work = ionic_cq_service(&lif->adminqcq->cq, budget,
1163 ionic_adminq_service, NULL, NULL);
e768929d 1164 spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
b4280948 1165
a8771bfe
SN		 1166 if (lif->hwstamp_rxq)
1167 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget,
1168 ionic_rx_service, NULL, NULL);
1169
1170 if (lif->hwstamp_txq)
1171 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget,
1172 ionic_tx_service, NULL, NULL);
1173
1174 work_done = max(max(n_work, a_work), max(rx_work, tx_work));
b4280948
SN		 1175 if (work_done < budget && napi_complete_done(napi, work_done)) {
1176 flags |= IONIC_INTR_CRED_UNMASK;
9b761574 1177 intr->rearm_count++;
b4280948 1178 }
77ceb68e 1179
b4280948
SN		 1180 if (work_done || flags) {
1181 flags |= IONIC_INTR_CRED_RESET_COALESCE;
a8771bfe
SN		 1182 credits = n_work + a_work + rx_work + tx_work;
1183 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags);
b4280948
SN		 1184 }
1185
1186 return work_done;
1d062b7b
SN		 1187}
1188
f64e0c56
SN		 1189void ionic_get_stats64(struct net_device *netdev,
1190 struct rtnl_link_stats64 *ns)
8d61aad4
SN		 1191{
1192 struct ionic_lif *lif = netdev_priv(netdev);
1193 struct ionic_lif_stats *ls;
1194
1195 memset(ns, 0, sizeof(*ns));
1196 ls = &lif->info->stats;
1197
1198 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
1199 le64_to_cpu(ls->rx_mcast_packets) +
1200 le64_to_cpu(ls->rx_bcast_packets);
1201
1202 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
1203 le64_to_cpu(ls->tx_mcast_packets) +
1204 le64_to_cpu(ls->tx_bcast_packets);
1205
1206 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
1207 le64_to_cpu(ls->rx_mcast_bytes) +
1208 le64_to_cpu(ls->rx_bcast_bytes);
1209
1210 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
1211 le64_to_cpu(ls->tx_mcast_bytes) +
1212 le64_to_cpu(ls->tx_bcast_bytes);
1213
1214 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
1215 le64_to_cpu(ls->rx_mcast_drop_packets) +
1216 le64_to_cpu(ls->rx_bcast_drop_packets);
1217
1218 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
1219 le64_to_cpu(ls->tx_mcast_drop_packets) +
1220 le64_to_cpu(ls->tx_bcast_drop_packets);
1221
1222 ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
1223
1224 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
1225
1226 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
1227 le64_to_cpu(ls->rx_queue_disabled) +
1228 le64_to_cpu(ls->rx_desc_fetch_error) +
1229 le64_to_cpu(ls->rx_desc_data_error);
1230
1231 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
1232 le64_to_cpu(ls->tx_queue_disabled) +
1233 le64_to_cpu(ls->tx_desc_fetch_error) +
1234 le64_to_cpu(ls->tx_desc_data_error);
1235
1236 ns->rx_errors = ns->rx_over_errors +
1237 ns->rx_missed_errors;
1238
1239 ns->tx_errors = ns->tx_aborted_errors;
1240}
1241
2a654540
SN		 1242static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr)
1243{
1244 struct ionic_admin_ctx ctx = {
1245 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1246 .cmd.rx_filter_add = {
1247 .opcode = IONIC_CMD_RX_FILTER_ADD,
1248 .lif_index = cpu_to_le16(lif->index),
1249 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC),
1250 },
1251 };
1252 struct ionic_rx_filter *f;
1253 int err;
1254
1255 /* don't bother if we already have it */
1256 spin_lock_bh(&lif->rx_filters.lock);
1257 f = ionic_rx_filter_by_addr(lif, addr);
1258 spin_unlock_bh(&lif->rx_filters.lock);
1259 if (f)
1260 return 0;
1261
cbec2153 1262 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr);
2a654540
SN		 1263
1264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN);
1265 err = ionic_adminq_post_wait(lif, &ctx);
53faea3d 1266 if (err && err != -EEXIST)
2a654540
SN		 1267 return err;
1268
1269 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
1270}
1271
1272static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr)
1273{
1274 struct ionic_admin_ctx ctx = {
1275 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1276 .cmd.rx_filter_del = {
1277 .opcode = IONIC_CMD_RX_FILTER_DEL,
1278 .lif_index = cpu_to_le16(lif->index),
1279 },
1280 };
1281 struct ionic_rx_filter *f;
1282 int err;
1283
1284 spin_lock_bh(&lif->rx_filters.lock);
1285 f = ionic_rx_filter_by_addr(lif, addr);
1286 if (!f) {
1287 spin_unlock_bh(&lif->rx_filters.lock);
1288 return -ENOENT;
1289 }
1290
cbec2153
SN		 1291 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n",
1292 addr, f->filter_id);
1293
2a654540
SN		 1294 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
1295 ionic_rx_filter_free(lif, f);
1296 spin_unlock_bh(&lif->rx_filters.lock);
1297
1298 err = ionic_adminq_post_wait(lif, &ctx);
53faea3d 1299 if (err && err != -EEXIST)
2a654540
SN		 1300 return err;
1301
2a654540
SN		 1302 return 0;
1303}
1304
1800eee1
SAS		 1305static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add,
1306 bool can_sleep)
2a654540 1307{
2a654540
SN		 1308 struct ionic_deferred_work *work;
1309 unsigned int nmfilters;
1310 unsigned int nufilters;
1311
1312 if (add) {
1313 /* Do we have space for this filter? We test the counters
1314 * here before checking the need for deferral so that we
1315 * can return an overflow error to the stack.
1316 */
bb9f80f3
SN		 1317 nmfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);
1318 nufilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
2a654540
SN		 1319
1320 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters))
1321 lif->nmcast++;
1322 else if (!is_multicast_ether_addr(addr) &&
1323 lif->nucast < nufilters)
1324 lif->nucast++;
1325 else
1326 return -ENOSPC;
1327 } else {
1328 if (is_multicast_ether_addr(addr) && lif->nmcast)
1329 lif->nmcast--;
1330 else if (!is_multicast_ether_addr(addr) && lif->nucast)
1331 lif->nucast--;
1332 }
1333
1800eee1 1334 if (!can_sleep) {
2a654540 1335 work = kzalloc(sizeof(*work), GFP_ATOMIC);
c0c682ee 1336 if (!work)
2a654540 1337 return -ENOMEM;
2a654540
SN		 1338 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD :
1339 IONIC_DW_TYPE_RX_ADDR_DEL;
1340 memcpy(work->addr, addr, ETH_ALEN);
1341 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
1342 add ? "add" : "del", addr);
1343 ionic_lif_deferred_enqueue(&lif->deferred, work);
1344 } else {
1345 netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
1346 add ? "add" : "del", addr);
1347 if (add)
1348 return ionic_lif_addr_add(lif, addr);
1349 else
1350 return ionic_lif_addr_del(lif, addr);
1351 }
1352
1353 return 0;
1354}
1355
1356static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
1357{
7c8d008c 1358 return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR, CAN_SLEEP);
1800eee1
SAS		 1359}
1360
1361static int ionic_ndo_addr_add(struct net_device *netdev, const u8 *addr)
1362{
7c8d008c 1363 return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR, CAN_NOT_SLEEP);
2a654540
SN		 1364}
1365
1366static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
1367{
7c8d008c 1368 return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR, CAN_SLEEP);
1800eee1
SAS		 1369}
1370
1371static int ionic_ndo_addr_del(struct net_device *netdev, const u8 *addr)
1372{
7c8d008c 1373 return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR, CAN_NOT_SLEEP);
2a654540
SN		 1374}
1375
1376static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode)
1377{
1378 struct ionic_admin_ctx ctx = {
1379 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1380 .cmd.rx_mode_set = {
1381 .opcode = IONIC_CMD_RX_MODE_SET,
1382 .lif_index = cpu_to_le16(lif->index),
1383 .rx_mode = cpu_to_le16(rx_mode),
1384 },
1385 };
1386 char buf[128];
1387 int err;
1388 int i;
1389#define REMAIN(__x) (sizeof(buf) - (__x))
1390
38e0f746
TI		 1391 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
1392 lif->rx_mode, rx_mode);
2a654540 1393 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
38e0f746 1394 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
2a654540 1395 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
38e0f746 1396 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
2a654540 1397 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
38e0f746 1398 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
2a654540 1399 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
38e0f746 1400 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
2a654540 1401 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
38e0f746 1402 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
2a654540
SN		 1403 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf);
1404
1405 err = ionic_adminq_post_wait(lif, &ctx);
1406 if (err)
1407 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n",
1408 rx_mode, err);
1409 else
1410 lif->rx_mode = rx_mode;
1411}
1412
81dbc241 1413static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep)
2a654540
SN		 1414{
1415 struct ionic_lif *lif = netdev_priv(netdev);
e94f76bb 1416 struct ionic_deferred_work *work;
2a654540
SN		 1417 unsigned int nfilters;
1418 unsigned int rx_mode;
1419
2a654540
SN		 1420 rx_mode = IONIC_RX_MODE_F_UNICAST;
1421 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
1422 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
1423 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
1424 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;
1425
1426 /* sync unicast addresses
1427 * next check to see if we're in an overflow state
1428 * if so, we track that we overflowed and enable NIC PROMISC
1429 * else if the overflow is set and not needed
1430 * we remove our overflow flag and check the netdev flags
1431 * to see if we can disable NIC PROMISC
1432 */
81dbc241 1433 if (can_sleep)
e0243e19 1434 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
81dbc241
SN		 1435 else
1436 __dev_uc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del);
bb9f80f3 1437 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
2a654540
SN		 1438 if (netdev_uc_count(netdev) + 1 > nfilters) {
1439 rx_mode |= IONIC_RX_MODE_F_PROMISC;
1440 lif->uc_overflow = true;
1441 } else if (lif->uc_overflow) {
1442 lif->uc_overflow = false;
1443 if (!(netdev->flags & IFF_PROMISC))
1444 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
1445 }
1446
1447 /* same for multicast */
81dbc241 1448 if (can_sleep)
e0243e19 1449 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
81dbc241
SN		 1450 else
1451 __dev_mc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del);
bb9f80f3 1452 nfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);
2a654540
SN		 1453 if (netdev_mc_count(netdev) > nfilters) {
1454 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
1455 lif->mc_overflow = true;
1456 } else if (lif->mc_overflow) {
1457 lif->mc_overflow = false;
1458 if (!(netdev->flags & IFF_ALLMULTI))
1459 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
1460 }
1461
e94f76bb 1462 if (lif->rx_mode != rx_mode) {
81dbc241 1463 if (!can_sleep) {
e94f76bb
SN		 1464 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1465 if (!work) {
c0c682ee 1466 netdev_err(lif->netdev, "rxmode change dropped\n");
e94f76bb
SN		 1467 return;
1468 }
1469 work->type = IONIC_DW_TYPE_RX_MODE;
1470 work->rx_mode = rx_mode;
1471 netdev_dbg(lif->netdev, "deferred: rx_mode\n");
1472 ionic_lif_deferred_enqueue(&lif->deferred, work);
1473 } else {
1474 ionic_lif_rx_mode(lif, rx_mode);
1475 }
1476 }
1800eee1
SAS		 1477}
1478
1479static void ionic_ndo_set_rx_mode(struct net_device *netdev)
1480{
7c8d008c 1481 ionic_set_rx_mode(netdev, CAN_NOT_SLEEP);
2a654540
SN		 1482}
1483
beead698
SN		 1484static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
1485{
1486 u64 wanted = 0;
1487
1488 if (features & NETIF_F_HW_VLAN_CTAG_TX)
1489 wanted |= IONIC_ETH_HW_VLAN_TX_TAG;
1490 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1491 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP;
1492 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1493 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER;
1494 if (features & NETIF_F_RXHASH)
1495 wanted |= IONIC_ETH_HW_RX_HASH;
1496 if (features & NETIF_F_RXCSUM)
1497 wanted |= IONIC_ETH_HW_RX_CSUM;
1498 if (features & NETIF_F_SG)
1499 wanted |= IONIC_ETH_HW_TX_SG;
1500 if (features & NETIF_F_HW_CSUM)
1501 wanted |= IONIC_ETH_HW_TX_CSUM;
1502 if (features & NETIF_F_TSO)
1503 wanted |= IONIC_ETH_HW_TSO;
1504 if (features & NETIF_F_TSO6)
1505 wanted |= IONIC_ETH_HW_TSO_IPV6;
1506 if (features & NETIF_F_TSO_ECN)
1507 wanted |= IONIC_ETH_HW_TSO_ECN;
1508 if (features & NETIF_F_GSO_GRE)
1509 wanted |= IONIC_ETH_HW_TSO_GRE;
1510 if (features & NETIF_F_GSO_GRE_CSUM)
1511 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM;
1512 if (features & NETIF_F_GSO_IPXIP4)
1513 wanted |= IONIC_ETH_HW_TSO_IPXIP4;
1514 if (features & NETIF_F_GSO_IPXIP6)
1515 wanted |= IONIC_ETH_HW_TSO_IPXIP6;
1516 if (features & NETIF_F_GSO_UDP_TUNNEL)
1517 wanted |= IONIC_ETH_HW_TSO_UDP;
1518 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
1519 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM;
1520
1521 return cpu_to_le64(wanted);
1522}
1523
1524static int ionic_set_nic_features(struct ionic_lif *lif,
1525 netdev_features_t features)
1526{
1527 struct device *dev = lif->ionic->dev;
1528 struct ionic_admin_ctx ctx = {
1529 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1530 .cmd.lif_setattr = {
1531 .opcode = IONIC_CMD_LIF_SETATTR,
1532 .index = cpu_to_le16(lif->index),
1533 .attr = IONIC_LIF_ATTR_FEATURES,
1534 },
1535 };
1536 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG |
1537 IONIC_ETH_HW_VLAN_RX_STRIP |
1538 IONIC_ETH_HW_VLAN_RX_FILTER;
75fcb75b 1539 u64 old_hw_features;
beead698
SN		 1540 int err;
1541
1542 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
a8771bfe 1543
afeefec6
SN		 1544 if (lif->phc)
1545 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP);
1546
beead698
SN		 1547 err = ionic_adminq_post_wait(lif, &ctx);
1548 if (err)
1549 return err;
1550
75fcb75b 1551 old_hw_features = lif->hw_features;
beead698
SN		 1552 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
1553 ctx.comp.lif_setattr.features);
1554
75fcb75b
SN		 1555 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
1556 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1557
beead698
SN		 1558 if ((vlan_flags & features) &&
1559 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
1560 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
1561
1562 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1563 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
1564 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1565 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
1566 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1567 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
1568 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1569 dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
1570 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1571 dev_dbg(dev, "feature ETH_HW_TX_SG\n");
1572 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1573 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
1574 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1575 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
1576 if (lif->hw_features & IONIC_ETH_HW_TSO)
1577 dev_dbg(dev, "feature ETH_HW_TSO\n");
1578 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1579 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
1580 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1581 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
1582 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1583 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
1584 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1585 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
1586 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1587 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
1588 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1589 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
1590 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1591 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
1592 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1593 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
afeefec6
SN		 1594 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP)
1595 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n");
beead698
SN		 1596
1597 return 0;
1598}
1599
1600static int ionic_init_nic_features(struct ionic_lif *lif)
1601{
1602 struct net_device *netdev = lif->netdev;
1603 netdev_features_t features;
1604 int err;
1605
1606 /* set up what we expect to support by default */
1607 features = NETIF_F_HW_VLAN_CTAG_TX |
1608 NETIF_F_HW_VLAN_CTAG_RX |
1609 NETIF_F_HW_VLAN_CTAG_FILTER |
1610 NETIF_F_RXHASH |
1611 NETIF_F_SG |
1612 NETIF_F_HW_CSUM |
1613 NETIF_F_RXCSUM |
1614 NETIF_F_TSO |
1615 NETIF_F_TSO6 |
1616 NETIF_F_TSO_ECN;
1617
1618 err = ionic_set_nic_features(lif, features);
1619 if (err)
1620 return err;
1621
1622 /* tell the netdev what we actually can support */
1623 netdev->features |= NETIF_F_HIGHDMA;
1624
1625 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1626 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
1627 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1628 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1629 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1630 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1631 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1632 netdev->hw_features |= NETIF_F_RXHASH;
1633 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1634 netdev->hw_features |= NETIF_F_SG;
1635
1636 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1637 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
1638 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1639 netdev->hw_enc_features |= NETIF_F_RXCSUM;
1640 if (lif->hw_features & IONIC_ETH_HW_TSO)
1641 netdev->hw_enc_features |= NETIF_F_TSO;
1642 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1643 netdev->hw_enc_features |= NETIF_F_TSO6;
1644 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1645 netdev->hw_enc_features |= NETIF_F_TSO_ECN;
1646 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1647 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
1648 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1649 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
1650 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1651 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
1652 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1653 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
1654 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1655 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
1656 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1657 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1658
1659 netdev->hw_features |= netdev->hw_enc_features;
1660 netdev->features |= netdev->hw_features;
ef7232da 1661 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES;
beead698 1662
c672412f
SN		 1663 netdev->priv_flags |= IFF_UNICAST_FLT |
1664 IFF_LIVE_ADDR_CHANGE;
beead698
SN		 1665
1666 return 0;
1667}
1668
1669static int ionic_set_features(struct net_device *netdev,
1670 netdev_features_t features)
1671{
1672 struct ionic_lif *lif = netdev_priv(netdev);
1673 int err;
1674
1675 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
1676 __func__, (u64)lif->netdev->features, (u64)features);
1677
1678 err = ionic_set_nic_features(lif, features);
1679
1680 return err;
1681}
1682
1683static int ionic_set_mac_address(struct net_device *netdev, void *sa)
1684{
2a654540
SN		 1685 struct sockaddr *addr = sa;
1686 u8 *mac;
1687 int err;
1688
1689 mac = (u8 *)addr->sa_data;
1690 if (ether_addr_equal(netdev->dev_addr, mac))
1691 return 0;
1692
1693 err = eth_prepare_mac_addr_change(netdev, addr);
1694 if (err)
1695 return err;
1696
1697 if (!is_zero_ether_addr(netdev->dev_addr)) {
1698 netdev_info(netdev, "deleting mac addr %pM\n",
1699 netdev->dev_addr);
1700 ionic_addr_del(netdev, netdev->dev_addr);
1701 }
1702
1703 eth_commit_mac_addr_change(netdev, addr);
1704 netdev_info(netdev, "updating mac addr %pM\n", mac);
1705
1706 return ionic_addr_add(netdev, mac);
beead698
SN		 1707}
1708
f053e1f8
SN		 1709static void ionic_stop_queues_reconfig(struct ionic_lif *lif)
1710{
1711 /* Stop and clean the queues before reconfiguration */
1712 mutex_lock(&lif->queue_lock);
1713 netif_device_detach(lif->netdev);
1714 ionic_stop_queues(lif);
1715 ionic_txrx_deinit(lif);
1716}
1717
1718static int ionic_start_queues_reconfig(struct ionic_lif *lif)
1719{
1720 int err;
1721
1722 /* Re-init the queues after reconfiguration */
1723
1724 /* The only way txrx_init can fail here is if communication
1725 * with FW is suddenly broken. There's not much we can do
1726 * at this point - error messages have already been printed,
1727 * so we can continue on and the user can eventually do a
1728 * DOWN and UP to try to reset and clear the issue.
1729 */
1730 err = ionic_txrx_init(lif);
1731 mutex_unlock(&lif->queue_lock);
25cc5a5f 1732 ionic_link_status_check_request(lif, CAN_SLEEP);
f053e1f8
SN		 1733 netif_device_attach(lif->netdev);
1734
1735 return err;
1736}
1737
beead698
SN		 1738static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
1739{
1740 struct ionic_lif *lif = netdev_priv(netdev);
1741 struct ionic_admin_ctx ctx = {
1742 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1743 .cmd.lif_setattr = {
1744 .opcode = IONIC_CMD_LIF_SETATTR,
1745 .index = cpu_to_le16(lif->index),
1746 .attr = IONIC_LIF_ATTR_MTU,
1747 .mtu = cpu_to_le32(new_mtu),
1748 },
1749 };
1750 int err;
1751
1752 err = ionic_adminq_post_wait(lif, &ctx);
1753 if (err)
1754 return err;
1755
f053e1f8 1756 /* if we're not running, nothing more to do */
79ba55a3
SN		 1757 if (!netif_running(netdev)) {
1758 netdev->mtu = new_mtu;
f053e1f8 1759 return 0;
79ba55a3 1760 }
beead698 1761
f053e1f8 1762 ionic_stop_queues_reconfig(lif);
79ba55a3 1763 netdev->mtu = new_mtu;
f053e1f8 1764 return ionic_start_queues_reconfig(lif);
beead698
SN		 1765}
1766
8c15440b
SN		 1767static void ionic_tx_timeout_work(struct work_struct *ws)
1768{
1769 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);
1770
8c775344
SN		 1771 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
1772 return;
8c15440b 1773
6f7d6f0f
SN		 1774 /* if we were stopped before this scheduled job was launched,
1775 * don't bother the queues as they are already stopped.
1776 */
1777 if (!netif_running(lif->netdev))
1778 return;
1779
1780 ionic_stop_queues_reconfig(lif);
1781 ionic_start_queues_reconfig(lif);
8c15440b
SN		 1782}
1783
0290bd29 1784static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
beead698 1785{
8c15440b
SN		 1786 struct ionic_lif *lif = netdev_priv(netdev);
1787
8c775344 1788 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue);
8c15440b 1789 schedule_work(&lif->tx_timeout_work);
beead698
SN		 1790}
1791
1792static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1793 u16 vid)
1794{
2a654540
SN		 1795 struct ionic_lif *lif = netdev_priv(netdev);
1796 struct ionic_admin_ctx ctx = {
1797 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1798 .cmd.rx_filter_add = {
1799 .opcode = IONIC_CMD_RX_FILTER_ADD,
1800 .lif_index = cpu_to_le16(lif->index),
1801 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN),
1802 .vlan.vlan = cpu_to_le16(vid),
1803 },
1804 };
1805 int err;
1806
cbec2153 1807 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid);
2a654540
SN		 1808 err = ionic_adminq_post_wait(lif, &ctx);
1809 if (err)
1810 return err;
1811
2a654540 1812 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
beead698
SN		 1813}
1814
1815static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1816 u16 vid)
1817{
2a654540
SN		 1818 struct ionic_lif *lif = netdev_priv(netdev);
1819 struct ionic_admin_ctx ctx = {
1820 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1821 .cmd.rx_filter_del = {
1822 .opcode = IONIC_CMD_RX_FILTER_DEL,
1823 .lif_index = cpu_to_le16(lif->index),
1824 },
1825 };
1826 struct ionic_rx_filter *f;
1827
1828 spin_lock_bh(&lif->rx_filters.lock);
1829
1830 f = ionic_rx_filter_by_vlan(lif, vid);
1831 if (!f) {
1832 spin_unlock_bh(&lif->rx_filters.lock);
1833 return -ENOENT;
1834 }
1835
cbec2153
SN		 1836 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n",
1837 vid, f->filter_id);
2a654540
SN		 1838
1839 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
1840 ionic_rx_filter_free(lif, f);
1841 spin_unlock_bh(&lif->rx_filters.lock);
1842
1843 return ionic_adminq_post_wait(lif, &ctx);
beead698
SN		 1844}
1845
aa319881
SN		 1846int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
1847 const u8 *key, const u32 *indir)
1848{
1849 struct ionic_admin_ctx ctx = {
1850 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1851 .cmd.lif_setattr = {
1852 .opcode = IONIC_CMD_LIF_SETATTR,
1853 .attr = IONIC_LIF_ATTR_RSS,
aa319881
SN		 1854 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
1855 },
1856 };
1857 unsigned int i, tbl_sz;
1858
75fcb75b
SN		 1859 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
1860 lif->rss_types = types;
1861 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types);
1862 }
aa319881
SN		 1863
1864 if (key)
1865 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1866
1867 if (indir) {
1868 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1869 for (i = 0; i < tbl_sz; i++)
1870 lif->rss_ind_tbl[i] = indir[i];
1871 }
1872
1873 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1874 IONIC_RSS_HASH_KEY_SIZE);
1875
1876 return ionic_adminq_post_wait(lif, &ctx);
1877}
1878
1879static int ionic_lif_rss_init(struct ionic_lif *lif)
1880{
aa319881
SN		 1881 unsigned int tbl_sz;
1882 unsigned int i;
1883
aa319881
SN		 1884 lif->rss_types = IONIC_RSS_TYPE_IPV4 |
1885 IONIC_RSS_TYPE_IPV4_TCP |
1886 IONIC_RSS_TYPE_IPV4_UDP |
1887 IONIC_RSS_TYPE_IPV6 |
1888 IONIC_RSS_TYPE_IPV6_TCP |
1889 IONIC_RSS_TYPE_IPV6_UDP;
1890
1891 /* Fill indirection table with 'default' values */
1892 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1893 for (i = 0; i < tbl_sz; i++)
1894 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
1895
ffac2027 1896 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
aa319881
SN		 1897}
1898
ffac2027 1899static void ionic_lif_rss_deinit(struct ionic_lif *lif)
aa319881 1900{
ffac2027
SN		 1901 int tbl_sz;
1902
1903 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1904 memset(lif->rss_ind_tbl, 0, tbl_sz);
1905 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);
1906
1907 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
aa319881
SN		 1908}
1909
e7e8e087
SN		 1910static void ionic_lif_quiesce(struct ionic_lif *lif)
1911{
1912 struct ionic_admin_ctx ctx = {
1913 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1914 .cmd.lif_setattr = {
1915 .opcode = IONIC_CMD_LIF_SETATTR,
1916 .index = cpu_to_le16(lif->index),
1917 .attr = IONIC_LIF_ATTR_STATE,
1918 .state = IONIC_LIF_QUIESCE,
1919 },
1920 };
1921 int err;
1922
1923 err = ionic_adminq_post_wait(lif, &ctx);
1924 if (err)
1925 netdev_err(lif->netdev, "lif quiesce failed %d\n", err);
1926}
1927
0f3154e6
SN		 1928static void ionic_txrx_disable(struct ionic_lif *lif)
1929{
1930 unsigned int i;
ba6ab8ac 1931 int err = 0;
0f3154e6 1932
d5eddde5 1933 if (lif->txqcqs) {
ba6ab8ac
SN		 1934 for (i = 0; i < lif->nxqs; i++)
1935 err = ionic_qcq_disable(lif->txqcqs[i], (err != -ETIMEDOUT));
d5eddde5
SN		 1936 }
1937
f0790bcd
SN		 1938 if (lif->hwstamp_txq)
1939 err = ionic_qcq_disable(lif->hwstamp_txq, (err != -ETIMEDOUT));
1940
d5eddde5 1941 if (lif->rxqcqs) {
ba6ab8ac
SN		 1942 for (i = 0; i < lif->nxqs; i++)
1943 err = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT));
0f3154e6 1944 }
e7e8e087 1945
f0790bcd
SN		 1946 if (lif->hwstamp_rxq)
1947 err = ionic_qcq_disable(lif->hwstamp_rxq, (err != -ETIMEDOUT));
1948
e7e8e087 1949 ionic_lif_quiesce(lif);
0f3154e6
SN		 1950}
1951
1952static void ionic_txrx_deinit(struct ionic_lif *lif)
1953{
1954 unsigned int i;
1955
d5eddde5 1956 if (lif->txqcqs) {
101b40a0 1957 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) {
34dec947
SN		 1958 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1959 ionic_tx_flush(&lif->txqcqs[i]->cq);
1960 ionic_tx_empty(&lif->txqcqs[i]->q);
d5eddde5
SN		 1961 }
1962 }
0f3154e6 1963
d5eddde5 1964 if (lif->rxqcqs) {
101b40a0 1965 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) {
34dec947 1966 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
34dec947 1967 ionic_rx_empty(&lif->rxqcqs[i]->q);
d5eddde5 1968 }
0f3154e6 1969 }
49d3b493 1970 lif->rx_mode = 0;
a8771bfe
SN		 1971
1972 if (lif->hwstamp_txq) {
1973 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq);
1974 ionic_tx_flush(&lif->hwstamp_txq->cq);
1975 ionic_tx_empty(&lif->hwstamp_txq->q);
1976 }
1977
1978 if (lif->hwstamp_rxq) {
1979 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq);
1980 ionic_rx_empty(&lif->hwstamp_rxq->q);
1981 }
0f3154e6
SN		 1982}
1983
1984static void ionic_txrx_free(struct ionic_lif *lif)
1985{
1986 unsigned int i;
1987
d5eddde5 1988 if (lif->txqcqs) {
101b40a0 1989 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) {
34dec947 1990 ionic_qcq_free(lif, lif->txqcqs[i]);
101b40a0 1991 devm_kfree(lif->ionic->dev, lif->txqcqs[i]);
34dec947 1992 lif->txqcqs[i] = NULL;
d5eddde5
SN		 1993 }
1994 }
0f3154e6 1995
d5eddde5 1996 if (lif->rxqcqs) {
101b40a0 1997 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
34dec947 1998 ionic_qcq_free(lif, lif->rxqcqs[i]);
101b40a0 1999 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]);
34dec947 2000 lif->rxqcqs[i] = NULL;
d5eddde5 2001 }
0f3154e6 2002 }
f0790bcd
SN		 2003
2004 if (lif->hwstamp_txq) {
2005 ionic_qcq_free(lif, lif->hwstamp_txq);
2006 devm_kfree(lif->ionic->dev, lif->hwstamp_txq);
2007 lif->hwstamp_txq = NULL;
2008 }
2009
2010 if (lif->hwstamp_rxq) {
2011 ionic_qcq_free(lif, lif->hwstamp_rxq);
2012 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq);
2013 lif->hwstamp_rxq = NULL;
2014 }
0f3154e6
SN		 2015}
2016
2017static int ionic_txrx_alloc(struct ionic_lif *lif)
2018{
33c252e1
SN		 2019 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
2020 unsigned int flags, i;
0f3154e6
SN		 2021 int err = 0;
2022
0ec9f666
SN		 2023 num_desc = lif->ntxq_descs;
2024 desc_sz = sizeof(struct ionic_txq_desc);
2025 comp_sz = sizeof(struct ionic_txq_comp);
2026
5b3f3f2a
SN		 2027 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2028 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2029 sizeof(struct ionic_txq_sg_desc_v1))
2030 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
2031 else
2032 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
2033
0f3154e6 2034 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
fe8c30b5
SN		 2035 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
2036 flags |= IONIC_QCQ_F_INTR;
0f3154e6
SN		 2037 for (i = 0; i < lif->nxqs; i++) {
2038 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
0ec9f666 2039 num_desc, desc_sz, comp_sz, sg_desc_sz,
34dec947 2040 lif->kern_pid, &lif->txqcqs[i]);
0f3154e6
SN		 2041 if (err)
2042 goto err_out;
2043
04a83459 2044 if (flags & IONIC_QCQ_F_INTR) {
fe8c30b5 2045 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
34dec947 2046 lif->txqcqs[i]->intr.index,
fe8c30b5 2047 lif->tx_coalesce_hw);
04a83459
SN		 2048 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
2049 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
2050 }
fe8c30b5 2051
34dec947 2052 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
0f3154e6
SN		 2053 }
2054
08f2e4b2 2055 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR;
0ec9f666
SN		 2056
2057 num_desc = lif->nrxq_descs;
2058 desc_sz = sizeof(struct ionic_rxq_desc);
2059 comp_sz = sizeof(struct ionic_rxq_comp);
2060 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
2061
2062 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC)
2063 comp_sz *= 2;
2064
0f3154e6
SN		 2065 for (i = 0; i < lif->nxqs; i++) {
2066 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
0ec9f666 2067 num_desc, desc_sz, comp_sz, sg_desc_sz,
34dec947 2068 lif->kern_pid, &lif->rxqcqs[i]);
0f3154e6
SN		 2069 if (err)
2070 goto err_out;
2071
0ec9f666
SN		 2072 lif->rxqcqs[i]->q.features = lif->rxq_features;
2073
8c15440b 2074 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
34dec947 2075 lif->rxqcqs[i]->intr.index,
780eded3 2076 lif->rx_coalesce_hw);
04a83459
SN		 2077 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state))
2078 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw;
fe8c30b5
SN		 2079
2080 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
34dec947
SN		 2081 ionic_link_qcq_interrupts(lif->rxqcqs[i],
2082 lif->txqcqs[i]);
fe8c30b5 2083
34dec947 2084 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
0f3154e6
SN		 2085 }
2086
2087 return 0;
2088
2089err_out:
2090 ionic_txrx_free(lif);
2091
2092 return err;
2093}
2094
2095static int ionic_txrx_init(struct ionic_lif *lif)
2096{
2097 unsigned int i;
2098 int err;
2099
2100 for (i = 0; i < lif->nxqs; i++) {
34dec947 2101 err = ionic_lif_txq_init(lif, lif->txqcqs[i]);
0f3154e6
SN		 2102 if (err)
2103 goto err_out;
2104
34dec947 2105 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]);
0f3154e6 2106 if (err) {
34dec947 2107 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
0f3154e6
SN		 2108 goto err_out;
2109 }
2110 }
2111
aa319881
SN		 2112 if (lif->netdev->features & NETIF_F_RXHASH)
2113 ionic_lif_rss_init(lif);
2114
7c8d008c 2115 ionic_set_rx_mode(lif->netdev, CAN_SLEEP);
0f3154e6
SN		 2116
2117 return 0;
2118
2119err_out:
2120 while (i--) {
34dec947
SN		 2121 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2122 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
0f3154e6
SN		 2123 }
2124
2125 return err;
2126}
2127
2128static int ionic_txrx_enable(struct ionic_lif *lif)
2129{
ba6ab8ac 2130 int derr = 0;
0f3154e6
SN		 2131 int i, err;
2132
2133 for (i = 0; i < lif->nxqs; i++) {
7c737fc4
SN		 2134 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) {
2135 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i);
2136 err = -ENXIO;
2137 goto err_out;
2138 }
2139
34dec947
SN		 2140 ionic_rx_fill(&lif->rxqcqs[i]->q);
2141 err = ionic_qcq_enable(lif->rxqcqs[i]);
0f3154e6
SN		 2142 if (err)
2143 goto err_out;
2144
34dec947 2145 err = ionic_qcq_enable(lif->txqcqs[i]);
0f3154e6 2146 if (err) {
ba6ab8ac 2147 derr = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT));
0f3154e6
SN		 2148 goto err_out;
2149 }
2150 }
2151
a8771bfe
SN		 2152 if (lif->hwstamp_rxq) {
2153 ionic_rx_fill(&lif->hwstamp_rxq->q);
2154 err = ionic_qcq_enable(lif->hwstamp_rxq);
2155 if (err)
2156 goto err_out_hwstamp_rx;
2157 }
2158
2159 if (lif->hwstamp_txq) {
2160 err = ionic_qcq_enable(lif->hwstamp_txq);
2161 if (err)
2162 goto err_out_hwstamp_tx;
2163 }
2164
0f3154e6
SN		 2165 return 0;
2166
a8771bfe
SN		 2167err_out_hwstamp_tx:
2168 if (lif->hwstamp_rxq)
2169 derr = ionic_qcq_disable(lif->hwstamp_rxq, (derr != -ETIMEDOUT));
2170err_out_hwstamp_rx:
2171 i = lif->nxqs;
0f3154e6
SN		 2172err_out:
2173 while (i--) {
ba6ab8ac
SN		 2174 derr = ionic_qcq_disable(lif->txqcqs[i], (derr != -ETIMEDOUT));
2175 derr = ionic_qcq_disable(lif->rxqcqs[i], (derr != -ETIMEDOUT));
0f3154e6
SN		 2176 }
2177
2178 return err;
2179}
2180
49d3b493
SN		 2181static int ionic_start_queues(struct ionic_lif *lif)
2182{
2183 int err;
2184
9e8eaf84
SN		 2185 if (test_bit(IONIC_LIF_F_BROKEN, lif->state))
2186 return -EIO;
2187
8c775344
SN		 2188 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2189 return -EBUSY;
2190
49d3b493
SN		 2191 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state))
2192 return 0;
2193
2194 err = ionic_txrx_enable(lif);
2195 if (err) {
2196 clear_bit(IONIC_LIF_F_UP, lif->state);
2197 return err;
2198 }
2199 netif_tx_wake_all_queues(lif->netdev);
2200
2201 return 0;
2202}
2203
d4881430 2204static int ionic_open(struct net_device *netdev)
beead698
SN		 2205{
2206 struct ionic_lif *lif = netdev_priv(netdev);
0f3154e6 2207 int err;
beead698 2208
9e8eaf84
SN		 2209 /* If recovering from a broken state, clear the bit and we'll try again */
2210 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
2211 netdev_info(netdev, "clearing broken state\n");
2212
0f3154e6
SN		 2213 err = ionic_txrx_alloc(lif);
2214 if (err)
2215 return err;
2216
2217 err = ionic_txrx_init(lif);
2218 if (err)
25cc5a5f 2219 goto err_txrx_free;
beead698 2220
fa48494c
SN		 2221 err = netif_set_real_num_tx_queues(netdev, lif->nxqs);
2222 if (err)
2223 goto err_txrx_deinit;
2224
2225 err = netif_set_real_num_rx_queues(netdev, lif->nxqs);
2226 if (err)
2227 goto err_txrx_deinit;
2228
49d3b493
SN		 2229 /* don't start the queues until we have link */
2230 if (netif_carrier_ok(netdev)) {
2231 err = ionic_start_queues(lif);
2232 if (err)
2233 goto err_txrx_deinit;
2234 }
8d61aad4 2235
beead698 2236 return 0;
0f3154e6
SN		 2237
2238err_txrx_deinit:
2239 ionic_txrx_deinit(lif);
25cc5a5f 2240err_txrx_free:
0f3154e6
SN		 2241 ionic_txrx_free(lif);
2242 return err;
beead698
SN		 2243}
2244
49d3b493 2245static void ionic_stop_queues(struct ionic_lif *lif)
beead698 2246{
49d3b493
SN		 2247 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state))
2248 return;
beead698 2249
49d3b493 2250 netif_tx_disable(lif->netdev);
b59eabd2 2251 ionic_txrx_disable(lif);
49d3b493 2252}
beead698 2253
d4881430 2254static int ionic_stop(struct net_device *netdev)
49d3b493
SN		 2255{
2256 struct ionic_lif *lif = netdev_priv(netdev);
0f3154e6 2257
b59eabd2 2258 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
c672412f
SN		 2259 return 0;
2260
49d3b493 2261 ionic_stop_queues(lif);
0f3154e6
SN		 2262 ionic_txrx_deinit(lif);
2263 ionic_txrx_free(lif);
beead698 2264
49d3b493 2265 return 0;
beead698
SN		 2266}
2267
a7605370 2268static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
afeefec6
SN		 2269{
2270 struct ionic_lif *lif = netdev_priv(netdev);
2271
2272 switch (cmd) {
2273 case SIOCSHWTSTAMP:
2274 return ionic_lif_hwstamp_set(lif, ifr);
2275 case SIOCGHWTSTAMP:
2276 return ionic_lif_hwstamp_get(lif, ifr);
2277 default:
2278 return -EOPNOTSUPP;
2279 }
2280}
2281
fbb39807
SN		 2282static int ionic_get_vf_config(struct net_device *netdev,
2283 int vf, struct ifla_vf_info *ivf)
2284{
2285 struct ionic_lif *lif = netdev_priv(netdev);
2286 struct ionic *ionic = lif->ionic;
2287 int ret = 0;
2288
a836c352
SN		 2289 if (!netif_device_present(netdev))
2290 return -EBUSY;
2291
fbb39807
SN		 2292 down_read(&ionic->vf_op_lock);
2293
2294 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2295 ret = -EINVAL;
2296 } else {
2297 ivf->vf = vf;
d701ec32 2298 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid);
fbb39807
SN		 2299 ivf->qos = 0;
2300 ivf->spoofchk = ionic->vfs[vf].spoofchk;
2301 ivf->linkstate = ionic->vfs[vf].linkstate;
d701ec32 2302 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate);
fbb39807
SN		 2303 ivf->trusted = ionic->vfs[vf].trusted;
2304 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr);
2305 }
2306
2307 up_read(&ionic->vf_op_lock);
2308 return ret;
2309}
2310
2311static int ionic_get_vf_stats(struct net_device *netdev, int vf,
2312 struct ifla_vf_stats *vf_stats)
2313{
2314 struct ionic_lif *lif = netdev_priv(netdev);
2315 struct ionic *ionic = lif->ionic;
2316 struct ionic_lif_stats *vs;
2317 int ret = 0;
2318
a836c352
SN		 2319 if (!netif_device_present(netdev))
2320 return -EBUSY;
2321
fbb39807
SN		 2322 down_read(&ionic->vf_op_lock);
2323
2324 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2325 ret = -EINVAL;
2326 } else {
2327 memset(vf_stats, 0, sizeof(*vf_stats));
2328 vs = &ionic->vfs[vf].stats;
2329
2330 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets);
2331 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets);
2332 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes);
2333 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes);
2334 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets);
2335 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets);
2336 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) +
2337 le64_to_cpu(vs->rx_mcast_drop_packets) +
2338 le64_to_cpu(vs->rx_bcast_drop_packets);
2339 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) +
2340 le64_to_cpu(vs->tx_mcast_drop_packets) +
2341 le64_to_cpu(vs->tx_bcast_drop_packets);
2342 }
2343
2344 up_read(&ionic->vf_op_lock);
2345 return ret;
2346}
2347
2348static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2349{
2350 struct ionic_lif *lif = netdev_priv(netdev);
2351 struct ionic *ionic = lif->ionic;
2352 int ret;
2353
2354 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac)))
2355 return -EINVAL;
2356
a836c352
SN		 2357 if (!netif_device_present(netdev))
2358 return -EBUSY;
2359
e396ce5f 2360 down_write(&ionic->vf_op_lock);
fbb39807
SN		 2361
2362 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2363 ret = -EINVAL;
2364 } else {
2365 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac);
2366 if (!ret)
2367 ether_addr_copy(ionic->vfs[vf].macaddr, mac);
2368 }
2369
e396ce5f 2370 up_write(&ionic->vf_op_lock);
fbb39807
SN		 2371 return ret;
2372}
2373
2374static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2375 u8 qos, __be16 proto)
2376{
2377 struct ionic_lif *lif = netdev_priv(netdev);
2378 struct ionic *ionic = lif->ionic;
2379 int ret;
2380
2381 /* until someday when we support qos */
2382 if (qos)
2383 return -EINVAL;
2384
2385 if (vlan > 4095)
2386 return -EINVAL;
2387
2388 if (proto != htons(ETH_P_8021Q))
2389 return -EPROTONOSUPPORT;
2390
a836c352
SN		 2391 if (!netif_device_present(netdev))
2392 return -EBUSY;
2393
e396ce5f 2394 down_write(&ionic->vf_op_lock);
fbb39807
SN		 2395
2396 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2397 ret = -EINVAL;
2398 } else {
2399 ret = ionic_set_vf_config(ionic, vf,
2400 IONIC_VF_ATTR_VLAN, (u8 *)&vlan);
2401 if (!ret)
d701ec32 2402 ionic->vfs[vf].vlanid = cpu_to_le16(vlan);
fbb39807
SN		 2403 }
2404
e396ce5f 2405 up_write(&ionic->vf_op_lock);
fbb39807
SN		 2406 return ret;
2407}
2408
2409static int ionic_set_vf_rate(struct net_device *netdev, int vf,
2410 int tx_min, int tx_max)
2411{
2412 struct ionic_lif *lif = netdev_priv(netdev);
2413 struct ionic *ionic = lif->ionic;
2414 int ret;
2415
2416 /* setting the min just seems silly */
2417 if (tx_min)
2418 return -EINVAL;
2419
a836c352
SN		 2420 if (!netif_device_present(netdev))
2421 return -EBUSY;
2422
fbb39807
SN		 2423 down_write(&ionic->vf_op_lock);
2424
2425 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2426 ret = -EINVAL;
2427 } else {
2428 ret = ionic_set_vf_config(ionic, vf,
2429 IONIC_VF_ATTR_RATE, (u8 *)&tx_max);
2430 if (!ret)
d701ec32 2431 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max);
fbb39807
SN		 2432 }
2433
2434 up_write(&ionic->vf_op_lock);
2435 return ret;
2436}
2437
2438static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set)
2439{
2440 struct ionic_lif *lif = netdev_priv(netdev);
2441 struct ionic *ionic = lif->ionic;
2442 u8 data = set; /* convert to u8 for config */
2443 int ret;
2444
a836c352
SN		 2445 if (!netif_device_present(netdev))
2446 return -EBUSY;
2447
fbb39807
SN		 2448 down_write(&ionic->vf_op_lock);
2449
2450 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2451 ret = -EINVAL;
2452 } else {
2453 ret = ionic_set_vf_config(ionic, vf,
2454 IONIC_VF_ATTR_SPOOFCHK, &data);
2455 if (!ret)
2456 ionic->vfs[vf].spoofchk = data;
2457 }
2458
2459 up_write(&ionic->vf_op_lock);
2460 return ret;
2461}
2462
2463static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set)
2464{
2465 struct ionic_lif *lif = netdev_priv(netdev);
2466 struct ionic *ionic = lif->ionic;
2467 u8 data = set; /* convert to u8 for config */
2468 int ret;
2469
a836c352
SN		 2470 if (!netif_device_present(netdev))
2471 return -EBUSY;
2472
fbb39807
SN		 2473 down_write(&ionic->vf_op_lock);
2474
2475 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2476 ret = -EINVAL;
2477 } else {
2478 ret = ionic_set_vf_config(ionic, vf,
2479 IONIC_VF_ATTR_TRUST, &data);
2480 if (!ret)
2481 ionic->vfs[vf].trusted = data;
2482 }
2483
2484 up_write(&ionic->vf_op_lock);
2485 return ret;
2486}
2487
2488static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set)
2489{
2490 struct ionic_lif *lif = netdev_priv(netdev);
2491 struct ionic *ionic = lif->ionic;
2492 u8 data;
2493 int ret;
2494
2495 switch (set) {
2496 case IFLA_VF_LINK_STATE_ENABLE:
2497 data = IONIC_VF_LINK_STATUS_UP;
2498 break;
2499 case IFLA_VF_LINK_STATE_DISABLE:
2500 data = IONIC_VF_LINK_STATUS_DOWN;
2501 break;
2502 case IFLA_VF_LINK_STATE_AUTO:
2503 data = IONIC_VF_LINK_STATUS_AUTO;
2504 break;
2505 default:
2506 return -EINVAL;
2507 }
2508
a836c352
SN		 2509 if (!netif_device_present(netdev))
2510 return -EBUSY;
2511
fbb39807
SN		 2512 down_write(&ionic->vf_op_lock);
2513
2514 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2515 ret = -EINVAL;
2516 } else {
2517 ret = ionic_set_vf_config(ionic, vf,
2518 IONIC_VF_ATTR_LINKSTATE, &data);
2519 if (!ret)
2520 ionic->vfs[vf].linkstate = set;
2521 }
2522
2523 up_write(&ionic->vf_op_lock);
2524 return ret;
2525}
2526
beead698
SN		 2527static const struct net_device_ops ionic_netdev_ops = {
2528 .ndo_open = ionic_open,
2529 .ndo_stop = ionic_stop,
a7605370 2530 .ndo_eth_ioctl = ionic_eth_ioctl,
0f3154e6 2531 .ndo_start_xmit = ionic_start_xmit,
8d61aad4 2532 .ndo_get_stats64 = ionic_get_stats64,
1800eee1 2533 .ndo_set_rx_mode = ionic_ndo_set_rx_mode,
beead698
SN		 2534 .ndo_set_features = ionic_set_features,
2535 .ndo_set_mac_address = ionic_set_mac_address,
2536 .ndo_validate_addr = eth_validate_addr,
2537 .ndo_tx_timeout = ionic_tx_timeout,
2538 .ndo_change_mtu = ionic_change_mtu,
2539 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid,
2540 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid,
fbb39807
SN		 2541 .ndo_set_vf_vlan = ionic_set_vf_vlan,
2542 .ndo_set_vf_trust = ionic_set_vf_trust,
2543 .ndo_set_vf_mac = ionic_set_vf_mac,
2544 .ndo_set_vf_rate = ionic_set_vf_rate,
2545 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk,
2546 .ndo_get_vf_config = ionic_get_vf_config,
2547 .ndo_set_vf_link_state = ionic_set_vf_link_state,
2548 .ndo_get_vf_stats = ionic_get_vf_stats,
beead698
SN		 2549};
2550
a34e25ab
SN		 2551static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b)
2552{
2553 /* only swapping the queues, not the napi, flags, or other stuff */
57a3a98d 2554 swap(a->q.features, b->q.features);
a34e25ab 2555 swap(a->q.num_descs, b->q.num_descs);
0ec9f666 2556 swap(a->q.desc_size, b->q.desc_size);
a34e25ab
SN		 2557 swap(a->q.base, b->q.base);
2558 swap(a->q.base_pa, b->q.base_pa);
2559 swap(a->q.info, b->q.info);
2560 swap(a->q_base, b->q_base);
2561 swap(a->q_base_pa, b->q_base_pa);
2562 swap(a->q_size, b->q_size);
2563
0ec9f666 2564 swap(a->q.sg_desc_size, b->q.sg_desc_size);
a34e25ab
SN		 2565 swap(a->q.sg_base, b->q.sg_base);
2566 swap(a->q.sg_base_pa, b->q.sg_base_pa);
2567 swap(a->sg_base, b->sg_base);
2568 swap(a->sg_base_pa, b->sg_base_pa);
2569 swap(a->sg_size, b->sg_size);
2570
2571 swap(a->cq.num_descs, b->cq.num_descs);
0ec9f666 2572 swap(a->cq.desc_size, b->cq.desc_size);
a34e25ab
SN		 2573 swap(a->cq.base, b->cq.base);
2574 swap(a->cq.base_pa, b->cq.base_pa);
2575 swap(a->cq.info, b->cq.info);
2576 swap(a->cq_base, b->cq_base);
2577 swap(a->cq_base_pa, b->cq_base_pa);
2578 swap(a->cq_size, b->cq_size);
55eda6bb
SN		 2579
2580 ionic_debugfs_del_qcq(a);
2581 ionic_debugfs_add_qcq(a->q.lif, a);
a34e25ab
SN		 2582}
2583
2584int ionic_reconfigure_queues(struct ionic_lif *lif,
2585 struct ionic_queue_params *qparam)
2586{
33c252e1 2587 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
a34e25ab
SN		 2588 struct ionic_qcq **tx_qcqs = NULL;
2589 struct ionic_qcq **rx_qcqs = NULL;
33c252e1 2590 unsigned int flags, i;
a34e25ab 2591 int err = -ENOMEM;
a34e25ab
SN		 2592
2593 /* allocate temporary qcq arrays to hold new queue structs */
101b40a0
SN		 2594 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) {
2595 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif,
a34e25ab
SN		 2596 sizeof(struct ionic_qcq *), GFP_KERNEL);
2597 if (!tx_qcqs)
2598 goto err_out;
2599 }
0ec9f666
SN		 2600 if (qparam->nxqs != lif->nxqs ||
2601 qparam->nrxq_descs != lif->nrxq_descs ||
2602 qparam->rxq_features != lif->rxq_features) {
101b40a0 2603 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif,
a34e25ab
SN		 2604 sizeof(struct ionic_qcq *), GFP_KERNEL);
2605 if (!rx_qcqs)
2606 goto err_out;
2607 }
2608
101b40a0
SN		 2609 /* allocate new desc_info and rings, but leave the interrupt setup
2610 * until later so as to not mess with the still-running queues
2611 */
a34e25ab 2612 if (tx_qcqs) {
0ec9f666
SN		 2613 num_desc = qparam->ntxq_descs;
2614 desc_sz = sizeof(struct ionic_txq_desc);
2615 comp_sz = sizeof(struct ionic_txq_comp);
2616
2617 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2618 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2619 sizeof(struct ionic_txq_sg_desc_v1))
2620 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
2621 else
2622 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
2623
101b40a0 2624 for (i = 0; i < qparam->nxqs; i++) {
a34e25ab
SN		 2625 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2626 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
0ec9f666 2627 num_desc, desc_sz, comp_sz, sg_desc_sz,
a34e25ab
SN		 2628 lif->kern_pid, &tx_qcqs[i]);
2629 if (err)
2630 goto err_out;
2631 }
2632 }
2633
2634 if (rx_qcqs) {
0ec9f666
SN		 2635 num_desc = qparam->nrxq_descs;
2636 desc_sz = sizeof(struct ionic_rxq_desc);
2637 comp_sz = sizeof(struct ionic_rxq_comp);
2638 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
2639
2640 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC)
2641 comp_sz *= 2;
2642
101b40a0 2643 for (i = 0; i < qparam->nxqs; i++) {
a34e25ab
SN		 2644 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2645 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
0ec9f666 2646 num_desc, desc_sz, comp_sz, sg_desc_sz,
a34e25ab
SN		 2647 lif->kern_pid, &rx_qcqs[i]);
2648 if (err)
2649 goto err_out;
0ec9f666
SN		 2650
2651 rx_qcqs[i]->q.features = qparam->rxq_features;
a34e25ab
SN		 2652 }
2653 }
2654
2655 /* stop and clean the queues */
2656 ionic_stop_queues_reconfig(lif);
2657
101b40a0
SN		 2658 if (qparam->nxqs != lif->nxqs) {
2659 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs);
2660 if (err)
2661 goto err_out_reinit_unlock;
2662 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs);
2663 if (err) {
2664 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs);
2665 goto err_out_reinit_unlock;
2666 }
2667 }
2668
a34e25ab
SN		 2669 /* swap new desc_info and rings, keeping existing interrupt config */
2670 if (tx_qcqs) {
2671 lif->ntxq_descs = qparam->ntxq_descs;
101b40a0 2672 for (i = 0; i < qparam->nxqs; i++)
a34e25ab
SN		 2673 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]);
2674 }
2675
2676 if (rx_qcqs) {
2677 lif->nrxq_descs = qparam->nrxq_descs;
101b40a0 2678 for (i = 0; i < qparam->nxqs; i++)
a34e25ab
SN		 2679 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]);
2680 }
2681
101b40a0
SN		 2682 /* if we need to change the interrupt layout, this is the time */
2683 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) ||
2684 qparam->nxqs != lif->nxqs) {
2685 if (qparam->intr_split) {
2686 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2687 } else {
2688 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2689 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2690 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2691 }
2692
2693 /* clear existing interrupt assignments */
2694 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) {
2695 ionic_qcq_intr_free(lif, lif->txqcqs[i]);
2696 ionic_qcq_intr_free(lif, lif->rxqcqs[i]);
2697 }
2698
2699 /* re-assign the interrupts */
2700 for (i = 0; i < qparam->nxqs; i++) {
2701 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2702 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]);
2703 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2704 lif->rxqcqs[i]->intr.index,
2705 lif->rx_coalesce_hw);
2706
2707 if (qparam->intr_split) {
2708 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2709 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]);
2710 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2711 lif->txqcqs[i]->intr.index,
2712 lif->tx_coalesce_hw);
04a83459
SN		 2713 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
2714 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
101b40a0
SN		 2715 } else {
2716 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2717 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]);
2718 }
2719 }
2720 }
2721
ed6d9b02
SN		 2722 /* now we can rework the debugfs mappings */
2723 if (tx_qcqs) {
2724 for (i = 0; i < qparam->nxqs; i++) {
2725 ionic_debugfs_del_qcq(lif->txqcqs[i]);
2726 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
2727 }
2728 }
2729
2730 if (rx_qcqs) {
2731 for (i = 0; i < qparam->nxqs; i++) {
2732 ionic_debugfs_del_qcq(lif->rxqcqs[i]);
2733 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
2734 }
2735 }
2736
101b40a0 2737 swap(lif->nxqs, qparam->nxqs);
0ec9f666 2738 swap(lif->rxq_features, qparam->rxq_features);
101b40a0
SN		 2739
2740err_out_reinit_unlock:
25cc5a5f 2741 /* re-init the queues, but don't lose an error code */
101b40a0
SN		 2742 if (err)
2743 ionic_start_queues_reconfig(lif);
2744 else
2745 err = ionic_start_queues_reconfig(lif);
a34e25ab
SN		 2746
2747err_out:
2748 /* free old allocs without cleaning intr */
101b40a0 2749 for (i = 0; i < qparam->nxqs; i++) {
a34e25ab
SN		 2750 if (tx_qcqs && tx_qcqs[i]) {
2751 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2752 ionic_qcq_free(lif, tx_qcqs[i]);
101b40a0 2753 devm_kfree(lif->ionic->dev, tx_qcqs[i]);
a34e25ab
SN		 2754 tx_qcqs[i] = NULL;
2755 }
2756 if (rx_qcqs && rx_qcqs[i]) {
2757 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2758 ionic_qcq_free(lif, rx_qcqs[i]);
101b40a0 2759 devm_kfree(lif->ionic->dev, rx_qcqs[i]);
a34e25ab
SN		 2760 rx_qcqs[i] = NULL;
2761 }
2762 }
2763
2764 /* free q array */
2765 if (rx_qcqs) {
2766 devm_kfree(lif->ionic->dev, rx_qcqs);
2767 rx_qcqs = NULL;
2768 }
2769 if (tx_qcqs) {
2770 devm_kfree(lif->ionic->dev, tx_qcqs);
2771 tx_qcqs = NULL;
2772 }
2773
101b40a0
SN		 2774 /* clean the unused dma and info allocations when new set is smaller
2775 * than the full array, but leave the qcq shells in place
2776 */
2777 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) {
2778 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2779 ionic_qcq_free(lif, lif->txqcqs[i]);
2780
2781 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2782 ionic_qcq_free(lif, lif->rxqcqs[i]);
2783 }
2784
a34e25ab
SN		 2785 return err;
2786}
2787
30b87ab4 2788int ionic_lif_alloc(struct ionic *ionic)
1a58e196
SN		 2789{
2790 struct device *dev = ionic->dev;
4b03b273 2791 union ionic_lif_identity *lid;
1a58e196
SN		 2792 struct net_device *netdev;
2793 struct ionic_lif *lif;
aa319881 2794 int tbl_sz;
1a58e196
SN		 2795 int err;
2796
4b03b273
SN		 2797 lid = kzalloc(sizeof(*lid), GFP_KERNEL);
2798 if (!lid)
30b87ab4 2799 return -ENOMEM;
4b03b273 2800
1a58e196
SN		 2801 netdev = alloc_etherdev_mqs(sizeof(*lif),
2802 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif);
2803 if (!netdev) {
2804 dev_err(dev, "Cannot allocate netdev, aborting\n");
4b1debbe
CIK		 2805 err = -ENOMEM;
2806 goto err_out_free_lid;
1a58e196
SN		 2807 }
2808
2809 SET_NETDEV_DEV(netdev, dev);
2810
2811 lif = netdev_priv(netdev);
2812 lif->netdev = netdev;
30b87ab4 2813 ionic->lif = lif;
beead698 2814 netdev->netdev_ops = &ionic_netdev_ops;
4d03e00a 2815 ionic_ethtool_set_ops(netdev);
beead698
SN		 2816
2817 netdev->watchdog_timeo = 2 * HZ;
aa47b540
SN		 2818 netif_carrier_off(netdev);
2819
4b03b273
SN		 2820 lif->identity = lid;
2821 lif->lif_type = IONIC_LIF_TYPE_CLASSIC;
bb9f80f3
SN		 2822 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity);
2823 if (err) {
2824 dev_err(ionic->dev, "Cannot identify type %d: %d\n",
2825 lif->lif_type, err);
2826 goto err_out_free_netdev;
2827 }
eba87609
SN		 2828 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU,
2829 le32_to_cpu(lif->identity->eth.min_frame_size));
4b03b273
SN		 2830 lif->netdev->max_mtu =
2831 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN;
1a58e196
SN		 2832
2833 lif->neqs = ionic->neqs_per_lif;
2834 lif->nxqs = ionic->ntxqs_per_lif;
2835
2836 lif->ionic = ionic;
30b87ab4 2837 lif->index = 0;
c0b03e83
SN		 2838
2839 if (is_kdump_kernel()) {
2840 lif->ntxq_descs = IONIC_MIN_TXRX_DESC;
2841 lif->nrxq_descs = IONIC_MIN_TXRX_DESC;
2842 } else {
2843 lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
2844 lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
2845 }
1a58e196 2846
8c15440b 2847 /* Convert the default coalesce value to actual hw resolution */
780eded3 2848 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT;
ff7ebed9 2849 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic,
780eded3 2850 lif->rx_coalesce_usecs);
fe8c30b5
SN		 2851 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2852 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
04a83459
SN		 2853 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
2854 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
8c15440b 2855
30b87ab4 2856 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
1a58e196 2857
1d062b7b
SN		 2858 spin_lock_init(&lif->adminq_lock);
2859
2a654540
SN		 2860 spin_lock_init(&lif->deferred.lock);
2861 INIT_LIST_HEAD(&lif->deferred.list);
2862 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
2863
1a58e196
SN		 2864 /* allocate lif info */
2865 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
2866 lif->info = dma_alloc_coherent(dev, lif->info_sz,
2867 &lif->info_pa, GFP_KERNEL);
2868 if (!lif->info) {
2869 dev_err(dev, "Failed to allocate lif info, aborting\n");
2870 err = -ENOMEM;
2871 goto err_out_free_netdev;
2872 }
2873
2a8c2c1a
SN		 2874 ionic_debugfs_add_lif(lif);
2875
30b87ab4
SN		 2876 /* allocate control queues and txrx queue arrays */
2877 ionic_lif_queue_identify(lif);
1d062b7b
SN		 2878 err = ionic_qcqs_alloc(lif);
2879 if (err)
2880 goto err_out_free_lif_info;
2881
aa319881
SN		 2882 /* allocate rss indirection table */
2883 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
2884 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
2885 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
2886 &lif->rss_ind_tbl_pa,
2887 GFP_KERNEL);
2888
2889 if (!lif->rss_ind_tbl) {
73a63ee9 2890 err = -ENOMEM;
aa319881
SN		 2891 dev_err(dev, "Failed to allocate rss indirection table, aborting\n");
2892 goto err_out_free_qcqs;
2893 }
ffac2027 2894 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
aa319881 2895
f0790bcd
SN		 2896 ionic_lif_alloc_phc(lif);
2897
30b87ab4 2898 return 0;
1a58e196 2899
aa319881
SN		 2900err_out_free_qcqs:
2901 ionic_qcqs_free(lif);
1d062b7b
SN		 2902err_out_free_lif_info:
2903 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
2904 lif->info = NULL;
2905 lif->info_pa = 0;
1a58e196
SN		 2906err_out_free_netdev:
2907 free_netdev(lif->netdev);
2908 lif = NULL;
4b1debbe 2909err_out_free_lid:
4b03b273 2910 kfree(lid);
1a58e196 2911
30b87ab4 2912 return err;
1a58e196
SN		 2913}
2914
2915static void ionic_lif_reset(struct ionic_lif *lif)
2916{
2917 struct ionic_dev *idev = &lif->ionic->idev;
2918
2919 mutex_lock(&lif->ionic->dev_cmd_lock);
2920 ionic_dev_cmd_lif_reset(idev, lif->index);
2921 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2922 mutex_unlock(&lif->ionic->dev_cmd_lock);
2923}
2924
c672412f
SN		 2925static void ionic_lif_handle_fw_down(struct ionic_lif *lif)
2926{
2927 struct ionic *ionic = lif->ionic;
2928
2929 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state))
2930 return;
2931
2932 dev_info(ionic->dev, "FW Down: Stopping LIFs\n");
2933
2934 netif_device_detach(lif->netdev);
2935
2936 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
2937 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n");
0925e9db 2938 mutex_lock(&lif->queue_lock);
c672412f 2939 ionic_stop_queues(lif);
0925e9db 2940 mutex_unlock(&lif->queue_lock);
c672412f
SN		 2941 }
2942
2943 if (netif_running(lif->netdev)) {
2944 ionic_txrx_deinit(lif);
2945 ionic_txrx_free(lif);
2946 }
30b87ab4 2947 ionic_lif_deinit(lif);
6bc977fa 2948 ionic_reset(ionic);
c672412f
SN		 2949 ionic_qcqs_free(lif);
2950
2951 dev_info(ionic->dev, "FW Down: LIFs stopped\n");
2952}
2953
2954static void ionic_lif_handle_fw_up(struct ionic_lif *lif)
2955{
2956 struct ionic *ionic = lif->ionic;
2957 int err;
2958
2959 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2960 return;
2961
2962 dev_info(ionic->dev, "FW Up: restarting LIFs\n");
2963
1d53aedc 2964 ionic_init_devinfo(ionic);
a21b5d49
SN		 2965 err = ionic_identify(ionic);
2966 if (err)
2967 goto err_out;
2968 err = ionic_port_identify(ionic);
2969 if (err)
2970 goto err_out;
2971 err = ionic_port_init(ionic);
2972 if (err)
2973 goto err_out;
c672412f
SN		 2974 err = ionic_qcqs_alloc(lif);
2975 if (err)
2976 goto err_out;
2977
30b87ab4 2978 err = ionic_lif_init(lif);
c672412f
SN		 2979 if (err)
2980 goto err_qcqs_free;
2981
2982 if (lif->registered)
2983 ionic_lif_set_netdev_info(lif);
2984
7e4d4759
SN		 2985 ionic_rx_filter_replay(lif);
2986
c672412f
SN		 2987 if (netif_running(lif->netdev)) {
2988 err = ionic_txrx_alloc(lif);
2989 if (err)
2990 goto err_lifs_deinit;
2991
2992 err = ionic_txrx_init(lif);
2993 if (err)
2994 goto err_txrx_free;
2995 }
2996
2997 clear_bit(IONIC_LIF_F_FW_RESET, lif->state);
25cc5a5f 2998 ionic_link_status_check_request(lif, CAN_SLEEP);
c672412f
SN		 2999 netif_device_attach(lif->netdev);
3000 dev_info(ionic->dev, "FW Up: LIFs restarted\n");
3001
51117874 3002 /* restore the hardware timestamping queues */
829600ce 3003 ionic_lif_hwstamp_replay(lif);
51117874 3004
c672412f
SN		 3005 return;
3006
3007err_txrx_free:
3008 ionic_txrx_free(lif);
3009err_lifs_deinit:
30b87ab4 3010 ionic_lif_deinit(lif);
c672412f
SN		 3011err_qcqs_free:
3012 ionic_qcqs_free(lif);
3013err_out:
3014 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err);
3015}
3016
30b87ab4 3017void ionic_lif_free(struct ionic_lif *lif)
1a58e196
SN		 3018{
3019 struct device *dev = lif->ionic->dev;
3020
f0790bcd
SN		 3021 ionic_lif_free_phc(lif);
3022
aa319881
SN		 3023 /* free rss indirection table */
3024 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
3025 lif->rss_ind_tbl_pa);
3026 lif->rss_ind_tbl = NULL;
3027 lif->rss_ind_tbl_pa = 0;
3028
1d062b7b
SN		 3029 /* free queues */
3030 ionic_qcqs_free(lif);
c672412f
SN		 3031 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3032 ionic_lif_reset(lif);
1a58e196
SN		 3033
3034 /* free lif info */
4b03b273 3035 kfree(lif->identity);
1a58e196
SN		 3036 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
3037 lif->info = NULL;
3038 lif->info_pa = 0;
3039
6461b446
SN		 3040 /* unmap doorbell page */
3041 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3042 lif->kern_dbpage = NULL;
3043 kfree(lif->dbid_inuse);
3044 lif->dbid_inuse = NULL;
3045
1a58e196
SN		 3046 /* free netdev & lif */
3047 ionic_debugfs_del_lif(lif);
1a58e196
SN		 3048 free_netdev(lif->netdev);
3049}
3050
30b87ab4 3051void ionic_lif_deinit(struct ionic_lif *lif)
1a58e196 3052{
c672412f 3053 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state))
1a58e196
SN		 3054 return;
3055
c672412f
SN		 3056 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3057 cancel_work_sync(&lif->deferred.work);
3058 cancel_work_sync(&lif->tx_timeout_work);
7e4d4759 3059 ionic_rx_filters_deinit(lif);
bdff4666
SN		 3060 if (lif->netdev->features & NETIF_F_RXHASH)
3061 ionic_lif_rss_deinit(lif);
c672412f 3062 }
1a58e196 3063
1d062b7b 3064 napi_disable(&lif->adminqcq->napi);
77ceb68e 3065 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1d062b7b
SN		 3066 ionic_lif_qcq_deinit(lif, lif->adminqcq);
3067
0925e9db 3068 mutex_destroy(&lif->queue_lock);
1a58e196
SN		 3069 ionic_lif_reset(lif);
3070}
3071
1d062b7b
SN		 3072static int ionic_lif_adminq_init(struct ionic_lif *lif)
3073{
3074 struct device *dev = lif->ionic->dev;
3075 struct ionic_q_init_comp comp;
3076 struct ionic_dev *idev;
3077 struct ionic_qcq *qcq;
3078 struct ionic_queue *q;
3079 int err;
3080
3081 idev = &lif->ionic->idev;
3082 qcq = lif->adminqcq;
3083 q = &qcq->q;
3084
3085 mutex_lock(&lif->ionic->dev_cmd_lock);
3086 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
3087 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3088 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3089 mutex_unlock(&lif->ionic->dev_cmd_lock);
3090 if (err) {
3091 netdev_err(lif->netdev, "adminq init failed %d\n", err);
3092 return err;
3093 }
3094
3095 q->hw_type = comp.hw_type;
3096 q->hw_index = le32_to_cpu(comp.hw_index);
3097 q->dbval = IONIC_DBELL_QID(q->hw_index);
3098
3099 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type);
3100 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index);
3101
3102 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi,
3103 NAPI_POLL_WEIGHT);
3104
1d062b7b
SN		 3105 napi_enable(&qcq->napi);
3106
3107 if (qcq->flags & IONIC_QCQ_F_INTR)
3108 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
3109 IONIC_INTR_MASK_CLEAR);
3110
3111 qcq->flags |= IONIC_QCQ_F_INITED;
3112
1d062b7b
SN		 3113 return 0;
3114}
3115
77ceb68e
SN		 3116static int ionic_lif_notifyq_init(struct ionic_lif *lif)
3117{
3118 struct ionic_qcq *qcq = lif->notifyqcq;
3119 struct device *dev = lif->ionic->dev;
3120 struct ionic_queue *q = &qcq->q;
3121 int err;
3122
3123 struct ionic_admin_ctx ctx = {
3124 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3125 .cmd.q_init = {
3126 .opcode = IONIC_CMD_Q_INIT,
3127 .lif_index = cpu_to_le16(lif->index),
3128 .type = q->type,
5b3f3f2a 3129 .ver = lif->qtype_info[q->type].version,
77ceb68e
SN		 3130 .index = cpu_to_le32(q->index),
3131 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
3132 IONIC_QINIT_F_ENA),
3133 .intr_index = cpu_to_le16(lif->adminqcq->intr.index),
3134 .pid = cpu_to_le16(q->pid),
3135 .ring_size = ilog2(q->num_descs),
3136 .ring_base = cpu_to_le64(q->base_pa),
3137 }
3138 };
3139
3140 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
3141 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
3142 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
3143 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
3144
3145 err = ionic_adminq_post_wait(lif, &ctx);
3146 if (err)
3147 return err;
3148
c672412f 3149 lif->last_eid = 0;
77ceb68e
SN		 3150 q->hw_type = ctx.comp.q_init.hw_type;
3151 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
3152 q->dbval = IONIC_DBELL_QID(q->hw_index);
3153
3154 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
3155 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
3156
3157 /* preset the callback info */
3158 q->info[0].cb_arg = lif;
3159
3160 qcq->flags |= IONIC_QCQ_F_INITED;
3161
77ceb68e
SN		 3162 return 0;
3163}
3164
2a654540
SN		 3165static int ionic_station_set(struct ionic_lif *lif)
3166{
3167 struct net_device *netdev = lif->netdev;
3168 struct ionic_admin_ctx ctx = {
3169 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3170 .cmd.lif_getattr = {
3171 .opcode = IONIC_CMD_LIF_GETATTR,
3172 .index = cpu_to_le16(lif->index),
3173 .attr = IONIC_LIF_ATTR_MAC,
3174 },
3175 };
3176 struct sockaddr addr;
3177 int err;
3178
3179 err = ionic_adminq_post_wait(lif, &ctx);
3180 if (err)
3181 return err;
216902ae
SN		 3182 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n",
3183 ctx.comp.lif_getattr.mac);
fbb39807
SN		 3184 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac))
3185 return 0;
3186
f20a4d40
SN		 3187 if (!is_zero_ether_addr(netdev->dev_addr)) {
3188 /* If the netdev mac is non-zero and doesn't match the default
3189 * device address, it was set by something earlier and we're
3190 * likely here again after a fw-upgrade reset. We need to be
3191 * sure the netdev mac is in our filter list.
3192 */
3193 if (!ether_addr_equal(ctx.comp.lif_getattr.mac,
3194 netdev->dev_addr))
7c8d008c 3195 ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR, CAN_SLEEP);
f20a4d40
SN		 3196 } else {
3197 /* Update the netdev mac with the device's mac */
216902ae
SN		 3198 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len);
3199 addr.sa_family = AF_INET;
3200 err = eth_prepare_mac_addr_change(netdev, &addr);
3201 if (err) {
3202 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n",
3203 addr.sa_data, err);
3204 return 0;
3205 }
2a654540 3206
216902ae
SN		 3207 eth_commit_mac_addr_change(netdev, &addr);
3208 }
fbb39807 3209
2a654540
SN		 3210 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
3211 netdev->dev_addr);
7c8d008c 3212 ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR, CAN_SLEEP);
2a654540
SN		 3213
3214 return 0;
3215}
3216
30b87ab4 3217int ionic_lif_init(struct ionic_lif *lif)
1a58e196
SN		 3218{
3219 struct ionic_dev *idev = &lif->ionic->idev;
6461b446 3220 struct device *dev = lif->ionic->dev;
1a58e196 3221 struct ionic_lif_init_comp comp;
6461b446 3222 int dbpage_num;
1a58e196
SN		 3223 int err;
3224
1a58e196
SN		 3225 mutex_lock(&lif->ionic->dev_cmd_lock);
3226 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
3227 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3228 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3229 mutex_unlock(&lif->ionic->dev_cmd_lock);
3230 if (err)
3231 return err;
3232
3233 lif->hw_index = le16_to_cpu(comp.hw_index);
0925e9db 3234 mutex_init(&lif->queue_lock);
1a58e196 3235
6461b446
SN		 3236 /* now that we have the hw_index we can figure out our doorbell page */
3237 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
3238 if (!lif->dbid_count) {
3239 dev_err(dev, "No doorbell pages, aborting\n");
3240 return -EINVAL;
3241 }
3242
3243 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL);
3244 if (!lif->dbid_inuse) {
3245 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n");
3246 return -ENOMEM;
3247 }
3248
3249 /* first doorbell id reserved for kernel (dbid aka pid == zero) */
3250 set_bit(0, lif->dbid_inuse);
3251 lif->kern_pid = 0;
3252
3253 dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
3254 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
3255 if (!lif->kern_dbpage) {
3256 dev_err(dev, "Cannot map dbpage, aborting\n");
3257 err = -ENOMEM;
3258 goto err_out_free_dbid;
3259 }
3260
1d062b7b
SN		 3261 err = ionic_lif_adminq_init(lif);
3262 if (err)
3263 goto err_out_adminq_deinit;
3264
77ceb68e
SN		 3265 if (lif->ionic->nnqs_per_lif) {
3266 err = ionic_lif_notifyq_init(lif);
3267 if (err)
3268 goto err_out_notifyq_deinit;
3269 }
3270
beead698
SN		 3271 err = ionic_init_nic_features(lif);
3272 if (err)
3273 goto err_out_notifyq_deinit;
3274
7e4d4759
SN		 3275 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3276 err = ionic_rx_filters_init(lif);
3277 if (err)
3278 goto err_out_notifyq_deinit;
3279 }
c1e329eb 3280
2a654540
SN		 3281 err = ionic_station_set(lif);
3282 if (err)
3283 goto err_out_notifyq_deinit;
3284
0f3154e6
SN		 3285 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
3286
c6d3d73a 3287 set_bit(IONIC_LIF_F_INITED, lif->state);
1a58e196 3288
8c15440b
SN		 3289 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
3290
1a58e196 3291 return 0;
6461b446 3292
77ceb68e
SN		 3293err_out_notifyq_deinit:
3294 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1d062b7b
SN		 3295err_out_adminq_deinit:
3296 ionic_lif_qcq_deinit(lif, lif->adminqcq);
3297 ionic_lif_reset(lif);
3298 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3299 lif->kern_dbpage = NULL;
6461b446
SN		 3300err_out_free_dbid:
3301 kfree(lif->dbid_inuse);
3302 lif->dbid_inuse = NULL;
3303
3304 return err;
1a58e196
SN		 3305}
3306
1a371ea1
SN		 3307static void ionic_lif_notify_work(struct work_struct *ws)
3308{
3309}
3310
3311static void ionic_lif_set_netdev_info(struct ionic_lif *lif)
3312{
3313 struct ionic_admin_ctx ctx = {
3314 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3315 .cmd.lif_setattr = {
3316 .opcode = IONIC_CMD_LIF_SETATTR,
3317 .index = cpu_to_le16(lif->index),
3318 .attr = IONIC_LIF_ATTR_NAME,
3319 },
3320 };
3321
3322 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
3323 sizeof(ctx.cmd.lif_setattr.name));
3324
3325 ionic_adminq_post_wait(lif, &ctx);
3326}
3327
3328static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev)
3329{
3330 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit)
3331 return NULL;
3332
3333 return netdev_priv(netdev);
3334}
3335
3336static int ionic_lif_notify(struct notifier_block *nb,
3337 unsigned long event, void *info)
3338{
3339 struct net_device *ndev = netdev_notifier_info_to_dev(info);
3340 struct ionic *ionic = container_of(nb, struct ionic, nb);
3341 struct ionic_lif *lif = ionic_netdev_lif(ndev);
3342
3343 if (!lif || lif->ionic != ionic)
3344 return NOTIFY_DONE;
3345
3346 switch (event) {
3347 case NETDEV_CHANGENAME:
3348 ionic_lif_set_netdev_info(lif);
3349 break;
3350 }
3351
3352 return NOTIFY_DONE;
3353}
3354
30b87ab4 3355int ionic_lif_register(struct ionic_lif *lif)
beead698
SN		 3356{
3357 int err;
3358
afeefec6
SN		 3359 ionic_lif_register_phc(lif);
3360
30b87ab4 3361 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work);
1a371ea1 3362
30b87ab4 3363 lif->ionic->nb.notifier_call = ionic_lif_notify;
1a371ea1 3364
30b87ab4 3365 err = register_netdevice_notifier(&lif->ionic->nb);
1a371ea1 3366 if (err)
30b87ab4 3367 lif->ionic->nb.notifier_call = NULL;
1a371ea1 3368
beead698 3369 /* only register LIF0 for now */
30b87ab4 3370 err = register_netdev(lif->netdev);
beead698 3371 if (err) {
30b87ab4 3372 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n");
afeefec6 3373 ionic_lif_unregister_phc(lif);
beead698
SN		 3374 return err;
3375 }
f6e428b2 3376
25cc5a5f 3377 ionic_link_status_check_request(lif, CAN_SLEEP);
30b87ab4
SN		 3378 lif->registered = true;
3379 ionic_lif_set_netdev_info(lif);
beead698
SN		 3380
3381 return 0;
3382}
3383
30b87ab4 3384void ionic_lif_unregister(struct ionic_lif *lif)
beead698 3385{
30b87ab4
SN		 3386 if (lif->ionic->nb.notifier_call) {
3387 unregister_netdevice_notifier(&lif->ionic->nb);
3388 cancel_work_sync(&lif->ionic->nb_work);
3389 lif->ionic->nb.notifier_call = NULL;
1a371ea1
SN		 3390 }
3391
30b87ab4
SN		 3392 if (lif->netdev->reg_state == NETREG_REGISTERED)
3393 unregister_netdev(lif->netdev);
f0790bcd 3394
afeefec6
SN		 3395 ionic_lif_unregister_phc(lif);
3396
30b87ab4 3397 lif->registered = false;
beead698
SN		 3398}
3399
5b3f3f2a
SN		 3400static void ionic_lif_queue_identify(struct ionic_lif *lif)
3401{
d701ec32 3402 union ionic_q_identity __iomem *q_ident;
5b3f3f2a 3403 struct ionic *ionic = lif->ionic;
5b3f3f2a
SN		 3404 struct ionic_dev *idev;
3405 int qtype;
3406 int err;
3407
3408 idev = &lif->ionic->idev;
d701ec32 3409 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data;
5b3f3f2a
SN		 3410
3411 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) {
3412 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
3413
3414 /* filter out the ones we know about */
3415 switch (qtype) {
3416 case IONIC_QTYPE_ADMINQ:
3417 case IONIC_QTYPE_NOTIFYQ:
3418 case IONIC_QTYPE_RXQ:
3419 case IONIC_QTYPE_TXQ:
3420 break;
3421 default:
3422 continue;
3423 }
3424
3425 memset(qti, 0, sizeof(*qti));
3426
3427 mutex_lock(&ionic->dev_cmd_lock);
3428 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype,
3429 ionic_qtype_versions[qtype]);
3430 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3431 if (!err) {
d701ec32
SN		 3432 qti->version = readb(&q_ident->version);
3433 qti->supported = readb(&q_ident->supported);
3434 qti->features = readq(&q_ident->features);
3435 qti->desc_sz = readw(&q_ident->desc_sz);
3436 qti->comp_sz = readw(&q_ident->comp_sz);
3437 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz);
3438 qti->max_sg_elems = readw(&q_ident->max_sg_elems);
3439 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride);
5b3f3f2a
SN		 3440 }
3441 mutex_unlock(&ionic->dev_cmd_lock);
3442
3443 if (err == -EINVAL) {
3444 dev_err(ionic->dev, "qtype %d not supported\n", qtype);
3445 continue;
3446 } else if (err == -EIO) {
3447 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n");
3448 return;
3449 } else if (err) {
3450 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n",
3451 qtype, err);
3452 return;
3453 }
3454
3455 dev_dbg(ionic->dev, " qtype[%d].version = %d\n",
3456 qtype, qti->version);
3457 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n",
3458 qtype, qti->supported);
3459 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n",
3460 qtype, qti->features);
3461 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n",
3462 qtype, qti->desc_sz);
3463 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n",
3464 qtype, qti->comp_sz);
3465 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n",
3466 qtype, qti->sg_desc_sz);
3467 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n",
3468 qtype, qti->max_sg_elems);
3469 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n",
3470 qtype, qti->sg_desc_stride);
3471 }
3472}
3473
1a58e196
SN		 3474int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
3475 union ionic_lif_identity *lid)
3476{
3477 struct ionic_dev *idev = &ionic->idev;
3478 size_t sz;
3479 int err;
3480
3481 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data));
3482
3483 mutex_lock(&ionic->dev_cmd_lock);
3484 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1);
3485 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3486 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz);
3487 mutex_unlock(&ionic->dev_cmd_lock);
3488 if (err)
3489 return (err);
3490
3491 dev_dbg(ionic->dev, "capabilities 0x%llx\n",
3492 le64_to_cpu(lid->capabilities));
3493
3494 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n",
3495 le32_to_cpu(lid->eth.max_ucast_filters));
3496 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n",
3497 le32_to_cpu(lid->eth.max_mcast_filters));
3498 dev_dbg(ionic->dev, "eth.features 0x%llx\n",
3499 le64_to_cpu(lid->eth.config.features));
3500 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n",
3501 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ]));
3502 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n",
3503 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]));
3504 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n",
3505 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ]));
3506 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n",
3507 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ]));
3508 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name);
3509 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac);
3510 dev_dbg(ionic->dev, "eth.config.mtu %d\n",
3511 le32_to_cpu(lid->eth.config.mtu));
3512
3513 return 0;
3514}
3515
30b87ab4 3516int ionic_lif_size(struct ionic *ionic)
1a58e196
SN		 3517{
3518 struct ionic_identity *ident = &ionic->ident;
3519 unsigned int nintrs, dev_nintrs;
3520 union ionic_lif_config *lc;
3521 unsigned int ntxqs_per_lif;
3522 unsigned int nrxqs_per_lif;
3523 unsigned int neqs_per_lif;
3524 unsigned int nnqs_per_lif;
3525 unsigned int nxqs, neqs;
3526 unsigned int min_intrs;
3527 int err;
3528
c0b03e83 3529 /* retrieve basic values from FW */
1a58e196
SN		 3530 lc = &ident->lif.eth.config;
3531 dev_nintrs = le32_to_cpu(ident->dev.nintrs);
3532 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
3533 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]);
3534 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]);
3535 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]);
3536
c0b03e83
SN		 3537 /* limit values to play nice with kdump */
3538 if (is_kdump_kernel()) {
3539 dev_nintrs = 2;
3540 neqs_per_lif = 0;
3541 nnqs_per_lif = 0;
3542 ntxqs_per_lif = 1;
3543 nrxqs_per_lif = 1;
3544 }
3545
f0790bcd
SN		 3546 /* reserve last queue id for hardware timestamping */
3547 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) {
3548 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) {
3549 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP);
3550 } else {
3551 ntxqs_per_lif -= 1;
3552 nrxqs_per_lif -= 1;
3553 }
3554 }
3555
1a58e196
SN		 3556 nxqs = min(ntxqs_per_lif, nrxqs_per_lif);
3557 nxqs = min(nxqs, num_online_cpus());
3558 neqs = min(neqs_per_lif, num_online_cpus());
3559
3560try_again:
3561 /* interrupt usage:
3562 * 1 for master lif adminq/notifyq
3563 * 1 for each CPU for master lif TxRx queue pairs
3564 * whatever's left is for RDMA queues
3565 */
3566 nintrs = 1 + nxqs + neqs;
3567 min_intrs = 2; /* adminq + 1 TxRx queue pair */
3568
3569 if (nintrs > dev_nintrs)
3570 goto try_fewer;
3571
3572 err = ionic_bus_alloc_irq_vectors(ionic, nintrs);
3573 if (err < 0 && err != -ENOSPC) {
3574 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err);
3575 return err;
3576 }
3577 if (err == -ENOSPC)
3578 goto try_fewer;
3579
3580 if (err != nintrs) {
3581 ionic_bus_free_irq_vectors(ionic);
3582 goto try_fewer;
3583 }
3584
3585 ionic->nnqs_per_lif = nnqs_per_lif;
3586 ionic->neqs_per_lif = neqs;
3587 ionic->ntxqs_per_lif = nxqs;
3588 ionic->nrxqs_per_lif = nxqs;
3589 ionic->nintrs = nintrs;
3590
3591 ionic_debugfs_add_sizes(ionic);
3592
3593 return 0;
3594
3595try_fewer:
3596 if (nnqs_per_lif > 1) {
3597 nnqs_per_lif >>= 1;
3598 goto try_again;
3599 }
3600 if (neqs > 1) {
3601 neqs >>= 1;
3602 goto try_again;
3603 }
3604 if (nxqs > 1) {
3605 nxqs >>= 1;
3606 goto try_again;
3607 }
3608 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs);
3609 return -ENOSPC;
3610}
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