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3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
13af7a6e | 3 | * Copyright (C) 2009 - QLogic Corporation. |
3d396eb1 | 4 | * All rights reserved. |
80922fbc | 5 | * |
3d396eb1 AK |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
cb8011ad | 10 | * |
3d396eb1 AK |
11 | * This program is distributed in the hope that it will be useful, but |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
cb8011ad | 15 | * |
3d396eb1 | 16 | * You should have received a copy of the GNU General Public License |
0ab75ae8 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
80922fbc | 18 | * |
3d396eb1 | 19 | * The full GNU General Public License is included in this distribution |
4d21fef4 | 20 | * in the file called "COPYING". |
80922fbc | 21 | * |
3d396eb1 AK |
22 | */ |
23 | ||
a5eb62f3 | 24 | #include <linux/io-64-nonatomic-lo-hi.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
3d396eb1 AK |
26 | #include "netxen_nic.h" |
27 | #include "netxen_nic_hw.h" | |
3d396eb1 | 28 | |
c9bdd4b5 ACM |
29 | #include <net/ip.h> |
30 | ||
3ce06a32 DP |
31 | #define MASK(n) ((1ULL<<(n))-1) |
32 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
33 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
34 | #define MS_WIN(addr) (addr & 0x0ffc0000) | |
35 | ||
36 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | |
37 | ||
38 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | |
39 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | |
40 | #define CRB_WINDOW_2M (0x130060) | |
41 | #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) | |
42 | #define CRB_INDIRECT_2M (0x1e0000UL) | |
43 | ||
f03b0ebd DP |
44 | static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, |
45 | void __iomem *addr, u32 data); | |
46 | static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, | |
47 | void __iomem *addr); | |
e98e3350 | 48 | |
1fbe6323 DP |
49 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
50 | ((adapter)->ahw.pci_base0 + (off)) | |
51 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
52 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
53 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
54 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
55 | ||
56 | static void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
57 | unsigned long off) | |
58 | { | |
59 | if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END)) | |
60 | return PCI_OFFSET_FIRST_RANGE(adapter, off); | |
61 | ||
62 | if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END)) | |
63 | return PCI_OFFSET_SECOND_RANGE(adapter, off); | |
64 | ||
65 | if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END)) | |
66 | return PCI_OFFSET_THIRD_RANGE(adapter, off); | |
67 | ||
68 | return NULL; | |
69 | } | |
70 | ||
ea7eaa39 DP |
71 | static crb_128M_2M_block_map_t |
72 | crb_128M_2M_map[64] __cacheline_aligned_in_smp = { | |
3ce06a32 DP |
73 | {{{0, 0, 0, 0} } }, /* 0: PCI */ |
74 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ | |
75 | {1, 0x0110000, 0x0120000, 0x130000}, | |
76 | {1, 0x0120000, 0x0122000, 0x124000}, | |
77 | {1, 0x0130000, 0x0132000, 0x126000}, | |
78 | {1, 0x0140000, 0x0142000, 0x128000}, | |
79 | {1, 0x0150000, 0x0152000, 0x12a000}, | |
80 | {1, 0x0160000, 0x0170000, 0x110000}, | |
81 | {1, 0x0170000, 0x0172000, 0x12e000}, | |
82 | {0, 0x0000000, 0x0000000, 0x000000}, | |
83 | {0, 0x0000000, 0x0000000, 0x000000}, | |
84 | {0, 0x0000000, 0x0000000, 0x000000}, | |
85 | {0, 0x0000000, 0x0000000, 0x000000}, | |
86 | {0, 0x0000000, 0x0000000, 0x000000}, | |
87 | {0, 0x0000000, 0x0000000, 0x000000}, | |
88 | {1, 0x01e0000, 0x01e0800, 0x122000}, | |
89 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
90 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ | |
91 | {{{0, 0, 0, 0} } }, /* 3: */ | |
92 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ | |
93 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ | |
94 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ | |
95 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ | |
96 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ | |
97 | {0, 0x0000000, 0x0000000, 0x000000}, | |
98 | {0, 0x0000000, 0x0000000, 0x000000}, | |
99 | {0, 0x0000000, 0x0000000, 0x000000}, | |
100 | {0, 0x0000000, 0x0000000, 0x000000}, | |
101 | {0, 0x0000000, 0x0000000, 0x000000}, | |
102 | {0, 0x0000000, 0x0000000, 0x000000}, | |
103 | {0, 0x0000000, 0x0000000, 0x000000}, | |
104 | {0, 0x0000000, 0x0000000, 0x000000}, | |
105 | {0, 0x0000000, 0x0000000, 0x000000}, | |
106 | {0, 0x0000000, 0x0000000, 0x000000}, | |
107 | {0, 0x0000000, 0x0000000, 0x000000}, | |
108 | {0, 0x0000000, 0x0000000, 0x000000}, | |
109 | {0, 0x0000000, 0x0000000, 0x000000}, | |
110 | {0, 0x0000000, 0x0000000, 0x000000}, | |
111 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | |
112 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ | |
113 | {0, 0x0000000, 0x0000000, 0x000000}, | |
114 | {0, 0x0000000, 0x0000000, 0x000000}, | |
115 | {0, 0x0000000, 0x0000000, 0x000000}, | |
116 | {0, 0x0000000, 0x0000000, 0x000000}, | |
117 | {0, 0x0000000, 0x0000000, 0x000000}, | |
118 | {0, 0x0000000, 0x0000000, 0x000000}, | |
119 | {0, 0x0000000, 0x0000000, 0x000000}, | |
120 | {0, 0x0000000, 0x0000000, 0x000000}, | |
121 | {0, 0x0000000, 0x0000000, 0x000000}, | |
122 | {0, 0x0000000, 0x0000000, 0x000000}, | |
123 | {0, 0x0000000, 0x0000000, 0x000000}, | |
124 | {0, 0x0000000, 0x0000000, 0x000000}, | |
125 | {0, 0x0000000, 0x0000000, 0x000000}, | |
126 | {0, 0x0000000, 0x0000000, 0x000000}, | |
127 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | |
128 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ | |
129 | {0, 0x0000000, 0x0000000, 0x000000}, | |
130 | {0, 0x0000000, 0x0000000, 0x000000}, | |
131 | {0, 0x0000000, 0x0000000, 0x000000}, | |
132 | {0, 0x0000000, 0x0000000, 0x000000}, | |
133 | {0, 0x0000000, 0x0000000, 0x000000}, | |
134 | {0, 0x0000000, 0x0000000, 0x000000}, | |
135 | {0, 0x0000000, 0x0000000, 0x000000}, | |
136 | {0, 0x0000000, 0x0000000, 0x000000}, | |
137 | {0, 0x0000000, 0x0000000, 0x000000}, | |
138 | {0, 0x0000000, 0x0000000, 0x000000}, | |
139 | {0, 0x0000000, 0x0000000, 0x000000}, | |
140 | {0, 0x0000000, 0x0000000, 0x000000}, | |
141 | {0, 0x0000000, 0x0000000, 0x000000}, | |
142 | {0, 0x0000000, 0x0000000, 0x000000}, | |
143 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | |
144 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ | |
145 | {0, 0x0000000, 0x0000000, 0x000000}, | |
146 | {0, 0x0000000, 0x0000000, 0x000000}, | |
147 | {0, 0x0000000, 0x0000000, 0x000000}, | |
148 | {0, 0x0000000, 0x0000000, 0x000000}, | |
149 | {0, 0x0000000, 0x0000000, 0x000000}, | |
150 | {0, 0x0000000, 0x0000000, 0x000000}, | |
151 | {0, 0x0000000, 0x0000000, 0x000000}, | |
152 | {0, 0x0000000, 0x0000000, 0x000000}, | |
153 | {0, 0x0000000, 0x0000000, 0x000000}, | |
154 | {0, 0x0000000, 0x0000000, 0x000000}, | |
155 | {0, 0x0000000, 0x0000000, 0x000000}, | |
156 | {0, 0x0000000, 0x0000000, 0x000000}, | |
157 | {0, 0x0000000, 0x0000000, 0x000000}, | |
158 | {0, 0x0000000, 0x0000000, 0x000000}, | |
159 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | |
160 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ | |
161 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ | |
162 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ | |
163 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ | |
164 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ | |
165 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ | |
166 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ | |
167 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ | |
168 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ | |
169 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ | |
170 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ | |
171 | {{{0, 0, 0, 0} } }, /* 23: */ | |
172 | {{{0, 0, 0, 0} } }, /* 24: */ | |
173 | {{{0, 0, 0, 0} } }, /* 25: */ | |
174 | {{{0, 0, 0, 0} } }, /* 26: */ | |
175 | {{{0, 0, 0, 0} } }, /* 27: */ | |
176 | {{{0, 0, 0, 0} } }, /* 28: */ | |
177 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ | |
178 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ | |
179 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ | |
180 | {{{0} } }, /* 32: PCI */ | |
181 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ | |
182 | {1, 0x2110000, 0x2120000, 0x130000}, | |
183 | {1, 0x2120000, 0x2122000, 0x124000}, | |
184 | {1, 0x2130000, 0x2132000, 0x126000}, | |
185 | {1, 0x2140000, 0x2142000, 0x128000}, | |
186 | {1, 0x2150000, 0x2152000, 0x12a000}, | |
187 | {1, 0x2160000, 0x2170000, 0x110000}, | |
188 | {1, 0x2170000, 0x2172000, 0x12e000}, | |
189 | {0, 0x0000000, 0x0000000, 0x000000}, | |
190 | {0, 0x0000000, 0x0000000, 0x000000}, | |
191 | {0, 0x0000000, 0x0000000, 0x000000}, | |
192 | {0, 0x0000000, 0x0000000, 0x000000}, | |
193 | {0, 0x0000000, 0x0000000, 0x000000}, | |
194 | {0, 0x0000000, 0x0000000, 0x000000}, | |
195 | {0, 0x0000000, 0x0000000, 0x000000}, | |
196 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
197 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ | |
198 | {{{0} } }, /* 35: */ | |
199 | {{{0} } }, /* 36: */ | |
200 | {{{0} } }, /* 37: */ | |
201 | {{{0} } }, /* 38: */ | |
202 | {{{0} } }, /* 39: */ | |
203 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ | |
204 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ | |
205 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ | |
206 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ | |
207 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ | |
208 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ | |
209 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ | |
210 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ | |
211 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ | |
212 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ | |
213 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ | |
214 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ | |
215 | {{{0} } }, /* 52: */ | |
216 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ | |
217 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ | |
218 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ | |
219 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ | |
220 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ | |
221 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ | |
222 | {{{0} } }, /* 59: I2C0 */ | |
223 | {{{0} } }, /* 60: I2C1 */ | |
224 | {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ | |
225 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ | |
226 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ | |
227 | }; | |
228 | ||
229 | /* | |
230 | * top 12 bits of crb internal address (hub, agent) | |
231 | */ | |
232 | static unsigned crb_hub_agt[64] = | |
233 | { | |
234 | 0, | |
235 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, | |
236 | NETXEN_HW_CRB_HUB_AGT_ADR_MN, | |
237 | NETXEN_HW_CRB_HUB_AGT_ADR_MS, | |
238 | 0, | |
239 | NETXEN_HW_CRB_HUB_AGT_ADR_SRE, | |
240 | NETXEN_HW_CRB_HUB_AGT_ADR_NIU, | |
241 | NETXEN_HW_CRB_HUB_AGT_ADR_QMN, | |
242 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, | |
243 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, | |
244 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, | |
245 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, | |
246 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, | |
247 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, | |
248 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
249 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, | |
250 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, | |
251 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, | |
252 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, | |
253 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, | |
254 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, | |
255 | NETXEN_HW_CRB_HUB_AGT_ADR_PGND, | |
256 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, | |
257 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, | |
258 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, | |
259 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, | |
260 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, | |
261 | 0, | |
262 | NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, | |
263 | NETXEN_HW_CRB_HUB_AGT_ADR_SN, | |
264 | 0, | |
265 | NETXEN_HW_CRB_HUB_AGT_ADR_EG, | |
266 | 0, | |
267 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, | |
268 | NETXEN_HW_CRB_HUB_AGT_ADR_CAM, | |
269 | 0, | |
270 | 0, | |
271 | 0, | |
272 | 0, | |
273 | 0, | |
274 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, | |
275 | 0, | |
276 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, | |
277 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, | |
278 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, | |
279 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, | |
280 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, | |
281 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, | |
282 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, | |
283 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, | |
284 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, | |
285 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
286 | 0, | |
287 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, | |
288 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, | |
289 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, | |
290 | NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, | |
291 | 0, | |
292 | NETXEN_HW_CRB_HUB_AGT_ADR_SMB, | |
293 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, | |
294 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, | |
295 | 0, | |
296 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, | |
297 | 0, | |
298 | }; | |
299 | ||
3d396eb1 AK |
300 | /* PCI Windowing for DDR regions. */ |
301 | ||
3ce06a32 | 302 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
3d396eb1 | 303 | |
c9517e58 DP |
304 | #define NETXEN_PCIE_SEM_TIMEOUT 10000 |
305 | ||
7e12bb0a | 306 | static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
307 | ||
c9517e58 DP |
308 | int |
309 | netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg) | |
310 | { | |
311 | int done = 0, timeout = 0; | |
312 | ||
313 | while (!done) { | |
314 | done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem))); | |
315 | if (done == 1) | |
316 | break; | |
317 | if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT) | |
7cecdca1 | 318 | return -EIO; |
c9517e58 DP |
319 | msleep(1); |
320 | } | |
321 | ||
322 | if (id_reg) | |
323 | NXWR32(adapter, id_reg, adapter->portnum); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | void | |
329 | netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem) | |
330 | { | |
581e8ae4 | 331 | NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem))); |
c9517e58 DP |
332 | } |
333 | ||
7e12bb0a | 334 | static int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) |
3ad4467c DP |
335 | { |
336 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
337 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); | |
338 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | /* Disable an XG interface */ | |
7e12bb0a | 345 | static int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) |
3ad4467c DP |
346 | { |
347 | __u32 mac_cfg; | |
348 | u32 port = adapter->physical_port; | |
349 | ||
350 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
351 | return 0; | |
352 | ||
ed3b856b | 353 | if (port >= NETXEN_NIU_MAX_XG_PORTS) |
3ad4467c DP |
354 | return -EINVAL; |
355 | ||
356 | mac_cfg = 0; | |
357 | if (NXWR32(adapter, | |
358 | NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) | |
359 | return -EIO; | |
360 | return 0; | |
361 | } | |
362 | ||
623621b0 DP |
363 | #define NETXEN_UNICAST_ADDR(port, index) \ |
364 | (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) | |
365 | #define NETXEN_MCAST_ADDR(port, index) \ | |
366 | (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) | |
367 | #define MAC_HI(addr) \ | |
368 | ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) | |
369 | #define MAC_LO(addr) \ | |
370 | ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) | |
371 | ||
7e12bb0a | 372 | static int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) |
3ad4467c | 373 | { |
a7483b0a NK |
374 | u32 mac_cfg; |
375 | u32 cnt = 0; | |
376 | __u32 reg = 0x0200; | |
3ad4467c | 377 | u32 port = adapter->physical_port; |
a7483b0a | 378 | u16 board_type = adapter->ahw.board_type; |
3ad4467c | 379 | |
ed3b856b | 380 | if (port >= NETXEN_NIU_MAX_XG_PORTS) |
3ad4467c DP |
381 | return -EINVAL; |
382 | ||
a7483b0a NK |
383 | mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port)); |
384 | mac_cfg &= ~0x4; | |
385 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); | |
3ad4467c | 386 | |
a7483b0a NK |
387 | if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) || |
388 | (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ)) | |
389 | reg = (0x20 << port); | |
3ad4467c | 390 | |
a7483b0a NK |
391 | NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg); |
392 | ||
393 | mdelay(10); | |
394 | ||
395 | while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20) | |
396 | mdelay(10); | |
397 | ||
398 | if (cnt < 20) { | |
399 | ||
400 | reg = NXRD32(adapter, | |
401 | NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port)); | |
402 | ||
403 | if (mode == NETXEN_NIU_PROMISC_MODE) | |
404 | reg = (reg | 0x2000UL); | |
405 | else | |
406 | reg = (reg & ~0x2000UL); | |
407 | ||
408 | if (mode == NETXEN_NIU_ALLMULTI_MODE) | |
409 | reg = (reg | 0x1000UL); | |
410 | else | |
411 | reg = (reg & ~0x1000UL); | |
412 | ||
413 | NXWR32(adapter, | |
414 | NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); | |
415 | } | |
416 | ||
417 | mac_cfg |= 0x4; | |
418 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); | |
3ad4467c DP |
419 | |
420 | return 0; | |
421 | } | |
422 | ||
7e12bb0a | 423 | static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) |
3ad4467c DP |
424 | { |
425 | u32 mac_hi, mac_lo; | |
426 | u32 reg_hi, reg_lo; | |
427 | ||
428 | u8 phy = adapter->physical_port; | |
429 | ||
430 | if (phy >= NETXEN_NIU_MAX_XG_PORTS) | |
431 | return -EINVAL; | |
432 | ||
433 | mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24); | |
434 | mac_hi = addr[2] | ((u32)addr[3] << 8) | | |
435 | ((u32)addr[4] << 16) | ((u32)addr[5] << 24); | |
436 | ||
437 | reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy); | |
438 | reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy); | |
439 | ||
440 | /* write twice to flush */ | |
441 | if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) | |
442 | return -EIO; | |
443 | if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) | |
444 | return -EIO; | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
623621b0 DP |
449 | static int |
450 | netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) | |
451 | { | |
452 | u32 val = 0; | |
453 | u16 port = adapter->physical_port; | |
5d09e534 | 454 | u8 *addr = adapter->mac_addr; |
623621b0 DP |
455 | |
456 | if (adapter->mc_enabled) | |
457 | return 0; | |
458 | ||
f98a9f69 | 459 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
623621b0 | 460 | val |= (1UL << (28+port)); |
f98a9f69 | 461 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
623621b0 DP |
462 | |
463 | /* add broadcast addr to filter */ | |
464 | val = 0xffffff; | |
f98a9f69 DP |
465 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
466 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); | |
623621b0 DP |
467 | |
468 | /* add station addr to filter */ | |
469 | val = MAC_HI(addr); | |
f98a9f69 | 470 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); |
623621b0 | 471 | val = MAC_LO(addr); |
f98a9f69 | 472 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); |
623621b0 DP |
473 | |
474 | adapter->mc_enabled = 1; | |
475 | return 0; | |
476 | } | |
477 | ||
478 | static int | |
479 | netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) | |
480 | { | |
481 | u32 val = 0; | |
482 | u16 port = adapter->physical_port; | |
5d09e534 | 483 | u8 *addr = adapter->mac_addr; |
623621b0 DP |
484 | |
485 | if (!adapter->mc_enabled) | |
486 | return 0; | |
487 | ||
f98a9f69 | 488 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
623621b0 | 489 | val &= ~(1UL << (28+port)); |
f98a9f69 | 490 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
623621b0 DP |
491 | |
492 | val = MAC_HI(addr); | |
f98a9f69 | 493 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
623621b0 | 494 | val = MAC_LO(addr); |
f98a9f69 | 495 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); |
623621b0 | 496 | |
f98a9f69 DP |
497 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); |
498 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); | |
623621b0 DP |
499 | |
500 | adapter->mc_enabled = 0; | |
501 | return 0; | |
502 | } | |
503 | ||
504 | static int | |
505 | netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, | |
506 | int index, u8 *addr) | |
507 | { | |
508 | u32 hi = 0, lo = 0; | |
509 | u16 port = adapter->physical_port; | |
510 | ||
511 | lo = MAC_LO(addr); | |
512 | hi = MAC_HI(addr); | |
513 | ||
f98a9f69 DP |
514 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi); |
515 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo); | |
623621b0 DP |
516 | |
517 | return 0; | |
518 | } | |
519 | ||
7e12bb0a | 520 | static void netxen_p2_nic_set_multi(struct net_device *netdev) |
3d396eb1 | 521 | { |
3176ff3e | 522 | struct netxen_adapter *adapter = netdev_priv(netdev); |
22bedad3 | 523 | struct netdev_hw_addr *ha; |
1409a932 | 524 | u8 null_addr[ETH_ALEN]; |
f9dcbcc9 | 525 | int i; |
623621b0 | 526 | |
c7bf7169 | 527 | eth_zero_addr(null_addr); |
3d396eb1 | 528 | |
3d396eb1 | 529 | if (netdev->flags & IFF_PROMISC) { |
623621b0 DP |
530 | |
531 | adapter->set_promisc(adapter, | |
532 | NETXEN_NIU_PROMISC_MODE); | |
533 | ||
534 | /* Full promiscuous mode */ | |
535 | netxen_nic_disable_mcast_filter(adapter); | |
536 | ||
537 | return; | |
538 | } | |
539 | ||
4cd24eaf | 540 | if (netdev_mc_empty(netdev)) { |
623621b0 DP |
541 | adapter->set_promisc(adapter, |
542 | NETXEN_NIU_NON_PROMISC_MODE); | |
543 | netxen_nic_disable_mcast_filter(adapter); | |
544 | return; | |
545 | } | |
546 | ||
547 | adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); | |
548 | if (netdev->flags & IFF_ALLMULTI || | |
4cd24eaf | 549 | netdev_mc_count(netdev) > adapter->max_mc_count) { |
623621b0 DP |
550 | netxen_nic_disable_mcast_filter(adapter); |
551 | return; | |
3d396eb1 | 552 | } |
623621b0 DP |
553 | |
554 | netxen_nic_enable_mcast_filter(adapter); | |
555 | ||
f9dcbcc9 | 556 | i = 0; |
22bedad3 JP |
557 | netdev_for_each_mc_addr(ha, netdev) |
558 | netxen_nic_set_mcast_addr(adapter, i++, ha->addr); | |
623621b0 DP |
559 | |
560 | /* Clear out remaining addresses */ | |
f9dcbcc9 JP |
561 | while (i < adapter->max_mc_count) |
562 | netxen_nic_set_mcast_addr(adapter, i++, null_addr); | |
3d396eb1 AK |
563 | } |
564 | ||
c9fc891f DP |
565 | static int |
566 | netxen_send_cmd_descs(struct netxen_adapter *adapter, | |
d877f1e3 | 567 | struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) |
c9fc891f | 568 | { |
d877f1e3 | 569 | u32 i, producer, consumer; |
c9fc891f DP |
570 | struct netxen_cmd_buffer *pbuf; |
571 | struct cmd_desc_type0 *cmd_desc; | |
d877f1e3 | 572 | struct nx_host_tx_ring *tx_ring; |
c9fc891f DP |
573 | |
574 | i = 0; | |
575 | ||
db4cfd8a DP |
576 | if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) |
577 | return -EIO; | |
578 | ||
4ea528a1 | 579 | tx_ring = adapter->tx_ring; |
b2af9cb0 | 580 | __netif_tx_lock_bh(tx_ring->txq); |
03e678ee | 581 | |
d877f1e3 DP |
582 | producer = tx_ring->producer; |
583 | consumer = tx_ring->sw_consumer; | |
584 | ||
b2af9cb0 DP |
585 | if (nr_desc >= netxen_tx_avail(tx_ring)) { |
586 | netif_tx_stop_queue(tx_ring->txq); | |
7a9905e6 RB |
587 | smp_mb(); |
588 | if (netxen_tx_avail(tx_ring) > nr_desc) { | |
589 | if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) | |
590 | netif_tx_wake_queue(tx_ring->txq); | |
591 | } else { | |
592 | __netif_tx_unlock_bh(tx_ring->txq); | |
593 | return -EBUSY; | |
594 | } | |
d877f1e3 DP |
595 | } |
596 | ||
c9fc891f DP |
597 | do { |
598 | cmd_desc = &cmd_desc_arr[i]; | |
599 | ||
d877f1e3 | 600 | pbuf = &tx_ring->cmd_buf_arr[producer]; |
c9fc891f | 601 | pbuf->skb = NULL; |
c9fc891f | 602 | pbuf->frag_count = 0; |
c9fc891f | 603 | |
d877f1e3 | 604 | memcpy(&tx_ring->desc_head[producer], |
c9fc891f DP |
605 | &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); |
606 | ||
d877f1e3 | 607 | producer = get_next_index(producer, tx_ring->num_desc); |
c9fc891f DP |
608 | i++; |
609 | ||
d877f1e3 | 610 | } while (i != nr_desc); |
c9fc891f | 611 | |
d877f1e3 | 612 | tx_ring->producer = producer; |
c9fc891f | 613 | |
cb2107be | 614 | netxen_nic_update_cmd_producer(adapter, tx_ring); |
c9fc891f | 615 | |
b2af9cb0 | 616 | __netif_tx_unlock_bh(tx_ring->txq); |
03e678ee | 617 | |
c9fc891f DP |
618 | return 0; |
619 | } | |
620 | ||
5cf4d323 DP |
621 | static int |
622 | nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op) | |
c9fc891f | 623 | { |
c9fc891f | 624 | nx_nic_req_t req; |
2edbb454 DP |
625 | nx_mac_req_t *mac_req; |
626 | u64 word; | |
c9fc891f DP |
627 | |
628 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
2edbb454 DP |
629 | req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); |
630 | ||
631 | word = NX_MAC_EVENT | ((u64)adapter->portnum << 16); | |
632 | req.req_hdr = cpu_to_le64(word); | |
633 | ||
634 | mac_req = (nx_mac_req_t *)&req.words[0]; | |
635 | mac_req->op = op; | |
d458cdf7 | 636 | memcpy(mac_req->mac_addr, addr, ETH_ALEN); |
c9fc891f | 637 | |
5cf4d323 DP |
638 | return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
639 | } | |
640 | ||
641 | static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, | |
215faf9c | 642 | const u8 *addr, struct list_head *del_list) |
5cf4d323 DP |
643 | { |
644 | struct list_head *head; | |
645 | nx_mac_list_t *cur; | |
646 | ||
647 | /* look up if already exists */ | |
648 | list_for_each(head, del_list) { | |
649 | cur = list_entry(head, nx_mac_list_t, list); | |
650 | ||
202af853 | 651 | if (ether_addr_equal(addr, cur->mac_addr)) { |
5cf4d323 DP |
652 | list_move_tail(head, &adapter->mac_list); |
653 | return 0; | |
654 | } | |
c9fc891f DP |
655 | } |
656 | ||
5cf4d323 | 657 | cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC); |
b2adaca9 | 658 | if (cur == NULL) |
5cf4d323 | 659 | return -ENOMEM; |
b2adaca9 | 660 | |
5cf4d323 DP |
661 | memcpy(cur->mac_addr, addr, ETH_ALEN); |
662 | list_add_tail(&cur->list, &adapter->mac_list); | |
663 | return nx_p3_sre_macaddr_change(adapter, | |
664 | cur->mac_addr, NETXEN_MAC_ADD); | |
c9fc891f DP |
665 | } |
666 | ||
7e12bb0a | 667 | static void netxen_p3_nic_set_multi(struct net_device *netdev) |
c9fc891f DP |
668 | { |
669 | struct netxen_adapter *adapter = netdev_priv(netdev); | |
22bedad3 | 670 | struct netdev_hw_addr *ha; |
215faf9c JP |
671 | static const u8 bcast_addr[ETH_ALEN] = { |
672 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff | |
673 | }; | |
9ad27643 | 674 | u32 mode = VPORT_MISS_MODE_DROP; |
5cf4d323 DP |
675 | LIST_HEAD(del_list); |
676 | struct list_head *head; | |
677 | nx_mac_list_t *cur; | |
c9fc891f | 678 | |
d49c9640 AKS |
679 | if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) |
680 | return; | |
681 | ||
5cf4d323 | 682 | list_splice_tail_init(&adapter->mac_list, &del_list); |
c9fc891f | 683 | |
5d09e534 | 684 | nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list); |
5cf4d323 | 685 | nx_p3_nic_add_mac(adapter, bcast_addr, &del_list); |
9ad27643 DP |
686 | |
687 | if (netdev->flags & IFF_PROMISC) { | |
688 | mode = VPORT_MISS_MODE_ACCEPT_ALL; | |
689 | goto send_fw_cmd; | |
690 | } | |
691 | ||
692 | if ((netdev->flags & IFF_ALLMULTI) || | |
4cd24eaf | 693 | (netdev_mc_count(netdev) > adapter->max_mc_count)) { |
9ad27643 DP |
694 | mode = VPORT_MISS_MODE_ACCEPT_MULTI; |
695 | goto send_fw_cmd; | |
696 | } | |
697 | ||
4cd24eaf | 698 | if (!netdev_mc_empty(netdev)) { |
22bedad3 JP |
699 | netdev_for_each_mc_addr(ha, netdev) |
700 | nx_p3_nic_add_mac(adapter, ha->addr, &del_list); | |
c9fc891f | 701 | } |
9ad27643 DP |
702 | |
703 | send_fw_cmd: | |
704 | adapter->set_promisc(adapter, mode); | |
5cf4d323 DP |
705 | head = &del_list; |
706 | while (!list_empty(head)) { | |
707 | cur = list_entry(head->next, nx_mac_list_t, list); | |
708 | ||
709 | nx_p3_sre_macaddr_change(adapter, | |
710 | cur->mac_addr, NETXEN_MAC_DEL); | |
711 | list_del(&cur->list); | |
c9fc891f | 712 | kfree(cur); |
c9fc891f DP |
713 | } |
714 | } | |
715 | ||
7e12bb0a | 716 | static int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) |
9ad27643 DP |
717 | { |
718 | nx_nic_req_t req; | |
2edbb454 | 719 | u64 word; |
9ad27643 DP |
720 | |
721 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
722 | ||
2edbb454 DP |
723 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
724 | ||
725 | word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE | | |
726 | ((u64)adapter->portnum << 16); | |
727 | req.req_hdr = cpu_to_le64(word); | |
728 | ||
9ad27643 DP |
729 | req.words[0] = cpu_to_le64(mode); |
730 | ||
731 | return netxen_send_cmd_descs(adapter, | |
732 | (struct cmd_desc_type0 *)&req, 1); | |
733 | } | |
734 | ||
06e9d9f9 DP |
735 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter) |
736 | { | |
5cf4d323 DP |
737 | nx_mac_list_t *cur; |
738 | struct list_head *head = &adapter->mac_list; | |
739 | ||
740 | while (!list_empty(head)) { | |
741 | cur = list_entry(head->next, nx_mac_list_t, list); | |
742 | nx_p3_sre_macaddr_change(adapter, | |
743 | cur->mac_addr, NETXEN_MAC_DEL); | |
744 | list_del(&cur->list); | |
06e9d9f9 | 745 | kfree(cur); |
06e9d9f9 DP |
746 | } |
747 | } | |
748 | ||
7e12bb0a | 749 | static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) |
3d0a3cc9 DP |
750 | { |
751 | /* assuming caller has already copied new addr to netdev */ | |
752 | netxen_p3_nic_set_multi(adapter->netdev); | |
753 | return 0; | |
754 | } | |
755 | ||
cd1f8160 DP |
756 | #define NETXEN_CONFIG_INTR_COALESCE 3 |
757 | ||
758 | /* | |
759 | * Send the interrupt coalescing parameter set by ethtool to the card. | |
760 | */ | |
761 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter) | |
762 | { | |
763 | nx_nic_req_t req; | |
c0703950 AKS |
764 | u64 word[6]; |
765 | int rv, i; | |
cd1f8160 DP |
766 | |
767 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
c0703950 | 768 | memset(word, 0, sizeof(word)); |
cd1f8160 | 769 | |
1bb482f8 | 770 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
2edbb454 | 771 | |
c0703950 AKS |
772 | word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); |
773 | req.req_hdr = cpu_to_le64(word[0]); | |
cd1f8160 | 774 | |
c0703950 AKS |
775 | memcpy(&word[0], &adapter->coal, sizeof(adapter->coal)); |
776 | for (i = 0; i < 6; i++) | |
777 | req.words[i] = cpu_to_le64(word[i]); | |
cd1f8160 DP |
778 | |
779 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
780 | if (rv != 0) { | |
781 | printk(KERN_ERR "ERROR. Could not send " | |
782 | "interrupt coalescing parameters\n"); | |
783 | } | |
784 | ||
785 | return rv; | |
786 | } | |
787 | ||
1bb482f8 NK |
788 | int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable) |
789 | { | |
790 | nx_nic_req_t req; | |
791 | u64 word; | |
792 | int rv = 0; | |
793 | ||
34624d66 SC |
794 | if (!test_bit(__NX_FW_ATTACHED, &adapter->state)) |
795 | return 0; | |
796 | ||
1bb482f8 NK |
797 | memset(&req, 0, sizeof(nx_nic_req_t)); |
798 | ||
799 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
800 | ||
801 | word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); | |
802 | req.req_hdr = cpu_to_le64(word); | |
803 | ||
804 | req.words[0] = cpu_to_le64(enable); | |
805 | ||
806 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
807 | if (rv != 0) { | |
808 | printk(KERN_ERR "ERROR. Could not send " | |
809 | "configure hw lro request\n"); | |
810 | } | |
811 | ||
1bb482f8 NK |
812 | return rv; |
813 | } | |
814 | ||
fa3ce355 NK |
815 | int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable) |
816 | { | |
817 | nx_nic_req_t req; | |
818 | u64 word; | |
819 | int rv = 0; | |
820 | ||
821 | if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable) | |
822 | return rv; | |
823 | ||
824 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
825 | ||
826 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
827 | ||
828 | word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING | | |
829 | ((u64)adapter->portnum << 16); | |
830 | req.req_hdr = cpu_to_le64(word); | |
831 | ||
832 | req.words[0] = cpu_to_le64(enable); | |
833 | ||
834 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
835 | if (rv != 0) { | |
836 | printk(KERN_ERR "ERROR. Could not send " | |
837 | "configure bridge mode request\n"); | |
838 | } | |
839 | ||
840 | adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED; | |
841 | ||
842 | return rv; | |
843 | } | |
844 | ||
845 | ||
d8b100c5 DP |
846 | #define RSS_HASHTYPE_IP_TCP 0x3 |
847 | ||
848 | int netxen_config_rss(struct netxen_adapter *adapter, int enable) | |
849 | { | |
850 | nx_nic_req_t req; | |
851 | u64 word; | |
852 | int i, rv; | |
853 | ||
215faf9c JP |
854 | static const u64 key[] = { |
855 | 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, | |
856 | 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, | |
857 | 0x255b0ec26d5a56daULL | |
858 | }; | |
d8b100c5 DP |
859 | |
860 | ||
861 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
862 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
863 | ||
864 | word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); | |
865 | req.req_hdr = cpu_to_le64(word); | |
866 | ||
867 | /* | |
868 | * RSS request: | |
869 | * bits 3-0: hash_method | |
870 | * 5-4: hash_type_ipv4 | |
871 | * 7-6: hash_type_ipv6 | |
872 | * 8: enable | |
873 | * 9: use indirection table | |
874 | * 47-10: reserved | |
875 | * 63-48: indirection table mask | |
876 | */ | |
877 | word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | | |
878 | ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | | |
879 | ((u64)(enable & 0x1) << 8) | | |
880 | ((0x7ULL) << 48); | |
881 | req.words[0] = cpu_to_le64(word); | |
215faf9c | 882 | for (i = 0; i < ARRAY_SIZE(key); i++) |
d8b100c5 DP |
883 | req.words[i+1] = cpu_to_le64(key[i]); |
884 | ||
885 | ||
886 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
887 | if (rv != 0) { | |
888 | printk(KERN_ERR "%s: could not configure RSS\n", | |
889 | adapter->netdev->name); | |
890 | } | |
891 | ||
892 | return rv; | |
893 | } | |
894 | ||
06d6c108 | 895 | int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd) |
6598b169 DP |
896 | { |
897 | nx_nic_req_t req; | |
898 | u64 word; | |
899 | int rv; | |
900 | ||
901 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
902 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
903 | ||
904 | word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); | |
905 | req.req_hdr = cpu_to_le64(word); | |
906 | ||
907 | req.words[0] = cpu_to_le64(cmd); | |
06d6c108 | 908 | memcpy(&req.words[1], &ip, sizeof(u32)); |
6598b169 DP |
909 | |
910 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
911 | if (rv != 0) { | |
9b13494c | 912 | printk(KERN_ERR "%s: could not notify %s IP 0x%x request\n", |
6598b169 DP |
913 | adapter->netdev->name, |
914 | (cmd == NX_IP_UP) ? "Add" : "Remove", ip); | |
915 | } | |
916 | return rv; | |
917 | } | |
918 | ||
3bf26ce3 DP |
919 | int netxen_linkevent_request(struct netxen_adapter *adapter, int enable) |
920 | { | |
921 | nx_nic_req_t req; | |
922 | u64 word; | |
923 | int rv; | |
924 | ||
925 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
926 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
927 | ||
928 | word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); | |
929 | req.req_hdr = cpu_to_le64(word); | |
22527864 | 930 | req.words[0] = cpu_to_le64(enable | (enable << 8)); |
3bf26ce3 DP |
931 | |
932 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
933 | if (rv != 0) { | |
934 | printk(KERN_ERR "%s: could not configure link notification\n", | |
935 | adapter->netdev->name); | |
936 | } | |
937 | ||
938 | return rv; | |
939 | } | |
940 | ||
1bb482f8 NK |
941 | int netxen_send_lro_cleanup(struct netxen_adapter *adapter) |
942 | { | |
943 | nx_nic_req_t req; | |
944 | u64 word; | |
945 | int rv; | |
946 | ||
34624d66 SC |
947 | if (!test_bit(__NX_FW_ATTACHED, &adapter->state)) |
948 | return 0; | |
949 | ||
1bb482f8 NK |
950 | memset(&req, 0, sizeof(nx_nic_req_t)); |
951 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
952 | ||
953 | word = NX_NIC_H2C_OPCODE_LRO_REQUEST | | |
954 | ((u64)adapter->portnum << 16) | | |
955 | ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ; | |
956 | ||
957 | req.req_hdr = cpu_to_le64(word); | |
958 | ||
959 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
960 | if (rv != 0) { | |
961 | printk(KERN_ERR "%s: could not cleanup lro flows\n", | |
962 | adapter->netdev->name); | |
963 | } | |
964 | return rv; | |
965 | } | |
966 | ||
3d396eb1 AK |
967 | /* |
968 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit | |
969 | * @returns 0 on success, negative on failure | |
970 | */ | |
c9fc891f DP |
971 | |
972 | #define MTU_FUDGE_FACTOR 100 | |
973 | ||
3d396eb1 AK |
974 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) |
975 | { | |
3176ff3e | 976 | struct netxen_adapter *adapter = netdev_priv(netdev); |
9ad27643 | 977 | int rc = 0; |
3d396eb1 | 978 | |
80922fbc | 979 | if (adapter->set_mtu) |
9ad27643 | 980 | rc = adapter->set_mtu(adapter, mtu); |
3d396eb1 | 981 | |
9ad27643 DP |
982 | if (!rc) |
983 | netdev->mtu = mtu; | |
c9fc891f | 984 | |
9ad27643 | 985 | return rc; |
3d396eb1 AK |
986 | } |
987 | ||
3d396eb1 | 988 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
f305f789 | 989 | int size, __le32 * buf) |
3d396eb1 | 990 | { |
1e2d0059 | 991 | int i, v, addr; |
f305f789 | 992 | __le32 *ptr32; |
545fea54 | 993 | int ret; |
3d396eb1 AK |
994 | |
995 | addr = base; | |
996 | ptr32 = buf; | |
997 | for (i = 0; i < size / sizeof(u32); i++) { | |
545fea54 DC |
998 | ret = netxen_rom_fast_read(adapter, addr, &v); |
999 | if (ret) | |
1000 | return ret; | |
1001 | ||
f305f789 | 1002 | *ptr32 = cpu_to_le32(v); |
3d396eb1 AK |
1003 | ptr32++; |
1004 | addr += sizeof(u32); | |
1005 | } | |
1006 | if ((char *)buf + size > (char *)ptr32) { | |
f305f789 | 1007 | __le32 local; |
545fea54 DC |
1008 | ret = netxen_rom_fast_read(adapter, addr, &v); |
1009 | if (ret) | |
1010 | return ret; | |
f305f789 | 1011 | local = cpu_to_le32(v); |
3d396eb1 AK |
1012 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
1013 | } | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
a03d2451 | 1018 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac) |
3d396eb1 | 1019 | { |
9dc28efe DP |
1020 | __le32 *pmac = (__le32 *) mac; |
1021 | u32 offset; | |
3d396eb1 | 1022 | |
06db58c0 | 1023 | offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64)); |
9dc28efe DP |
1024 | |
1025 | if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) | |
3d396eb1 | 1026 | return -1; |
9dc28efe | 1027 | |
06d6c108 | 1028 | if (*mac == ~0ULL) { |
9dc28efe | 1029 | |
06db58c0 DP |
1030 | offset = NX_OLD_MAC_ADDR_OFFSET + |
1031 | (adapter->portnum * sizeof(u64)); | |
9dc28efe | 1032 | |
3d396eb1 | 1033 | if (netxen_get_flash_block(adapter, |
9dc28efe | 1034 | offset, sizeof(u64), pmac) == -1) |
3d396eb1 | 1035 | return -1; |
9dc28efe | 1036 | |
06d6c108 | 1037 | if (*mac == ~0ULL) |
3d396eb1 AK |
1038 | return -1; |
1039 | } | |
1040 | return 0; | |
1041 | } | |
1042 | ||
a03d2451 | 1043 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac) |
9dc28efe DP |
1044 | { |
1045 | uint32_t crbaddr, mac_hi, mac_lo; | |
1046 | int pci_func = adapter->ahw.pci_func; | |
1047 | ||
1048 | crbaddr = CRB_MAC_BLOCK_START + | |
1049 | (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); | |
1050 | ||
f98a9f69 DP |
1051 | mac_lo = NXRD32(adapter, crbaddr); |
1052 | mac_hi = NXRD32(adapter, crbaddr+4); | |
9dc28efe | 1053 | |
9dc28efe | 1054 | if (pci_func & 1) |
2edbb454 | 1055 | *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); |
9dc28efe | 1056 | else |
2edbb454 | 1057 | *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32)); |
9dc28efe DP |
1058 | |
1059 | return 0; | |
1060 | } | |
1061 | ||
3d396eb1 AK |
1062 | /* |
1063 | * Changes the CRB window to the specified window. | |
1064 | */ | |
195c5f98 | 1065 | static void |
907fa120 DP |
1066 | netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter, |
1067 | u32 window) | |
3d396eb1 AK |
1068 | { |
1069 | void __iomem *offset; | |
907fa120 DP |
1070 | int count = 10; |
1071 | u8 func = adapter->ahw.pci_func; | |
3d396eb1 | 1072 | |
907fa120 | 1073 | if (adapter->ahw.crb_win == window) |
3d396eb1 | 1074 | return; |
907fa120 | 1075 | |
e4c93c81 DP |
1076 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
1077 | NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); | |
3d396eb1 | 1078 | |
907fa120 DP |
1079 | writel(window, offset); |
1080 | do { | |
1081 | if (window == readl(offset)) | |
1082 | break; | |
3d396eb1 | 1083 | |
907fa120 DP |
1084 | if (printk_ratelimit()) |
1085 | dev_warn(&adapter->pdev->dev, | |
1086 | "failed to set CRB window to %d\n", | |
1087 | (window == NETXEN_WINDOW_ONE)); | |
1088 | udelay(1); | |
3d396eb1 | 1089 | |
907fa120 | 1090 | } while (--count > 0); |
3d396eb1 | 1091 | |
907fa120 DP |
1092 | if (count > 0) |
1093 | adapter->ahw.crb_win = window; | |
3d396eb1 AK |
1094 | } |
1095 | ||
3ce06a32 | 1096 | /* |
7cecdca1 | 1097 | * Returns < 0 if off is not valid, |
3ce06a32 DP |
1098 | * 1 if window access is needed. 'off' is set to offset from |
1099 | * CRB space in 128M pci map | |
1100 | * 0 if no window access is needed. 'off' is set to 2M addr | |
1101 | * In: 'off' is offset from base in 128M pci map | |
1102 | */ | |
1103 | static int | |
a9ac07de DP |
1104 | netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, |
1105 | ulong off, void __iomem **addr) | |
3ce06a32 | 1106 | { |
3ce06a32 DP |
1107 | crb_128M_2M_sub_block_map_t *m; |
1108 | ||
1109 | ||
a9ac07de | 1110 | if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE)) |
7cecdca1 | 1111 | return -EINVAL; |
3ce06a32 | 1112 | |
a9ac07de | 1113 | off -= NETXEN_PCI_CRBSPACE; |
3ce06a32 DP |
1114 | |
1115 | /* | |
1116 | * Try direct map | |
1117 | */ | |
a9ac07de | 1118 | m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; |
3ce06a32 | 1119 | |
a9ac07de DP |
1120 | if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { |
1121 | *addr = adapter->ahw.pci_base0 + m->start_2M + | |
1122 | (off - m->start_128M); | |
3ce06a32 DP |
1123 | return 0; |
1124 | } | |
1125 | ||
1126 | /* | |
1127 | * Not in direct map, use crb window | |
1128 | */ | |
a9ac07de DP |
1129 | *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + |
1130 | (off & MASK(16)); | |
3ce06a32 DP |
1131 | return 1; |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * In: 'off' is offset from CRB space in 128M pci map | |
1136 | * Out: 'off' is 2M pci map addr | |
1137 | * side effect: lock crb window | |
1138 | */ | |
1139 | static void | |
a9ac07de | 1140 | netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off) |
3ce06a32 | 1141 | { |
907fa120 DP |
1142 | u32 window; |
1143 | void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M; | |
3ce06a32 | 1144 | |
a9ac07de DP |
1145 | off -= NETXEN_PCI_CRBSPACE; |
1146 | ||
1147 | window = CRB_HI(off); | |
907fa120 | 1148 | |
907fa120 DP |
1149 | writel(window, addr); |
1150 | if (readl(addr) != window) { | |
1151 | if (printk_ratelimit()) | |
1152 | dev_warn(&adapter->pdev->dev, | |
1153 | "failed to set CRB window to %d off 0x%lx\n", | |
a9ac07de | 1154 | window, off); |
3ce06a32 | 1155 | } |
3ce06a32 DP |
1156 | } |
1157 | ||
f58dbd73 NK |
1158 | static void __iomem * |
1159 | netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter, | |
1160 | ulong win_off, void __iomem **mem_ptr) | |
1161 | { | |
1162 | ulong off = win_off; | |
1163 | void __iomem *addr; | |
1164 | resource_size_t mem_base; | |
1165 | ||
1166 | if (ADDR_IN_WINDOW1(win_off)) | |
1167 | off = NETXEN_CRB_NORMAL(win_off); | |
1168 | ||
1169 | addr = pci_base_offset(adapter, off); | |
1170 | if (addr) | |
1171 | return addr; | |
1172 | ||
1173 | if (adapter->ahw.pci_len0 == 0) | |
1174 | off -= NETXEN_PCI_CRBSPACE; | |
1175 | ||
1176 | mem_base = pci_resource_start(adapter->pdev, 0); | |
1177 | *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE); | |
1178 | if (*mem_ptr) | |
1179 | addr = *mem_ptr + (off & (PAGE_SIZE - 1)); | |
1180 | ||
1181 | return addr; | |
1182 | } | |
1183 | ||
195c5f98 | 1184 | static int |
1fbe6323 | 1185 | netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data) |
3d396eb1 | 1186 | { |
195c5f98 | 1187 | unsigned long flags; |
f58dbd73 | 1188 | void __iomem *addr, *mem_ptr = NULL; |
3d396eb1 | 1189 | |
f58dbd73 NK |
1190 | addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); |
1191 | if (!addr) | |
1192 | return -EIO; | |
195c5f98 | 1193 | |
f58dbd73 | 1194 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
f03b0ebd | 1195 | netxen_nic_io_write_128M(adapter, addr, data); |
f58dbd73 | 1196 | } else { /* Window 0 */ |
f03b0ebd | 1197 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
907fa120 | 1198 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
195c5f98 | 1199 | writel(data, addr); |
907fa120 DP |
1200 | netxen_nic_pci_set_crbwindow_128M(adapter, |
1201 | NETXEN_WINDOW_ONE); | |
f03b0ebd | 1202 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
cb8011ad AK |
1203 | } |
1204 | ||
f58dbd73 NK |
1205 | if (mem_ptr) |
1206 | iounmap(mem_ptr); | |
1207 | ||
3d396eb1 AK |
1208 | return 0; |
1209 | } | |
1210 | ||
195c5f98 | 1211 | static u32 |
1fbe6323 | 1212 | netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off) |
3d396eb1 | 1213 | { |
195c5f98 | 1214 | unsigned long flags; |
f58dbd73 | 1215 | void __iomem *addr, *mem_ptr = NULL; |
1fbe6323 | 1216 | u32 data; |
d8313ce0 | 1217 | |
f58dbd73 NK |
1218 | addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); |
1219 | if (!addr) | |
1220 | return -EIO; | |
3d396eb1 | 1221 | |
f58dbd73 | 1222 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
f03b0ebd | 1223 | data = netxen_nic_io_read_128M(adapter, addr); |
f58dbd73 | 1224 | } else { /* Window 0 */ |
f03b0ebd | 1225 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
907fa120 | 1226 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
195c5f98 | 1227 | data = readl(addr); |
907fa120 DP |
1228 | netxen_nic_pci_set_crbwindow_128M(adapter, |
1229 | NETXEN_WINDOW_ONE); | |
f03b0ebd | 1230 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
195c5f98 | 1231 | } |
3d396eb1 | 1232 | |
f58dbd73 NK |
1233 | if (mem_ptr) |
1234 | iounmap(mem_ptr); | |
1235 | ||
1fbe6323 | 1236 | return data; |
3d396eb1 AK |
1237 | } |
1238 | ||
195c5f98 | 1239 | static int |
1fbe6323 | 1240 | netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data) |
3ce06a32 | 1241 | { |
195c5f98 | 1242 | unsigned long flags; |
3ce06a32 | 1243 | int rv; |
a9ac07de | 1244 | void __iomem *addr = NULL; |
3d396eb1 | 1245 | |
a9ac07de | 1246 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); |
3d396eb1 | 1247 | |
7cecdca1 | 1248 | if (rv == 0) { |
a9ac07de | 1249 | writel(data, addr); |
7cecdca1 | 1250 | return 0; |
3ce06a32 DP |
1251 | } |
1252 | ||
7cecdca1 DP |
1253 | if (rv > 0) { |
1254 | /* indirect access */ | |
f03b0ebd | 1255 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
3ce06a32 | 1256 | crb_win_lock(adapter); |
a9ac07de DP |
1257 | netxen_nic_pci_set_crbwindow_2M(adapter, off); |
1258 | writel(data, addr); | |
3ce06a32 | 1259 | crb_win_unlock(adapter); |
f03b0ebd | 1260 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
7cecdca1 DP |
1261 | return 0; |
1262 | } | |
3ce06a32 | 1263 | |
7cecdca1 DP |
1264 | dev_err(&adapter->pdev->dev, |
1265 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1266 | dump_stack(); | |
1267 | return -EIO; | |
3d396eb1 AK |
1268 | } |
1269 | ||
195c5f98 | 1270 | static u32 |
1fbe6323 | 1271 | netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) |
3ce06a32 | 1272 | { |
195c5f98 | 1273 | unsigned long flags; |
3ce06a32 | 1274 | int rv; |
1fbe6323 | 1275 | u32 data; |
a9ac07de | 1276 | void __iomem *addr = NULL; |
3d396eb1 | 1277 | |
a9ac07de | 1278 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); |
3ce06a32 | 1279 | |
7cecdca1 | 1280 | if (rv == 0) |
a9ac07de | 1281 | return readl(addr); |
3ce06a32 | 1282 | |
7cecdca1 DP |
1283 | if (rv > 0) { |
1284 | /* indirect access */ | |
f03b0ebd | 1285 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
3ce06a32 | 1286 | crb_win_lock(adapter); |
a9ac07de DP |
1287 | netxen_nic_pci_set_crbwindow_2M(adapter, off); |
1288 | data = readl(addr); | |
3ce06a32 | 1289 | crb_win_unlock(adapter); |
f03b0ebd | 1290 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
7cecdca1 DP |
1291 | return data; |
1292 | } | |
3ce06a32 | 1293 | |
7cecdca1 DP |
1294 | dev_err(&adapter->pdev->dev, |
1295 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1296 | dump_stack(); | |
1297 | return -1; | |
3ce06a32 DP |
1298 | } |
1299 | ||
195c5f98 AKS |
1300 | /* window 1 registers only */ |
1301 | static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, | |
1302 | void __iomem *addr, u32 data) | |
3ce06a32 | 1303 | { |
f03b0ebd | 1304 | read_lock(&adapter->ahw.crb_lock); |
195c5f98 | 1305 | writel(data, addr); |
f03b0ebd | 1306 | read_unlock(&adapter->ahw.crb_lock); |
195c5f98 AKS |
1307 | } |
1308 | ||
1309 | static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, | |
1310 | void __iomem *addr) | |
1311 | { | |
1312 | u32 val; | |
1313 | ||
f03b0ebd | 1314 | read_lock(&adapter->ahw.crb_lock); |
195c5f98 | 1315 | val = readl(addr); |
f03b0ebd | 1316 | read_unlock(&adapter->ahw.crb_lock); |
195c5f98 AKS |
1317 | |
1318 | return val; | |
3ce06a32 DP |
1319 | } |
1320 | ||
195c5f98 AKS |
1321 | static void netxen_nic_io_write_2M(struct netxen_adapter *adapter, |
1322 | void __iomem *addr, u32 data) | |
3ce06a32 | 1323 | { |
195c5f98 AKS |
1324 | writel(data, addr); |
1325 | } | |
1326 | ||
1327 | static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter, | |
1328 | void __iomem *addr) | |
1329 | { | |
1330 | return readl(addr); | |
1331 | } | |
1332 | ||
1333 | void __iomem * | |
1334 | netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset) | |
1335 | { | |
a9ac07de | 1336 | void __iomem *addr = NULL; |
195c5f98 AKS |
1337 | |
1338 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
a9ac07de DP |
1339 | if ((offset < NETXEN_CRB_PCIX_HOST2) && |
1340 | (offset > NETXEN_CRB_PCIX_HOST)) | |
1341 | addr = PCI_OFFSET_SECOND_RANGE(adapter, offset); | |
1342 | else | |
1343 | addr = NETXEN_CRB_NORMALIZE(adapter, offset); | |
1344 | } else { | |
1345 | WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter, | |
1346 | offset, &addr)); | |
195c5f98 AKS |
1347 | } |
1348 | ||
a9ac07de | 1349 | return addr; |
3ce06a32 DP |
1350 | } |
1351 | ||
47abe356 DP |
1352 | static int |
1353 | netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, | |
1354 | u64 addr, u32 *start) | |
3ce06a32 | 1355 | { |
47abe356 DP |
1356 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
1357 | *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0); | |
1358 | return 0; | |
3ce06a32 | 1359 | } else if (ADDR_IN_RANGE(addr, |
47abe356 DP |
1360 | NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
1361 | *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1); | |
1362 | return 0; | |
1363 | } | |
3ce06a32 | 1364 | |
47abe356 DP |
1365 | return -EIO; |
1366 | } | |
3ce06a32 | 1367 | |
47abe356 DP |
1368 | static int |
1369 | netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |
1370 | u64 addr, u32 *start) | |
1371 | { | |
6abb4b83 | 1372 | u32 window; |
3ce06a32 | 1373 | |
14e2cfbb | 1374 | window = OCM_WIN(addr); |
6abb4b83 | 1375 | |
47abe356 | 1376 | writel(window, adapter->ahw.ocm_win_crb); |
6abb4b83 AKS |
1377 | /* read back to flush */ |
1378 | readl(adapter->ahw.ocm_win_crb); | |
47abe356 DP |
1379 | |
1380 | adapter->ahw.ocm_win = window; | |
1381 | *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr); | |
1382 | return 0; | |
3ce06a32 | 1383 | } |
47abe356 DP |
1384 | |
1385 | static int | |
1386 | netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off, | |
1387 | u64 *data, int op) | |
1388 | { | |
1389 | void __iomem *addr, *mem_ptr = NULL; | |
1390 | resource_size_t mem_base; | |
14e2cfbb | 1391 | int ret; |
47abe356 DP |
1392 | u32 start; |
1393 | ||
f03b0ebd | 1394 | spin_lock(&adapter->ahw.mem_lock); |
47abe356 DP |
1395 | |
1396 | ret = adapter->pci_set_window(adapter, off, &start); | |
1397 | if (ret != 0) | |
1398 | goto unlock; | |
1399 | ||
14e2cfbb SC |
1400 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
1401 | addr = adapter->ahw.pci_base0 + start; | |
1402 | } else { | |
1403 | addr = pci_base_offset(adapter, start); | |
1404 | if (addr) | |
1405 | goto noremap; | |
1406 | ||
1407 | mem_base = pci_resource_start(adapter->pdev, 0) + | |
1408 | (start & PAGE_MASK); | |
1409 | mem_ptr = ioremap(mem_base, PAGE_SIZE); | |
1410 | if (mem_ptr == NULL) { | |
1411 | ret = -EIO; | |
1412 | goto unlock; | |
1413 | } | |
47abe356 | 1414 | |
14e2cfbb | 1415 | addr = mem_ptr + (start & (PAGE_SIZE-1)); |
3d396eb1 | 1416 | } |
47abe356 DP |
1417 | noremap: |
1418 | if (op == 0) /* read */ | |
1419 | *data = readq(addr); | |
1420 | else /* write */ | |
1421 | writeq(*data, addr); | |
1422 | ||
1423 | unlock: | |
f03b0ebd DP |
1424 | spin_unlock(&adapter->ahw.mem_lock); |
1425 | ||
47abe356 DP |
1426 | if (mem_ptr) |
1427 | iounmap(mem_ptr); | |
1428 | return ret; | |
3d396eb1 AK |
1429 | } |
1430 | ||
0b9715e6 AKS |
1431 | void |
1432 | netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data) | |
1433 | { | |
1434 | void __iomem *addr = adapter->ahw.pci_base0 + | |
1435 | NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); | |
1436 | ||
1437 | spin_lock(&adapter->ahw.mem_lock); | |
1438 | *data = readq(addr); | |
1439 | spin_unlock(&adapter->ahw.mem_lock); | |
1440 | } | |
1441 | ||
1442 | void | |
1443 | netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data) | |
1444 | { | |
1445 | void __iomem *addr = adapter->ahw.pci_base0 + | |
1446 | NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); | |
1447 | ||
1448 | spin_lock(&adapter->ahw.mem_lock); | |
1449 | writeq(data, addr); | |
1450 | spin_unlock(&adapter->ahw.mem_lock); | |
1451 | } | |
1452 | ||
3ce06a32 DP |
1453 | #define MAX_CTL_CHECK 1000 |
1454 | ||
195c5f98 | 1455 | static int |
3ce06a32 | 1456 | netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, |
1f5e055d | 1457 | u64 off, u64 data) |
3ce06a32 | 1458 | { |
1f5e055d AKS |
1459 | int j, ret; |
1460 | u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; | |
d8313ce0 | 1461 | void __iomem *mem_crb; |
3ce06a32 | 1462 | |
1f5e055d AKS |
1463 | /* Only 64-bit aligned access */ |
1464 | if (off & 7) | |
ea6828b8 DP |
1465 | return -EIO; |
1466 | ||
1f5e055d | 1467 | /* P2 has different SIU and MIU test agent base addr */ |
ea6828b8 DP |
1468 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1469 | NETXEN_ADDR_QDR_NET_MAX_P2)) { | |
1f5e055d AKS |
1470 | mem_crb = pci_base_offset(adapter, |
1471 | NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); | |
1472 | addr_hi = SIU_TEST_AGT_ADDR_HI; | |
1473 | data_lo = SIU_TEST_AGT_WRDATA_LO; | |
1474 | data_hi = SIU_TEST_AGT_WRDATA_HI; | |
1475 | off_lo = off & SIU_TEST_AGT_ADDR_MASK; | |
1476 | off_hi = SIU_TEST_AGT_UPPER_ADDR(off); | |
ea6828b8 DP |
1477 | goto correct; |
1478 | } | |
3ce06a32 | 1479 | |
ea6828b8 | 1480 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1481 | mem_crb = pci_base_offset(adapter, |
1482 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
1483 | addr_hi = MIU_TEST_AGT_ADDR_HI; | |
1484 | data_lo = MIU_TEST_AGT_WRDATA_LO; | |
1485 | data_hi = MIU_TEST_AGT_WRDATA_HI; | |
1486 | off_lo = off & MIU_TEST_AGT_ADDR_MASK; | |
1487 | off_hi = 0; | |
ea6828b8 DP |
1488 | goto correct; |
1489 | } | |
1490 | ||
47abe356 DP |
1491 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || |
1492 | ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
1493 | if (adapter->ahw.pci_len0 != 0) { | |
1494 | return netxen_nic_pci_mem_access_direct(adapter, | |
1495 | off, &data, 1); | |
1496 | } | |
1497 | } | |
1498 | ||
ea6828b8 DP |
1499 | return -EIO; |
1500 | ||
1501 | correct: | |
f03b0ebd | 1502 | spin_lock(&adapter->ahw.mem_lock); |
907fa120 | 1503 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
3ce06a32 | 1504 | |
1f5e055d AKS |
1505 | writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1506 | writel(off_hi, (mem_crb + addr_hi)); | |
1507 | writel(data & 0xffffffff, (mem_crb + data_lo)); | |
1508 | writel((data >> 32) & 0xffffffff, (mem_crb + data_hi)); | |
1509 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); | |
1510 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | |
1511 | (mem_crb + TEST_AGT_CTRL)); | |
1512 | ||
1513 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1514 | temp = readl((mem_crb + TEST_AGT_CTRL)); | |
1515 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1516 | break; |
3ce06a32 DP |
1517 | } |
1518 | ||
1f5e055d AKS |
1519 | if (j >= MAX_CTL_CHECK) { |
1520 | if (printk_ratelimit()) | |
1521 | dev_err(&adapter->pdev->dev, | |
1522 | "failed to write through agent\n"); | |
1523 | ret = -EIO; | |
1524 | } else | |
1525 | ret = 0; | |
1526 | ||
907fa120 | 1527 | netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); |
f03b0ebd | 1528 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 DP |
1529 | return ret; |
1530 | } | |
1531 | ||
195c5f98 | 1532 | static int |
3ce06a32 | 1533 | netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
1f5e055d | 1534 | u64 off, u64 *data) |
3ce06a32 | 1535 | { |
1f5e055d AKS |
1536 | int j, ret; |
1537 | u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; | |
1538 | u64 val; | |
d8313ce0 | 1539 | void __iomem *mem_crb; |
3ce06a32 | 1540 | |
1f5e055d AKS |
1541 | /* Only 64-bit aligned access */ |
1542 | if (off & 7) | |
ea6828b8 DP |
1543 | return -EIO; |
1544 | ||
1f5e055d | 1545 | /* P2 has different SIU and MIU test agent base addr */ |
ea6828b8 DP |
1546 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1547 | NETXEN_ADDR_QDR_NET_MAX_P2)) { | |
1f5e055d AKS |
1548 | mem_crb = pci_base_offset(adapter, |
1549 | NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); | |
1550 | addr_hi = SIU_TEST_AGT_ADDR_HI; | |
1551 | data_lo = SIU_TEST_AGT_RDDATA_LO; | |
1552 | data_hi = SIU_TEST_AGT_RDDATA_HI; | |
1553 | off_lo = off & SIU_TEST_AGT_ADDR_MASK; | |
1554 | off_hi = SIU_TEST_AGT_UPPER_ADDR(off); | |
ea6828b8 DP |
1555 | goto correct; |
1556 | } | |
3ce06a32 | 1557 | |
ea6828b8 | 1558 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1559 | mem_crb = pci_base_offset(adapter, |
1560 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
1561 | addr_hi = MIU_TEST_AGT_ADDR_HI; | |
1562 | data_lo = MIU_TEST_AGT_RDDATA_LO; | |
1563 | data_hi = MIU_TEST_AGT_RDDATA_HI; | |
1564 | off_lo = off & MIU_TEST_AGT_ADDR_MASK; | |
1565 | off_hi = 0; | |
ea6828b8 DP |
1566 | goto correct; |
1567 | } | |
1568 | ||
47abe356 DP |
1569 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || |
1570 | ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
1571 | if (adapter->ahw.pci_len0 != 0) { | |
1572 | return netxen_nic_pci_mem_access_direct(adapter, | |
1573 | off, data, 0); | |
1574 | } | |
1575 | } | |
1576 | ||
ea6828b8 | 1577 | return -EIO; |
3ce06a32 | 1578 | |
ea6828b8 | 1579 | correct: |
f03b0ebd | 1580 | spin_lock(&adapter->ahw.mem_lock); |
907fa120 | 1581 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
3ce06a32 | 1582 | |
1f5e055d AKS |
1583 | writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1584 | writel(off_hi, (mem_crb + addr_hi)); | |
1585 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | |
1586 | writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); | |
3ce06a32 | 1587 | |
1f5e055d AKS |
1588 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
1589 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1590 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1591 | break; |
1f5e055d | 1592 | } |
3ce06a32 | 1593 | |
1f5e055d AKS |
1594 | if (j >= MAX_CTL_CHECK) { |
1595 | if (printk_ratelimit()) | |
1596 | dev_err(&adapter->pdev->dev, | |
1597 | "failed to read through agent\n"); | |
1598 | ret = -EIO; | |
1599 | } else { | |
1600 | ||
1601 | temp = readl(mem_crb + data_hi); | |
1602 | val = ((u64)temp << 32); | |
1603 | val |= readl(mem_crb + data_lo); | |
1604 | *data = val; | |
1605 | ret = 0; | |
3ce06a32 DP |
1606 | } |
1607 | ||
907fa120 | 1608 | netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); |
f03b0ebd | 1609 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 | 1610 | |
1f5e055d | 1611 | return ret; |
3ce06a32 DP |
1612 | } |
1613 | ||
195c5f98 | 1614 | static int |
3ce06a32 | 1615 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
1f5e055d | 1616 | u64 off, u64 data) |
3ce06a32 | 1617 | { |
215387a4 | 1618 | int j, ret; |
1f5e055d | 1619 | u32 temp, off8; |
ea6828b8 | 1620 | void __iomem *mem_crb; |
3ce06a32 | 1621 | |
1f5e055d AKS |
1622 | /* Only 64-bit aligned access */ |
1623 | if (off & 7) | |
ea6828b8 DP |
1624 | return -EIO; |
1625 | ||
1f5e055d | 1626 | /* P3 onward, test agent base for MIU and SIU is same */ |
ea6828b8 DP |
1627 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1628 | NETXEN_ADDR_QDR_NET_MAX_P3)) { | |
1f5e055d AKS |
1629 | mem_crb = netxen_get_ioaddr(adapter, |
1630 | NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 DP |
1631 | goto correct; |
1632 | } | |
1633 | ||
1634 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | |
1f5e055d AKS |
1635 | mem_crb = netxen_get_ioaddr(adapter, |
1636 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 | 1637 | goto correct; |
3ce06a32 DP |
1638 | } |
1639 | ||
47abe356 DP |
1640 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) |
1641 | return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1); | |
1642 | ||
ea6828b8 DP |
1643 | return -EIO; |
1644 | ||
1645 | correct: | |
215387a4 | 1646 | off8 = off & 0xfffffff8; |
3ce06a32 | 1647 | |
f03b0ebd | 1648 | spin_lock(&adapter->ahw.mem_lock); |
3ce06a32 | 1649 | |
1f5e055d AKS |
1650 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1651 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | |
fb1f6a43 | 1652 | |
fb1f6a43 | 1653 | writel(data & 0xffffffff, |
215387a4 | 1654 | mem_crb + MIU_TEST_AGT_WRDATA_LO); |
fb1f6a43 | 1655 | writel((data >> 32) & 0xffffffff, |
215387a4 | 1656 | mem_crb + MIU_TEST_AGT_WRDATA_HI); |
fb1f6a43 | 1657 | |
1f5e055d AKS |
1658 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); |
1659 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | |
1660 | (mem_crb + TEST_AGT_CTRL)); | |
1661 | ||
1662 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1663 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1664 | if ((temp & TA_CTL_BUSY) == 0) | |
1665 | break; | |
3ce06a32 DP |
1666 | } |
1667 | ||
1f5e055d AKS |
1668 | if (j >= MAX_CTL_CHECK) { |
1669 | if (printk_ratelimit()) | |
1670 | dev_err(&adapter->pdev->dev, | |
39754f44 | 1671 | "failed to write through agent\n"); |
1f5e055d AKS |
1672 | ret = -EIO; |
1673 | } else | |
1674 | ret = 0; | |
1675 | ||
f03b0ebd | 1676 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 | 1677 | |
3ce06a32 DP |
1678 | return ret; |
1679 | } | |
1680 | ||
195c5f98 | 1681 | static int |
3ce06a32 | 1682 | netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
1f5e055d | 1683 | u64 off, u64 *data) |
3ce06a32 | 1684 | { |
1f5e055d AKS |
1685 | int j, ret; |
1686 | u32 temp, off8; | |
215387a4 | 1687 | u64 val; |
ea6828b8 | 1688 | void __iomem *mem_crb; |
3ce06a32 | 1689 | |
1f5e055d AKS |
1690 | /* Only 64-bit aligned access */ |
1691 | if (off & 7) | |
ea6828b8 | 1692 | return -EIO; |
3ce06a32 | 1693 | |
1f5e055d | 1694 | /* P3 onward, test agent base for MIU and SIU is same */ |
ea6828b8 DP |
1695 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1696 | NETXEN_ADDR_QDR_NET_MAX_P3)) { | |
1f5e055d AKS |
1697 | mem_crb = netxen_get_ioaddr(adapter, |
1698 | NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 | 1699 | goto correct; |
3ce06a32 DP |
1700 | } |
1701 | ||
ea6828b8 | 1702 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1703 | mem_crb = netxen_get_ioaddr(adapter, |
1704 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 DP |
1705 | goto correct; |
1706 | } | |
1707 | ||
907fa120 DP |
1708 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
1709 | return netxen_nic_pci_mem_access_direct(adapter, | |
1710 | off, data, 0); | |
1711 | } | |
47abe356 | 1712 | |
ea6828b8 DP |
1713 | return -EIO; |
1714 | ||
1715 | correct: | |
215387a4 | 1716 | off8 = off & 0xfffffff8; |
3ce06a32 | 1717 | |
f03b0ebd | 1718 | spin_lock(&adapter->ahw.mem_lock); |
3ce06a32 | 1719 | |
1f5e055d AKS |
1720 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1721 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | |
1722 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | |
1723 | writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); | |
3ce06a32 | 1724 | |
1f5e055d AKS |
1725 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
1726 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1727 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1728 | break; |
3ce06a32 DP |
1729 | } |
1730 | ||
1f5e055d AKS |
1731 | if (j >= MAX_CTL_CHECK) { |
1732 | if (printk_ratelimit()) | |
1733 | dev_err(&adapter->pdev->dev, | |
1734 | "failed to read through agent\n"); | |
1735 | ret = -EIO; | |
3ce06a32 | 1736 | } else { |
215387a4 SC |
1737 | val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32; |
1738 | val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO); | |
1f5e055d AKS |
1739 | *data = val; |
1740 | ret = 0; | |
3ce06a32 DP |
1741 | } |
1742 | ||
f03b0ebd | 1743 | spin_unlock(&adapter->ahw.mem_lock); |
1f5e055d AKS |
1744 | |
1745 | return ret; | |
3ce06a32 DP |
1746 | } |
1747 | ||
195c5f98 AKS |
1748 | void |
1749 | netxen_setup_hwops(struct netxen_adapter *adapter) | |
3ce06a32 | 1750 | { |
195c5f98 AKS |
1751 | adapter->init_port = netxen_niu_xg_init_port; |
1752 | adapter->stop_port = netxen_niu_disable_xg_port; | |
3ce06a32 | 1753 | |
195c5f98 AKS |
1754 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
1755 | adapter->crb_read = netxen_nic_hw_read_wx_128M, | |
1756 | adapter->crb_write = netxen_nic_hw_write_wx_128M, | |
1757 | adapter->pci_set_window = netxen_nic_pci_set_window_128M, | |
1758 | adapter->pci_mem_read = netxen_nic_pci_mem_read_128M, | |
1759 | adapter->pci_mem_write = netxen_nic_pci_mem_write_128M, | |
1760 | adapter->io_read = netxen_nic_io_read_128M, | |
1761 | adapter->io_write = netxen_nic_io_write_128M, | |
1762 | ||
1763 | adapter->macaddr_set = netxen_p2_nic_set_mac_addr; | |
1764 | adapter->set_multi = netxen_p2_nic_set_multi; | |
1765 | adapter->set_mtu = netxen_nic_set_mtu_xgb; | |
1766 | adapter->set_promisc = netxen_p2_nic_set_promisc; | |
3ce06a32 | 1767 | |
195c5f98 AKS |
1768 | } else { |
1769 | adapter->crb_read = netxen_nic_hw_read_wx_2M, | |
1770 | adapter->crb_write = netxen_nic_hw_write_wx_2M, | |
1771 | adapter->pci_set_window = netxen_nic_pci_set_window_2M, | |
1772 | adapter->pci_mem_read = netxen_nic_pci_mem_read_2M, | |
1773 | adapter->pci_mem_write = netxen_nic_pci_mem_write_2M, | |
1774 | adapter->io_read = netxen_nic_io_read_2M, | |
1775 | adapter->io_write = netxen_nic_io_write_2M, | |
1776 | ||
1777 | adapter->set_mtu = nx_fw_cmd_set_mtu; | |
1778 | adapter->set_promisc = netxen_p3_nic_set_promisc; | |
1779 | adapter->macaddr_set = netxen_p3_nic_set_mac_addr; | |
1780 | adapter->set_multi = netxen_p3_nic_set_multi; | |
1781 | ||
1782 | adapter->phy_read = nx_fw_cmd_query_phy; | |
1783 | adapter->phy_write = nx_fw_cmd_set_phy; | |
1784 | } | |
3ce06a32 DP |
1785 | } |
1786 | ||
3d396eb1 AK |
1787 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
1788 | { | |
0dc6d9cb | 1789 | int offset, board_type, magic; |
1e2d0059 | 1790 | struct pci_dev *pdev = adapter->pdev; |
3d396eb1 | 1791 | |
06db58c0 | 1792 | offset = NX_FW_MAGIC_OFFSET; |
1e2d0059 DP |
1793 | if (netxen_rom_fast_read(adapter, offset, &magic)) |
1794 | return -EIO; | |
3d396eb1 | 1795 | |
0dc6d9cb DP |
1796 | if (magic != NETXEN_BDINFO_MAGIC) { |
1797 | dev_err(&pdev->dev, "invalid board config, magic=%08x\n", | |
1798 | magic); | |
1e2d0059 | 1799 | return -EIO; |
3d396eb1 AK |
1800 | } |
1801 | ||
06db58c0 | 1802 | offset = NX_BRDTYPE_OFFSET; |
1e2d0059 DP |
1803 | if (netxen_rom_fast_read(adapter, offset, &board_type)) |
1804 | return -EIO; | |
1805 | ||
1e2d0059 | 1806 | if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { |
f98a9f69 | 1807 | u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I); |
c7860a2a | 1808 | if ((gpio & 0x8000) == 0) |
1e2d0059 | 1809 | board_type = NETXEN_BRDTYPE_P3_10G_TP; |
c7860a2a DP |
1810 | } |
1811 | ||
dce87b96 | 1812 | adapter->ahw.board_type = board_type; |
1813 | ||
e98e3350 | 1814 | switch (board_type) { |
3d396eb1 | 1815 | case NETXEN_BRDTYPE_P2_SB35_4G: |
1e2d0059 | 1816 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
3d396eb1 AK |
1817 | break; |
1818 | case NETXEN_BRDTYPE_P2_SB31_10G: | |
1819 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: | |
1820 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: | |
1821 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: | |
e4c93c81 DP |
1822 | case NETXEN_BRDTYPE_P3_HMEZ: |
1823 | case NETXEN_BRDTYPE_P3_XG_LOM: | |
1824 | case NETXEN_BRDTYPE_P3_10G_CX4: | |
1825 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: | |
1826 | case NETXEN_BRDTYPE_P3_IMEZ: | |
1827 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: | |
a70f9393 DP |
1828 | case NETXEN_BRDTYPE_P3_10G_SFP_CT: |
1829 | case NETXEN_BRDTYPE_P3_10G_SFP_QT: | |
e4c93c81 DP |
1830 | case NETXEN_BRDTYPE_P3_10G_XFP: |
1831 | case NETXEN_BRDTYPE_P3_10000_BASE_T: | |
1e2d0059 | 1832 | adapter->ahw.port_type = NETXEN_NIC_XGBE; |
3d396eb1 AK |
1833 | break; |
1834 | case NETXEN_BRDTYPE_P1_BD: | |
1835 | case NETXEN_BRDTYPE_P1_SB: | |
1836 | case NETXEN_BRDTYPE_P1_SMAX: | |
1837 | case NETXEN_BRDTYPE_P1_SOCK: | |
e4c93c81 DP |
1838 | case NETXEN_BRDTYPE_P3_REF_QG: |
1839 | case NETXEN_BRDTYPE_P3_4_GB: | |
1840 | case NETXEN_BRDTYPE_P3_4_GB_MM: | |
1e2d0059 | 1841 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
3d396eb1 | 1842 | break; |
c7860a2a | 1843 | case NETXEN_BRDTYPE_P3_10G_TP: |
1e2d0059 | 1844 | adapter->ahw.port_type = (adapter->portnum < 2) ? |
c7860a2a DP |
1845 | NETXEN_NIC_XGBE : NETXEN_NIC_GBE; |
1846 | break; | |
3d396eb1 | 1847 | default: |
1e2d0059 DP |
1848 | dev_err(&pdev->dev, "unknown board type %x\n", board_type); |
1849 | adapter->ahw.port_type = NETXEN_NIC_XGBE; | |
3d396eb1 AK |
1850 | break; |
1851 | } | |
1852 | ||
1e2d0059 | 1853 | return 0; |
3d396eb1 AK |
1854 | } |
1855 | ||
1856 | /* NIU access sections */ | |
7e12bb0a | 1857 | static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1858 | { |
9ad27643 | 1859 | new_mtu += MTU_FUDGE_FACTOR; |
3276fbad | 1860 | if (adapter->physical_port == 0) |
f98a9f69 | 1861 | NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); |
4790654c | 1862 | else |
f98a9f69 | 1863 | NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); |
3d396eb1 AK |
1864 | return 0; |
1865 | } | |
1866 | ||
3176ff3e | 1867 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
3d396eb1 | 1868 | { |
a608ab9c AV |
1869 | __u32 status; |
1870 | __u32 autoneg; | |
24a7a455 | 1871 | __u32 port_mode; |
3d396eb1 | 1872 | |
c7860a2a DP |
1873 | if (!netif_carrier_ok(adapter->netdev)) { |
1874 | adapter->link_speed = 0; | |
1875 | adapter->link_duplex = -1; | |
1876 | adapter->link_autoneg = AUTONEG_ENABLE; | |
1877 | return; | |
1878 | } | |
24a7a455 | 1879 | |
1e2d0059 | 1880 | if (adapter->ahw.port_type == NETXEN_NIC_GBE) { |
f98a9f69 | 1881 | port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); |
24a7a455 DP |
1882 | if (port_mode == NETXEN_PORT_MODE_802_3_AP) { |
1883 | adapter->link_speed = SPEED_1000; | |
1884 | adapter->link_duplex = DUPLEX_FULL; | |
1885 | adapter->link_autoneg = AUTONEG_DISABLE; | |
1886 | return; | |
1887 | } | |
1888 | ||
8e95a202 JP |
1889 | if (adapter->phy_read && |
1890 | adapter->phy_read(adapter, | |
1891 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, | |
1892 | &status) == 0) { | |
3d396eb1 AK |
1893 | if (netxen_get_phy_link(status)) { |
1894 | switch (netxen_get_phy_speed(status)) { | |
1895 | case 0: | |
3176ff3e | 1896 | adapter->link_speed = SPEED_10; |
3d396eb1 AK |
1897 | break; |
1898 | case 1: | |
3176ff3e | 1899 | adapter->link_speed = SPEED_100; |
3d396eb1 AK |
1900 | break; |
1901 | case 2: | |
3176ff3e | 1902 | adapter->link_speed = SPEED_1000; |
3d396eb1 AK |
1903 | break; |
1904 | default: | |
c7860a2a | 1905 | adapter->link_speed = 0; |
3d396eb1 AK |
1906 | break; |
1907 | } | |
1908 | switch (netxen_get_phy_duplex(status)) { | |
1909 | case 0: | |
3176ff3e | 1910 | adapter->link_duplex = DUPLEX_HALF; |
3d396eb1 AK |
1911 | break; |
1912 | case 1: | |
3176ff3e | 1913 | adapter->link_duplex = DUPLEX_FULL; |
3d396eb1 AK |
1914 | break; |
1915 | default: | |
3176ff3e | 1916 | adapter->link_duplex = -1; |
3d396eb1 AK |
1917 | break; |
1918 | } | |
8e95a202 JP |
1919 | if (adapter->phy_read && |
1920 | adapter->phy_read(adapter, | |
1921 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, | |
1c755ffa | 1922 | &autoneg) == 0) |
3176ff3e | 1923 | adapter->link_autoneg = autoneg; |
3d396eb1 AK |
1924 | } else |
1925 | goto link_down; | |
1926 | } else { | |
1927 | link_down: | |
c7860a2a | 1928 | adapter->link_speed = 0; |
3176ff3e | 1929 | adapter->link_duplex = -1; |
3d396eb1 AK |
1930 | } |
1931 | } | |
1932 | } | |
1933 | ||
0b72e659 DP |
1934 | int |
1935 | netxen_nic_wol_supported(struct netxen_adapter *adapter) | |
1936 | { | |
1937 | u32 wol_cfg; | |
1938 | ||
1939 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1940 | return 0; | |
1941 | ||
f98a9f69 | 1942 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); |
0b72e659 | 1943 | if (wol_cfg & (1UL << adapter->portnum)) { |
f98a9f69 | 1944 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); |
0b72e659 DP |
1945 | if (wol_cfg & (1 << adapter->portnum)) |
1946 | return 1; | |
1947 | } | |
1948 | ||
1949 | return 0; | |
1950 | } | |
83f18a55 M |
1951 | |
1952 | static u32 netxen_md_cntrl(struct netxen_adapter *adapter, | |
1953 | struct netxen_minidump_template_hdr *template_hdr, | |
1954 | struct netxen_minidump_entry_crb *crtEntry) | |
1955 | { | |
1956 | int loop_cnt, i, rv = 0, timeout_flag; | |
1957 | u32 op_count, stride; | |
1958 | u32 opcode, read_value, addr; | |
1959 | unsigned long timeout, timeout_jiffies; | |
1960 | addr = crtEntry->addr; | |
1961 | op_count = crtEntry->op_count; | |
1962 | stride = crtEntry->addr_stride; | |
1963 | ||
1964 | for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { | |
1965 | for (i = 0; i < sizeof(crtEntry->opcode) * 8; i++) { | |
1966 | opcode = (crtEntry->opcode & (0x1 << i)); | |
1967 | if (opcode) { | |
1968 | switch (opcode) { | |
1969 | case NX_DUMP_WCRB: | |
1970 | NX_WR_DUMP_REG(addr, | |
1971 | adapter->ahw.pci_base0, | |
1972 | crtEntry->value_1); | |
1973 | break; | |
1974 | case NX_DUMP_RWCRB: | |
1975 | NX_RD_DUMP_REG(addr, | |
1976 | adapter->ahw.pci_base0, | |
1977 | &read_value); | |
1978 | NX_WR_DUMP_REG(addr, | |
1979 | adapter->ahw.pci_base0, | |
1980 | read_value); | |
1981 | break; | |
1982 | case NX_DUMP_ANDCRB: | |
1983 | NX_RD_DUMP_REG(addr, | |
1984 | adapter->ahw.pci_base0, | |
1985 | &read_value); | |
1986 | read_value &= crtEntry->value_2; | |
1987 | NX_WR_DUMP_REG(addr, | |
1988 | adapter->ahw.pci_base0, | |
1989 | read_value); | |
1990 | break; | |
1991 | case NX_DUMP_ORCRB: | |
1992 | NX_RD_DUMP_REG(addr, | |
1993 | adapter->ahw.pci_base0, | |
1994 | &read_value); | |
1995 | read_value |= crtEntry->value_3; | |
1996 | NX_WR_DUMP_REG(addr, | |
1997 | adapter->ahw.pci_base0, | |
1998 | read_value); | |
1999 | break; | |
2000 | case NX_DUMP_POLLCRB: | |
2001 | timeout = crtEntry->poll_timeout; | |
2002 | NX_RD_DUMP_REG(addr, | |
2003 | adapter->ahw.pci_base0, | |
2004 | &read_value); | |
2005 | timeout_jiffies = | |
2006 | msecs_to_jiffies(timeout) + jiffies; | |
2007 | for (timeout_flag = 0; | |
2008 | !timeout_flag | |
2009 | && ((read_value & crtEntry->value_2) | |
2010 | != crtEntry->value_1);) { | |
2011 | if (time_after(jiffies, | |
2012 | timeout_jiffies)) | |
2013 | timeout_flag = 1; | |
2014 | NX_RD_DUMP_REG(addr, | |
2015 | adapter->ahw.pci_base0, | |
2016 | &read_value); | |
2017 | } | |
2018 | ||
2019 | if (timeout_flag) { | |
2020 | dev_err(&adapter->pdev->dev, "%s : " | |
2021 | "Timeout in poll_crb control operation.\n" | |
2022 | , __func__); | |
2023 | return -1; | |
2024 | } | |
2025 | break; | |
2026 | case NX_DUMP_RD_SAVE: | |
2027 | /* Decide which address to use */ | |
2028 | if (crtEntry->state_index_a) | |
2029 | addr = | |
2030 | template_hdr->saved_state_array | |
2031 | [crtEntry->state_index_a]; | |
2032 | NX_RD_DUMP_REG(addr, | |
2033 | adapter->ahw.pci_base0, | |
2034 | &read_value); | |
2035 | template_hdr->saved_state_array | |
2036 | [crtEntry->state_index_v] | |
2037 | = read_value; | |
2038 | break; | |
2039 | case NX_DUMP_WRT_SAVED: | |
2040 | /* Decide which value to use */ | |
2041 | if (crtEntry->state_index_v) | |
2042 | read_value = | |
2043 | template_hdr->saved_state_array | |
2044 | [crtEntry->state_index_v]; | |
2045 | else | |
2046 | read_value = crtEntry->value_1; | |
2047 | ||
2048 | /* Decide which address to use */ | |
2049 | if (crtEntry->state_index_a) | |
2050 | addr = | |
2051 | template_hdr->saved_state_array | |
2052 | [crtEntry->state_index_a]; | |
2053 | ||
2054 | NX_WR_DUMP_REG(addr, | |
2055 | adapter->ahw.pci_base0, | |
2056 | read_value); | |
2057 | break; | |
2058 | case NX_DUMP_MOD_SAVE_ST: | |
2059 | read_value = | |
2060 | template_hdr->saved_state_array | |
2061 | [crtEntry->state_index_v]; | |
2062 | read_value <<= crtEntry->shl; | |
2063 | read_value >>= crtEntry->shr; | |
2064 | if (crtEntry->value_2) | |
2065 | read_value &= | |
2066 | crtEntry->value_2; | |
2067 | read_value |= crtEntry->value_3; | |
2068 | read_value += crtEntry->value_1; | |
2069 | /* Write value back to state area.*/ | |
2070 | template_hdr->saved_state_array | |
2071 | [crtEntry->state_index_v] | |
2072 | = read_value; | |
2073 | break; | |
2074 | default: | |
2075 | rv = 1; | |
2076 | break; | |
2077 | } | |
2078 | } | |
2079 | } | |
2080 | addr = addr + stride; | |
2081 | } | |
2082 | return rv; | |
2083 | } | |
2084 | ||
2085 | /* Read memory or MN */ | |
2086 | static u32 | |
2087 | netxen_md_rdmem(struct netxen_adapter *adapter, | |
2088 | struct netxen_minidump_entry_rdmem | |
2089 | *memEntry, u64 *data_buff) | |
2090 | { | |
2091 | u64 addr, value = 0; | |
2092 | int i = 0, loop_cnt; | |
2093 | ||
2094 | addr = (u64)memEntry->read_addr; | |
2095 | loop_cnt = memEntry->read_data_size; /* This is size in bytes */ | |
2096 | loop_cnt /= sizeof(value); | |
2097 | ||
2098 | for (i = 0; i < loop_cnt; i++) { | |
2099 | if (netxen_nic_pci_mem_read_2M(adapter, addr, &value)) | |
2100 | goto out; | |
2101 | *data_buff++ = value; | |
2102 | addr += sizeof(value); | |
2103 | } | |
2104 | out: | |
2105 | return i * sizeof(value); | |
2106 | } | |
2107 | ||
2108 | /* Read CRB operation */ | |
2109 | static u32 netxen_md_rd_crb(struct netxen_adapter *adapter, | |
2110 | struct netxen_minidump_entry_crb | |
2111 | *crbEntry, u32 *data_buff) | |
2112 | { | |
2113 | int loop_cnt; | |
2114 | u32 op_count, addr, stride, value; | |
2115 | ||
2116 | addr = crbEntry->addr; | |
2117 | op_count = crbEntry->op_count; | |
2118 | stride = crbEntry->addr_stride; | |
2119 | ||
2120 | for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { | |
2121 | NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, &value); | |
2122 | *data_buff++ = addr; | |
2123 | *data_buff++ = value; | |
2124 | addr = addr + stride; | |
2125 | } | |
2126 | return loop_cnt * (2 * sizeof(u32)); | |
2127 | } | |
2128 | ||
2129 | /* Read ROM */ | |
2130 | static u32 | |
2131 | netxen_md_rdrom(struct netxen_adapter *adapter, | |
2132 | struct netxen_minidump_entry_rdrom | |
06d6c108 | 2133 | *romEntry, __le32 *data_buff) |
83f18a55 M |
2134 | { |
2135 | int i, count = 0; | |
2136 | u32 size, lck_val; | |
2137 | u32 val; | |
2138 | u32 fl_addr, waddr, raddr; | |
2139 | fl_addr = romEntry->read_addr; | |
2140 | size = romEntry->read_data_size/4; | |
2141 | lock_try: | |
2142 | lck_val = readl((void __iomem *)(adapter->ahw.pci_base0 + | |
2143 | NX_FLASH_SEM2_LK)); | |
2144 | if (!lck_val && count < MAX_CTL_CHECK) { | |
2145 | msleep(20); | |
2146 | count++; | |
2147 | goto lock_try; | |
2148 | } | |
2149 | writel(adapter->ahw.pci_func, (void __iomem *)(adapter->ahw.pci_base0 + | |
2150 | NX_FLASH_LOCK_ID)); | |
2151 | for (i = 0; i < size; i++) { | |
2152 | waddr = fl_addr & 0xFFFF0000; | |
2153 | NX_WR_DUMP_REG(FLASH_ROM_WINDOW, adapter->ahw.pci_base0, waddr); | |
2154 | raddr = FLASH_ROM_DATA + (fl_addr & 0x0000FFFF); | |
2155 | NX_RD_DUMP_REG(raddr, adapter->ahw.pci_base0, &val); | |
2156 | *data_buff++ = cpu_to_le32(val); | |
2157 | fl_addr += sizeof(val); | |
2158 | } | |
2159 | readl((void __iomem *)(adapter->ahw.pci_base0 + NX_FLASH_SEM2_ULK)); | |
2160 | return romEntry->read_data_size; | |
2161 | } | |
2162 | ||
2163 | /* Handle L2 Cache */ | |
2164 | static u32 | |
2165 | netxen_md_L2Cache(struct netxen_adapter *adapter, | |
2166 | struct netxen_minidump_entry_cache | |
2167 | *cacheEntry, u32 *data_buff) | |
2168 | { | |
2169 | int loop_cnt, i, k, timeout_flag = 0; | |
2170 | u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr; | |
2171 | u32 tag_value, read_cnt; | |
2172 | u8 cntl_value_w, cntl_value_r; | |
2173 | unsigned long timeout, timeout_jiffies; | |
2174 | ||
2175 | loop_cnt = cacheEntry->op_count; | |
2176 | read_addr = cacheEntry->read_addr; | |
2177 | cntrl_addr = cacheEntry->control_addr; | |
2178 | cntl_value_w = (u32) cacheEntry->write_value; | |
2179 | tag_reg_addr = cacheEntry->tag_reg_addr; | |
2180 | tag_value = cacheEntry->init_tag_value; | |
2181 | read_cnt = cacheEntry->read_addr_cnt; | |
2182 | ||
2183 | for (i = 0; i < loop_cnt; i++) { | |
2184 | NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value); | |
2185 | if (cntl_value_w) | |
2186 | NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0, | |
2187 | (u32)cntl_value_w); | |
2188 | if (cacheEntry->poll_mask) { | |
2189 | timeout = cacheEntry->poll_wait; | |
2190 | NX_RD_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0, | |
2191 | &cntl_value_r); | |
2192 | timeout_jiffies = msecs_to_jiffies(timeout) + jiffies; | |
2193 | for (timeout_flag = 0; !timeout_flag && | |
2194 | ((cntl_value_r & cacheEntry->poll_mask) != 0);) { | |
2195 | if (time_after(jiffies, timeout_jiffies)) | |
2196 | timeout_flag = 1; | |
2197 | NX_RD_DUMP_REG(cntrl_addr, | |
2198 | adapter->ahw.pci_base0, | |
2199 | &cntl_value_r); | |
2200 | } | |
2201 | if (timeout_flag) { | |
2202 | dev_err(&adapter->pdev->dev, | |
2203 | "Timeout in processing L2 Tag poll.\n"); | |
2204 | return -1; | |
2205 | } | |
2206 | } | |
2207 | addr = read_addr; | |
2208 | for (k = 0; k < read_cnt; k++) { | |
2209 | NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, | |
2210 | &read_value); | |
2211 | *data_buff++ = read_value; | |
2212 | addr += cacheEntry->read_addr_stride; | |
2213 | } | |
2214 | tag_value += cacheEntry->tag_value_stride; | |
2215 | } | |
2216 | return read_cnt * loop_cnt * sizeof(read_value); | |
2217 | } | |
2218 | ||
2219 | ||
2220 | /* Handle L1 Cache */ | |
2221 | static u32 netxen_md_L1Cache(struct netxen_adapter *adapter, | |
2222 | struct netxen_minidump_entry_cache | |
2223 | *cacheEntry, u32 *data_buff) | |
2224 | { | |
2225 | int i, k, loop_cnt; | |
2226 | u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr; | |
2227 | u32 tag_value, read_cnt; | |
2228 | u8 cntl_value_w; | |
2229 | ||
2230 | loop_cnt = cacheEntry->op_count; | |
2231 | read_addr = cacheEntry->read_addr; | |
2232 | cntrl_addr = cacheEntry->control_addr; | |
2233 | cntl_value_w = (u32) cacheEntry->write_value; | |
2234 | tag_reg_addr = cacheEntry->tag_reg_addr; | |
2235 | tag_value = cacheEntry->init_tag_value; | |
2236 | read_cnt = cacheEntry->read_addr_cnt; | |
2237 | ||
2238 | for (i = 0; i < loop_cnt; i++) { | |
2239 | NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value); | |
2240 | NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0, | |
2241 | (u32) cntl_value_w); | |
2242 | addr = read_addr; | |
2243 | for (k = 0; k < read_cnt; k++) { | |
2244 | NX_RD_DUMP_REG(addr, | |
2245 | adapter->ahw.pci_base0, | |
2246 | &read_value); | |
2247 | *data_buff++ = read_value; | |
2248 | addr += cacheEntry->read_addr_stride; | |
2249 | } | |
2250 | tag_value += cacheEntry->tag_value_stride; | |
2251 | } | |
2252 | return read_cnt * loop_cnt * sizeof(read_value); | |
2253 | } | |
2254 | ||
2255 | /* Reading OCM memory */ | |
2256 | static u32 | |
2257 | netxen_md_rdocm(struct netxen_adapter *adapter, | |
2258 | struct netxen_minidump_entry_rdocm | |
2259 | *ocmEntry, u32 *data_buff) | |
2260 | { | |
2261 | int i, loop_cnt; | |
2262 | u32 value; | |
2263 | void __iomem *addr; | |
2264 | addr = (ocmEntry->read_addr + adapter->ahw.pci_base0); | |
2265 | loop_cnt = ocmEntry->op_count; | |
2266 | ||
2267 | for (i = 0; i < loop_cnt; i++) { | |
2268 | value = readl(addr); | |
2269 | *data_buff++ = value; | |
2270 | addr += ocmEntry->read_addr_stride; | |
2271 | } | |
2272 | return i * sizeof(u32); | |
2273 | } | |
2274 | ||
2275 | /* Read MUX data */ | |
2276 | static u32 | |
2277 | netxen_md_rdmux(struct netxen_adapter *adapter, struct netxen_minidump_entry_mux | |
2278 | *muxEntry, u32 *data_buff) | |
2279 | { | |
2280 | int loop_cnt = 0; | |
2281 | u32 read_addr, read_value, select_addr, sel_value; | |
2282 | ||
2283 | read_addr = muxEntry->read_addr; | |
2284 | sel_value = muxEntry->select_value; | |
2285 | select_addr = muxEntry->select_addr; | |
2286 | ||
2287 | for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) { | |
2288 | NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, sel_value); | |
2289 | NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0, &read_value); | |
2290 | *data_buff++ = sel_value; | |
2291 | *data_buff++ = read_value; | |
2292 | sel_value += muxEntry->select_value_stride; | |
2293 | } | |
2294 | return loop_cnt * (2 * sizeof(u32)); | |
2295 | } | |
2296 | ||
2297 | /* Handling Queue State Reads */ | |
2298 | static u32 | |
2299 | netxen_md_rdqueue(struct netxen_adapter *adapter, | |
2300 | struct netxen_minidump_entry_queue | |
2301 | *queueEntry, u32 *data_buff) | |
2302 | { | |
2303 | int loop_cnt, k; | |
2304 | u32 queue_id, read_addr, read_value, read_stride, select_addr, read_cnt; | |
2305 | ||
2306 | read_cnt = queueEntry->read_addr_cnt; | |
2307 | read_stride = queueEntry->read_addr_stride; | |
2308 | select_addr = queueEntry->select_addr; | |
2309 | ||
2310 | for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count; | |
2311 | loop_cnt++) { | |
2312 | NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, queue_id); | |
2313 | read_addr = queueEntry->read_addr; | |
a120d9ab | 2314 | for (k = 0; k < read_cnt; k++) { |
83f18a55 M |
2315 | NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0, |
2316 | &read_value); | |
2317 | *data_buff++ = read_value; | |
2318 | read_addr += read_stride; | |
2319 | } | |
2320 | queue_id += queueEntry->queue_id_stride; | |
2321 | } | |
2322 | return loop_cnt * (read_cnt * sizeof(read_value)); | |
2323 | } | |
2324 | ||
2325 | ||
2326 | /* | |
2327 | * We catch an error where driver does not read | |
2328 | * as much data as we expect from the entry. | |
2329 | */ | |
2330 | ||
2331 | static int netxen_md_entry_err_chk(struct netxen_adapter *adapter, | |
a584b7ae | 2332 | struct netxen_minidump_entry *entry, int esize) |
83f18a55 M |
2333 | { |
2334 | if (esize < 0) { | |
2335 | entry->hdr.driver_flags |= NX_DUMP_SKIP; | |
2336 | return esize; | |
2337 | } | |
2338 | if (esize != entry->hdr.entry_capture_size) { | |
2339 | entry->hdr.entry_capture_size = esize; | |
2340 | entry->hdr.driver_flags |= NX_DUMP_SIZE_ERR; | |
2341 | dev_info(&adapter->pdev->dev, | |
2342 | "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n", | |
2343 | entry->hdr.entry_type, entry->hdr.entry_capture_mask, | |
2344 | esize, entry->hdr.entry_capture_size); | |
2345 | dev_info(&adapter->pdev->dev, "Aborting further dump capture\n"); | |
2346 | } | |
2347 | return 0; | |
2348 | } | |
2349 | ||
2350 | static int netxen_parse_md_template(struct netxen_adapter *adapter) | |
2351 | { | |
2352 | int num_of_entries, buff_level, e_cnt, esize; | |
2353 | int end_cnt = 0, rv = 0, sane_start = 0, sane_end = 0; | |
2354 | char *dbuff; | |
2355 | void *template_buff = adapter->mdump.md_template; | |
2356 | char *dump_buff = adapter->mdump.md_capture_buff; | |
2357 | int capture_mask = adapter->mdump.md_capture_mask; | |
2358 | struct netxen_minidump_template_hdr *template_hdr; | |
2359 | struct netxen_minidump_entry *entry; | |
2360 | ||
2361 | if ((capture_mask & 0x3) != 0x3) { | |
2362 | dev_err(&adapter->pdev->dev, "Capture mask %02x below minimum needed " | |
2363 | "for valid firmware dump\n", capture_mask); | |
2364 | return -EINVAL; | |
2365 | } | |
2366 | template_hdr = (struct netxen_minidump_template_hdr *) template_buff; | |
2367 | num_of_entries = template_hdr->num_of_entries; | |
2368 | entry = (struct netxen_minidump_entry *) ((char *) template_buff + | |
2369 | template_hdr->first_entry_offset); | |
2370 | memcpy(dump_buff, template_buff, adapter->mdump.md_template_size); | |
2371 | dump_buff = dump_buff + adapter->mdump.md_template_size; | |
2372 | ||
2373 | if (template_hdr->entry_type == TLHDR) | |
2374 | sane_start = 1; | |
2375 | ||
2376 | for (e_cnt = 0, buff_level = 0; e_cnt < num_of_entries; e_cnt++) { | |
2377 | if (!(entry->hdr.entry_capture_mask & capture_mask)) { | |
2378 | entry->hdr.driver_flags |= NX_DUMP_SKIP; | |
2379 | entry = (struct netxen_minidump_entry *) | |
2380 | ((char *) entry + entry->hdr.entry_size); | |
2381 | continue; | |
2382 | } | |
2383 | switch (entry->hdr.entry_type) { | |
2384 | case RDNOP: | |
2385 | entry->hdr.driver_flags |= NX_DUMP_SKIP; | |
2386 | break; | |
2387 | case RDEND: | |
2388 | entry->hdr.driver_flags |= NX_DUMP_SKIP; | |
2389 | if (!sane_end) | |
2390 | end_cnt = e_cnt; | |
2391 | sane_end += 1; | |
2392 | break; | |
2393 | case CNTRL: | |
2394 | rv = netxen_md_cntrl(adapter, | |
2395 | template_hdr, (void *)entry); | |
2396 | if (rv) | |
2397 | entry->hdr.driver_flags |= NX_DUMP_SKIP; | |
2398 | break; | |
2399 | case RDCRB: | |
2400 | dbuff = dump_buff + buff_level; | |
2401 | esize = netxen_md_rd_crb(adapter, | |
2402 | (void *) entry, (void *) dbuff); | |
2403 | rv = netxen_md_entry_err_chk | |
2404 | (adapter, entry, esize); | |
2405 | if (rv < 0) | |
2406 | break; | |
2407 | buff_level += esize; | |
2408 | break; | |
2409 | case RDMN: | |
2410 | case RDMEM: | |
2411 | dbuff = dump_buff + buff_level; | |
2412 | esize = netxen_md_rdmem(adapter, | |
2413 | (void *) entry, (void *) dbuff); | |
2414 | rv = netxen_md_entry_err_chk | |
2415 | (adapter, entry, esize); | |
2416 | if (rv < 0) | |
2417 | break; | |
2418 | buff_level += esize; | |
2419 | break; | |
2420 | case BOARD: | |
2421 | case RDROM: | |
2422 | dbuff = dump_buff + buff_level; | |
2423 | esize = netxen_md_rdrom(adapter, | |
2424 | (void *) entry, (void *) dbuff); | |
2425 | rv = netxen_md_entry_err_chk | |
2426 | (adapter, entry, esize); | |
2427 | if (rv < 0) | |
2428 | break; | |
2429 | buff_level += esize; | |
2430 | break; | |
2431 | case L2ITG: | |
2432 | case L2DTG: | |
2433 | case L2DAT: | |
2434 | case L2INS: | |
2435 | dbuff = dump_buff + buff_level; | |
2436 | esize = netxen_md_L2Cache(adapter, | |
2437 | (void *) entry, (void *) dbuff); | |
2438 | rv = netxen_md_entry_err_chk | |
2439 | (adapter, entry, esize); | |
2440 | if (rv < 0) | |
2441 | break; | |
2442 | buff_level += esize; | |
2443 | break; | |
2444 | case L1DAT: | |
2445 | case L1INS: | |
2446 | dbuff = dump_buff + buff_level; | |
2447 | esize = netxen_md_L1Cache(adapter, | |
2448 | (void *) entry, (void *) dbuff); | |
2449 | rv = netxen_md_entry_err_chk | |
2450 | (adapter, entry, esize); | |
2451 | if (rv < 0) | |
2452 | break; | |
2453 | buff_level += esize; | |
2454 | break; | |
2455 | case RDOCM: | |
2456 | dbuff = dump_buff + buff_level; | |
2457 | esize = netxen_md_rdocm(adapter, | |
2458 | (void *) entry, (void *) dbuff); | |
2459 | rv = netxen_md_entry_err_chk | |
2460 | (adapter, entry, esize); | |
2461 | if (rv < 0) | |
2462 | break; | |
2463 | buff_level += esize; | |
2464 | break; | |
2465 | case RDMUX: | |
2466 | dbuff = dump_buff + buff_level; | |
2467 | esize = netxen_md_rdmux(adapter, | |
2468 | (void *) entry, (void *) dbuff); | |
2469 | rv = netxen_md_entry_err_chk | |
2470 | (adapter, entry, esize); | |
2471 | if (rv < 0) | |
2472 | break; | |
2473 | buff_level += esize; | |
2474 | break; | |
2475 | case QUEUE: | |
2476 | dbuff = dump_buff + buff_level; | |
2477 | esize = netxen_md_rdqueue(adapter, | |
2478 | (void *) entry, (void *) dbuff); | |
2479 | rv = netxen_md_entry_err_chk | |
2480 | (adapter, entry, esize); | |
2481 | if (rv < 0) | |
2482 | break; | |
2483 | buff_level += esize; | |
2484 | break; | |
2485 | default: | |
2486 | entry->hdr.driver_flags |= NX_DUMP_SKIP; | |
2487 | break; | |
2488 | } | |
2489 | /* Next entry in the template */ | |
2490 | entry = (struct netxen_minidump_entry *) | |
2491 | ((char *) entry + entry->hdr.entry_size); | |
2492 | } | |
2493 | if (!sane_start || sane_end > 1) { | |
2494 | dev_err(&adapter->pdev->dev, | |
2495 | "Firmware minidump template configuration error.\n"); | |
2496 | } | |
2497 | return 0; | |
2498 | } | |
2499 | ||
2500 | static int | |
2501 | netxen_collect_minidump(struct netxen_adapter *adapter) | |
2502 | { | |
2503 | int ret = 0; | |
2504 | struct netxen_minidump_template_hdr *hdr; | |
2505 | struct timespec val; | |
2506 | hdr = (struct netxen_minidump_template_hdr *) | |
2507 | adapter->mdump.md_template; | |
2508 | hdr->driver_capture_mask = adapter->mdump.md_capture_mask; | |
2509 | jiffies_to_timespec(jiffies, &val); | |
2510 | hdr->driver_timestamp = (u32) val.tv_sec; | |
2511 | hdr->driver_info_word2 = adapter->fw_version; | |
2512 | hdr->driver_info_word3 = NXRD32(adapter, CRB_DRIVER_VERSION); | |
2513 | ret = netxen_parse_md_template(adapter); | |
2514 | if (ret) | |
2515 | return ret; | |
2516 | ||
2517 | return ret; | |
2518 | } | |
2519 | ||
2520 | ||
2521 | void | |
2522 | netxen_dump_fw(struct netxen_adapter *adapter) | |
2523 | { | |
2524 | struct netxen_minidump_template_hdr *hdr; | |
2525 | int i, k, data_size = 0; | |
2526 | u32 capture_mask; | |
2527 | hdr = (struct netxen_minidump_template_hdr *) | |
2528 | adapter->mdump.md_template; | |
2529 | capture_mask = adapter->mdump.md_capture_mask; | |
2530 | ||
2531 | for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) { | |
2532 | if (i & capture_mask) | |
2533 | data_size += hdr->capture_size_array[k]; | |
2534 | } | |
2535 | if (!data_size) { | |
2536 | dev_err(&adapter->pdev->dev, | |
2537 | "Invalid cap sizes for capture_mask=0x%x\n", | |
2538 | adapter->mdump.md_capture_mask); | |
2539 | return; | |
2540 | } | |
2541 | adapter->mdump.md_capture_size = data_size; | |
2542 | adapter->mdump.md_dump_size = adapter->mdump.md_template_size + | |
2543 | adapter->mdump.md_capture_size; | |
2544 | if (!adapter->mdump.md_capture_buff) { | |
2545 | adapter->mdump.md_capture_buff = | |
b2adaca9 JP |
2546 | vzalloc(adapter->mdump.md_dump_size); |
2547 | if (!adapter->mdump.md_capture_buff) | |
83f18a55 | 2548 | return; |
b2adaca9 | 2549 | |
83f18a55 M |
2550 | if (netxen_collect_minidump(adapter)) { |
2551 | adapter->mdump.has_valid_dump = 0; | |
2552 | adapter->mdump.md_dump_size = 0; | |
2553 | vfree(adapter->mdump.md_capture_buff); | |
2554 | adapter->mdump.md_capture_buff = NULL; | |
2555 | dev_err(&adapter->pdev->dev, | |
2556 | "Error in collecting firmware minidump.\n"); | |
2557 | } else { | |
2558 | adapter->mdump.md_timestamp = jiffies; | |
2559 | adapter->mdump.has_valid_dump = 1; | |
2560 | adapter->fw_mdump_rdy = 1; | |
2561 | dev_info(&adapter->pdev->dev, "%s Successfully " | |
2562 | "collected fw dump.\n", adapter->netdev->name); | |
2563 | } | |
2564 | ||
2565 | } else { | |
2566 | dev_info(&adapter->pdev->dev, | |
2567 | "Cannot overwrite previously collected " | |
2568 | "firmware minidump.\n"); | |
2569 | adapter->fw_mdump_rdy = 1; | |
2570 | return; | |
2571 | } | |
2572 | } |