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qed: Don't use main-ptt in unrelated flows
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
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fe56b9e6 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
fe56b9e6
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/io.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/mutex.h>
41#include <linux/pci.h>
42#include <linux/slab.h>
43#include <linux/string.h>
a91eb52a 44#include <linux/vmalloc.h>
fe56b9e6
YM		 45#include <linux/etherdevice.h>
46#include <linux/qed/qed_chain.h>
47#include <linux/qed/qed_if.h>
48#include "qed.h"
49#include "qed_cxt.h"
39651abd 50#include "qed_dcbx.h"
fe56b9e6 51#include "qed_dev_api.h"
1e128c81 52#include "qed_fcoe.h"
fe56b9e6
YM		 53#include "qed_hsi.h"
54#include "qed_hw.h"
55#include "qed_init_ops.h"
56#include "qed_int.h"
fc831825 57#include "qed_iscsi.h"
0a7fb11c 58#include "qed_ll2.h"
fe56b9e6 59#include "qed_mcp.h"
1d6cff4f 60#include "qed_ooo.h"
fe56b9e6
YM		 61#include "qed_reg_addr.h"
62#include "qed_sp.h"
32a47e72 63#include "qed_sriov.h"
0b55e27d 64#include "qed_vf.h"
51ff1725 65#include "qed_roce.h"
fe56b9e6 66
0caf5b26 67static DEFINE_SPINLOCK(qm_lock);
39651abd 68
51ff1725
RA		 69#define QED_MIN_DPIS (4)
70#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
71
fe56b9e6 72/* API common to all protocols */
c2035eea
RA		 73enum BAR_ID {
74 BAR_ID_0, /* used for GRC */
75 BAR_ID_1 /* Used for doorbells */
76};
77
15582962
RV		 78static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
79 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
c2035eea 80{
1408cc1f
YM		 81 u32 bar_reg = (bar_id == BAR_ID_0 ?
82 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
83 u32 val;
c2035eea 84
1408cc1f
YM		 85 if (IS_VF(p_hwfn->cdev))
86 return 1 << 17;
87
15582962 88 val = qed_rd(p_hwfn, p_ptt, bar_reg);
c2035eea
RA		 89 if (val)
90 return 1 << (val + 15);
91
92 /* Old MFW initialized above registered only conditionally */
93 if (p_hwfn->cdev->num_hwfns > 1) {
94 DP_INFO(p_hwfn,
95 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
96 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
97 } else {
98 DP_INFO(p_hwfn,
99 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
100 return 512 * 1024;
101 }
102}
103
1a635e48 104void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
fe56b9e6
YM		 105{
106 u32 i;
107
108 cdev->dp_level = dp_level;
109 cdev->dp_module = dp_module;
110 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
111 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
112
113 p_hwfn->dp_level = dp_level;
114 p_hwfn->dp_module = dp_module;
115 }
116}
117
118void qed_init_struct(struct qed_dev *cdev)
119{
120 u8 i;
121
122 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
123 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
124
125 p_hwfn->cdev = cdev;
126 p_hwfn->my_id = i;
127 p_hwfn->b_active = false;
128
129 mutex_init(&p_hwfn->dmae_info.mutex);
130 }
131
132 /* hwfn 0 is always active */
133 cdev->hwfns[0].b_active = true;
134
135 /* set the default cache alignment to 128 */
136 cdev->cache_shift = 7;
137}
138
139static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
140{
141 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
142
143 kfree(qm_info->qm_pq_params);
144 qm_info->qm_pq_params = NULL;
145 kfree(qm_info->qm_vport_params);
146 qm_info->qm_vport_params = NULL;
147 kfree(qm_info->qm_port_params);
148 qm_info->qm_port_params = NULL;
bcd197c8
MC		 149 kfree(qm_info->wfq_data);
150 qm_info->wfq_data = NULL;
fe56b9e6
YM		 151}
152
153void qed_resc_free(struct qed_dev *cdev)
154{
155 int i;
156
1408cc1f
YM		 157 if (IS_VF(cdev))
158 return;
159
fe56b9e6
YM		 160 kfree(cdev->fw_data);
161 cdev->fw_data = NULL;
162
163 kfree(cdev->reset_stats);
164
165 for_each_hwfn(cdev, i) {
166 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
167
168 qed_cxt_mngr_free(p_hwfn);
169 qed_qm_info_free(p_hwfn);
170 qed_spq_free(p_hwfn);
171 qed_eq_free(p_hwfn, p_hwfn->p_eq);
172 qed_consq_free(p_hwfn, p_hwfn->p_consq);
173 qed_int_free(p_hwfn);
0a7fb11c
YM		 174#ifdef CONFIG_QED_LL2
175 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
176#endif
1e128c81
AE		 177 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
178 qed_fcoe_free(p_hwfn, p_hwfn->p_fcoe_info);
179
1d6cff4f 180 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 181 qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 182 qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info);
183 }
32a47e72 184 qed_iov_free(p_hwfn);
fe56b9e6 185 qed_dmae_info_free(p_hwfn);
39651abd 186 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
fe56b9e6
YM		 187 }
188}
189
b5a9ee7c
AE		 190/******************** QM initialization *******************/
191#define ACTIVE_TCS_BMAP 0x9f
192#define ACTIVE_TCS_BMAP_4PORT_K2 0xf
193
194/* determines the physical queue flags for a given PF. */
195static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
fe56b9e6 196{
b5a9ee7c 197 u32 flags;
fe56b9e6 198
b5a9ee7c
AE		 199 /* common flags */
200 flags = PQ_FLAGS_LB;
fe56b9e6 201
b5a9ee7c
AE		 202 /* feature flags */
203 if (IS_QED_SRIOV(p_hwfn->cdev))
204 flags |= PQ_FLAGS_VFS;
dbb799c3 205
b5a9ee7c
AE		 206 /* protocol flags */
207 switch (p_hwfn->hw_info.personality) {
208 case QED_PCI_ETH:
209 flags |= PQ_FLAGS_MCOS;
210 break;
211 case QED_PCI_FCOE:
212 flags |= PQ_FLAGS_OFLD;
213 break;
214 case QED_PCI_ISCSI:
215 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
216 break;
217 case QED_PCI_ETH_ROCE:
218 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
219 break;
220 default:
221 DP_ERR(p_hwfn,
222 "unknown personality %d\n", p_hwfn->hw_info.personality);
223 return 0;
dbb799c3
YM		 224 }
225
b5a9ee7c
AE		 226 return flags;
227}
dbb799c3 228
b5a9ee7c
AE		 229/* Getters for resource amounts necessary for qm initialization */
230u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
231{
232 return p_hwfn->hw_info.num_hw_tc;
233}
fe56b9e6 234
b5a9ee7c
AE		 235u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
236{
237 return IS_QED_SRIOV(p_hwfn->cdev) ?
238 p_hwfn->cdev->p_iov_info->total_vfs : 0;
239}
fe56b9e6 240
b5a9ee7c 241#define NUM_DEFAULT_RLS 1
fe56b9e6 242
b5a9ee7c
AE		 243u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
244{
245 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
fe56b9e6 246
b5a9ee7c
AE		 247 /* num RLs can't exceed resource amount of rls or vports */
248 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
249 RESC_NUM(p_hwfn, QED_VPORT));
bcd197c8 250
b5a9ee7c
AE		 251 /* Make sure after we reserve there's something left */
252 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
253 return 0;
fe56b9e6 254
b5a9ee7c
AE		 255 /* subtract rls necessary for VFs and one default one for the PF */
256 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
dbb799c3 257
b5a9ee7c
AE		 258 return num_pf_rls;
259}
39651abd 260
b5a9ee7c
AE		 261u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
262{
263 u32 pq_flags = qed_get_pq_flags(p_hwfn);
264
265 /* all pqs share the same vport, except for vfs and pf_rl pqs */
266 return (!!(PQ_FLAGS_RLS & pq_flags)) *
267 qed_init_qm_get_num_pf_rls(p_hwfn) +
268 (!!(PQ_FLAGS_VFS & pq_flags)) *
269 qed_init_qm_get_num_vfs(p_hwfn) + 1;
270}
271
272/* calc amount of PQs according to the requested flags */
273u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
274{
275 u32 pq_flags = qed_get_pq_flags(p_hwfn);
276
277 return (!!(PQ_FLAGS_RLS & pq_flags)) *
278 qed_init_qm_get_num_pf_rls(p_hwfn) +
279 (!!(PQ_FLAGS_MCOS & pq_flags)) *
280 qed_init_qm_get_num_tcs(p_hwfn) +
281 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
282 (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
283 (!!(PQ_FLAGS_LLT & pq_flags)) +
284 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
285}
286
287/* initialize the top level QM params */
288static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
289{
290 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
291 bool four_port;
292
293 /* pq and vport bases for this PF */
294 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
295 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
296
297 /* rate limiting and weighted fair queueing are always enabled */
298 qm_info->vport_rl_en = 1;
299 qm_info->vport_wfq_en = 1;
fe56b9e6 300
b5a9ee7c
AE		 301 /* TC config is different for AH 4 port */
302 four_port = p_hwfn->cdev->num_ports_in_engines == MAX_NUM_PORTS_K2;
fe56b9e6 303
b5a9ee7c
AE		 304 /* in AH 4 port we have fewer TCs per port */
305 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
306 NUM_OF_PHYS_TCS;
307
308 /* unless MFW indicated otherwise, ooo_tc == 3 for
309 * AH 4-port and 4 otherwise.
310 */
311 if (!qm_info->ooo_tc)
312 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
313 DCBX_TCP_OOO_TC;
314}
315
316/* initialize qm vport params */
317static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
318{
319 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
320 u8 i;
321
322 /* all vports participate in weighted fair queueing */
323 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
324 qm_info->qm_vport_params[i].vport_wfq = 1;
325}
326
327/* initialize qm port params */
328static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
329{
fe56b9e6 330 /* Initialize qm port parameters */
b5a9ee7c
AE		 331 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engines;
332
333 /* indicate how ooo and high pri traffic is dealt with */
334 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
335 ACTIVE_TCS_BMAP_4PORT_K2 :
336 ACTIVE_TCS_BMAP;
337
fe56b9e6 338 for (i = 0; i < num_ports; i++) {
b5a9ee7c
AE		 339 struct init_qm_port_params *p_qm_port =
340 &p_hwfn->qm_info.qm_port_params[i];
341
fe56b9e6 342 p_qm_port->active = 1;
b5a9ee7c 343 p_qm_port->active_phys_tcs = active_phys_tcs;
fe56b9e6
YM		 344 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
345 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
346 }
b5a9ee7c
AE		 347}
348
349/* Reset the params which must be reset for qm init. QM init may be called as
350 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
351 * params may be affected by the init but would simply recalculate to the same
352 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
353 * affected as these amounts stay the same.
354 */
355static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
356{
357 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
358
359 qm_info->num_pqs = 0;
360 qm_info->num_vports = 0;
361 qm_info->num_pf_rls = 0;
362 qm_info->num_vf_pqs = 0;
363 qm_info->first_vf_pq = 0;
364 qm_info->first_mcos_pq = 0;
365 qm_info->first_rl_pq = 0;
366}
367
368static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
369{
370 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
371
372 qm_info->num_vports++;
373
374 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
375 DP_ERR(p_hwfn,
376 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
377 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
378}
379
380/* initialize a single pq and manage qm_info resources accounting.
381 * The pq_init_flags param determines whether the PQ is rate limited
382 * (for VF or PF) and whether a new vport is allocated to the pq or not
383 * (i.e. vport will be shared).
384 */
fe56b9e6 385
b5a9ee7c
AE		 386/* flags for pq init */
387#define PQ_INIT_SHARE_VPORT (1 << 0)
388#define PQ_INIT_PF_RL (1 << 1)
389#define PQ_INIT_VF_RL (1 << 2)
fe56b9e6 390
b5a9ee7c
AE		 391/* defines for pq init */
392#define PQ_INIT_DEFAULT_WRR_GROUP 1
393#define PQ_INIT_DEFAULT_TC 0
394#define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
fe56b9e6 395
b5a9ee7c
AE		 396static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
397 struct qed_qm_info *qm_info,
398 u8 tc, u32 pq_init_flags)
399{
400 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
401
402 if (pq_idx > max_pq)
403 DP_ERR(p_hwfn,
404 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
405
406 /* init pq params */
407 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
408 qm_info->num_vports;
409 qm_info->qm_pq_params[pq_idx].tc_id = tc;
410 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
411 qm_info->qm_pq_params[pq_idx].rl_valid =
412 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
413
414 /* qm params accounting */
415 qm_info->num_pqs++;
416 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
417 qm_info->num_vports++;
418
419 if (pq_init_flags & PQ_INIT_PF_RL)
420 qm_info->num_pf_rls++;
421
422 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
423 DP_ERR(p_hwfn,
424 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
425 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
426
427 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
428 DP_ERR(p_hwfn,
429 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
430 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
431}
432
433/* get pq index according to PQ_FLAGS */
434static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
435 u32 pq_flags)
436{
437 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
438
439 /* Can't have multiple flags set here */
440 if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
441 goto err;
442
443 switch (pq_flags) {
444 case PQ_FLAGS_RLS:
445 return &qm_info->first_rl_pq;
446 case PQ_FLAGS_MCOS:
447 return &qm_info->first_mcos_pq;
448 case PQ_FLAGS_LB:
449 return &qm_info->pure_lb_pq;
450 case PQ_FLAGS_OOO:
451 return &qm_info->ooo_pq;
452 case PQ_FLAGS_ACK:
453 return &qm_info->pure_ack_pq;
454 case PQ_FLAGS_OFLD:
455 return &qm_info->offload_pq;
456 case PQ_FLAGS_LLT:
457 return &qm_info->low_latency_pq;
458 case PQ_FLAGS_VFS:
459 return &qm_info->first_vf_pq;
460 default:
461 goto err;
462 }
463
464err:
465 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
466 return NULL;
467}
468
469/* save pq index in qm info */
470static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
471 u32 pq_flags, u16 pq_val)
472{
473 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
474
475 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
476}
477
478/* get tx pq index, with the PQ TX base already set (ready for context init) */
479u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
480{
481 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
482
483 return *base_pq_idx + CM_TX_PQ_BASE;
484}
485
486u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
487{
488 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
489
490 if (tc > max_tc)
491 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
492
493 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
494}
495
496u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
497{
498 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
499
500 if (vf > max_vf)
501 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
502
503 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
504}
505
506u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
507{
508 u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
509
510 if (rl > max_rl)
511 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
512
513 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
514}
515
516/* Functions for creating specific types of pqs */
517static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
518{
519 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
520
521 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
522 return;
523
524 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
525 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
526}
527
528static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
529{
530 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
531
532 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
533 return;
534
535 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
536 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
537}
538
539static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
540{
541 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
542
543 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
544 return;
545
546 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
547 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
548}
549
550static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
551{
552 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
553
554 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
555 return;
556
557 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
558 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
559}
560
561static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
562{
563 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
564
565 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
566 return;
567
568 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
569 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
570}
571
572static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
573{
574 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
575 u8 tc_idx;
576
577 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
578 return;
579
580 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
581 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
582 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
583}
584
585static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
586{
587 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
588 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
589
590 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
591 return;
592
593 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1408cc1f 594 qm_info->num_vf_pqs = num_vfs;
b5a9ee7c
AE		 595 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
596 qed_init_qm_pq(p_hwfn,
597 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
598}
fe56b9e6 599
b5a9ee7c
AE		 600static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
601{
602 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
603 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
a64b02d5 604
b5a9ee7c
AE		 605 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
606 return;
607
608 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
609 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
610 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
611}
612
613static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
614{
615 /* rate limited pqs, must come first (FW assumption) */
616 qed_init_qm_rl_pqs(p_hwfn);
617
618 /* pqs for multi cos */
619 qed_init_qm_mcos_pqs(p_hwfn);
620
621 /* pure loopback pq */
622 qed_init_qm_lb_pq(p_hwfn);
623
624 /* out of order pq */
625 qed_init_qm_ooo_pq(p_hwfn);
626
627 /* pure ack pq */
628 qed_init_qm_pure_ack_pq(p_hwfn);
629
630 /* pq for offloaded protocol */
631 qed_init_qm_offload_pq(p_hwfn);
632
633 /* low latency pq */
634 qed_init_qm_low_latency_pq(p_hwfn);
635
636 /* done sharing vports */
637 qed_init_qm_advance_vport(p_hwfn);
638
639 /* pqs for vfs */
640 qed_init_qm_vf_pqs(p_hwfn);
641}
642
643/* compare values of getters against resources amounts */
644static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
645{
646 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
647 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
648 return -EINVAL;
649 }
650
651 if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
652 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
653 return -EINVAL;
654 }
fe56b9e6
YM		 655
656 return 0;
b5a9ee7c 657}
fe56b9e6 658
b5a9ee7c
AE		 659static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
660{
661 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
662 struct init_qm_vport_params *vport;
663 struct init_qm_port_params *port;
664 struct init_qm_pq_params *pq;
665 int i, tc;
666
667 /* top level params */
668 DP_VERBOSE(p_hwfn,
669 NETIF_MSG_HW,
670 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
671 qm_info->start_pq,
672 qm_info->start_vport,
673 qm_info->pure_lb_pq,
674 qm_info->offload_pq, qm_info->pure_ack_pq);
675 DP_VERBOSE(p_hwfn,
676 NETIF_MSG_HW,
677 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
678 qm_info->ooo_pq,
679 qm_info->first_vf_pq,
680 qm_info->num_pqs,
681 qm_info->num_vf_pqs,
682 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
683 DP_VERBOSE(p_hwfn,
684 NETIF_MSG_HW,
685 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
686 qm_info->pf_rl_en,
687 qm_info->pf_wfq_en,
688 qm_info->vport_rl_en,
689 qm_info->vport_wfq_en,
690 qm_info->pf_wfq,
691 qm_info->pf_rl,
692 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
693
694 /* port table */
695 for (i = 0; i < p_hwfn->cdev->num_ports_in_engines; i++) {
696 port = &(qm_info->qm_port_params[i]);
697 DP_VERBOSE(p_hwfn,
698 NETIF_MSG_HW,
699 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
700 i,
701 port->active,
702 port->active_phys_tcs,
703 port->num_pbf_cmd_lines,
704 port->num_btb_blocks, port->reserved);
705 }
706
707 /* vport table */
708 for (i = 0; i < qm_info->num_vports; i++) {
709 vport = &(qm_info->qm_vport_params[i]);
710 DP_VERBOSE(p_hwfn,
711 NETIF_MSG_HW,
712 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
713 qm_info->start_vport + i,
714 vport->vport_rl, vport->vport_wfq);
715 for (tc = 0; tc < NUM_OF_TCS; tc++)
716 DP_VERBOSE(p_hwfn,
717 NETIF_MSG_HW,
718 "%d ", vport->first_tx_pq_id[tc]);
719 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
720 }
721
722 /* pq table */
723 for (i = 0; i < qm_info->num_pqs; i++) {
724 pq = &(qm_info->qm_pq_params[i]);
725 DP_VERBOSE(p_hwfn,
726 NETIF_MSG_HW,
727 "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
728 qm_info->start_pq + i,
729 pq->vport_id,
730 pq->tc_id, pq->wrr_group, pq->rl_valid);
731 }
732}
733
734static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
735{
736 /* reset params required for init run */
737 qed_init_qm_reset_params(p_hwfn);
738
739 /* init QM top level params */
740 qed_init_qm_params(p_hwfn);
741
742 /* init QM port params */
743 qed_init_qm_port_params(p_hwfn);
744
745 /* init QM vport params */
746 qed_init_qm_vport_params(p_hwfn);
747
748 /* init QM physical queue params */
749 qed_init_qm_pq_params(p_hwfn);
750
751 /* display all that init */
752 qed_dp_init_qm_params(p_hwfn);
fe56b9e6
YM		 753}
754
39651abd
SRK		 755/* This function reconfigures the QM pf on the fly.
756 * For this purpose we:
757 * 1. reconfigure the QM database
758 * 2. set new values to runtime arrat
759 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
760 * 4. activate init tool in QM_PF stage
761 * 5. send an sdm_qm_cmd through rbc interface to release the QM
762 */
763int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
764{
765 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
766 bool b_rc;
767 int rc;
768
39651abd 769 /* initialize qed's qm data structure */
b5a9ee7c 770 qed_init_qm_info(p_hwfn);
39651abd
SRK		 771
772 /* stop PF's qm queues */
773 spin_lock_bh(&qm_lock);
774 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
775 qm_info->start_pq, qm_info->num_pqs);
776 spin_unlock_bh(&qm_lock);
777 if (!b_rc)
778 return -EINVAL;
779
780 /* clear the QM_PF runtime phase leftovers from previous init */
781 qed_init_clear_rt_data(p_hwfn);
782
783 /* prepare QM portion of runtime array */
15582962 784 qed_qm_init_pf(p_hwfn, p_ptt);
39651abd
SRK		 785
786 /* activate init tool on runtime array */
787 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
788 p_hwfn->hw_info.hw_mode);
789 if (rc)
790 return rc;
791
792 /* start PF's qm queues */
793 spin_lock_bh(&qm_lock);
794 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
795 qm_info->start_pq, qm_info->num_pqs);
796 spin_unlock_bh(&qm_lock);
797 if (!b_rc)
798 return -EINVAL;
799
800 return 0;
801}
802
b5a9ee7c
AE		 803static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
804{
805 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
806 int rc;
807
808 rc = qed_init_qm_sanity(p_hwfn);
809 if (rc)
810 goto alloc_err;
811
812 qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
813 qed_init_qm_get_num_pqs(p_hwfn),
814 GFP_KERNEL);
815 if (!qm_info->qm_pq_params)
816 goto alloc_err;
817
818 qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
819 qed_init_qm_get_num_vports(p_hwfn),
820 GFP_KERNEL);
821 if (!qm_info->qm_vport_params)
822 goto alloc_err;
823
824 qm_info->qm_port_params = kzalloc(sizeof(qm_info->qm_port_params) *
825 p_hwfn->cdev->num_ports_in_engines,
826 GFP_KERNEL);
827 if (!qm_info->qm_port_params)
828 goto alloc_err;
829
830 qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
831 qed_init_qm_get_num_vports(p_hwfn),
832 GFP_KERNEL);
833 if (!qm_info->wfq_data)
834 goto alloc_err;
835
836 return 0;
837
838alloc_err:
839 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
840 qed_qm_info_free(p_hwfn);
841 return -ENOMEM;
842}
843
fe56b9e6
YM		 844int qed_resc_alloc(struct qed_dev *cdev)
845{
fc831825 846 struct qed_iscsi_info *p_iscsi_info;
1e128c81 847 struct qed_fcoe_info *p_fcoe_info;
1d6cff4f 848 struct qed_ooo_info *p_ooo_info;
0a7fb11c
YM		 849#ifdef CONFIG_QED_LL2
850 struct qed_ll2_info *p_ll2_info;
851#endif
f9dc4d1f 852 u32 rdma_tasks, excess_tasks;
fe56b9e6
YM		 853 struct qed_consq *p_consq;
854 struct qed_eq *p_eq;
f9dc4d1f 855 u32 line_count;
fe56b9e6
YM		 856 int i, rc = 0;
857
1408cc1f
YM		 858 if (IS_VF(cdev))
859 return rc;
860
fe56b9e6
YM		 861 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
862 if (!cdev->fw_data)
863 return -ENOMEM;
864
865 for_each_hwfn(cdev, i) {
866 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dbb799c3 867 u32 n_eqes, num_cons;
fe56b9e6
YM		 868
869 /* First allocate the context manager structure */
870 rc = qed_cxt_mngr_alloc(p_hwfn);
871 if (rc)
872 goto alloc_err;
873
874 /* Set the HW cid/tid numbers (in the contest manager)
875 * Must be done prior to any further computations.
876 */
f9dc4d1f 877 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
fe56b9e6
YM		 878 if (rc)
879 goto alloc_err;
880
b5a9ee7c 881 rc = qed_alloc_qm_data(p_hwfn);
fe56b9e6
YM		 882 if (rc)
883 goto alloc_err;
884
b5a9ee7c
AE		 885 /* init qm info */
886 qed_init_qm_info(p_hwfn);
887
fe56b9e6 888 /* Compute the ILT client partition */
f9dc4d1f
RA		 889 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
890 if (rc) {
891 DP_NOTICE(p_hwfn,
892 "too many ILT lines; re-computing with less lines\n");
893 /* In case there are not enough ILT lines we reduce the
894 * number of RDMA tasks and re-compute.
895 */
896 excess_tasks =
897 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
898 if (!excess_tasks)
899 goto alloc_err;
900
901 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
902 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
903 if (rc)
904 goto alloc_err;
905
906 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
907 if (rc) {
908 DP_ERR(p_hwfn,
909 "failed ILT compute. Requested too many lines: %u\n",
910 line_count);
911
912 goto alloc_err;
913 }
914 }
fe56b9e6
YM		 915
916 /* CID map / ILT shadow table / T2
917 * The talbes sizes are determined by the computations above
918 */
919 rc = qed_cxt_tables_alloc(p_hwfn);
920 if (rc)
921 goto alloc_err;
922
923 /* SPQ, must follow ILT because initializes SPQ context */
924 rc = qed_spq_alloc(p_hwfn);
925 if (rc)
926 goto alloc_err;
927
928 /* SP status block allocation */
929 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
930 RESERVED_PTT_DPC);
931
932 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
933 if (rc)
934 goto alloc_err;
935
32a47e72
YM		 936 rc = qed_iov_alloc(p_hwfn);
937 if (rc)
938 goto alloc_err;
939
fe56b9e6 940 /* EQ */
dbb799c3
YM		 941 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
942 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
943 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
944 PROTOCOLID_ROCE,
8c93beaf 945 NULL) * 2;
dbb799c3
YM		 946 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
947 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
948 num_cons =
949 qed_cxt_get_proto_cid_count(p_hwfn,
8c93beaf
YM		 950 PROTOCOLID_ISCSI,
951 NULL);
dbb799c3
YM		 952 n_eqes += 2 * num_cons;
953 }
954
955 if (n_eqes > 0xFFFF) {
956 DP_ERR(p_hwfn,
957 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
958 n_eqes, 0xFFFF);
1b4985b5 959 rc = -EINVAL;
fe56b9e6 960 goto alloc_err;
9b15acbf 961 }
dbb799c3
YM		 962
963 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
964 if (!p_eq)
965 goto alloc_no_mem;
fe56b9e6
YM		 966 p_hwfn->p_eq = p_eq;
967
968 p_consq = qed_consq_alloc(p_hwfn);
dbb799c3
YM		 969 if (!p_consq)
970 goto alloc_no_mem;
fe56b9e6
YM		 971 p_hwfn->p_consq = p_consq;
972
0a7fb11c
YM		 973#ifdef CONFIG_QED_LL2
974 if (p_hwfn->using_ll2) {
975 p_ll2_info = qed_ll2_alloc(p_hwfn);
976 if (!p_ll2_info)
977 goto alloc_no_mem;
978 p_hwfn->p_ll2_info = p_ll2_info;
979 }
980#endif
1e128c81
AE		 981
982 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
983 p_fcoe_info = qed_fcoe_alloc(p_hwfn);
984 if (!p_fcoe_info)
985 goto alloc_no_mem;
986 p_hwfn->p_fcoe_info = p_fcoe_info;
987 }
988
fc831825
YM		 989 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
990 p_iscsi_info = qed_iscsi_alloc(p_hwfn);
991 if (!p_iscsi_info)
992 goto alloc_no_mem;
993 p_hwfn->p_iscsi_info = p_iscsi_info;
1d6cff4f
YM		 994 p_ooo_info = qed_ooo_alloc(p_hwfn);
995 if (!p_ooo_info)
996 goto alloc_no_mem;
997 p_hwfn->p_ooo_info = p_ooo_info;
fc831825 998 }
0a7fb11c 999
fe56b9e6
YM		 1000 /* DMA info initialization */
1001 rc = qed_dmae_info_alloc(p_hwfn);
2591c280 1002 if (rc)
fe56b9e6 1003 goto alloc_err;
39651abd
SRK		 1004
1005 /* DCBX initialization */
1006 rc = qed_dcbx_info_alloc(p_hwfn);
2591c280 1007 if (rc)
39651abd 1008 goto alloc_err;
fe56b9e6
YM		 1009 }
1010
1011 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2591c280 1012 if (!cdev->reset_stats)
83aeb933 1013 goto alloc_no_mem;
fe56b9e6
YM		 1014
1015 return 0;
1016
dbb799c3
YM		 1017alloc_no_mem:
1018 rc = -ENOMEM;
fe56b9e6
YM		 1019alloc_err:
1020 qed_resc_free(cdev);
1021 return rc;
1022}
1023
1024void qed_resc_setup(struct qed_dev *cdev)
1025{
1026 int i;
1027
1408cc1f
YM		 1028 if (IS_VF(cdev))
1029 return;
1030
fe56b9e6
YM		 1031 for_each_hwfn(cdev, i) {
1032 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1033
1034 qed_cxt_mngr_setup(p_hwfn);
1035 qed_spq_setup(p_hwfn);
1036 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
1037 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
1038
1039 /* Read shadow of current MFW mailbox */
1040 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1041 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1042 p_hwfn->mcp_info->mfw_mb_cur,
1043 p_hwfn->mcp_info->mfw_mb_length);
1044
1045 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
32a47e72
YM		 1046
1047 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
0a7fb11c
YM		 1048#ifdef CONFIG_QED_LL2
1049 if (p_hwfn->using_ll2)
1050 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
1051#endif
1e128c81
AE		 1052 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1053 qed_fcoe_setup(p_hwfn, p_hwfn->p_fcoe_info);
1054
1d6cff4f 1055 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 1056 qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 1057 qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info);
1058 }
fe56b9e6
YM		 1059 }
1060}
1061
fe56b9e6
YM		 1062#define FINAL_CLEANUP_POLL_CNT (100)
1063#define FINAL_CLEANUP_POLL_TIME (10)
1064int qed_final_cleanup(struct qed_hwfn *p_hwfn,
0b55e27d 1065 struct qed_ptt *p_ptt, u16 id, bool is_vf)
fe56b9e6
YM		 1066{
1067 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1068 int rc = -EBUSY;
1069
fc48b7a6
YM		 1070 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1071 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
fe56b9e6 1072
0b55e27d
YM		 1073 if (is_vf)
1074 id += 0x10;
1075
fc48b7a6
YM		 1076 command |= X_FINAL_CLEANUP_AGG_INT <<
1077 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1078 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1079 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1080 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
fe56b9e6
YM		 1081
1082 /* Make sure notification is not set before initiating final cleanup */
1083 if (REG_RD(p_hwfn, addr)) {
1a635e48
YM		 1084 DP_NOTICE(p_hwfn,
1085 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
fe56b9e6
YM		 1086 REG_WR(p_hwfn, addr, 0);
1087 }
1088
1089 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1090 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1091 id, command);
1092
1093 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1094
1095 /* Poll until completion */
1096 while (!REG_RD(p_hwfn, addr) && count--)
1097 msleep(FINAL_CLEANUP_POLL_TIME);
1098
1099 if (REG_RD(p_hwfn, addr))
1100 rc = 0;
1101 else
1102 DP_NOTICE(p_hwfn,
1103 "Failed to receive FW final cleanup notification\n");
1104
1105 /* Cleanup afterwards */
1106 REG_WR(p_hwfn, addr, 0);
1107
1108 return rc;
1109}
1110
9c79ddaa 1111static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
fe56b9e6
YM		 1112{
1113 int hw_mode = 0;
1114
9c79ddaa
MY		 1115 if (QED_IS_BB_B0(p_hwfn->cdev)) {
1116 hw_mode |= 1 << MODE_BB;
1117 } else if (QED_IS_AH(p_hwfn->cdev)) {
1118 hw_mode |= 1 << MODE_K2;
1119 } else {
1120 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1121 p_hwfn->cdev->type);
1122 return -EINVAL;
1123 }
fe56b9e6
YM		 1124
1125 switch (p_hwfn->cdev->num_ports_in_engines) {
1126 case 1:
1127 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1128 break;
1129 case 2:
1130 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1131 break;
1132 case 4:
1133 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1134 break;
1135 default:
1136 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1137 p_hwfn->cdev->num_ports_in_engines);
9c79ddaa 1138 return -EINVAL;
fe56b9e6
YM		 1139 }
1140
1141 switch (p_hwfn->cdev->mf_mode) {
fc48b7a6
YM		 1142 case QED_MF_DEFAULT:
1143 case QED_MF_NPAR:
1144 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6 1145 break;
fc48b7a6 1146 case QED_MF_OVLAN:
fe56b9e6
YM		 1147 hw_mode |= 1 << MODE_MF_SD;
1148 break;
fe56b9e6 1149 default:
fc48b7a6
YM		 1150 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1151 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6
YM		 1152 }
1153
1154 hw_mode |= 1 << MODE_ASIC;
1155
1af9dcf7
YM		 1156 if (p_hwfn->cdev->num_hwfns > 1)
1157 hw_mode |= 1 << MODE_100G;
1158
fe56b9e6 1159 p_hwfn->hw_info.hw_mode = hw_mode;
1af9dcf7
YM		 1160
1161 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1162 "Configuring function for hw_mode: 0x%08x\n",
1163 p_hwfn->hw_info.hw_mode);
9c79ddaa
MY		 1164
1165 return 0;
fe56b9e6
YM		 1166}
1167
1168/* Init run time data for all PFs on an engine. */
1169static void qed_init_cau_rt_data(struct qed_dev *cdev)
1170{
1171 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1172 int i, sb_id;
1173
1174 for_each_hwfn(cdev, i) {
1175 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1176 struct qed_igu_info *p_igu_info;
1177 struct qed_igu_block *p_block;
1178 struct cau_sb_entry sb_entry;
1179
1180 p_igu_info = p_hwfn->hw_info.p_igu_info;
1181
1182 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
1183 sb_id++) {
1184 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1185 if (!p_block->is_pf)
1186 continue;
1187
1188 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1a635e48
YM		 1189 p_block->function_id, 0, 0);
1190 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
fe56b9e6
YM		 1191 }
1192 }
1193}
1194
1195static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1a635e48 1196 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6
YM		 1197{
1198 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1199 struct qed_qm_common_rt_init_params params;
1200 struct qed_dev *cdev = p_hwfn->cdev;
9c79ddaa 1201 u8 vf_id, max_num_vfs;
dbb799c3 1202 u16 num_pfs, pf_id;
1408cc1f 1203 u32 concrete_fid;
fe56b9e6
YM		 1204 int rc = 0;
1205
1206 qed_init_cau_rt_data(cdev);
1207
1208 /* Program GTT windows */
1209 qed_gtt_init(p_hwfn);
1210
1211 if (p_hwfn->mcp_info) {
1212 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1213 qm_info->pf_rl_en = 1;
1214 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1215 qm_info->pf_wfq_en = 1;
1216 }
1217
1218 memset(&params, 0, sizeof(params));
1219 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
1220 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1221 params.pf_rl_en = qm_info->pf_rl_en;
1222 params.pf_wfq_en = qm_info->pf_wfq_en;
1223 params.vport_rl_en = qm_info->vport_rl_en;
1224 params.vport_wfq_en = qm_info->vport_wfq_en;
1225 params.port_params = qm_info->qm_port_params;
1226
1227 qed_qm_common_rt_init(p_hwfn, &params);
1228
1229 qed_cxt_hw_init_common(p_hwfn);
1230
1231 /* Close gate from NIG to BRB/Storm; By default they are open, but
1232 * we close them to prevent NIG from passing data to reset blocks.
1233 * Should have been done in the ENGINE phase, but init-tool lacks
1234 * proper port-pretend capabilities.
1235 */
1236 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1237 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1238 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1239 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1240 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1241 qed_port_unpretend(p_hwfn, p_ptt);
1242
1243 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1a635e48 1244 if (rc)
fe56b9e6
YM		 1245 return rc;
1246
1247 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1248 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1249
dbb799c3
YM		 1250 if (QED_IS_BB(p_hwfn->cdev)) {
1251 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1252 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1253 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1254 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1255 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1256 }
1257 /* pretend to original PF */
1258 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1259 }
fe56b9e6 1260
9c79ddaa
MY		 1261 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1262 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1408cc1f
YM		 1263 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1264 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1265 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
05fafbfb
YM		 1266 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1267 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1268 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1408cc1f
YM		 1269 }
1270 /* pretend to original PF */
1271 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1272
fe56b9e6
YM		 1273 return rc;
1274}
1275
51ff1725
RA		 1276static int
1277qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1278 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1279{
1280 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1281 u32 dpi_bit_shift, dpi_count;
1282 u32 min_dpis;
1283
1284 /* Calculate DPI size */
1285 dpi_page_size_1 = QED_WID_SIZE * n_cpus;
1286 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
1287 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
1288 dpi_page_size = roundup_pow_of_two(dpi_page_size);
1289 dpi_bit_shift = ilog2(dpi_page_size / 4096);
1290
1291 dpi_count = pwm_region_size / dpi_page_size;
1292
1293 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1294 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1295
1296 p_hwfn->dpi_size = dpi_page_size;
1297 p_hwfn->dpi_count = dpi_count;
1298
1299 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1300
1301 if (dpi_count < min_dpis)
1302 return -EINVAL;
1303
1304 return 0;
1305}
1306
1307enum QED_ROCE_EDPM_MODE {
1308 QED_ROCE_EDPM_MODE_ENABLE = 0,
1309 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1310 QED_ROCE_EDPM_MODE_DISABLE = 2,
1311};
1312
1313static int
1314qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1315{
1316 u32 pwm_regsize, norm_regsize;
1317 u32 non_pwm_conn, min_addr_reg1;
1318 u32 db_bar_size, n_cpus;
1319 u32 roce_edpm_mode;
1320 u32 pf_dems_shift;
1321 int rc = 0;
1322 u8 cond;
1323
15582962 1324 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
51ff1725
RA		 1325 if (p_hwfn->cdev->num_hwfns > 1)
1326 db_bar_size /= 2;
1327
1328 /* Calculate doorbell regions */
1329 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1330 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1331 NULL) +
1332 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1333 NULL);
1334 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
1335 min_addr_reg1 = norm_regsize / 4096;
1336 pwm_regsize = db_bar_size - norm_regsize;
1337
1338 /* Check that the normal and PWM sizes are valid */
1339 if (db_bar_size < norm_regsize) {
1340 DP_ERR(p_hwfn->cdev,
1341 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1342 db_bar_size, norm_regsize);
1343 return -EINVAL;
1344 }
1345
1346 if (pwm_regsize < QED_MIN_PWM_REGION) {
1347 DP_ERR(p_hwfn->cdev,
1348 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1349 pwm_regsize,
1350 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1351 return -EINVAL;
1352 }
1353
1354 /* Calculate number of DPIs */
1355 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1356 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1357 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1358 /* Either EDPM is mandatory, or we are attempting to allocate a
1359 * WID per CPU.
1360 */
c2dedf87 1361 n_cpus = num_present_cpus();
51ff1725
RA		 1362 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1363 }
1364
1365 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1366 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1367 if (cond || p_hwfn->dcbx_no_edpm) {
1368 /* Either EDPM is disabled from user configuration, or it is
1369 * disabled via DCBx, or it is not mandatory and we failed to
1370 * allocated a WID per CPU.
1371 */
1372 n_cpus = 1;
1373 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1374
1375 if (cond)
1376 qed_rdma_dpm_bar(p_hwfn, p_ptt);
1377 }
1378
1379 DP_INFO(p_hwfn,
1380 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1381 norm_regsize,
1382 pwm_regsize,
1383 p_hwfn->dpi_size,
1384 p_hwfn->dpi_count,
1385 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1386 "disabled" : "enabled");
1387
1388 if (rc) {
1389 DP_ERR(p_hwfn,
1390 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1391 p_hwfn->dpi_count,
1392 p_hwfn->pf_params.rdma_pf_params.min_dpis);
1393 return -EINVAL;
1394 }
1395
1396 p_hwfn->dpi_start_offset = norm_regsize;
1397
1398 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1399 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1400 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1401 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1402
1403 return 0;
1404}
1405
fe56b9e6 1406static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1a635e48 1407 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6 1408{
05fafbfb
YM		 1409 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
1410 p_hwfn->port_id, hw_mode);
fe56b9e6
YM		 1411}
1412
1413static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1414 struct qed_ptt *p_ptt,
464f6645 1415 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 1416 int hw_mode,
1417 bool b_hw_start,
1418 enum qed_int_mode int_mode,
1419 bool allow_npar_tx_switch)
1420{
1421 u8 rel_pf_id = p_hwfn->rel_pf_id;
1422 int rc = 0;
1423
1424 if (p_hwfn->mcp_info) {
1425 struct qed_mcp_function_info *p_info;
1426
1427 p_info = &p_hwfn->mcp_info->func_info;
1428 if (p_info->bandwidth_min)
1429 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1430
1431 /* Update rate limit once we'll actually have a link */
4b01e519 1432 p_hwfn->qm_info.pf_rl = 100000;
fe56b9e6
YM		 1433 }
1434
15582962 1435 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
fe56b9e6
YM		 1436
1437 qed_int_igu_init_rt(p_hwfn);
1438
1439 /* Set VLAN in NIG if needed */
1a635e48 1440 if (hw_mode & BIT(MODE_MF_SD)) {
fe56b9e6
YM		 1441 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1442 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1443 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1444 p_hwfn->hw_info.ovlan);
1445 }
1446
1447 /* Enable classification by MAC if needed */
1a635e48 1448 if (hw_mode & BIT(MODE_MF_SI)) {
fe56b9e6
YM		 1449 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1450 "Configuring TAGMAC_CLS_TYPE\n");
1451 STORE_RT_REG(p_hwfn,
1452 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1453 }
1454
1455 /* Protocl Configuration */
dbb799c3
YM		 1456 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1457 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1e128c81
AE		 1458 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1459 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
fe56b9e6
YM		 1460 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1461
1462 /* Cleanup chip from previous driver if such remains exist */
0b55e27d 1463 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1a635e48 1464 if (rc)
fe56b9e6
YM		 1465 return rc;
1466
1467 /* PF Init sequence */
1468 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1469 if (rc)
1470 return rc;
1471
1472 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1473 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1474 if (rc)
1475 return rc;
1476
1477 /* Pure runtime initializations - directly to the HW */
1478 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1479
51ff1725
RA		 1480 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1481 if (rc)
1482 return rc;
1483
fe56b9e6
YM		 1484 if (b_hw_start) {
1485 /* enable interrupts */
1486 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1487
1488 /* send function start command */
831bfb0e
YM		 1489 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1490 allow_npar_tx_switch);
1e128c81 1491 if (rc) {
fe56b9e6 1492 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1e128c81
AE		 1493 return rc;
1494 }
1495 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1496 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1497 qed_wr(p_hwfn, p_ptt,
1498 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1499 0x100);
1500 }
fe56b9e6
YM		 1501 }
1502 return rc;
1503}
1504
1505static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1506 struct qed_ptt *p_ptt,
1507 u8 enable)
1508{
1509 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1510
1511 /* Change PF in PXP */
1512 qed_wr(p_hwfn, p_ptt,
1513 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1514
1515 /* wait until value is set - try for 1 second every 50us */
1516 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1517 val = qed_rd(p_hwfn, p_ptt,
1518 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1519 if (val == set_val)
1520 break;
1521
1522 usleep_range(50, 60);
1523 }
1524
1525 if (val != set_val) {
1526 DP_NOTICE(p_hwfn,
1527 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1528 return -EAGAIN;
1529 }
1530
1531 return 0;
1532}
1533
1534static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1535 struct qed_ptt *p_main_ptt)
1536{
1537 /* Read shadow of current MFW mailbox */
1538 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1539 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1a635e48 1540 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
fe56b9e6
YM		 1541}
1542
5d24bcf1
TT		 1543static void
1544qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1545 struct qed_drv_load_params *p_drv_load)
1546{
1547 memset(p_load_req, 0, sizeof(*p_load_req));
1548
1549 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1550 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1551 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1552 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1553 p_load_req->override_force_load = p_drv_load->override_force_load;
1554}
1555
c0c2d0b4 1556int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
fe56b9e6 1557{
5d24bcf1 1558 struct qed_load_req_params load_req_params;
0fefbfba
SK		 1559 u32 load_code, param, drv_mb_param;
1560 bool b_default_mtu = true;
1561 struct qed_hwfn *p_hwfn;
1562 int rc = 0, mfw_rc, i;
fe56b9e6 1563
c0c2d0b4 1564 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
bb13ace7
SRK		 1565 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1566 return -EINVAL;
1567 }
1568
1408cc1f 1569 if (IS_PF(cdev)) {
c0c2d0b4 1570 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1a635e48 1571 if (rc)
1408cc1f
YM		 1572 return rc;
1573 }
fe56b9e6
YM		 1574
1575 for_each_hwfn(cdev, i) {
1576 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1577
0fefbfba
SK		 1578 /* If management didn't provide a default, set one of our own */
1579 if (!p_hwfn->hw_info.mtu) {
1580 p_hwfn->hw_info.mtu = 1500;
1581 b_default_mtu = false;
1582 }
1583
1408cc1f
YM		 1584 if (IS_VF(cdev)) {
1585 p_hwfn->b_int_enabled = 1;
1586 continue;
1587 }
1588
fe56b9e6
YM		 1589 /* Enable DMAE in PXP */
1590 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1591
9c79ddaa
MY		 1592 rc = qed_calc_hw_mode(p_hwfn);
1593 if (rc)
1594 return rc;
fe56b9e6 1595
5d24bcf1
TT		 1596 qed_fill_load_req_params(&load_req_params,
1597 p_params->p_drv_load_params);
1598 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1599 &load_req_params);
fe56b9e6 1600 if (rc) {
5d24bcf1 1601 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
fe56b9e6
YM		 1602 return rc;
1603 }
1604
5d24bcf1 1605 load_code = load_req_params.load_code;
fe56b9e6 1606 DP_VERBOSE(p_hwfn, QED_MSG_SP,
5d24bcf1
TT		 1607 "Load request was sent. Load code: 0x%x\n",
1608 load_code);
1609
1610 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
fe56b9e6
YM		 1611
1612 p_hwfn->first_on_engine = (load_code ==
1613 FW_MSG_CODE_DRV_LOAD_ENGINE);
1614
1615 switch (load_code) {
1616 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1617 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1618 p_hwfn->hw_info.hw_mode);
1619 if (rc)
1620 break;
1621 /* Fall into */
1622 case FW_MSG_CODE_DRV_LOAD_PORT:
1623 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1624 p_hwfn->hw_info.hw_mode);
1625 if (rc)
1626 break;
1627
1628 /* Fall into */
1629 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1630 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
c0c2d0b4
MY		 1631 p_params->p_tunn,
1632 p_hwfn->hw_info.hw_mode,
1633 p_params->b_hw_start,
1634 p_params->int_mode,
1635 p_params->allow_npar_tx_switch);
fe56b9e6
YM		 1636 break;
1637 default:
c0c2d0b4
MY		 1638 DP_NOTICE(p_hwfn,
1639 "Unexpected load code [0x%08x]", load_code);
fe56b9e6
YM		 1640 rc = -EINVAL;
1641 break;
1642 }
1643
1644 if (rc)
1645 DP_NOTICE(p_hwfn,
1646 "init phase failed for loadcode 0x%x (rc %d)\n",
1647 load_code, rc);
1648
1649 /* ACK mfw regardless of success or failure of initialization */
1650 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1651 DRV_MSG_CODE_LOAD_DONE,
1652 0, &load_code, &param);
1653 if (rc)
1654 return rc;
1655 if (mfw_rc) {
1656 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1657 return mfw_rc;
1658 }
1659
39651abd
SRK		 1660 /* send DCBX attention request command */
1661 DP_VERBOSE(p_hwfn,
1662 QED_MSG_DCB,
1663 "sending phony dcbx set command to trigger DCBx attention handling\n");
1664 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1665 DRV_MSG_CODE_SET_DCBX,
1666 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1667 &load_code, &param);
1668 if (mfw_rc) {
1669 DP_NOTICE(p_hwfn,
1670 "Failed to send DCBX attention request\n");
1671 return mfw_rc;
1672 }
1673
fe56b9e6
YM		 1674 p_hwfn->hw_init_done = true;
1675 }
1676
0fefbfba
SK		 1677 if (IS_PF(cdev)) {
1678 p_hwfn = QED_LEADING_HWFN(cdev);
5d24bcf1 1679 drv_mb_param = STORM_FW_VERSION;
0fefbfba
SK		 1680 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1681 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1682 drv_mb_param, &load_code, &param);
1683 if (rc)
1684 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1685
1686 if (!b_default_mtu) {
1687 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1688 p_hwfn->hw_info.mtu);
1689 if (rc)
1690 DP_INFO(p_hwfn,
1691 "Failed to update default mtu\n");
1692 }
1693
1694 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1695 p_hwfn->p_main_ptt,
1696 QED_OV_DRIVER_STATE_DISABLED);
1697 if (rc)
1698 DP_INFO(p_hwfn, "Failed to update driver state\n");
1699
1700 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1701 QED_OV_ESWITCH_VEB);
1702 if (rc)
1703 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1704 }
1705
fe56b9e6
YM		 1706 return 0;
1707}
1708
1709#define QED_HW_STOP_RETRY_LIMIT (10)
1a635e48
YM		 1710static void qed_hw_timers_stop(struct qed_dev *cdev,
1711 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
8c925c44
YM		 1712{
1713 int i;
1714
1715 /* close timers */
1716 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1717 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1718
1719 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1720 if ((!qed_rd(p_hwfn, p_ptt,
1721 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1a635e48 1722 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
8c925c44
YM		 1723 break;
1724
1725 /* Dependent on number of connection/tasks, possibly
1726 * 1ms sleep is required between polls
1727 */
1728 usleep_range(1000, 2000);
1729 }
1730
1731 if (i < QED_HW_STOP_RETRY_LIMIT)
1732 return;
1733
1734 DP_NOTICE(p_hwfn,
1735 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1736 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1737 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1738}
1739
1740void qed_hw_timers_stop_all(struct qed_dev *cdev)
1741{
1742 int j;
1743
1744 for_each_hwfn(cdev, j) {
1745 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1746 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1747
1748 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1749 }
1750}
1751
fe56b9e6
YM		 1752int qed_hw_stop(struct qed_dev *cdev)
1753{
1226337a
TT		 1754 struct qed_hwfn *p_hwfn;
1755 struct qed_ptt *p_ptt;
1756 int rc, rc2 = 0;
8c925c44 1757 int j;
fe56b9e6
YM		 1758
1759 for_each_hwfn(cdev, j) {
1226337a
TT		 1760 p_hwfn = &cdev->hwfns[j];
1761 p_ptt = p_hwfn->p_main_ptt;
fe56b9e6
YM		 1762
1763 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1764
1408cc1f 1765 if (IS_VF(cdev)) {
0b55e27d 1766 qed_vf_pf_int_cleanup(p_hwfn);
1226337a
TT		 1767 rc = qed_vf_pf_reset(p_hwfn);
1768 if (rc) {
1769 DP_NOTICE(p_hwfn,
1770 "qed_vf_pf_reset failed. rc = %d.\n",
1771 rc);
1772 rc2 = -EINVAL;
1773 }
1408cc1f
YM		 1774 continue;
1775 }
1776
fe56b9e6
YM		 1777 /* mark the hw as uninitialized... */
1778 p_hwfn->hw_init_done = false;
1779
1226337a
TT		 1780 /* Send unload command to MCP */
1781 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1782 if (rc) {
1783 DP_NOTICE(p_hwfn,
1784 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1785 rc);
1786 rc2 = -EINVAL;
1787 }
1788
1789 qed_slowpath_irq_sync(p_hwfn);
1790
1791 /* After this point no MFW attentions are expected, e.g. prevent
1792 * race between pf stop and dcbx pf update.
1793 */
fe56b9e6 1794 rc = qed_sp_pf_stop(p_hwfn);
1226337a 1795 if (rc) {
8c925c44 1796 DP_NOTICE(p_hwfn,
1226337a
TT		 1797 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1798 rc);
1799 rc2 = -EINVAL;
1800 }
fe56b9e6
YM		 1801
1802 qed_wr(p_hwfn, p_ptt,
1803 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1804
1805 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1806 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1807 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1808 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1809 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1810
8c925c44 1811 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
fe56b9e6
YM		 1812
1813 /* Disable Attention Generation */
1814 qed_int_igu_disable_int(p_hwfn, p_ptt);
1815
1816 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1817 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1818
1819 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1820
1821 /* Need to wait 1ms to guarantee SBs are cleared */
1822 usleep_range(1000, 2000);
1226337a
TT		 1823
1824 /* Disable PF in HW blocks */
1825 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1826 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1827
1828 qed_mcp_unload_done(p_hwfn, p_ptt);
1829 if (rc) {
1830 DP_NOTICE(p_hwfn,
1831 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1832 rc);
1833 rc2 = -EINVAL;
1834 }
fe56b9e6
YM		 1835 }
1836
1408cc1f 1837 if (IS_PF(cdev)) {
1226337a
TT		 1838 p_hwfn = QED_LEADING_HWFN(cdev);
1839 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1840
1408cc1f
YM		 1841 /* Disable DMAE in PXP - in CMT, this should only be done for
1842 * first hw-function, and only after all transactions have
1843 * stopped for all active hw-functions.
1844 */
1226337a
TT		 1845 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1846 if (rc) {
1847 DP_NOTICE(p_hwfn,
1848 "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1849 rc2 = -EINVAL;
1850 }
1408cc1f 1851 }
fe56b9e6 1852
1226337a 1853 return rc2;
fe56b9e6
YM		 1854}
1855
15582962 1856int qed_hw_stop_fastpath(struct qed_dev *cdev)
cee4d264 1857{
8c925c44 1858 int j;
cee4d264
MC		 1859
1860 for_each_hwfn(cdev, j) {
1861 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
15582962 1862 struct qed_ptt *p_ptt;
dacd88d6
YM		 1863
1864 if (IS_VF(cdev)) {
1865 qed_vf_pf_int_cleanup(p_hwfn);
1866 continue;
1867 }
15582962
RV		 1868 p_ptt = qed_ptt_acquire(p_hwfn);
1869 if (!p_ptt)
1870 return -EAGAIN;
cee4d264
MC		 1871
1872 DP_VERBOSE(p_hwfn,
1a635e48 1873 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
cee4d264
MC		 1874
1875 qed_wr(p_hwfn, p_ptt,
1876 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1877
1878 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1879 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1880 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1881 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1882 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1883
cee4d264
MC		 1884 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1885
1886 /* Need to wait 1ms to guarantee SBs are cleared */
1887 usleep_range(1000, 2000);
15582962 1888 qed_ptt_release(p_hwfn, p_ptt);
cee4d264 1889 }
15582962
RV		 1890
1891 return 0;
cee4d264
MC		 1892}
1893
15582962 1894int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
cee4d264 1895{
15582962
RV		 1896 struct qed_ptt *p_ptt;
1897
dacd88d6 1898 if (IS_VF(p_hwfn->cdev))
15582962
RV		 1899 return 0;
1900
1901 p_ptt = qed_ptt_acquire(p_hwfn);
1902 if (!p_ptt)
1903 return -EAGAIN;
dacd88d6 1904
cee4d264 1905 /* Re-open incoming traffic */
15582962
RV		 1906 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1907 qed_ptt_release(p_hwfn, p_ptt);
1908
1909 return 0;
cee4d264
MC		 1910}
1911
fe56b9e6
YM		 1912/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1913static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1914{
1915 qed_ptt_pool_free(p_hwfn);
1916 kfree(p_hwfn->hw_info.p_igu_info);
1917}
1918
1919/* Setup bar access */
12e09c69 1920static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
fe56b9e6 1921{
fe56b9e6 1922 /* clear indirect access */
9c79ddaa
MY		 1923 if (QED_IS_AH(p_hwfn->cdev)) {
1924 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1925 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
1926 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1927 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
1928 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1929 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
1930 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1931 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
1932 } else {
1933 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1934 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
1935 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1936 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
1937 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1938 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
1939 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1940 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
1941 }
fe56b9e6
YM		 1942
1943 /* Clean Previous errors if such exist */
1944 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1a635e48 1945 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
fe56b9e6
YM		 1946
1947 /* enable internal target-read */
1948 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1949 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
fe56b9e6
YM		 1950}
1951
1952static void get_function_id(struct qed_hwfn *p_hwfn)
1953{
1954 /* ME Register */
1a635e48
YM		 1955 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1956 PXP_PF_ME_OPAQUE_ADDR);
fe56b9e6
YM		 1957
1958 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1959
1960 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1961 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1962 PXP_CONCRETE_FID_PFID);
1963 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1964 PXP_CONCRETE_FID_PORT);
525ef5c0
YM		 1965
1966 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1967 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1968 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
fe56b9e6
YM		 1969}
1970
25c089d7
YM		 1971static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1972{
1973 u32 *feat_num = p_hwfn->hw_info.feat_num;
5a1f965a 1974 struct qed_sb_cnt_info sb_cnt_info;
810bb1f0 1975 u32 non_l2_sbs = 0;
25c089d7 1976
0189efb8
YM		 1977 if (IS_ENABLED(CONFIG_QED_RDMA) &&
1978 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
1979 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
1980 * the status blocks equally between L2 / RoCE but with
1981 * consideration as to how many l2 queues / cnqs we have.
1982 */
51ff1725 1983 feat_num[QED_RDMA_CNQ] =
810bb1f0 1984 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 2,
51ff1725 1985 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
810bb1f0
MY		 1986
1987 non_l2_sbs = feat_num[QED_RDMA_CNQ];
51ff1725 1988 }
0189efb8 1989
dec26533
MY		 1990 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
1991 p_hwfn->hw_info.personality == QED_PCI_ETH) {
1992 /* Start by allocating VF queues, then PF's */
1993 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1994 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1995 feat_num[QED_VF_L2_QUE] = min_t(u32,
1996 RESC_NUM(p_hwfn, QED_L2_QUEUE),
1997 sb_cnt_info.sb_iov_cnt);
1998 feat_num[QED_PF_L2_QUE] = min_t(u32,
1999 RESC_NUM(p_hwfn, QED_SB) -
2000 non_l2_sbs,
2001 RESC_NUM(p_hwfn,
2002 QED_L2_QUEUE) -
2003 FEAT_NUM(p_hwfn,
2004 QED_VF_L2_QUE));
2005 }
5a1f965a
MY		 2006
2007 DP_VERBOSE(p_hwfn,
2008 NETIF_MSG_PROBE,
810bb1f0 2009 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d\n",
5a1f965a
MY		 2010 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2011 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2012 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
810bb1f0 2013 RESC_NUM(p_hwfn, QED_SB));
25c089d7
YM		 2014}
2015
9c8517c4 2016const char *qed_hw_get_resc_name(enum qed_resources res_id)
2edbff8d 2017{
2edbff8d 2018 switch (res_id) {
2edbff8d 2019 case QED_L2_QUEUE:
9c8517c4 2020 return "L2_QUEUE";
2edbff8d 2021 case QED_VPORT:
9c8517c4 2022 return "VPORT";
2edbff8d 2023 case QED_RSS_ENG:
9c8517c4 2024 return "RSS_ENG";
2edbff8d 2025 case QED_PQ:
9c8517c4 2026 return "PQ";
2edbff8d 2027 case QED_RL:
9c8517c4 2028 return "RL";
2edbff8d 2029 case QED_MAC:
9c8517c4 2030 return "MAC";
2edbff8d 2031 case QED_VLAN:
9c8517c4
TT		 2032 return "VLAN";
2033 case QED_RDMA_CNQ_RAM:
2034 return "RDMA_CNQ_RAM";
2edbff8d 2035 case QED_ILT:
9c8517c4 2036 return "ILT";
2edbff8d 2037 case QED_LL2_QUEUE:
9c8517c4 2038 return "LL2_QUEUE";
2edbff8d 2039 case QED_CMDQS_CQS:
9c8517c4 2040 return "CMDQS_CQS";
2edbff8d 2041 case QED_RDMA_STATS_QUEUE:
9c8517c4
TT		 2042 return "RDMA_STATS_QUEUE";
2043 case QED_BDQ:
2044 return "BDQ";
2045 case QED_SB:
2046 return "SB";
2edbff8d 2047 default:
9c8517c4 2048 return "UNKNOWN_RESOURCE";
2edbff8d 2049 }
9c8517c4
TT		 2050}
2051
2052static int
2053__qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2054 struct qed_ptt *p_ptt,
2055 enum qed_resources res_id,
2056 u32 resc_max_val, u32 *p_mcp_resp)
2057{
2058 int rc;
2edbff8d 2059
9c8517c4
TT		 2060 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2061 resc_max_val, p_mcp_resp);
2062 if (rc) {
2063 DP_NOTICE(p_hwfn,
2064 "MFW response failure for a max value setting of resource %d [%s]\n",
2065 res_id, qed_hw_get_resc_name(res_id));
2066 return rc;
2067 }
2068
2069 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2070 DP_INFO(p_hwfn,
2071 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2072 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2073
2074 return 0;
2075}
2076
2077static int
2078qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2079{
2080 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2081 u32 resc_max_val, mcp_resp;
2082 u8 res_id;
2083 int rc;
2084
2085 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2086 switch (res_id) {
2087 case QED_LL2_QUEUE:
2088 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2089 break;
2090 case QED_RDMA_CNQ_RAM:
2091 /* No need for a case for QED_CMDQS_CQS since
2092 * CNQ/CMDQS are the same resource.
2093 */
2094 resc_max_val = NUM_OF_CMDQS_CQS;
2095 break;
2096 case QED_RDMA_STATS_QUEUE:
2097 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2098 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2099 break;
2100 case QED_BDQ:
2101 resc_max_val = BDQ_NUM_RESOURCES;
2102 break;
2103 default:
2104 continue;
2105 }
2106
2107 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2108 resc_max_val, &mcp_resp);
2109 if (rc)
2110 return rc;
2111
2112 /* There's no point to continue to the next resource if the
2113 * command is not supported by the MFW.
2114 * We do continue if the command is supported but the resource
2115 * is unknown to the MFW. Such a resource will be later
2116 * configured with the default allocation values.
2117 */
2118 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2119 return -EINVAL;
2120 }
2121
2122 return 0;
2edbff8d
TT		 2123}
2124
9c8517c4
TT		 2125static
2126int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2127 enum qed_resources res_id,
2128 u32 *p_resc_num, u32 *p_resc_start)
fe56b9e6 2129{
1408cc1f 2130 u8 num_funcs = p_hwfn->num_funcs_on_engine;
9c79ddaa 2131 bool b_ah = QED_IS_AH(p_hwfn->cdev);
4ac801b7 2132 struct qed_sb_cnt_info sb_cnt_info;
fe56b9e6 2133
2edbff8d 2134 switch (res_id) {
2edbff8d 2135 case QED_L2_QUEUE:
9c8517c4
TT		 2136 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2137 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2edbff8d
TT		 2138 break;
2139 case QED_VPORT:
9c8517c4
TT		 2140 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2141 MAX_NUM_VPORTS_BB) / num_funcs;
2edbff8d
TT		 2142 break;
2143 case QED_RSS_ENG:
9c8517c4
TT		 2144 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2145 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2edbff8d
TT		 2146 break;
2147 case QED_PQ:
9c8517c4
TT		 2148 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2149 MAX_QM_TX_QUEUES_BB) / num_funcs;
2150 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
2edbff8d
TT		 2151 break;
2152 case QED_RL:
9c8517c4 2153 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2edbff8d
TT		 2154 break;
2155 case QED_MAC:
2156 case QED_VLAN:
2157 /* Each VFC resource can accommodate both a MAC and a VLAN */
9c8517c4 2158 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2edbff8d
TT		 2159 break;
2160 case QED_ILT:
9c8517c4
TT		 2161 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2162 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2edbff8d
TT		 2163 break;
2164 case QED_LL2_QUEUE:
9c8517c4 2165 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2edbff8d
TT		 2166 break;
2167 case QED_RDMA_CNQ_RAM:
2168 case QED_CMDQS_CQS:
2169 /* CNQ/CMDQS are the same resource */
9c8517c4 2170 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
2edbff8d
TT		 2171 break;
2172 case QED_RDMA_STATS_QUEUE:
9c8517c4
TT		 2173 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2174 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2edbff8d 2175 break;
9c8517c4
TT		 2176 case QED_BDQ:
2177 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2178 p_hwfn->hw_info.personality != QED_PCI_FCOE)
2179 *p_resc_num = 0;
2180 else
2181 *p_resc_num = 1;
2182 break;
2183 case QED_SB:
2184 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2185 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2186 *p_resc_num = sb_cnt_info.sb_cnt;
2edbff8d 2187 break;
9c8517c4
TT		 2188 default:
2189 return -EINVAL;
2edbff8d 2190 }
08feecd7 2191
2edbff8d 2192 switch (res_id) {
9c8517c4
TT		 2193 case QED_BDQ:
2194 if (!*p_resc_num)
2195 *p_resc_start = 0;
2196 else if (p_hwfn->cdev->num_ports_in_engines == 4)
2197 *p_resc_start = p_hwfn->port_id;
2198 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2199 *p_resc_start = p_hwfn->port_id;
2200 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2201 *p_resc_start = p_hwfn->port_id + 2;
2202 break;
2edbff8d 2203 default:
9c8517c4
TT		 2204 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2205 break;
2edbff8d 2206 }
9c8517c4
TT		 2207
2208 return 0;
2edbff8d
TT		 2209}
2210
9c8517c4
TT		 2211static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2212 enum qed_resources res_id)
2edbff8d 2213{
9c8517c4
TT		 2214 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2215 u32 mcp_resp, *p_resc_num, *p_resc_start;
2edbff8d
TT		 2216 int rc;
2217
2218 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2219 p_resc_start = &RESC_START(p_hwfn, res_id);
2220
9c8517c4
TT		 2221 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2222 &dflt_resc_start);
2223 if (rc) {
2edbff8d
TT		 2224 DP_ERR(p_hwfn,
2225 "Failed to get default amount for resource %d [%s]\n",
2226 res_id, qed_hw_get_resc_name(res_id));
9c8517c4 2227 return rc;
2edbff8d
TT		 2228 }
2229
9c8517c4
TT		 2230 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2231 &mcp_resp, p_resc_num, p_resc_start);
2edbff8d
TT		 2232 if (rc) {
2233 DP_NOTICE(p_hwfn,
2234 "MFW response failure for an allocation request for resource %d [%s]\n",
2235 res_id, qed_hw_get_resc_name(res_id));
2236 return rc;
2237 }
2238
2239 /* Default driver values are applied in the following cases:
2240 * - The resource allocation MB command is not supported by the MFW
2241 * - There is an internal error in the MFW while processing the request
2242 * - The resource ID is unknown to the MFW
2243 */
9c8517c4
TT		 2244 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2245 DP_INFO(p_hwfn,
2246 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2247 res_id,
2248 qed_hw_get_resc_name(res_id),
2249 mcp_resp, dflt_resc_num, dflt_resc_start);
2edbff8d
TT		 2250 *p_resc_num = dflt_resc_num;
2251 *p_resc_start = dflt_resc_start;
2252 goto out;
2253 }
2254
2255 /* Special handling for status blocks; Would be revised in future */
2256 if (res_id == QED_SB) {
9c8517c4
TT		 2257 *p_resc_num -= 1;
2258 *p_resc_start -= p_hwfn->enabled_func_idx;
2edbff8d 2259 }
2edbff8d
TT		 2260out:
2261 /* PQs have to divide by 8 [that's the HW granularity].
2262 * Reduce number so it would fit.
2263 */
2264 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2265 DP_INFO(p_hwfn,
2266 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2267 *p_resc_num,
2268 (*p_resc_num) & ~0x7,
2269 *p_resc_start, (*p_resc_start) & ~0x7);
2270 *p_resc_num &= ~0x7;
2271 *p_resc_start &= ~0x7;
2272 }
4ac801b7 2273
2edbff8d
TT		 2274 return 0;
2275}
2276
9c8517c4 2277static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2edbff8d 2278{
2edbff8d 2279 int rc;
9c8517c4 2280 u8 res_id;
2edbff8d
TT		 2281
2282 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
9c8517c4 2283 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2edbff8d
TT		 2284 if (rc)
2285 return rc;
2286 }
dbb799c3 2287
9c8517c4
TT		 2288 return 0;
2289}
2290
2291#define QED_RESC_ALLOC_LOCK_RETRY_CNT 10
2292#define QED_RESC_ALLOC_LOCK_RETRY_INTVL_US 10000 /* 10 msec */
2293
2294static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2295{
2296 struct qed_resc_unlock_params resc_unlock_params;
2297 struct qed_resc_lock_params resc_lock_params;
2298 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2299 u8 res_id;
2300 int rc;
2301
2302 /* Setting the max values of the soft resources and the following
2303 * resources allocation queries should be atomic. Since several PFs can
2304 * run in parallel - a resource lock is needed.
2305 * If either the resource lock or resource set value commands are not
2306 * supported - skip the the max values setting, release the lock if
2307 * needed, and proceed to the queries. Other failures, including a
2308 * failure to acquire the lock, will cause this function to fail.
2309 */
2310 memset(&resc_lock_params, 0, sizeof(resc_lock_params));
2311 resc_lock_params.resource = QED_RESC_LOCK_RESC_ALLOC;
2312 resc_lock_params.retry_num = QED_RESC_ALLOC_LOCK_RETRY_CNT;
2313 resc_lock_params.retry_interval = QED_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2314 resc_lock_params.sleep_b4_retry = true;
2315 memset(&resc_unlock_params, 0, sizeof(resc_unlock_params));
2316 resc_unlock_params.resource = QED_RESC_LOCK_RESC_ALLOC;
2317
2318 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2319 if (rc && rc != -EINVAL) {
2320 return rc;
2321 } else if (rc == -EINVAL) {
2322 DP_INFO(p_hwfn,
2323 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2324 } else if (!rc && !resc_lock_params.b_granted) {
2325 DP_NOTICE(p_hwfn,
2326 "Failed to acquire the resource lock for the resource allocation commands\n");
2327 return -EBUSY;
2328 } else {
2329 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2330 if (rc && rc != -EINVAL) {
2331 DP_NOTICE(p_hwfn,
2332 "Failed to set the max values of the soft resources\n");
2333 goto unlock_and_exit;
2334 } else if (rc == -EINVAL) {
2335 DP_INFO(p_hwfn,
2336 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2337 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2338 &resc_unlock_params);
2339 if (rc)
2340 DP_INFO(p_hwfn,
2341 "Failed to release the resource lock for the resource allocation commands\n");
2342 }
2343 }
2344
2345 rc = qed_hw_set_resc_info(p_hwfn);
2346 if (rc)
2347 goto unlock_and_exit;
2348
2349 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2350 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2351 if (rc)
2352 DP_INFO(p_hwfn,
2353 "Failed to release the resource lock for the resource allocation commands\n");
2354 }
2355
dbb799c3 2356 /* Sanity for ILT */
9c79ddaa
MY		 2357 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2358 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
dbb799c3
YM		 2359 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2360 RESC_START(p_hwfn, QED_ILT),
2361 RESC_END(p_hwfn, QED_ILT) - 1);
2362 return -EINVAL;
2363 }
fe56b9e6 2364
25c089d7
YM		 2365 qed_hw_set_feat(p_hwfn);
2366
2edbff8d
TT		 2367 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2368 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2369 qed_hw_get_resc_name(res_id),
2370 RESC_NUM(p_hwfn, res_id),
2371 RESC_START(p_hwfn, res_id));
dbb799c3
YM		 2372
2373 return 0;
9c8517c4
TT		 2374
2375unlock_and_exit:
2376 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2377 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2378 return rc;
fe56b9e6
YM		 2379}
2380
1a635e48 2381static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6 2382{
fc48b7a6 2383 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1e128c81 2384 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
cc875c2e 2385 struct qed_mcp_link_params *link;
fe56b9e6
YM		 2386
2387 /* Read global nvm_cfg address */
2388 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2389
2390 /* Verify MCP has initialized it */
2391 if (!nvm_cfg_addr) {
2392 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2393 return -EINVAL;
2394 }
2395
2396 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2397 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2398
cc875c2e
YM		 2399 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2400 offsetof(struct nvm_cfg1, glob) +
2401 offsetof(struct nvm_cfg1_glob, core_cfg);
2402
2403 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2404
2405 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2406 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
351a4ded 2407 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
cc875c2e
YM		 2408 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2409 break;
351a4ded 2410 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
cc875c2e
YM		 2411 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2412 break;
351a4ded 2413 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
cc875c2e
YM		 2414 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2415 break;
351a4ded 2416 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
cc875c2e
YM		 2417 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2418 break;
351a4ded 2419 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
cc875c2e
YM		 2420 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2421 break;
351a4ded 2422 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
cc875c2e
YM		 2423 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2424 break;
351a4ded 2425 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
cc875c2e
YM		 2426 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2427 break;
351a4ded 2428 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
cc875c2e
YM		 2429 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2430 break;
9c79ddaa
MY		 2431 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2432 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2433 break;
351a4ded 2434 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
cc875c2e
YM		 2435 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2436 break;
9c79ddaa
MY		 2437 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2438 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2439 break;
cc875c2e 2440 default:
1a635e48 2441 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
cc875c2e
YM		 2442 break;
2443 }
2444
cc875c2e
YM		 2445 /* Read default link configuration */
2446 link = &p_hwfn->mcp_info->link_input;
2447 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2448 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2449 link_temp = qed_rd(p_hwfn, p_ptt,
2450 port_cfg_addr +
2451 offsetof(struct nvm_cfg1_port, speed_cap_mask));
83aeb933
YM		 2452 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2453 link->speed.advertised_speeds = link_temp;
cc875c2e 2454
83aeb933
YM		 2455 link_temp = link->speed.advertised_speeds;
2456 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
cc875c2e
YM		 2457
2458 link_temp = qed_rd(p_hwfn, p_ptt,
2459 port_cfg_addr +
2460 offsetof(struct nvm_cfg1_port, link_settings));
2461 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2462 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2463 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2464 link->speed.autoneg = true;
2465 break;
2466 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2467 link->speed.forced_speed = 1000;
2468 break;
2469 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2470 link->speed.forced_speed = 10000;
2471 break;
2472 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2473 link->speed.forced_speed = 25000;
2474 break;
2475 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2476 link->speed.forced_speed = 40000;
2477 break;
2478 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2479 link->speed.forced_speed = 50000;
2480 break;
351a4ded 2481 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
cc875c2e
YM		 2482 link->speed.forced_speed = 100000;
2483 break;
2484 default:
1a635e48 2485 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
cc875c2e
YM		 2486 }
2487
2488 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2489 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2490 link->pause.autoneg = !!(link_temp &
2491 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2492 link->pause.forced_rx = !!(link_temp &
2493 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2494 link->pause.forced_tx = !!(link_temp &
2495 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2496 link->loopback_mode = 0;
2497
2498 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2499 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2500 link->speed.forced_speed, link->speed.advertised_speeds,
2501 link->speed.autoneg, link->pause.autoneg);
2502
fe56b9e6
YM		 2503 /* Read Multi-function information from shmem */
2504 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2505 offsetof(struct nvm_cfg1, glob) +
2506 offsetof(struct nvm_cfg1_glob, generic_cont0);
2507
2508 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2509
2510 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2511 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2512
2513 switch (mf_mode) {
2514 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
fc48b7a6 2515 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
fe56b9e6
YM		 2516 break;
2517 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
fc48b7a6 2518 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
fe56b9e6 2519 break;
fc48b7a6
YM		 2520 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2521 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
fe56b9e6
YM		 2522 break;
2523 }
2524 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2525 p_hwfn->cdev->mf_mode);
2526
fc48b7a6
YM		 2527 /* Read Multi-function information from shmem */
2528 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2529 offsetof(struct nvm_cfg1, glob) +
2530 offsetof(struct nvm_cfg1_glob, device_capabilities);
2531
2532 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2533 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2534 __set_bit(QED_DEV_CAP_ETH,
2535 &p_hwfn->hw_info.device_capabilities);
1e128c81
AE		 2536 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2537 __set_bit(QED_DEV_CAP_FCOE,
2538 &p_hwfn->hw_info.device_capabilities);
c5ac9319
YM		 2539 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2540 __set_bit(QED_DEV_CAP_ISCSI,
2541 &p_hwfn->hw_info.device_capabilities);
2542 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2543 __set_bit(QED_DEV_CAP_ROCE,
2544 &p_hwfn->hw_info.device_capabilities);
fc48b7a6 2545
fe56b9e6
YM		 2546 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2547}
2548
1408cc1f
YM		 2549static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2550{
dbb799c3
YM		 2551 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2552 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
9c79ddaa 2553 struct qed_dev *cdev = p_hwfn->cdev;
1408cc1f 2554
9c79ddaa 2555 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
1408cc1f
YM		 2556
2557 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2558 * in the other bits are selected.
2559 * Bits 1-15 are for functions 1-15, respectively, and their value is
2560 * '0' only for enabled functions (function 0 always exists and
2561 * enabled).
2562 * In case of CMT, only the "even" functions are enabled, and thus the
2563 * number of functions for both hwfns is learnt from the same bits.
2564 */
2565 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2566
2567 if (reg_function_hide & 0x1) {
9c79ddaa
MY		 2568 if (QED_IS_BB(cdev)) {
2569 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2570 num_funcs = 0;
2571 eng_mask = 0xaaaa;
2572 } else {
2573 num_funcs = 1;
2574 eng_mask = 0x5554;
2575 }
1408cc1f
YM		 2576 } else {
2577 num_funcs = 1;
9c79ddaa 2578 eng_mask = 0xfffe;
1408cc1f
YM		 2579 }
2580
2581 /* Get the number of the enabled functions on the engine */
2582 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2583 while (tmp) {
2584 if (tmp & 0x1)
2585 num_funcs++;
2586 tmp >>= 0x1;
2587 }
dbb799c3
YM		 2588
2589 /* Get the PF index within the enabled functions */
2590 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2591 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2592 while (tmp) {
2593 if (tmp & 0x1)
2594 enabled_func_idx--;
2595 tmp >>= 0x1;
2596 }
1408cc1f
YM		 2597 }
2598
2599 p_hwfn->num_funcs_on_engine = num_funcs;
dbb799c3 2600 p_hwfn->enabled_func_idx = enabled_func_idx;
1408cc1f
YM		 2601
2602 DP_VERBOSE(p_hwfn,
2603 NETIF_MSG_PROBE,
525ef5c0 2604 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1408cc1f
YM		 2605 p_hwfn->rel_pf_id,
2606 p_hwfn->abs_pf_id,
525ef5c0 2607 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1408cc1f
YM		 2608}
2609
9c79ddaa
MY		 2610static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2611 struct qed_ptt *p_ptt)
fe56b9e6
YM		 2612{
2613 u32 port_mode;
fe56b9e6 2614
9c79ddaa 2615 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
fe56b9e6
YM		 2616
2617 if (port_mode < 3) {
2618 p_hwfn->cdev->num_ports_in_engines = 1;
2619 } else if (port_mode <= 5) {
2620 p_hwfn->cdev->num_ports_in_engines = 2;
2621 } else {
2622 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2623 p_hwfn->cdev->num_ports_in_engines);
2624
2625 /* Default num_ports_in_engines to something */
2626 p_hwfn->cdev->num_ports_in_engines = 1;
2627 }
9c79ddaa
MY		 2628}
2629
2630static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2631 struct qed_ptt *p_ptt)
2632{
2633 u32 port;
2634 int i;
2635
2636 p_hwfn->cdev->num_ports_in_engines = 0;
2637
2638 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2639 port = qed_rd(p_hwfn, p_ptt,
2640 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2641 if (port & 1)
2642 p_hwfn->cdev->num_ports_in_engines++;
2643 }
2644
2645 if (!p_hwfn->cdev->num_ports_in_engines) {
2646 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2647
2648 /* Default num_ports_in_engine to something */
2649 p_hwfn->cdev->num_ports_in_engines = 1;
2650 }
2651}
2652
2653static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2654{
2655 if (QED_IS_BB(p_hwfn->cdev))
2656 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2657 else
2658 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2659}
2660
2661static int
2662qed_get_hw_info(struct qed_hwfn *p_hwfn,
2663 struct qed_ptt *p_ptt,
2664 enum qed_pci_personality personality)
2665{
2666 int rc;
2667
2668 /* Since all information is common, only first hwfns should do this */
2669 if (IS_LEAD_HWFN(p_hwfn)) {
2670 rc = qed_iov_hw_info(p_hwfn);
2671 if (rc)
2672 return rc;
2673 }
2674
2675 qed_hw_info_port_num(p_hwfn, p_ptt);
fe56b9e6
YM		 2676
2677 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2678
2679 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2680 if (rc)
2681 return rc;
2682
2683 if (qed_mcp_is_init(p_hwfn))
2684 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2685 p_hwfn->mcp_info->func_info.mac);
2686 else
2687 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2688
2689 if (qed_mcp_is_init(p_hwfn)) {
2690 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2691 p_hwfn->hw_info.ovlan =
2692 p_hwfn->mcp_info->func_info.ovlan;
2693
2694 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2695 }
2696
2697 if (qed_mcp_is_init(p_hwfn)) {
2698 enum qed_pci_personality protocol;
2699
2700 protocol = p_hwfn->mcp_info->func_info.protocol;
2701 p_hwfn->hw_info.personality = protocol;
2702 }
2703
b5a9ee7c
AE		 2704 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2705 p_hwfn->hw_info.num_active_tc = 1;
2706
1408cc1f
YM		 2707 qed_get_num_funcs(p_hwfn, p_ptt);
2708
0fefbfba
SK		 2709 if (qed_mcp_is_init(p_hwfn))
2710 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2711
9c8517c4 2712 return qed_hw_get_resc(p_hwfn, p_ptt);
fe56b9e6
YM		 2713}
2714
15582962 2715static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6 2716{
15582962 2717 struct qed_dev *cdev = p_hwfn->cdev;
9c79ddaa 2718 u16 device_id_mask;
fe56b9e6
YM		 2719 u32 tmp;
2720
fc48b7a6 2721 /* Read Vendor Id / Device Id */
1a635e48
YM		 2722 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2723 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2724
9c79ddaa
MY		 2725 /* Determine type */
2726 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2727 switch (device_id_mask) {
2728 case QED_DEV_ID_MASK_BB:
2729 cdev->type = QED_DEV_TYPE_BB;
2730 break;
2731 case QED_DEV_ID_MASK_AH:
2732 cdev->type = QED_DEV_TYPE_AH;
2733 break;
2734 default:
2735 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2736 return -EBUSY;
2737 }
2738
15582962
RV		 2739 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2740 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2741
fe56b9e6
YM		 2742 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2743
2744 /* Learn number of HW-functions */
15582962 2745 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
fe56b9e6 2746
fc48b7a6 2747 if (tmp & (1 << p_hwfn->rel_pf_id)) {
fe56b9e6
YM		 2748 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2749 cdev->num_hwfns = 2;
2750 } else {
2751 cdev->num_hwfns = 1;
2752 }
2753
15582962 2754 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
fe56b9e6
YM		 2755 MISCS_REG_CHIP_TEST_REG) >> 4;
2756 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
15582962 2757 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
fe56b9e6
YM		 2758 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2759
2760 DP_INFO(cdev->hwfns,
9c79ddaa
MY		 2761 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2762 QED_IS_BB(cdev) ? "BB" : "AH",
2763 'A' + cdev->chip_rev,
2764 (int)cdev->chip_metal,
fe56b9e6
YM		 2765 cdev->chip_num, cdev->chip_rev,
2766 cdev->chip_bond_id, cdev->chip_metal);
12e09c69
YM		 2767
2768 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
2769 DP_NOTICE(cdev->hwfns,
2770 "The chip type/rev (BB A0) is not supported!\n");
2771 return -EINVAL;
2772 }
2773
2774 return 0;
fe56b9e6
YM		 2775}
2776
2777static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2778 void __iomem *p_regview,
2779 void __iomem *p_doorbells,
2780 enum qed_pci_personality personality)
2781{
2782 int rc = 0;
2783
2784 /* Split PCI bars evenly between hwfns */
2785 p_hwfn->regview = p_regview;
2786 p_hwfn->doorbells = p_doorbells;
2787
1408cc1f
YM		 2788 if (IS_VF(p_hwfn->cdev))
2789 return qed_vf_hw_prepare(p_hwfn);
2790
fe56b9e6
YM		 2791 /* Validate that chip access is feasible */
2792 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2793 DP_ERR(p_hwfn,
2794 "Reading the ME register returns all Fs; Preventing further chip access\n");
2795 return -EINVAL;
2796 }
2797
2798 get_function_id(p_hwfn);
2799
12e09c69
YM		 2800 /* Allocate PTT pool */
2801 rc = qed_ptt_pool_alloc(p_hwfn);
2591c280 2802 if (rc)
fe56b9e6 2803 goto err0;
fe56b9e6 2804
12e09c69
YM		 2805 /* Allocate the main PTT */
2806 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2807
fe56b9e6 2808 /* First hwfn learns basic information, e.g., number of hwfns */
12e09c69 2809 if (!p_hwfn->my_id) {
15582962 2810 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
1a635e48 2811 if (rc)
12e09c69
YM		 2812 goto err1;
2813 }
2814
2815 qed_hw_hwfn_prepare(p_hwfn);
fe56b9e6
YM		 2816
2817 /* Initialize MCP structure */
2818 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2819 if (rc) {
2820 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2821 goto err1;
2822 }
2823
2824 /* Read the device configuration information from the HW and SHMEM */
2825 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2826 if (rc) {
2827 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2828 goto err2;
2829 }
2830
18a69e36
MY		 2831 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2832 * is called as it sets the ports number in an engine.
2833 */
2834 if (IS_LEAD_HWFN(p_hwfn)) {
2835 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2836 if (rc)
2837 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2838 }
2839
fe56b9e6
YM		 2840 /* Allocate the init RT array and initialize the init-ops engine */
2841 rc = qed_init_alloc(p_hwfn);
2591c280 2842 if (rc)
fe56b9e6 2843 goto err2;
fe56b9e6
YM		 2844
2845 return rc;
2846err2:
32a47e72
YM		 2847 if (IS_LEAD_HWFN(p_hwfn))
2848 qed_iov_free_hw_info(p_hwfn->cdev);
fe56b9e6
YM		 2849 qed_mcp_free(p_hwfn);
2850err1:
2851 qed_hw_hwfn_free(p_hwfn);
2852err0:
2853 return rc;
2854}
2855
fe56b9e6
YM		 2856int qed_hw_prepare(struct qed_dev *cdev,
2857 int personality)
2858{
c78df14e
AE		 2859 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2860 int rc;
fe56b9e6
YM		 2861
2862 /* Store the precompiled init data ptrs */
1408cc1f
YM		 2863 if (IS_PF(cdev))
2864 qed_init_iro_array(cdev);
fe56b9e6
YM		 2865
2866 /* Initialize the first hwfn - will learn number of hwfns */
c78df14e
AE		 2867 rc = qed_hw_prepare_single(p_hwfn,
2868 cdev->regview,
fe56b9e6
YM		 2869 cdev->doorbells, personality);
2870 if (rc)
2871 return rc;
2872
c78df14e 2873 personality = p_hwfn->hw_info.personality;
fe56b9e6
YM		 2874
2875 /* Initialize the rest of the hwfns */
c78df14e 2876 if (cdev->num_hwfns > 1) {
fe56b9e6 2877 void __iomem *p_regview, *p_doorbell;
c78df14e
AE		 2878 u8 __iomem *addr;
2879
2880 /* adjust bar offset for second engine */
15582962
RV		 2881 addr = cdev->regview +
2882 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2883 BAR_ID_0) / 2;
c78df14e 2884 p_regview = addr;
fe56b9e6 2885
15582962
RV		 2886 addr = cdev->doorbells +
2887 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2888 BAR_ID_1) / 2;
c78df14e
AE		 2889 p_doorbell = addr;
2890
2891 /* prepare second hw function */
2892 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
fe56b9e6 2893 p_doorbell, personality);
c78df14e
AE		 2894
2895 /* in case of error, need to free the previously
2896 * initiliazed hwfn 0.
2897 */
fe56b9e6 2898 if (rc) {
1408cc1f
YM		 2899 if (IS_PF(cdev)) {
2900 qed_init_free(p_hwfn);
2901 qed_mcp_free(p_hwfn);
2902 qed_hw_hwfn_free(p_hwfn);
2903 }
fe56b9e6
YM		 2904 }
2905 }
2906
c78df14e 2907 return rc;
fe56b9e6
YM		 2908}
2909
2910void qed_hw_remove(struct qed_dev *cdev)
2911{
0fefbfba 2912 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 2913 int i;
2914
0fefbfba
SK		 2915 if (IS_PF(cdev))
2916 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2917 QED_OV_DRIVER_STATE_NOT_LOADED);
2918
fe56b9e6
YM		 2919 for_each_hwfn(cdev, i) {
2920 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2921
1408cc1f 2922 if (IS_VF(cdev)) {
0b55e27d 2923 qed_vf_pf_release(p_hwfn);
1408cc1f
YM		 2924 continue;
2925 }
2926
fe56b9e6
YM		 2927 qed_init_free(p_hwfn);
2928 qed_hw_hwfn_free(p_hwfn);
2929 qed_mcp_free(p_hwfn);
2930 }
32a47e72
YM		 2931
2932 qed_iov_free_hw_info(cdev);
fe56b9e6
YM		 2933}
2934
a91eb52a
YM		 2935static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2936 struct qed_chain *p_chain)
2937{
2938 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2939 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2940 struct qed_chain_next *p_next;
2941 u32 size, i;
2942
2943 if (!p_virt)
2944 return;
2945
2946 size = p_chain->elem_size * p_chain->usable_per_page;
2947
2948 for (i = 0; i < p_chain->page_cnt; i++) {
2949 if (!p_virt)
2950 break;
2951
2952 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2953 p_virt_next = p_next->next_virt;
2954 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2955
2956 dma_free_coherent(&cdev->pdev->dev,
2957 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2958
2959 p_virt = p_virt_next;
2960 p_phys = p_phys_next;
2961 }
2962}
2963
2964static void qed_chain_free_single(struct qed_dev *cdev,
2965 struct qed_chain *p_chain)
2966{
2967 if (!p_chain->p_virt_addr)
2968 return;
2969
2970 dma_free_coherent(&cdev->pdev->dev,
2971 QED_CHAIN_PAGE_SIZE,
2972 p_chain->p_virt_addr, p_chain->p_phys_addr);
2973}
2974
2975static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2976{
2977 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2978 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
6d937acf 2979 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
a91eb52a
YM		 2980
2981 if (!pp_virt_addr_tbl)
2982 return;
2983
6d937acf 2984 if (!p_pbl_virt)
a91eb52a
YM		 2985 goto out;
2986
2987 for (i = 0; i < page_cnt; i++) {
2988 if (!pp_virt_addr_tbl[i])
2989 break;
2990
2991 dma_free_coherent(&cdev->pdev->dev,
2992 QED_CHAIN_PAGE_SIZE,
2993 pp_virt_addr_tbl[i],
2994 *(dma_addr_t *)p_pbl_virt);
2995
2996 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2997 }
2998
2999 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3000 dma_free_coherent(&cdev->pdev->dev,
3001 pbl_size,
6d937acf
MY		 3002 p_chain->pbl_sp.p_virt_table,
3003 p_chain->pbl_sp.p_phys_table);
a91eb52a
YM		 3004out:
3005 vfree(p_chain->pbl.pp_virt_addr_tbl);
3006}
3007
3008void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3009{
3010 switch (p_chain->mode) {
3011 case QED_CHAIN_MODE_NEXT_PTR:
3012 qed_chain_free_next_ptr(cdev, p_chain);
3013 break;
3014 case QED_CHAIN_MODE_SINGLE:
3015 qed_chain_free_single(cdev, p_chain);
3016 break;
3017 case QED_CHAIN_MODE_PBL:
3018 qed_chain_free_pbl(cdev, p_chain);
3019 break;
3020 }
3021}
3022
3023static int
3024qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3025 enum qed_chain_cnt_type cnt_type,
3026 size_t elem_size, u32 page_cnt)
fe56b9e6 3027{
a91eb52a
YM		 3028 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3029
3030 /* The actual chain size can be larger than the maximal possible value
3031 * after rounding up the requested elements number to pages, and after
3032 * taking into acount the unusuable elements (next-ptr elements).
3033 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3034 * size/capacity fields are of a u32 type.
3035 */
3036 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3ef310a7
TT		 3037 chain_size > ((u32)U16_MAX + 1)) ||
3038 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
a91eb52a
YM		 3039 DP_NOTICE(cdev,
3040 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3041 chain_size);
3042 return -EINVAL;
3043 }
3044
3045 return 0;
3046}
3047
3048static int
3049qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3050{
3051 void *p_virt = NULL, *p_virt_prev = NULL;
fe56b9e6 3052 dma_addr_t p_phys = 0;
a91eb52a 3053 u32 i;
fe56b9e6 3054
a91eb52a
YM		 3055 for (i = 0; i < p_chain->page_cnt; i++) {
3056 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3057 QED_CHAIN_PAGE_SIZE,
3058 &p_phys, GFP_KERNEL);
2591c280 3059 if (!p_virt)
a91eb52a 3060 return -ENOMEM;
a91eb52a
YM		 3061
3062 if (i == 0) {
3063 qed_chain_init_mem(p_chain, p_virt, p_phys);
3064 qed_chain_reset(p_chain);
3065 } else {
3066 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3067 p_virt, p_phys);
3068 }
3069
3070 p_virt_prev = p_virt;
3071 }
3072 /* Last page's next element should point to the beginning of the
3073 * chain.
3074 */
3075 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3076 p_chain->p_virt_addr,
3077 p_chain->p_phys_addr);
3078
3079 return 0;
3080}
3081
3082static int
3083qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3084{
3085 dma_addr_t p_phys = 0;
3086 void *p_virt = NULL;
fe56b9e6 3087
fe56b9e6 3088 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
a91eb52a 3089 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2591c280 3090 if (!p_virt)
a91eb52a 3091 return -ENOMEM;
fe56b9e6 3092
a91eb52a
YM		 3093 qed_chain_init_mem(p_chain, p_virt, p_phys);
3094 qed_chain_reset(p_chain);
fe56b9e6 3095
a91eb52a
YM		 3096 return 0;
3097}
3098
3099static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3100{
3101 u32 page_cnt = p_chain->page_cnt, size, i;
3102 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3103 void **pp_virt_addr_tbl = NULL;
3104 u8 *p_pbl_virt = NULL;
3105 void *p_virt = NULL;
3106
3107 size = page_cnt * sizeof(*pp_virt_addr_tbl);
2591c280
JP		 3108 pp_virt_addr_tbl = vzalloc(size);
3109 if (!pp_virt_addr_tbl)
a91eb52a 3110 return -ENOMEM;
fe56b9e6 3111
a91eb52a
YM		 3112 /* The allocation of the PBL table is done with its full size, since it
3113 * is expected to be successive.
3114 * qed_chain_init_pbl_mem() is called even in a case of an allocation
3115 * failure, since pp_virt_addr_tbl was previously allocated, and it
3116 * should be saved to allow its freeing during the error flow.
3117 */
3118 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3119 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3120 size, &p_pbl_phys, GFP_KERNEL);
3121 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3122 pp_virt_addr_tbl);
2591c280 3123 if (!p_pbl_virt)
a91eb52a 3124 return -ENOMEM;
fe56b9e6 3125
a91eb52a
YM		 3126 for (i = 0; i < page_cnt; i++) {
3127 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3128 QED_CHAIN_PAGE_SIZE,
3129 &p_phys, GFP_KERNEL);
2591c280 3130 if (!p_virt)
a91eb52a 3131 return -ENOMEM;
fe56b9e6 3132
a91eb52a
YM		 3133 if (i == 0) {
3134 qed_chain_init_mem(p_chain, p_virt, p_phys);
3135 qed_chain_reset(p_chain);
3136 }
3137
3138 /* Fill the PBL table with the physical address of the page */
3139 *(dma_addr_t *)p_pbl_virt = p_phys;
3140 /* Keep the virtual address of the page */
3141 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3142
3143 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3144 }
3145
3146 return 0;
fe56b9e6
YM		 3147}
3148
a91eb52a
YM		 3149int qed_chain_alloc(struct qed_dev *cdev,
3150 enum qed_chain_use_mode intended_use,
3151 enum qed_chain_mode mode,
3152 enum qed_chain_cnt_type cnt_type,
3153 u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
fe56b9e6 3154{
a91eb52a
YM		 3155 u32 page_cnt;
3156 int rc = 0;
fe56b9e6 3157
a91eb52a
YM		 3158 if (mode == QED_CHAIN_MODE_SINGLE)
3159 page_cnt = 1;
3160 else
3161 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
fe56b9e6 3162
a91eb52a
YM		 3163 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3164 if (rc) {
3165 DP_NOTICE(cdev,
2591c280
JP		 3166 "Cannot allocate a chain with the given arguments:\n");
3167 DP_NOTICE(cdev,
a91eb52a
YM		 3168 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3169 intended_use, mode, cnt_type, num_elems, elem_size);
3170 return rc;
fe56b9e6
YM		 3171 }
3172
a91eb52a
YM		 3173 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3174 mode, cnt_type);
3175
3176 switch (mode) {
3177 case QED_CHAIN_MODE_NEXT_PTR:
3178 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3179 break;
3180 case QED_CHAIN_MODE_SINGLE:
3181 rc = qed_chain_alloc_single(cdev, p_chain);
3182 break;
3183 case QED_CHAIN_MODE_PBL:
3184 rc = qed_chain_alloc_pbl(cdev, p_chain);
3185 break;
3186 }
3187 if (rc)
3188 goto nomem;
3189
3190 return 0;
3191
3192nomem:
3193 qed_chain_free(cdev, p_chain);
3194 return rc;
fe56b9e6 3195}
cee4d264 3196
a91eb52a 3197int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
cee4d264
MC		 3198{
3199 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3200 u16 min, max;
3201
a91eb52a 3202 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
cee4d264
MC		 3203 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3204 DP_NOTICE(p_hwfn,
3205 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3206 src_id, min, max);
3207
3208 return -EINVAL;
3209 }
3210
3211 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3212
3213 return 0;
3214}
3215
1a635e48 3216int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 3217{
3218 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3219 u8 min, max;
3220
3221 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3222 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3223 DP_NOTICE(p_hwfn,
3224 "vport id [%d] is not valid, available indices [%d - %d]\n",
3225 src_id, min, max);
3226
3227 return -EINVAL;
3228 }
3229
3230 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3231
3232 return 0;
3233}
3234
1a635e48 3235int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 3236{
3237 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3238 u8 min, max;
3239
3240 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3241 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3242 DP_NOTICE(p_hwfn,
3243 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3244 src_id, min, max);
3245
3246 return -EINVAL;
3247 }
3248
3249 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3250
3251 return 0;
3252}
bcd197c8 3253
0a7fb11c
YM		 3254static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3255 u8 *p_filter)
3256{
3257 *p_high = p_filter[1] | (p_filter[0] << 8);
3258 *p_low = p_filter[5] | (p_filter[4] << 8) |
3259 (p_filter[3] << 16) | (p_filter[2] << 24);
3260}
3261
3262int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3263 struct qed_ptt *p_ptt, u8 *p_filter)
3264{
3265 u32 high = 0, low = 0, en;
3266 int i;
3267
3268 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3269 return 0;
3270
3271 qed_llh_mac_to_filter(&high, &low, p_filter);
3272
3273 /* Find a free entry and utilize it */
3274 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3275 en = qed_rd(p_hwfn, p_ptt,
3276 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3277 if (en)
3278 continue;
3279 qed_wr(p_hwfn, p_ptt,
3280 NIG_REG_LLH_FUNC_FILTER_VALUE +
3281 2 * i * sizeof(u32), low);
3282 qed_wr(p_hwfn, p_ptt,
3283 NIG_REG_LLH_FUNC_FILTER_VALUE +
3284 (2 * i + 1) * sizeof(u32), high);
3285 qed_wr(p_hwfn, p_ptt,
3286 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3287 qed_wr(p_hwfn, p_ptt,
3288 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3289 i * sizeof(u32), 0);
3290 qed_wr(p_hwfn, p_ptt,
3291 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3292 break;
3293 }
3294 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3295 DP_NOTICE(p_hwfn,
3296 "Failed to find an empty LLH filter to utilize\n");
3297 return -EINVAL;
3298 }
3299
3300 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3301 "mac: %pM is added at %d\n",
3302 p_filter, i);
3303
3304 return 0;
3305}
3306
3307void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3308 struct qed_ptt *p_ptt, u8 *p_filter)
3309{
3310 u32 high = 0, low = 0;
3311 int i;
3312
3313 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3314 return;
3315
3316 qed_llh_mac_to_filter(&high, &low, p_filter);
3317
3318 /* Find the entry and clean it */
3319 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3320 if (qed_rd(p_hwfn, p_ptt,
3321 NIG_REG_LLH_FUNC_FILTER_VALUE +
3322 2 * i * sizeof(u32)) != low)
3323 continue;
3324 if (qed_rd(p_hwfn, p_ptt,
3325 NIG_REG_LLH_FUNC_FILTER_VALUE +
3326 (2 * i + 1) * sizeof(u32)) != high)
3327 continue;
3328
3329 qed_wr(p_hwfn, p_ptt,
3330 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3331 qed_wr(p_hwfn, p_ptt,
3332 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3333 qed_wr(p_hwfn, p_ptt,
3334 NIG_REG_LLH_FUNC_FILTER_VALUE +
3335 (2 * i + 1) * sizeof(u32), 0);
3336
3337 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3338 "mac: %pM is removed from %d\n",
3339 p_filter, i);
3340 break;
3341 }
3342 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3343 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3344}
3345
1e128c81
AE		 3346int
3347qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3348 struct qed_ptt *p_ptt,
3349 u16 source_port_or_eth_type,
3350 u16 dest_port, enum qed_llh_port_filter_type_t type)
3351{
3352 u32 high = 0, low = 0, en;
3353 int i;
3354
3355 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3356 return 0;
3357
3358 switch (type) {
3359 case QED_LLH_FILTER_ETHERTYPE:
3360 high = source_port_or_eth_type;
3361 break;
3362 case QED_LLH_FILTER_TCP_SRC_PORT:
3363 case QED_LLH_FILTER_UDP_SRC_PORT:
3364 low = source_port_or_eth_type << 16;
3365 break;
3366 case QED_LLH_FILTER_TCP_DEST_PORT:
3367 case QED_LLH_FILTER_UDP_DEST_PORT:
3368 low = dest_port;
3369 break;
3370 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3371 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3372 low = (source_port_or_eth_type << 16) | dest_port;
3373 break;
3374 default:
3375 DP_NOTICE(p_hwfn,
3376 "Non valid LLH protocol filter type %d\n", type);
3377 return -EINVAL;
3378 }
3379 /* Find a free entry and utilize it */
3380 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3381 en = qed_rd(p_hwfn, p_ptt,
3382 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3383 if (en)
3384 continue;
3385 qed_wr(p_hwfn, p_ptt,
3386 NIG_REG_LLH_FUNC_FILTER_VALUE +
3387 2 * i * sizeof(u32), low);
3388 qed_wr(p_hwfn, p_ptt,
3389 NIG_REG_LLH_FUNC_FILTER_VALUE +
3390 (2 * i + 1) * sizeof(u32), high);
3391 qed_wr(p_hwfn, p_ptt,
3392 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3393 qed_wr(p_hwfn, p_ptt,
3394 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3395 i * sizeof(u32), 1 << type);
3396 qed_wr(p_hwfn, p_ptt,
3397 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3398 break;
3399 }
3400 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3401 DP_NOTICE(p_hwfn,
3402 "Failed to find an empty LLH filter to utilize\n");
3403 return -EINVAL;
3404 }
3405 switch (type) {
3406 case QED_LLH_FILTER_ETHERTYPE:
3407 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3408 "ETH type %x is added at %d\n",
3409 source_port_or_eth_type, i);
3410 break;
3411 case QED_LLH_FILTER_TCP_SRC_PORT:
3412 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3413 "TCP src port %x is added at %d\n",
3414 source_port_or_eth_type, i);
3415 break;
3416 case QED_LLH_FILTER_UDP_SRC_PORT:
3417 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3418 "UDP src port %x is added at %d\n",
3419 source_port_or_eth_type, i);
3420 break;
3421 case QED_LLH_FILTER_TCP_DEST_PORT:
3422 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3423 "TCP dst port %x is added at %d\n", dest_port, i);
3424 break;
3425 case QED_LLH_FILTER_UDP_DEST_PORT:
3426 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3427 "UDP dst port %x is added at %d\n", dest_port, i);
3428 break;
3429 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3430 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3431 "TCP src/dst ports %x/%x are added at %d\n",
3432 source_port_or_eth_type, dest_port, i);
3433 break;
3434 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3435 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3436 "UDP src/dst ports %x/%x are added at %d\n",
3437 source_port_or_eth_type, dest_port, i);
3438 break;
3439 }
3440 return 0;
3441}
3442
3443void
3444qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3445 struct qed_ptt *p_ptt,
3446 u16 source_port_or_eth_type,
3447 u16 dest_port,
3448 enum qed_llh_port_filter_type_t type)
3449{
3450 u32 high = 0, low = 0;
3451 int i;
3452
3453 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3454 return;
3455
3456 switch (type) {
3457 case QED_LLH_FILTER_ETHERTYPE:
3458 high = source_port_or_eth_type;
3459 break;
3460 case QED_LLH_FILTER_TCP_SRC_PORT:
3461 case QED_LLH_FILTER_UDP_SRC_PORT:
3462 low = source_port_or_eth_type << 16;
3463 break;
3464 case QED_LLH_FILTER_TCP_DEST_PORT:
3465 case QED_LLH_FILTER_UDP_DEST_PORT:
3466 low = dest_port;
3467 break;
3468 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3469 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3470 low = (source_port_or_eth_type << 16) | dest_port;
3471 break;
3472 default:
3473 DP_NOTICE(p_hwfn,
3474 "Non valid LLH protocol filter type %d\n", type);
3475 return;
3476 }
3477
3478 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3479 if (!qed_rd(p_hwfn, p_ptt,
3480 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3481 continue;
3482 if (!qed_rd(p_hwfn, p_ptt,
3483 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3484 continue;
3485 if (!(qed_rd(p_hwfn, p_ptt,
3486 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3487 i * sizeof(u32)) & BIT(type)))
3488 continue;
3489 if (qed_rd(p_hwfn, p_ptt,
3490 NIG_REG_LLH_FUNC_FILTER_VALUE +
3491 2 * i * sizeof(u32)) != low)
3492 continue;
3493 if (qed_rd(p_hwfn, p_ptt,
3494 NIG_REG_LLH_FUNC_FILTER_VALUE +
3495 (2 * i + 1) * sizeof(u32)) != high)
3496 continue;
3497
3498 qed_wr(p_hwfn, p_ptt,
3499 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3500 qed_wr(p_hwfn, p_ptt,
3501 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3502 qed_wr(p_hwfn, p_ptt,
3503 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3504 i * sizeof(u32), 0);
3505 qed_wr(p_hwfn, p_ptt,
3506 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3507 qed_wr(p_hwfn, p_ptt,
3508 NIG_REG_LLH_FUNC_FILTER_VALUE +
3509 (2 * i + 1) * sizeof(u32), 0);
3510 break;
3511 }
3512
3513 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3514 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3515}
3516
722003ac
SRK		 3517static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3518 u32 hw_addr, void *p_eth_qzone,
3519 size_t eth_qzone_size, u8 timeset)
3520{
3521 struct coalescing_timeset *p_coal_timeset;
3522
3523 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3524 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3525 return -EINVAL;
3526 }
3527
3528 p_coal_timeset = p_eth_qzone;
3529 memset(p_coal_timeset, 0, eth_qzone_size);
3530 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3531 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3532 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3533
3534 return 0;
3535}
3536
3537int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3538 u16 coalesce, u8 qid, u16 sb_id)
3539{
3540 struct ustorm_eth_queue_zone eth_qzone;
3541 u8 timeset, timer_res;
3542 u16 fw_qid = 0;
3543 u32 address;
3544 int rc;
3545
3546 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3547 if (coalesce <= 0x7F) {
3548 timer_res = 0;
3549 } else if (coalesce <= 0xFF) {
3550 timer_res = 1;
3551 } else if (coalesce <= 0x1FF) {
3552 timer_res = 2;
3553 } else {
3554 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3555 return -EINVAL;
3556 }
3557 timeset = (u8)(coalesce >> timer_res);
3558
3559 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3560 if (rc)
3561 return rc;
3562
3563 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3564 if (rc)
3565 goto out;
3566
3567 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3568
3569 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3570 sizeof(struct ustorm_eth_queue_zone), timeset);
3571 if (rc)
3572 goto out;
3573
3574 p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3575out:
3576 return rc;
3577}
3578
3579int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3580 u16 coalesce, u8 qid, u16 sb_id)
3581{
3582 struct xstorm_eth_queue_zone eth_qzone;
3583 u8 timeset, timer_res;
3584 u16 fw_qid = 0;
3585 u32 address;
3586 int rc;
3587
3588 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3589 if (coalesce <= 0x7F) {
3590 timer_res = 0;
3591 } else if (coalesce <= 0xFF) {
3592 timer_res = 1;
3593 } else if (coalesce <= 0x1FF) {
3594 timer_res = 2;
3595 } else {
3596 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3597 return -EINVAL;
3598 }
3599 timeset = (u8)(coalesce >> timer_res);
3600
3601 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3602 if (rc)
3603 return rc;
3604
3605 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3606 if (rc)
3607 goto out;
3608
3609 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3610
3611 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3612 sizeof(struct xstorm_eth_queue_zone), timeset);
3613 if (rc)
3614 goto out;
3615
3616 p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3617out:
3618 return rc;
3619}
3620
bcd197c8
MC		 3621/* Calculate final WFQ values for all vports and configure them.
3622 * After this configuration each vport will have
3623 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3624 */
3625static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3626 struct qed_ptt *p_ptt,
3627 u32 min_pf_rate)
3628{
3629 struct init_qm_vport_params *vport_params;
3630 int i;
3631
3632 vport_params = p_hwfn->qm_info.qm_vport_params;
3633
3634 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3635 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3636
3637 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3638 min_pf_rate;
3639 qed_init_vport_wfq(p_hwfn, p_ptt,
3640 vport_params[i].first_tx_pq_id,
3641 vport_params[i].vport_wfq);
3642 }
3643}
3644
3645static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3646 u32 min_pf_rate)
3647
3648{
3649 int i;
3650
3651 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3652 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3653}
3654
3655static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3656 struct qed_ptt *p_ptt,
3657 u32 min_pf_rate)
3658{
3659 struct init_qm_vport_params *vport_params;
3660 int i;
3661
3662 vport_params = p_hwfn->qm_info.qm_vport_params;
3663
3664 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3665 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3666 qed_init_vport_wfq(p_hwfn, p_ptt,
3667 vport_params[i].first_tx_pq_id,
3668 vport_params[i].vport_wfq);
3669 }
3670}
3671
3672/* This function performs several validations for WFQ
3673 * configuration and required min rate for a given vport
3674 * 1. req_rate must be greater than one percent of min_pf_rate.
3675 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3676 * rates to get less than one percent of min_pf_rate.
3677 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3678 */
3679static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1a635e48 3680 u16 vport_id, u32 req_rate, u32 min_pf_rate)
bcd197c8
MC		 3681{
3682 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3683 int non_requested_count = 0, req_count = 0, i, num_vports;
3684
3685 num_vports = p_hwfn->qm_info.num_vports;
3686
3687 /* Accounting for the vports which are configured for WFQ explicitly */
3688 for (i = 0; i < num_vports; i++) {
3689 u32 tmp_speed;
3690
3691 if ((i != vport_id) &&
3692 p_hwfn->qm_info.wfq_data[i].configured) {
3693 req_count++;
3694 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3695 total_req_min_rate += tmp_speed;
3696 }
3697 }
3698
3699 /* Include current vport data as well */
3700 req_count++;
3701 total_req_min_rate += req_rate;
3702 non_requested_count = num_vports - req_count;
3703
3704 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3705 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3706 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3707 vport_id, req_rate, min_pf_rate);
3708 return -EINVAL;
3709 }
3710
3711 if (num_vports > QED_WFQ_UNIT) {
3712 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3713 "Number of vports is greater than %d\n",
3714 QED_WFQ_UNIT);
3715 return -EINVAL;
3716 }
3717
3718 if (total_req_min_rate > min_pf_rate) {
3719 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3720 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3721 total_req_min_rate, min_pf_rate);
3722 return -EINVAL;
3723 }
3724
3725 total_left_rate = min_pf_rate - total_req_min_rate;
3726
3727 left_rate_per_vp = total_left_rate / non_requested_count;
3728 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
3729 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3730 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3731 left_rate_per_vp, min_pf_rate);
3732 return -EINVAL;
3733 }
3734
3735 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3736 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3737
3738 for (i = 0; i < num_vports; i++) {
3739 if (p_hwfn->qm_info.wfq_data[i].configured)
3740 continue;
3741
3742 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3743 }
3744
3745 return 0;
3746}
3747
733def6a
YM		 3748static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3749 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3750{
3751 struct qed_mcp_link_state *p_link;
3752 int rc = 0;
3753
3754 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3755
3756 if (!p_link->min_pf_rate) {
3757 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3758 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3759 return rc;
3760 }
3761
3762 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3763
1a635e48 3764 if (!rc)
733def6a
YM		 3765 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3766 p_link->min_pf_rate);
3767 else
3768 DP_NOTICE(p_hwfn,
3769 "Validation failed while configuring min rate\n");
3770
3771 return rc;
3772}
3773
bcd197c8
MC		 3774static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3775 struct qed_ptt *p_ptt,
3776 u32 min_pf_rate)
3777{
3778 bool use_wfq = false;
3779 int rc = 0;
3780 u16 i;
3781
3782 /* Validate all pre configured vports for wfq */
3783 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3784 u32 rate;
3785
3786 if (!p_hwfn->qm_info.wfq_data[i].configured)
3787 continue;
3788
3789 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3790 use_wfq = true;
3791
3792 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3793 if (rc) {
3794 DP_NOTICE(p_hwfn,
3795 "WFQ validation failed while configuring min rate\n");
3796 break;
3797 }
3798 }
3799
3800 if (!rc && use_wfq)
3801 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3802 else
3803 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3804
3805 return rc;
3806}
3807
733def6a
YM		 3808/* Main API for qed clients to configure vport min rate.
3809 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3810 * rate - Speed in Mbps needs to be assigned to a given vport.
3811 */
3812int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3813{
3814 int i, rc = -EINVAL;
3815
3816 /* Currently not supported; Might change in future */
3817 if (cdev->num_hwfns > 1) {
3818 DP_NOTICE(cdev,
3819 "WFQ configuration is not supported for this device\n");
3820 return rc;
3821 }
3822
3823 for_each_hwfn(cdev, i) {
3824 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3825 struct qed_ptt *p_ptt;
3826
3827 p_ptt = qed_ptt_acquire(p_hwfn);
3828 if (!p_ptt)
3829 return -EBUSY;
3830
3831 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3832
d572c430 3833 if (rc) {
733def6a
YM		 3834 qed_ptt_release(p_hwfn, p_ptt);
3835 return rc;
3836 }
3837
3838 qed_ptt_release(p_hwfn, p_ptt);
3839 }
3840
3841 return rc;
3842}
3843
bcd197c8 3844/* API to configure WFQ from mcp link change */
6f437d43
MY		 3845void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3846 struct qed_ptt *p_ptt, u32 min_pf_rate)
bcd197c8
MC		 3847{
3848 int i;
3849
3e7cfce2
YM		 3850 if (cdev->num_hwfns > 1) {
3851 DP_VERBOSE(cdev,
3852 NETIF_MSG_LINK,
3853 "WFQ configuration is not supported for this device\n");
3854 return;
3855 }
3856
bcd197c8
MC		 3857 for_each_hwfn(cdev, i) {
3858 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3859
6f437d43 3860 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
bcd197c8
MC		 3861 min_pf_rate);
3862 }
3863}
4b01e519
MC		 3864
3865int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3866 struct qed_ptt *p_ptt,
3867 struct qed_mcp_link_state *p_link,
3868 u8 max_bw)
3869{
3870 int rc = 0;
3871
3872 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3873
3874 if (!p_link->line_speed && (max_bw != 100))
3875 return rc;
3876
3877 p_link->speed = (p_link->line_speed * max_bw) / 100;
3878 p_hwfn->qm_info.pf_rl = p_link->speed;
3879
3880 /* Since the limiter also affects Tx-switched traffic, we don't want it
3881 * to limit such traffic in case there's no actual limit.
3882 * In that case, set limit to imaginary high boundary.
3883 */
3884 if (max_bw == 100)
3885 p_hwfn->qm_info.pf_rl = 100000;
3886
3887 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3888 p_hwfn->qm_info.pf_rl);
3889
3890 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3891 "Configured MAX bandwidth to be %08x Mb/sec\n",
3892 p_link->speed);
3893
3894 return rc;
3895}
3896
3897/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3898int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3899{
3900 int i, rc = -EINVAL;
3901
3902 if (max_bw < 1 || max_bw > 100) {
3903 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3904 return rc;
3905 }
3906
3907 for_each_hwfn(cdev, i) {
3908 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3909 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3910 struct qed_mcp_link_state *p_link;
3911 struct qed_ptt *p_ptt;
3912
3913 p_link = &p_lead->mcp_info->link_output;
3914
3915 p_ptt = qed_ptt_acquire(p_hwfn);
3916 if (!p_ptt)
3917 return -EBUSY;
3918
3919 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3920 p_link, max_bw);
3921
3922 qed_ptt_release(p_hwfn, p_ptt);
3923
3924 if (rc)
3925 break;
3926 }
3927
3928 return rc;
3929}
a64b02d5
MC		 3930
3931int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3932 struct qed_ptt *p_ptt,
3933 struct qed_mcp_link_state *p_link,
3934 u8 min_bw)
3935{
3936 int rc = 0;
3937
3938 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3939 p_hwfn->qm_info.pf_wfq = min_bw;
3940
3941 if (!p_link->line_speed)
3942 return rc;
3943
3944 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3945
3946 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3947
3948 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3949 "Configured MIN bandwidth to be %d Mb/sec\n",
3950 p_link->min_pf_rate);
3951
3952 return rc;
3953}
3954
3955/* Main API to configure PF min bandwidth where bw range is [1-100] */
3956int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
3957{
3958 int i, rc = -EINVAL;
3959
3960 if (min_bw < 1 || min_bw > 100) {
3961 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
3962 return rc;
3963 }
3964
3965 for_each_hwfn(cdev, i) {
3966 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3967 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3968 struct qed_mcp_link_state *p_link;
3969 struct qed_ptt *p_ptt;
3970
3971 p_link = &p_lead->mcp_info->link_output;
3972
3973 p_ptt = qed_ptt_acquire(p_hwfn);
3974 if (!p_ptt)
3975 return -EBUSY;
3976
3977 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3978 p_link, min_bw);
3979 if (rc) {
3980 qed_ptt_release(p_hwfn, p_ptt);
3981 return rc;
3982 }
3983
3984 if (p_link->min_pf_rate) {
3985 u32 min_rate = p_link->min_pf_rate;
3986
3987 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
3988 p_ptt,
3989 min_rate);
3990 }
3991
3992 qed_ptt_release(p_hwfn, p_ptt);
3993 }
3994
3995 return rc;
3996}
733def6a
YM		 3997
3998void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3999{
4000 struct qed_mcp_link_state *p_link;
4001
4002 p_link = &p_hwfn->mcp_info->link_output;
4003
4004 if (p_link->min_pf_rate)
4005 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4006 p_link->min_pf_rate);
4007
4008 memset(p_hwfn->qm_info.wfq_data, 0,
4009 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4010}
9c79ddaa
MY		 4011
4012int qed_device_num_engines(struct qed_dev *cdev)
4013{
4014 return QED_IS_BB(cdev) ? 2 : 1;
4015}
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